if_em.h revision 152276 
1/**************************************************************************
2
3Copyright (c) 2001-2005, Intel Corporation
4All rights reserved.
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7modification, are permitted provided that the following conditions are met:
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10    this list of conditions and the following disclaimer.
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12 2. Redistributions in binary form must reproduce the above copyright
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14    documentation and/or other materials provided with the distribution.
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16 3. Neither the name of the Intel Corporation nor the names of its
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19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31
32***************************************************************************/
33
34/*$FreeBSD: head/sys/dev/em/if_em.h 152276 2005-11-10 11:44:37Z glebius $*/
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/mbuf.h>
46#include <sys/malloc.h>
47#include <sys/module.h>
48#include <sys/socket.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
51
52#include <machine/bus.h>
53#include <sys/rman.h>
54#include <machine/resource.h>
55
56#include <net/bpf.h>
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_media.h>
62
63#include <net/if_types.h>
64#include <net/if_vlan_var.h>
65
66#include <netinet/in_systm.h>
67#include <netinet/in.h>
68#include <netinet/ip.h>
69#include <netinet/tcp.h>
70#include <netinet/udp.h>
71
72#include <dev/pci/pcivar.h>
73#include <dev/pci/pcireg.h>
74
75#include <dev/em/if_em_hw.h>
76
77/* Tunables */
78
79/*
80 * EM_TXD: Maximum number of Transmit Descriptors
81 * Valid Range: 80-256 for 82542 and 82543-based adapters
82 *              80-4096 for others
83 * Default Value: 256
84 *   This value is the number of transmit descriptors allocated by the driver.
85 *   Increasing this value allows the driver to queue more transmits. Each
86 *   descriptor is 16 bytes.
87 */
88#define EM_TXD		256
89#define EM_TXD_82544	4096
90
91/*
92 * EM_RXD - Maximum number of receive Descriptors
93 * Valid Range: 80-256 for 82542 and 82543-based adapters
94 *              80-4096 for others
95 * Default Value: 256
96 *   This value is the number of receive descriptors allocated by the driver.
97 *   Increasing this value allows the driver to buffer more incoming packets.
98 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
99 *   descriptor. The maximum MTU size is 16110.
100 *
101 */
102#define EM_RXD		256
103#define EM_RXD_82544	4096
104
105/*
106 * EM_TIDV - Transmit Interrupt Delay Value
107 * Valid Range: 0-65535 (0=off)
108 * Default Value: 64
109 *   This value delays the generation of transmit interrupts in units of
110 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
111 *   efficiency if properly tuned for specific network traffic. If the
112 *   system is reporting dropped transmits, this value may be set too high
113 *   causing the driver to run out of available transmit descriptors.
114 */
115#define EM_TIDV                         64
116
117/*
118 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
119 * Valid Range: 0-65535 (0=off)
120 * Default Value: 64
121 *   This value, in units of 1.024 microseconds, limits the delay in which a
122 *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
123 *   this value ensures that an interrupt is generated after the initial
124 *   packet is sent on the wire within the set amount of time.  Proper tuning,
125 *   along with EM_TIDV, may improve traffic throughput in specific
126 *   network conditions.
127 */
128#define EM_TADV                         64
129
130/*
131 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
132 * Valid Range: 0-65535 (0=off)
133 * Default Value: 0
134 *   This value delays the generation of receive interrupts in units of 1.024
135 *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
136 *   properly tuned for specific network traffic. Increasing this value adds
137 *   extra latency to frame reception and can end up decreasing the throughput
138 *   of TCP traffic. If the system is reporting dropped receives, this value
139 *   may be set too high, causing the driver to run out of available receive
140 *   descriptors.
141 *
142 *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
143 *            may hang (stop transmitting) under certain network conditions.
144 *            If this occurs a WATCHDOG message is logged in the system event log.
145 *            In addition, the controller is automatically reset, restoring the
146 *            network connection. To eliminate the potential for the hang
147 *            ensure that EM_RDTR is set to 0.
148 */
149#define EM_RDTR                         0
150
151/*
152 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
153 * Valid Range: 0-65535 (0=off)
154 * Default Value: 64
155 *   This value, in units of 1.024 microseconds, limits the delay in which a
156 *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
157 *   this value ensures that an interrupt is generated after the initial
158 *   packet is received within the set amount of time.  Proper tuning,
159 *   along with EM_RDTR, may improve traffic throughput in specific network
160 *   conditions.
161 */
162#define EM_RADV                         64
163
164/*
165 * Inform the stack about transmit checksum offload capabilities.
166 */
167#define EM_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
168
169/*
170 * This parameter controls the duration of transmit watchdog timer.
171 */
172#define EM_TX_TIMEOUT                   5    /* set to 5 seconds */
173
174/*
175 * This parameter controls when the driver calls the routine to reclaim
176 * transmit descriptors.
177 */
178#define EM_TX_CLEANUP_THRESHOLD		(adapter->num_tx_desc / 8)
179
180/*
181 * This parameter controls whether or not autonegotation is enabled.
182 *              0 - Disable autonegotiation
183 *              1 - Enable  autonegotiation
184 */
185#define DO_AUTO_NEG                     1
186
187/*
188 * This parameter control whether or not the driver will wait for
189 * autonegotiation to complete.
190 *              1 - Wait for autonegotiation to complete
191 *              0 - Don't wait for autonegotiation to complete
192 */
193#define WAIT_FOR_AUTO_NEG_DEFAULT       0
194
195/*
196 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
197 * with 82541/82547 devices and some switches.  See the "Known Limitations" section of
198 * the README file for a complete description and a list of affected switches.
199 *
200 *              0 = Hardware default
201 *              1 = Master mode
202 *              2 = Slave mode
203 *              3 = Auto master/slave
204 */
205/* #define EM_MASTER_SLAVE      2 */
206
207/* Tunables -- End */
208
209#define AUTONEG_ADV_DEFAULT             (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
210                                         ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
211                                         ADVERTISE_1000_FULL)
212
213#define EM_VENDOR_ID                    0x8086
214#define EM_MMBA                         0x0010 /* Mem base address */
215#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
216
217#define EM_JUMBO_PBA                    0x00000028
218#define EM_DEFAULT_PBA                  0x00000030
219#define EM_SMARTSPEED_DOWNSHIFT         3
220#define EM_SMARTSPEED_MAX               15
221
222
223#define MAX_NUM_MULTICAST_ADDRESSES     128
224#define PCI_ANY_ID                      (~0U)
225#define ETHER_ALIGN                     2
226
227/* Defines for printing debug information */
228#define DEBUG_INIT  0
229#define DEBUG_IOCTL 0
230#define DEBUG_HW    0
231
232#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
233#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
234#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
235#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
236#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
237#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
238#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
239#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
240#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
241
242
243/* Supported RX Buffer Sizes */
244#define EM_RXBUFFER_2048        2048
245#define EM_RXBUFFER_4096        4096
246#define EM_RXBUFFER_8192        8192
247#define EM_RXBUFFER_16384      16384
248
249#define EM_MAX_SCATTER            64
250
251/* ******************************************************************************
252 * vendor_info_array
253 *
254 * This array contains the list of Subvendor/Subdevice IDs on which the driver
255 * should load.
256 *
257 * ******************************************************************************/
258typedef struct _em_vendor_info_t {
259	unsigned int vendor_id;
260	unsigned int device_id;
261	unsigned int subvendor_id;
262	unsigned int subdevice_id;
263	unsigned int index;
264} em_vendor_info_t;
265
266
267struct em_buffer {
268        struct mbuf    *m_head;
269        bus_dmamap_t    map;         /* bus_dma map for packet */
270};
271
272/*
273 * Bus dma allocation structure used by
274 * em_dma_malloc and em_dma_free.
275 */
276struct em_dma_alloc {
277        bus_addr_t              dma_paddr;
278        caddr_t                 dma_vaddr;
279        bus_dma_tag_t           dma_tag;
280        bus_dmamap_t            dma_map;
281        bus_dma_segment_t       dma_seg;
282        int                     dma_nseg;
283};
284
285typedef enum _XSUM_CONTEXT_T {
286	OFFLOAD_NONE,
287	OFFLOAD_TCP_IP,
288	OFFLOAD_UDP_IP
289} XSUM_CONTEXT_T;
290
291struct adapter;
292struct em_int_delay_info {
293	struct adapter *adapter;	/* Back-pointer to the adapter struct */
294	int offset;			/* Register offset to read/write */
295	int value;			/* Current value in usecs */
296};
297
298/* For 82544 PCIX  Workaround */
299typedef struct _ADDRESS_LENGTH_PAIR
300{
301    u_int64_t   address;
302    u_int32_t   length;
303} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
304
305typedef struct _DESCRIPTOR_PAIR
306{
307    ADDRESS_LENGTH_PAIR descriptor[4];
308    u_int32_t   elements;
309} DESC_ARRAY, *PDESC_ARRAY;
310
311/* Our adapter structure */
312struct adapter {
313	struct ifnet   *ifp;
314	struct em_hw    hw;
315
316	/* FreeBSD operating-system-specific structures */
317	struct em_osdep osdep;
318	struct device   *dev;
319	struct resource *res_memory;
320	struct resource *res_ioport;
321	struct resource *res_interrupt;
322	void            *int_handler_tag;
323	struct ifmedia  media;
324	struct callout	timer;
325	struct callout	tx_fifo_timer;
326	int             io_rid;
327	u_int8_t        unit;
328	struct mtx	mtx;
329	int		em_insert_vlan_header;
330
331	/* Info about the board itself */
332	u_int32_t       part_num;
333	u_int8_t        link_active;
334	u_int16_t       link_speed;
335	u_int16_t       link_duplex;
336	u_int32_t       smartspeed;
337	struct em_int_delay_info tx_int_delay;
338	struct em_int_delay_info tx_abs_int_delay;
339	struct em_int_delay_info rx_int_delay;
340	struct em_int_delay_info rx_abs_int_delay;
341
342	XSUM_CONTEXT_T  active_checksum_context;
343
344	/*
345         * Transmit definitions
346         *
347         * We have an array of num_tx_desc descriptors (handled
348         * by the controller) paired with an array of tx_buffers
349         * (at tx_buffer_area).
350         * The index of the next available descriptor is next_avail_tx_desc.
351         * The number of remaining tx_desc is num_tx_desc_avail.
352         */
353	struct em_dma_alloc txdma;              /* bus_dma glue for tx desc */
354        struct em_tx_desc *tx_desc_base;
355        u_int32_t          next_avail_tx_desc;
356	u_int32_t          oldest_used_tx_desc;
357        volatile u_int16_t num_tx_desc_avail;
358        u_int16_t          num_tx_desc;
359        u_int32_t          txd_cmd;
360        struct em_buffer   *tx_buffer_area;
361	bus_dma_tag_t      txtag;               /* dma tag for tx */
362
363	/*
364	 * Receive definitions
365         *
366         * we have an array of num_rx_desc rx_desc (handled by the
367         * controller), and paired with an array of rx_buffers
368         * (at rx_buffer_area).
369         * The next pair to check on receive is at offset next_rx_desc_to_check
370         */
371	struct em_dma_alloc rxdma;              /* bus_dma glue for rx desc */
372        struct em_rx_desc *rx_desc_base;
373        u_int32_t          next_rx_desc_to_check;
374        u_int16_t          num_rx_desc;
375        u_int32_t          rx_buffer_len;
376        struct em_buffer   *rx_buffer_area;
377	bus_dma_tag_t      rxtag;
378
379	/* Jumbo frame */
380	struct mbuf        *fmp;
381	struct mbuf        *lmp;
382
383	/* Misc stats maintained by the driver */
384	unsigned long   dropped_pkts;
385	unsigned long   mbuf_alloc_failed;
386	unsigned long   mbuf_cluster_failed;
387	unsigned long   no_tx_desc_avail1;
388	unsigned long   no_tx_desc_avail2;
389	unsigned long   no_tx_map_avail;
390        unsigned long   no_tx_dma_setup;
391	unsigned long	watchdog_events;
392	unsigned long	rx_overruns;
393
394	/* Used in for 82547 10Mb Half workaround */
395	#define EM_PBA_BYTES_SHIFT	0xA
396	#define EM_TX_HEAD_ADDR_SHIFT	7
397	#define EM_PBA_TX_MASK		0xFFFF0000
398	#define EM_FIFO_HDR              0x10
399
400	#define EM_82547_PKT_THRESH      0x3e0
401
402	u_int32_t       tx_fifo_size;
403	u_int32_t       tx_fifo_head;
404	u_int32_t       tx_fifo_head_addr;
405	u_int64_t       tx_fifo_reset_cnt;
406	u_int64_t       tx_fifo_wrk_cnt;
407	u_int32_t       tx_head_addr;
408
409        /* For 82544 PCIX Workaround */
410        boolean_t       pcix_82544;
411	boolean_t       in_detach;
412
413	struct em_hw_stats stats;
414};
415
416#define	EM_LOCK_INIT(_sc, _name) \
417	mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
418#define	EM_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->mtx)
419#define	EM_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
420#define	EM_UNLOCK(_sc)		mtx_unlock(&(_sc)->mtx)
421#define	EM_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED)
422
423#endif                                                  /* _EM_H_DEFINED_ */
424