if_em.h revision 152247 
1/**************************************************************************
2
3Copyright (c) 2001-2005, Intel Corporation
4All rights reserved.
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6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
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10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
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19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*$FreeBSD: head/sys/dev/em/if_em.h 152247 2005-11-09 15:23:54Z glebius $*/
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/mbuf.h>
46#include <sys/malloc.h>
47#include <sys/module.h>
48#include <sys/socket.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
51
52#include <machine/bus.h>
53#include <sys/rman.h>
54#include <machine/resource.h>
55
56#include <net/bpf.h>
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_media.h>
62
63#include <net/if_types.h>
64#include <net/if_vlan_var.h>
65
66#include <netinet/in_systm.h>
67#include <netinet/in.h>
68#include <netinet/ip.h>
69#include <netinet/tcp.h>
70#include <netinet/udp.h>
71
72#include <dev/pci/pcivar.h>
73#include <dev/pci/pcireg.h>
74
75#include <dev/em/if_em_hw.h>
76
77/* Tunables */
78
79/*
80 * EM_MAX_TXD: Maximum number of Transmit Descriptors
81 * Valid Range: 80-256 for 82542 and 82543-based adapters
82 *              80-4096 for others
83 * Default Value: 256
84 *   This value is the number of transmit descriptors allocated by the driver.
85 *   Increasing this value allows the driver to queue more transmits. Each
86 *   descriptor is 16 bytes.
87 */
88#define EM_MAX_TXD                      256
89
90/*
91 * EM_MAX_RXD - Maximum number of receive Descriptors
92 * Valid Range: 80-256 for 82542 and 82543-based adapters
93 *              80-4096 for others
94 * Default Value: 256
95 *   This value is the number of receive descriptors allocated by the driver.
96 *   Increasing this value allows the driver to buffer more incoming packets.
97 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
98 *   descriptor. The maximum MTU size is 16110.
99 *
100 */
101#define EM_MAX_RXD                      256
102
103/*
104 * EM_TIDV - Transmit Interrupt Delay Value
105 * Valid Range: 0-65535 (0=off)
106 * Default Value: 64
107 *   This value delays the generation of transmit interrupts in units of
108 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
109 *   efficiency if properly tuned for specific network traffic. If the
110 *   system is reporting dropped transmits, this value may be set too high
111 *   causing the driver to run out of available transmit descriptors.
112 */
113#define EM_TIDV                         64
114
115/*
116 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
117 * Valid Range: 0-65535 (0=off)
118 * Default Value: 64
119 *   This value, in units of 1.024 microseconds, limits the delay in which a
120 *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
121 *   this value ensures that an interrupt is generated after the initial
122 *   packet is sent on the wire within the set amount of time.  Proper tuning,
123 *   along with EM_TIDV, may improve traffic throughput in specific
124 *   network conditions.
125 */
126#define EM_TADV                         64
127
128/*
129 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
130 * Valid Range: 0-65535 (0=off)
131 * Default Value: 0
132 *   This value delays the generation of receive interrupts in units of 1.024
133 *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
134 *   properly tuned for specific network traffic. Increasing this value adds
135 *   extra latency to frame reception and can end up decreasing the throughput
136 *   of TCP traffic. If the system is reporting dropped receives, this value
137 *   may be set too high, causing the driver to run out of available receive
138 *   descriptors.
139 *
140 *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
141 *            may hang (stop transmitting) under certain network conditions.
142 *            If this occurs a WATCHDOG message is logged in the system event log.
143 *            In addition, the controller is automatically reset, restoring the
144 *            network connection. To eliminate the potential for the hang
145 *            ensure that EM_RDTR is set to 0.
146 */
147#define EM_RDTR                         0
148
149/*
150 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
151 * Valid Range: 0-65535 (0=off)
152 * Default Value: 64
153 *   This value, in units of 1.024 microseconds, limits the delay in which a
154 *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
155 *   this value ensures that an interrupt is generated after the initial
156 *   packet is received within the set amount of time.  Proper tuning,
157 *   along with EM_RDTR, may improve traffic throughput in specific network
158 *   conditions.
159 */
160#define EM_RADV                         64
161
162/*
163 * Inform the stack about transmit checksum offload capabilities.
164 */
165#define EM_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
166
167/*
168 * This parameter controls the duration of transmit watchdog timer.
169 */
170#define EM_TX_TIMEOUT                   5    /* set to 5 seconds */
171
172/*
173 * This parameter controls when the driver calls the routine to reclaim
174 * transmit descriptors.
175 */
176#define EM_TX_CLEANUP_THRESHOLD         EM_MAX_TXD / 8
177
178/*
179 * This parameter controls whether or not autonegotation is enabled.
180 *              0 - Disable autonegotiation
181 *              1 - Enable  autonegotiation
182 */
183#define DO_AUTO_NEG                     1
184
185/*
186 * This parameter control whether or not the driver will wait for
187 * autonegotiation to complete.
188 *              1 - Wait for autonegotiation to complete
189 *              0 - Don't wait for autonegotiation to complete
190 */
191#define WAIT_FOR_AUTO_NEG_DEFAULT       0
192
193/*
194 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
195 * with 82541/82547 devices and some switches.  See the "Known Limitations" section of
196 * the README file for a complete description and a list of affected switches.
197 *
198 *              0 = Hardware default
199 *              1 = Master mode
200 *              2 = Slave mode
201 *              3 = Auto master/slave
202 */
203/* #define EM_MASTER_SLAVE      2 */
204
205/* Tunables -- End */
206
207#define AUTONEG_ADV_DEFAULT             (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
208                                         ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
209                                         ADVERTISE_1000_FULL)
210
211#define EM_VENDOR_ID                    0x8086
212#define EM_MMBA                         0x0010 /* Mem base address */
213#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
214
215#define EM_JUMBO_PBA                    0x00000028
216#define EM_DEFAULT_PBA                  0x00000030
217#define EM_SMARTSPEED_DOWNSHIFT         3
218#define EM_SMARTSPEED_MAX               15
219
220
221#define MAX_NUM_MULTICAST_ADDRESSES     128
222#define PCI_ANY_ID                      (~0U)
223#define ETHER_ALIGN                     2
224
225/* Defines for printing debug information */
226#define DEBUG_INIT  0
227#define DEBUG_IOCTL 0
228#define DEBUG_HW    0
229
230#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
231#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
232#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
233#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
234#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
235#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
236#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
237#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
238#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
239
240
241/* Supported RX Buffer Sizes */
242#define EM_RXBUFFER_2048        2048
243#define EM_RXBUFFER_4096        4096
244#define EM_RXBUFFER_8192        8192
245#define EM_RXBUFFER_16384      16384
246
247#define EM_MAX_SCATTER            64
248
249/* ******************************************************************************
250 * vendor_info_array
251 *
252 * This array contains the list of Subvendor/Subdevice IDs on which the driver
253 * should load.
254 *
255 * ******************************************************************************/
256typedef struct _em_vendor_info_t {
257	unsigned int vendor_id;
258	unsigned int device_id;
259	unsigned int subvendor_id;
260	unsigned int subdevice_id;
261	unsigned int index;
262} em_vendor_info_t;
263
264
265struct em_buffer {
266        struct mbuf    *m_head;
267        bus_dmamap_t    map;         /* bus_dma map for packet */
268};
269
270/*
271 * Bus dma allocation structure used by
272 * em_dma_malloc and em_dma_free.
273 */
274struct em_dma_alloc {
275        bus_addr_t              dma_paddr;
276        caddr_t                 dma_vaddr;
277        bus_dma_tag_t           dma_tag;
278        bus_dmamap_t            dma_map;
279        bus_dma_segment_t       dma_seg;
280        int                     dma_nseg;
281};
282
283typedef enum _XSUM_CONTEXT_T {
284	OFFLOAD_NONE,
285	OFFLOAD_TCP_IP,
286	OFFLOAD_UDP_IP
287} XSUM_CONTEXT_T;
288
289struct adapter;
290struct em_int_delay_info {
291	struct adapter *adapter;	/* Back-pointer to the adapter struct */
292	int offset;			/* Register offset to read/write */
293	int value;			/* Current value in usecs */
294};
295
296/* For 82544 PCIX  Workaround */
297typedef struct _ADDRESS_LENGTH_PAIR
298{
299    u_int64_t   address;
300    u_int32_t   length;
301} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
302
303typedef struct _DESCRIPTOR_PAIR
304{
305    ADDRESS_LENGTH_PAIR descriptor[4];
306    u_int32_t   elements;
307} DESC_ARRAY, *PDESC_ARRAY;
308
309/* Our adapter structure */
310struct adapter {
311	struct ifnet   *ifp;
312	struct em_hw    hw;
313
314	/* FreeBSD operating-system-specific structures */
315	struct em_osdep osdep;
316	struct device   *dev;
317	struct resource *res_memory;
318	struct resource *res_ioport;
319	struct resource *res_interrupt;
320	void            *int_handler_tag;
321	struct ifmedia  media;
322	struct callout	timer;
323	struct callout	tx_fifo_timer;
324	int             io_rid;
325	u_int8_t        unit;
326	struct mtx	mtx;
327	int		em_insert_vlan_header;
328
329	/* Info about the board itself */
330	u_int32_t       part_num;
331	u_int8_t        link_active;
332	u_int16_t       link_speed;
333	u_int16_t       link_duplex;
334	u_int32_t       smartspeed;
335	struct em_int_delay_info tx_int_delay;
336	struct em_int_delay_info tx_abs_int_delay;
337	struct em_int_delay_info rx_int_delay;
338	struct em_int_delay_info rx_abs_int_delay;
339
340	XSUM_CONTEXT_T  active_checksum_context;
341
342	/*
343         * Transmit definitions
344         *
345         * We have an array of num_tx_desc descriptors (handled
346         * by the controller) paired with an array of tx_buffers
347         * (at tx_buffer_area).
348         * The index of the next available descriptor is next_avail_tx_desc.
349         * The number of remaining tx_desc is num_tx_desc_avail.
350         */
351	struct em_dma_alloc txdma;              /* bus_dma glue for tx desc */
352        struct em_tx_desc *tx_desc_base;
353        u_int32_t          next_avail_tx_desc;
354	u_int32_t          oldest_used_tx_desc;
355        volatile u_int16_t num_tx_desc_avail;
356        u_int16_t          num_tx_desc;
357        u_int32_t          txd_cmd;
358        struct em_buffer   *tx_buffer_area;
359	bus_dma_tag_t      txtag;               /* dma tag for tx */
360
361	/*
362	 * Receive definitions
363         *
364         * we have an array of num_rx_desc rx_desc (handled by the
365         * controller), and paired with an array of rx_buffers
366         * (at rx_buffer_area).
367         * The next pair to check on receive is at offset next_rx_desc_to_check
368         */
369	struct em_dma_alloc rxdma;              /* bus_dma glue for rx desc */
370        struct em_rx_desc *rx_desc_base;
371        u_int32_t          next_rx_desc_to_check;
372        u_int16_t          num_rx_desc;
373        u_int32_t          rx_buffer_len;
374        struct em_buffer   *rx_buffer_area;
375	bus_dma_tag_t      rxtag;
376
377	/* Jumbo frame */
378	struct mbuf        *fmp;
379	struct mbuf        *lmp;
380
381	/* Misc stats maintained by the driver */
382	unsigned long   dropped_pkts;
383	unsigned long   mbuf_alloc_failed;
384	unsigned long   mbuf_cluster_failed;
385	unsigned long   no_tx_desc_avail1;
386	unsigned long   no_tx_desc_avail2;
387	unsigned long   no_tx_map_avail;
388        unsigned long   no_tx_dma_setup;
389	unsigned long	watchdog_events;
390	unsigned long	rx_overruns;
391
392	/* Used in for 82547 10Mb Half workaround */
393	#define EM_PBA_BYTES_SHIFT	0xA
394	#define EM_TX_HEAD_ADDR_SHIFT	7
395	#define EM_PBA_TX_MASK		0xFFFF0000
396	#define EM_FIFO_HDR              0x10
397
398	#define EM_82547_PKT_THRESH      0x3e0
399
400	u_int32_t       tx_fifo_size;
401	u_int32_t       tx_fifo_head;
402	u_int32_t       tx_fifo_head_addr;
403	u_int64_t       tx_fifo_reset_cnt;
404	u_int64_t       tx_fifo_wrk_cnt;
405	u_int32_t       tx_head_addr;
406
407        /* For 82544 PCIX Workaround */
408        boolean_t       pcix_82544;
409	boolean_t       in_detach;
410
411	struct em_hw_stats stats;
412};
413
414#define	EM_LOCK_INIT(_sc, _name) \
415	mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
416#define	EM_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->mtx)
417#define	EM_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
418#define	EM_UNLOCK(_sc)		mtx_unlock(&(_sc)->mtx)
419#define	EM_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED)
420
421#endif                                                  /* _EM_H_DEFINED_ */
422