if_em.c revision 170141
1151912Sphk/************************************************************************** 2151912Sphk 3209440SmavCopyright (c) 2001-2007, Intel Corporation 4151912SphkAll rights reserved. 5151912Sphk 6151912SphkRedistribution and use in source and binary forms, with or without 7151912Sphkmodification, are permitted provided that the following conditions are met: 8151912Sphk 9151912Sphk 1. Redistributions of source code must retain the above copyright notice, 10151912Sphk this list of conditions and the following disclaimer. 11151912Sphk 12151912Sphk 2. Redistributions in binary form must reproduce the above copyright 13151912Sphk notice, this list of conditions and the following disclaimer in the 14151912Sphk documentation and/or other materials provided with the distribution. 15151912Sphk 16151912Sphk 3. Neither the name of the Intel Corporation nor the names of its 17151912Sphk contributors may be used to endorse or promote products derived from 18151912Sphk this software without specific prior written permission. 19151912Sphk 20151912SphkTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21151912SphkAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22151912SphkIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23151912SphkARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24151912SphkLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25151912SphkCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26151912SphkSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27151912SphkINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28151912SphkCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29151912SphkARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30151912SphkPOSSIBILITY OF SUCH DAMAGE. 31151912Sphk 32268351Smarcel***************************************************************************/ 33209371Smav 34209371Smav/*$FreeBSD: head/sys/dev/em/if_em.c 170141 2007-05-30 23:32:21Z jfv $*/ 35209371Smav 36209371Smav#ifdef HAVE_KERNEL_OPTION_HEADERS 37151912Sphk#include "opt_device_polling.h" 38273598Srpaulo#endif 39159217Snjl 40151912Sphk#include <sys/param.h> 41151912Sphk#include <sys/systm.h> 42209371Smav#include <sys/bus.h> 43151912Sphk#include <sys/endian.h> 44273598Srpaulo#include <sys/kernel.h> 45151912Sphk#include <sys/kthread.h> 46209371Smav#include <sys/malloc.h> 47209371Smav#include <sys/mbuf.h> 48209371Smav#include <sys/module.h> 49151912Sphk#include <sys/rman.h> 50159217Snjl#include <sys/socket.h> 51193530Sjkim#include <sys/sockio.h> 52193530Sjkim#include <sys/sysctl.h> 53193530Sjkim#include <sys/taskqueue.h> 54151912Sphk 55175385Sjhb#include <machine/bus.h> 56151912Sphk#include <machine/resource.h> 57209371Smav 58209371Smav#include <net/bpf.h> 59209371Smav#include <net/ethernet.h> 60209371Smav#include <net/if.h> 61203062Savg#include <net/if_arp.h> 62240286Smav#include <net/if_dl.h> 63203062Savg#include <net/if_media.h> 64213302Smav 65232797Smav#include <net/if_types.h> 66203062Savg#include <net/if_vlan_var.h> 67151912Sphk 68151912Sphk#include <netinet/in_systm.h> 69209371Smav#include <netinet/in.h> 70169574Stakawata#include <netinet/if_ether.h> 71151931Sscottl#include <netinet/ip.h> 72151935Sscottl#include <netinet/ip6.h> 73151931Sscottl#include <netinet/tcp.h> 74151931Sscottl#include <netinet/udp.h> 75209371Smav 76151912Sphk#include <machine/in_cksum.h> 77209371Smav#include <dev/pci/pcivar.h> 78209371Smav#include <dev/pci/pcireg.h> 79209371Smav 80209371Smav#include "e1000_api.h" 81209440Smav#include "e1000_82575.h" 82212533Smav#include "if_em.h" 83212238Smav 84159217Snjl/********************************************************************* 85209371Smav * Set this to one to display debug statistics 86209371Smav *********************************************************************/ 87151912Sphkint em_display_debug_stats = 0; 88209371Smav 89209440Smav/********************************************************************* 90209371Smav * Driver version: 91209371Smav *********************************************************************/ 92209371Smavchar em_driver_version[] = "Version - 6.5.3"; 93209371Smav 94209371Smav 95209371Smav/********************************************************************* 96209371Smav * PCI Device ID Table 97209371Smav * 98212323Smav * Used by probe to select devices to load on 99212323Smav * Last field stores an index into e1000_strings 100209371Smav * Last entry must be all 0s 101209371Smav * 102209371Smav * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 103209371Smav *********************************************************************/ 104209371Smav 105209371Smavstatic em_vendor_info_t em_vendor_info_array[] = 106209371Smav{ 107212491Smav /* Intel(R) PRO/1000 Network Connection */ 108209371Smav { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 109209371Smav { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 110209371Smav { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 111273598Srpaulo { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 112273598Srpaulo { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 113273598Srpaulo 114273598Srpaulo { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115151912Sphk { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 116151912Sphk { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 117273598Srpaulo { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 118273598Srpaulo { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 119273598Srpaulo { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 120273598Srpaulo { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 121273598Srpaulo 122273598Srpaulo { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 123273598Srpaulo 124273598Srpaulo { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125273598Srpaulo { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126273598Srpaulo 127273598Srpaulo { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 128273598Srpaulo { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129273598Srpaulo { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130159217Snjl { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 131209371Smav 132151912Sphk { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133159217Snjl { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 134159217Snjl { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135269515Sroyger { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136269515Sroyger { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 137269515Sroyger 138159217Snjl { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139151912Sphk { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140151912Sphk { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 141209371Smav { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142151912Sphk { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143151912Sphk { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 144175385Sjhb { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145151912Sphk { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 146151912Sphk { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 147175361Sjhb PCI_ANY_ID, PCI_ANY_ID, 0}, 148209371Smav 149175361Sjhb { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 150175361Sjhb { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 151175385Sjhb { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 152175385Sjhb 153209440Smav { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154209440Smav { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155209440Smav { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156209440Smav { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 157185103Sjkim PCI_ANY_ID, PCI_ANY_ID, 0}, 158185103Sjkim { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 159175361Sjhb PCI_ANY_ID, PCI_ANY_ID, 0}, 160175361Sjhb { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 161175361Sjhb PCI_ANY_ID, PCI_ANY_ID, 0}, 162209371Smav { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 163175361Sjhb { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 164175361Sjhb { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 165175385Sjhb { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 166175385Sjhb 167185103Sjkim { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 168185103Sjkim { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 169175361Sjhb { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 170175361Sjhb { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 171209371Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 172247463Smav { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 173209371Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 174209371Smav { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 175209371Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 176209371Smav { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 177212491Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 178209371Smav { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 179209371Smav { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 180247463Smav { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 181209371Smav { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 182247463Smav { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 183209371Smav { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 184209371Smav { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 185209371Smav 186209371Smav { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 187247463Smav { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 188247463Smav { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 189247463Smav { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 190210290Smav { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 191212238Smav 192212238Smav { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 193212238Smav { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 194212491Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 195212238Smav { 0x8086, E1000_DEV_ID_82575EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 196212491Smav { 0x8086, E1000_DEV_ID_82575EM_FIBER_SERDES, 197209371Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 198209371Smav { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 199209371Smav PCI_ANY_ID, PCI_ANY_ID, 0}, 200209371Smav /* required last entry */ 201212491Smav { 0, 0, 0, 0, 0} 202212491Smav}; 203212491Smav 204212491Smav/********************************************************************* 205209371Smav * Table of branding strings for all supported NICs. 206212238Smav *********************************************************************/ 207212491Smav 208212491Smavstatic char *em_strings[] = { 209212491Smav "Intel(R) PRO/1000 Network Connection" 210212491Smav}; 211209371Smav 212224919Smav/********************************************************************* 213224919Smav * Function prototypes 214224919Smav *********************************************************************/ 215224919Smavstatic int em_probe(device_t); 216212238Smavstatic int em_attach(device_t); 217209371Smavstatic int em_detach(device_t); 218209371Smavstatic int em_shutdown(device_t); 219209371Smavstatic int em_suspend(device_t); 220209371Smavstatic int em_resume(device_t); 221209371Smavstatic void em_start(struct ifnet *); 222209371Smavstatic void em_start_locked(struct ifnet *ifp); 223209371Smavstatic int em_ioctl(struct ifnet *, u_long, caddr_t); 224209371Smavstatic void em_watchdog(struct adapter *); 225209371Smavstatic void em_init(void *); 226209371Smavstatic void em_init_locked(struct adapter *); 227209371Smavstatic void em_stop(void *); 228209371Smavstatic void em_media_status(struct ifnet *, struct ifmediareq *); 229209371Smavstatic int em_media_change(struct ifnet *); 230209371Smavstatic void em_identify_hardware(struct adapter *); 231209371Smavstatic int em_allocate_pci_resources(struct adapter *); 232209371Smavstatic int em_allocate_intr(struct adapter *); 233209371Smavstatic void em_free_intr(struct adapter *); 234209371Smavstatic void em_free_pci_resources(struct adapter *); 235209371Smavstatic void em_local_timer(void *); 236209371Smavstatic int em_hardware_init(struct adapter *); 237209371Smavstatic void em_setup_interface(device_t, struct adapter *); 238209371Smavstatic int em_setup_transmit_structures(struct adapter *); 239209371Smavstatic void em_initialize_transmit_unit(struct adapter *); 240209371Smavstatic int em_setup_receive_structures(struct adapter *); 241209371Smavstatic void em_initialize_receive_unit(struct adapter *); 242212491Smavstatic void em_enable_intr(struct adapter *); 243212491Smavstatic void em_disable_intr(struct adapter *); 244212323Smavstatic void em_free_transmit_structures(struct adapter *); 245212323Smavstatic void em_free_receive_structures(struct adapter *); 246212323Smavstatic void em_update_stats_counters(struct adapter *); 247212323Smavstatic void em_txeof(struct adapter *); 248212323Smavstatic int em_allocate_receive_structures(struct adapter *); 249212323Smavstatic int em_allocate_transmit_structures(struct adapter *); 250212323Smavstatic int em_rxeof(struct adapter *, int); 251212323Smav#ifndef __NO_STRICT_ALIGNMENT 252212323Smavstatic int em_fixup_rx(struct adapter *); 253212323Smav#endif 254212323Smavstatic void em_receive_checksum(struct adapter *, struct e1000_rx_desc *, 255212323Smav struct mbuf *); 256212323Smavstatic void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 257212323Smav uint32_t *, uint32_t *); 258212491Smavstatic boolean_t em_tx_adv_ctx_setup(struct adapter *, struct mbuf *); 259212491Smavstatic boolean_t em_tso_setup(struct adapter *, struct mbuf *, uint32_t *, 260212323Smav uint32_t *); 261212491Smavstatic boolean_t em_tso_adv_setup(struct adapter *, struct mbuf *, uint32_t *); 262212323Smavstatic void em_set_promisc(struct adapter *); 263212323Smavstatic void em_disable_promisc(struct adapter *); 264212323Smavstatic void em_set_multi(struct adapter *); 265209371Smavstatic void em_print_hw_stats(struct adapter *); 266209371Smavstatic void em_update_link_status(struct adapter *); 267212491Smavstatic int em_get_buf(struct adapter *, int); 268209371Smavstatic void em_enable_vlans(struct adapter *); 269212491Smavstatic int em_encap(struct adapter *, struct mbuf **); 270212491Smavstatic int em_adv_encap(struct adapter *, struct mbuf **); 271209371Smavstatic void em_smartspeed(struct adapter *); 272212491Smavstatic int em_82547_fifo_workaround(struct adapter *, int); 273209371Smavstatic void em_82547_update_fifo_head(struct adapter *, int); 274209371Smavstatic int em_82547_tx_fifo_reset(struct adapter *); 275209371Smavstatic void em_82547_move_tail(void *); 276209990Smavstatic int em_dma_malloc(struct adapter *, bus_size_t, 277209990Smav struct em_dma_alloc *, int); 278209371Smavstatic void em_dma_free(struct adapter *, struct em_dma_alloc *); 279209371Smavstatic void em_print_debug_info(struct adapter *); 280209371Smavstatic int em_is_valid_ether_addr(uint8_t *); 281209371Smavstatic int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 282209371Smavstatic int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 283209371Smavstatic uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 284209371Smav PDESC_ARRAY desc_array); 285209371Smavstatic int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 286209371Smavstatic void em_add_int_delay_sysctl(struct adapter *, const char *, 287209371Smav const char *, struct em_int_delay_info *, int, int); 288209371Smav/* Management and WOL Support */ 289209371Smavstatic void em_init_manageability(struct adapter *); 290209371Smavstatic void em_release_manageability(struct adapter *); 291209371Smavstatic void em_get_hw_control(struct adapter *); 292209371Smavstatic void em_release_hw_control(struct adapter *); 293209371Smavstatic void em_enable_wakeup(device_t); 294209371Smav 295209371Smav#ifdef DEVICE_POLLING 296209371Smavstatic poll_handler_t em_poll; 297209371Smavstatic void em_intr(void *); 298209371Smav#else 299209371Smavstatic int em_intr_fast(void *); 300209371Smavstatic void em_add_rx_process_limit(struct adapter *, const char *, 301209371Smav const char *, int *, int); 302208436Smavstatic void em_handle_rxtx(void *context, int pending); 303209371Smavstatic void em_handle_link(void *context, int pending); 304208436Smav#endif 305208436Smav 306208436Smav/********************************************************************* 307208436Smav * FreeBSD Device Interface Entry Points 308208438Smav *********************************************************************/ 309208436Smav 310208436Smavstatic device_method_t em_methods[] = { 311208436Smav /* Device interface */ 312208436Smav DEVMETHOD(device_probe, em_probe), 313208436Smav DEVMETHOD(device_attach, em_attach), 314208436Smav DEVMETHOD(device_detach, em_detach), 315208436Smav DEVMETHOD(device_shutdown, em_shutdown), 316209371Smav DEVMETHOD(device_suspend, em_suspend), 317209371Smav DEVMETHOD(device_resume, em_resume), 318258164Smav {0, 0} 319208436Smav}; 320208436Smav 321208436Smavstatic driver_t em_driver = { 322216263Sjhb "em", em_methods, sizeof(struct adapter), 323216263Sjhb}; 324216263Sjhb 325216263Sjhbstatic devclass_t em_devclass; 326216263SjhbDRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 327216263SjhbMODULE_DEPEND(em, pci, 1, 1, 1); 328216263SjhbMODULE_DEPEND(em, ether, 1, 1, 1); 329216263Sjhb 330216263Sjhb/********************************************************************* 331216263Sjhb * Tunable default values. 332216263Sjhb *********************************************************************/ 333216263Sjhb 334216263Sjhb#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 335216263Sjhb#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 336216263Sjhb#define M_TSO_LEN 66 337216263Sjhb 338216263Sjhbstatic int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 339273598Srpaulostatic int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 340273598Srpaulostatic int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 341273598Srpaulostatic int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 342273598Srpaulostatic int em_rxd = EM_DEFAULT_RXD; 343273598Srpaulostatic int em_txd = EM_DEFAULT_TXD; 344273598Srpaulostatic int em_smart_pwr_down = FALSE; 345273598Srpaulo 346273598SrpauloTUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 347273598SrpauloTUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 348273598SrpauloTUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 349273598SrpauloTUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 350273598SrpauloTUNABLE_INT("hw.em.rxd", &em_rxd); 351273598SrpauloTUNABLE_INT("hw.em.txd", &em_txd); 352273598SrpauloTUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 353273598Srpaulo#ifndef DEVICE_POLLING 354273598Srpaulo/* How many packets rxeof tries to clean at a time */ 355273598Srpaulostatic int em_rx_process_limit = 100; 356273598SrpauloTUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 357273598Srpaulo#endif 358273598Srpaulo/* Global used in WOL setup with multiport cards */ 359273598Srpaulostatic int global_quad_port_a = 0; 360273598Srpaulo 361273598Srpaulo/********************************************************************* 362273598Srpaulo * Device identification routine 363273598Srpaulo * 364273598Srpaulo * em_probe determines if the driver should be loaded on 365273598Srpaulo * adapter based on PCI vendor/device id of the adapter. 366273598Srpaulo * 367273598Srpaulo * return BUS_PROBE_DEFAULT on success, positive on failure 368273598Srpaulo *********************************************************************/ 369273598Srpaulo 370273598Srpaulostatic int 371273598Srpauloem_probe(device_t dev) 372273598Srpaulo{ 373273598Srpaulo char adapter_name[60]; 374273598Srpaulo uint16_t pci_vendor_id = 0; 375273598Srpaulo uint16_t pci_device_id = 0; 376273598Srpaulo uint16_t pci_subvendor_id = 0; 377273598Srpaulo uint16_t pci_subdevice_id = 0; 378273598Srpaulo em_vendor_info_t *ent; 379273598Srpaulo 380169592Snjl INIT_DEBUGOUT("em_probe: begin"); 381172489Snjl 382209371Smav pci_vendor_id = pci_get_vendor(dev); 383169574Stakawata if (pci_vendor_id != EM_VENDOR_ID) 384169574Stakawata return (ENXIO); 385169574Stakawata 386169574Stakawata pci_device_id = pci_get_device(dev); 387258164Smav pci_subvendor_id = pci_get_subvendor(dev); 388169574Stakawata pci_subdevice_id = pci_get_subdevice(dev); 389172489Snjl 390209371Smav ent = em_vendor_info_array; 391172489Snjl while (ent->vendor_id != 0) { 392208436Smav if ((pci_vendor_id == ent->vendor_id) && 393208436Smav (pci_device_id == ent->device_id) && 394208436Smav 395208436Smav ((pci_subvendor_id == ent->subvendor_id) || 396208436Smav (ent->subvendor_id == PCI_ANY_ID)) && 397208436Smav 398258164Smav ((pci_subdevice_id == ent->subdevice_id) || 399208436Smav (ent->subdevice_id == PCI_ANY_ID))) { 400258164Smav sprintf(adapter_name, "%s %s", 401258164Smav em_strings[ent->index], 402208436Smav em_driver_version); 403258164Smav device_set_desc_copy(dev, adapter_name); 404258164Smav return (BUS_PROBE_DEFAULT); 405258164Smav } 406258164Smav ent++; 407258164Smav } 408208436Smav 409258164Smav return (ENXIO); 410208436Smav} 411231161Sjkim 412208436Smav/********************************************************************* 413208436Smav * Device initialization routine 414208436Smav * 415208436Smav * The attach entry point is called when the driver is being loaded. 416208436Smav * This routine identifies the type of hardware, allocates all resources 417208436Smav * and initializes the hardware. 418169574Stakawata * 419169574Stakawata * return 0 on success, positive on failure 420169574Stakawata *********************************************************************/ 421151912Sphk 422209371Smavstatic int 423151912Sphkem_attach(device_t dev) 424159217Snjl{ 425159217Snjl struct adapter *adapter; 426269515Sroyger int tsize, rsize; 427151912Sphk int error = 0; 428199016Savg u16 eeprom_data, device_id; 429208436Smav 430169592Snjl INIT_DEBUGOUT("em_attach: begin"); 431151912Sphk 432159217Snjl adapter = device_get_softc(dev); 433151912Sphk adapter->dev = adapter->osdep.dev = dev; 434151912Sphk EM_LOCK_INIT(adapter, device_get_nameunit(dev)); 435151912Sphk 436151912Sphk /* SYSCTL stuff */ 437209371Smav SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 438151912Sphk SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 439209371Smav OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 440209371Smav em_sysctl_debug_info, "I", "Debug Information"); 441209371Smav 442209371Smav SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 443209371Smav SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 444212238Smav OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 445209371Smav em_sysctl_stats, "I", "Statistics"); 446151912Sphk 447151912Sphk callout_init_mtx(&adapter->timer, &adapter->mtx, 0); 448151912Sphk callout_init_mtx(&adapter->tx_fifo_timer, &adapter->mtx, 0); 449151912Sphk 450151912Sphk /* Determine hardware and mac info */ 451151912Sphk em_identify_hardware(adapter); 452151912Sphk 453209371Smav /* Setup PCI resources */ 454209371Smav if (em_allocate_pci_resources(adapter)) { 455159217Snjl device_printf(dev, "Allocation of PCI resources failed\n"); 456159217Snjl error = ENXIO; 457159217Snjl goto err_pci; 458151912Sphk } 459159217Snjl 460159217Snjl /* 461159217Snjl ** For ICH8 and family we need to 462159217Snjl ** map the flash memory, and this 463159217Snjl ** must happen after the MAC is 464159217Snjl ** identified 465159217Snjl */ 466151912Sphk if ((adapter->hw.mac.type == e1000_ich8lan) || 467171547Snjl (adapter->hw.mac.type == e1000_ich9lan)) { 468175361Sjhb int rid = EM_BAR_TYPE_FLASH; 469171547Snjl adapter->flash_mem = bus_alloc_resource_any(dev, 470159217Snjl SYS_RES_MEMORY, &rid, RF_ACTIVE); 471175385Sjhb /* This is used in the shared code */ 472175361Sjhb adapter->hw.flash_address = (u8 *)adapter->flash_mem; 473175361Sjhb adapter->osdep.flash_bus_space_tag = 474175361Sjhb rman_get_bustag(adapter->flash_mem); 475175361Sjhb adapter->osdep.flash_bus_space_handle = 476175361Sjhb rman_get_bushandle(adapter->flash_mem); 477175361Sjhb } 478175361Sjhb 479209371Smav /* Do Shared Code initialization */ 480209440Smav if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 481209440Smav device_printf(dev, "Setup of Shared code failed\n"); 482209440Smav error = ENXIO; 483209440Smav goto err_pci; 484209371Smav } 485209371Smav 486209371Smav e1000_get_bus_info(&adapter->hw); 487209371Smav 488209371Smav /* Set up some sysctls for the tunable interrupt delays */ 489209371Smav em_add_int_delay_sysctl(adapter, "rx_int_delay", 490209371Smav "receive interrupt delay in usecs", &adapter->rx_int_delay, 491209371Smav E1000_REGISTER(&adapter->hw, E1000_RDTR), em_rx_int_delay_dflt); 492209371Smav em_add_int_delay_sysctl(adapter, "tx_int_delay", 493159217Snjl "transmit interrupt delay in usecs", &adapter->tx_int_delay, 494159217Snjl E1000_REGISTER(&adapter->hw, E1000_TIDV), em_tx_int_delay_dflt); 495209371Smav if (adapter->hw.mac.type >= e1000_82540) { 496209440Smav em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 497209440Smav "receive interrupt delay limit in usecs", 498209440Smav &adapter->rx_abs_int_delay, 499209440Smav E1000_REGISTER(&adapter->hw, E1000_RADV), 500159217Snjl em_rx_abs_int_delay_dflt); 501209371Smav em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 502209371Smav "transmit interrupt delay limit in usecs", 503209371Smav &adapter->tx_abs_int_delay, 504209371Smav E1000_REGISTER(&adapter->hw, E1000_TADV), 505209371Smav em_tx_abs_int_delay_dflt); 506209371Smav } 507209371Smav 508212323Smav#ifndef DEVICE_POLLING 509212323Smav /* Sysctls for limiting the amount of work done in the taskqueue */ 510209371Smav em_add_rx_process_limit(adapter, "rx_processing_limit", 511209371Smav "max number of rx packets to process", &adapter->rx_process_limit, 512209371Smav em_rx_process_limit); 513209371Smav#endif 514209371Smav 515209371Smav /* 516209371Smav * Validate number of transmit and receive descriptors. It 517209371Smav * must not exceed hardware maximum, and must be multiple 518209371Smav * of E1000_DBA_ALIGN. 519209371Smav */ 520209371Smav if (((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN) != 0 || 521209371Smav (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 522159217Snjl (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 523209371Smav (em_txd < EM_MIN_TXD)) { 524171547Snjl device_printf(dev, "Using %d TX descriptors instead of %d!\n", 525171547Snjl EM_DEFAULT_TXD, em_txd); 526171547Snjl adapter->num_tx_desc = EM_DEFAULT_TXD; 527171547Snjl } else 528175385Sjhb adapter->num_tx_desc = em_txd; 529171547Snjl if (((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN) != 0 || 530175385Sjhb (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 531171547Snjl (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 532171547Snjl (em_rxd < EM_MIN_RXD)) { 533175361Sjhb device_printf(dev, "Using %d RX descriptors instead of %d!\n", 534171547Snjl EM_DEFAULT_RXD, em_rxd); 535171547Snjl adapter->num_rx_desc = EM_DEFAULT_RXD; 536171547Snjl } else 537208436Smav adapter->num_rx_desc = em_rxd; 538208436Smav 539209371Smav adapter->hw.mac.autoneg = DO_AUTO_NEG; 540209371Smav adapter->hw.phy.wait_for_link = FALSE; 541209371Smav adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 542222222Sjkim adapter->rx_buffer_len = 2048; 543209371Smav 544209371Smav e1000_init_script_state_82541(&adapter->hw, TRUE); 545209371Smav e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 546208436Smav 547209371Smav /* Copper options */ 548209371Smav if (adapter->hw.media_type == e1000_media_type_copper) { 549209371Smav adapter->hw.phy.mdix = AUTO_ALL_MODES; 550209371Smav adapter->hw.phy.disable_polarity_correction = FALSE; 551209440Smav adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 552209440Smav } 553209440Smav 554209440Smav /* 555209440Smav * Set the max frame size assuming standard ethernet 556209440Smav * sized frames. 557209440Smav */ 558209440Smav adapter->hw.mac.max_frame_size = 559209440Smav ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 560209440Smav 561209440Smav adapter->hw.mac.min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; 562209440Smav 563212238Smav /* 564212238Smav * This controls when hardware reports transmit completion 565212238Smav * status. 566209371Smav */ 567209371Smav adapter->hw.mac.report_tx_early = 1; 568209371Smav 569209371Smav tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 570209371Smav EM_DBA_ALIGN); 571209371Smav 572209371Smav /* Allocate Transmit Descriptor ring */ 573240286Smav if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 574212238Smav device_printf(dev, "Unable to allocate tx_desc memory\n"); 575212238Smav error = ENOMEM; 576213302Smav goto err_tx_desc; 577213302Smav } 578213302Smav adapter->tx_desc_base = 579213302Smav (struct e1000_tx_desc *)adapter->txdma.dma_vaddr; 580213302Smav 581213302Smav rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 582232797Smav EM_DBA_ALIGN); 583232797Smav 584232797Smav /* Allocate Receive Descriptor ring */ 585232797Smav if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 586232797Smav device_printf(dev, "Unable to allocate rx_desc memory\n"); 587232797Smav error = ENOMEM; 588232797Smav goto err_rx_desc; 589212238Smav } 590212238Smav adapter->rx_desc_base = 591215473Sjhb (struct e1000_rx_desc *)adapter->rxdma.dma_vaddr; 592212238Smav 593212238Smav /* Make sure we have a good EEPROM before we read from it */ 594212238Smav if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 595212238Smav /* 596212238Smav ** Some PCI-E parts fail the first check due to 597212238Smav ** the link being in sleep state, call it again, 598212238Smav ** if it fails a second time its a real issue. 599212533Smav */ 600212533Smav if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 601212533Smav device_printf(dev, 602212533Smav "The EEPROM Checksum Is Not Valid\n"); 603212533Smav error = EIO; 604212238Smav goto err_hw_init; 605212238Smav } 606212238Smav } 607212238Smav 608212238Smav if (e1000_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { 609212238Smav device_printf(dev, "EEPROM read error " 610212238Smav "reading part number\n"); 611209371Smav error = EIO; 612209371Smav goto err_hw_init; 613209440Smav } 614209440Smav 615209371Smav /* Initialize the hardware */ 616209440Smav if (em_hardware_init(adapter)) { 617209371Smav device_printf(dev, "Unable to initialize the hardware\n"); 618209371Smav error = EIO; 619209371Smav goto err_hw_init; 620209371Smav } 621269897Sneel 622269897Sneel /* Copy the permanent MAC address out of the EEPROM */ 623209440Smav if (e1000_read_mac_addr(&adapter->hw) < 0) { 624209440Smav device_printf(dev, "EEPROM read error while reading MAC" 625209440Smav " address\n"); 626212238Smav error = EIO; 627212238Smav goto err_hw_init; 628212238Smav } 629212238Smav 630209440Smav if (!em_is_valid_ether_addr(adapter->hw.mac.addr)) { 631216263Sjhb device_printf(dev, "Invalid MAC address\n"); 632216490Sjhb error = EIO; 633216490Sjhb goto err_hw_init; 634216490Sjhb } 635209440Smav 636209440Smav /* Setup OS specific network interface */ 637209440Smav em_setup_interface(dev, adapter); 638216490Sjhb 639216490Sjhb em_allocate_intr(adapter); 640216490Sjhb 641209440Smav /* Initialize statistics */ 642209440Smav em_update_stats_counters(adapter); 643209440Smav 644209371Smav adapter->hw.mac.get_link_status = 1; 645209371Smav em_update_link_status(adapter); 646209371Smav 647209371Smav /* Indicate SOL/IDER usage */ 648209371Smav if (e1000_check_reset_block(&adapter->hw)) 649209440Smav device_printf(dev, 650209440Smav "PHY reset is blocked due to SOL/IDER session.\n"); 651209371Smav 652209371Smav /* Determine if we have to control management hardware */ 653209371Smav adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 654209371Smav 655209440Smav /* 656209440Smav * Setup Wake-on-Lan 657209440Smav */ 658209440Smav switch (adapter->hw.mac.type) { 659209440Smav 660212533Smav case e1000_82542: 661209440Smav case e1000_82543: 662209440Smav break; 663209440Smav case e1000_82546: 664209440Smav case e1000_82546_rev_3: 665209440Smav case e1000_82571: 666209440Smav case e1000_80003es2lan: 667209440Smav if (adapter->hw.bus.func == 1) 668209440Smav e1000_read_nvm(&adapter->hw, 669212323Smav NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 670209440Smav else 671209440Smav e1000_read_nvm(&adapter->hw, 672209440Smav NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 673209440Smav eeprom_data &= EM_EEPROM_APME; 674209440Smav break; 675209440Smav default: 676212238Smav /* APME bit in EEPROM is mapped to WUC.APME */ 677212238Smav eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & 678209440Smav E1000_WUC_APME; 679209371Smav break; 680209371Smav } 681215473Sjhb if (eeprom_data) 682209371Smav adapter->wol = E1000_WUFC_MAG; 683209371Smav /* 684209371Smav * We have the eeprom settings, now apply the special cases 685209371Smav * where the eeprom may be wrong or the board won't support 686216263Sjhb * wake on lan on a particular port 687216490Sjhb */ 688216490Sjhb device_id = pci_get_device(dev); 689216490Sjhb switch (device_id) { 690216490Sjhb case E1000_DEV_ID_82546GB_PCIE: 691216490Sjhb adapter->wol = 0; 692216490Sjhb break; 693209371Smav case E1000_DEV_ID_82546EB_FIBER: 694209371Smav case E1000_DEV_ID_82546GB_FIBER: 695209371Smav case E1000_DEV_ID_82571EB_FIBER: 696209371Smav /* Wake events only supported on port A for dual fiber 697209371Smav * regardless of eeprom setting */ 698209371Smav if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 699209371Smav E1000_STATUS_FUNC_1) 700209371Smav adapter->wol = 0; 701209371Smav break; 702209371Smav case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 703209371Smav case E1000_DEV_ID_82571EB_QUAD_COPPER: 704209371Smav case E1000_DEV_ID_82571EB_QUAD_FIBER: 705209440Smav case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 706209371Smav /* if quad port adapter, disable WoL on all but port A */ 707209440Smav if (global_quad_port_a != 0) 708209440Smav adapter->wol = 0; 709209440Smav /* Reset for multiple quad port adapters */ 710209371Smav if (++global_quad_port_a == 4) 711212238Smav global_quad_port_a = 0; 712209371Smav break; 713209371Smav } 714209371Smav 715209371Smav /* Do we need workaround for 82544 PCI-X adapter? */ 716209371Smav if (adapter->hw.bus.type == e1000_bus_type_pcix && 717209371Smav adapter->hw.mac.type == e1000_82544) 718209371Smav adapter->pcix_82544 = TRUE; 719209371Smav else 720209371Smav adapter->pcix_82544 = FALSE; 721209371Smav 722209371Smav /* Get control from any management/hw control */ 723209371Smav if (((adapter->hw.mac.type == e1000_82573) || 724209371Smav (adapter->hw.mac.type == e1000_ich8lan) || 725209371Smav (adapter->hw.mac.type == e1000_ich9lan)) && 726209371Smav e1000_check_mng_mode(&adapter->hw)) 727212238Smav em_get_hw_control(adapter); 728212238Smav 729212238Smav /* Tell the stack that the interface is not active */ 730209371Smav adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 731209371Smav 732209371Smav INIT_DEBUGOUT("em_attach: end"); 733209371Smav 734209371Smav return (0); 735209371Smav 736209371Smaverr_hw_init: 737209371Smav em_release_hw_control(adapter); 738209371Smav e1000_remove_device(&adapter->hw); 739209371Smav em_dma_free(adapter, &adapter->rxdma); 740209371Smaverr_rx_desc: 741209371Smav em_dma_free(adapter, &adapter->txdma); 742209371Smaverr_tx_desc: 743209371Smaverr_pci: 744209371Smav em_free_intr(adapter); 745209371Smav em_free_pci_resources(adapter); 746209371Smav EM_LOCK_DESTROY(adapter); 747209371Smav 748248170Smav return (error); 749248154Smav} 750209371Smav 751209371Smav/********************************************************************* 752209371Smav * Device removal routine 753247463Smav * 754247463Smav * The detach entry point is called when the driver is being removed. 755247463Smav * This routine stops the adapter and deallocates all the resources 756209371Smav * that were allocated for driver operation. 757209371Smav * 758209371Smav * return 0 on success, positive on failure 759209371Smav *********************************************************************/ 760209371Smav 761209371Smavstatic int 762209371Smavem_detach(device_t dev) 763209371Smav{ 764273598Srpaulo struct adapter *adapter = device_get_softc(dev); 765273598Srpaulo struct ifnet *ifp = adapter->ifp; 766273598Srpaulo 767273598Srpaulo INIT_DEBUGOUT("em_detach: begin"); 768273598Srpaulo 769273598Srpaulo#ifdef DEVICE_POLLING 770273598Srpaulo if (ifp->if_capenable & IFCAP_POLLING) 771273598Srpaulo ether_poll_deregister(ifp); 772273598Srpaulo#endif 773273598Srpaulo 774273598Srpaulo em_disable_intr(adapter); 775273598Srpaulo em_free_intr(adapter); 776273598Srpaulo EM_LOCK(adapter); 777273598Srpaulo adapter->in_detach = 1; 778273598Srpaulo em_stop(adapter); 779273598Srpaulo e1000_phy_hw_reset(&adapter->hw); 780273598Srpaulo 781273598Srpaulo em_release_manageability(adapter); 782273598Srpaulo 783273598Srpaulo if (((adapter->hw.mac.type == e1000_82573) || 784159217Snjl (adapter->hw.mac.type == e1000_ich8lan) || 785159217Snjl (adapter->hw.mac.type == e1000_ich9lan)) && 786159217Snjl e1000_check_mng_mode(&adapter->hw)) 787159217Snjl em_release_hw_control(adapter); 788209371Smav 789159217Snjl if (adapter->wol) { 790159217Snjl E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 791159217Snjl E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 792159217Snjl em_enable_wakeup(dev); 793159217Snjl } 794159217Snjl 795159217Snjl EM_UNLOCK(adapter); 796168010Snjl ether_ifdetach(adapter->ifp); 797209371Smav 798175361Sjhb callout_drain(&adapter->timer); 799212541Smav callout_drain(&adapter->tx_fifo_timer); 800175361Sjhb 801175361Sjhb em_free_pci_resources(adapter); 802175361Sjhb bus_generic_detach(dev); 803175361Sjhb if_free(ifp); 804175361Sjhb 805175361Sjhb e1000_remove_device(&adapter->hw); 806212541Smav em_free_transmit_structures(adapter); 807212541Smav em_free_receive_structures(adapter); 808175361Sjhb 809175361Sjhb /* Free Transmit Descriptor ring */ 810175361Sjhb if (adapter->tx_desc_base) { 811175361Sjhb em_dma_free(adapter, &adapter->txdma); 812175361Sjhb adapter->tx_desc_base = NULL; 813209371Smav } 814168010Snjl 815209371Smav /* Free Receive Descriptor ring */ 816209371Smav if (adapter->rx_desc_base) { 817209371Smav em_dma_free(adapter, &adapter->rxdma); 818168010Snjl adapter->rx_desc_base = NULL; 819168010Snjl } 820168010Snjl 821175361Sjhb EM_LOCK_DESTROY(adapter); 822209371Smav 823209371Smav return (0); 824209371Smav} 825209371Smav 826209440Smav/********************************************************************* 827209371Smav * 828209371Smav * Shutdown entry point 829209371Smav * 830209371Smav **********************************************************************/ 831209371Smav 832209371Smavstatic int 833209371Smavem_shutdown(device_t dev) 834209371Smav{ 835209371Smav return em_suspend(dev); 836209371Smav} 837209371Smav 838209371Smav/* 839209371Smav * Suspend/resume device methods. 840209371Smav */ 841209371Smavstatic int 842212491Smavem_suspend(device_t dev) 843209371Smav{ 844209371Smav struct adapter *adapter = device_get_softc(dev); 845212491Smav 846209371Smav EM_LOCK(adapter); 847209371Smav em_stop(adapter); 848209371Smav 849212491Smav em_release_manageability(adapter); 850209371Smav 851209371Smav if (((adapter->hw.mac.type == e1000_82573) || 852209371Smav (adapter->hw.mac.type == e1000_ich8lan) || 853209371Smav (adapter->hw.mac.type == e1000_ich9lan)) && 854212491Smav e1000_check_mng_mode(&adapter->hw)) 855209371Smav em_release_hw_control(adapter); 856212491Smav 857209371Smav if (adapter->wol) { 858209371Smav E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 859209371Smav E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 860209371Smav em_enable_wakeup(dev); 861168010Snjl } 862168010Snjl 863168010Snjl EM_UNLOCK(adapter); 864159217Snjl 865159217Snjl return bus_generic_suspend(dev); 866209371Smav} 867159217Snjl 868151912Sphkstatic int 869151912Sphkem_resume(device_t dev) 870151912Sphk{ 871151912Sphk struct adapter *adapter = device_get_softc(dev); 872151912Sphk struct ifnet *ifp = adapter->ifp; 873151912Sphk 874151912Sphk EM_LOCK(adapter); 875151912Sphk em_init_locked(adapter); 876175385Sjhb 877151912Sphk /* Get control from any management/hw control */ 878175385Sjhb if (((adapter->hw.mac.type == e1000_82573) || 879151912Sphk (adapter->hw.mac.type == e1000_ich8lan) || 880175385Sjhb (adapter->hw.mac.type == e1000_ich9lan)) && 881151912Sphk e1000_check_mng_mode(&adapter->hw)) 882151912Sphk em_get_hw_control(adapter); 883151912Sphk em_init_manageability(adapter); 884151912Sphk 885151912Sphk if ((ifp->if_flags & IFF_UP) && 886151912Sphk (ifp->if_drv_flags & IFF_DRV_RUNNING)) 887159217Snjl em_start_locked(ifp); 888151912Sphk 889151912Sphk EM_UNLOCK(adapter); 890159217Snjl 891151912Sphk return bus_generic_resume(dev); 892151912Sphk} 893209371Smav 894209371Smav 895209371Smav/********************************************************************* 896209371Smav * Transmit entry point 897209371Smav * 898209371Smav * em_start is called by the stack to initiate a transmit. 899209371Smav * The driver will remain in this routine as long as there are 900209371Smav * packets to transmit and transmit resources are available. 901209371Smav * In case resources are not available stack is notified and 902209371Smav * the packet is requeued. 903209371Smav **********************************************************************/ 904209371Smav 905209371Smavstatic void 906209371Smavem_start_locked(struct ifnet *ifp) 907209371Smav{ 908209371Smav struct adapter *adapter = ifp->if_softc; 909209371Smav struct mbuf *m_head; 910209371Smav 911209371Smav EM_LOCK_ASSERT(adapter); 912209371Smav 913209371Smav if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 914209371Smav IFF_DRV_RUNNING) 915209371Smav return; 916209371Smav if (!adapter->link_active) 917209371Smav return; 918209371Smav 919209371Smav while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 920209371Smav 921209371Smav IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 922209371Smav if (m_head == NULL) 923151912Sphk break; 924209371Smav /* 925209371Smav * Encapsulation can modify our pointer, and or make it 926209371Smav * NULL on failure. In that event, we can't requeue. 927209371Smav * 928209371Smav * We now use a pointer to accomodate legacy and 929209371Smav * advanced transmit functions. 930151912Sphk */ 931209371Smav if (adapter->em_xmit(adapter, &m_head)) { 932209371Smav if (m_head == NULL) 933209371Smav break; 934209371Smav ifp->if_drv_flags |= IFF_DRV_OACTIVE; 935246128Ssbz IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 936151912Sphk break; 937151912Sphk } 938209371Smav 939209371Smav /* Send a copy of the frame to the BPF listener */ 940209371Smav ETHER_BPF_MTAP(ifp, m_head); 941209371Smav 942151912Sphk /* Set timeout in case hardware has problems transmitting. */ 943151912Sphk adapter->watchdog_timer = EM_TX_TIMEOUT; 944209371Smav } 945209371Smav} 946 947static void 948em_start(struct ifnet *ifp) 949{ 950 struct adapter *adapter = ifp->if_softc; 951 952 EM_LOCK(adapter); 953 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 954 em_start_locked(ifp); 955 EM_UNLOCK(adapter); 956} 957 958/********************************************************************* 959 * Ioctl entry point 960 * 961 * em_ioctl is called when the user wants to configure the 962 * interface. 963 * 964 * return 0 on success, positive on failure 965 **********************************************************************/ 966 967static int 968em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 969{ 970 struct adapter *adapter = ifp->if_softc; 971 struct ifreq *ifr = (struct ifreq *)data; 972 struct ifaddr *ifa = (struct ifaddr *)data; 973 int error = 0; 974 975 if (adapter->in_detach) 976 return (error); 977 978 switch (command) { 979 case SIOCSIFADDR: 980 if (ifa->ifa_addr->sa_family == AF_INET) { 981 /* 982 * XXX 983 * Since resetting hardware takes a very long time 984 * and results in link renegotiation we only 985 * initialize the hardware only when it is absolutely 986 * required. 987 */ 988 ifp->if_flags |= IFF_UP; 989 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 990 EM_LOCK(adapter); 991 em_init_locked(adapter); 992 EM_UNLOCK(adapter); 993 } 994 arp_ifinit(ifp, ifa); 995 } else 996 error = ether_ioctl(ifp, command, data); 997 break; 998 case SIOCSIFMTU: 999 { 1000 int max_frame_size; 1001 uint16_t eeprom_data = 0; 1002 1003 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1004 1005 EM_LOCK(adapter); 1006 switch (adapter->hw.mac.type) { 1007 case e1000_82573: 1008 /* 1009 * 82573 only supports jumbo frames 1010 * if ASPM is disabled. 1011 */ 1012 e1000_read_nvm(&adapter->hw, 1013 NVM_INIT_3GIO_3, 1, &eeprom_data); 1014 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1015 max_frame_size = ETHER_MAX_LEN; 1016 break; 1017 } 1018 /* Allow Jumbo frames - fall thru */ 1019 case e1000_82571: 1020 case e1000_82572: 1021 case e1000_ich9lan: 1022 case e1000_82575: 1023 case e1000_80003es2lan: /* Limit Jumbo Frame size */ 1024 max_frame_size = 9234; 1025 break; 1026 /* Adapters that do not support jumbo frames */ 1027 case e1000_82542: 1028 case e1000_ich8lan: 1029 max_frame_size = ETHER_MAX_LEN; 1030 break; 1031 default: 1032 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1033 } 1034 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1035 ETHER_CRC_LEN) { 1036 EM_UNLOCK(adapter); 1037 error = EINVAL; 1038 break; 1039 } 1040 1041 ifp->if_mtu = ifr->ifr_mtu; 1042 adapter->hw.mac.max_frame_size = 1043 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1044 em_init_locked(adapter); 1045 EM_UNLOCK(adapter); 1046 break; 1047 } 1048 case SIOCSIFFLAGS: 1049 IOCTL_DEBUGOUT("ioctl rcv'd:\ 1050 SIOCSIFFLAGS (Set Interface Flags)"); 1051 EM_LOCK(adapter); 1052 if (ifp->if_flags & IFF_UP) { 1053 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1054 if ((ifp->if_flags ^ adapter->if_flags) & 1055 IFF_PROMISC) { 1056 em_disable_promisc(adapter); 1057 em_set_promisc(adapter); 1058 } 1059 } else 1060 em_init_locked(adapter); 1061 } else 1062 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1063 em_stop(adapter); 1064 adapter->if_flags = ifp->if_flags; 1065 EM_UNLOCK(adapter); 1066 break; 1067 case SIOCADDMULTI: 1068 case SIOCDELMULTI: 1069 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 1070 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1071 EM_LOCK(adapter); 1072 em_disable_intr(adapter); 1073 em_set_multi(adapter); 1074 if (adapter->hw.mac.type == e1000_82542 && 1075 adapter->hw.revision_id == E1000_REVISION_2) { 1076 em_initialize_receive_unit(adapter); 1077 } 1078#ifdef DEVICE_POLLING 1079 if (!(ifp->if_capenable & IFCAP_POLLING)) 1080#endif 1081 em_enable_intr(adapter); 1082 EM_UNLOCK(adapter); 1083 } 1084 break; 1085 case SIOCSIFMEDIA: 1086 /* Check SOL/IDER usage */ 1087 EM_LOCK(adapter); 1088 if (e1000_check_reset_block(&adapter->hw)) { 1089 EM_UNLOCK(adapter); 1090 device_printf(adapter->dev, "Media change is" 1091 " blocked due to SOL/IDER session.\n"); 1092 break; 1093 } 1094 EM_UNLOCK(adapter); 1095 case SIOCGIFMEDIA: 1096 IOCTL_DEBUGOUT("ioctl rcv'd: \ 1097 SIOCxIFMEDIA (Get/Set Interface Media)"); 1098 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1099 break; 1100 case SIOCSIFCAP: 1101 { 1102 int mask, reinit; 1103 1104 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 1105 reinit = 0; 1106 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1107#ifdef DEVICE_POLLING 1108 if (mask & IFCAP_POLLING) { 1109 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1110 error = ether_poll_register(em_poll, ifp); 1111 if (error) 1112 return (error); 1113 EM_LOCK(adapter); 1114 em_disable_intr(adapter); 1115 ifp->if_capenable |= IFCAP_POLLING; 1116 EM_UNLOCK(adapter); 1117 } else { 1118 error = ether_poll_deregister(ifp); 1119 /* Enable interrupt even in error case */ 1120 EM_LOCK(adapter); 1121 em_enable_intr(adapter); 1122 ifp->if_capenable &= ~IFCAP_POLLING; 1123 EM_UNLOCK(adapter); 1124 } 1125 } 1126#endif 1127 if (mask & IFCAP_HWCSUM) { 1128 ifp->if_capenable ^= IFCAP_HWCSUM; 1129 reinit = 1; 1130 } 1131 if (mask & IFCAP_TSO4) { 1132 ifp->if_capenable ^= IFCAP_TSO4; 1133 reinit = 1; 1134 } 1135 if (mask & IFCAP_VLAN_HWTAGGING) { 1136 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1137 reinit = 1; 1138 } 1139 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1140 em_init(adapter); 1141 VLAN_CAPABILITIES(ifp); 1142 break; 1143 } 1144 default: 1145 error = ether_ioctl(ifp, command, data); 1146 break; 1147 } 1148 1149 return (error); 1150} 1151 1152/********************************************************************* 1153 * Watchdog timer: 1154 * 1155 * This routine is called from the local timer every second. 1156 * As long as transmit descriptors are being cleaned the value 1157 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 1158 * and we then reset the device. 1159 * 1160 **********************************************************************/ 1161 1162static void 1163em_watchdog(struct adapter *adapter) 1164{ 1165 1166 EM_LOCK_ASSERT(adapter); 1167 1168 /* 1169 ** The timer is set to 5 every time start queues a packet. 1170 ** Then txeof keeps resetting to 5 as long as it cleans at 1171 ** least one descriptor. 1172 ** Finally, anytime all descriptors are clean the timer is 1173 ** set to 0. 1174 */ 1175 if (adapter->watchdog_timer == 0 || --adapter->watchdog_timer) 1176 return; 1177 1178 /* If we are in this routine because of pause frames, then 1179 * don't reset the hardware. 1180 */ 1181 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1182 E1000_STATUS_TXOFF) { 1183 adapter->watchdog_timer = EM_TX_TIMEOUT; 1184 return; 1185 } 1186 1187 if (e1000_check_for_link(&adapter->hw) == 0) 1188 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1189 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1190 adapter->watchdog_events++; 1191 1192 em_init_locked(adapter); 1193} 1194 1195/********************************************************************* 1196 * Init entry point 1197 * 1198 * This routine is used in two ways. It is used by the stack as 1199 * init entry point in network interface structure. It is also used 1200 * by the driver as a hw/sw initialization routine to get to a 1201 * consistent state. 1202 * 1203 * return 0 on success, positive on failure 1204 **********************************************************************/ 1205 1206static void 1207em_init_locked(struct adapter *adapter) 1208{ 1209 struct ifnet *ifp = adapter->ifp; 1210 device_t dev = adapter->dev; 1211 uint32_t pba; 1212 1213 INIT_DEBUGOUT("em_init: begin"); 1214 1215 EM_LOCK_ASSERT(adapter); 1216 1217 em_stop(adapter); 1218 1219 /* 1220 * Packet Buffer Allocation (PBA) 1221 * Writing PBA sets the receive portion of the buffer 1222 * the remainder is used for the transmit buffer. 1223 * 1224 * Devices before the 82547 had a Packet Buffer of 64K. 1225 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1226 * After the 82547 the buffer was reduced to 40K. 1227 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1228 * Note: default does not leave enough room for Jumbo Frame >10k. 1229 */ 1230 switch (adapter->hw.mac.type) { 1231 case e1000_82547: 1232 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1233 if (adapter->hw.mac.max_frame_size > 8192) 1234 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1235 else 1236 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1237 adapter->tx_fifo_head = 0; 1238 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1239 adapter->tx_fifo_size = 1240 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1241 break; 1242 /* Total Packet Buffer on these is 48K */ 1243 case e1000_82571: 1244 case e1000_82572: 1245 case e1000_82575: 1246 case e1000_80003es2lan: 1247 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1248 break; 1249 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1250 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1251 break; 1252 case e1000_ich9lan: 1253#define E1000_PBA_10K 0x000A 1254 pba = E1000_PBA_10K; 1255 break; 1256 case e1000_ich8lan: 1257 pba = E1000_PBA_8K; 1258 break; 1259 default: 1260 /* Devices before 82547 had a Packet Buffer of 64K. */ 1261 if (adapter->hw.mac.max_frame_size > 8192) 1262 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1263 else 1264 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1265 } 1266 1267 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1268 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1269 1270 /* Get the latest mac address, User can use a LAA */ 1271 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr, 1272 ETHER_ADDR_LEN); 1273 1274 /* Put the address into the Receive Address Array */ 1275 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1276 1277 /* 1278 * With 82571 controllers, LAA may be overwritten 1279 * due to controller reset from the other port. 1280 */ 1281 if (adapter->hw.mac.type == e1000_82571) 1282 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1283 1284 /* Initialize the hardware */ 1285 if (em_hardware_init(adapter)) { 1286 device_printf(dev, "Unable to initialize the hardware\n"); 1287 return; 1288 } 1289 em_update_link_status(adapter); 1290 1291 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1292 em_enable_vlans(adapter); 1293 1294 /* Set hardware offload abilities */ 1295 ifp->if_hwassist = 0; 1296 if (adapter->hw.mac.type >= e1000_82543) { 1297 if (ifp->if_capenable & IFCAP_TXCSUM) 1298 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1299 if (ifp->if_capenable & IFCAP_TSO4) 1300 ifp->if_hwassist |= CSUM_TSO; 1301 } 1302 1303 /* Configure for OS presence */ 1304 em_init_manageability(adapter); 1305 1306 /* Prepare transmit descriptors and buffers */ 1307 if (em_setup_transmit_structures(adapter)) { 1308 device_printf(dev, "Could not setup transmit structures\n"); 1309 em_stop(adapter); 1310 return; 1311 } 1312 em_initialize_transmit_unit(adapter); 1313 1314 /* Setup Multicast table */ 1315 em_set_multi(adapter); 1316 1317 /* Prepare receive descriptors and buffers */ 1318 if (em_setup_receive_structures(adapter)) { 1319 device_printf(dev, "Could not setup receive structures\n"); 1320 em_stop(adapter); 1321 return; 1322 } 1323 em_initialize_receive_unit(adapter); 1324 1325 /* Don't lose promiscuous settings */ 1326 em_set_promisc(adapter); 1327 1328 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1329 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1330 1331 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1332 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1333 1334#ifdef DEVICE_POLLING 1335 /* 1336 * Only enable interrupts if we are not polling, make sure 1337 * they are off otherwise. 1338 */ 1339 if (ifp->if_capenable & IFCAP_POLLING) 1340 em_disable_intr(adapter); 1341 else 1342#endif /* DEVICE_POLLING */ 1343 em_enable_intr(adapter); 1344 1345 /* Don't reset the phy next time init gets called */ 1346 adapter->hw.phy.reset_disable = TRUE; 1347} 1348 1349static void 1350em_init(void *arg) 1351{ 1352 struct adapter *adapter = arg; 1353 1354 EM_LOCK(adapter); 1355 em_init_locked(adapter); 1356 EM_UNLOCK(adapter); 1357} 1358 1359 1360#ifdef DEVICE_POLLING 1361/********************************************************************* 1362 * 1363 * Legacy polling routine 1364 * 1365 *********************************************************************/ 1366static void 1367em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1368{ 1369 struct adapter *adapter = ifp->if_softc; 1370 uint32_t reg_icr; 1371 1372 EM_LOCK(adapter); 1373 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1374 EM_UNLOCK(adapter); 1375 return; 1376 } 1377 1378 if (cmd == POLL_AND_CHECK_STATUS) { 1379 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1380 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1381 callout_stop(&adapter->timer); 1382 adapter->hw.mac.get_link_status = 1; 1383 e1000_check_for_link(&adapter->hw); 1384 em_update_link_status(adapter); 1385 callout_reset(&adapter->timer, hz, 1386 em_local_timer, adapter); 1387 } 1388 } 1389 em_rxeof(adapter, count); 1390 em_txeof(adapter); 1391 1392 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1393 em_start_locked(ifp); 1394 EM_UNLOCK(adapter); 1395} 1396 1397/********************************************************************* 1398 * 1399 * Legacy Interrupt Service routine 1400 * 1401 *********************************************************************/ 1402 1403static void 1404em_intr(void *arg) 1405{ 1406 struct adapter *adapter = arg; 1407 struct ifnet *ifp; 1408 uint32_t reg_icr; 1409 1410 EM_LOCK(adapter); 1411 ifp = adapter->ifp; 1412 1413 if (ifp->if_capenable & IFCAP_POLLING) { 1414 EM_UNLOCK(adapter); 1415 return; 1416 } 1417 1418 for (;;) { 1419 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1420 1421 if (adapter->hw.mac.type >= e1000_82571 && 1422 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1423 break; 1424 else if (reg_icr == 0) 1425 break; 1426 1427 /* 1428 * XXX: some laptops trigger several spurious interrupts 1429 * on em(4) when in the resume cycle. The ICR register 1430 * reports all-ones value in this case. Processing such 1431 * interrupts would lead to a freeze. I don't know why. 1432 */ 1433 if (reg_icr == 0xffffffff) 1434 break; 1435 1436 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1437 em_rxeof(adapter, -1); 1438 em_txeof(adapter); 1439 } 1440 1441 /* Link status change */ 1442 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1443 callout_stop(&adapter->timer); 1444 adapter->hw.mac.get_link_status = 1; 1445 e1000_check_for_link(&adapter->hw); 1446 em_update_link_status(adapter); 1447 callout_reset(&adapter->timer, hz, 1448 em_local_timer, adapter); 1449 } 1450 1451 if (reg_icr & E1000_ICR_RXO) 1452 adapter->rx_overruns++; 1453 } 1454 1455 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1456 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1457 em_start_locked(ifp); 1458 EM_UNLOCK(adapter); 1459} 1460 1461#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1462 1463static void 1464em_handle_link(void *context, int pending) 1465{ 1466 struct adapter *adapter = context; 1467 struct ifnet *ifp; 1468 1469 ifp = adapter->ifp; 1470 1471 EM_LOCK(adapter); 1472 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1473 EM_UNLOCK(adapter); 1474 return; 1475 } 1476 1477 callout_stop(&adapter->timer); 1478 adapter->hw.mac.get_link_status = 1; 1479 e1000_check_for_link(&adapter->hw); 1480 em_update_link_status(adapter); 1481 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1482 EM_UNLOCK(adapter); 1483} 1484 1485static void 1486em_handle_rxtx(void *context, int pending) 1487{ 1488 struct adapter *adapter = context; 1489 struct ifnet *ifp; 1490 1491 NET_LOCK_GIANT(); 1492 ifp = adapter->ifp; 1493 1494 /* 1495 * TODO: 1496 * It should be possible to run the tx clean loop without the lock. 1497 */ 1498 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1499 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1500 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1501 EM_LOCK(adapter); 1502 em_txeof(adapter); 1503 1504 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1505 em_start_locked(ifp); 1506 EM_UNLOCK(adapter); 1507 } 1508 1509 em_enable_intr(adapter); 1510 NET_UNLOCK_GIANT(); 1511} 1512 1513/********************************************************************* 1514 * 1515 * Fast Interrupt Service routine 1516 * 1517 *********************************************************************/ 1518static int 1519em_intr_fast(void *arg) 1520{ 1521 struct adapter *adapter = arg; 1522 struct ifnet *ifp; 1523 uint32_t reg_icr; 1524 1525 ifp = adapter->ifp; 1526 1527 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1528 1529 /* Hot eject? */ 1530 if (reg_icr == 0xffffffff) 1531 return (FILTER_STRAY); 1532 1533 /* Definitely not our interrupt. */ 1534 if (reg_icr == 0x0) 1535 return (FILTER_STRAY); 1536 1537 /* 1538 * Starting with the 82571 chip, bit 31 should be used to 1539 * determine whether the interrupt belongs to us. 1540 */ 1541 if (adapter->hw.mac.type >= e1000_82571 && 1542 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1543 return (FILTER_STRAY); 1544 1545 /* 1546 * Mask interrupts until the taskqueue is finished running. This is 1547 * cheap, just assume that it is needed. This also works around the 1548 * MSI message reordering errata on certain systems. 1549 */ 1550 em_disable_intr(adapter); 1551 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1552 1553 /* Link status change */ 1554 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1555 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1556 1557 if (reg_icr & E1000_ICR_RXO) 1558 adapter->rx_overruns++; 1559 return (FILTER_HANDLED); 1560} 1561#endif /* ! DEVICE_POLLING */ 1562 1563/********************************************************************* 1564 * 1565 * Media Ioctl callback 1566 * 1567 * This routine is called whenever the user queries the status of 1568 * the interface using ifconfig. 1569 * 1570 **********************************************************************/ 1571static void 1572em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1573{ 1574 struct adapter *adapter = ifp->if_softc; 1575 u_char fiber_type = IFM_1000_SX; 1576 1577 INIT_DEBUGOUT("em_media_status: begin"); 1578 1579 EM_LOCK(adapter); 1580 e1000_check_for_link(&adapter->hw); 1581 em_update_link_status(adapter); 1582 1583 ifmr->ifm_status = IFM_AVALID; 1584 ifmr->ifm_active = IFM_ETHER; 1585 1586 if (!adapter->link_active) { 1587 EM_UNLOCK(adapter); 1588 return; 1589 } 1590 1591 ifmr->ifm_status |= IFM_ACTIVE; 1592 1593 if ((adapter->hw.media_type == e1000_media_type_fiber) || 1594 (adapter->hw.media_type == e1000_media_type_internal_serdes)) { 1595 if (adapter->hw.mac.type == e1000_82545) 1596 fiber_type = IFM_1000_LX; 1597 ifmr->ifm_active |= fiber_type | IFM_FDX; 1598 } else { 1599 switch (adapter->link_speed) { 1600 case 10: 1601 ifmr->ifm_active |= IFM_10_T; 1602 break; 1603 case 100: 1604 ifmr->ifm_active |= IFM_100_TX; 1605 break; 1606 case 1000: 1607 ifmr->ifm_active |= IFM_1000_T; 1608 break; 1609 } 1610 if (adapter->link_duplex == FULL_DUPLEX) 1611 ifmr->ifm_active |= IFM_FDX; 1612 else 1613 ifmr->ifm_active |= IFM_HDX; 1614 } 1615 EM_UNLOCK(adapter); 1616} 1617 1618/********************************************************************* 1619 * 1620 * Media Ioctl callback 1621 * 1622 * This routine is called when the user changes speed/duplex using 1623 * media/mediopt option with ifconfig. 1624 * 1625 **********************************************************************/ 1626static int 1627em_media_change(struct ifnet *ifp) 1628{ 1629 struct adapter *adapter = ifp->if_softc; 1630 struct ifmedia *ifm = &adapter->media; 1631 1632 INIT_DEBUGOUT("em_media_change: begin"); 1633 1634 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1635 return (EINVAL); 1636 1637 EM_LOCK(adapter); 1638 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1639 case IFM_AUTO: 1640 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1641 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1642 break; 1643 case IFM_1000_LX: 1644 case IFM_1000_SX: 1645 case IFM_1000_T: 1646 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1647 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1648 break; 1649 case IFM_100_TX: 1650 adapter->hw.mac.autoneg = FALSE; 1651 adapter->hw.phy.autoneg_advertised = 0; 1652 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1653 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1654 else 1655 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1656 break; 1657 case IFM_10_T: 1658 adapter->hw.mac.autoneg = FALSE; 1659 adapter->hw.phy.autoneg_advertised = 0; 1660 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1661 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1662 else 1663 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1664 break; 1665 default: 1666 device_printf(adapter->dev, "Unsupported media type\n"); 1667 } 1668 1669 /* As the speed/duplex settings my have changed we need to 1670 * reset the PHY. 1671 */ 1672 adapter->hw.phy.reset_disable = FALSE; 1673 1674 em_init_locked(adapter); 1675 EM_UNLOCK(adapter); 1676 1677 return (0); 1678} 1679 1680/********************************************************************* 1681 * 1682 * This routine maps the mbufs to tx descriptors. 1683 * 1684 * return 0 on success, positive on failure 1685 **********************************************************************/ 1686 1687static int 1688em_encap(struct adapter *adapter, struct mbuf **m_headp) 1689{ 1690 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1691 bus_dmamap_t map; 1692 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1693 struct e1000_tx_desc *ctxd = NULL; 1694 struct mbuf *m_head; 1695 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1696 int nsegs, i, j, first, last = 0; 1697 int error, do_tso, tso_desc = 0; 1698 1699 m_head = *m_headp; 1700 txd_upper = txd_lower = txd_used = txd_saved = 0; 1701 1702 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 1703 1704 /* 1705 * Force a cleanup if number of TX descriptors 1706 * available hits the threshold 1707 */ 1708 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1709 em_txeof(adapter); 1710 /* Now do we at least have a minimal? */ 1711 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1712 adapter->no_tx_desc_avail1++; 1713 return (ENOBUFS); 1714 } 1715 } 1716 1717 1718 /* 1719 * TSO workaround: 1720 * If an mbuf is only header we need 1721 * to pull 4 bytes of data into it. 1722 */ 1723 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 1724 m_head = m_pullup(m_head, M_TSO_LEN + 4); 1725 *m_headp = m_head; 1726 if (m_head == NULL) 1727 return (ENOBUFS); 1728 } 1729 1730 /* 1731 * Map the packet for DMA 1732 * 1733 * Capture the first descriptor index, 1734 * this descriptor will have the index 1735 * of the EOP which is the only one that 1736 * now gets a DONE bit writeback. 1737 */ 1738 first = adapter->next_avail_tx_desc; 1739 tx_buffer = &adapter->tx_buffer_area[first]; 1740 tx_buffer_mapped = tx_buffer; 1741 map = tx_buffer->map; 1742 1743 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1744 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1745 1746 /* 1747 * There are two types of errors we can (try) to handle: 1748 * - EFBIG means the mbuf chain was too long and bus_dma ran 1749 * out of segments. Defragment the mbuf chain and try again. 1750 * - ENOMEM means bus_dma could not obtain enough bounce buffers 1751 * at this point in time. Defer sending and try again later. 1752 * All other errors, in particular EINVAL, are fatal and prevent the 1753 * mbuf chain from ever going through. Drop it and report error. 1754 */ 1755 if (error == EFBIG) { 1756 struct mbuf *m; 1757 1758 m = m_defrag(*m_headp, M_DONTWAIT); 1759 if (m == NULL) { 1760 adapter->mbuf_alloc_failed++; 1761 m_freem(*m_headp); 1762 *m_headp = NULL; 1763 return (ENOBUFS); 1764 } 1765 *m_headp = m; 1766 1767 /* Try it again */ 1768 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1769 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1770 1771 if (error == ENOMEM) { 1772 adapter->no_tx_dma_setup++; 1773 return (error); 1774 } else if (error != 0) { 1775 adapter->no_tx_dma_setup++; 1776 m_freem(*m_headp); 1777 *m_headp = NULL; 1778 return (error); 1779 } 1780 } else if (error == ENOMEM) { 1781 adapter->no_tx_dma_setup++; 1782 return (error); 1783 } else if (error != 0) { 1784 adapter->no_tx_dma_setup++; 1785 m_freem(*m_headp); 1786 *m_headp = NULL; 1787 return (error); 1788 } 1789 1790 /* 1791 * TSO Hardware workaround, if this packet is not 1792 * TSO, and is only a single descriptor long, and 1793 * it follows a TSO burst, then we need to add a 1794 * sentinel descriptor to prevent premature writeback. 1795 */ 1796 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 1797 if (nsegs == 1) 1798 tso_desc = TRUE; 1799 adapter->tx_tso = FALSE; 1800 } 1801 1802 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 1803 adapter->no_tx_desc_avail2++; 1804 bus_dmamap_unload(adapter->txtag, map); 1805 return (ENOBUFS); 1806 } 1807 m_head = *m_headp; 1808 1809 /* Do hardware assists */ 1810 if (em_tso_setup(adapter, m_head, &txd_upper, &txd_lower)) 1811 /* we need to make a final sentinel transmit desc */ 1812 tso_desc = TRUE; 1813 else if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) 1814 em_transmit_checksum_setup(adapter, m_head, 1815 &txd_upper, &txd_lower); 1816 1817 i = adapter->next_avail_tx_desc; 1818 if (adapter->pcix_82544) 1819 txd_saved = i; 1820 1821 /* Set up our transmit descriptors */ 1822 for (j = 0; j < nsegs; j++) { 1823 bus_size_t seg_len; 1824 bus_addr_t seg_addr; 1825 /* If adapter is 82544 and on PCIX bus */ 1826 if(adapter->pcix_82544) { 1827 DESC_ARRAY desc_array; 1828 uint32_t array_elements, counter; 1829 /* 1830 * Check the Address and Length combination and 1831 * split the data accordingly 1832 */ 1833 array_elements = em_fill_descriptors(segs[j].ds_addr, 1834 segs[j].ds_len, &desc_array); 1835 for (counter = 0; counter < array_elements; counter++) { 1836 if (txd_used == adapter->num_tx_desc_avail) { 1837 adapter->next_avail_tx_desc = txd_saved; 1838 adapter->no_tx_desc_avail2++; 1839 bus_dmamap_unload(adapter->txtag, map); 1840 return (ENOBUFS); 1841 } 1842 tx_buffer = &adapter->tx_buffer_area[i]; 1843 ctxd = &adapter->tx_desc_base[i]; 1844 ctxd->buffer_addr = htole64( 1845 desc_array.descriptor[counter].address); 1846 ctxd->lower.data = htole32( 1847 (adapter->txd_cmd | txd_lower | (uint16_t) 1848 desc_array.descriptor[counter].length)); 1849 ctxd->upper.data = 1850 htole32((txd_upper)); 1851 last = i; 1852 if (++i == adapter->num_tx_desc) 1853 i = 0; 1854 tx_buffer->m_head = NULL; 1855 tx_buffer->next_eop = -1; 1856 txd_used++; 1857 } 1858 } else { 1859 tx_buffer = &adapter->tx_buffer_area[i]; 1860 ctxd = &adapter->tx_desc_base[i]; 1861 seg_addr = segs[j].ds_addr; 1862 seg_len = segs[j].ds_len; 1863 /* 1864 ** TSO Workaround: 1865 ** If this is the last descriptor, we want to 1866 ** split it so we have a small final sentinel 1867 */ 1868 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 1869 seg_len -= 4; 1870 ctxd->buffer_addr = htole64(seg_addr); 1871 ctxd->lower.data = htole32( 1872 adapter->txd_cmd | txd_lower | seg_len); 1873 ctxd->upper.data = 1874 htole32(txd_upper); 1875 if (++i == adapter->num_tx_desc) 1876 i = 0; 1877 /* Now make the sentinel */ 1878 ++txd_used; /* using an extra txd */ 1879 ctxd = &adapter->tx_desc_base[i]; 1880 tx_buffer = &adapter->tx_buffer_area[i]; 1881 ctxd->buffer_addr = 1882 htole64(seg_addr + seg_len); 1883 ctxd->lower.data = htole32( 1884 adapter->txd_cmd | txd_lower | 4); 1885 ctxd->upper.data = 1886 htole32(txd_upper); 1887 last = i; 1888 if (++i == adapter->num_tx_desc) 1889 i = 0; 1890 } else { 1891 ctxd->buffer_addr = htole64(seg_addr); 1892 ctxd->lower.data = htole32( 1893 adapter->txd_cmd | txd_lower | seg_len); 1894 ctxd->upper.data = 1895 htole32(txd_upper); 1896 last = i; 1897 if (++i == adapter->num_tx_desc) 1898 i = 0; 1899 } 1900 tx_buffer->m_head = NULL; 1901 tx_buffer->next_eop = -1; 1902 } 1903 } 1904 1905 adapter->next_avail_tx_desc = i; 1906 if (adapter->pcix_82544) 1907 adapter->num_tx_desc_avail -= txd_used; 1908 else { 1909 adapter->num_tx_desc_avail -= nsegs; 1910 if (tso_desc) /* TSO used an extra for sentinel */ 1911 adapter->num_tx_desc_avail -= txd_used; 1912 } 1913 1914 if (m_head->m_flags & M_VLANTAG) { 1915 /* Set the vlan id. */ 1916 ctxd->upper.fields.special = 1917 htole16(m_head->m_pkthdr.ether_vtag); 1918 /* Tell hardware to add tag */ 1919 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1920 } 1921 1922 tx_buffer->m_head = m_head; 1923 tx_buffer_mapped->map = tx_buffer->map; 1924 tx_buffer->map = map; 1925 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1926 1927 /* 1928 * Last Descriptor of Packet 1929 * needs End Of Packet (EOP) 1930 * and Report Status (RS) 1931 */ 1932 ctxd->lower.data |= 1933 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1934 /* 1935 * Keep track in the first buffer which 1936 * descriptor will be written back 1937 */ 1938 tx_buffer = &adapter->tx_buffer_area[first]; 1939 tx_buffer->next_eop = last; 1940 1941 /* 1942 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 1943 * that this frame is available to transmit. 1944 */ 1945 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1947 if (adapter->hw.mac.type == e1000_82547 && 1948 adapter->link_duplex == HALF_DUPLEX) 1949 em_82547_move_tail(adapter); 1950 else { 1951 E1000_WRITE_REG(&adapter->hw, E1000_TDT, i); 1952 if (adapter->hw.mac.type == e1000_82547) 1953 em_82547_update_fifo_head(adapter, 1954 m_head->m_pkthdr.len); 1955 } 1956 1957 return (0); 1958} 1959 1960/********************************************************************* 1961 * 1962 * This routine maps the mbufs to Advanced TX descriptors. 1963 * used by the 82575 adapter. It also needs no workarounds. 1964 * 1965 **********************************************************************/ 1966 1967static int 1968em_adv_encap(struct adapter *adapter, struct mbuf **m_headp) 1969{ 1970 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1971 bus_dmamap_t map; 1972 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1973 union e1000_adv_tx_desc *txd = NULL; 1974 struct mbuf *m_head; 1975 u32 olinfo_status = 0, cmd_type_len = 0; 1976 u32 paylen = 0; 1977 int nsegs, i, j, error, first, last = 0; 1978 1979 m_head = *m_headp; 1980 1981 1982 /* Set basic descriptor constants */ 1983 cmd_type_len |= E1000_ADVTXD_DTYP_DATA; 1984 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT; 1985 1986 /* 1987 * Force a cleanup if number of TX descriptors 1988 * available hits the threshold 1989 */ 1990 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1991 em_txeof(adapter); 1992 /* Now do we at least have a minimal? */ 1993 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1994 adapter->no_tx_desc_avail1++; 1995 return (ENOBUFS); 1996 } 1997 } 1998 1999 /* 2000 * Map the packet for DMA. 2001 * 2002 * Capture the first descriptor index, 2003 * this descriptor will have the index 2004 * of the EOP which is the only one that 2005 * now gets a DONE bit writeback. 2006 */ 2007 first = adapter->next_avail_tx_desc; 2008 tx_buffer = &adapter->tx_buffer_area[first]; 2009 tx_buffer_mapped = tx_buffer; 2010 map = tx_buffer->map; 2011 2012 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2013 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2014 2015 if (error == EFBIG) { 2016 struct mbuf *m; 2017 2018 m = m_defrag(*m_headp, M_DONTWAIT); 2019 if (m == NULL) { 2020 adapter->mbuf_alloc_failed++; 2021 m_freem(*m_headp); 2022 *m_headp = NULL; 2023 return (ENOBUFS); 2024 } 2025 *m_headp = m; 2026 2027 /* Try it again */ 2028 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2029 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2030 2031 if (error == ENOMEM) { 2032 adapter->no_tx_dma_setup++; 2033 return (error); 2034 } else if (error != 0) { 2035 adapter->no_tx_dma_setup++; 2036 m_freem(*m_headp); 2037 *m_headp = NULL; 2038 return (error); 2039 } 2040 } else if (error == ENOMEM) { 2041 adapter->no_tx_dma_setup++; 2042 return (error); 2043 } else if (error != 0) { 2044 adapter->no_tx_dma_setup++; 2045 m_freem(*m_headp); 2046 *m_headp = NULL; 2047 return (error); 2048 } 2049 2050 /* Check again to be sure we have enough descriptors */ 2051 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 2052 adapter->no_tx_desc_avail2++; 2053 bus_dmamap_unload(adapter->txtag, map); 2054 return (ENOBUFS); 2055 } 2056 m_head = *m_headp; 2057 2058 /* 2059 * Set up the context descriptor: 2060 * used when any hardware offload is done. 2061 * This includes CSUM, VLAN, and TSO. It 2062 * will use the first descriptor. 2063 */ 2064 /* First try TSO */ 2065 if (em_tso_adv_setup(adapter, m_head, &paylen)) { 2066 cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 2067 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 2068 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2069 olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 2070 } else if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) { 2071 if (em_tx_adv_ctx_setup(adapter, m_head)) 2072 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2073 } 2074 2075 /* Set up our transmit descriptors */ 2076 i = adapter->next_avail_tx_desc; 2077 for (j = 0; j < nsegs; j++) { 2078 bus_size_t seg_len; 2079 bus_addr_t seg_addr; 2080 2081 tx_buffer = &adapter->tx_buffer_area[i]; 2082 txd = (union e1000_adv_tx_desc *)&adapter->tx_desc_base[i]; 2083 seg_addr = segs[j].ds_addr; 2084 seg_len = segs[j].ds_len; 2085 2086 txd->read.buffer_addr = htole64(seg_addr); 2087 txd->read.cmd_type_len = htole32( 2088 adapter->txd_cmd | cmd_type_len | seg_len); 2089 txd->read.olinfo_status = htole32(olinfo_status); 2090 last = i; 2091 if (++i == adapter->num_tx_desc) 2092 i = 0; 2093 tx_buffer->m_head = NULL; 2094 tx_buffer->next_eop = -1; 2095 } 2096 2097 adapter->next_avail_tx_desc = i; 2098 adapter->num_tx_desc_avail -= nsegs; 2099 2100 tx_buffer->m_head = m_head; 2101 tx_buffer_mapped->map = tx_buffer->map; 2102 tx_buffer->map = map; 2103 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2104 2105 /* 2106 * Last Descriptor of Packet 2107 * needs End Of Packet (EOP) 2108 * and Report Status (RS) 2109 */ 2110 txd->read.cmd_type_len |= 2111 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2112 /* 2113 * Keep track in the first buffer which 2114 * descriptor will be written back 2115 */ 2116 tx_buffer = &adapter->tx_buffer_area[first]; 2117 tx_buffer->next_eop = last; 2118 2119 /* 2120 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2121 * that this frame is available to transmit. 2122 */ 2123 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2124 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2125 E1000_WRITE_REG(&adapter->hw, E1000_TDT, i); 2126 2127 return (0); 2128 2129} 2130 2131/********************************************************************* 2132 * 2133 * 82547 workaround to avoid controller hang in half-duplex environment. 2134 * The workaround is to avoid queuing a large packet that would span 2135 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 2136 * in this case. We do that only when FIFO is quiescent. 2137 * 2138 **********************************************************************/ 2139static void 2140em_82547_move_tail(void *arg) 2141{ 2142 struct adapter *adapter = arg; 2143 uint16_t hw_tdt; 2144 uint16_t sw_tdt; 2145 struct e1000_tx_desc *tx_desc; 2146 uint16_t length = 0; 2147 boolean_t eop = 0; 2148 2149 EM_LOCK_ASSERT(adapter); 2150 2151 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT); 2152 sw_tdt = adapter->next_avail_tx_desc; 2153 2154 while (hw_tdt != sw_tdt) { 2155 tx_desc = &adapter->tx_desc_base[hw_tdt]; 2156 length += tx_desc->lower.flags.length; 2157 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2158 if (++hw_tdt == adapter->num_tx_desc) 2159 hw_tdt = 0; 2160 2161 if (eop) { 2162 if (em_82547_fifo_workaround(adapter, length)) { 2163 adapter->tx_fifo_wrk_cnt++; 2164 callout_reset(&adapter->tx_fifo_timer, 1, 2165 em_82547_move_tail, adapter); 2166 break; 2167 } 2168 E1000_WRITE_REG(&adapter->hw, E1000_TDT, hw_tdt); 2169 em_82547_update_fifo_head(adapter, length); 2170 length = 0; 2171 } 2172 } 2173} 2174 2175static int 2176em_82547_fifo_workaround(struct adapter *adapter, int len) 2177{ 2178 int fifo_space, fifo_pkt_len; 2179 2180 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2181 2182 if (adapter->link_duplex == HALF_DUPLEX) { 2183 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2184 2185 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2186 if (em_82547_tx_fifo_reset(adapter)) 2187 return (0); 2188 else 2189 return (1); 2190 } 2191 } 2192 2193 return (0); 2194} 2195 2196static void 2197em_82547_update_fifo_head(struct adapter *adapter, int len) 2198{ 2199 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2200 2201 /* tx_fifo_head is always 16 byte aligned */ 2202 adapter->tx_fifo_head += fifo_pkt_len; 2203 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 2204 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2205 } 2206} 2207 2208 2209static int 2210em_82547_tx_fifo_reset(struct adapter *adapter) 2211{ 2212 uint32_t tctl; 2213 2214 if ((E1000_READ_REG(&adapter->hw, E1000_TDT) == 2215 E1000_READ_REG(&adapter->hw, E1000_TDH)) && 2216 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2217 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2218 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2219 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2220 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2221 /* Disable TX unit */ 2222 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2223 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2224 tctl & ~E1000_TCTL_EN); 2225 2226 /* Reset FIFO pointers */ 2227 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2228 adapter->tx_head_addr); 2229 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2230 adapter->tx_head_addr); 2231 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2232 adapter->tx_head_addr); 2233 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2234 adapter->tx_head_addr); 2235 2236 /* Re-enable TX unit */ 2237 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2238 E1000_WRITE_FLUSH(&adapter->hw); 2239 2240 adapter->tx_fifo_head = 0; 2241 adapter->tx_fifo_reset_cnt++; 2242 2243 return (TRUE); 2244 } 2245 else { 2246 return (FALSE); 2247 } 2248} 2249 2250static void 2251em_set_promisc(struct adapter *adapter) 2252{ 2253 struct ifnet *ifp = adapter->ifp; 2254 uint32_t reg_rctl; 2255 2256 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2257 2258 if (ifp->if_flags & IFF_PROMISC) { 2259 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2260 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2261 } else if (ifp->if_flags & IFF_ALLMULTI) { 2262 reg_rctl |= E1000_RCTL_MPE; 2263 reg_rctl &= ~E1000_RCTL_UPE; 2264 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2265 } 2266} 2267 2268static void 2269em_disable_promisc(struct adapter *adapter) 2270{ 2271 uint32_t reg_rctl; 2272 2273 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2274 2275 reg_rctl &= (~E1000_RCTL_UPE); 2276 reg_rctl &= (~E1000_RCTL_MPE); 2277 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2278} 2279 2280 2281/********************************************************************* 2282 * Multicast Update 2283 * 2284 * This routine is called whenever multicast address list is updated. 2285 * 2286 **********************************************************************/ 2287 2288static void 2289em_set_multi(struct adapter *adapter) 2290{ 2291 struct ifnet *ifp = adapter->ifp; 2292 struct ifmultiaddr *ifma; 2293 uint32_t reg_rctl = 0; 2294 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 2295 int mcnt = 0; 2296 2297 IOCTL_DEBUGOUT("em_set_multi: begin"); 2298 2299 if (adapter->hw.mac.type == e1000_82542 && 2300 adapter->hw.revision_id == E1000_REVISION_2) { 2301 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2302 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2303 e1000_pci_clear_mwi(&adapter->hw); 2304 reg_rctl |= E1000_RCTL_RST; 2305 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2306 msec_delay(5); 2307 } 2308 2309 IF_ADDR_LOCK(ifp); 2310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2311 if (ifma->ifma_addr->sa_family != AF_LINK) 2312 continue; 2313 2314 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2315 break; 2316 2317 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2318 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN); 2319 mcnt++; 2320 } 2321 IF_ADDR_UNLOCK(ifp); 2322 2323 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2324 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2325 reg_rctl |= E1000_RCTL_MPE; 2326 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2327 } else 2328 e1000_mc_addr_list_update(&adapter->hw, mta, 2329 mcnt, 1, adapter->hw.mac.rar_entry_count); 2330 2331 if (adapter->hw.mac.type == e1000_82542 && 2332 adapter->hw.revision_id == E1000_REVISION_2) { 2333 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2334 reg_rctl &= ~E1000_RCTL_RST; 2335 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2336 msec_delay(5); 2337 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2338 e1000_pci_set_mwi(&adapter->hw); 2339 } 2340} 2341 2342 2343/********************************************************************* 2344 * Timer routine 2345 * 2346 * This routine checks for link status and updates statistics. 2347 * 2348 **********************************************************************/ 2349 2350static void 2351em_local_timer(void *arg) 2352{ 2353 struct adapter *adapter = arg; 2354 struct ifnet *ifp = adapter->ifp; 2355 2356 EM_LOCK_ASSERT(adapter); 2357 2358 e1000_check_for_link(&adapter->hw); 2359 em_update_link_status(adapter); 2360 em_update_stats_counters(adapter); 2361 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2362 em_print_hw_stats(adapter); 2363 em_smartspeed(adapter); 2364 /* 2365 * Each second we check the watchdog to 2366 * protect against hardware hangs. 2367 */ 2368 em_watchdog(adapter); 2369 2370 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2371 2372} 2373 2374static void 2375em_update_link_status(struct adapter *adapter) 2376{ 2377 struct ifnet *ifp = adapter->ifp; 2378 device_t dev = adapter->dev; 2379 2380 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 2381 E1000_STATUS_LU) { 2382 if (adapter->link_active == 0) { 2383 e1000_get_speed_and_duplex(&adapter->hw, 2384 &adapter->link_speed, &adapter->link_duplex); 2385 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2386 if ((adapter->link_speed != SPEED_1000) && 2387 ((adapter->hw.mac.type == e1000_82571) || 2388 (adapter->hw.mac.type == e1000_82572))) { 2389 int tarc0; 2390 2391 tarc0 = E1000_READ_REG(&adapter->hw, 2392 E1000_TARC0); 2393 tarc0 &= ~SPEED_MODE_BIT; 2394 E1000_WRITE_REG(&adapter->hw, 2395 E1000_TARC0, tarc0); 2396 } 2397 if (bootverbose) 2398 device_printf(dev, "Link is up %d Mbps %s\n", 2399 adapter->link_speed, 2400 ((adapter->link_duplex == FULL_DUPLEX) ? 2401 "Full Duplex" : "Half Duplex")); 2402 adapter->link_active = 1; 2403 adapter->smartspeed = 0; 2404 ifp->if_baudrate = adapter->link_speed * 1000000; 2405 if_link_state_change(ifp, LINK_STATE_UP); 2406 } 2407 } else { 2408 if (adapter->link_active == 1) { 2409 ifp->if_baudrate = adapter->link_speed = 0; 2410 adapter->link_duplex = 0; 2411 if (bootverbose) 2412 device_printf(dev, "Link is Down\n"); 2413 adapter->link_active = 0; 2414 if_link_state_change(ifp, LINK_STATE_DOWN); 2415 } 2416 } 2417} 2418 2419/********************************************************************* 2420 * 2421 * This routine disables all traffic on the adapter by issuing a 2422 * global reset on the MAC and deallocates TX/RX buffers. 2423 * 2424 **********************************************************************/ 2425 2426static void 2427em_stop(void *arg) 2428{ 2429 struct adapter *adapter = arg; 2430 struct ifnet *ifp = adapter->ifp; 2431 2432 EM_LOCK_ASSERT(adapter); 2433 2434 INIT_DEBUGOUT("em_stop: begin"); 2435 2436 em_disable_intr(adapter); 2437 callout_stop(&adapter->timer); 2438 callout_stop(&adapter->tx_fifo_timer); 2439 em_free_transmit_structures(adapter); 2440 em_free_receive_structures(adapter); 2441 2442 /* Tell the stack that the interface is no longer active */ 2443 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2444 2445 e1000_reset_hw(&adapter->hw); 2446 if (adapter->hw.mac.type >= e1000_82544) 2447 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2448} 2449 2450 2451/********************************************************************* 2452 * 2453 * Determine hardware revision. 2454 * 2455 **********************************************************************/ 2456static void 2457em_identify_hardware(struct adapter *adapter) 2458{ 2459 device_t dev = adapter->dev; 2460 2461 /* Make sure our PCI config space has the necessary stuff set */ 2462 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2463 if ((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 2464 (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN)) { 2465 device_printf(dev, "Memory Access and/or Bus Master bits " 2466 "were not set!\n"); 2467 adapter->hw.bus.pci_cmd_word |= 2468 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2469 pci_write_config(dev, PCIR_COMMAND, 2470 adapter->hw.bus.pci_cmd_word, 2); 2471 } 2472 2473 /* Save off the information about this board */ 2474 adapter->hw.vendor_id = pci_get_vendor(dev); 2475 adapter->hw.device_id = pci_get_device(dev); 2476 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2477 adapter->hw.subsystem_vendor_id = 2478 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2479 adapter->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2480 2481 /* Do Shared Code Init and Setup */ 2482 if (e1000_set_mac_type(&adapter->hw)) { 2483 device_printf(dev, "Setup init failure\n"); 2484 return; 2485 } 2486} 2487 2488static int 2489em_allocate_pci_resources(struct adapter *adapter) 2490{ 2491 device_t dev = adapter->dev; 2492 int val, rid; 2493 2494 rid = PCIR_BAR(0); 2495 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2496 &rid, RF_ACTIVE); 2497 if (adapter->res_memory == NULL) { 2498 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2499 return (ENXIO); 2500 } 2501 adapter->osdep.mem_bus_space_tag = 2502 rman_get_bustag(adapter->res_memory); 2503 adapter->osdep.mem_bus_space_handle = 2504 rman_get_bushandle(adapter->res_memory); 2505 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2506 2507 /* Only older adapters use IO mapping */ 2508 if ((adapter->hw.mac.type > e1000_82542) && 2509 (adapter->hw.mac.type < e1000_82571)) { 2510 /* Figure our where our IO BAR is ? */ 2511 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2512 val = pci_read_config(dev, rid, 4); 2513 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2514 adapter->io_rid = rid; 2515 break; 2516 } 2517 rid += 4; 2518 /* check for 64bit BAR */ 2519 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2520 rid += 4; 2521 } 2522 if (rid >= PCIR_CIS) { 2523 device_printf(dev, "Unable to locate IO BAR\n"); 2524 return (ENXIO); 2525 } 2526 adapter->res_ioport = bus_alloc_resource_any(dev, 2527 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2528 if (adapter->res_ioport == NULL) { 2529 device_printf(dev, "Unable to allocate bus resource: " 2530 "ioport\n"); 2531 return (ENXIO); 2532 } 2533 adapter->hw.io_base = 0; 2534 adapter->osdep.io_bus_space_tag = 2535 rman_get_bustag(adapter->res_ioport); 2536 adapter->osdep.io_bus_space_handle = 2537 rman_get_bushandle(adapter->res_ioport); 2538 } 2539 2540 /* 2541 * Setup MSI/X or MSI if PCI Express 2542 * only the latest can use MSI/X and 2543 * real support for it is forthcoming 2544 */ 2545 adapter->msi = 0; /* Set defaults */ 2546 rid = 0x0; 2547 if (adapter->hw.mac.type >= e1000_82575) { 2548 /* 2549 * Setup MSI/X 2550 */ 2551 rid = PCIR_BAR(EM_MSIX_BAR); 2552 adapter->msix_mem = bus_alloc_resource_any(dev, 2553 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2554 if (!adapter->msix_mem) { 2555 device_printf(dev,"Unable to map MSIX table \n"); 2556 return (ENXIO); 2557 } 2558 /* 2559 * Eventually this may be used 2560 * for Multiqueue, for now we will 2561 * just use one vector. 2562 * 2563 * val = pci_msix_count(dev); 2564 */ 2565 val = 1; 2566 if ((val) && pci_alloc_msix(dev, &val) == 0) { 2567 rid = 1; 2568 adapter->msi = 1; 2569 } 2570 } else if (adapter->hw.mac.type > e1000_82571) { 2571 val = pci_msi_count(dev); 2572 if (val == 1 && pci_alloc_msi(dev, &val) == 0) { 2573 rid = 1; 2574 adapter->msi = 1; 2575 } 2576 } 2577 adapter->res_interrupt = bus_alloc_resource_any(dev, 2578 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2579 if (adapter->res_interrupt == NULL) { 2580 device_printf(dev, "Unable to allocate bus resource: " 2581 "interrupt\n"); 2582 return (ENXIO); 2583 } 2584 2585 adapter->hw.back = &adapter->osdep; 2586 2587 return (0); 2588} 2589 2590/********************************************************************* 2591 * 2592 * Setup the appropriate Interrupt handlers. 2593 * 2594 **********************************************************************/ 2595int 2596em_allocate_intr(struct adapter *adapter) 2597{ 2598 device_t dev = adapter->dev; 2599 int error; 2600 2601 /* Manually turn off all interrupts */ 2602 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2603 2604#ifdef DEVICE_POLLING 2605 /* We do Legacy setup */ 2606 if (adapter->int_handler_tag == NULL && 2607 (error = bus_setup_intr(dev, adapter->res_interrupt, 2608 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_intr, adapter, 2609 &adapter->int_handler_tag)) != 0) { 2610 device_printf(dev, "Failed to register interrupt handler"); 2611 return (error); 2612 } 2613 2614#else 2615 /* 2616 * Try allocating a fast interrupt and the associated deferred 2617 * processing contexts. 2618 */ 2619 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2620 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2621 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2622 taskqueue_thread_enqueue, &adapter->tq); 2623 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2624 device_get_nameunit(adapter->dev)); 2625 if ((error = bus_setup_intr(dev, adapter->res_interrupt, 2626 INTR_TYPE_NET, em_intr_fast, NULL, adapter, 2627 &adapter->int_handler_tag)) != 0) { 2628 device_printf(dev, "Failed to register fast interrupt " 2629 "handler: %d\n", error); 2630 taskqueue_free(adapter->tq); 2631 adapter->tq = NULL; 2632 return (error); 2633 } 2634#endif 2635 2636 em_enable_intr(adapter); 2637 return (0); 2638} 2639 2640static void 2641em_free_intr(struct adapter *adapter) 2642{ 2643 device_t dev = adapter->dev; 2644 2645 if (adapter->res_interrupt != NULL) { 2646 bus_teardown_intr(dev, adapter->res_interrupt, 2647 adapter->int_handler_tag); 2648 adapter->int_handler_tag = NULL; 2649 } 2650 if (adapter->tq != NULL) { 2651 taskqueue_drain(adapter->tq, &adapter->rxtx_task); 2652 taskqueue_drain(taskqueue_fast, &adapter->link_task); 2653 taskqueue_free(adapter->tq); 2654 adapter->tq = NULL; 2655 } 2656} 2657 2658static void 2659em_free_pci_resources(struct adapter *adapter) 2660{ 2661 device_t dev = adapter->dev; 2662 2663 if (adapter->res_interrupt != NULL) 2664 bus_release_resource(dev, SYS_RES_IRQ, 2665 adapter->msi ? 1 : 0, adapter->res_interrupt); 2666 2667 if (adapter->msix_mem != NULL) 2668 bus_release_resource(dev, SYS_RES_MEMORY, 2669 PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem); 2670 2671 if (adapter->msi) 2672 pci_release_msi(dev); 2673 2674 if (adapter->res_memory != NULL) 2675 bus_release_resource(dev, SYS_RES_MEMORY, 2676 PCIR_BAR(0), adapter->res_memory); 2677 2678 if (adapter->flash_mem != NULL) 2679 bus_release_resource(dev, SYS_RES_MEMORY, 2680 EM_FLASH, adapter->flash_mem); 2681 2682 if (adapter->res_ioport != NULL) 2683 bus_release_resource(dev, SYS_RES_IOPORT, 2684 adapter->io_rid, adapter->res_ioport); 2685} 2686 2687/********************************************************************* 2688 * 2689 * Initialize the hardware to a configuration 2690 * as specified by the adapter structure. 2691 * 2692 **********************************************************************/ 2693static int 2694em_hardware_init(struct adapter *adapter) 2695{ 2696 device_t dev = adapter->dev; 2697 uint16_t rx_buffer_size; 2698 2699 INIT_DEBUGOUT("em_hardware_init: begin"); 2700 2701 /* Issue a global reset */ 2702 e1000_reset_hw(&adapter->hw); 2703 2704 /* When hardware is reset, fifo_head is also reset */ 2705 adapter->tx_fifo_head = 0; 2706 2707 /* Set up smart power down as default off on newer adapters. */ 2708 if (!em_smart_pwr_down && (adapter->hw.mac.type == e1000_82571 || 2709 adapter->hw.mac.type == e1000_82572)) { 2710 uint16_t phy_tmp = 0; 2711 2712 /* Speed up time to link by disabling smart power down. */ 2713 e1000_read_phy_reg(&adapter->hw, 2714 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2715 phy_tmp &= ~IGP02E1000_PM_SPD; 2716 e1000_write_phy_reg(&adapter->hw, 2717 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2718 } 2719 2720 /* 2721 * These parameters control the automatic generation (Tx) and 2722 * response (Rx) to Ethernet PAUSE frames. 2723 * - High water mark should allow for at least two frames to be 2724 * received after sending an XOFF. 2725 * - Low water mark works best when it is very near the high water mark. 2726 * This allows the receiver to restart by sending XON when it has 2727 * drained a bit. Here we use an arbitary value of 1500 which will 2728 * restart after one full frame is pulled from the buffer. There 2729 * could be several smaller frames in the buffer and if so they will 2730 * not trigger the XON until their total number reduces the buffer 2731 * by 1500. 2732 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2733 */ 2734 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 2735 0xffff) << 10 ); 2736 2737 adapter->hw.mac.fc_high_water = rx_buffer_size - 2738 roundup2(adapter->hw.mac.max_frame_size, 1024); 2739 adapter->hw.mac.fc_low_water = adapter->hw.mac.fc_high_water - 1500; 2740 if (adapter->hw.mac.type == e1000_80003es2lan) 2741 adapter->hw.mac.fc_pause_time = 0xFFFF; 2742 else 2743 adapter->hw.mac.fc_pause_time = EM_FC_PAUSE_TIME; 2744 adapter->hw.mac.fc_send_xon = TRUE; 2745 adapter->hw.mac.fc = e1000_fc_full; 2746 2747 if (e1000_init_hw(&adapter->hw) < 0) { 2748 device_printf(dev, "Hardware Initialization Failed\n"); 2749 return (EIO); 2750 } 2751 2752 e1000_check_for_link(&adapter->hw); 2753 2754 return (0); 2755} 2756 2757/********************************************************************* 2758 * 2759 * Setup networking device structure and register an interface. 2760 * 2761 **********************************************************************/ 2762static void 2763em_setup_interface(device_t dev, struct adapter *adapter) 2764{ 2765 struct ifnet *ifp; 2766 2767 INIT_DEBUGOUT("em_setup_interface: begin"); 2768 2769 ifp = adapter->ifp = if_alloc(IFT_ETHER); 2770 if (ifp == NULL) 2771 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2772 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2773 ifp->if_mtu = ETHERMTU; 2774 ifp->if_init = em_init; 2775 ifp->if_softc = adapter; 2776 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2777 ifp->if_ioctl = em_ioctl; 2778 ifp->if_start = em_start; 2779 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 2780 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 2781 IFQ_SET_READY(&ifp->if_snd); 2782 2783 ether_ifattach(ifp, adapter->hw.mac.addr); 2784 2785 ifp->if_capabilities = ifp->if_capenable = 0; 2786 2787 if (adapter->hw.mac.type >= e1000_82543) { 2788 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2789 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2790 } 2791 2792 /* Identify TSO capable adapters */ 2793 if ((adapter->hw.mac.type > e1000_82544) && 2794 (adapter->hw.mac.type != e1000_82547)) 2795 ifp->if_capabilities |= IFCAP_TSO4; 2796 /* 2797 * By default only enable on PCI-E, this 2798 * can be overriden by ifconfig. 2799 */ 2800 if (adapter->hw.mac.type >= e1000_82571) 2801 ifp->if_capenable |= IFCAP_TSO4; 2802 2803 /* 2804 * Tell the upper layer(s) we support long frames. 2805 */ 2806 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2807 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2808 ifp->if_capenable |= IFCAP_VLAN_MTU; 2809 2810#ifdef DEVICE_POLLING 2811 ifp->if_capabilities |= IFCAP_POLLING; 2812#endif 2813 2814 /* 2815 * Specify the media types supported by this adapter and register 2816 * callbacks to update media and link information 2817 */ 2818 ifmedia_init(&adapter->media, IFM_IMASK, 2819 em_media_change, em_media_status); 2820 if ((adapter->hw.media_type == e1000_media_type_fiber) || 2821 (adapter->hw.media_type == e1000_media_type_internal_serdes)) { 2822 u_char fiber_type = IFM_1000_SX; /* default type */ 2823 2824 if (adapter->hw.mac.type == e1000_82545) 2825 fiber_type = IFM_1000_LX; 2826 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2827 0, NULL); 2828 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2829 } else { 2830 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2831 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2832 0, NULL); 2833 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2834 0, NULL); 2835 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2836 0, NULL); 2837 if (adapter->hw.phy.type != e1000_phy_ife) { 2838 ifmedia_add(&adapter->media, 2839 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2840 ifmedia_add(&adapter->media, 2841 IFM_ETHER | IFM_1000_T, 0, NULL); 2842 } 2843 } 2844 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2845 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2846} 2847 2848 2849/********************************************************************* 2850 * 2851 * Workaround for SmartSpeed on 82541 and 82547 controllers 2852 * 2853 **********************************************************************/ 2854static void 2855em_smartspeed(struct adapter *adapter) 2856{ 2857 uint16_t phy_tmp; 2858 2859 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2860 adapter->hw.mac.autoneg == 0 || 2861 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2862 return; 2863 2864 if (adapter->smartspeed == 0) { 2865 /* If Master/Slave config fault is asserted twice, 2866 * we assume back-to-back */ 2867 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2868 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2869 return; 2870 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2871 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2872 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2873 if(phy_tmp & CR_1000T_MS_ENABLE) { 2874 phy_tmp &= ~CR_1000T_MS_ENABLE; 2875 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, 2876 phy_tmp); 2877 adapter->smartspeed++; 2878 if(adapter->hw.mac.autoneg && 2879 !e1000_phy_setup_autoneg(&adapter->hw) && 2880 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, 2881 &phy_tmp)) { 2882 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2883 MII_CR_RESTART_AUTO_NEG); 2884 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 2885 phy_tmp); 2886 } 2887 } 2888 } 2889 return; 2890 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2891 /* If still no link, perhaps using 2/3 pair cable */ 2892 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2893 phy_tmp |= CR_1000T_MS_ENABLE; 2894 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2895 if(adapter->hw.mac.autoneg && 2896 !e1000_phy_setup_autoneg(&adapter->hw) && 2897 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2898 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2899 MII_CR_RESTART_AUTO_NEG); 2900 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2901 } 2902 } 2903 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2904 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2905 adapter->smartspeed = 0; 2906} 2907 2908 2909/* 2910 * Manage DMA'able memory. 2911 */ 2912static void 2913em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2914{ 2915 if (error) 2916 return; 2917 *(bus_addr_t *) arg = segs[0].ds_addr; 2918} 2919 2920static int 2921em_dma_malloc(struct adapter *adapter, bus_size_t size, 2922 struct em_dma_alloc *dma, int mapflags) 2923{ 2924 int error; 2925 2926 error = bus_dma_tag_create(bus_get_dma_tag(adapter->dev), /* parent */ 2927 EM_DBA_ALIGN, 0, /* alignment, bounds */ 2928 BUS_SPACE_MAXADDR, /* lowaddr */ 2929 BUS_SPACE_MAXADDR, /* highaddr */ 2930 NULL, NULL, /* filter, filterarg */ 2931 size, /* maxsize */ 2932 1, /* nsegments */ 2933 size, /* maxsegsize */ 2934 0, /* flags */ 2935 NULL, /* lockfunc */ 2936 NULL, /* lockarg */ 2937 &dma->dma_tag); 2938 if (error) { 2939 device_printf(adapter->dev, 2940 "%s: bus_dma_tag_create failed: %d\n", 2941 __func__, error); 2942 goto fail_0; 2943 } 2944 2945 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2946 BUS_DMA_NOWAIT, &dma->dma_map); 2947 if (error) { 2948 device_printf(adapter->dev, 2949 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2950 __func__, (uintmax_t)size, error); 2951 goto fail_2; 2952 } 2953 2954 dma->dma_paddr = 0; 2955 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2956 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2957 if (error || dma->dma_paddr == 0) { 2958 device_printf(adapter->dev, 2959 "%s: bus_dmamap_load failed: %d\n", 2960 __func__, error); 2961 goto fail_3; 2962 } 2963 2964 return (0); 2965 2966fail_3: 2967 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2968fail_2: 2969 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2970 bus_dma_tag_destroy(dma->dma_tag); 2971fail_0: 2972 dma->dma_map = NULL; 2973 dma->dma_tag = NULL; 2974 2975 return (error); 2976} 2977 2978static void 2979em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2980{ 2981 if (dma->dma_tag == NULL) 2982 return; 2983 if (dma->dma_map != NULL) { 2984 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2985 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2986 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2987 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2988 dma->dma_map = NULL; 2989 } 2990 bus_dma_tag_destroy(dma->dma_tag); 2991 dma->dma_tag = NULL; 2992} 2993 2994 2995/********************************************************************* 2996 * 2997 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2998 * the information needed to transmit a packet on the wire. 2999 * 3000 **********************************************************************/ 3001static int 3002em_allocate_transmit_structures(struct adapter *adapter) 3003{ 3004 device_t dev = adapter->dev; 3005 3006 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 3007 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 3008 if (adapter->tx_buffer_area == NULL) { 3009 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 3010 return (ENOMEM); 3011 } 3012 3013 bzero(adapter->tx_buffer_area, 3014 (sizeof(struct em_buffer)) * adapter->num_tx_desc); 3015 3016 return (0); 3017} 3018 3019/********************************************************************* 3020 * 3021 * Initialize transmit structures. 3022 * 3023 **********************************************************************/ 3024static int 3025em_setup_transmit_structures(struct adapter *adapter) 3026{ 3027 device_t dev = adapter->dev; 3028 struct em_buffer *tx_buffer; 3029 int error, i; 3030 3031 /* 3032 * Create DMA tags for tx descriptors 3033 */ 3034 if ((error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3035 1, 0, /* alignment, bounds */ 3036 BUS_SPACE_MAXADDR, /* lowaddr */ 3037 BUS_SPACE_MAXADDR, /* highaddr */ 3038 NULL, NULL, /* filter, filterarg */ 3039 EM_TSO_SIZE, /* maxsize */ 3040 EM_MAX_SCATTER, /* nsegments */ 3041 EM_TSO_SEG_SIZE, /* maxsegsize */ 3042 0, /* flags */ 3043 NULL, /* lockfunc */ 3044 NULL, /* lockarg */ 3045 &adapter->txtag)) != 0) { 3046 device_printf(dev, "Unable to allocate TX DMA tag\n"); 3047 goto fail; 3048 } 3049 3050 if ((error = em_allocate_transmit_structures(adapter)) != 0) 3051 goto fail; 3052 3053 /* Clear the old ring contents */ 3054 bzero(adapter->tx_desc_base, 3055 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 3056 3057 /* Create the descriptor buffer dma maps */ 3058 tx_buffer = adapter->tx_buffer_area; 3059 for (i = 0; i < adapter->num_tx_desc; i++) { 3060 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 3061 if (error != 0) { 3062 device_printf(dev, "Unable to create TX DMA map\n"); 3063 goto fail; 3064 } 3065 tx_buffer->next_eop = -1; 3066 tx_buffer++; 3067 } 3068 3069 adapter->next_avail_tx_desc = 0; 3070 adapter->next_tx_to_clean = 0; 3071 3072 /* Set number of descriptors available */ 3073 adapter->num_tx_desc_avail = adapter->num_tx_desc; 3074 3075 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3077 3078 return (0); 3079 3080fail: 3081 em_free_transmit_structures(adapter); 3082 return (error); 3083} 3084 3085/********************************************************************* 3086 * 3087 * Enable transmit unit. 3088 * 3089 **********************************************************************/ 3090static void 3091em_initialize_transmit_unit(struct adapter *adapter) 3092{ 3093 uint32_t tctl, tarc, tipg = 0; 3094 uint64_t bus_addr; 3095 3096 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3097 /* Setup the Base and Length of the Tx Descriptor Ring */ 3098 bus_addr = adapter->txdma.dma_paddr; 3099 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN, 3100 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 3101 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH, (uint32_t)(bus_addr >> 32)); 3102 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL, (uint32_t)bus_addr); 3103 3104 /* Setup the HW Tx Head and Tail descriptor pointers */ 3105 E1000_WRITE_REG(&adapter->hw, E1000_TDT, 0); 3106 E1000_WRITE_REG(&adapter->hw, E1000_TDH, 0); 3107 3108 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3109 E1000_READ_REG(&adapter->hw, E1000_TDBAL), 3110 E1000_READ_REG(&adapter->hw, E1000_TDLEN)); 3111 3112 /* Set the default values for the Tx Inter Packet Gap timer */ 3113 switch (adapter->hw.mac.type) { 3114 case e1000_82542: 3115 tipg = DEFAULT_82542_TIPG_IPGT; 3116 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3117 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3118 break; 3119 case e1000_80003es2lan: 3120 tipg = DEFAULT_82543_TIPG_IPGR1; 3121 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3122 E1000_TIPG_IPGR2_SHIFT; 3123 break; 3124 default: 3125 if ((adapter->hw.media_type == e1000_media_type_fiber) || 3126 (adapter->hw.media_type == 3127 e1000_media_type_internal_serdes)) 3128 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3129 else 3130 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3131 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3132 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3133 } 3134 3135 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3136 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3137 if(adapter->hw.mac.type >= e1000_82540) 3138 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3139 adapter->tx_abs_int_delay.value); 3140 3141 if ((adapter->hw.mac.type == e1000_82571) || 3142 (adapter->hw.mac.type == e1000_82572)) { 3143 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC0); 3144 tarc |= SPEED_MODE_BIT; 3145 E1000_WRITE_REG(&adapter->hw, E1000_TARC0, tarc); 3146 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3147 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC0); 3148 tarc |= 1; 3149 E1000_WRITE_REG(&adapter->hw, E1000_TARC0, tarc); 3150 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC1); 3151 tarc |= 1; 3152 E1000_WRITE_REG(&adapter->hw, E1000_TARC1, tarc); 3153 } 3154 3155 /* Program the Transmit Control Register */ 3156 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3157 tctl &= ~E1000_TCTL_CT; 3158 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3159 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3160 3161 if (adapter->hw.mac.type >= e1000_82571) 3162 tctl |= E1000_TCTL_MULR; 3163 3164 /* This write will effectively turn on the transmit unit. */ 3165 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3166 3167 /* Setup Transmit Descriptor Base Settings */ 3168 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 3169 3170 if ((adapter->tx_int_delay.value > 0) && 3171 (adapter->hw.mac.type != e1000_82575)) 3172 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3173 3174 /* Set the function pointer for the transmit routine */ 3175 if (adapter->hw.mac.type >= e1000_82575) 3176 adapter->em_xmit = em_adv_encap; 3177 else 3178 adapter->em_xmit = em_encap; 3179} 3180 3181/********************************************************************* 3182 * 3183 * Free all transmit related data structures. 3184 * 3185 **********************************************************************/ 3186static void 3187em_free_transmit_structures(struct adapter *adapter) 3188{ 3189 struct em_buffer *tx_buffer; 3190 int i; 3191 3192 INIT_DEBUGOUT("free_transmit_structures: begin"); 3193 3194 if (adapter->tx_buffer_area != NULL) { 3195 tx_buffer = adapter->tx_buffer_area; 3196 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 3197 if (tx_buffer->m_head != NULL) { 3198 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3199 BUS_DMASYNC_POSTWRITE); 3200 bus_dmamap_unload(adapter->txtag, 3201 tx_buffer->map); 3202 m_freem(tx_buffer->m_head); 3203 tx_buffer->m_head = NULL; 3204 } else if (tx_buffer->map != NULL) 3205 bus_dmamap_unload(adapter->txtag, 3206 tx_buffer->map); 3207 if (tx_buffer->map != NULL) { 3208 bus_dmamap_destroy(adapter->txtag, 3209 tx_buffer->map); 3210 tx_buffer->map = NULL; 3211 } 3212 } 3213 } 3214 if (adapter->tx_buffer_area != NULL) { 3215 free(adapter->tx_buffer_area, M_DEVBUF); 3216 adapter->tx_buffer_area = NULL; 3217 } 3218 if (adapter->txtag != NULL) { 3219 bus_dma_tag_destroy(adapter->txtag); 3220 adapter->txtag = NULL; 3221 } 3222} 3223 3224/********************************************************************* 3225 * 3226 * The offload context needs to be set when we transfer the first 3227 * packet of a particular protocol (TCP/UDP). This routine has been 3228 * enhanced to deal with inserted VLAN headers, and IPV6 (not complete) 3229 * 3230 **********************************************************************/ 3231static void 3232em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 3233 uint32_t *txd_upper, uint32_t *txd_lower) 3234{ 3235 struct e1000_context_desc *TXD; 3236 struct em_buffer *tx_buffer; 3237 struct ether_vlan_header *eh; 3238 struct ip *ip; 3239 struct ip6_hdr *ip6; 3240 struct tcp_hdr *th; 3241 int curr_txd, ehdrlen, hdr_len, ip_hlen; 3242 uint32_t cmd = 0; 3243 uint16_t etype; 3244 uint8_t ipproto; 3245 3246 /* Setup checksum offload context. */ 3247 curr_txd = adapter->next_avail_tx_desc; 3248 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3249 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3250 3251 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3252 E1000_TXD_DTYP_D; /* Data descr */ 3253 3254 /* 3255 * Determine where frame payload starts. 3256 * Jump over vlan headers if already present, 3257 * helpful for QinQ too. 3258 */ 3259 eh = mtod(mp, struct ether_vlan_header *); 3260 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3261 etype = ntohs(eh->evl_proto); 3262 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3263 } else { 3264 etype = ntohs(eh->evl_encap_proto); 3265 ehdrlen = ETHER_HDR_LEN; 3266 } 3267 3268 /* 3269 * We only support TCP/UDP for IPv4 and IPv6 for the moment. 3270 * TODO: Support SCTP too when it hits the tree. 3271 */ 3272 switch (etype) { 3273 case ETHERTYPE_IP: 3274 ip = (struct ip *)(mp->m_data + ehdrlen); 3275 ip_hlen = ip->ip_hl << 2; 3276 3277 /* Setup of IP header checksum. */ 3278 if (mp->m_pkthdr.csum_flags & CSUM_IP) { 3279 /* 3280 * Start offset for header checksum calculation. 3281 * End offset for header checksum calculation. 3282 * Offset of place to put the checksum. 3283 */ 3284 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3285 TXD->lower_setup.ip_fields.ipcse = 3286 htole16(ehdrlen + ip_hlen); 3287 TXD->lower_setup.ip_fields.ipcso = 3288 ehdrlen + offsetof(struct ip, ip_sum); 3289 cmd |= E1000_TXD_CMD_IP; 3290 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3291 } 3292 3293 if (mp->m_len < ehdrlen + ip_hlen) 3294 return; /* failure */ 3295 3296 hdr_len = ehdrlen + ip_hlen; 3297 ipproto = ip->ip_p; 3298 3299 break; 3300 case ETHERTYPE_IPV6: 3301 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3302 ip_hlen = sizeof(struct ip6_hdr); /* XXX: No header stacking. */ 3303 3304 if (mp->m_len < ehdrlen + ip_hlen) 3305 return; /* failure */ 3306 3307 /* IPv6 doesn't have a header checksum. */ 3308 3309 hdr_len = ehdrlen + ip_hlen; 3310 ipproto = ip6->ip6_nxt; 3311 3312 break; 3313 default: 3314 *txd_upper = 0; 3315 *txd_lower = 0; 3316 return; 3317 } 3318 3319 switch (ipproto) { 3320 case IPPROTO_TCP: 3321 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 3322 /* 3323 * Start offset for payload checksum calculation. 3324 * End offset for payload checksum calculation. 3325 * Offset of place to put the checksum. 3326 */ 3327 th = (struct tcp_hdr *)(mp->m_data + hdr_len); 3328 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3329 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3330 TXD->upper_setup.tcp_fields.tucso = 3331 hdr_len + offsetof(struct tcphdr, th_sum); 3332 cmd |= E1000_TXD_CMD_TCP; 3333 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3334 } 3335 break; 3336 case IPPROTO_UDP: 3337 if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 3338 /* 3339 * Start offset for header checksum calculation. 3340 * End offset for header checksum calculation. 3341 * Offset of place to put the checksum. 3342 */ 3343 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3344 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3345 TXD->upper_setup.tcp_fields.tucso = 3346 hdr_len + offsetof(struct udphdr, uh_sum); 3347 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3348 } 3349 break; 3350 default: 3351 break; 3352 } 3353 3354 TXD->tcp_seg_setup.data = htole32(0); 3355 TXD->cmd_and_length = 3356 htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT | cmd); 3357 tx_buffer->m_head = NULL; 3358 tx_buffer->next_eop = -1; 3359 3360 if (++curr_txd == adapter->num_tx_desc) 3361 curr_txd = 0; 3362 3363 adapter->num_tx_desc_avail--; 3364 adapter->next_avail_tx_desc = curr_txd; 3365} 3366 3367/********************************************************************** 3368 * 3369 * Setup work for hardware segmentation offload (TSO) 3370 * 3371 **********************************************************************/ 3372static boolean_t 3373em_tso_setup(struct adapter *adapter, struct mbuf *mp, uint32_t *txd_upper, 3374 uint32_t *txd_lower) 3375{ 3376 struct e1000_context_desc *TXD; 3377 struct em_buffer *tx_buffer; 3378 struct ether_vlan_header *eh; 3379 struct ip *ip; 3380 struct ip6_hdr *ip6; 3381 struct tcphdr *th; 3382 int curr_txd, ehdrlen, hdr_len, ip_hlen, isip6; 3383 uint16_t etype; 3384 3385 /* 3386 * XXX: This is not really correct as the stack would not have 3387 * set up all checksums. 3388 * XXX: Return FALSE is not sufficient as we may have to return 3389 * in true failure cases as well. Should do -1 (failure), 0 (no) 3390 * and 1 (success). 3391 */ 3392 if (((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) || 3393 (mp->m_pkthdr.len <= EM_TX_BUFFER_SIZE)) 3394 return FALSE; 3395 3396 /* 3397 * This function could/should be extended to support IP/IPv6 3398 * fragmentation as well. But as they say, one step at a time. 3399 */ 3400 3401 /* 3402 * Determine where frame payload starts. 3403 * Jump over vlan headers if already present, 3404 * helpful for QinQ too. 3405 */ 3406 eh = mtod(mp, struct ether_vlan_header *); 3407 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3408 etype = ntohs(eh->evl_proto); 3409 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3410 } else { 3411 etype = ntohs(eh->evl_encap_proto); 3412 ehdrlen = ETHER_HDR_LEN; 3413 } 3414 3415 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3416 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3417 return FALSE; /* -1 */ 3418 3419 /* 3420 * We only support TCP for IPv4 and IPv6 (notyet) for the moment. 3421 * TODO: Support SCTP too when it hits the tree. 3422 */ 3423 switch (etype) { 3424 case ETHERTYPE_IP: 3425 isip6 = 0; 3426 ip = (struct ip *)(mp->m_data + ehdrlen); 3427 if (ip->ip_p != IPPROTO_TCP) 3428 return FALSE; /* 0 */ 3429 ip->ip_len = 0; 3430 ip->ip_sum = 0; 3431 ip_hlen = ip->ip_hl << 2; 3432 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3433 return FALSE; /* -1 */ 3434 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3435#if 1 3436 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3437 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3438#else 3439 th->th_sum = mp->m_pkthdr.csum_data; 3440#endif 3441 break; 3442 case ETHERTYPE_IPV6: 3443 isip6 = 1; 3444 return FALSE; /* Not supported yet. */ 3445 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3446 if (ip6->ip6_nxt != IPPROTO_TCP) 3447 return FALSE; /* 0 */ 3448 ip6->ip6_plen = 0; 3449 ip_hlen = sizeof(struct ip6_hdr); /* XXX: no header stacking. */ 3450 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3451 return FALSE; /* -1 */ 3452 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 3453#if 0 3454 th->th_sum = in6_pseudo(ip6->ip6_src, ip->ip6_dst, 3455 htons(IPPROTO_TCP)); /* XXX: function notyet. */ 3456#else 3457 th->th_sum = mp->m_pkthdr.csum_data; 3458#endif 3459 break; 3460 default: 3461 return FALSE; 3462 } 3463 hdr_len = ehdrlen + ip_hlen + (th->th_off << 2); 3464 3465 *txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */ 3466 E1000_TXD_DTYP_D | /* Data descr type */ 3467 E1000_TXD_CMD_TSE); /* Do TSE on this packet */ 3468 3469 /* IP and/or TCP header checksum calculation and insertion. */ 3470 *txd_upper = ((isip6 ? 0 : E1000_TXD_POPTS_IXSM) | 3471 E1000_TXD_POPTS_TXSM) << 8; 3472 3473 curr_txd = adapter->next_avail_tx_desc; 3474 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3475 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3476 3477 /* IPv6 doesn't have a header checksum. */ 3478 if (!isip6) { 3479 /* 3480 * Start offset for header checksum calculation. 3481 * End offset for header checksum calculation. 3482 * Offset of place put the checksum. 3483 */ 3484 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3485 TXD->lower_setup.ip_fields.ipcse = 3486 htole16(ehdrlen + ip_hlen - 1); 3487 TXD->lower_setup.ip_fields.ipcso = 3488 ehdrlen + offsetof(struct ip, ip_sum); 3489 } 3490 /* 3491 * Start offset for payload checksum calculation. 3492 * End offset for payload checksum calculation. 3493 * Offset of place to put the checksum. 3494 */ 3495 TXD->upper_setup.tcp_fields.tucss = 3496 ehdrlen + ip_hlen; 3497 TXD->upper_setup.tcp_fields.tucse = 0; 3498 TXD->upper_setup.tcp_fields.tucso = 3499 ehdrlen + ip_hlen + offsetof(struct tcphdr, th_sum); 3500 /* 3501 * Payload size per packet w/o any headers. 3502 * Length of all headers up to payload. 3503 */ 3504 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3505 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3506 3507 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3508 E1000_TXD_CMD_DEXT | /* Extended descr */ 3509 E1000_TXD_CMD_TSE | /* TSE context */ 3510 (isip6 ? 0 : E1000_TXD_CMD_IP) | /* Do IP csum */ 3511 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3512 (mp->m_pkthdr.len - (hdr_len))); /* Total len */ 3513 3514 tx_buffer->m_head = NULL; 3515 tx_buffer->next_eop = -1; 3516 3517 if (++curr_txd == adapter->num_tx_desc) 3518 curr_txd = 0; 3519 3520 adapter->num_tx_desc_avail--; 3521 adapter->next_avail_tx_desc = curr_txd; 3522 adapter->tx_tso = TRUE; 3523 3524 return TRUE; 3525} 3526 3527 3528/********************************************************************** 3529 * 3530 * Setup work for hardware segmentation offload (TSO) on 3531 * adapters using advanced tx descriptors 3532 * 3533 **********************************************************************/ 3534static boolean_t 3535em_tso_adv_setup(struct adapter *adapter, struct mbuf *mp, u32 *paylen) 3536{ 3537 struct e1000_adv_tx_context_desc *TXD; 3538 struct em_buffer *tx_buffer; 3539 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3540 u32 mss_l4len_idx = 0; 3541 u16 vtag = 0; 3542 int ctxd, ehdrlen, hdrlen, ip_hlen, tcp_hlen; 3543 struct ether_vlan_header *eh; 3544 struct ip *ip; 3545 struct tcphdr *th; 3546 3547 if (((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) || 3548 (mp->m_pkthdr.len <= EM_TX_BUFFER_SIZE)) 3549 return FALSE; 3550 3551 /* 3552 * Determine where frame payload starts. 3553 * Jump over vlan headers if already present 3554 */ 3555 eh = mtod(mp, struct ether_vlan_header *); 3556 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) 3557 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3558 else 3559 ehdrlen = ETHER_HDR_LEN; 3560 3561 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3562 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3563 return FALSE; 3564 3565 /* Only supports IPV4 for now */ 3566 ctxd = adapter->next_avail_tx_desc; 3567 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3568 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3569 3570 ip = (struct ip *)(mp->m_data + ehdrlen); 3571 if (ip->ip_p != IPPROTO_TCP) 3572 return FALSE; /* 0 */ 3573 ip->ip_len = 0; 3574 ip->ip_sum = 0; 3575 ip_hlen = ip->ip_hl << 2; 3576 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3577 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3578 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3579 tcp_hlen = th->th_off << 2; 3580 hdrlen = ehdrlen + ip_hlen + tcp_hlen; 3581 /* Calculate payload, this is used in the transmit desc in encap */ 3582 *paylen = mp->m_pkthdr.len - hdrlen; 3583 3584 /* VLAN MACLEN IPLEN */ 3585 if (mp->m_flags & M_VLANTAG) { 3586 vtag = htole16(mp->m_pkthdr.ether_vtag); 3587 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3588 } 3589 vlan_macip_lens |= (ehdrlen << E1000_ADVTXD_MACLEN_SHIFT); 3590 vlan_macip_lens |= ip_hlen; 3591 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3592 3593 /* ADV DTYPE TUCMD */ 3594 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3595 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3596 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3597 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3598 3599 /* MSS L4LEN IDX */ 3600 mss_l4len_idx |= (mp->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT); 3601 mss_l4len_idx |= (tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 3602 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 3603 3604 TXD->seqnum_seed = htole32(0); 3605 tx_buffer->m_head = NULL; 3606 tx_buffer->next_eop = -1; 3607 3608 if (++ctxd == adapter->num_tx_desc) 3609 ctxd = 0; 3610 3611 adapter->num_tx_desc_avail--; 3612 adapter->next_avail_tx_desc = ctxd; 3613 return TRUE; 3614} 3615 3616 3617/********************************************************************* 3618 * 3619 * Advanced Context Descriptor setup for VLAN or CSUM 3620 * 3621 **********************************************************************/ 3622 3623static boolean_t 3624em_tx_adv_ctx_setup(struct adapter *adapter, struct mbuf *mp) 3625{ 3626 struct e1000_adv_tx_context_desc *TXD; 3627 struct em_buffer *tx_buffer; 3628 uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3629 struct ether_vlan_header *eh; 3630 struct ip *ip; 3631 struct ip6_hdr *ip6; 3632 int ehdrlen, ip_hlen; 3633 u16 etype; 3634 u8 ipproto; 3635 3636 int ctxd = adapter->next_avail_tx_desc; 3637 u16 vtag = 0; 3638 3639 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3640 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3641 3642 /* 3643 ** In advanced descriptors the vlan tag must 3644 ** be placed into the descriptor itself. 3645 */ 3646 if (mp->m_flags & M_VLANTAG) { 3647 vtag = htole16(mp->m_pkthdr.ether_vtag); 3648 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3649 } 3650 3651 /* 3652 * Determine where frame payload starts. 3653 * Jump over vlan headers if already present, 3654 * helpful for QinQ too. 3655 */ 3656 eh = mtod(mp, struct ether_vlan_header *); 3657 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3658 etype = ntohs(eh->evl_proto); 3659 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3660 } else { 3661 etype = ntohs(eh->evl_encap_proto); 3662 ehdrlen = ETHER_HDR_LEN; 3663 } 3664 3665 /* Set the ether header length */ 3666 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 3667 3668 switch (etype) { 3669 case ETHERTYPE_IP: 3670 ip = (struct ip *)(mp->m_data + ehdrlen); 3671 ip_hlen = ip->ip_hl << 2; 3672 if (mp->m_len < ehdrlen + ip_hlen) 3673 return FALSE; /* failure */ 3674 ipproto = ip->ip_p; 3675 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3676 break; 3677 case ETHERTYPE_IPV6: 3678 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3679 ip_hlen = sizeof(struct ip6_hdr); 3680 if (mp->m_len < ehdrlen + ip_hlen) 3681 return FALSE; /* failure */ 3682 ipproto = ip6->ip6_nxt; 3683 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 3684 break; 3685 default: 3686 return FALSE; 3687 } 3688 3689 vlan_macip_lens |= ip_hlen; 3690 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3691 3692 switch (ipproto) { 3693 case IPPROTO_TCP: 3694 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 3695 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3696 break; 3697 case IPPROTO_UDP: 3698 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 3699 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3700 break; 3701 } 3702 3703 /* Now copy bits into descriptor */ 3704 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3705 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3706 TXD->seqnum_seed = htole32(0); 3707 TXD->mss_l4len_idx = htole32(0); 3708 3709 tx_buffer->m_head = NULL; 3710 tx_buffer->next_eop = -1; 3711 3712 /* We've consumed the first desc, adjust counters */ 3713 if (++ctxd == adapter->num_tx_desc) 3714 ctxd = 0; 3715 adapter->next_avail_tx_desc = ctxd; 3716 --adapter->num_tx_desc_avail; 3717 3718 return TRUE; 3719} 3720 3721 3722/********************************************************************** 3723 * 3724 * Examine each tx_buffer in the used queue. If the hardware is done 3725 * processing the packet then free associated resources. The 3726 * tx_buffer is put back on the free queue. 3727 * 3728 **********************************************************************/ 3729static void 3730em_txeof(struct adapter *adapter) 3731{ 3732 int first, last, done, num_avail; 3733 struct em_buffer *tx_buffer; 3734 struct e1000_tx_desc *tx_desc, *eop_desc; 3735 struct ifnet *ifp = adapter->ifp; 3736 3737 EM_LOCK_ASSERT(adapter); 3738 3739 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3740 return; 3741 3742 num_avail = adapter->num_tx_desc_avail; 3743 first = adapter->next_tx_to_clean; 3744 tx_desc = &adapter->tx_desc_base[first]; 3745 tx_buffer = &adapter->tx_buffer_area[first]; 3746 last = tx_buffer->next_eop; 3747 eop_desc = &adapter->tx_desc_base[last]; 3748 3749 /* 3750 * What this does is get the index of the 3751 * first descriptor AFTER the EOP of the 3752 * first packet, that way we can do the 3753 * simple comparison on the inner while loop. 3754 */ 3755 if (++last == adapter->num_tx_desc) 3756 last = 0; 3757 done = last; 3758 3759 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3760 BUS_DMASYNC_POSTREAD); 3761 3762 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3763 /* We clean the range of the packet */ 3764 while (first != done) { 3765 tx_desc->upper.data = 0; 3766 tx_desc->lower.data = 0; 3767 tx_desc->buffer_addr = 0; 3768 num_avail++; 3769 3770 if (tx_buffer->m_head) { 3771 ifp->if_opackets++; 3772 bus_dmamap_sync(adapter->txtag, 3773 tx_buffer->map, 3774 BUS_DMASYNC_POSTWRITE); 3775 bus_dmamap_unload(adapter->txtag, 3776 tx_buffer->map); 3777 3778 m_freem(tx_buffer->m_head); 3779 tx_buffer->m_head = NULL; 3780 } 3781 tx_buffer->next_eop = -1; 3782 3783 if (++first == adapter->num_tx_desc) 3784 first = 0; 3785 3786 tx_buffer = &adapter->tx_buffer_area[first]; 3787 tx_desc = &adapter->tx_desc_base[first]; 3788 } 3789 /* See if we can continue to the next packet */ 3790 last = tx_buffer->next_eop; 3791 if (last != -1) { 3792 eop_desc = &adapter->tx_desc_base[last]; 3793 /* Get new done point */ 3794 if (++last == adapter->num_tx_desc) last = 0; 3795 done = last; 3796 } else 3797 break; 3798 } 3799 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3801 3802 adapter->next_tx_to_clean = first; 3803 3804 /* 3805 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3806 * that it is OK to send packets. 3807 * If there are no pending descriptors, clear the timeout. Otherwise, 3808 * if some descriptors have been freed, restart the timeout. 3809 */ 3810 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 3811 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3812 /* All clean, turn off the timer */ 3813 if (num_avail == adapter->num_tx_desc) 3814 adapter->watchdog_timer = 0; 3815 /* Some cleaned, reset the timer */ 3816 else if (num_avail != adapter->num_tx_desc_avail) 3817 adapter->watchdog_timer = EM_TX_TIMEOUT; 3818 } 3819 adapter->num_tx_desc_avail = num_avail; 3820 return; 3821} 3822 3823/********************************************************************* 3824 * 3825 * Get a buffer from system mbuf buffer pool. 3826 * 3827 **********************************************************************/ 3828static int 3829em_get_buf(struct adapter *adapter, int i) 3830{ 3831 struct mbuf *m; 3832 bus_dma_segment_t segs[1]; 3833 bus_dmamap_t map; 3834 struct em_buffer *rx_buffer; 3835 int error, nsegs; 3836 3837 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3838 if (m == NULL) { 3839 adapter->mbuf_cluster_failed++; 3840 return (ENOBUFS); 3841 } 3842 m->m_len = m->m_pkthdr.len = MCLBYTES; 3843 3844 if (adapter->hw.mac.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3845 m_adj(m, ETHER_ALIGN); 3846 3847 /* 3848 * Using memory from the mbuf cluster pool, invoke the 3849 * bus_dma machinery to arrange the memory mapping. 3850 */ 3851 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, 3852 adapter->rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 3853 if (error != 0) { 3854 m_free(m); 3855 return (error); 3856 } 3857 3858 /* If nsegs is wrong then the stack is corrupt. */ 3859 KASSERT(nsegs == 1, ("Too many segments returned!")); 3860 3861 rx_buffer = &adapter->rx_buffer_area[i]; 3862 if (rx_buffer->m_head != NULL) 3863 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3864 3865 map = rx_buffer->map; 3866 rx_buffer->map = adapter->rx_sparemap; 3867 adapter->rx_sparemap = map; 3868 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 3869 rx_buffer->m_head = m; 3870 3871 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 3872 return (0); 3873} 3874 3875/********************************************************************* 3876 * 3877 * Allocate memory for rx_buffer structures. Since we use one 3878 * rx_buffer per received packet, the maximum number of rx_buffer's 3879 * that we'll need is equal to the number of receive descriptors 3880 * that we've allocated. 3881 * 3882 **********************************************************************/ 3883static int 3884em_allocate_receive_structures(struct adapter *adapter) 3885{ 3886 device_t dev = adapter->dev; 3887 struct em_buffer *rx_buffer; 3888 int i, error; 3889 3890 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 3891 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT); 3892 if (adapter->rx_buffer_area == NULL) { 3893 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 3894 return (ENOMEM); 3895 } 3896 3897 bzero(adapter->rx_buffer_area, 3898 sizeof(struct em_buffer) * adapter->num_rx_desc); 3899 3900 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3901 1, 0, /* alignment, bounds */ 3902 BUS_SPACE_MAXADDR, /* lowaddr */ 3903 BUS_SPACE_MAXADDR, /* highaddr */ 3904 NULL, NULL, /* filter, filterarg */ 3905 MCLBYTES, /* maxsize */ 3906 1, /* nsegments */ 3907 MCLBYTES, /* maxsegsize */ 3908 0, /* flags */ 3909 NULL, /* lockfunc */ 3910 NULL, /* lockarg */ 3911 &adapter->rxtag); 3912 if (error) { 3913 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 3914 __func__, error); 3915 goto fail; 3916 } 3917 3918 /* Create the spare map (used by getbuf) */ 3919 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 3920 &adapter->rx_sparemap); 3921 if (error) { 3922 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 3923 __func__, error); 3924 goto fail; 3925 } 3926 3927 rx_buffer = adapter->rx_buffer_area; 3928 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 3929 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 3930 &rx_buffer->map); 3931 if (error) { 3932 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 3933 __func__, error); 3934 goto fail; 3935 } 3936 } 3937 3938 /* Setup the initial buffers */ 3939 for (i = 0; i < adapter->num_rx_desc; i++) { 3940 error = em_get_buf(adapter, i); 3941 if (error) 3942 goto fail; 3943 } 3944 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3946 3947 return (0); 3948 3949fail: 3950 em_free_receive_structures(adapter); 3951 return (error); 3952} 3953 3954/********************************************************************* 3955 * 3956 * Allocate and initialize receive structures. 3957 * 3958 **********************************************************************/ 3959static int 3960em_setup_receive_structures(struct adapter *adapter) 3961{ 3962 int error; 3963 3964 bzero(adapter->rx_desc_base, 3965 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3966 3967 if ((error = em_allocate_receive_structures(adapter)) !=0) 3968 return (error); 3969 3970 /* Setup our descriptor pointers */ 3971 adapter->next_rx_desc_to_check = 0; 3972 3973 return (0); 3974} 3975 3976/********************************************************************* 3977 * 3978 * Enable receive unit. 3979 * 3980 **********************************************************************/ 3981static void 3982em_initialize_receive_unit(struct adapter *adapter) 3983{ 3984 struct ifnet *ifp = adapter->ifp; 3985 uint64_t bus_addr; 3986 uint32_t reg_rctl; 3987 uint32_t reg_rxcsum; 3988 3989 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 3990 3991 /* 3992 * Make sure receives are disabled while setting 3993 * up the descriptor ring 3994 */ 3995 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3996 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl & ~E1000_RCTL_EN); 3997 3998 if(adapter->hw.mac.type >= e1000_82540) { 3999 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 4000 adapter->rx_abs_int_delay.value); 4001 /* 4002 * Set the interrupt throttling rate. Value is calculated 4003 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 4004 */ 4005#define MAX_INTS_PER_SEC 8000 4006#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4007 E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); 4008 } 4009 4010 /* Setup the Base and Length of the Rx Descriptor Ring */ 4011 bus_addr = adapter->rxdma.dma_paddr; 4012 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN, adapter->num_rx_desc * 4013 sizeof(struct e1000_rx_desc)); 4014 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH, (uint32_t)(bus_addr >> 32)); 4015 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL, (uint32_t)bus_addr); 4016 4017 /* Setup the Receive Control Register */ 4018 reg_rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4019 reg_rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 4020 E1000_RCTL_RDMTS_HALF | 4021 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4022 4023 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 4024 reg_rctl |= E1000_RCTL_SBP; 4025 else 4026 reg_rctl &= ~E1000_RCTL_SBP; 4027 4028 switch (adapter->rx_buffer_len) { 4029 default: 4030 case 2048: 4031 reg_rctl |= E1000_RCTL_SZ_2048; 4032 break; 4033 case 4096: 4034 reg_rctl |= E1000_RCTL_SZ_4096 | 4035 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4036 break; 4037 case 8192: 4038 reg_rctl |= E1000_RCTL_SZ_8192 | 4039 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4040 break; 4041 case 16384: 4042 reg_rctl |= E1000_RCTL_SZ_16384 | 4043 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4044 break; 4045 } 4046 4047 if (ifp->if_mtu > ETHERMTU) 4048 reg_rctl |= E1000_RCTL_LPE; 4049 else 4050 reg_rctl &= ~E1000_RCTL_LPE; 4051 4052 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 4053 if ((adapter->hw.mac.type >= e1000_82543) && 4054 (ifp->if_capenable & IFCAP_RXCSUM)) { 4055 reg_rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 4056 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 4057 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, reg_rxcsum); 4058 } 4059 4060 /* 4061 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 4062 ** long latencies are observed, like Lenovo X60. This 4063 ** change eliminates the problem, but since having positive 4064 ** values in RDTR is a known source of problems on other 4065 ** platforms another solution is being sought. 4066 */ 4067 if (adapter->hw.mac.type == e1000_82573) 4068 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 0x20); 4069 4070 /* Enable Receives */ 4071 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 4072 4073 /* 4074 * Setup the HW Rx Head and 4075 * Tail Descriptor Pointers 4076 */ 4077 E1000_WRITE_REG(&adapter->hw, E1000_RDH, 0); 4078 E1000_WRITE_REG(&adapter->hw, E1000_RDT, adapter->num_rx_desc - 1); 4079 4080 return; 4081} 4082 4083/********************************************************************* 4084 * 4085 * Free receive related data structures. 4086 * 4087 **********************************************************************/ 4088static void 4089em_free_receive_structures(struct adapter *adapter) 4090{ 4091 struct em_buffer *rx_buffer; 4092 int i; 4093 4094 INIT_DEBUGOUT("free_receive_structures: begin"); 4095 4096 if (adapter->rx_sparemap) { 4097 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 4098 adapter->rx_sparemap = NULL; 4099 } 4100 4101 /* Cleanup any existing buffers */ 4102 if (adapter->rx_buffer_area != NULL) { 4103 rx_buffer = adapter->rx_buffer_area; 4104 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4105 if (rx_buffer->m_head != NULL) { 4106 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4107 BUS_DMASYNC_POSTREAD); 4108 bus_dmamap_unload(adapter->rxtag, 4109 rx_buffer->map); 4110 m_freem(rx_buffer->m_head); 4111 rx_buffer->m_head = NULL; 4112 } else if (rx_buffer->map != NULL) 4113 bus_dmamap_unload(adapter->rxtag, 4114 rx_buffer->map); 4115 if (rx_buffer->map != NULL) { 4116 bus_dmamap_destroy(adapter->rxtag, 4117 rx_buffer->map); 4118 rx_buffer->map = NULL; 4119 } 4120 } 4121 } 4122 4123 if (adapter->rx_buffer_area != NULL) { 4124 free(adapter->rx_buffer_area, M_DEVBUF); 4125 adapter->rx_buffer_area = NULL; 4126 } 4127 4128 if (adapter->rxtag != NULL) { 4129 bus_dma_tag_destroy(adapter->rxtag); 4130 adapter->rxtag = NULL; 4131 } 4132} 4133 4134/********************************************************************* 4135 * 4136 * This routine executes in interrupt context. It replenishes 4137 * the mbufs in the descriptor and sends data which has been 4138 * dma'ed into host memory to upper layer. 4139 * 4140 * We loop at most count times if count is > 0, or until done if 4141 * count < 0. 4142 * 4143 *********************************************************************/ 4144static int 4145em_rxeof(struct adapter *adapter, int count) 4146{ 4147 struct ifnet *ifp; 4148 struct mbuf *mp; 4149 uint8_t accept_frame = 0; 4150 uint8_t eop = 0; 4151 uint16_t len, desc_len, prev_len_adj; 4152 int i; 4153 4154 /* Pointer to the receive descriptor being examined. */ 4155 struct e1000_rx_desc *current_desc; 4156 uint8_t status; 4157 4158 ifp = adapter->ifp; 4159 i = adapter->next_rx_desc_to_check; 4160 current_desc = &adapter->rx_desc_base[i]; 4161 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4162 BUS_DMASYNC_POSTREAD); 4163 4164 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4165 return (0); 4166 4167 while ((current_desc->status & E1000_RXD_STAT_DD) && 4168 (count != 0) && 4169 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4170 struct mbuf *m = NULL; 4171 4172 mp = adapter->rx_buffer_area[i].m_head; 4173 /* 4174 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 4175 * needs to access the last received byte in the mbuf. 4176 */ 4177 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 4178 BUS_DMASYNC_POSTREAD); 4179 4180 accept_frame = 1; 4181 prev_len_adj = 0; 4182 desc_len = le16toh(current_desc->length); 4183 status = current_desc->status; 4184 if (status & E1000_RXD_STAT_EOP) { 4185 count--; 4186 eop = 1; 4187 if (desc_len < ETHER_CRC_LEN) { 4188 len = 0; 4189 prev_len_adj = ETHER_CRC_LEN - desc_len; 4190 } else 4191 len = desc_len - ETHER_CRC_LEN; 4192 } else { 4193 eop = 0; 4194 len = desc_len; 4195 } 4196 4197 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 4198 uint8_t last_byte; 4199 uint32_t pkt_len = desc_len; 4200 4201 if (adapter->fmp != NULL) 4202 pkt_len += adapter->fmp->m_pkthdr.len; 4203 4204 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 4205 if (TBI_ACCEPT(&adapter->hw, status, 4206 current_desc->errors, pkt_len, last_byte)) { 4207 e1000_tbi_adjust_stats_82543(&adapter->hw, 4208 &adapter->stats, pkt_len, 4209 adapter->hw.mac.addr); 4210 if (len > 0) 4211 len--; 4212 } else 4213 accept_frame = 0; 4214 } 4215 4216 if (accept_frame) { 4217 if (em_get_buf(adapter, i) != 0) { 4218 ifp->if_iqdrops++; 4219 goto discard; 4220 } 4221 4222 /* Assign correct length to the current fragment */ 4223 mp->m_len = len; 4224 4225 if (adapter->fmp == NULL) { 4226 mp->m_pkthdr.len = len; 4227 adapter->fmp = mp; /* Store the first mbuf */ 4228 adapter->lmp = mp; 4229 } else { 4230 /* Chain mbuf's together */ 4231 mp->m_flags &= ~M_PKTHDR; 4232 /* 4233 * Adjust length of previous mbuf in chain if 4234 * we received less than 4 bytes in the last 4235 * descriptor. 4236 */ 4237 if (prev_len_adj > 0) { 4238 adapter->lmp->m_len -= prev_len_adj; 4239 adapter->fmp->m_pkthdr.len -= 4240 prev_len_adj; 4241 } 4242 adapter->lmp->m_next = mp; 4243 adapter->lmp = adapter->lmp->m_next; 4244 adapter->fmp->m_pkthdr.len += len; 4245 } 4246 4247 if (eop) { 4248 adapter->fmp->m_pkthdr.rcvif = ifp; 4249 ifp->if_ipackets++; 4250 em_receive_checksum(adapter, current_desc, 4251 adapter->fmp); 4252#ifndef __NO_STRICT_ALIGNMENT 4253 if (adapter->hw.mac.max_frame_size > 4254 (MCLBYTES - ETHER_ALIGN) && 4255 em_fixup_rx(adapter) != 0) 4256 goto skip; 4257#endif 4258 if (status & E1000_RXD_STAT_VP) { 4259 adapter->fmp->m_pkthdr.ether_vtag = 4260 (le16toh(current_desc->special) & 4261 E1000_RXD_SPC_VLAN_MASK); 4262 adapter->fmp->m_flags |= M_VLANTAG; 4263 } 4264#ifndef __NO_STRICT_ALIGNMENT 4265skip: 4266#endif 4267 m = adapter->fmp; 4268 adapter->fmp = NULL; 4269 adapter->lmp = NULL; 4270 } 4271 } else { 4272 ifp->if_ierrors++; 4273discard: 4274 /* Reuse loaded DMA map and just update mbuf chain */ 4275 mp = adapter->rx_buffer_area[i].m_head; 4276 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 4277 mp->m_data = mp->m_ext.ext_buf; 4278 mp->m_next = NULL; 4279 if (adapter->hw.mac.max_frame_size <= 4280 (MCLBYTES - ETHER_ALIGN)) 4281 m_adj(mp, ETHER_ALIGN); 4282 if (adapter->fmp != NULL) { 4283 m_freem(adapter->fmp); 4284 adapter->fmp = NULL; 4285 adapter->lmp = NULL; 4286 } 4287 m = NULL; 4288 } 4289 4290 /* Zero out the receive descriptors status. */ 4291 current_desc->status = 0; 4292 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4293 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4294 4295 /* Advance our pointers to the next descriptor. */ 4296 if (++i == adapter->num_rx_desc) 4297 i = 0; 4298 if (m != NULL) { 4299 adapter->next_rx_desc_to_check = i; 4300#ifdef DEVICE_POLLING 4301 EM_UNLOCK(adapter); 4302 (*ifp->if_input)(ifp, m); 4303 EM_LOCK(adapter); 4304#else 4305 /* Already running unlocked */ 4306 (*ifp->if_input)(ifp, m); 4307#endif 4308 i = adapter->next_rx_desc_to_check; 4309 } 4310 current_desc = &adapter->rx_desc_base[i]; 4311 } 4312 adapter->next_rx_desc_to_check = i; 4313 4314 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 4315 if (--i < 0) 4316 i = adapter->num_rx_desc - 1; 4317 E1000_WRITE_REG(&adapter->hw, E1000_RDT, i); 4318 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4319 return (0); 4320 4321 return (1); 4322} 4323 4324#ifndef __NO_STRICT_ALIGNMENT 4325/* 4326 * When jumbo frames are enabled we should realign entire payload on 4327 * architecures with strict alignment. This is serious design mistake of 8254x 4328 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 4329 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 4330 * payload. On architecures without strict alignment restrictions 8254x still 4331 * performs unaligned memory access which would reduce the performance too. 4332 * To avoid copying over an entire frame to align, we allocate a new mbuf and 4333 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 4334 * existing mbuf chain. 4335 * 4336 * Be aware, best performance of the 8254x is achived only when jumbo frame is 4337 * not used at all on architectures with strict alignment. 4338 */ 4339static int 4340em_fixup_rx(struct adapter *adapter) 4341{ 4342 struct mbuf *m, *n; 4343 int error; 4344 4345 error = 0; 4346 m = adapter->fmp; 4347 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 4348 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 4349 m->m_data += ETHER_HDR_LEN; 4350 } else { 4351 MGETHDR(n, M_DONTWAIT, MT_DATA); 4352 if (n != NULL) { 4353 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 4354 m->m_data += ETHER_HDR_LEN; 4355 m->m_len -= ETHER_HDR_LEN; 4356 n->m_len = ETHER_HDR_LEN; 4357 M_MOVE_PKTHDR(n, m); 4358 n->m_next = m; 4359 adapter->fmp = n; 4360 } else { 4361 adapter->dropped_pkts++; 4362 m_freem(adapter->fmp); 4363 adapter->fmp = NULL; 4364 error = ENOMEM; 4365 } 4366 } 4367 4368 return (error); 4369} 4370#endif 4371 4372/********************************************************************* 4373 * 4374 * Verify that the hardware indicated that the checksum is valid. 4375 * Inform the stack about the status of checksum so that stack 4376 * doesn't spend time verifying the checksum. 4377 * 4378 *********************************************************************/ 4379static void 4380em_receive_checksum(struct adapter *adapter, 4381 struct e1000_rx_desc *rx_desc, struct mbuf *mp) 4382{ 4383 /* 82543 or newer only */ 4384 if ((adapter->hw.mac.type < e1000_82543) || 4385 /* Ignore Checksum bit is set */ 4386 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 4387 mp->m_pkthdr.csum_flags = 0; 4388 return; 4389 } 4390 4391 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 4392 /* Did it pass? */ 4393 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 4394 /* IP Checksum Good */ 4395 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 4396 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4397 4398 } else { 4399 mp->m_pkthdr.csum_flags = 0; 4400 } 4401 } 4402 4403 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 4404 /* Did it pass? */ 4405 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 4406 mp->m_pkthdr.csum_flags |= 4407 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 4408 mp->m_pkthdr.csum_data = htons(0xffff); 4409 } 4410 } 4411} 4412 4413 4414static void 4415em_enable_vlans(struct adapter *adapter) 4416{ 4417 uint32_t ctrl; 4418 4419 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 4420 4421 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 4422 ctrl |= E1000_CTRL_VME; 4423 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 4424} 4425 4426static void 4427em_enable_intr(struct adapter *adapter) 4428{ 4429 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 4430 (IMS_ENABLE_MASK)); 4431} 4432 4433static void 4434em_disable_intr(struct adapter *adapter) 4435{ 4436 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 4437} 4438 4439/* 4440 * Bit of a misnomer, what this really means is 4441 * to enable OS management of the system... aka 4442 * to disable special hardware management features 4443 */ 4444static void 4445em_init_manageability(struct adapter *adapter) 4446{ 4447 /* A shared code workaround */ 4448#define E1000_82542_MANC2H E1000_MANC2H 4449 if (adapter->has_manage) { 4450 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 4451 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4452 4453 /* disable hardware interception of ARP */ 4454 manc &= ~(E1000_MANC_ARP_EN); 4455 4456 /* enable receiving management packets to the host */ 4457 if (adapter->hw.mac.type >= e1000_82571) { 4458 manc |= E1000_MANC_EN_MNG2HOST; 4459#define E1000_MNG2HOST_PORT_623 (1 << 5) 4460#define E1000_MNG2HOST_PORT_664 (1 << 6) 4461 manc2h |= E1000_MNG2HOST_PORT_623; 4462 manc2h |= E1000_MNG2HOST_PORT_664; 4463 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 4464 } 4465 4466 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4467 } 4468} 4469 4470/* 4471 * Give control back to hardware management 4472 * controller if there is one. 4473 */ 4474static void 4475em_release_manageability(struct adapter *adapter) 4476{ 4477 if (adapter->has_manage) { 4478 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4479 4480 /* re-enable hardware interception of ARP */ 4481 manc |= E1000_MANC_ARP_EN; 4482 4483 if (adapter->hw.mac.type >= e1000_82571) 4484 manc &= ~E1000_MANC_EN_MNG2HOST; 4485 4486 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4487 } 4488} 4489 4490/* 4491 * em_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4492 * For ASF and Pass Through versions of f/w this means that 4493 * the driver is loaded. For AMT version (only with 82573) 4494 * of the f/w this means that the network i/f is open. 4495 * 4496 */ 4497static void 4498em_get_hw_control(struct adapter *adapter) 4499{ 4500 u32 ctrl_ext, swsm; 4501 4502 /* Let firmware know the driver has taken over */ 4503 switch (adapter->hw.mac.type) { 4504 case e1000_82573: 4505 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4506 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4507 swsm | E1000_SWSM_DRV_LOAD); 4508 break; 4509 case e1000_82571: 4510 case e1000_82572: 4511 case e1000_80003es2lan: 4512 case e1000_ich8lan: 4513 case e1000_ich9lan: 4514 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4515 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4516 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4517 break; 4518 default: 4519 break; 4520 } 4521} 4522 4523/* 4524 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4525 * For ASF and Pass Through versions of f/w this means that the 4526 * driver is no longer loaded. For AMT version (only with 82573) i 4527 * of the f/w this means that the network i/f is closed. 4528 * 4529 */ 4530static void 4531em_release_hw_control(struct adapter *adapter) 4532{ 4533 u32 ctrl_ext, swsm; 4534 4535 /* Let firmware taken over control of h/w */ 4536 switch (adapter->hw.mac.type) { 4537 case e1000_82573: 4538 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4539 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4540 swsm & ~E1000_SWSM_DRV_LOAD); 4541 break; 4542 case e1000_82571: 4543 case e1000_82572: 4544 case e1000_80003es2lan: 4545 case e1000_ich8lan: 4546 case e1000_ich9lan: 4547 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4548 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4549 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4550 break; 4551 default: 4552 break; 4553 4554 } 4555} 4556 4557static int 4558em_is_valid_ether_addr(uint8_t *addr) 4559{ 4560 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4561 4562 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4563 return (FALSE); 4564 } 4565 4566 return (TRUE); 4567} 4568 4569/* 4570 * NOTE: the following routines using the e1000 4571 * naming style are provided to the shared 4572 * code which expects that rather than 'em' 4573 */ 4574 4575void 4576e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4577{ 4578 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 4579} 4580 4581void 4582e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4583{ 4584 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 4585} 4586 4587void 4588e1000_pci_set_mwi(struct e1000_hw *hw) 4589{ 4590 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4591 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 4592} 4593 4594void 4595e1000_pci_clear_mwi(struct e1000_hw *hw) 4596{ 4597 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4598 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 4599} 4600 4601/* 4602 * Read the PCI Express capabilities 4603 */ 4604int32_t 4605e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4606{ 4607 int32_t error = E1000_SUCCESS; 4608 uint16_t cap_off; 4609 4610 switch (hw->mac.type) { 4611 4612 case e1000_82571: 4613 case e1000_82572: 4614 case e1000_82573: 4615 case e1000_80003es2lan: 4616 cap_off = 0xE0; 4617 e1000_read_pci_cfg(hw, cap_off + reg, value); 4618 break; 4619 default: 4620 error = ~E1000_NOT_IMPLEMENTED; 4621 break; 4622 } 4623 4624 return (error); 4625} 4626 4627int32_t 4628e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, uint32_t size) 4629{ 4630 int32_t error = 0; 4631 4632 hw->dev_spec = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 4633 if (hw->dev_spec == NULL) 4634 error = ENOMEM; 4635 4636 return (error); 4637} 4638 4639void 4640e1000_free_dev_spec_struct(struct e1000_hw *hw) 4641{ 4642 if (hw->dev_spec != NULL) 4643 free(hw->dev_spec, M_DEVBUF); 4644 return; 4645} 4646 4647/* 4648 * Enable PCI Wake On Lan capability 4649 */ 4650void 4651em_enable_wakeup(device_t dev) 4652{ 4653 u16 cap, status; 4654 u8 id; 4655 4656 /* First find the capabilities pointer*/ 4657 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4658 /* Read the PM Capabilities */ 4659 id = pci_read_config(dev, cap, 1); 4660 if (id != PCIY_PMG) /* Something wrong */ 4661 return; 4662 /* OK, we have the power capabilities, so 4663 now get the status register */ 4664 cap += PCIR_POWER_STATUS; 4665 status = pci_read_config(dev, cap, 2); 4666 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4667 pci_write_config(dev, cap, status, 2); 4668 return; 4669} 4670 4671 4672/********************************************************************* 4673* 82544 Coexistence issue workaround. 4674* There are 2 issues. 4675* 1. Transmit Hang issue. 4676* To detect this issue, following equation can be used... 4677* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4678* If SUM[3:0] is in between 1 to 4, we will have this issue. 4679* 4680* 2. DAC issue. 4681* To detect this issue, following equation can be used... 4682* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4683* If SUM[3:0] is in between 9 to c, we will have this issue. 4684* 4685* 4686* WORKAROUND: 4687* Make sure we do not have ending address 4688* as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4689* 4690*************************************************************************/ 4691static uint32_t 4692em_fill_descriptors (bus_addr_t address, uint32_t length, 4693 PDESC_ARRAY desc_array) 4694{ 4695 /* Since issue is sensitive to length and address.*/ 4696 /* Let us first check the address...*/ 4697 uint32_t safe_terminator; 4698 if (length <= 4) { 4699 desc_array->descriptor[0].address = address; 4700 desc_array->descriptor[0].length = length; 4701 desc_array->elements = 1; 4702 return (desc_array->elements); 4703 } 4704 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + 4705 (length & 0xF)) & 0xF); 4706 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4707 if (safe_terminator == 0 || 4708 (safe_terminator > 4 && 4709 safe_terminator < 9) || 4710 (safe_terminator > 0xC && 4711 safe_terminator <= 0xF)) { 4712 desc_array->descriptor[0].address = address; 4713 desc_array->descriptor[0].length = length; 4714 desc_array->elements = 1; 4715 return (desc_array->elements); 4716 } 4717 4718 desc_array->descriptor[0].address = address; 4719 desc_array->descriptor[0].length = length - 4; 4720 desc_array->descriptor[1].address = address + (length - 4); 4721 desc_array->descriptor[1].length = 4; 4722 desc_array->elements = 2; 4723 return (desc_array->elements); 4724} 4725 4726/********************************************************************** 4727 * 4728 * Update the board statistics counters. 4729 * 4730 **********************************************************************/ 4731static void 4732em_update_stats_counters(struct adapter *adapter) 4733{ 4734 struct ifnet *ifp; 4735 4736 if(adapter->hw.media_type == e1000_media_type_copper || 4737 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4738 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4739 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4740 } 4741 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4742 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4743 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4744 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4745 4746 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4747 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4748 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4749 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4750 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4751 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4752 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4753 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4754 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4755 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4756 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4757 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4758 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4759 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4760 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4761 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4762 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4763 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4764 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4765 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4766 4767 /* For the 64-bit byte counters the low dword must be read first. */ 4768 /* Both registers clear on the read of the high dword */ 4769 4770 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, E1000_GORCL); 4771 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, E1000_GORCH); 4772 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, E1000_GOTCL); 4773 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 4774 4775 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4776 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4777 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4778 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4779 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4780 4781 adapter->stats.torl += E1000_READ_REG(&adapter->hw, E1000_TORL); 4782 adapter->stats.torh += E1000_READ_REG(&adapter->hw, E1000_TORH); 4783 adapter->stats.totl += E1000_READ_REG(&adapter->hw, E1000_TOTL); 4784 adapter->stats.toth += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4785 4786 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4787 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4788 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4789 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4790 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4791 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4792 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4793 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4794 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4795 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4796 4797 if (adapter->hw.mac.type >= e1000_82543) { 4798 adapter->stats.algnerrc += 4799 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4800 adapter->stats.rxerrc += 4801 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4802 adapter->stats.tncrs += 4803 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4804 adapter->stats.cexterr += 4805 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4806 adapter->stats.tsctc += 4807 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4808 adapter->stats.tsctfc += 4809 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4810 } 4811 ifp = adapter->ifp; 4812 4813 ifp->if_collisions = adapter->stats.colc; 4814 4815 /* Rx Errors */ 4816 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 4817 adapter->stats.crcerrs + adapter->stats.algnerrc + 4818 adapter->stats.ruc + adapter->stats.roc + 4819 adapter->stats.mpc + adapter->stats.cexterr; 4820 4821 /* Tx Errors */ 4822 ifp->if_oerrors = adapter->stats.ecol + 4823 adapter->stats.latecol + adapter->watchdog_events; 4824} 4825 4826 4827/********************************************************************** 4828 * 4829 * This routine is called only when em_display_debug_stats is enabled. 4830 * This routine provides a way to take a look at important statistics 4831 * maintained by the driver and hardware. 4832 * 4833 **********************************************************************/ 4834static void 4835em_print_debug_info(struct adapter *adapter) 4836{ 4837 device_t dev = adapter->dev; 4838 uint8_t *hw_addr = adapter->hw.hw_addr; 4839 4840 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 4841 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 4842 E1000_READ_REG(&adapter->hw, E1000_CTRL), 4843 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 4844 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 4845 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 4846 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 4847 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 4848 adapter->hw.mac.fc_high_water, 4849 adapter->hw.mac.fc_low_water); 4850 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 4851 E1000_READ_REG(&adapter->hw, E1000_TIDV), 4852 E1000_READ_REG(&adapter->hw, E1000_TADV)); 4853 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 4854 E1000_READ_REG(&adapter->hw, E1000_RDTR), 4855 E1000_READ_REG(&adapter->hw, E1000_RADV)); 4856 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 4857 (long long)adapter->tx_fifo_wrk_cnt, 4858 (long long)adapter->tx_fifo_reset_cnt); 4859 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4860 E1000_READ_REG(&adapter->hw, E1000_TDH), 4861 E1000_READ_REG(&adapter->hw, E1000_TDT)); 4862 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4863 E1000_READ_REG(&adapter->hw, E1000_RDH), 4864 E1000_READ_REG(&adapter->hw, E1000_RDT)); 4865 device_printf(dev, "Num Tx descriptors avail = %d\n", 4866 adapter->num_tx_desc_avail); 4867 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 4868 adapter->no_tx_desc_avail1); 4869 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 4870 adapter->no_tx_desc_avail2); 4871 device_printf(dev, "Std mbuf failed = %ld\n", 4872 adapter->mbuf_alloc_failed); 4873 device_printf(dev, "Std mbuf cluster failed = %ld\n", 4874 adapter->mbuf_cluster_failed); 4875 device_printf(dev, "Driver dropped packets = %ld\n", 4876 adapter->dropped_pkts); 4877 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 4878 adapter->no_tx_dma_setup); 4879} 4880 4881static void 4882em_print_hw_stats(struct adapter *adapter) 4883{ 4884 device_t dev = adapter->dev; 4885 4886 device_printf(dev, "Excessive collisions = %lld\n", 4887 (long long)adapter->stats.ecol); 4888#if (DEBUG_HW > 0) /* Dont output these errors normally */ 4889 device_printf(dev, "Symbol errors = %lld\n", 4890 (long long)adapter->stats.symerrs); 4891#endif 4892 device_printf(dev, "Sequence errors = %lld\n", 4893 (long long)adapter->stats.sec); 4894 device_printf(dev, "Defer count = %lld\n", 4895 (long long)adapter->stats.dc); 4896 device_printf(dev, "Missed Packets = %lld\n", 4897 (long long)adapter->stats.mpc); 4898 device_printf(dev, "Receive No Buffers = %lld\n", 4899 (long long)adapter->stats.rnbc); 4900 /* RLEC is inaccurate on some hardware, calculate our own. */ 4901 device_printf(dev, "Receive Length Errors = %lld\n", 4902 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 4903 device_printf(dev, "Receive errors = %lld\n", 4904 (long long)adapter->stats.rxerrc); 4905 device_printf(dev, "Crc errors = %lld\n", 4906 (long long)adapter->stats.crcerrs); 4907 device_printf(dev, "Alignment errors = %lld\n", 4908 (long long)adapter->stats.algnerrc); 4909 device_printf(dev, "Carrier extension errors = %lld\n", 4910 (long long)adapter->stats.cexterr); 4911 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 4912 device_printf(dev, "watchdog timeouts = %ld\n", 4913 adapter->watchdog_events); 4914 device_printf(dev, "XON Rcvd = %lld\n", 4915 (long long)adapter->stats.xonrxc); 4916 device_printf(dev, "XON Xmtd = %lld\n", 4917 (long long)adapter->stats.xontxc); 4918 device_printf(dev, "XOFF Rcvd = %lld\n", 4919 (long long)adapter->stats.xoffrxc); 4920 device_printf(dev, "XOFF Xmtd = %lld\n", 4921 (long long)adapter->stats.xofftxc); 4922 device_printf(dev, "Good Packets Rcvd = %lld\n", 4923 (long long)adapter->stats.gprc); 4924 device_printf(dev, "Good Packets Xmtd = %lld\n", 4925 (long long)adapter->stats.gptc); 4926 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 4927 (long long)adapter->stats.tsctc); 4928 device_printf(dev, "TSO Contexts Failed = %lld\n", 4929 (long long)adapter->stats.tsctfc); 4930} 4931 4932static int 4933em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4934{ 4935 struct adapter *adapter; 4936 int error; 4937 int result; 4938 4939 result = -1; 4940 error = sysctl_handle_int(oidp, &result, 0, req); 4941 4942 if (error || !req->newptr) 4943 return (error); 4944 4945 if (result == 1) { 4946 adapter = (struct adapter *)arg1; 4947 em_print_debug_info(adapter); 4948 } 4949 4950 return (error); 4951} 4952 4953 4954static int 4955em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4956{ 4957 struct adapter *adapter; 4958 int error; 4959 int result; 4960 4961 result = -1; 4962 error = sysctl_handle_int(oidp, &result, 0, req); 4963 4964 if (error || !req->newptr) 4965 return (error); 4966 4967 if (result == 1) { 4968 adapter = (struct adapter *)arg1; 4969 em_print_hw_stats(adapter); 4970 } 4971 4972 return (error); 4973} 4974 4975static int 4976em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4977{ 4978 struct em_int_delay_info *info; 4979 struct adapter *adapter; 4980 uint32_t regval; 4981 int error; 4982 int usecs; 4983 int ticks; 4984 4985 info = (struct em_int_delay_info *)arg1; 4986 usecs = info->value; 4987 error = sysctl_handle_int(oidp, &usecs, 0, req); 4988 if (error != 0 || req->newptr == NULL) 4989 return (error); 4990 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4991 return (EINVAL); 4992 info->value = usecs; 4993 ticks = EM_USECS_TO_TICKS(usecs); 4994 4995 adapter = info->adapter; 4996 4997 EM_LOCK(adapter); 4998 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4999 regval = (regval & ~0xffff) | (ticks & 0xffff); 5000 /* Handle a few special cases. */ 5001 switch (info->offset) { 5002 case E1000_RDTR: 5003 break; 5004 case E1000_TIDV: 5005 if (ticks == 0) { 5006 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 5007 /* Don't write 0 into the TIDV register. */ 5008 regval++; 5009 } else 5010 if (adapter->hw.mac.type != e1000_82575) 5011 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 5012 break; 5013 } 5014 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 5015 EM_UNLOCK(adapter); 5016 return (0); 5017} 5018 5019static void 5020em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 5021 const char *description, struct em_int_delay_info *info, 5022 int offset, int value) 5023{ 5024 info->adapter = adapter; 5025 info->offset = offset; 5026 info->value = value; 5027 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 5028 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5029 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5030 info, 0, em_sysctl_int_delay, "I", description); 5031} 5032 5033#ifndef DEVICE_POLLING 5034static void 5035em_add_rx_process_limit(struct adapter *adapter, const char *name, 5036 const char *description, int *limit, int value) 5037{ 5038 *limit = value; 5039 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 5040 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5041 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 5042} 5043#endif 5044