if_em.c revision 169397
1210311Sjmallett/************************************************************************** 2210311Sjmallett 3210311SjmallettCopyright (c) 2001-2007, Intel Corporation 4210311SjmallettAll rights reserved. 5210311Sjmallett 6210311SjmallettRedistribution and use in source and binary forms, with or without 7210311Sjmallettmodification, are permitted provided that the following conditions are met: 8210311Sjmallett 9210311Sjmallett 1. Redistributions of source code must retain the above copyright notice, 10210311Sjmallett this list of conditions and the following disclaimer. 11210311Sjmallett 12210311Sjmallett 2. Redistributions in binary form must reproduce the above copyright 13210311Sjmallett notice, this list of conditions and the following disclaimer in the 14210311Sjmallett documentation and/or other materials provided with the distribution. 15210311Sjmallett 16210311Sjmallett 3. Neither the name of the Intel Corporation nor the names of its 17210311Sjmallett contributors may be used to endorse or promote products derived from 18210311Sjmallett this software without specific prior written permission. 19210311Sjmallett 20210311SjmallettTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21210311SjmallettAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22210311SjmallettIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23210311SjmallettARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24210311SjmallettLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25210311SjmallettCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26210311SjmallettSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27210311SjmallettINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28210311SjmallettCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29210311SjmallettARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30210311SjmallettPOSSIBILITY OF SUCH DAMAGE. 31210311Sjmallett 32210311Sjmallett***************************************************************************/ 33210311Sjmallett 34210311Sjmallett/*$FreeBSD: head/sys/dev/em/if_em.c 169397 2007-05-09 00:41:45Z jfv $*/ 35210311Sjmallett 36210311Sjmallett#ifdef HAVE_KERNEL_OPTION_HEADERS 37210311Sjmallett#include "opt_device_polling.h" 38210311Sjmallett#endif 39210311Sjmallett 40216092Sjmallett#include <sys/param.h> 41210311Sjmallett#include <sys/systm.h> 42210311Sjmallett#include <sys/bus.h> 43210311Sjmallett#include <sys/endian.h> 44210311Sjmallett#include <sys/kernel.h> 45210311Sjmallett#include <sys/kthread.h> 46232812Sjmallett#include <sys/malloc.h> 47210311Sjmallett#include <sys/mbuf.h> 48210311Sjmallett#include <sys/module.h> 49210311Sjmallett#include <sys/rman.h> 50210311Sjmallett#include <sys/socket.h> 51210311Sjmallett#include <sys/sockio.h> 52210311Sjmallett#include <sys/sysctl.h> 53210311Sjmallett#include <sys/taskqueue.h> 54210311Sjmallett 55210311Sjmallett#include <machine/bus.h> 56232812Sjmallett#include <machine/resource.h> 57232812Sjmallett 58210311Sjmallett#include <net/bpf.h> 59210311Sjmallett#include <net/ethernet.h> 60232812Sjmallett#include <net/if.h> 61232812Sjmallett#include <net/if_arp.h> 62210311Sjmallett#include <net/if_dl.h> 63210311Sjmallett#include <net/if_media.h> 64210311Sjmallett 65210311Sjmallett#include <net/if_types.h> 66210311Sjmallett#include <net/if_vlan_var.h> 67210311Sjmallett 68210311Sjmallett#include <netinet/in_systm.h> 69210311Sjmallett#include <netinet/in.h> 70210311Sjmallett#include <netinet/if_ether.h> 71210311Sjmallett#include <netinet/ip.h> 72210311Sjmallett#include <netinet/ip6.h> 73210311Sjmallett#include <netinet/tcp.h> 74210311Sjmallett#include <netinet/udp.h> 75210311Sjmallett 76210311Sjmallett#include <machine/in_cksum.h> 77210311Sjmallett#include <dev/pci/pcivar.h> 78294883Sjhibbits#include <dev/pci/pcireg.h> 79294883Sjhibbits 80210311Sjmallett#include "e1000_api.h" 81210311Sjmallett#include "e1000_82575.h" 82210311Sjmallett#include "if_em.h" 83213090Sjmallett 84213090Sjmallett/********************************************************************* 85216092Sjmallett * Set this to one to display debug statistics 86216092Sjmallett *********************************************************************/ 87216092Sjmallettint em_display_debug_stats = 0; 88216092Sjmallett 89216092Sjmallett/********************************************************************* 90210311Sjmallett * Driver version: 91210311Sjmallett *********************************************************************/ 92210311Sjmallettchar em_driver_version[] = "Version - 6.5.0"; 93210311Sjmallett 94216092Sjmallett 95271712Sadrian/********************************************************************* 96216092Sjmallett * PCI Device ID Table 97210311Sjmallett * 98210311Sjmallett * Used by probe to select devices to load on 99210311Sjmallett * Last field stores an index into e1000_strings 100216092Sjmallett * Last entry must be all 0s 101271712Sadrian * 102216092Sjmallett * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 103210311Sjmallett *********************************************************************/ 104210311Sjmallett 105210311Sjmallettstatic em_vendor_info_t em_vendor_info_array[] = 106210311Sjmallett{ 107210311Sjmallett /* Intel(R) PRO/1000 Network Connection */ 108210311Sjmallett { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 109210311Sjmallett { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 110210311Sjmallett { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 111210311Sjmallett { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 112210311Sjmallett { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 113257338Snwhitehorn 114210311Sjmallett { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115210311Sjmallett { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 116210311Sjmallett { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 117210311Sjmallett { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 118210311Sjmallett { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 119210311Sjmallett { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 120210311Sjmallett { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 121210311Sjmallett 122210311Sjmallett { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 123210311Sjmallett 124210311Sjmallett { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125210311Sjmallett { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126210311Sjmallett 127210311Sjmallett { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 128210311Sjmallett { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129210311Sjmallett { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130210311Sjmallett { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 131210311Sjmallett 132210311Sjmallett { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133210311Sjmallett { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 134210311Sjmallett { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135210311Sjmallett { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136210311Sjmallett { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 137210311Sjmallett 138210311Sjmallett { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139210311Sjmallett { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140210311Sjmallett { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 141210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 144210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 146210311Sjmallett { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 147210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 148210311Sjmallett 149210311Sjmallett { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 150210311Sjmallett { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 151210311Sjmallett { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 152210311Sjmallett 153210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 157210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 158210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 159210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 160210311Sjmallett { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 161210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 162210311Sjmallett { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 163210311Sjmallett { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 164210311Sjmallett { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 165210311Sjmallett { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 166210311Sjmallett 167210311Sjmallett { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 168210311Sjmallett { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 169210311Sjmallett { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 170210311Sjmallett { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 171210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 172210311Sjmallett { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 173210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 174210311Sjmallett { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 175294883Sjhibbits PCI_ANY_ID, PCI_ANY_ID, 0}, 176210311Sjmallett { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 177210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 178210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 179210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 180210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 181210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 182210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 183210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 184210311Sjmallett { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 185210311Sjmallett 186210311Sjmallett { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 187210311Sjmallett { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 188210311Sjmallett { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 189210311Sjmallett { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 190210311Sjmallett { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 191210311Sjmallett 192210311Sjmallett { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 193210311Sjmallett { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 194210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 195210311Sjmallett { 0x8086, E1000_DEV_ID_82575EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 196210311Sjmallett { 0x8086, E1000_DEV_ID_82575EM_FIBER_SERDES, 197210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 198210311Sjmallett { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 199210311Sjmallett PCI_ANY_ID, PCI_ANY_ID, 0}, 200210311Sjmallett /* required last entry */ 201210311Sjmallett { 0, 0, 0, 0, 0} 202210311Sjmallett}; 203210311Sjmallett 204210311Sjmallett/********************************************************************* 205210311Sjmallett * Table of branding strings for all supported NICs. 206210311Sjmallett *********************************************************************/ 207210311Sjmallett 208210311Sjmallettstatic char *em_strings[] = { 209210311Sjmallett "Intel(R) PRO/1000 Network Connection" 210210311Sjmallett}; 211210311Sjmallett 212271712Sadrian/********************************************************************* 213210311Sjmallett * Function prototypes 214210311Sjmallett *********************************************************************/ 215210311Sjmallettstatic int em_probe(device_t); 216210311Sjmallettstatic int em_attach(device_t); 217210311Sjmallettstatic int em_detach(device_t); 218210311Sjmallettstatic int em_shutdown(device_t); 219210311Sjmallettstatic int em_suspend(device_t); 220210311Sjmallettstatic int em_resume(device_t); 221210311Sjmallettstatic void em_start(struct ifnet *); 222210311Sjmallettstatic void em_start_locked(struct ifnet *ifp); 223216092Sjmallettstatic int em_ioctl(struct ifnet *, u_long, caddr_t); 224216092Sjmallettstatic void em_watchdog(struct adapter *); 225216092Sjmallettstatic void em_init(void *); 226210311Sjmallettstatic void em_init_locked(struct adapter *); 227210311Sjmallettstatic void em_stop(void *); 228210311Sjmallettstatic void em_media_status(struct ifnet *, struct ifmediareq *); 229210311Sjmallettstatic int em_media_change(struct ifnet *); 230210311Sjmallettstatic void em_identify_hardware(struct adapter *); 231216092Sjmallettstatic int em_allocate_pci_resources(struct adapter *); 232216092Sjmallettstatic int em_allocate_intr(struct adapter *); 233216092Sjmallettstatic void em_free_intr(struct adapter *); 234210311Sjmallettstatic void em_free_pci_resources(struct adapter *); 235216092Sjmallettstatic void em_local_timer(void *); 236216092Sjmallettstatic int em_hardware_init(struct adapter *); 237216092Sjmallettstatic void em_setup_interface(device_t, struct adapter *); 238210311Sjmallettstatic int em_setup_transmit_structures(struct adapter *); 239210311Sjmallettstatic void em_initialize_transmit_unit(struct adapter *); 240210311Sjmallettstatic int em_setup_receive_structures(struct adapter *); 241216092Sjmallettstatic void em_initialize_receive_unit(struct adapter *); 242210311Sjmallettstatic void em_enable_intr(struct adapter *); 243210311Sjmallettstatic void em_disable_intr(struct adapter *); 244210311Sjmallettstatic void em_free_transmit_structures(struct adapter *); 245210311Sjmallettstatic void em_free_receive_structures(struct adapter *); 246210311Sjmallettstatic void em_update_stats_counters(struct adapter *); 247210311Sjmallettstatic void em_txeof(struct adapter *); 248210311Sjmallettstatic int em_allocate_receive_structures(struct adapter *); 249210311Sjmallettstatic int em_allocate_transmit_structures(struct adapter *); 250210311Sjmallettstatic int em_rxeof(struct adapter *, int); 251210311Sjmallett#ifndef __NO_STRICT_ALIGNMENT 252210311Sjmallettstatic int em_fixup_rx(struct adapter *); 253210311Sjmallett#endif 254210311Sjmallettstatic void em_receive_checksum(struct adapter *, struct e1000_rx_desc *, 255210311Sjmallett struct mbuf *); 256210311Sjmallettstatic void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 257210311Sjmallett uint32_t *, uint32_t *); 258213090Sjmallettstatic boolean_t em_tx_adv_ctx_setup(struct adapter *, struct mbuf *); 259213090Sjmallettstatic boolean_t em_tso_setup(struct adapter *, struct mbuf *, uint32_t *, 260213090Sjmallett uint32_t *); 261213090Sjmallettstatic boolean_t em_tso_adv_setup(struct adapter *, struct mbuf *, uint32_t *); 262213090Sjmallettstatic void em_set_promisc(struct adapter *); 263213090Sjmallettstatic void em_disable_promisc(struct adapter *); 264213090Sjmallettstatic void em_set_multi(struct adapter *); 265213090Sjmallettstatic void em_print_hw_stats(struct adapter *); 266213090Sjmallettstatic void em_update_link_status(struct adapter *); 267213090Sjmallettstatic int em_get_buf(struct adapter *, int); 268213090Sjmallettstatic void em_enable_vlans(struct adapter *); 269213090Sjmallettstatic int em_encap(struct adapter *, struct mbuf **); 270213090Sjmallettstatic int em_adv_encap(struct adapter *, struct mbuf **); 271216092Sjmallettstatic void em_smartspeed(struct adapter *); 272216092Sjmallettstatic int em_82547_fifo_workaround(struct adapter *, int); 273216092Sjmallettstatic void em_82547_update_fifo_head(struct adapter *, int); 274216092Sjmallettstatic int em_82547_tx_fifo_reset(struct adapter *); 275216092Sjmallettstatic void em_82547_move_tail(void *); 276216092Sjmallettstatic int em_dma_malloc(struct adapter *, bus_size_t, 277216092Sjmallett struct em_dma_alloc *, int); 278216092Sjmallettstatic void em_dma_free(struct adapter *, struct em_dma_alloc *); 279216092Sjmallettstatic void em_print_debug_info(struct adapter *); 280216092Sjmallettstatic int em_is_valid_ether_addr(uint8_t *); 281216092Sjmallettstatic int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 282216092Sjmallettstatic int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 283216092Sjmallettstatic uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 284216092Sjmallett PDESC_ARRAY desc_array); 285216092Sjmallettstatic int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 286216092Sjmallettstatic void em_add_int_delay_sysctl(struct adapter *, const char *, 287216092Sjmallett const char *, struct em_int_delay_info *, int, int); 288216092Sjmallett/* Management and WOL Support */ 289216092Sjmallettstatic void em_init_manageability(struct adapter *); 290216092Sjmallettstatic void em_release_manageability(struct adapter *); 291216092Sjmallettstatic void em_get_hw_control(struct adapter *); 292216092Sjmallettstatic void em_release_hw_control(struct adapter *); 293216092Sjmallettstatic void em_enable_wakeup(device_t); 294216092Sjmallett 295216092Sjmallett#ifdef DEVICE_POLLING 296216092Sjmallettstatic poll_handler_t em_poll; 297216092Sjmallettstatic void em_intr(void *); 298216092Sjmallett#else 299216092Sjmallettstatic int em_intr_fast(void *); 300216092Sjmallettstatic void em_add_rx_process_limit(struct adapter *, const char *, 301216092Sjmallett const char *, int *, int); 302216092Sjmallettstatic void em_handle_rxtx(void *context, int pending); 303216092Sjmallettstatic void em_handle_link(void *context, int pending); 304216092Sjmallett#endif 305216092Sjmallett 306216092Sjmallett/********************************************************************* 307216092Sjmallett * FreeBSD Device Interface Entry Points 308216092Sjmallett *********************************************************************/ 309216092Sjmallett 310216092Sjmallettstatic device_method_t em_methods[] = { 311216092Sjmallett /* Device interface */ 312216092Sjmallett DEVMETHOD(device_probe, em_probe), 313216092Sjmallett DEVMETHOD(device_attach, em_attach), 314216092Sjmallett DEVMETHOD(device_detach, em_detach), 315210311Sjmallett DEVMETHOD(device_shutdown, em_shutdown), 316210311Sjmallett DEVMETHOD(device_suspend, em_suspend), 317210311Sjmallett DEVMETHOD(device_resume, em_resume), 318210311Sjmallett {0, 0} 319210311Sjmallett}; 320210311Sjmallett 321210311Sjmallettstatic driver_t em_driver = { 322210311Sjmallett "em", em_methods, sizeof(struct adapter), 323210311Sjmallett}; 324210311Sjmallett 325210311Sjmallettstatic devclass_t em_devclass; 326210311SjmallettDRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 327210311SjmallettMODULE_DEPEND(em, pci, 1, 1, 1); 328210311SjmallettMODULE_DEPEND(em, ether, 1, 1, 1); 329210311Sjmallett 330210311Sjmallett/********************************************************************* 331210311Sjmallett * Tunable default values. 332210311Sjmallett *********************************************************************/ 333210311Sjmallett 334210311Sjmallett#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 335210311Sjmallett#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 336210311Sjmallett#define M_TSO_LEN 66 337210311Sjmallett 338210311Sjmallettstatic int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 339210311Sjmallettstatic int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 340210311Sjmallettstatic int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 341210311Sjmallettstatic int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 342210311Sjmallettstatic int em_rxd = EM_DEFAULT_RXD; 343210311Sjmallettstatic int em_txd = EM_DEFAULT_TXD; 344210311Sjmallettstatic int em_smart_pwr_down = FALSE; 345216092Sjmallett 346216092SjmallettTUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 347271712SadrianTUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 348216092SjmallettTUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 349216092SjmallettTUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 350216092SjmallettTUNABLE_INT("hw.em.rxd", &em_rxd); 351216092SjmallettTUNABLE_INT("hw.em.txd", &em_txd); 352216092SjmallettTUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 353216092Sjmallett#ifndef DEVICE_POLLING 354216092Sjmallett/* How many packets rxeof tries to clean at a time */ 355216092Sjmallettstatic int em_rx_process_limit = 100; 356216092SjmallettTUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 357216092Sjmallett#endif 358216092Sjmallett/* Global used in WOL setup with multiport cards */ 359216092Sjmallettstatic int global_quad_port_a = 0; 360216092Sjmallett 361216092Sjmallett/********************************************************************* 362216092Sjmallett * Device identification routine 363216092Sjmallett * 364216092Sjmallett * em_probe determines if the driver should be loaded on 365216092Sjmallett * adapter based on PCI vendor/device id of the adapter. 366216092Sjmallett * 367210311Sjmallett * return BUS_PROBE_DEFAULT on success, positive on failure 368210311Sjmallett *********************************************************************/ 369210311Sjmallett 370210311Sjmallettstatic int 371210311Sjmallettem_probe(device_t dev) 372210311Sjmallett{ 373210311Sjmallett char adapter_name[60]; 374210311Sjmallett uint16_t pci_vendor_id = 0; 375210311Sjmallett uint16_t pci_device_id = 0; 376210311Sjmallett uint16_t pci_subvendor_id = 0; 377210311Sjmallett uint16_t pci_subdevice_id = 0; 378210311Sjmallett em_vendor_info_t *ent; 379210311Sjmallett 380210311Sjmallett INIT_DEBUGOUT("em_probe: begin"); 381210311Sjmallett 382210311Sjmallett pci_vendor_id = pci_get_vendor(dev); 383210311Sjmallett if (pci_vendor_id != EM_VENDOR_ID) 384210311Sjmallett return (ENXIO); 385210311Sjmallett 386210311Sjmallett pci_device_id = pci_get_device(dev); 387210311Sjmallett pci_subvendor_id = pci_get_subvendor(dev); 388210311Sjmallett pci_subdevice_id = pci_get_subdevice(dev); 389210311Sjmallett 390210311Sjmallett ent = em_vendor_info_array; 391216092Sjmallett while (ent->vendor_id != 0) { 392210311Sjmallett if ((pci_vendor_id == ent->vendor_id) && 393271712Sadrian (pci_device_id == ent->device_id) && 394216092Sjmallett 395216092Sjmallett ((pci_subvendor_id == ent->subvendor_id) || 396216092Sjmallett (ent->subvendor_id == PCI_ANY_ID)) && 397216092Sjmallett 398216092Sjmallett ((pci_subdevice_id == ent->subdevice_id) || 399216092Sjmallett (ent->subdevice_id == PCI_ANY_ID))) { 400216092Sjmallett sprintf(adapter_name, "%s %s", 401216092Sjmallett em_strings[ent->index], 402216092Sjmallett em_driver_version); 403216092Sjmallett device_set_desc_copy(dev, adapter_name); 404216092Sjmallett return (BUS_PROBE_DEFAULT); 405216092Sjmallett } 406216092Sjmallett ent++; 407216092Sjmallett } 408216092Sjmallett 409216092Sjmallett return (ENXIO); 410216092Sjmallett} 411216092Sjmallett 412216092Sjmallett/********************************************************************* 413216092Sjmallett * Device initialization routine 414210311Sjmallett * 415210311Sjmallett * The attach entry point is called when the driver is being loaded. 416210311Sjmallett * This routine identifies the type of hardware, allocates all resources 417210311Sjmallett * and initializes the hardware. 418210311Sjmallett * 419210311Sjmallett * return 0 on success, positive on failure 420210311Sjmallett *********************************************************************/ 421210311Sjmallett 422210311Sjmallettstatic int 423210311Sjmallettem_attach(device_t dev) 424210311Sjmallett{ 425210311Sjmallett struct adapter *adapter; 426210311Sjmallett int tsize, rsize; 427210311Sjmallett int error = 0; 428210311Sjmallett u16 eeprom_data, device_id; 429210311Sjmallett 430210311Sjmallett INIT_DEBUGOUT("em_attach: begin"); 431210311Sjmallett 432210311Sjmallett adapter = device_get_softc(dev); 433210311Sjmallett adapter->dev = adapter->osdep.dev = dev; 434210311Sjmallett EM_LOCK_INIT(adapter, device_get_nameunit(dev)); 435210311Sjmallett 436210311Sjmallett /* SYSCTL stuff */ 437210311Sjmallett SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 438210311Sjmallett SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 439210311Sjmallett OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 440210311Sjmallett em_sysctl_debug_info, "I", "Debug Information"); 441210311Sjmallett 442210311Sjmallett SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 443210311Sjmallett SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 444210311Sjmallett OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 445210311Sjmallett em_sysctl_stats, "I", "Statistics"); 446210311Sjmallett 447210311Sjmallett callout_init_mtx(&adapter->timer, &adapter->mtx, 0); 448210311Sjmallett callout_init_mtx(&adapter->tx_fifo_timer, &adapter->mtx, 0); 449210311Sjmallett 450210311Sjmallett /* Determine hardware revision */ 451210311Sjmallett em_identify_hardware(adapter); 452210311Sjmallett 453210311Sjmallett /* Setup PCI resources */ 454210311Sjmallett if (em_allocate_pci_resources(adapter)) { 455210311Sjmallett device_printf(dev, "Allocation of PCI resources failed\n"); 456210311Sjmallett error = ENXIO; 457210311Sjmallett goto err_pci; 458210311Sjmallett } 459210311Sjmallett 460210311Sjmallett /* 461210311Sjmallett ** For ICH8 and family we need to 462210311Sjmallett ** map the flash memory, and this 463210311Sjmallett ** must happen after the MAC is 464210311Sjmallett ** identified 465210311Sjmallett */ 466210311Sjmallett if ((adapter->hw.mac.type == e1000_ich8lan) || 467210311Sjmallett (adapter->hw.mac.type == e1000_ich9lan)) { 468210311Sjmallett int rid = EM_BAR_TYPE_FLASH; 469213090Sjmallett adapter->flash_mem = bus_alloc_resource_any(dev, 470216092Sjmallett SYS_RES_MEMORY, &rid, RF_ACTIVE); 471216092Sjmallett /* This is used in the shared code */ 472216092Sjmallett adapter->hw.flash_address = (u8 *)adapter->flash_mem; 473216092Sjmallett adapter->osdep.flash_bus_space_tag = 474210311Sjmallett rman_get_bustag(adapter->flash_mem); 475210311Sjmallett adapter->osdep.flash_bus_space_handle = 476210311Sjmallett rman_get_bushandle(adapter->flash_mem); 477210311Sjmallett } 478210311Sjmallett 479210311Sjmallett /* Do Shared Code initialization */ 480210311Sjmallett if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 481210311Sjmallett device_printf(dev, "Setup of Shared code failed\n"); 482210311Sjmallett error = ENXIO; 483210311Sjmallett goto err_pci; 484210311Sjmallett } 485210311Sjmallett 486210311Sjmallett e1000_get_bus_info(&adapter->hw); 487210311Sjmallett 488 /* Set up some sysctls for the tunable interrupt delays */ 489 em_add_int_delay_sysctl(adapter, "rx_int_delay", 490 "receive interrupt delay in usecs", &adapter->rx_int_delay, 491 E1000_REGISTER(&adapter->hw, E1000_RDTR), em_rx_int_delay_dflt); 492 em_add_int_delay_sysctl(adapter, "tx_int_delay", 493 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 494 E1000_REGISTER(&adapter->hw, E1000_TIDV), em_tx_int_delay_dflt); 495 if (adapter->hw.mac.type >= e1000_82540) { 496 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 497 "receive interrupt delay limit in usecs", 498 &adapter->rx_abs_int_delay, 499 E1000_REGISTER(&adapter->hw, E1000_RADV), 500 em_rx_abs_int_delay_dflt); 501 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 502 "transmit interrupt delay limit in usecs", 503 &adapter->tx_abs_int_delay, 504 E1000_REGISTER(&adapter->hw, E1000_TADV), 505 em_tx_abs_int_delay_dflt); 506 } 507 508#ifndef DEVICE_POLLING 509 /* Sysctls for limiting the amount of work done in the taskqueue */ 510 em_add_rx_process_limit(adapter, "rx_processing_limit", 511 "max number of rx packets to process", &adapter->rx_process_limit, 512 em_rx_process_limit); 513#endif 514 515 /* 516 * Validate number of transmit and receive descriptors. It 517 * must not exceed hardware maximum, and must be multiple 518 * of E1000_DBA_ALIGN. 519 */ 520 if (((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN) != 0 || 521 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 522 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 523 (em_txd < EM_MIN_TXD)) { 524 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 525 EM_DEFAULT_TXD, em_txd); 526 adapter->num_tx_desc = EM_DEFAULT_TXD; 527 } else 528 adapter->num_tx_desc = em_txd; 529 if (((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN) != 0 || 530 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 531 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 532 (em_rxd < EM_MIN_RXD)) { 533 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 534 EM_DEFAULT_RXD, em_rxd); 535 adapter->num_rx_desc = EM_DEFAULT_RXD; 536 } else 537 adapter->num_rx_desc = em_rxd; 538 539 adapter->hw.mac.autoneg = DO_AUTO_NEG; 540 adapter->hw.phy.wait_for_link = FALSE; 541 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 542 adapter->rx_buffer_len = 2048; 543 544 e1000_init_script_state_82541(&adapter->hw, TRUE); 545 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 546 547 /* Copper options */ 548 if (adapter->hw.media_type == e1000_media_type_copper) { 549 adapter->hw.phy.mdix = AUTO_ALL_MODES; 550 adapter->hw.phy.disable_polarity_correction = FALSE; 551 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 552 } 553 554 /* 555 * Set the max frame size assuming standard ethernet 556 * sized frames. 557 */ 558 adapter->hw.mac.max_frame_size = 559 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 560 561 adapter->hw.mac.min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; 562 563 /* 564 * This controls when hardware reports transmit completion 565 * status. 566 */ 567 adapter->hw.mac.report_tx_early = 1; 568 569 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 570 EM_DBA_ALIGN); 571 572 /* Allocate Transmit Descriptor ring */ 573 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 574 device_printf(dev, "Unable to allocate tx_desc memory\n"); 575 error = ENOMEM; 576 goto err_tx_desc; 577 } 578 adapter->tx_desc_base = 579 (struct e1000_tx_desc *)adapter->txdma.dma_vaddr; 580 581 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 582 EM_DBA_ALIGN); 583 584 /* Allocate Receive Descriptor ring */ 585 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 586 device_printf(dev, "Unable to allocate rx_desc memory\n"); 587 error = ENOMEM; 588 goto err_rx_desc; 589 } 590 adapter->rx_desc_base = 591 (struct e1000_rx_desc *)adapter->rxdma.dma_vaddr; 592 593 /* Make sure we have a good EEPROM before we read from it */ 594 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 595 /* 596 ** Some PCI-E parts fail the first check due to 597 ** the link being in sleep state, call it again, 598 ** if it fails a second time its a real issue. 599 */ 600 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 601 device_printf(dev, 602 "The EEPROM Checksum Is Not Valid\n"); 603 error = EIO; 604 goto err_hw_init; 605 } 606 } 607 608 if (e1000_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { 609 device_printf(dev, "EEPROM read error " 610 "reading part number\n"); 611 error = EIO; 612 goto err_hw_init; 613 } 614 615 /* Initialize the hardware */ 616 if (em_hardware_init(adapter)) { 617 device_printf(dev, "Unable to initialize the hardware\n"); 618 error = EIO; 619 goto err_hw_init; 620 } 621 622 /* Copy the permanent MAC address out of the EEPROM */ 623 if (e1000_read_mac_addr(&adapter->hw) < 0) { 624 device_printf(dev, "EEPROM read error while reading MAC" 625 " address\n"); 626 error = EIO; 627 goto err_hw_init; 628 } 629 630 if (!em_is_valid_ether_addr(adapter->hw.mac.addr)) { 631 device_printf(dev, "Invalid MAC address\n"); 632 error = EIO; 633 goto err_hw_init; 634 } 635 636 /* Setup OS specific network interface */ 637 em_setup_interface(dev, adapter); 638 639 em_allocate_intr(adapter); 640 641 /* Initialize statistics */ 642 em_update_stats_counters(adapter); 643 644 adapter->hw.mac.get_link_status = 1; 645 em_update_link_status(adapter); 646 647 /* Indicate SOL/IDER usage */ 648 if (e1000_check_reset_block(&adapter->hw)) 649 device_printf(dev, 650 "PHY reset is blocked due to SOL/IDER session.\n"); 651 652 /* Determine if we have to control management hardware */ 653 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 654 655 /* 656 * Setup Wake-on-Lan 657 */ 658 switch (adapter->hw.mac.type) { 659 660 case e1000_82542: 661 case e1000_82543: 662 break; 663 case e1000_82546: 664 case e1000_82546_rev_3: 665 case e1000_82571: 666 case e1000_80003es2lan: 667 if (adapter->hw.bus.func == 1) 668 e1000_read_nvm(&adapter->hw, 669 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 670 else 671 e1000_read_nvm(&adapter->hw, 672 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 673 eeprom_data &= EM_EEPROM_APME; 674 break; 675 default: 676 /* APME bit in EEPROM is mapped to WUC.APME */ 677 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & 678 E1000_WUC_APME; 679 break; 680 } 681 if (eeprom_data) 682 adapter->wol = E1000_WUFC_MAG; 683 /* 684 * We have the eeprom settings, now apply the special cases 685 * where the eeprom may be wrong or the board won't support 686 * wake on lan on a particular port 687 */ 688 device_id = pci_get_device(dev); 689 switch (device_id) { 690 case E1000_DEV_ID_82546GB_PCIE: 691 adapter->wol = 0; 692 break; 693 case E1000_DEV_ID_82546EB_FIBER: 694 case E1000_DEV_ID_82546GB_FIBER: 695 case E1000_DEV_ID_82571EB_FIBER: 696 /* Wake events only supported on port A for dual fiber 697 * regardless of eeprom setting */ 698 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 699 E1000_STATUS_FUNC_1) 700 adapter->wol = 0; 701 break; 702 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 703 case E1000_DEV_ID_82571EB_QUAD_COPPER: 704 case E1000_DEV_ID_82571EB_QUAD_FIBER: 705 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 706 /* if quad port adapter, disable WoL on all but port A */ 707 if (global_quad_port_a != 0) 708 adapter->wol = 0; 709 /* Reset for multiple quad port adapters */ 710 if (++global_quad_port_a == 4) 711 global_quad_port_a = 0; 712 break; 713 } 714 715 /* Do we need workaround for 82544 PCI-X adapter? */ 716 if (adapter->hw.bus.type == e1000_bus_type_pcix && 717 adapter->hw.mac.type == e1000_82544) 718 adapter->pcix_82544 = TRUE; 719 else 720 adapter->pcix_82544 = FALSE; 721 722 /* Get control from any management/hw control */ 723 if (((adapter->hw.mac.type != e1000_82573) && 724 (adapter->hw.mac.type != e1000_ich8lan) && 725 (adapter->hw.mac.type != e1000_ich9lan)) || 726 !e1000_check_mng_mode(&adapter->hw)) 727 em_get_hw_control(adapter); 728 729 /* Tell the stack that the interface is not active */ 730 adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 731 732 INIT_DEBUGOUT("em_attach: end"); 733 734 return (0); 735 736err_hw_init: 737 em_release_hw_control(adapter); 738 e1000_remove_device(&adapter->hw); 739 em_dma_free(adapter, &adapter->rxdma); 740err_rx_desc: 741 em_dma_free(adapter, &adapter->txdma); 742err_tx_desc: 743err_pci: 744 em_free_intr(adapter); 745 em_free_pci_resources(adapter); 746 EM_LOCK_DESTROY(adapter); 747 748 return (error); 749} 750 751/********************************************************************* 752 * Device removal routine 753 * 754 * The detach entry point is called when the driver is being removed. 755 * This routine stops the adapter and deallocates all the resources 756 * that were allocated for driver operation. 757 * 758 * return 0 on success, positive on failure 759 *********************************************************************/ 760 761static int 762em_detach(device_t dev) 763{ 764 struct adapter *adapter = device_get_softc(dev); 765 struct ifnet *ifp = adapter->ifp; 766 767 INIT_DEBUGOUT("em_detach: begin"); 768 769#ifdef DEVICE_POLLING 770 if (ifp->if_capenable & IFCAP_POLLING) 771 ether_poll_deregister(ifp); 772#endif 773 774 em_disable_intr(adapter); 775 em_free_intr(adapter); 776 EM_LOCK(adapter); 777 adapter->in_detach = 1; 778 em_stop(adapter); 779 e1000_phy_hw_reset(&adapter->hw); 780 781 em_release_manageability(adapter); 782 if (((adapter->hw.mac.type != e1000_82573) && 783 (adapter->hw.mac.type != e1000_ich8lan) && 784 (adapter->hw.mac.type != e1000_ich9lan)) || 785 !e1000_check_mng_mode(&adapter->hw)) 786 em_release_hw_control(adapter); 787 if (adapter->wol) { 788 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 789 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 790 em_enable_wakeup(dev); 791 } 792 793 EM_UNLOCK(adapter); 794 ether_ifdetach(adapter->ifp); 795 796 callout_drain(&adapter->timer); 797 callout_drain(&adapter->tx_fifo_timer); 798 799 em_free_pci_resources(adapter); 800 bus_generic_detach(dev); 801 if_free(ifp); 802 803 e1000_remove_device(&adapter->hw); 804 em_free_transmit_structures(adapter); 805 em_free_receive_structures(adapter); 806 807 /* Free Transmit Descriptor ring */ 808 if (adapter->tx_desc_base) { 809 em_dma_free(adapter, &adapter->txdma); 810 adapter->tx_desc_base = NULL; 811 } 812 813 /* Free Receive Descriptor ring */ 814 if (adapter->rx_desc_base) { 815 em_dma_free(adapter, &adapter->rxdma); 816 adapter->rx_desc_base = NULL; 817 } 818 819 EM_LOCK_DESTROY(adapter); 820 821 return (0); 822} 823 824/********************************************************************* 825 * 826 * Shutdown entry point 827 * 828 **********************************************************************/ 829 830static int 831em_shutdown(device_t dev) 832{ 833 return em_suspend(dev); 834} 835 836/* 837 * Suspend/resume device methods. 838 */ 839static int 840em_suspend(device_t dev) 841{ 842 struct adapter *adapter = device_get_softc(dev); 843 844 EM_LOCK(adapter); 845 em_stop(adapter); 846 847 em_release_manageability(adapter); 848 if (((adapter->hw.mac.type != e1000_82573) && 849 (adapter->hw.mac.type != e1000_ich8lan) && 850 (adapter->hw.mac.type != e1000_ich9lan)) || 851 !e1000_check_mng_mode(&adapter->hw)) 852 em_release_hw_control(adapter); 853 if (adapter->wol) { 854 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 855 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 856 em_enable_wakeup(dev); 857 } 858 859 EM_UNLOCK(adapter); 860 861 return bus_generic_suspend(dev); 862} 863 864static int 865em_resume(device_t dev) 866{ 867 struct adapter *adapter = device_get_softc(dev); 868 struct ifnet *ifp = adapter->ifp; 869 870 EM_LOCK(adapter); 871 em_init_locked(adapter); 872 873 /* Get control from any management/hw control */ 874 if (((adapter->hw.mac.type != e1000_82573) && 875 (adapter->hw.mac.type != e1000_ich8lan) && 876 (adapter->hw.mac.type != e1000_ich9lan)) || 877 !e1000_check_mng_mode(&adapter->hw)) 878 em_get_hw_control(adapter); 879 em_init_manageability(adapter); 880 881 if ((ifp->if_flags & IFF_UP) && 882 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 883 em_start_locked(ifp); 884 885 EM_UNLOCK(adapter); 886 887 return bus_generic_resume(dev); 888} 889 890 891/********************************************************************* 892 * Transmit entry point 893 * 894 * em_start is called by the stack to initiate a transmit. 895 * The driver will remain in this routine as long as there are 896 * packets to transmit and transmit resources are available. 897 * In case resources are not available stack is notified and 898 * the packet is requeued. 899 **********************************************************************/ 900 901static void 902em_start_locked(struct ifnet *ifp) 903{ 904 struct adapter *adapter = ifp->if_softc; 905 struct mbuf *m_head; 906 907 EM_LOCK_ASSERT(adapter); 908 909 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 910 IFF_DRV_RUNNING) 911 return; 912 if (!adapter->link_active) 913 return; 914 915 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 916 917 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 918 if (m_head == NULL) 919 break; 920 /* 921 * Encapsulation can modify our pointer, and or make it 922 * NULL on failure. In that event, we can't requeue. 923 * 924 * We now use a pointer to accomodate legacy and 925 * advanced transmit functions. 926 */ 927 if (adapter->em_xmit(adapter, &m_head)) { 928 if (m_head == NULL) 929 break; 930 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 931 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 932 break; 933 } 934 935 /* Send a copy of the frame to the BPF listener */ 936 ETHER_BPF_MTAP(ifp, m_head); 937 938 /* Set timeout in case hardware has problems transmitting. */ 939 adapter->watchdog_timer = EM_TX_TIMEOUT; 940 } 941} 942 943static void 944em_start(struct ifnet *ifp) 945{ 946 struct adapter *adapter = ifp->if_softc; 947 948 EM_LOCK(adapter); 949 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 950 em_start_locked(ifp); 951 EM_UNLOCK(adapter); 952} 953 954/********************************************************************* 955 * Ioctl entry point 956 * 957 * em_ioctl is called when the user wants to configure the 958 * interface. 959 * 960 * return 0 on success, positive on failure 961 **********************************************************************/ 962 963static int 964em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 965{ 966 struct adapter *adapter = ifp->if_softc; 967 struct ifreq *ifr = (struct ifreq *)data; 968 struct ifaddr *ifa = (struct ifaddr *)data; 969 int error = 0; 970 971 if (adapter->in_detach) 972 return (error); 973 974 switch (command) { 975 case SIOCSIFADDR: 976 case SIOCGIFADDR: 977 if (ifa->ifa_addr->sa_family == AF_INET) { 978 /* 979 * XXX 980 * Since resetting hardware takes a very long time 981 * and results in link renegotiation we only 982 * initialize the hardware only when it is absolutely 983 * required. 984 */ 985 ifp->if_flags |= IFF_UP; 986 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 987 EM_LOCK(adapter); 988 em_init_locked(adapter); 989 EM_UNLOCK(adapter); 990 } 991 arp_ifinit(ifp, ifa); 992 } else 993 error = ether_ioctl(ifp, command, data); 994 break; 995 case SIOCSIFMTU: 996 { 997 int max_frame_size; 998 uint16_t eeprom_data = 0; 999 1000 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1001 1002 EM_LOCK(adapter); 1003 switch (adapter->hw.mac.type) { 1004 case e1000_82573: 1005 /* 1006 * 82573 only supports jumbo frames 1007 * if ASPM is disabled. 1008 */ 1009 e1000_read_nvm(&adapter->hw, 1010 NVM_INIT_3GIO_3, 1, &eeprom_data); 1011 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1012 max_frame_size = ETHER_MAX_LEN; 1013 break; 1014 } 1015 /* Allow Jumbo frames - fall thru */ 1016 case e1000_82571: 1017 case e1000_82572: 1018 case e1000_ich9lan: 1019 case e1000_82575: 1020 case e1000_80003es2lan: /* Limit Jumbo Frame size */ 1021 max_frame_size = 9234; 1022 break; 1023 case e1000_ich8lan: 1024 /* ICH8 does not support jumbo frames */ 1025 max_frame_size = ETHER_MAX_LEN; 1026 break; 1027 default: 1028 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1029 } 1030 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1031 ETHER_CRC_LEN) { 1032 EM_UNLOCK(adapter); 1033 error = EINVAL; 1034 break; 1035 } 1036 1037 ifp->if_mtu = ifr->ifr_mtu; 1038 adapter->hw.mac.max_frame_size = 1039 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1040 em_init_locked(adapter); 1041 EM_UNLOCK(adapter); 1042 break; 1043 } 1044 case SIOCSIFFLAGS: 1045 IOCTL_DEBUGOUT("ioctl rcv'd:\ 1046 SIOCSIFFLAGS (Set Interface Flags)"); 1047 EM_LOCK(adapter); 1048 if (ifp->if_flags & IFF_UP) { 1049 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1050 if ((ifp->if_flags ^ adapter->if_flags) & 1051 IFF_PROMISC) { 1052 em_disable_promisc(adapter); 1053 em_set_promisc(adapter); 1054 } 1055 } else 1056 em_init_locked(adapter); 1057 } else 1058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1059 em_stop(adapter); 1060 adapter->if_flags = ifp->if_flags; 1061 EM_UNLOCK(adapter); 1062 break; 1063 case SIOCADDMULTI: 1064 case SIOCDELMULTI: 1065 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 1066 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1067 EM_LOCK(adapter); 1068 em_disable_intr(adapter); 1069 em_set_multi(adapter); 1070 if (adapter->hw.mac.type == e1000_82542 && 1071 adapter->hw.revision_id == E1000_REVISION_2) { 1072 em_initialize_receive_unit(adapter); 1073 } 1074#ifdef DEVICE_POLLING 1075 if (!(ifp->if_capenable & IFCAP_POLLING)) 1076#endif 1077 em_enable_intr(adapter); 1078 EM_UNLOCK(adapter); 1079 } 1080 break; 1081 case SIOCSIFMEDIA: 1082 /* Check SOL/IDER usage */ 1083 EM_LOCK(adapter); 1084 if (e1000_check_reset_block(&adapter->hw)) { 1085 EM_UNLOCK(adapter); 1086 device_printf(adapter->dev, "Media change is" 1087 " blocked due to SOL/IDER session.\n"); 1088 break; 1089 } 1090 EM_UNLOCK(adapter); 1091 case SIOCGIFMEDIA: 1092 IOCTL_DEBUGOUT("ioctl rcv'd: \ 1093 SIOCxIFMEDIA (Get/Set Interface Media)"); 1094 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1095 break; 1096 case SIOCSIFCAP: 1097 { 1098 int mask, reinit; 1099 1100 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 1101 reinit = 0; 1102 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1103#ifdef DEVICE_POLLING 1104 if (mask & IFCAP_POLLING) { 1105 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1106 error = ether_poll_register(em_poll, ifp); 1107 if (error) 1108 return (error); 1109 EM_LOCK(adapter); 1110 em_disable_intr(adapter); 1111 ifp->if_capenable |= IFCAP_POLLING; 1112 EM_UNLOCK(adapter); 1113 } else { 1114 error = ether_poll_deregister(ifp); 1115 /* Enable interrupt even in error case */ 1116 EM_LOCK(adapter); 1117 em_enable_intr(adapter); 1118 ifp->if_capenable &= ~IFCAP_POLLING; 1119 EM_UNLOCK(adapter); 1120 } 1121 } 1122#endif 1123 if (mask & IFCAP_HWCSUM) { 1124 ifp->if_capenable ^= IFCAP_HWCSUM; 1125 reinit = 1; 1126 } 1127 if (mask & IFCAP_TSO4) { 1128 ifp->if_capenable ^= IFCAP_TSO4; 1129 reinit = 1; 1130 } 1131 if (mask & IFCAP_VLAN_HWTAGGING) { 1132 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1133 reinit = 1; 1134 } 1135 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1136 em_init(adapter); 1137 VLAN_CAPABILITIES(ifp); 1138 break; 1139 } 1140 default: 1141 error = ether_ioctl(ifp, command, data); 1142 break; 1143 } 1144 1145 return (error); 1146} 1147 1148/********************************************************************* 1149 * Watchdog timer: 1150 * 1151 * This routine is called from the local timer every second. 1152 * As long as transmit descriptors are being cleaned the value 1153 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 1154 * and we then reset the device. 1155 * 1156 **********************************************************************/ 1157 1158static void 1159em_watchdog(struct adapter *adapter) 1160{ 1161 1162 EM_LOCK_ASSERT(adapter); 1163 1164 /* 1165 ** The timer is set to 5 every time start queues a packet. 1166 ** Then txeof keeps resetting to 5 as long as it cleans at 1167 ** least one descriptor. 1168 ** Finally, anytime all descriptors are clean the timer is 1169 ** set to 0. 1170 */ 1171 if (adapter->watchdog_timer == 0 || --adapter->watchdog_timer) 1172 return; 1173 1174 /* If we are in this routine because of pause frames, then 1175 * don't reset the hardware. 1176 */ 1177 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1178 E1000_STATUS_TXOFF) { 1179 adapter->watchdog_timer = EM_TX_TIMEOUT; 1180 return; 1181 } 1182 1183 if (e1000_check_for_link(&adapter->hw) == 0) 1184 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1185 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1186 adapter->watchdog_events++; 1187 1188 em_init_locked(adapter); 1189} 1190 1191/********************************************************************* 1192 * Init entry point 1193 * 1194 * This routine is used in two ways. It is used by the stack as 1195 * init entry point in network interface structure. It is also used 1196 * by the driver as a hw/sw initialization routine to get to a 1197 * consistent state. 1198 * 1199 * return 0 on success, positive on failure 1200 **********************************************************************/ 1201 1202static void 1203em_init_locked(struct adapter *adapter) 1204{ 1205 struct ifnet *ifp = adapter->ifp; 1206 device_t dev = adapter->dev; 1207 uint32_t pba; 1208 1209 INIT_DEBUGOUT("em_init: begin"); 1210 1211 EM_LOCK_ASSERT(adapter); 1212 1213 em_stop(adapter); 1214 1215 /* 1216 * Packet Buffer Allocation (PBA) 1217 * Writing PBA sets the receive portion of the buffer 1218 * the remainder is used for the transmit buffer. 1219 * 1220 * Devices before the 82547 had a Packet Buffer of 64K. 1221 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1222 * After the 82547 the buffer was reduced to 40K. 1223 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1224 * Note: default does not leave enough room for Jumbo Frame >10k. 1225 */ 1226 switch (adapter->hw.mac.type) { 1227 case e1000_82547: 1228 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1229 if (adapter->hw.mac.max_frame_size > 8192) 1230 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1231 else 1232 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1233 adapter->tx_fifo_head = 0; 1234 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1235 adapter->tx_fifo_size = 1236 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1237 break; 1238 /* Total Packet Buffer on these is 48K */ 1239 case e1000_82571: 1240 case e1000_82572: 1241 case e1000_82575: 1242 case e1000_80003es2lan: 1243 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1244 break; 1245 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1246 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1247 break; 1248 case e1000_ich9lan: 1249#define E1000_PBA_10K 0x000A 1250 pba = E1000_PBA_10K; 1251 break; 1252 case e1000_ich8lan: 1253 pba = E1000_PBA_8K; 1254 break; 1255 default: 1256 /* Devices before 82547 had a Packet Buffer of 64K. */ 1257 if (adapter->hw.mac.max_frame_size > 8192) 1258 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1259 else 1260 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1261 } 1262 1263 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1264 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1265 1266 /* Get the latest mac address, User can use a LAA */ 1267 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr, 1268 ETHER_ADDR_LEN); 1269 1270 /* Put the address into the Receive Address Array */ 1271 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1272 1273 /* 1274 * With 82571 controllers, LAA may be overwritten 1275 * due to controller reset from the other port. 1276 */ 1277 if (adapter->hw.mac.type == e1000_82571) 1278 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1279 1280 /* Initialize the hardware */ 1281 if (em_hardware_init(adapter)) { 1282 device_printf(dev, "Unable to initialize the hardware\n"); 1283 return; 1284 } 1285 em_update_link_status(adapter); 1286 1287 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1288 em_enable_vlans(adapter); 1289 1290 /* Set hardware offload abilities */ 1291 ifp->if_hwassist = 0; 1292 if (adapter->hw.mac.type >= e1000_82543) { 1293 if (ifp->if_capenable & IFCAP_TXCSUM) 1294 ifp->if_hwassist |= EM_CHECKSUM_FEATURES; 1295 if (ifp->if_capenable & IFCAP_TSO) 1296 ifp->if_hwassist |= EM_TCPSEG_FEATURES; 1297 } 1298 1299 /* Configure for OS presence */ 1300 em_init_manageability(adapter); 1301 1302 /* Prepare transmit descriptors and buffers */ 1303 if (em_setup_transmit_structures(adapter)) { 1304 device_printf(dev, "Could not setup transmit structures\n"); 1305 em_stop(adapter); 1306 return; 1307 } 1308 em_initialize_transmit_unit(adapter); 1309 1310 /* Setup Multicast table */ 1311 em_set_multi(adapter); 1312 1313 /* Prepare receive descriptors and buffers */ 1314 if (em_setup_receive_structures(adapter)) { 1315 device_printf(dev, "Could not setup receive structures\n"); 1316 em_stop(adapter); 1317 return; 1318 } 1319 em_initialize_receive_unit(adapter); 1320 1321 /* Don't lose promiscuous settings */ 1322 em_set_promisc(adapter); 1323 1324 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1325 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1326 1327 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1328 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1329 1330#ifdef DEVICE_POLLING 1331 /* 1332 * Only enable interrupts if we are not polling, make sure 1333 * they are off otherwise. 1334 */ 1335 if (ifp->if_capenable & IFCAP_POLLING) 1336 em_disable_intr(adapter); 1337 else 1338#endif /* DEVICE_POLLING */ 1339 em_enable_intr(adapter); 1340 1341 /* Don't reset the phy next time init gets called */ 1342 adapter->hw.phy.reset_disable = TRUE; 1343} 1344 1345static void 1346em_init(void *arg) 1347{ 1348 struct adapter *adapter = arg; 1349 1350 EM_LOCK(adapter); 1351 em_init_locked(adapter); 1352 EM_UNLOCK(adapter); 1353} 1354 1355 1356#ifdef DEVICE_POLLING 1357/********************************************************************* 1358 * 1359 * Legacy polling routine 1360 * 1361 *********************************************************************/ 1362static void 1363em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1364{ 1365 struct adapter *adapter = ifp->if_softc; 1366 uint32_t reg_icr; 1367 1368 EM_LOCK(adapter); 1369 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1370 EM_UNLOCK(adapter); 1371 return; 1372 } 1373 1374 if (cmd == POLL_AND_CHECK_STATUS) { 1375 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1376 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1377 callout_stop(&adapter->timer); 1378 adapter->hw.mac.get_link_status = 1; 1379 e1000_check_for_link(&adapter->hw); 1380 em_update_link_status(adapter); 1381 callout_reset(&adapter->timer, hz, 1382 em_local_timer, adapter); 1383 } 1384 } 1385 em_rxeof(adapter, count); 1386 em_txeof(adapter); 1387 1388 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1389 em_start_locked(ifp); 1390 EM_UNLOCK(adapter); 1391} 1392 1393/********************************************************************* 1394 * 1395 * Legacy Interrupt Service routine 1396 * 1397 *********************************************************************/ 1398 1399static void 1400em_intr(void *arg) 1401{ 1402 struct adapter *adapter = arg; 1403 struct ifnet *ifp; 1404 uint32_t reg_icr; 1405 1406 EM_LOCK(adapter); 1407 ifp = adapter->ifp; 1408 1409 if (ifp->if_capenable & IFCAP_POLLING) { 1410 EM_UNLOCK(adapter); 1411 return; 1412 } 1413 1414 for (;;) { 1415 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1416 1417 if (adapter->hw.mac.type >= e1000_82571 && 1418 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1419 break; 1420 else if (reg_icr == 0) 1421 break; 1422 1423 /* 1424 * XXX: some laptops trigger several spurious interrupts 1425 * on em(4) when in the resume cycle. The ICR register 1426 * reports all-ones value in this case. Processing such 1427 * interrupts would lead to a freeze. I don't know why. 1428 */ 1429 if (reg_icr == 0xffffffff) 1430 break; 1431 1432 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1433 em_rxeof(adapter, -1); 1434 em_txeof(adapter); 1435 } 1436 1437 /* Link status change */ 1438 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1439 callout_stop(&adapter->timer); 1440 adapter->hw.mac.get_link_status = 1; 1441 e1000_check_for_link(&adapter->hw); 1442 em_update_link_status(adapter); 1443 callout_reset(&adapter->timer, hz, 1444 em_local_timer, adapter); 1445 } 1446 1447 if (reg_icr & E1000_ICR_RXO) 1448 adapter->rx_overruns++; 1449 } 1450 1451 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1452 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1453 em_start_locked(ifp); 1454 EM_UNLOCK(adapter); 1455} 1456 1457#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1458 1459static void 1460em_handle_link(void *context, int pending) 1461{ 1462 struct adapter *adapter = context; 1463 struct ifnet *ifp; 1464 1465 ifp = adapter->ifp; 1466 1467 EM_LOCK(adapter); 1468 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1469 EM_UNLOCK(adapter); 1470 return; 1471 } 1472 1473 callout_stop(&adapter->timer); 1474 adapter->hw.mac.get_link_status = 1; 1475 e1000_check_for_link(&adapter->hw); 1476 em_update_link_status(adapter); 1477 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1478 EM_UNLOCK(adapter); 1479} 1480 1481static void 1482em_handle_rxtx(void *context, int pending) 1483{ 1484 struct adapter *adapter = context; 1485 struct ifnet *ifp; 1486 1487 NET_LOCK_GIANT(); 1488 ifp = adapter->ifp; 1489 1490 /* 1491 * TODO: 1492 * It should be possible to run the tx clean loop without the lock. 1493 */ 1494 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1495 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1496 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1497 EM_LOCK(adapter); 1498 em_txeof(adapter); 1499 1500 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1501 em_start_locked(ifp); 1502 EM_UNLOCK(adapter); 1503 } 1504 1505 em_enable_intr(adapter); 1506 NET_UNLOCK_GIANT(); 1507} 1508 1509/********************************************************************* 1510 * 1511 * Fast Interrupt Service routine 1512 * 1513 *********************************************************************/ 1514static int 1515em_intr_fast(void *arg) 1516{ 1517 struct adapter *adapter = arg; 1518 struct ifnet *ifp; 1519 uint32_t reg_icr; 1520 1521 ifp = adapter->ifp; 1522 1523 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1524 1525 /* Hot eject? */ 1526 if (reg_icr == 0xffffffff) 1527 return (FILTER_STRAY); 1528 1529 /* Definitely not our interrupt. */ 1530 if (reg_icr == 0x0) 1531 return (FILTER_STRAY); 1532 1533 /* 1534 * Starting with the 82571 chip, bit 31 should be used to 1535 * determine whether the interrupt belongs to us. 1536 */ 1537 if (adapter->hw.mac.type >= e1000_82571 && 1538 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1539 return (FILTER_STRAY); 1540 1541 /* 1542 * Mask interrupts until the taskqueue is finished running. This is 1543 * cheap, just assume that it is needed. This also works around the 1544 * MSI message reordering errata on certain systems. 1545 */ 1546 em_disable_intr(adapter); 1547 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1548 1549 /* Link status change */ 1550 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1551 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1552 1553 if (reg_icr & E1000_ICR_RXO) 1554 adapter->rx_overruns++; 1555 return (FILTER_HANDLED); 1556} 1557#endif /* ! DEVICE_POLLING */ 1558 1559/********************************************************************* 1560 * 1561 * Media Ioctl callback 1562 * 1563 * This routine is called whenever the user queries the status of 1564 * the interface using ifconfig. 1565 * 1566 **********************************************************************/ 1567static void 1568em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1569{ 1570 struct adapter *adapter = ifp->if_softc; 1571 u_char fiber_type = IFM_1000_SX; 1572 1573 INIT_DEBUGOUT("em_media_status: begin"); 1574 1575 EM_LOCK(adapter); 1576 e1000_check_for_link(&adapter->hw); 1577 em_update_link_status(adapter); 1578 1579 ifmr->ifm_status = IFM_AVALID; 1580 ifmr->ifm_active = IFM_ETHER; 1581 1582 if (!adapter->link_active) { 1583 EM_UNLOCK(adapter); 1584 return; 1585 } 1586 1587 ifmr->ifm_status |= IFM_ACTIVE; 1588 1589 if ((adapter->hw.media_type == e1000_media_type_fiber) || 1590 (adapter->hw.media_type == e1000_media_type_internal_serdes)) { 1591 if (adapter->hw.mac.type == e1000_82545) 1592 fiber_type = IFM_1000_LX; 1593 ifmr->ifm_active |= fiber_type | IFM_FDX; 1594 } else { 1595 switch (adapter->link_speed) { 1596 case 10: 1597 ifmr->ifm_active |= IFM_10_T; 1598 break; 1599 case 100: 1600 ifmr->ifm_active |= IFM_100_TX; 1601 break; 1602 case 1000: 1603 ifmr->ifm_active |= IFM_1000_T; 1604 break; 1605 } 1606 if (adapter->link_duplex == FULL_DUPLEX) 1607 ifmr->ifm_active |= IFM_FDX; 1608 else 1609 ifmr->ifm_active |= IFM_HDX; 1610 } 1611 EM_UNLOCK(adapter); 1612} 1613 1614/********************************************************************* 1615 * 1616 * Media Ioctl callback 1617 * 1618 * This routine is called when the user changes speed/duplex using 1619 * media/mediopt option with ifconfig. 1620 * 1621 **********************************************************************/ 1622static int 1623em_media_change(struct ifnet *ifp) 1624{ 1625 struct adapter *adapter = ifp->if_softc; 1626 struct ifmedia *ifm = &adapter->media; 1627 1628 INIT_DEBUGOUT("em_media_change: begin"); 1629 1630 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1631 return (EINVAL); 1632 1633 EM_LOCK(adapter); 1634 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1635 case IFM_AUTO: 1636 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1637 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1638 break; 1639 case IFM_1000_LX: 1640 case IFM_1000_SX: 1641 case IFM_1000_T: 1642 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1643 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1644 break; 1645 case IFM_100_TX: 1646 adapter->hw.mac.autoneg = FALSE; 1647 adapter->hw.phy.autoneg_advertised = 0; 1648 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1649 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1650 else 1651 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1652 break; 1653 case IFM_10_T: 1654 adapter->hw.mac.autoneg = FALSE; 1655 adapter->hw.phy.autoneg_advertised = 0; 1656 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1657 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1658 else 1659 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1660 break; 1661 default: 1662 device_printf(adapter->dev, "Unsupported media type\n"); 1663 } 1664 1665 /* As the speed/duplex settings my have changed we need to 1666 * reset the PHY. 1667 */ 1668 adapter->hw.phy.reset_disable = FALSE; 1669 1670 em_init_locked(adapter); 1671 EM_UNLOCK(adapter); 1672 1673 return (0); 1674} 1675 1676/********************************************************************* 1677 * 1678 * This routine maps the mbufs to tx descriptors. 1679 * 1680 * return 0 on success, positive on failure 1681 **********************************************************************/ 1682 1683static int 1684em_encap(struct adapter *adapter, struct mbuf **m_headp) 1685{ 1686 struct ifnet *ifp = adapter->ifp; 1687 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1688 bus_dmamap_t map; 1689 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1690 struct e1000_tx_desc *ctxd = NULL; 1691 struct mbuf *m_head; 1692 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1693 int nsegs, i, j, first, last = 0; 1694 int error, do_tso, tso_desc = 0; 1695 1696 m_head = *m_headp; 1697 txd_upper = txd_lower = txd_used = txd_saved = 0; 1698 1699 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 1700 1701 /* 1702 * Force a cleanup if number of TX descriptors 1703 * available hits the threshold 1704 */ 1705 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1706 em_txeof(adapter); 1707 /* Now do we at least have a minimal? */ 1708 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1709 adapter->no_tx_desc_avail1++; 1710 return (ENOBUFS); 1711 } 1712 } 1713 1714 1715 /* 1716 * TSO workaround: 1717 * If an mbuf is only header we need 1718 * to pull 4 bytes of data into it. 1719 */ 1720 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 1721 m_head = m_pullup(m_head, M_TSO_LEN + 4); 1722 *m_headp = m_head; 1723 if (m_head == NULL) 1724 return (ENOBUFS); 1725 } 1726 1727 /* 1728 * Map the packet for DMA 1729 * 1730 * Capture the first descriptor index, 1731 * this descriptor will have the index 1732 * of the EOP which is the only one that 1733 * now gets a DONE bit writeback. 1734 */ 1735 first = adapter->next_avail_tx_desc; 1736 tx_buffer = &adapter->tx_buffer_area[first]; 1737 tx_buffer_mapped = tx_buffer; 1738 map = tx_buffer->map; 1739 1740 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1741 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1742 1743 /* 1744 * There are two types of errors we can (try) to handle: 1745 * - EFBIG means the mbuf chain was too long and bus_dma ran 1746 * out of segments. Defragment the mbuf chain and try again. 1747 * - ENOMEM means bus_dma could not obtain enough bounce buffers 1748 * at this point in time. Defer sending and try again later. 1749 * All other errors, in particular EINVAL, are fatal and prevent the 1750 * mbuf chain from ever going through. Drop it and report error. 1751 */ 1752 if (error == EFBIG) { 1753 struct mbuf *m; 1754 1755 m = m_defrag(*m_headp, M_DONTWAIT); 1756 if (m == NULL) { 1757 adapter->mbuf_alloc_failed++; 1758 m_freem(*m_headp); 1759 *m_headp = NULL; 1760 return (ENOBUFS); 1761 } 1762 *m_headp = m; 1763 1764 /* Try it again */ 1765 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1766 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1767 1768 if (error == ENOMEM) { 1769 adapter->no_tx_dma_setup++; 1770 return (error); 1771 } else if (error != 0) { 1772 adapter->no_tx_dma_setup++; 1773 m_freem(*m_headp); 1774 *m_headp = NULL; 1775 return (error); 1776 } 1777 } else if (error == ENOMEM) { 1778 adapter->no_tx_dma_setup++; 1779 return (error); 1780 } else if (error != 0) { 1781 adapter->no_tx_dma_setup++; 1782 m_freem(*m_headp); 1783 *m_headp = NULL; 1784 return (error); 1785 } 1786 1787 /* 1788 * TSO Hardware workaround, if this packet is not 1789 * TSO, and is only a single descriptor long, and 1790 * it follows a TSO burst, then we need to add a 1791 * sentinel descriptor to prevent premature writeback. 1792 */ 1793 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 1794 if (nsegs == 1) 1795 tso_desc = TRUE; 1796 adapter->tx_tso = FALSE; 1797 } 1798 1799 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 1800 adapter->no_tx_desc_avail2++; 1801 bus_dmamap_unload(adapter->txtag, map); 1802 return (ENOBUFS); 1803 } 1804 m_head = *m_headp; 1805 1806 /* Do hardware assists */ 1807 if (ifp->if_hwassist > 0) { 1808 if (do_tso && em_tso_setup(adapter, m_head, 1809 &txd_upper, &txd_lower)) { 1810 /* we need to make a final sentinel transmit desc */ 1811 tso_desc = TRUE; 1812 } else 1813 em_transmit_checksum_setup(adapter, m_head, 1814 &txd_upper, &txd_lower); 1815 } 1816 1817 i = adapter->next_avail_tx_desc; 1818 if (adapter->pcix_82544) 1819 txd_saved = i; 1820 1821 /* Set up our transmit descriptors */ 1822 for (j = 0; j < nsegs; j++) { 1823 bus_size_t seg_len; 1824 bus_addr_t seg_addr; 1825 /* If adapter is 82544 and on PCIX bus */ 1826 if(adapter->pcix_82544) { 1827 DESC_ARRAY desc_array; 1828 uint32_t array_elements, counter; 1829 /* 1830 * Check the Address and Length combination and 1831 * split the data accordingly 1832 */ 1833 array_elements = em_fill_descriptors(segs[j].ds_addr, 1834 segs[j].ds_len, &desc_array); 1835 for (counter = 0; counter < array_elements; counter++) { 1836 if (txd_used == adapter->num_tx_desc_avail) { 1837 adapter->next_avail_tx_desc = txd_saved; 1838 adapter->no_tx_desc_avail2++; 1839 bus_dmamap_unload(adapter->txtag, map); 1840 return (ENOBUFS); 1841 } 1842 tx_buffer = &adapter->tx_buffer_area[i]; 1843 ctxd = &adapter->tx_desc_base[i]; 1844 ctxd->buffer_addr = htole64( 1845 desc_array.descriptor[counter].address); 1846 ctxd->lower.data = htole32( 1847 (adapter->txd_cmd | txd_lower | (uint16_t) 1848 desc_array.descriptor[counter].length)); 1849 ctxd->upper.data = 1850 htole32((txd_upper)); 1851 last = i; 1852 if (++i == adapter->num_tx_desc) 1853 i = 0; 1854 tx_buffer->m_head = NULL; 1855 tx_buffer->next_eop = -1; 1856 txd_used++; 1857 } 1858 } else { 1859 tx_buffer = &adapter->tx_buffer_area[i]; 1860 ctxd = &adapter->tx_desc_base[i]; 1861 seg_addr = segs[j].ds_addr; 1862 seg_len = segs[j].ds_len; 1863 /* 1864 ** TSO Workaround: 1865 ** If this is the last descriptor, we want to 1866 ** split it so we have a small final sentinel 1867 */ 1868 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 1869 seg_len -= 4; 1870 ctxd->buffer_addr = htole64(seg_addr); 1871 ctxd->lower.data = htole32( 1872 adapter->txd_cmd | txd_lower | seg_len); 1873 ctxd->upper.data = 1874 htole32(txd_upper); 1875 if (++i == adapter->num_tx_desc) 1876 i = 0; 1877 /* Now make the sentinel */ 1878 ++txd_used; /* using an extra txd */ 1879 ctxd = &adapter->tx_desc_base[i]; 1880 tx_buffer = &adapter->tx_buffer_area[i]; 1881 ctxd->buffer_addr = 1882 htole64(seg_addr + seg_len); 1883 ctxd->lower.data = htole32( 1884 adapter->txd_cmd | txd_lower | 4); 1885 ctxd->upper.data = 1886 htole32(txd_upper); 1887 last = i; 1888 if (++i == adapter->num_tx_desc) 1889 i = 0; 1890 } else { 1891 ctxd->buffer_addr = seg_addr; 1892 ctxd->lower.data = htole32( 1893 adapter->txd_cmd | txd_lower | seg_len); 1894 ctxd->upper.data = 1895 htole32(txd_upper); 1896 last = i; 1897 if (++i == adapter->num_tx_desc) 1898 i = 0; 1899 } 1900 tx_buffer->m_head = NULL; 1901 tx_buffer->next_eop = -1; 1902 } 1903 } 1904 1905 adapter->next_avail_tx_desc = i; 1906 if (adapter->pcix_82544) 1907 adapter->num_tx_desc_avail -= txd_used; 1908 else { 1909 adapter->num_tx_desc_avail -= nsegs; 1910 if (tso_desc) /* TSO used an extra for sentinel */ 1911 adapter->num_tx_desc_avail -= txd_used; 1912 } 1913 1914 if (m_head->m_flags & M_VLANTAG) { 1915 /* Set the vlan id. */ 1916 ctxd->upper.fields.special = 1917 htole16(m_head->m_pkthdr.ether_vtag); 1918 /* Tell hardware to add tag */ 1919 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1920 } 1921 1922 tx_buffer->m_head = m_head; 1923 tx_buffer_mapped->map = tx_buffer->map; 1924 tx_buffer->map = map; 1925 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1926 1927 /* 1928 * Last Descriptor of Packet 1929 * needs End Of Packet (EOP) 1930 * and Report Status (RS) 1931 */ 1932 ctxd->lower.data |= 1933 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1934 /* 1935 * Keep track in the first buffer which 1936 * descriptor will be written back 1937 */ 1938 tx_buffer = &adapter->tx_buffer_area[first]; 1939 tx_buffer->next_eop = last; 1940 1941 /* 1942 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 1943 * that this frame is available to transmit. 1944 */ 1945 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1947 if (adapter->hw.mac.type == e1000_82547 && 1948 adapter->link_duplex == HALF_DUPLEX) 1949 em_82547_move_tail(adapter); 1950 else { 1951 E1000_WRITE_REG(&adapter->hw, E1000_TDT, i); 1952 if (adapter->hw.mac.type == e1000_82547) 1953 em_82547_update_fifo_head(adapter, 1954 m_head->m_pkthdr.len); 1955 } 1956 1957 return (0); 1958} 1959 1960/********************************************************************* 1961 * 1962 * This routine maps the mbufs to Advanced TX descriptors. 1963 * used by the 82575 adapter. It also needs no workarounds. 1964 * 1965 **********************************************************************/ 1966#define CSUM_OFFLOAD 7 /* Checksum bits */ 1967 1968static int 1969em_adv_encap(struct adapter *adapter, struct mbuf **m_headp) 1970{ 1971 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1972 bus_dmamap_t map; 1973 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1974 union e1000_adv_tx_desc *txd = NULL; 1975 struct mbuf *m_head; 1976 u32 olinfo_status = 0, cmd_type_len = 0; 1977 u32 paylen = 0; 1978 int nsegs, i, j, error, first, last = 0; 1979 1980 m_head = *m_headp; 1981 1982 1983 /* Set basic descriptor constants */ 1984 cmd_type_len |= E1000_ADVTXD_DTYP_DATA; 1985 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT; 1986 1987 /* 1988 * Force a cleanup if number of TX descriptors 1989 * available hits the threshold 1990 */ 1991 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1992 em_txeof(adapter); 1993 /* Now do we at least have a minimal? */ 1994 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1995 adapter->no_tx_desc_avail1++; 1996 return (ENOBUFS); 1997 } 1998 } 1999 2000 /* 2001 * Map the packet for DMA. 2002 * 2003 * Capture the first descriptor index, 2004 * this descriptor will have the index 2005 * of the EOP which is the only one that 2006 * now gets a DONE bit writeback. 2007 */ 2008 first = adapter->next_avail_tx_desc; 2009 tx_buffer = &adapter->tx_buffer_area[first]; 2010 tx_buffer_mapped = tx_buffer; 2011 map = tx_buffer->map; 2012 2013 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2014 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2015 2016 if (error == EFBIG) { 2017 struct mbuf *m; 2018 2019 m = m_defrag(*m_headp, M_DONTWAIT); 2020 if (m == NULL) { 2021 adapter->mbuf_alloc_failed++; 2022 m_freem(*m_headp); 2023 *m_headp = NULL; 2024 return (ENOBUFS); 2025 } 2026 *m_headp = m; 2027 2028 /* Try it again */ 2029 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2030 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2031 2032 if (error == ENOMEM) { 2033 adapter->no_tx_dma_setup++; 2034 return (error); 2035 } else if (error != 0) { 2036 adapter->no_tx_dma_setup++; 2037 m_freem(*m_headp); 2038 *m_headp = NULL; 2039 return (error); 2040 } 2041 } else if (error == ENOMEM) { 2042 adapter->no_tx_dma_setup++; 2043 return (error); 2044 } else if (error != 0) { 2045 adapter->no_tx_dma_setup++; 2046 m_freem(*m_headp); 2047 *m_headp = NULL; 2048 return (error); 2049 } 2050 2051 /* Check again to be sure we have enough descriptors */ 2052 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 2053 adapter->no_tx_desc_avail2++; 2054 bus_dmamap_unload(adapter->txtag, map); 2055 return (ENOBUFS); 2056 } 2057 m_head = *m_headp; 2058 2059 /* 2060 * Set up the context descriptor: 2061 * used when any hardware offload is done. 2062 * This includes CSUM, VLAN, and TSO. It 2063 * will use the first descriptor. 2064 */ 2065 /* First try TSO */ 2066 if (em_tso_adv_setup(adapter, m_head, &paylen)) { 2067 cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 2068 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 2069 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2070 olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 2071 } else if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) { 2072 if (em_tx_adv_ctx_setup(adapter, m_head)) 2073 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2074 } 2075 2076 /* Set up our transmit descriptors */ 2077 i = adapter->next_avail_tx_desc; 2078 for (j = 0; j < nsegs; j++) { 2079 bus_size_t seg_len; 2080 bus_addr_t seg_addr; 2081 2082 tx_buffer = &adapter->tx_buffer_area[i]; 2083 txd = (union e1000_adv_tx_desc *)&adapter->tx_desc_base[i]; 2084 seg_addr = segs[j].ds_addr; 2085 seg_len = segs[j].ds_len; 2086 2087 txd->read.buffer_addr = htole64(seg_addr); 2088 txd->read.cmd_type_len = htole32( 2089 adapter->txd_cmd | cmd_type_len | seg_len); 2090 txd->read.olinfo_status = htole32(olinfo_status); 2091 last = i; 2092 if (++i == adapter->num_tx_desc) 2093 i = 0; 2094 tx_buffer->m_head = NULL; 2095 tx_buffer->next_eop = -1; 2096 } 2097 2098 adapter->next_avail_tx_desc = i; 2099 adapter->num_tx_desc_avail -= nsegs; 2100 2101 tx_buffer->m_head = m_head; 2102 tx_buffer_mapped->map = tx_buffer->map; 2103 tx_buffer->map = map; 2104 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2105 2106 /* 2107 * Last Descriptor of Packet 2108 * needs End Of Packet (EOP) 2109 * and Report Status (RS) 2110 */ 2111 txd->read.cmd_type_len |= 2112 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2113 /* 2114 * Keep track in the first buffer which 2115 * descriptor will be written back 2116 */ 2117 tx_buffer = &adapter->tx_buffer_area[first]; 2118 tx_buffer->next_eop = last; 2119 2120 /* 2121 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2122 * that this frame is available to transmit. 2123 */ 2124 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2125 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2126 E1000_WRITE_REG(&adapter->hw, E1000_TDT, i); 2127 2128 return (0); 2129 2130} 2131 2132/********************************************************************* 2133 * 2134 * 82547 workaround to avoid controller hang in half-duplex environment. 2135 * The workaround is to avoid queuing a large packet that would span 2136 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 2137 * in this case. We do that only when FIFO is quiescent. 2138 * 2139 **********************************************************************/ 2140static void 2141em_82547_move_tail(void *arg) 2142{ 2143 struct adapter *adapter = arg; 2144 uint16_t hw_tdt; 2145 uint16_t sw_tdt; 2146 struct e1000_tx_desc *tx_desc; 2147 uint16_t length = 0; 2148 boolean_t eop = 0; 2149 2150 EM_LOCK_ASSERT(adapter); 2151 2152 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT); 2153 sw_tdt = adapter->next_avail_tx_desc; 2154 2155 while (hw_tdt != sw_tdt) { 2156 tx_desc = &adapter->tx_desc_base[hw_tdt]; 2157 length += tx_desc->lower.flags.length; 2158 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2159 if (++hw_tdt == adapter->num_tx_desc) 2160 hw_tdt = 0; 2161 2162 if (eop) { 2163 if (em_82547_fifo_workaround(adapter, length)) { 2164 adapter->tx_fifo_wrk_cnt++; 2165 callout_reset(&adapter->tx_fifo_timer, 1, 2166 em_82547_move_tail, adapter); 2167 break; 2168 } 2169 E1000_WRITE_REG(&adapter->hw, E1000_TDT, hw_tdt); 2170 em_82547_update_fifo_head(adapter, length); 2171 length = 0; 2172 } 2173 } 2174} 2175 2176static int 2177em_82547_fifo_workaround(struct adapter *adapter, int len) 2178{ 2179 int fifo_space, fifo_pkt_len; 2180 2181 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2182 2183 if (adapter->link_duplex == HALF_DUPLEX) { 2184 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2185 2186 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2187 if (em_82547_tx_fifo_reset(adapter)) 2188 return (0); 2189 else 2190 return (1); 2191 } 2192 } 2193 2194 return (0); 2195} 2196 2197static void 2198em_82547_update_fifo_head(struct adapter *adapter, int len) 2199{ 2200 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2201 2202 /* tx_fifo_head is always 16 byte aligned */ 2203 adapter->tx_fifo_head += fifo_pkt_len; 2204 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 2205 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2206 } 2207} 2208 2209 2210static int 2211em_82547_tx_fifo_reset(struct adapter *adapter) 2212{ 2213 uint32_t tctl; 2214 2215 if ((E1000_READ_REG(&adapter->hw, E1000_TDT) == 2216 E1000_READ_REG(&adapter->hw, E1000_TDH)) && 2217 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2218 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2219 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2220 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2221 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2222 /* Disable TX unit */ 2223 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2224 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2225 tctl & ~E1000_TCTL_EN); 2226 2227 /* Reset FIFO pointers */ 2228 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2229 adapter->tx_head_addr); 2230 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2231 adapter->tx_head_addr); 2232 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2233 adapter->tx_head_addr); 2234 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2235 adapter->tx_head_addr); 2236 2237 /* Re-enable TX unit */ 2238 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2239 E1000_WRITE_FLUSH(&adapter->hw); 2240 2241 adapter->tx_fifo_head = 0; 2242 adapter->tx_fifo_reset_cnt++; 2243 2244 return (TRUE); 2245 } 2246 else { 2247 return (FALSE); 2248 } 2249} 2250 2251static void 2252em_set_promisc(struct adapter *adapter) 2253{ 2254 struct ifnet *ifp = adapter->ifp; 2255 uint32_t reg_rctl; 2256 2257 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2258 2259 if (ifp->if_flags & IFF_PROMISC) { 2260 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2261 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2262 } else if (ifp->if_flags & IFF_ALLMULTI) { 2263 reg_rctl |= E1000_RCTL_MPE; 2264 reg_rctl &= ~E1000_RCTL_UPE; 2265 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2266 } 2267} 2268 2269static void 2270em_disable_promisc(struct adapter *adapter) 2271{ 2272 uint32_t reg_rctl; 2273 2274 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2275 2276 reg_rctl &= (~E1000_RCTL_UPE); 2277 reg_rctl &= (~E1000_RCTL_MPE); 2278 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2279} 2280 2281 2282/********************************************************************* 2283 * Multicast Update 2284 * 2285 * This routine is called whenever multicast address list is updated. 2286 * 2287 **********************************************************************/ 2288 2289static void 2290em_set_multi(struct adapter *adapter) 2291{ 2292 struct ifnet *ifp = adapter->ifp; 2293 struct ifmultiaddr *ifma; 2294 uint32_t reg_rctl = 0; 2295 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 2296 int mcnt = 0; 2297 2298 IOCTL_DEBUGOUT("em_set_multi: begin"); 2299 2300 if (adapter->hw.mac.type == e1000_82542 && 2301 adapter->hw.revision_id == E1000_REVISION_2) { 2302 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2303 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2304 e1000_pci_clear_mwi(&adapter->hw); 2305 reg_rctl |= E1000_RCTL_RST; 2306 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2307 msec_delay(5); 2308 } 2309 2310 IF_ADDR_LOCK(ifp); 2311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2312 if (ifma->ifma_addr->sa_family != AF_LINK) 2313 continue; 2314 2315 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2316 break; 2317 2318 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2319 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN); 2320 mcnt++; 2321 } 2322 IF_ADDR_UNLOCK(ifp); 2323 2324 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2325 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2326 reg_rctl |= E1000_RCTL_MPE; 2327 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2328 } else 2329 e1000_mc_addr_list_update(&adapter->hw, mta, 2330 mcnt, 1, adapter->hw.mac.rar_entry_count); 2331 2332 if (adapter->hw.mac.type == e1000_82542 && 2333 adapter->hw.revision_id == E1000_REVISION_2) { 2334 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2335 reg_rctl &= ~E1000_RCTL_RST; 2336 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2337 msec_delay(5); 2338 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2339 e1000_pci_set_mwi(&adapter->hw); 2340 } 2341} 2342 2343 2344/********************************************************************* 2345 * Timer routine 2346 * 2347 * This routine checks for link status and updates statistics. 2348 * 2349 **********************************************************************/ 2350 2351static void 2352em_local_timer(void *arg) 2353{ 2354 struct adapter *adapter = arg; 2355 struct ifnet *ifp = adapter->ifp; 2356 2357 EM_LOCK_ASSERT(adapter); 2358 2359 e1000_check_for_link(&adapter->hw); 2360 em_update_link_status(adapter); 2361 em_update_stats_counters(adapter); 2362 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2363 em_print_hw_stats(adapter); 2364 em_smartspeed(adapter); 2365 /* 2366 * Each second we check the watchdog to 2367 * protect against hardware hangs. 2368 */ 2369 em_watchdog(adapter); 2370 2371 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2372 2373} 2374 2375static void 2376em_update_link_status(struct adapter *adapter) 2377{ 2378 struct ifnet *ifp = adapter->ifp; 2379 device_t dev = adapter->dev; 2380 2381 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 2382 E1000_STATUS_LU) { 2383 if (adapter->link_active == 0) { 2384 e1000_get_speed_and_duplex(&adapter->hw, 2385 &adapter->link_speed, &adapter->link_duplex); 2386 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2387 if ((adapter->link_speed != SPEED_1000) && 2388 ((adapter->hw.mac.type == e1000_82571) || 2389 (adapter->hw.mac.type == e1000_82572))) { 2390 int tarc0; 2391 2392 tarc0 = E1000_READ_REG(&adapter->hw, 2393 E1000_TARC0); 2394 tarc0 &= ~SPEED_MODE_BIT; 2395 E1000_WRITE_REG(&adapter->hw, 2396 E1000_TARC0, tarc0); 2397 } 2398 if (bootverbose) 2399 device_printf(dev, "Link is up %d Mbps %s\n", 2400 adapter->link_speed, 2401 ((adapter->link_duplex == FULL_DUPLEX) ? 2402 "Full Duplex" : "Half Duplex")); 2403 adapter->link_active = 1; 2404 adapter->smartspeed = 0; 2405 ifp->if_baudrate = adapter->link_speed * 1000000; 2406 if_link_state_change(ifp, LINK_STATE_UP); 2407 } 2408 } else { 2409 if (adapter->link_active == 1) { 2410 ifp->if_baudrate = adapter->link_speed = 0; 2411 adapter->link_duplex = 0; 2412 if (bootverbose) 2413 device_printf(dev, "Link is Down\n"); 2414 adapter->link_active = 0; 2415 if_link_state_change(ifp, LINK_STATE_DOWN); 2416 } 2417 } 2418} 2419 2420/********************************************************************* 2421 * 2422 * This routine disables all traffic on the adapter by issuing a 2423 * global reset on the MAC and deallocates TX/RX buffers. 2424 * 2425 **********************************************************************/ 2426 2427static void 2428em_stop(void *arg) 2429{ 2430 struct adapter *adapter = arg; 2431 struct ifnet *ifp = adapter->ifp; 2432 2433 EM_LOCK_ASSERT(adapter); 2434 2435 INIT_DEBUGOUT("em_stop: begin"); 2436 2437 em_disable_intr(adapter); 2438 callout_stop(&adapter->timer); 2439 callout_stop(&adapter->tx_fifo_timer); 2440 em_free_transmit_structures(adapter); 2441 em_free_receive_structures(adapter); 2442 2443 /* Tell the stack that the interface is no longer active */ 2444 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2445 2446 e1000_reset_hw(&adapter->hw); 2447 if (adapter->hw.mac.type >= e1000_82544) 2448 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2449} 2450 2451 2452/********************************************************************* 2453 * 2454 * Determine hardware revision. 2455 * 2456 **********************************************************************/ 2457static void 2458em_identify_hardware(struct adapter *adapter) 2459{ 2460 device_t dev = adapter->dev; 2461 2462 /* Make sure our PCI config space has the necessary stuff set */ 2463 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2464 if ((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 2465 (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN)) { 2466 device_printf(dev, "Memory Access and/or Bus Master bits " 2467 "were not set!\n"); 2468 adapter->hw.bus.pci_cmd_word |= 2469 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2470 pci_write_config(dev, PCIR_COMMAND, 2471 adapter->hw.bus.pci_cmd_word, 2); 2472 } 2473 2474 /* Save off the information about this board */ 2475 adapter->hw.vendor_id = pci_get_vendor(dev); 2476 adapter->hw.device_id = pci_get_device(dev); 2477 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2478 adapter->hw.subsystem_vendor_id = 2479 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2480 adapter->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2481 2482 /* Do Shared Code Init and Setup */ 2483 if (e1000_set_mac_type(&adapter->hw)) { 2484 device_printf(dev, "Setup init failure\n"); 2485 return; 2486 } 2487} 2488 2489static int 2490em_allocate_pci_resources(struct adapter *adapter) 2491{ 2492 device_t dev = adapter->dev; 2493 int val, rid; 2494 2495 rid = PCIR_BAR(0); 2496 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2497 &rid, RF_ACTIVE); 2498 if (adapter->res_memory == NULL) { 2499 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2500 return (ENXIO); 2501 } 2502 adapter->osdep.mem_bus_space_tag = 2503 rman_get_bustag(adapter->res_memory); 2504 adapter->osdep.mem_bus_space_handle = 2505 rman_get_bushandle(adapter->res_memory); 2506 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2507 2508 /* Only older adapters use IO mapping */ 2509 if (adapter->hw.mac.type <= e1000_82543) { 2510 /* Figure our where our IO BAR is ? */ 2511 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2512 val = pci_read_config(dev, rid, 4); 2513 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2514 adapter->io_rid = rid; 2515 break; 2516 } 2517 rid += 4; 2518 /* check for 64bit BAR */ 2519 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2520 rid += 4; 2521 } 2522 if (rid >= PCIR_CIS) { 2523 device_printf(dev, "Unable to locate IO BAR\n"); 2524 return (ENXIO); 2525 } 2526 adapter->res_ioport = bus_alloc_resource_any(dev, 2527 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2528 if (adapter->res_ioport == NULL) { 2529 device_printf(dev, "Unable to allocate bus resource: " 2530 "ioport\n"); 2531 return (ENXIO); 2532 } 2533 adapter->hw.io_base = 0; 2534 adapter->osdep.io_bus_space_tag = 2535 rman_get_bustag(adapter->res_ioport); 2536 adapter->osdep.io_bus_space_handle = 2537 rman_get_bushandle(adapter->res_ioport); 2538 } 2539 2540 /* 2541 * Setup MSI/X or MSI if PCI Express 2542 * only the latest can use MSI/X and 2543 * real support for it is forthcoming 2544 */ 2545 adapter->msi = 0; /* Set defaults */ 2546 rid = 0x0; 2547 if (adapter->hw.mac.type >= e1000_82575) { 2548 /* 2549 * Eventually this will be used 2550 * for Multiqueue, for now we will 2551 * just use one vector. 2552 */ 2553 val = pci_msix_count(dev); 2554 if ((val) && pci_alloc_msix(dev, &val) == 0) { 2555 rid = 1; 2556 adapter->msi = 1; 2557 } 2558 } else if (adapter->hw.bus.type == e1000_bus_type_pci_express) { 2559 val = pci_msi_count(dev); 2560 if (val == 1 && pci_alloc_msi(dev, &val) == 0) { 2561 rid = 1; 2562 adapter->msi = 1; 2563 } 2564 } 2565 adapter->res_interrupt = bus_alloc_resource_any(dev, 2566 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2567 if (adapter->res_interrupt == NULL) { 2568 device_printf(dev, "Unable to allocate bus resource: " 2569 "interrupt\n"); 2570 return (ENXIO); 2571 } 2572 2573 adapter->hw.back = &adapter->osdep; 2574 2575 return (0); 2576} 2577 2578/********************************************************************* 2579 * 2580 * Setup the appropriate Interrupt handlers. 2581 * 2582 **********************************************************************/ 2583int 2584em_allocate_intr(struct adapter *adapter) 2585{ 2586 device_t dev = adapter->dev; 2587 int error; 2588 2589 /* Manually turn off all interrupts */ 2590 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2591 2592#ifdef DEVICE_POLLING 2593 /* We do Legacy setup */ 2594 if (adapter->int_handler_tag == NULL && 2595 (error = bus_setup_intr(dev, adapter->res_interrupt, 2596 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_intr, adapter, 2597 &adapter->int_handler_tag)) != 0) { 2598 device_printf(dev, "Failed to register interrupt handler"); 2599 return (error); 2600 } 2601 2602#else 2603 /* 2604 * Try allocating a fast interrupt and the associated deferred 2605 * processing contexts. 2606 */ 2607 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2608 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2609 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2610 taskqueue_thread_enqueue, &adapter->tq); 2611 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2612 device_get_nameunit(adapter->dev)); 2613 if ((error = bus_setup_intr(dev, adapter->res_interrupt, 2614 INTR_TYPE_NET, em_intr_fast, NULL, adapter, 2615 &adapter->int_handler_tag)) != 0) { 2616 device_printf(dev, "Failed to register fast interrupt " 2617 "handler: %d\n", error); 2618 taskqueue_free(adapter->tq); 2619 adapter->tq = NULL; 2620 return (error); 2621 } 2622#endif 2623 2624 em_enable_intr(adapter); 2625 return (0); 2626} 2627 2628static void 2629em_free_intr(struct adapter *adapter) 2630{ 2631 device_t dev = adapter->dev; 2632 2633 if (adapter->res_interrupt != NULL) { 2634 bus_teardown_intr(dev, adapter->res_interrupt, 2635 adapter->int_handler_tag); 2636 adapter->int_handler_tag = NULL; 2637 } 2638 if (adapter->tq != NULL) { 2639 taskqueue_drain(adapter->tq, &adapter->rxtx_task); 2640 taskqueue_drain(taskqueue_fast, &adapter->link_task); 2641 taskqueue_free(adapter->tq); 2642 adapter->tq = NULL; 2643 } 2644} 2645 2646static void 2647em_free_pci_resources(struct adapter *adapter) 2648{ 2649 device_t dev = adapter->dev; 2650 2651 if (adapter->res_interrupt != NULL) 2652 bus_release_resource(dev, SYS_RES_IRQ, 2653 0, adapter->res_interrupt); 2654 2655 if (adapter->msi) 2656 pci_release_msi(dev); 2657 2658 if (adapter->res_memory != NULL) 2659 bus_release_resource(dev, SYS_RES_MEMORY, 2660 PCIR_BAR(0), adapter->res_memory); 2661 2662 if (adapter->flash_mem != NULL) 2663 bus_release_resource(dev, SYS_RES_MEMORY, 2664 EM_FLASH, adapter->flash_mem); 2665 2666 if (adapter->res_ioport != NULL) 2667 bus_release_resource(dev, SYS_RES_IOPORT, 2668 adapter->io_rid, adapter->res_ioport); 2669} 2670 2671/********************************************************************* 2672 * 2673 * Initialize the hardware to a configuration 2674 * as specified by the adapter structure. 2675 * 2676 **********************************************************************/ 2677static int 2678em_hardware_init(struct adapter *adapter) 2679{ 2680 device_t dev = adapter->dev; 2681 uint16_t rx_buffer_size; 2682 2683 INIT_DEBUGOUT("em_hardware_init: begin"); 2684 2685 /* Issue a global reset */ 2686 e1000_reset_hw(&adapter->hw); 2687 2688 /* When hardware is reset, fifo_head is also reset */ 2689 adapter->tx_fifo_head = 0; 2690 2691 /* Set up smart power down as default off on newer adapters. */ 2692 if (!em_smart_pwr_down && (adapter->hw.mac.type == e1000_82571 || 2693 adapter->hw.mac.type == e1000_82572)) { 2694 uint16_t phy_tmp = 0; 2695 2696 /* Speed up time to link by disabling smart power down. */ 2697 e1000_read_phy_reg(&adapter->hw, 2698 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2699 phy_tmp &= ~IGP02E1000_PM_SPD; 2700 e1000_write_phy_reg(&adapter->hw, 2701 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2702 } 2703 2704 /* 2705 * These parameters control the automatic generation (Tx) and 2706 * response (Rx) to Ethernet PAUSE frames. 2707 * - High water mark should allow for at least two frames to be 2708 * received after sending an XOFF. 2709 * - Low water mark works best when it is very near the high water mark. 2710 * This allows the receiver to restart by sending XON when it has 2711 * drained a bit. Here we use an arbitary value of 1500 which will 2712 * restart after one full frame is pulled from the buffer. There 2713 * could be several smaller frames in the buffer and if so they will 2714 * not trigger the XON until their total number reduces the buffer 2715 * by 1500. 2716 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2717 */ 2718 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 2719 0xffff) << 10 ); 2720 2721 adapter->hw.mac.fc_high_water = rx_buffer_size - 2722 roundup2(adapter->hw.mac.max_frame_size, 1024); 2723 adapter->hw.mac.fc_low_water = adapter->hw.mac.fc_high_water - 1500; 2724 if (adapter->hw.mac.type == e1000_80003es2lan) 2725 adapter->hw.mac.fc_pause_time = 0xFFFF; 2726 else 2727 adapter->hw.mac.fc_pause_time = EM_FC_PAUSE_TIME; 2728 adapter->hw.mac.fc_send_xon = TRUE; 2729 adapter->hw.mac.fc = e1000_fc_full; 2730 2731 if (e1000_init_hw(&adapter->hw) < 0) { 2732 device_printf(dev, "Hardware Initialization Failed\n"); 2733 return (EIO); 2734 } 2735 2736 e1000_check_for_link(&adapter->hw); 2737 2738 return (0); 2739} 2740 2741/********************************************************************* 2742 * 2743 * Setup networking device structure and register an interface. 2744 * 2745 **********************************************************************/ 2746static void 2747em_setup_interface(device_t dev, struct adapter *adapter) 2748{ 2749 struct ifnet *ifp; 2750 2751 INIT_DEBUGOUT("em_setup_interface: begin"); 2752 2753 ifp = adapter->ifp = if_alloc(IFT_ETHER); 2754 if (ifp == NULL) 2755 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2756 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2757 ifp->if_mtu = ETHERMTU; 2758 ifp->if_init = em_init; 2759 ifp->if_softc = adapter; 2760 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2761 ifp->if_ioctl = em_ioctl; 2762 ifp->if_start = em_start; 2763 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 2764 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 2765 IFQ_SET_READY(&ifp->if_snd); 2766 2767 ether_ifattach(ifp, adapter->hw.mac.addr); 2768 2769 ifp->if_capabilities = ifp->if_capenable = 0; 2770 2771 if (adapter->hw.mac.type >= e1000_82543) { 2772 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2773 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2774 } 2775 2776 /* Enable TSO if available */ 2777 if ((adapter->hw.mac.type > e1000_82544) && 2778 (adapter->hw.mac.type != e1000_82547)) { 2779 ifp->if_capabilities |= IFCAP_TSO4; 2780 ifp->if_capenable |= IFCAP_TSO4; 2781 } 2782 2783 /* 2784 * Tell the upper layer(s) we support long frames. 2785 */ 2786 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2787 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2788 ifp->if_capenable |= IFCAP_VLAN_MTU; 2789 2790#ifdef DEVICE_POLLING 2791 ifp->if_capabilities |= IFCAP_POLLING; 2792#endif 2793 2794 /* 2795 * Specify the media types supported by this adapter and register 2796 * callbacks to update media and link information 2797 */ 2798 ifmedia_init(&adapter->media, IFM_IMASK, 2799 em_media_change, em_media_status); 2800 if ((adapter->hw.media_type == e1000_media_type_fiber) || 2801 (adapter->hw.media_type == e1000_media_type_internal_serdes)) { 2802 u_char fiber_type = IFM_1000_SX; /* default type */ 2803 2804 if (adapter->hw.mac.type == e1000_82545) 2805 fiber_type = IFM_1000_LX; 2806 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2807 0, NULL); 2808 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2809 } else { 2810 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2811 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2812 0, NULL); 2813 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2814 0, NULL); 2815 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2816 0, NULL); 2817 if (adapter->hw.phy.type != e1000_phy_ife) { 2818 ifmedia_add(&adapter->media, 2819 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2820 ifmedia_add(&adapter->media, 2821 IFM_ETHER | IFM_1000_T, 0, NULL); 2822 } 2823 } 2824 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2825 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2826} 2827 2828 2829/********************************************************************* 2830 * 2831 * Workaround for SmartSpeed on 82541 and 82547 controllers 2832 * 2833 **********************************************************************/ 2834static void 2835em_smartspeed(struct adapter *adapter) 2836{ 2837 uint16_t phy_tmp; 2838 2839 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2840 adapter->hw.mac.autoneg == 0 || 2841 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2842 return; 2843 2844 if (adapter->smartspeed == 0) { 2845 /* If Master/Slave config fault is asserted twice, 2846 * we assume back-to-back */ 2847 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2848 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2849 return; 2850 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2851 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2852 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2853 if(phy_tmp & CR_1000T_MS_ENABLE) { 2854 phy_tmp &= ~CR_1000T_MS_ENABLE; 2855 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, 2856 phy_tmp); 2857 adapter->smartspeed++; 2858 if(adapter->hw.mac.autoneg && 2859 !e1000_phy_setup_autoneg(&adapter->hw) && 2860 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, 2861 &phy_tmp)) { 2862 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2863 MII_CR_RESTART_AUTO_NEG); 2864 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 2865 phy_tmp); 2866 } 2867 } 2868 } 2869 return; 2870 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2871 /* If still no link, perhaps using 2/3 pair cable */ 2872 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2873 phy_tmp |= CR_1000T_MS_ENABLE; 2874 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2875 if(adapter->hw.mac.autoneg && 2876 !e1000_phy_setup_autoneg(&adapter->hw) && 2877 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2878 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2879 MII_CR_RESTART_AUTO_NEG); 2880 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2881 } 2882 } 2883 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2884 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2885 adapter->smartspeed = 0; 2886} 2887 2888 2889/* 2890 * Manage DMA'able memory. 2891 */ 2892static void 2893em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2894{ 2895 if (error) 2896 return; 2897 *(bus_addr_t *) arg = segs[0].ds_addr; 2898} 2899 2900static int 2901em_dma_malloc(struct adapter *adapter, bus_size_t size, 2902 struct em_dma_alloc *dma, int mapflags) 2903{ 2904 int error; 2905 2906 error = bus_dma_tag_create(bus_get_dma_tag(adapter->dev), /* parent */ 2907 EM_DBA_ALIGN, 0, /* alignment, bounds */ 2908 BUS_SPACE_MAXADDR, /* lowaddr */ 2909 BUS_SPACE_MAXADDR, /* highaddr */ 2910 NULL, NULL, /* filter, filterarg */ 2911 size, /* maxsize */ 2912 1, /* nsegments */ 2913 size, /* maxsegsize */ 2914 0, /* flags */ 2915 NULL, /* lockfunc */ 2916 NULL, /* lockarg */ 2917 &dma->dma_tag); 2918 if (error) { 2919 device_printf(adapter->dev, 2920 "%s: bus_dma_tag_create failed: %d\n", 2921 __func__, error); 2922 goto fail_0; 2923 } 2924 2925 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2926 BUS_DMA_NOWAIT, &dma->dma_map); 2927 if (error) { 2928 device_printf(adapter->dev, 2929 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2930 __func__, (uintmax_t)size, error); 2931 goto fail_2; 2932 } 2933 2934 dma->dma_paddr = 0; 2935 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2936 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2937 if (error || dma->dma_paddr == 0) { 2938 device_printf(adapter->dev, 2939 "%s: bus_dmamap_load failed: %d\n", 2940 __func__, error); 2941 goto fail_3; 2942 } 2943 2944 return (0); 2945 2946fail_3: 2947 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2948fail_2: 2949 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2950 bus_dma_tag_destroy(dma->dma_tag); 2951fail_0: 2952 dma->dma_map = NULL; 2953 dma->dma_tag = NULL; 2954 2955 return (error); 2956} 2957 2958static void 2959em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2960{ 2961 if (dma->dma_tag == NULL) 2962 return; 2963 if (dma->dma_map != NULL) { 2964 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2965 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2966 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2967 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2968 dma->dma_map = NULL; 2969 } 2970 bus_dma_tag_destroy(dma->dma_tag); 2971 dma->dma_tag = NULL; 2972} 2973 2974 2975/********************************************************************* 2976 * 2977 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2978 * the information needed to transmit a packet on the wire. 2979 * 2980 **********************************************************************/ 2981static int 2982em_allocate_transmit_structures(struct adapter *adapter) 2983{ 2984 device_t dev = adapter->dev; 2985 2986 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2987 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 2988 if (adapter->tx_buffer_area == NULL) { 2989 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 2990 return (ENOMEM); 2991 } 2992 2993 bzero(adapter->tx_buffer_area, 2994 (sizeof(struct em_buffer)) * adapter->num_tx_desc); 2995 2996 return (0); 2997} 2998 2999/********************************************************************* 3000 * 3001 * Initialize transmit structures. 3002 * 3003 **********************************************************************/ 3004static int 3005em_setup_transmit_structures(struct adapter *adapter) 3006{ 3007 device_t dev = adapter->dev; 3008 struct em_buffer *tx_buffer; 3009 int error, i; 3010 3011 /* 3012 * Create DMA tags for tx descriptors 3013 */ 3014 if ((error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3015 1, 0, /* alignment, bounds */ 3016 BUS_SPACE_MAXADDR, /* lowaddr */ 3017 BUS_SPACE_MAXADDR, /* highaddr */ 3018 NULL, NULL, /* filter, filterarg */ 3019 EM_TSO_SIZE, /* maxsize */ 3020 EM_MAX_SCATTER, /* nsegments */ 3021 EM_TSO_SEG_SIZE, /* maxsegsize */ 3022 0, /* flags */ 3023 NULL, /* lockfunc */ 3024 NULL, /* lockarg */ 3025 &adapter->txtag)) != 0) { 3026 device_printf(dev, "Unable to allocate TX DMA tag\n"); 3027 goto fail; 3028 } 3029 3030 if ((error = em_allocate_transmit_structures(adapter)) != 0) 3031 goto fail; 3032 3033 /* Clear the old ring contents */ 3034 bzero(adapter->tx_desc_base, 3035 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 3036 3037 /* Create the descriptor buffer dma maps */ 3038 tx_buffer = adapter->tx_buffer_area; 3039 for (i = 0; i < adapter->num_tx_desc; i++) { 3040 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 3041 if (error != 0) { 3042 device_printf(dev, "Unable to create TX DMA map\n"); 3043 goto fail; 3044 } 3045 tx_buffer->next_eop = -1; 3046 tx_buffer++; 3047 } 3048 3049 adapter->next_avail_tx_desc = 0; 3050 adapter->next_tx_to_clean = 0; 3051 3052 /* Set number of descriptors available */ 3053 adapter->num_tx_desc_avail = adapter->num_tx_desc; 3054 3055 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3056 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3057 3058 return (0); 3059 3060fail: 3061 em_free_transmit_structures(adapter); 3062 return (error); 3063} 3064 3065/********************************************************************* 3066 * 3067 * Enable transmit unit. 3068 * 3069 **********************************************************************/ 3070static void 3071em_initialize_transmit_unit(struct adapter *adapter) 3072{ 3073 uint32_t tctl, tarc, tipg = 0; 3074 uint64_t bus_addr; 3075 3076 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3077 /* Setup the Base and Length of the Tx Descriptor Ring */ 3078 bus_addr = adapter->txdma.dma_paddr; 3079 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN, 3080 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 3081 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH, (uint32_t)(bus_addr >> 32)); 3082 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL, (uint32_t)bus_addr); 3083 3084 /* Setup the HW Tx Head and Tail descriptor pointers */ 3085 E1000_WRITE_REG(&adapter->hw, E1000_TDT, 0); 3086 E1000_WRITE_REG(&adapter->hw, E1000_TDH, 0); 3087 3088 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3089 E1000_READ_REG(&adapter->hw, E1000_TDBAL), 3090 E1000_READ_REG(&adapter->hw, E1000_TDLEN)); 3091 3092 /* Set the default values for the Tx Inter Packet Gap timer */ 3093 switch (adapter->hw.mac.type) { 3094 case e1000_82542: 3095 tipg = DEFAULT_82542_TIPG_IPGT; 3096 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3097 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3098 break; 3099 case e1000_80003es2lan: 3100 tipg = DEFAULT_82543_TIPG_IPGR1; 3101 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3102 E1000_TIPG_IPGR2_SHIFT; 3103 break; 3104 default: 3105 if ((adapter->hw.media_type == e1000_media_type_fiber) || 3106 (adapter->hw.media_type == 3107 e1000_media_type_internal_serdes)) 3108 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3109 else 3110 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3111 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3112 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3113 } 3114 3115 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3116 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3117 if(adapter->hw.mac.type >= e1000_82540) 3118 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3119 adapter->tx_abs_int_delay.value); 3120 3121 if ((adapter->hw.mac.type == e1000_82571) || 3122 (adapter->hw.mac.type == e1000_82572)) { 3123 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC0); 3124 tarc |= SPEED_MODE_BIT; 3125 E1000_WRITE_REG(&adapter->hw, E1000_TARC0, tarc); 3126 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3127 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC0); 3128 tarc |= 1; 3129 E1000_WRITE_REG(&adapter->hw, E1000_TARC0, tarc); 3130 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC1); 3131 tarc |= 1; 3132 E1000_WRITE_REG(&adapter->hw, E1000_TARC1, tarc); 3133 } 3134 3135 /* Program the Transmit Control Register */ 3136 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3137 tctl &= ~E1000_TCTL_CT; 3138 tctl = E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3139 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3140 3141 if (adapter->hw.mac.type >= e1000_82571) 3142 tctl |= E1000_TCTL_MULR; 3143 3144 /* This write will effectively turn on the transmit unit. */ 3145 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3146 3147 /* Setup Transmit Descriptor Base Settings */ 3148 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 3149 3150 if ((adapter->tx_int_delay.value > 0) && 3151 (adapter->hw.mac.type != e1000_82575)) 3152 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3153 3154 /* Set the function pointer for the transmit routine */ 3155 if (adapter->hw.mac.type >= e1000_82575) 3156 adapter->em_xmit = em_adv_encap; 3157 else 3158 adapter->em_xmit = em_encap; 3159} 3160 3161/********************************************************************* 3162 * 3163 * Free all transmit related data structures. 3164 * 3165 **********************************************************************/ 3166static void 3167em_free_transmit_structures(struct adapter *adapter) 3168{ 3169 struct em_buffer *tx_buffer; 3170 int i; 3171 3172 INIT_DEBUGOUT("free_transmit_structures: begin"); 3173 3174 if (adapter->tx_buffer_area != NULL) { 3175 tx_buffer = adapter->tx_buffer_area; 3176 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 3177 if (tx_buffer->m_head != NULL) { 3178 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3179 BUS_DMASYNC_POSTWRITE); 3180 bus_dmamap_unload(adapter->txtag, 3181 tx_buffer->map); 3182 m_freem(tx_buffer->m_head); 3183 tx_buffer->m_head = NULL; 3184 } else if (tx_buffer->map != NULL) 3185 bus_dmamap_unload(adapter->txtag, 3186 tx_buffer->map); 3187 if (tx_buffer->map != NULL) { 3188 bus_dmamap_destroy(adapter->txtag, 3189 tx_buffer->map); 3190 tx_buffer->map = NULL; 3191 } 3192 } 3193 } 3194 if (adapter->tx_buffer_area != NULL) { 3195 free(adapter->tx_buffer_area, M_DEVBUF); 3196 adapter->tx_buffer_area = NULL; 3197 } 3198 if (adapter->txtag != NULL) { 3199 bus_dma_tag_destroy(adapter->txtag); 3200 adapter->txtag = NULL; 3201 } 3202} 3203 3204/********************************************************************* 3205 * 3206 * The offload context needs to be set when we transfer the first 3207 * packet of a particular protocol (TCP/UDP). This routine has been 3208 * enhanced to deal with inserted VLAN headers, and IPV6 (not complete) 3209 * 3210 **********************************************************************/ 3211static void 3212em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 3213 uint32_t *txd_upper, uint32_t *txd_lower) 3214{ 3215 struct e1000_context_desc *TXD; 3216 struct em_buffer *tx_buffer; 3217 struct ether_vlan_header *eh; 3218 struct ip *ip; 3219 struct ip6_hdr *ip6; 3220 struct tcp_hdr *th; 3221 int curr_txd, ehdrlen, hdr_len, ip_hlen; 3222 uint32_t cmd = 0; 3223 uint16_t etype; 3224 uint8_t ipproto; 3225 3226 /* Setup checksum offload context. */ 3227 curr_txd = adapter->next_avail_tx_desc; 3228 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3229 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3230 3231 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3232 E1000_TXD_DTYP_D; /* Data descr */ 3233 3234 /* 3235 * Determine where frame payload starts. 3236 * Jump over vlan headers if already present, 3237 * helpful for QinQ too. 3238 */ 3239 eh = mtod(mp, struct ether_vlan_header *); 3240 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3241 etype = ntohs(eh->evl_proto); 3242 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3243 } else { 3244 etype = ntohs(eh->evl_encap_proto); 3245 ehdrlen = ETHER_HDR_LEN; 3246 } 3247 3248 /* 3249 * We only support TCP/UDP for IPv4 and IPv6 for the moment. 3250 * TODO: Support SCTP too when it hits the tree. 3251 */ 3252 switch (etype) { 3253 case ETHERTYPE_IP: 3254 ip = (struct ip *)(mp->m_data + ehdrlen); 3255 ip_hlen = ip->ip_hl << 2; 3256 3257 /* Setup of IP header checksum. */ 3258 if (mp->m_pkthdr.csum_flags & CSUM_IP) { 3259 /* 3260 * Start offset for header checksum calculation. 3261 * End offset for header checksum calculation. 3262 * Offset of place to put the checksum. 3263 */ 3264 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3265 TXD->lower_setup.ip_fields.ipcse = 3266 htole16(ehdrlen + ip_hlen); 3267 TXD->lower_setup.ip_fields.ipcso = 3268 ehdrlen + offsetof(struct ip, ip_sum); 3269 cmd |= E1000_TXD_CMD_IP; 3270 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3271 } 3272 3273 if (mp->m_len < ehdrlen + ip_hlen) 3274 return; /* failure */ 3275 3276 hdr_len = ehdrlen + ip_hlen; 3277 ipproto = ip->ip_p; 3278 3279 break; 3280 case ETHERTYPE_IPV6: 3281 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3282 ip_hlen = sizeof(struct ip6_hdr); /* XXX: No header stacking. */ 3283 3284 if (mp->m_len < ehdrlen + ip_hlen) 3285 return; /* failure */ 3286 3287 /* IPv6 doesn't have a header checksum. */ 3288 3289 hdr_len = ehdrlen + ip_hlen; 3290 ipproto = ip6->ip6_nxt; 3291 3292 break; 3293 default: 3294 *txd_upper = 0; 3295 *txd_lower = 0; 3296 return; 3297 } 3298 3299 switch (ipproto) { 3300 case IPPROTO_TCP: 3301 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 3302 /* 3303 * Start offset for payload checksum calculation. 3304 * End offset for payload checksum calculation. 3305 * Offset of place to put the checksum. 3306 */ 3307 th = (struct tcp_hdr *)(mp->m_data + hdr_len); 3308 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3309 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3310 TXD->upper_setup.tcp_fields.tucso = 3311 hdr_len + offsetof(struct tcphdr, th_sum); 3312 cmd |= E1000_TXD_CMD_TCP; 3313 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3314 } 3315 break; 3316 case IPPROTO_UDP: 3317 if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 3318 /* 3319 * Start offset for header checksum calculation. 3320 * End offset for header checksum calculation. 3321 * Offset of place to put the checksum. 3322 */ 3323 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3324 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3325 TXD->upper_setup.tcp_fields.tucso = 3326 hdr_len + offsetof(struct udphdr, uh_sum); 3327 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3328 } 3329 break; 3330 default: 3331 break; 3332 } 3333 3334 TXD->tcp_seg_setup.data = htole32(0); 3335 TXD->cmd_and_length = 3336 htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT | cmd); 3337 tx_buffer->m_head = NULL; 3338 tx_buffer->next_eop = -1; 3339 3340 if (++curr_txd == adapter->num_tx_desc) 3341 curr_txd = 0; 3342 3343 adapter->num_tx_desc_avail--; 3344 adapter->next_avail_tx_desc = curr_txd; 3345} 3346 3347/********************************************************************** 3348 * 3349 * Setup work for hardware segmentation offload (TSO) 3350 * 3351 **********************************************************************/ 3352static boolean_t 3353em_tso_setup(struct adapter *adapter, struct mbuf *mp, uint32_t *txd_upper, 3354 uint32_t *txd_lower) 3355{ 3356 struct e1000_context_desc *TXD; 3357 struct em_buffer *tx_buffer; 3358 struct ether_vlan_header *eh; 3359 struct ip *ip; 3360 struct ip6_hdr *ip6; 3361 struct tcphdr *th; 3362 int curr_txd, ehdrlen, hdr_len, ip_hlen, isip6; 3363 uint16_t etype; 3364 3365 /* 3366 * XXX: This is not really correct as the stack would not have 3367 * set up all checksums. 3368 * XXX: Return FALSE is not sufficient as we may have to return 3369 * in true failure cases as well. Should do -1 (failure), 0 (no) 3370 * and 1 (success). 3371 */ 3372 if (mp->m_pkthdr.len <= EM_TX_BUFFER_SIZE) 3373 return FALSE; /* 0 */ 3374 3375 /* 3376 * This function could/should be extended to support IP/IPv6 3377 * fragmentation as well. But as they say, one step at a time. 3378 */ 3379 3380 /* 3381 * Determine where frame payload starts. 3382 * Jump over vlan headers if already present, 3383 * helpful for QinQ too. 3384 */ 3385 eh = mtod(mp, struct ether_vlan_header *); 3386 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3387 etype = ntohs(eh->evl_proto); 3388 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3389 } else { 3390 etype = ntohs(eh->evl_encap_proto); 3391 ehdrlen = ETHER_HDR_LEN; 3392 } 3393 3394 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3395 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3396 return FALSE; /* -1 */ 3397 3398 /* 3399 * We only support TCP for IPv4 and IPv6 (notyet) for the moment. 3400 * TODO: Support SCTP too when it hits the tree. 3401 */ 3402 switch (etype) { 3403 case ETHERTYPE_IP: 3404 isip6 = 0; 3405 ip = (struct ip *)(mp->m_data + ehdrlen); 3406 if (ip->ip_p != IPPROTO_TCP) 3407 return FALSE; /* 0 */ 3408 ip->ip_len = 0; 3409 ip->ip_sum = 0; 3410 ip_hlen = ip->ip_hl << 2; 3411 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3412 return FALSE; /* -1 */ 3413 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3414#if 1 3415 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3416 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3417#else 3418 th->th_sum = mp->m_pkthdr.csum_data; 3419#endif 3420 break; 3421 case ETHERTYPE_IPV6: 3422 isip6 = 1; 3423 return FALSE; /* Not supported yet. */ 3424 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3425 if (ip6->ip6_nxt != IPPROTO_TCP) 3426 return FALSE; /* 0 */ 3427 ip6->ip6_plen = 0; 3428 ip_hlen = sizeof(struct ip6_hdr); /* XXX: no header stacking. */ 3429 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3430 return FALSE; /* -1 */ 3431 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 3432#if 0 3433 th->th_sum = in6_pseudo(ip6->ip6_src, ip->ip6_dst, 3434 htons(IPPROTO_TCP)); /* XXX: function notyet. */ 3435#else 3436 th->th_sum = mp->m_pkthdr.csum_data; 3437#endif 3438 break; 3439 default: 3440 return FALSE; 3441 } 3442 hdr_len = ehdrlen + ip_hlen + (th->th_off << 2); 3443 3444 *txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */ 3445 E1000_TXD_DTYP_D | /* Data descr type */ 3446 E1000_TXD_CMD_TSE); /* Do TSE on this packet */ 3447 3448 /* IP and/or TCP header checksum calculation and insertion. */ 3449 *txd_upper = ((isip6 ? 0 : E1000_TXD_POPTS_IXSM) | 3450 E1000_TXD_POPTS_TXSM) << 8; 3451 3452 curr_txd = adapter->next_avail_tx_desc; 3453 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3454 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3455 3456 /* IPv6 doesn't have a header checksum. */ 3457 if (!isip6) { 3458 /* 3459 * Start offset for header checksum calculation. 3460 * End offset for header checksum calculation. 3461 * Offset of place put the checksum. 3462 */ 3463 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3464 TXD->lower_setup.ip_fields.ipcse = 3465 htole16(ehdrlen + ip_hlen - 1); 3466 TXD->lower_setup.ip_fields.ipcso = 3467 ehdrlen + offsetof(struct ip, ip_sum); 3468 } 3469 /* 3470 * Start offset for payload checksum calculation. 3471 * End offset for payload checksum calculation. 3472 * Offset of place to put the checksum. 3473 */ 3474 TXD->upper_setup.tcp_fields.tucss = 3475 ehdrlen + ip_hlen; 3476 TXD->upper_setup.tcp_fields.tucse = 0; 3477 TXD->upper_setup.tcp_fields.tucso = 3478 ehdrlen + ip_hlen + offsetof(struct tcphdr, th_sum); 3479 /* 3480 * Payload size per packet w/o any headers. 3481 * Length of all headers up to payload. 3482 */ 3483 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3484 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3485 3486 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3487 E1000_TXD_CMD_DEXT | /* Extended descr */ 3488 E1000_TXD_CMD_TSE | /* TSE context */ 3489 (isip6 ? 0 : E1000_TXD_CMD_IP) | /* Do IP csum */ 3490 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3491 (mp->m_pkthdr.len - (hdr_len))); /* Total len */ 3492 3493 tx_buffer->m_head = NULL; 3494 tx_buffer->next_eop = -1; 3495 3496 if (++curr_txd == adapter->num_tx_desc) 3497 curr_txd = 0; 3498 3499 adapter->num_tx_desc_avail--; 3500 adapter->next_avail_tx_desc = curr_txd; 3501 adapter->tx_tso = TRUE; 3502 3503 return TRUE; 3504} 3505 3506 3507/********************************************************************** 3508 * 3509 * Setup work for hardware segmentation offload (TSO) on 3510 * adapters using advanced tx descriptors 3511 * 3512 **********************************************************************/ 3513static boolean_t 3514em_tso_adv_setup(struct adapter *adapter, struct mbuf *mp, u32 *paylen) 3515{ 3516 struct e1000_adv_tx_context_desc *TXD; 3517 struct em_buffer *tx_buffer; 3518 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3519 u32 mss_l4len_idx = 0; 3520 u16 vtag = 0; 3521 int ctxd, ehdrlen, hdrlen, ip_hlen, tcp_hlen; 3522 struct ether_vlan_header *eh; 3523 struct ip *ip; 3524 struct tcphdr *th; 3525 3526 if (((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) || 3527 (mp->m_pkthdr.len <= EM_TX_BUFFER_SIZE)) 3528 return FALSE; 3529 3530 /* 3531 * Determine where frame payload starts. 3532 * Jump over vlan headers if already present 3533 */ 3534 eh = mtod(mp, struct ether_vlan_header *); 3535 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) 3536 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3537 else 3538 ehdrlen = ETHER_HDR_LEN; 3539 3540 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3541 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3542 return FALSE; 3543 3544 /* Only supports IPV4 for now */ 3545 ctxd = adapter->next_avail_tx_desc; 3546 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3547 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3548 3549 ip = (struct ip *)(mp->m_data + ehdrlen); 3550 if (ip->ip_p != IPPROTO_TCP) 3551 return FALSE; /* 0 */ 3552 ip->ip_len = 0; 3553 ip->ip_sum = 0; 3554 ip_hlen = ip->ip_hl << 2; 3555 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3556 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3557 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3558 tcp_hlen = th->th_off << 2; 3559 hdrlen = ehdrlen + ip_hlen + tcp_hlen; 3560 /* Calculate payload, this is used in the transmit desc in encap */ 3561 *paylen = mp->m_pkthdr.len - hdrlen; 3562 3563 /* VLAN MACLEN IPLEN */ 3564 if (mp->m_flags & M_VLANTAG) { 3565 vtag = htole16(mp->m_pkthdr.ether_vtag); 3566 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3567 } 3568 vlan_macip_lens |= (ehdrlen << E1000_ADVTXD_MACLEN_SHIFT); 3569 vlan_macip_lens |= ip_hlen; 3570 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3571 3572 /* ADV DTYPE TUCMD */ 3573 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3574 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3575 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3576 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3577 3578 /* MSS L4LEN IDX */ 3579 mss_l4len_idx |= (mp->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT); 3580 mss_l4len_idx |= (tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 3581 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 3582 3583 TXD->seqnum_seed = htole32(0); 3584 tx_buffer->m_head = NULL; 3585 tx_buffer->next_eop = -1; 3586 3587 if (++ctxd == adapter->num_tx_desc) 3588 ctxd = 0; 3589 3590 adapter->num_tx_desc_avail--; 3591 adapter->next_avail_tx_desc = ctxd; 3592 return TRUE; 3593} 3594 3595 3596/********************************************************************* 3597 * 3598 * Advanced Context Descriptor setup for VLAN or CSUM 3599 * 3600 **********************************************************************/ 3601 3602static boolean_t 3603em_tx_adv_ctx_setup(struct adapter *adapter, struct mbuf *mp) 3604{ 3605 struct e1000_adv_tx_context_desc *TXD; 3606 struct em_buffer *tx_buffer; 3607 uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3608 struct ether_vlan_header *eh; 3609 struct ip *ip; 3610 struct ip6_hdr *ip6; 3611 int ehdrlen, ip_hlen; 3612 u16 etype; 3613 u8 ipproto; 3614 3615 int ctxd = adapter->next_avail_tx_desc; 3616 u16 vtag = 0; 3617 3618 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3619 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3620 3621 /* 3622 ** In advanced descriptors the vlan tag must 3623 ** be placed into the descriptor itself. 3624 */ 3625 if (mp->m_flags & M_VLANTAG) { 3626 vtag = htole16(mp->m_pkthdr.ether_vtag); 3627 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3628 } 3629 3630 /* 3631 * Determine where frame payload starts. 3632 * Jump over vlan headers if already present, 3633 * helpful for QinQ too. 3634 */ 3635 eh = mtod(mp, struct ether_vlan_header *); 3636 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3637 etype = ntohs(eh->evl_proto); 3638 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3639 } else { 3640 etype = ntohs(eh->evl_encap_proto); 3641 ehdrlen = ETHER_HDR_LEN; 3642 } 3643 3644 /* Set the ether header length */ 3645 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 3646 3647 switch (etype) { 3648 case ETHERTYPE_IP: 3649 ip = (struct ip *)(mp->m_data + ehdrlen); 3650 ip_hlen = ip->ip_hl << 2; 3651 if (mp->m_len < ehdrlen + ip_hlen) 3652 return FALSE; /* failure */ 3653 ipproto = ip->ip_p; 3654 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3655 break; 3656 case ETHERTYPE_IPV6: 3657 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3658 ip_hlen = sizeof(struct ip6_hdr); 3659 if (mp->m_len < ehdrlen + ip_hlen) 3660 return FALSE; /* failure */ 3661 ipproto = ip6->ip6_nxt; 3662 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 3663 break; 3664 default: 3665 return FALSE; 3666 } 3667 3668 vlan_macip_lens |= ip_hlen; 3669 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3670 3671 switch (ipproto) { 3672 case IPPROTO_TCP: 3673 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 3674 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3675 break; 3676 case IPPROTO_UDP: 3677 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 3678 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3679 break; 3680 } 3681 3682 /* Now copy bits into descriptor */ 3683 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3684 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3685 TXD->seqnum_seed = htole32(0); 3686 TXD->mss_l4len_idx = htole32(0); 3687 3688 tx_buffer->m_head = NULL; 3689 tx_buffer->next_eop = -1; 3690 3691 /* We've consumed the first desc, adjust counters */ 3692 if (++ctxd == adapter->num_tx_desc) 3693 ctxd = 0; 3694 adapter->next_avail_tx_desc = ctxd; 3695 --adapter->num_tx_desc_avail; 3696 3697 return TRUE; 3698} 3699 3700 3701/********************************************************************** 3702 * 3703 * Examine each tx_buffer in the used queue. If the hardware is done 3704 * processing the packet then free associated resources. The 3705 * tx_buffer is put back on the free queue. 3706 * 3707 **********************************************************************/ 3708static void 3709em_txeof(struct adapter *adapter) 3710{ 3711 int first, last, done, num_avail; 3712 struct em_buffer *tx_buffer; 3713 struct e1000_tx_desc *tx_desc, *eop_desc; 3714 struct ifnet *ifp = adapter->ifp; 3715 3716 EM_LOCK_ASSERT(adapter); 3717 3718 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3719 return; 3720 3721 num_avail = adapter->num_tx_desc_avail; 3722 first = adapter->next_tx_to_clean; 3723 tx_desc = &adapter->tx_desc_base[first]; 3724 tx_buffer = &adapter->tx_buffer_area[first]; 3725 last = tx_buffer->next_eop; 3726 eop_desc = &adapter->tx_desc_base[last]; 3727 3728 /* 3729 * What this does is get the index of the 3730 * first descriptor AFTER the EOP of the 3731 * first packet, that way we can do the 3732 * simple comparison on the inner while loop. 3733 */ 3734 if (++last == adapter->num_tx_desc) 3735 last = 0; 3736 done = last; 3737 3738 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3739 BUS_DMASYNC_POSTREAD); 3740 3741 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3742 /* We clean the range of the packet */ 3743 while (first != done) { 3744 tx_desc->upper.data = 0; 3745 tx_desc->lower.data = 0; 3746 tx_desc->buffer_addr = 0; 3747 num_avail++; 3748 3749 if (tx_buffer->m_head) { 3750 ifp->if_opackets++; 3751 bus_dmamap_sync(adapter->txtag, 3752 tx_buffer->map, 3753 BUS_DMASYNC_POSTWRITE); 3754 bus_dmamap_unload(adapter->txtag, 3755 tx_buffer->map); 3756 3757 m_freem(tx_buffer->m_head); 3758 tx_buffer->m_head = NULL; 3759 } 3760 tx_buffer->next_eop = -1; 3761 3762 if (++first == adapter->num_tx_desc) 3763 first = 0; 3764 3765 tx_buffer = &adapter->tx_buffer_area[first]; 3766 tx_desc = &adapter->tx_desc_base[first]; 3767 } 3768 /* See if we can continue to the next packet */ 3769 last = tx_buffer->next_eop; 3770 if (last != -1) { 3771 eop_desc = &adapter->tx_desc_base[last]; 3772 /* Get new done point */ 3773 if (++last == adapter->num_tx_desc) last = 0; 3774 done = last; 3775 } else 3776 break; 3777 } 3778 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3779 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3780 3781 adapter->next_tx_to_clean = first; 3782 3783 /* 3784 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3785 * that it is OK to send packets. 3786 * If there are no pending descriptors, clear the timeout. Otherwise, 3787 * if some descriptors have been freed, restart the timeout. 3788 */ 3789 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 3790 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3791 /* All clean, turn off the timer */ 3792 if (num_avail == adapter->num_tx_desc) 3793 adapter->watchdog_timer = 0; 3794 /* Some cleaned, reset the timer */ 3795 else if (num_avail != adapter->num_tx_desc_avail) 3796 adapter->watchdog_timer = EM_TX_TIMEOUT; 3797 } 3798 adapter->num_tx_desc_avail = num_avail; 3799 return; 3800} 3801 3802/********************************************************************* 3803 * 3804 * Get a buffer from system mbuf buffer pool. 3805 * 3806 **********************************************************************/ 3807static int 3808em_get_buf(struct adapter *adapter, int i) 3809{ 3810 struct mbuf *m; 3811 bus_dma_segment_t segs[1]; 3812 bus_dmamap_t map; 3813 struct em_buffer *rx_buffer; 3814 int error, nsegs; 3815 3816 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3817 if (m == NULL) { 3818 adapter->mbuf_cluster_failed++; 3819 return (ENOBUFS); 3820 } 3821 m->m_len = m->m_pkthdr.len = MCLBYTES; 3822 3823 if (adapter->hw.mac.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3824 m_adj(m, ETHER_ALIGN); 3825 3826 /* 3827 * Using memory from the mbuf cluster pool, invoke the 3828 * bus_dma machinery to arrange the memory mapping. 3829 */ 3830 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, 3831 adapter->rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 3832 if (error != 0) { 3833 m_free(m); 3834 return (error); 3835 } 3836 3837 /* If nsegs is wrong then the stack is corrupt. */ 3838 KASSERT(nsegs == 1, ("Too many segments returned!")); 3839 3840 rx_buffer = &adapter->rx_buffer_area[i]; 3841 if (rx_buffer->m_head != NULL) 3842 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3843 3844 map = rx_buffer->map; 3845 rx_buffer->map = adapter->rx_sparemap; 3846 adapter->rx_sparemap = map; 3847 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 3848 rx_buffer->m_head = m; 3849 3850 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 3851 return (0); 3852} 3853 3854/********************************************************************* 3855 * 3856 * Allocate memory for rx_buffer structures. Since we use one 3857 * rx_buffer per received packet, the maximum number of rx_buffer's 3858 * that we'll need is equal to the number of receive descriptors 3859 * that we've allocated. 3860 * 3861 **********************************************************************/ 3862static int 3863em_allocate_receive_structures(struct adapter *adapter) 3864{ 3865 device_t dev = adapter->dev; 3866 struct em_buffer *rx_buffer; 3867 int i, error; 3868 3869 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 3870 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT); 3871 if (adapter->rx_buffer_area == NULL) { 3872 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 3873 return (ENOMEM); 3874 } 3875 3876 bzero(adapter->rx_buffer_area, 3877 sizeof(struct em_buffer) * adapter->num_rx_desc); 3878 3879 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3880 1, 0, /* alignment, bounds */ 3881 BUS_SPACE_MAXADDR, /* lowaddr */ 3882 BUS_SPACE_MAXADDR, /* highaddr */ 3883 NULL, NULL, /* filter, filterarg */ 3884 MCLBYTES, /* maxsize */ 3885 1, /* nsegments */ 3886 MCLBYTES, /* maxsegsize */ 3887 0, /* flags */ 3888 NULL, /* lockfunc */ 3889 NULL, /* lockarg */ 3890 &adapter->rxtag); 3891 if (error) { 3892 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 3893 __func__, error); 3894 goto fail; 3895 } 3896 3897 /* Create the spare map (used by getbuf) */ 3898 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 3899 &adapter->rx_sparemap); 3900 if (error) { 3901 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 3902 __func__, error); 3903 goto fail; 3904 } 3905 3906 rx_buffer = adapter->rx_buffer_area; 3907 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 3908 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 3909 &rx_buffer->map); 3910 if (error) { 3911 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 3912 __func__, error); 3913 goto fail; 3914 } 3915 } 3916 3917 /* Setup the initial buffers */ 3918 for (i = 0; i < adapter->num_rx_desc; i++) { 3919 error = em_get_buf(adapter, i); 3920 if (error) 3921 goto fail; 3922 } 3923 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3925 3926 return (0); 3927 3928fail: 3929 em_free_receive_structures(adapter); 3930 return (error); 3931} 3932 3933/********************************************************************* 3934 * 3935 * Allocate and initialize receive structures. 3936 * 3937 **********************************************************************/ 3938static int 3939em_setup_receive_structures(struct adapter *adapter) 3940{ 3941 int error; 3942 3943 bzero(adapter->rx_desc_base, 3944 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3945 3946 if ((error = em_allocate_receive_structures(adapter)) !=0) 3947 return (error); 3948 3949 /* Setup our descriptor pointers */ 3950 adapter->next_rx_desc_to_check = 0; 3951 3952 return (0); 3953} 3954 3955/********************************************************************* 3956 * 3957 * Enable receive unit. 3958 * 3959 **********************************************************************/ 3960static void 3961em_initialize_receive_unit(struct adapter *adapter) 3962{ 3963 struct ifnet *ifp = adapter->ifp; 3964 uint64_t bus_addr; 3965 uint32_t reg_rctl; 3966 uint32_t reg_rxcsum; 3967 3968 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 3969 3970 /* 3971 * Make sure receives are disabled while setting 3972 * up the descriptor ring 3973 */ 3974 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3975 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl & ~E1000_RCTL_EN); 3976 3977 if(adapter->hw.mac.type >= e1000_82540) { 3978 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3979 adapter->rx_abs_int_delay.value); 3980 /* 3981 * Set the interrupt throttling rate. Value is calculated 3982 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3983 */ 3984#define MAX_INTS_PER_SEC 8000 3985#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 3986 E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); 3987 } 3988 3989 /* Setup the Base and Length of the Rx Descriptor Ring */ 3990 bus_addr = adapter->rxdma.dma_paddr; 3991 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN, adapter->num_rx_desc * 3992 sizeof(struct e1000_rx_desc)); 3993 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH, (uint32_t)(bus_addr >> 32)); 3994 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL, (uint32_t)bus_addr); 3995 3996 /* Setup the Receive Control Register */ 3997 reg_rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3998 reg_rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3999 E1000_RCTL_RDMTS_HALF | 4000 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4001 4002 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 4003 reg_rctl |= E1000_RCTL_SBP; 4004 else 4005 reg_rctl &= ~E1000_RCTL_SBP; 4006 4007 switch (adapter->rx_buffer_len) { 4008 default: 4009 case 2048: 4010 reg_rctl |= E1000_RCTL_SZ_2048; 4011 break; 4012 case 4096: 4013 reg_rctl |= E1000_RCTL_SZ_4096 | 4014 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4015 break; 4016 case 8192: 4017 reg_rctl |= E1000_RCTL_SZ_8192 | 4018 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4019 break; 4020 case 16384: 4021 reg_rctl |= E1000_RCTL_SZ_16384 | 4022 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4023 break; 4024 } 4025 4026 if (ifp->if_mtu > ETHERMTU) 4027 reg_rctl |= E1000_RCTL_LPE; 4028 else 4029 reg_rctl &= ~E1000_RCTL_LPE; 4030 4031 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 4032 if ((adapter->hw.mac.type >= e1000_82543) && 4033 (ifp->if_capenable & IFCAP_RXCSUM)) { 4034 reg_rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 4035 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 4036 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, reg_rxcsum); 4037 } 4038 4039 /* 4040 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 4041 ** long latencies are observed, like Lenovo X60. This 4042 ** change eliminates the problem, but since having positive 4043 ** values in RDTR is a known source of problems on other 4044 ** platforms another solution is being sought. 4045 */ 4046 if (adapter->hw.mac.type == e1000_82573) 4047 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 0x20); 4048 4049 /* Enable Receives */ 4050 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 4051 4052 /* 4053 * Setup the HW Rx Head and 4054 * Tail Descriptor Pointers 4055 */ 4056 E1000_WRITE_REG(&adapter->hw, E1000_RDH, 0); 4057 E1000_WRITE_REG(&adapter->hw, E1000_RDT, adapter->num_rx_desc - 1); 4058 4059 return; 4060} 4061 4062/********************************************************************* 4063 * 4064 * Free receive related data structures. 4065 * 4066 **********************************************************************/ 4067static void 4068em_free_receive_structures(struct adapter *adapter) 4069{ 4070 struct em_buffer *rx_buffer; 4071 int i; 4072 4073 INIT_DEBUGOUT("free_receive_structures: begin"); 4074 4075 if (adapter->rx_sparemap) { 4076 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 4077 adapter->rx_sparemap = NULL; 4078 } 4079 4080 /* Cleanup any existing buffers */ 4081 if (adapter->rx_buffer_area != NULL) { 4082 rx_buffer = adapter->rx_buffer_area; 4083 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4084 if (rx_buffer->m_head != NULL) { 4085 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4086 BUS_DMASYNC_POSTREAD); 4087 bus_dmamap_unload(adapter->rxtag, 4088 rx_buffer->map); 4089 m_freem(rx_buffer->m_head); 4090 rx_buffer->m_head = NULL; 4091 } else if (rx_buffer->map != NULL) 4092 bus_dmamap_unload(adapter->rxtag, 4093 rx_buffer->map); 4094 if (rx_buffer->map != NULL) { 4095 bus_dmamap_destroy(adapter->rxtag, 4096 rx_buffer->map); 4097 rx_buffer->map = NULL; 4098 } 4099 } 4100 } 4101 4102 if (adapter->rx_buffer_area != NULL) { 4103 free(adapter->rx_buffer_area, M_DEVBUF); 4104 adapter->rx_buffer_area = NULL; 4105 } 4106 4107 if (adapter->rxtag != NULL) { 4108 bus_dma_tag_destroy(adapter->rxtag); 4109 adapter->rxtag = NULL; 4110 } 4111} 4112 4113/********************************************************************* 4114 * 4115 * This routine executes in interrupt context. It replenishes 4116 * the mbufs in the descriptor and sends data which has been 4117 * dma'ed into host memory to upper layer. 4118 * 4119 * We loop at most count times if count is > 0, or until done if 4120 * count < 0. 4121 * 4122 *********************************************************************/ 4123static int 4124em_rxeof(struct adapter *adapter, int count) 4125{ 4126 struct ifnet *ifp; 4127 struct mbuf *mp; 4128 uint8_t accept_frame = 0; 4129 uint8_t eop = 0; 4130 uint16_t len, desc_len, prev_len_adj; 4131 int i; 4132 4133 /* Pointer to the receive descriptor being examined. */ 4134 struct e1000_rx_desc *current_desc; 4135 uint8_t status; 4136 4137 ifp = adapter->ifp; 4138 i = adapter->next_rx_desc_to_check; 4139 current_desc = &adapter->rx_desc_base[i]; 4140 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4141 BUS_DMASYNC_POSTREAD); 4142 4143 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4144 return (0); 4145 4146 while ((current_desc->status & E1000_RXD_STAT_DD) && 4147 (count != 0) && 4148 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4149 struct mbuf *m = NULL; 4150 4151 mp = adapter->rx_buffer_area[i].m_head; 4152 /* 4153 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 4154 * needs to access the last received byte in the mbuf. 4155 */ 4156 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 4157 BUS_DMASYNC_POSTREAD); 4158 4159 accept_frame = 1; 4160 prev_len_adj = 0; 4161 desc_len = le16toh(current_desc->length); 4162 status = current_desc->status; 4163 if (status & E1000_RXD_STAT_EOP) { 4164 count--; 4165 eop = 1; 4166 if (desc_len < ETHER_CRC_LEN) { 4167 len = 0; 4168 prev_len_adj = ETHER_CRC_LEN - desc_len; 4169 } else 4170 len = desc_len - ETHER_CRC_LEN; 4171 } else { 4172 eop = 0; 4173 len = desc_len; 4174 } 4175 4176 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 4177 uint8_t last_byte; 4178 uint32_t pkt_len = desc_len; 4179 4180 if (adapter->fmp != NULL) 4181 pkt_len += adapter->fmp->m_pkthdr.len; 4182 4183 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 4184 if (TBI_ACCEPT(&adapter->hw, status, 4185 current_desc->errors, pkt_len, last_byte)) { 4186 e1000_tbi_adjust_stats_82543(&adapter->hw, 4187 &adapter->stats, pkt_len, 4188 adapter->hw.mac.addr); 4189 if (len > 0) 4190 len--; 4191 } else 4192 accept_frame = 0; 4193 } 4194 4195 if (accept_frame) { 4196 if (em_get_buf(adapter, i) != 0) { 4197 ifp->if_iqdrops++; 4198 goto discard; 4199 } 4200 4201 /* Assign correct length to the current fragment */ 4202 mp->m_len = len; 4203 4204 if (adapter->fmp == NULL) { 4205 mp->m_pkthdr.len = len; 4206 adapter->fmp = mp; /* Store the first mbuf */ 4207 adapter->lmp = mp; 4208 } else { 4209 /* Chain mbuf's together */ 4210 mp->m_flags &= ~M_PKTHDR; 4211 /* 4212 * Adjust length of previous mbuf in chain if 4213 * we received less than 4 bytes in the last 4214 * descriptor. 4215 */ 4216 if (prev_len_adj > 0) { 4217 adapter->lmp->m_len -= prev_len_adj; 4218 adapter->fmp->m_pkthdr.len -= 4219 prev_len_adj; 4220 } 4221 adapter->lmp->m_next = mp; 4222 adapter->lmp = adapter->lmp->m_next; 4223 adapter->fmp->m_pkthdr.len += len; 4224 } 4225 4226 if (eop) { 4227 adapter->fmp->m_pkthdr.rcvif = ifp; 4228 ifp->if_ipackets++; 4229 em_receive_checksum(adapter, current_desc, 4230 adapter->fmp); 4231#ifndef __NO_STRICT_ALIGNMENT 4232 if (adapter->hw.mac.max_frame_size > 4233 (MCLBYTES - ETHER_ALIGN) && 4234 em_fixup_rx(adapter) != 0) 4235 goto skip; 4236#endif 4237 if (status & E1000_RXD_STAT_VP) { 4238 adapter->fmp->m_pkthdr.ether_vtag = 4239 (le16toh(current_desc->special) & 4240 E1000_RXD_SPC_VLAN_MASK); 4241 adapter->fmp->m_flags |= M_VLANTAG; 4242 } 4243#ifndef __NO_STRICT_ALIGNMENT 4244skip: 4245#endif 4246 m = adapter->fmp; 4247 adapter->fmp = NULL; 4248 adapter->lmp = NULL; 4249 } 4250 } else { 4251 ifp->if_ierrors++; 4252discard: 4253 /* Reuse loaded DMA map and just update mbuf chain */ 4254 mp = adapter->rx_buffer_area[i].m_head; 4255 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 4256 mp->m_data = mp->m_ext.ext_buf; 4257 mp->m_next = NULL; 4258 if (adapter->hw.mac.max_frame_size <= 4259 (MCLBYTES - ETHER_ALIGN)) 4260 m_adj(mp, ETHER_ALIGN); 4261 if (adapter->fmp != NULL) { 4262 m_freem(adapter->fmp); 4263 adapter->fmp = NULL; 4264 adapter->lmp = NULL; 4265 } 4266 m = NULL; 4267 } 4268 4269 /* Zero out the receive descriptors status. */ 4270 current_desc->status = 0; 4271 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4272 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4273 4274 /* Advance our pointers to the next descriptor. */ 4275 if (++i == adapter->num_rx_desc) 4276 i = 0; 4277 if (m != NULL) { 4278 adapter->next_rx_desc_to_check = i; 4279#ifdef DEVICE_POLLING 4280 EM_UNLOCK(adapter); 4281 (*ifp->if_input)(ifp, m); 4282 EM_LOCK(adapter); 4283#else 4284 /* Already running unlocked */ 4285 (*ifp->if_input)(ifp, m); 4286#endif 4287 i = adapter->next_rx_desc_to_check; 4288 } 4289 current_desc = &adapter->rx_desc_base[i]; 4290 } 4291 adapter->next_rx_desc_to_check = i; 4292 4293 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 4294 if (--i < 0) 4295 i = adapter->num_rx_desc - 1; 4296 E1000_WRITE_REG(&adapter->hw, E1000_RDT, i); 4297 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4298 return (0); 4299 4300 return (1); 4301} 4302 4303#ifndef __NO_STRICT_ALIGNMENT 4304/* 4305 * When jumbo frames are enabled we should realign entire payload on 4306 * architecures with strict alignment. This is serious design mistake of 8254x 4307 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 4308 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 4309 * payload. On architecures without strict alignment restrictions 8254x still 4310 * performs unaligned memory access which would reduce the performance too. 4311 * To avoid copying over an entire frame to align, we allocate a new mbuf and 4312 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 4313 * existing mbuf chain. 4314 * 4315 * Be aware, best performance of the 8254x is achived only when jumbo frame is 4316 * not used at all on architectures with strict alignment. 4317 */ 4318static int 4319em_fixup_rx(struct adapter *adapter) 4320{ 4321 struct mbuf *m, *n; 4322 int error; 4323 4324 error = 0; 4325 m = adapter->fmp; 4326 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 4327 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 4328 m->m_data += ETHER_HDR_LEN; 4329 } else { 4330 MGETHDR(n, M_DONTWAIT, MT_DATA); 4331 if (n != NULL) { 4332 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 4333 m->m_data += ETHER_HDR_LEN; 4334 m->m_len -= ETHER_HDR_LEN; 4335 n->m_len = ETHER_HDR_LEN; 4336 M_MOVE_PKTHDR(n, m); 4337 n->m_next = m; 4338 adapter->fmp = n; 4339 } else { 4340 adapter->dropped_pkts++; 4341 m_freem(adapter->fmp); 4342 adapter->fmp = NULL; 4343 error = ENOMEM; 4344 } 4345 } 4346 4347 return (error); 4348} 4349#endif 4350 4351/********************************************************************* 4352 * 4353 * Verify that the hardware indicated that the checksum is valid. 4354 * Inform the stack about the status of checksum so that stack 4355 * doesn't spend time verifying the checksum. 4356 * 4357 *********************************************************************/ 4358static void 4359em_receive_checksum(struct adapter *adapter, 4360 struct e1000_rx_desc *rx_desc, struct mbuf *mp) 4361{ 4362 /* 82543 or newer only */ 4363 if ((adapter->hw.mac.type < e1000_82543) || 4364 /* Ignore Checksum bit is set */ 4365 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 4366 mp->m_pkthdr.csum_flags = 0; 4367 return; 4368 } 4369 4370 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 4371 /* Did it pass? */ 4372 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 4373 /* IP Checksum Good */ 4374 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 4375 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4376 4377 } else { 4378 mp->m_pkthdr.csum_flags = 0; 4379 } 4380 } 4381 4382 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 4383 /* Did it pass? */ 4384 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 4385 mp->m_pkthdr.csum_flags |= 4386 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 4387 mp->m_pkthdr.csum_data = htons(0xffff); 4388 } 4389 } 4390} 4391 4392 4393static void 4394em_enable_vlans(struct adapter *adapter) 4395{ 4396 uint32_t ctrl; 4397 4398 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 4399 4400 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 4401 ctrl |= E1000_CTRL_VME; 4402 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 4403} 4404 4405static void 4406em_enable_intr(struct adapter *adapter) 4407{ 4408 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 4409 (IMS_ENABLE_MASK)); 4410} 4411 4412static void 4413em_disable_intr(struct adapter *adapter) 4414{ 4415 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 4416} 4417 4418/* 4419 * Bit of a misnomer, what this really means is 4420 * to enable OS management of the system... aka 4421 * to disable special hardware management features 4422 */ 4423static void 4424em_init_manageability(struct adapter *adapter) 4425{ 4426 /* A shared code workaround */ 4427#define E1000_82542_MANC2H E1000_MANC2H 4428 if (adapter->has_manage) { 4429 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 4430 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4431 4432 /* disable hardware interception of ARP */ 4433 manc &= ~(E1000_MANC_ARP_EN); 4434 4435 /* enable receiving management packets to the host */ 4436 if (adapter->hw.mac.type >= e1000_82571) { 4437 manc |= E1000_MANC_EN_MNG2HOST; 4438#define E1000_MNG2HOST_PORT_623 (1 << 5) 4439#define E1000_MNG2HOST_PORT_664 (1 << 6) 4440 manc2h |= E1000_MNG2HOST_PORT_623; 4441 manc2h |= E1000_MNG2HOST_PORT_664; 4442 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 4443 } 4444 4445 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4446 } 4447} 4448 4449/* 4450 * Give control back to hardware management 4451 * controller if there is one. 4452 */ 4453static void 4454em_release_manageability(struct adapter *adapter) 4455{ 4456 if (adapter->has_manage) { 4457 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4458 4459 /* re-enable hardware interception of ARP */ 4460 manc |= E1000_MANC_ARP_EN; 4461 4462 if (adapter->hw.mac.type >= e1000_82571) 4463 manc &= ~E1000_MANC_EN_MNG2HOST; 4464 4465 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4466 } 4467} 4468 4469/* 4470 * em_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4471 * For ASF and Pass Through versions of f/w this means that 4472 * the driver is loaded. For AMT version (only with 82573) 4473 * of the f/w this means that the network i/f is open. 4474 * 4475 */ 4476static void 4477em_get_hw_control(struct adapter *adapter) 4478{ 4479 u32 ctrl_ext, swsm; 4480 4481 /* Let firmware know the driver has taken over */ 4482 switch (adapter->hw.mac.type) { 4483 case e1000_82573: 4484 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4485 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4486 swsm | E1000_SWSM_DRV_LOAD); 4487 break; 4488 case e1000_82571: 4489 case e1000_82572: 4490 case e1000_80003es2lan: 4491 case e1000_ich8lan: 4492 case e1000_ich9lan: 4493 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4494 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4495 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4496 break; 4497 default: 4498 break; 4499 } 4500} 4501 4502/* 4503 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4504 * For ASF and Pass Through versions of f/w this means that the 4505 * driver is no longer loaded. For AMT version (only with 82573) i 4506 * of the f/w this means that the network i/f is closed. 4507 * 4508 */ 4509static void 4510em_release_hw_control(struct adapter *adapter) 4511{ 4512 u32 ctrl_ext, swsm; 4513 4514 /* Let firmware taken over control of h/w */ 4515 switch (adapter->hw.mac.type) { 4516 case e1000_82573: 4517 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4518 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4519 swsm & ~E1000_SWSM_DRV_LOAD); 4520 break; 4521 case e1000_82571: 4522 case e1000_82572: 4523 case e1000_80003es2lan: 4524 case e1000_ich8lan: 4525 case e1000_ich9lan: 4526 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4527 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4528 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4529 break; 4530 default: 4531 break; 4532 4533 } 4534} 4535 4536static int 4537em_is_valid_ether_addr(uint8_t *addr) 4538{ 4539 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4540 4541 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4542 return (FALSE); 4543 } 4544 4545 return (TRUE); 4546} 4547 4548/* 4549 * NOTE: the following routines using the e1000 4550 * naming style are provided to the shared 4551 * code which expects that rather than 'em' 4552 */ 4553 4554void 4555e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4556{ 4557 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 4558} 4559 4560void 4561e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4562{ 4563 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 4564} 4565 4566void 4567e1000_pci_set_mwi(struct e1000_hw *hw) 4568{ 4569 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4570 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 4571} 4572 4573void 4574e1000_pci_clear_mwi(struct e1000_hw *hw) 4575{ 4576 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4577 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 4578} 4579 4580/* 4581 * Read the PCI Express capabilities 4582 */ 4583int32_t 4584e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4585{ 4586 int32_t error = E1000_SUCCESS; 4587 uint16_t cap_off; 4588 4589 switch (hw->mac.type) { 4590 4591 case e1000_82571: 4592 case e1000_82572: 4593 case e1000_82573: 4594 case e1000_80003es2lan: 4595 cap_off = 0xE0; 4596 e1000_read_pci_cfg(hw, cap_off + reg, value); 4597 break; 4598 default: 4599 error = ~E1000_NOT_IMPLEMENTED; 4600 break; 4601 } 4602 4603 return (error); 4604} 4605 4606int32_t 4607e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, uint32_t size) 4608{ 4609 int32_t error = 0; 4610 4611 hw->dev_spec = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 4612 if (hw->dev_spec == NULL) 4613 error = ENOMEM; 4614 bzero(hw->dev_spec, size); 4615 4616 return (error); 4617} 4618 4619void 4620e1000_free_dev_spec_struct(struct e1000_hw *hw) 4621{ 4622 if (hw->dev_spec != NULL) 4623 free(hw->dev_spec, M_DEVBUF); 4624 return; 4625} 4626 4627/* 4628 * Enable PCI Wake On Lan capability 4629 */ 4630void 4631em_enable_wakeup(device_t dev) 4632{ 4633 u16 cap, status; 4634 u8 id; 4635 4636 /* First find the capabilities pointer*/ 4637 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4638 /* Read the PM Capabilities */ 4639 id = pci_read_config(dev, cap, 1); 4640 if (id != PCIY_PMG) /* Something wrong */ 4641 return; 4642 /* OK, we have the power capabilities, so 4643 now get the status register */ 4644 cap += PCIR_POWER_STATUS; 4645 status = pci_read_config(dev, cap, 2); 4646 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4647 pci_write_config(dev, cap, status, 2); 4648 return; 4649} 4650 4651 4652/********************************************************************* 4653* 82544 Coexistence issue workaround. 4654* There are 2 issues. 4655* 1. Transmit Hang issue. 4656* To detect this issue, following equation can be used... 4657* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4658* If SUM[3:0] is in between 1 to 4, we will have this issue. 4659* 4660* 2. DAC issue. 4661* To detect this issue, following equation can be used... 4662* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4663* If SUM[3:0] is in between 9 to c, we will have this issue. 4664* 4665* 4666* WORKAROUND: 4667* Make sure we do not have ending address 4668* as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4669* 4670*************************************************************************/ 4671static uint32_t 4672em_fill_descriptors (bus_addr_t address, uint32_t length, 4673 PDESC_ARRAY desc_array) 4674{ 4675 /* Since issue is sensitive to length and address.*/ 4676 /* Let us first check the address...*/ 4677 uint32_t safe_terminator; 4678 if (length <= 4) { 4679 desc_array->descriptor[0].address = address; 4680 desc_array->descriptor[0].length = length; 4681 desc_array->elements = 1; 4682 return (desc_array->elements); 4683 } 4684 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + 4685 (length & 0xF)) & 0xF); 4686 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4687 if (safe_terminator == 0 || 4688 (safe_terminator > 4 && 4689 safe_terminator < 9) || 4690 (safe_terminator > 0xC && 4691 safe_terminator <= 0xF)) { 4692 desc_array->descriptor[0].address = address; 4693 desc_array->descriptor[0].length = length; 4694 desc_array->elements = 1; 4695 return (desc_array->elements); 4696 } 4697 4698 desc_array->descriptor[0].address = address; 4699 desc_array->descriptor[0].length = length - 4; 4700 desc_array->descriptor[1].address = address + (length - 4); 4701 desc_array->descriptor[1].length = 4; 4702 desc_array->elements = 2; 4703 return (desc_array->elements); 4704} 4705 4706/********************************************************************** 4707 * 4708 * Update the board statistics counters. 4709 * 4710 **********************************************************************/ 4711static void 4712em_update_stats_counters(struct adapter *adapter) 4713{ 4714 struct ifnet *ifp; 4715 4716 if(adapter->hw.media_type == e1000_media_type_copper || 4717 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4718 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4719 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4720 } 4721 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4722 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4723 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4724 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4725 4726 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4727 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4728 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4729 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4730 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4731 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4732 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4733 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4734 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4735 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4736 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4737 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4738 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4739 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4740 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4741 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4742 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4743 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4744 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4745 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4746 4747 /* For the 64-bit byte counters the low dword must be read first. */ 4748 /* Both registers clear on the read of the high dword */ 4749 4750 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, E1000_GORCL); 4751 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, E1000_GORCH); 4752 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, E1000_GOTCL); 4753 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 4754 4755 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4756 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4757 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4758 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4759 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4760 4761 adapter->stats.torl += E1000_READ_REG(&adapter->hw, E1000_TORL); 4762 adapter->stats.torh += E1000_READ_REG(&adapter->hw, E1000_TORH); 4763 adapter->stats.totl += E1000_READ_REG(&adapter->hw, E1000_TOTL); 4764 adapter->stats.toth += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4765 4766 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4767 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4768 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4769 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4770 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4771 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4772 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4773 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4774 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4775 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4776 4777 if (adapter->hw.mac.type >= e1000_82543) { 4778 adapter->stats.algnerrc += 4779 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4780 adapter->stats.rxerrc += 4781 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4782 adapter->stats.tncrs += 4783 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4784 adapter->stats.cexterr += 4785 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4786 adapter->stats.tsctc += 4787 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4788 adapter->stats.tsctfc += 4789 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4790 } 4791 ifp = adapter->ifp; 4792 4793 ifp->if_collisions = adapter->stats.colc; 4794 4795 /* Rx Errors */ 4796 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 4797 adapter->stats.crcerrs + adapter->stats.algnerrc + 4798 adapter->stats.ruc + adapter->stats.roc + 4799 adapter->stats.mpc + adapter->stats.cexterr; 4800 4801 /* Tx Errors */ 4802 ifp->if_oerrors = adapter->stats.ecol + 4803 adapter->stats.latecol + adapter->watchdog_events; 4804} 4805 4806 4807/********************************************************************** 4808 * 4809 * This routine is called only when em_display_debug_stats is enabled. 4810 * This routine provides a way to take a look at important statistics 4811 * maintained by the driver and hardware. 4812 * 4813 **********************************************************************/ 4814static void 4815em_print_debug_info(struct adapter *adapter) 4816{ 4817 device_t dev = adapter->dev; 4818 uint8_t *hw_addr = adapter->hw.hw_addr; 4819 4820 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 4821 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 4822 E1000_READ_REG(&adapter->hw, E1000_CTRL), 4823 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 4824 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 4825 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 4826 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 4827 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 4828 adapter->hw.mac.fc_high_water, 4829 adapter->hw.mac.fc_low_water); 4830 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 4831 E1000_READ_REG(&adapter->hw, E1000_TIDV), 4832 E1000_READ_REG(&adapter->hw, E1000_TADV)); 4833 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 4834 E1000_READ_REG(&adapter->hw, E1000_RDTR), 4835 E1000_READ_REG(&adapter->hw, E1000_RADV)); 4836 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 4837 (long long)adapter->tx_fifo_wrk_cnt, 4838 (long long)adapter->tx_fifo_reset_cnt); 4839 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4840 E1000_READ_REG(&adapter->hw, E1000_TDH), 4841 E1000_READ_REG(&adapter->hw, E1000_TDT)); 4842 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4843 E1000_READ_REG(&adapter->hw, E1000_RDH), 4844 E1000_READ_REG(&adapter->hw, E1000_RDT)); 4845 device_printf(dev, "Num Tx descriptors avail = %d\n", 4846 adapter->num_tx_desc_avail); 4847 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 4848 adapter->no_tx_desc_avail1); 4849 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 4850 adapter->no_tx_desc_avail2); 4851 device_printf(dev, "Std mbuf failed = %ld\n", 4852 adapter->mbuf_alloc_failed); 4853 device_printf(dev, "Std mbuf cluster failed = %ld\n", 4854 adapter->mbuf_cluster_failed); 4855 device_printf(dev, "Driver dropped packets = %ld\n", 4856 adapter->dropped_pkts); 4857 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 4858 adapter->no_tx_dma_setup); 4859} 4860 4861static void 4862em_print_hw_stats(struct adapter *adapter) 4863{ 4864 device_t dev = adapter->dev; 4865 4866 device_printf(dev, "Excessive collisions = %lld\n", 4867 (long long)adapter->stats.ecol); 4868#if (DEBUG_HW > 0) /* Dont output these errors normally */ 4869 device_printf(dev, "Symbol errors = %lld\n", 4870 (long long)adapter->stats.symerrs); 4871#endif 4872 device_printf(dev, "Sequence errors = %lld\n", 4873 (long long)adapter->stats.sec); 4874 device_printf(dev, "Defer count = %lld\n", 4875 (long long)adapter->stats.dc); 4876 device_printf(dev, "Missed Packets = %lld\n", 4877 (long long)adapter->stats.mpc); 4878 device_printf(dev, "Receive No Buffers = %lld\n", 4879 (long long)adapter->stats.rnbc); 4880 /* RLEC is inaccurate on some hardware, calculate our own. */ 4881 device_printf(dev, "Receive Length Errors = %lld\n", 4882 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 4883 device_printf(dev, "Receive errors = %lld\n", 4884 (long long)adapter->stats.rxerrc); 4885 device_printf(dev, "Crc errors = %lld\n", 4886 (long long)adapter->stats.crcerrs); 4887 device_printf(dev, "Alignment errors = %lld\n", 4888 (long long)adapter->stats.algnerrc); 4889 device_printf(dev, "Carrier extension errors = %lld\n", 4890 (long long)adapter->stats.cexterr); 4891 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 4892 device_printf(dev, "watchdog timeouts = %ld\n", 4893 adapter->watchdog_events); 4894 device_printf(dev, "XON Rcvd = %lld\n", 4895 (long long)adapter->stats.xonrxc); 4896 device_printf(dev, "XON Xmtd = %lld\n", 4897 (long long)adapter->stats.xontxc); 4898 device_printf(dev, "XOFF Rcvd = %lld\n", 4899 (long long)adapter->stats.xoffrxc); 4900 device_printf(dev, "XOFF Xmtd = %lld\n", 4901 (long long)adapter->stats.xofftxc); 4902 device_printf(dev, "Good Packets Rcvd = %lld\n", 4903 (long long)adapter->stats.gprc); 4904 device_printf(dev, "Good Packets Xmtd = %lld\n", 4905 (long long)adapter->stats.gptc); 4906 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 4907 (long long)adapter->stats.tsctc); 4908 device_printf(dev, "TSO Contexts Failed = %lld\n", 4909 (long long)adapter->stats.tsctfc); 4910} 4911 4912static int 4913em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4914{ 4915 struct adapter *adapter; 4916 int error; 4917 int result; 4918 4919 result = -1; 4920 error = sysctl_handle_int(oidp, &result, 0, req); 4921 4922 if (error || !req->newptr) 4923 return (error); 4924 4925 if (result == 1) { 4926 adapter = (struct adapter *)arg1; 4927 em_print_debug_info(adapter); 4928 } 4929 4930 return (error); 4931} 4932 4933 4934static int 4935em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4936{ 4937 struct adapter *adapter; 4938 int error; 4939 int result; 4940 4941 result = -1; 4942 error = sysctl_handle_int(oidp, &result, 0, req); 4943 4944 if (error || !req->newptr) 4945 return (error); 4946 4947 if (result == 1) { 4948 adapter = (struct adapter *)arg1; 4949 em_print_hw_stats(adapter); 4950 } 4951 4952 return (error); 4953} 4954 4955static int 4956em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4957{ 4958 struct em_int_delay_info *info; 4959 struct adapter *adapter; 4960 uint32_t regval; 4961 int error; 4962 int usecs; 4963 int ticks; 4964 4965 info = (struct em_int_delay_info *)arg1; 4966 usecs = info->value; 4967 error = sysctl_handle_int(oidp, &usecs, 0, req); 4968 if (error != 0 || req->newptr == NULL) 4969 return (error); 4970 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4971 return (EINVAL); 4972 info->value = usecs; 4973 ticks = EM_USECS_TO_TICKS(usecs); 4974 4975 adapter = info->adapter; 4976 4977 EM_LOCK(adapter); 4978 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4979 regval = (regval & ~0xffff) | (ticks & 0xffff); 4980 /* Handle a few special cases. */ 4981 switch (info->offset) { 4982 case E1000_RDTR: 4983 break; 4984 case E1000_TIDV: 4985 if (ticks == 0) { 4986 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4987 /* Don't write 0 into the TIDV register. */ 4988 regval++; 4989 } else 4990 if (adapter->hw.mac.type != e1000_82575) 4991 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4992 break; 4993 } 4994 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4995 EM_UNLOCK(adapter); 4996 return (0); 4997} 4998 4999static void 5000em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 5001 const char *description, struct em_int_delay_info *info, 5002 int offset, int value) 5003{ 5004 info->adapter = adapter; 5005 info->offset = offset; 5006 info->value = value; 5007 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 5008 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5009 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5010 info, 0, em_sysctl_int_delay, "I", description); 5011} 5012 5013#ifndef DEVICE_POLLING 5014static void 5015em_add_rx_process_limit(struct adapter *adapter, const char *name, 5016 const char *description, int *limit, int value) 5017{ 5018 *limit = value; 5019 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 5020 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5021 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 5022} 5023#endif 5024