if_em.c revision 161134
125537Sdfr/**************************************************************************
225537Sdfr
325537SdfrCopyright (c) 2001-2006, Intel Corporation
425537SdfrAll rights reserved.
525537Sdfr
625537SdfrRedistribution and use in source and binary forms, with or without
725537Sdfrmodification, are permitted provided that the following conditions are met:
825537Sdfr
925537Sdfr 1. Redistributions of source code must retain the above copyright notice,
1025537Sdfr    this list of conditions and the following disclaimer.
1125537Sdfr
1225537Sdfr 2. Redistributions in binary form must reproduce the above copyright
1325537Sdfr    notice, this list of conditions and the following disclaimer in the
1425537Sdfr    documentation and/or other materials provided with the distribution.
1525537Sdfr
1625537Sdfr 3. Neither the name of the Intel Corporation nor the names of its
1725537Sdfr    contributors may be used to endorse or promote products derived from
1825537Sdfr    this software without specific prior written permission.
1925537Sdfr
2025537SdfrTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2125537SdfrAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2225537SdfrIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2325537SdfrARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
2425537SdfrLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2525537SdfrCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2625537SdfrSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27140482SpsINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28140482SpsCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29116182SobrienARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30116182SobrienPOSSIBILITY OF SUCH DAMAGE.
31116182Sobrien
3225537Sdfr***************************************************************************/
3325537Sdfr
3425537Sdfr/*$FreeBSD: head/sys/dev/em/if_em.c 161134 2006-08-09 20:10:35Z pdeuskar $*/
3550107Smsmith
3625537Sdfr#ifdef HAVE_KERNEL_OPTION_HEADERS
3725537Sdfr#include "opt_device_polling.h"
3825537Sdfr#endif
3930994Sphk
4082749Sdillon#include <sys/param.h>
4182749Sdillon#include <sys/systm.h>
42134092Struckman#include <sys/bus.h>
4392547Sarr#include <sys/endian.h>
4492547Sarr#include <sys/kernel.h>
4592547Sarr#include <sys/kthread.h>
4625537Sdfr#include <sys/malloc.h>
4769774Sphk#include <sys/mbuf.h>
4825537Sdfr#include <sys/module.h>
4960938Sjake#include <sys/rman.h>
5025537Sdfr#include <sys/socket.h>
5190963Sarr#include <sys/sockio.h>
5290963Sarr#include <sys/sysctl.h>
5390963Sarr#include <sys/taskqueue.h>
5490963Sarr
5590963Sarr#include <machine/bus.h>
5690963Sarr#include <machine/resource.h>
5790963Sarr
5890963Sarr#include <net/bpf.h>
5990963Sarr#include <net/ethernet.h>
6025537Sdfr#include <net/if.h>
6125537Sdfr#include <net/if_arp.h>
6290963Sarr#include <net/if_dl.h>
6325537Sdfr#include <net/if_media.h>
6425537Sdfr
6592547Sarr#include <net/if_types.h>
6625537Sdfr#include <net/if_vlan_var.h>
6790963Sarr
6825537Sdfr#include <netinet/in_systm.h>
6952991Speter#include <netinet/in.h>
7090963Sarr#include <netinet/if_ether.h>
7152991Speter#include <netinet/ip.h>
72132167Sphk#include <netinet/tcp.h>
73132167Sphk#include <netinet/udp.h>
74132167Sphk
75132167Sphk#include <dev/pci/pcivar.h>
76132167Sphk#include <dev/pci/pcireg.h>
77132167Sphk#include <dev/em/if_em_hw.h>
78132167Sphk#include <dev/em/if_em.h>
79132167Sphk
80132167Sphk/*********************************************************************
8152991Speter *  Set this to one to display debug statistics
8252991Speter *********************************************************************/
8325537Sdfrint	em_display_debug_stats = 0;
8490963Sarr
8525537Sdfr/*********************************************************************
8690963Sarr *  Driver version
8792547Sarr *********************************************************************/
8890963Sarr
89108905Speterchar em_driver_version[] = "Version - 6.0.5";
9090963Sarr
9125537Sdfr
9225537Sdfr/*********************************************************************
93177253Srwatson *  PCI Device ID Table
9425537Sdfr *
9525537Sdfr *  Used by probe to select devices to load on
9690963Sarr *  Last field stores an index into em_strings
9725537Sdfr *  Last entry must be all 0s
9890963Sarr *
9925537Sdfr *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
100134092Struckman *********************************************************************/
101134092Struckman
102159957Sjhbstatic em_vendor_info_t em_vendor_info_array[] =
10392547Sarr{
10490963Sarr	/* Intel(R) PRO/1000 Network Connection */
10590963Sarr	{ 0x8086, E1000_DEV_ID_82540EM,		PCI_ANY_ID, PCI_ANY_ID, 0},
10692547Sarr	{ 0x8086, E1000_DEV_ID_82540EM_LOM,	PCI_ANY_ID, PCI_ANY_ID, 0},
107159957Sjhb	{ 0x8086, E1000_DEV_ID_82540EP,		PCI_ANY_ID, PCI_ANY_ID, 0},
10825537Sdfr	{ 0x8086, E1000_DEV_ID_82540EP_LOM,	PCI_ANY_ID, PCI_ANY_ID, 0},
10925537Sdfr	{ 0x8086, E1000_DEV_ID_82540EP_LP,	PCI_ANY_ID, PCI_ANY_ID, 0},
11025537Sdfr
11143387Sdillon	{ 0x8086, E1000_DEV_ID_82541EI,		PCI_ANY_ID, PCI_ANY_ID, 0},
11225537Sdfr	{ 0x8086, E1000_DEV_ID_82541ER,		PCI_ANY_ID, PCI_ANY_ID, 0},
11390963Sarr	{ 0x8086, E1000_DEV_ID_82541ER_LOM,	PCI_ANY_ID, PCI_ANY_ID, 0},
11490963Sarr	{ 0x8086, E1000_DEV_ID_82541EI_MOBILE,	PCI_ANY_ID, PCI_ANY_ID, 0},
11590963Sarr	{ 0x8086, E1000_DEV_ID_82541GI,		PCI_ANY_ID, PCI_ANY_ID, 0},
11625537Sdfr	{ 0x8086, E1000_DEV_ID_82541GI_LF,	PCI_ANY_ID, PCI_ANY_ID, 0},
117159957Sjhb	{ 0x8086, E1000_DEV_ID_82541GI_MOBILE,	PCI_ANY_ID, PCI_ANY_ID, 0},
11892547Sarr
11990963Sarr	{ 0x8086, E1000_DEV_ID_82542,		PCI_ANY_ID, PCI_ANY_ID, 0},
12090963Sarr
12191067Sarr	{ 0x8086, E1000_DEV_ID_82543GC_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
12290963Sarr	{ 0x8086, E1000_DEV_ID_82543GC_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
12392547Sarr
12490963Sarr	{ 0x8086, E1000_DEV_ID_82544EI_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
12590963Sarr	{ 0x8086, E1000_DEV_ID_82544EI_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
12690963Sarr	{ 0x8086, E1000_DEV_ID_82544GC_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
12792547Sarr	{ 0x8086, E1000_DEV_ID_82544GC_LOM,	PCI_ANY_ID, PCI_ANY_ID, 0},
12890963Sarr
12992547Sarr	{ 0x8086, E1000_DEV_ID_82545EM_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13091261Speter	{ 0x8086, E1000_DEV_ID_82545EM_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13191261Speter	{ 0x8086, E1000_DEV_ID_82545GM_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13291067Sarr	{ 0x8086, E1000_DEV_ID_82545GM_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13390963Sarr	{ 0x8086, E1000_DEV_ID_82545GM_SERDES,	PCI_ANY_ID, PCI_ANY_ID, 0},
134159957Sjhb
13525537Sdfr	{ 0x8086, E1000_DEV_ID_82546EB_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13625537Sdfr	{ 0x8086, E1000_DEV_ID_82546EB_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13725537Sdfr	{ 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
13846693Speter	{ 0x8086, E1000_DEV_ID_82546GB_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
13925537Sdfr	{ 0x8086, E1000_DEV_ID_82546GB_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
14090963Sarr	{ 0x8086, E1000_DEV_ID_82546GB_SERDES,	PCI_ANY_ID, PCI_ANY_ID, 0},
14190963Sarr	{ 0x8086, E1000_DEV_ID_82546GB_PCIE,	PCI_ANY_ID, PCI_ANY_ID, 0},
14225537Sdfr	{ 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
143159634Smaxim	{ 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
14490963Sarr						PCI_ANY_ID, PCI_ANY_ID, 0},
14590963Sarr
146159634Smaxim	{ 0x8086, E1000_DEV_ID_82547EI,		PCI_ANY_ID, PCI_ANY_ID, 0},
14791067Sarr	{ 0x8086, E1000_DEV_ID_82547EI_MOBILE,	PCI_ANY_ID, PCI_ANY_ID, 0},
14890963Sarr	{ 0x8086, E1000_DEV_ID_82547GI,		PCI_ANY_ID, PCI_ANY_ID, 0},
14990980Sarr
15090963Sarr	{ 0x8086, E1000_DEV_ID_82571EB_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
15190963Sarr	{ 0x8086, E1000_DEV_ID_82571EB_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
152111119Simp	{ 0x8086, E1000_DEV_ID_82571EB_SERDES,	PCI_ANY_ID, PCI_ANY_ID, 0},
153159634Smaxim
154159634Smaxim	{ 0x8086, E1000_DEV_ID_82572EI_COPPER,	PCI_ANY_ID, PCI_ANY_ID, 0},
15590980Sarr	{ 0x8086, E1000_DEV_ID_82572EI_FIBER,	PCI_ANY_ID, PCI_ANY_ID, 0},
156159634Smaxim	{ 0x8086, E1000_DEV_ID_82572EI_SERDES,	PCI_ANY_ID, PCI_ANY_ID, 0},
15790963Sarr	{ 0x8086, E1000_DEV_ID_82572EI,		PCI_ANY_ID, PCI_ANY_ID, 0},
15890963Sarr
15990963Sarr	{ 0x8086, E1000_DEV_ID_82573E,		PCI_ANY_ID, PCI_ANY_ID, 0},
16090963Sarr	{ 0x8086, E1000_DEV_ID_82573E_IAMT,	PCI_ANY_ID, PCI_ANY_ID, 0},
16190963Sarr	{ 0x8086, E1000_DEV_ID_82573L,		PCI_ANY_ID, PCI_ANY_ID, 0},
16290963Sarr	{ 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
16390963Sarr						PCI_ANY_ID, PCI_ANY_ID, 0},
16490963Sarr	{ 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
16525537Sdfr						PCI_ANY_ID, PCI_ANY_ID, 0},
16690963Sarr	{ 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
16790963Sarr						PCI_ANY_ID, PCI_ANY_ID, 0},
16890963Sarr	{ 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
16992547Sarr						PCI_ANY_ID, PCI_ANY_ID, 0},
17090980Sarr	{ 0x8086, E1000_DEV_ID_ICH8_IGP_AMT,	PCI_ANY_ID, PCI_ANY_ID, 0},
17125537Sdfr	{ 0x8086, E1000_DEV_ID_ICH8_IGP_C,	PCI_ANY_ID, PCI_ANY_ID, 0},
17225537Sdfr	{ 0x8086, E1000_DEV_ID_ICH8_IFE,	PCI_ANY_ID, PCI_ANY_ID, 0},
17325537Sdfr
17425537Sdfr	/* required last entry */
17525537Sdfr	{ 0, 0, 0, 0, 0}
17625537Sdfr};
17792547Sarr
17892547Sarr/*********************************************************************
17990963Sarr *  Table of branding strings for all supported NICs.
18090963Sarr *********************************************************************/
18125537Sdfr
18225537Sdfrstatic char *em_strings[] = {
18325537Sdfr	"Intel(R) PRO/1000 Network Connection"
18425537Sdfr};
18525537Sdfr
18625537Sdfr/*********************************************************************
18792547Sarr *  Function prototypes
18892547Sarr *********************************************************************/
18990963Sarrstatic int	em_probe(device_t);
19090963Sarrstatic int	em_attach(device_t);
19125537Sdfrstatic int	em_detach(device_t);
19290963Sarrstatic int	em_shutdown(device_t);
19392547Sarrstatic int	em_suspend(device_t);
19490963Sarrstatic int	em_resume(device_t);
19590963Sarrstatic void	em_start(struct ifnet *);
19690963Sarrstatic void	em_start_locked(struct ifnet *ifp);
19790963Sarrstatic int	em_ioctl(struct ifnet *, u_long, caddr_t);
19890963Sarrstatic void	em_watchdog(struct ifnet *);
19992547Sarrstatic void	em_init(void *);
20090963Sarrstatic void	em_init_locked(struct adapter *);
20192547Sarrstatic void	em_stop(void *);
20225537Sdfrstatic void	em_media_status(struct ifnet *, struct ifmediareq *);
20325537Sdfrstatic int	em_media_change(struct ifnet *);
20425537Sdfrstatic void	em_identify_hardware(struct adapter *);
20525537Sdfrstatic int	em_allocate_pci_resources(struct adapter *);
20690963Sarrstatic int	em_allocate_intr(struct adapter *);
20725537Sdfrstatic void	em_free_intr(struct adapter *);
20890963Sarrstatic void	em_free_pci_resources(struct adapter *);
20990963Sarrstatic void	em_local_timer(void *);
21025537Sdfrstatic int	em_hardware_init(struct adapter *);
21192547Sarrstatic void	em_setup_interface(device_t, struct adapter *);
21292547Sarrstatic int	em_setup_transmit_structures(struct adapter *);
21390963Sarrstatic void	em_initialize_transmit_unit(struct adapter *);
21490963Sarrstatic int	em_setup_receive_structures(struct adapter *);
21590963Sarrstatic void	em_initialize_receive_unit(struct adapter *);
21690980Sarrstatic void	em_enable_intr(struct adapter *);
21790963Sarrstatic void	em_disable_intr(struct adapter *);
21890980Sarrstatic void	em_free_transmit_structures(struct adapter *);
21925537Sdfrstatic void	em_free_receive_structures(struct adapter *);
22025537Sdfrstatic void	em_update_stats_counters(struct adapter *);
22125537Sdfrstatic void	em_txeof(struct adapter *);
22225537Sdfrstatic int	em_allocate_receive_structures(struct adapter *);
22325537Sdfrstatic int	em_allocate_transmit_structures(struct adapter *);
22492547Sarrstatic int	em_rxeof(struct adapter *, int);
22525537Sdfr#ifndef __NO_STRICT_ALIGNMENT
22692547Sarrstatic int	em_fixup_rx(struct adapter *);
22792547Sarr#endif
22892547Sarrstatic void	em_receive_checksum(struct adapter *, struct em_rx_desc *,
22992547Sarr		    struct mbuf *);
23092547Sarrstatic void	em_transmit_checksum_setup(struct adapter *, struct mbuf *,
23192547Sarr		    uint32_t *, uint32_t *);
23225537Sdfrstatic void	em_set_promisc(struct adapter *);
23325537Sdfrstatic void	em_disable_promisc(struct adapter *);
23425537Sdfrstatic void	em_set_multi(struct adapter *);
235132117Sphkstatic void	em_print_hw_stats(struct adapter *);
23625537Sdfrstatic void	em_update_link_status(struct adapter *);
237132117Sphkstatic int	em_get_buf(int i, struct adapter *, struct mbuf *);
23890963Sarrstatic void	em_enable_vlans(struct adapter *);
239159957Sjhbstatic void	em_disable_vlans(struct adapter *);
240132117Sphkstatic int	em_encap(struct adapter *, struct mbuf **);
241132199Sphkstatic void	em_smartspeed(struct adapter *);
242132117Sphkstatic int	em_82547_fifo_workaround(struct adapter *, int);
243159957Sjhbstatic void	em_82547_update_fifo_head(struct adapter *, int);
244159957Sjhbstatic int	em_82547_tx_fifo_reset(struct adapter *);
245159957Sjhbstatic void	em_82547_move_tail(void *arg);
246159957Sjhbstatic void	em_82547_move_tail_locked(struct adapter *);
24725537Sdfrstatic int	em_dma_malloc(struct adapter *, bus_size_t,
24825537Sdfr		struct em_dma_alloc *, int);
24925537Sdfrstatic void	em_dma_free(struct adapter *, struct em_dma_alloc *);
25025537Sdfrstatic void	em_print_debug_info(struct adapter *);
25125537Sdfrstatic int 	em_is_valid_ether_addr(uint8_t *);
25290963Sarrstatic int	em_sysctl_stats(SYSCTL_HANDLER_ARGS);
25392547Sarrstatic int	em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
25490980Sarrstatic uint32_t	em_fill_descriptors (bus_addr_t address, uint32_t length,
25525537Sdfr		    PDESC_ARRAY desc_array);
25625537Sdfrstatic int	em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
25725537Sdfrstatic void	em_add_int_delay_sysctl(struct adapter *, const char *,
25825537Sdfr		const char *, struct em_int_delay_info *, int, int);
25925537Sdfr
26090963Sarr/*
26192547Sarr * Fast interrupt handler and legacy ithread/polling modes are
26290980Sarr * mutually exclusive.
26325537Sdfr */
26425537Sdfr#ifdef DEVICE_POLLING
26542435Sdfrstatic poll_handler_t em_poll;
26642435Sdfrstatic void	em_intr(void *);
26742435Sdfr#else
26890963Sarrstatic void	em_intr_fast(void *);
26992547Sarrstatic void	em_add_int_process_limit(struct adapter *, const char *,
27090963Sarr		const char *, int *, int);
27142435Sdfrstatic void	em_handle_rxtx(void *context, int pending);
27242435Sdfrstatic void	em_handle_link(void *context, int pending);
273157818Sjhb#endif
274157818Sjhb
275157818Sjhb/*********************************************************************
276157818Sjhb *  FreeBSD Device Interface Entry Points
277157818Sjhb *********************************************************************/
278157818Sjhb
279157818Sjhbstatic device_method_t em_methods[] = {
28025537Sdfr	/* Device interface */
28125537Sdfr	DEVMETHOD(device_probe, em_probe),
28225537Sdfr	DEVMETHOD(device_attach, em_attach),
28325537Sdfr	DEVMETHOD(device_detach, em_detach),
28483366Sjulian	DEVMETHOD(device_shutdown, em_shutdown),
28525537Sdfr	DEVMETHOD(device_suspend, em_suspend),
28690963Sarr	DEVMETHOD(device_resume, em_resume),
28790963Sarr	{0, 0}
28825537Sdfr};
28998835Sarr
29082749Sdillonstatic driver_t em_driver = {
29192547Sarr	"em", em_methods, sizeof(struct adapter),
292107849Salfred};
29390963Sarr
29490963Sarrstatic devclass_t em_devclass;
29590963SarrDRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
29690963SarrMODULE_DEPEND(em, pci, 1, 1, 1);
29790963SarrMODULE_DEPEND(em, ether, 1, 1, 1);
29890963Sarr
29990963Sarr/*********************************************************************
300107849Salfred *  Tunable default values.
30190963Sarr *********************************************************************/
30290963Sarr
30390963Sarr#define E1000_TICKS_TO_USECS(ticks)	((1024 * (ticks) + 500) / 1000)
30490963Sarr#define E1000_USECS_TO_TICKS(usecs)	((1000 * (usecs) + 512) / 1024)
30590963Sarr
30690963Sarrstatic int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
30782749Sdillonstatic int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
30890963Sarrstatic int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
30982749Sdillonstatic int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
31092547Sarrstatic int em_rxd = EM_DEFAULT_RXD;
31190963Sarrstatic int em_txd = EM_DEFAULT_TXD;
31225537Sdfrstatic int em_smart_pwr_down = FALSE;
31325537Sdfr
31425537SdfrTUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
31583366SjulianTUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
31625537SdfrTUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
31790963SarrTUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
31890963SarrTUNABLE_INT("hw.em.rxd", &em_rxd);
31925537SdfrTUNABLE_INT("hw.em.txd", &em_txd);
32090963SarrTUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
32125537Sdfr#ifndef DEVICE_POLLING
32292547Sarrstatic int em_rx_process_limit = 100;
323107849SalfredTUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit);
32490963Sarr#endif
32590963Sarr
32690963Sarr/*********************************************************************
32790963Sarr *  Device identification routine
32890963Sarr *
32990963Sarr *  em_probe determines if the driver should be loaded on
33090963Sarr *  adapter based on PCI vendor/device id of the adapter.
33190963Sarr *
33290963Sarr *  return BUS_PROBE_DEFAULT on success, positive on failure
33392547Sarr *********************************************************************/
33490963Sarr
33525537Sdfrstatic int
33625537Sdfrem_probe(device_t dev)
33742435Sdfr{
33891067Sarr	char		adapter_name[60];
33991067Sarr	uint16_t	pci_vendor_id = 0;
34091067Sarr	uint16_t	pci_device_id = 0;
34191067Sarr	uint16_t	pci_subvendor_id = 0;
34242435Sdfr	uint16_t	pci_subdevice_id = 0;
34342435Sdfr	em_vendor_info_t *ent;
34425537Sdfr
34583366Sjulian	INIT_DEBUGOUT("em_probe: begin");
34625537Sdfr
34790963Sarr	pci_vendor_id = pci_get_vendor(dev);
34892547Sarr	if (pci_vendor_id != EM_VENDOR_ID)
34990963Sarr		return (ENXIO);
35092547Sarr
35190963Sarr	pci_device_id = pci_get_device(dev);
35292547Sarr	pci_subvendor_id = pci_get_subvendor(dev);
35325537Sdfr	pci_subdevice_id = pci_get_subdevice(dev);
35492547Sarr
355107849Salfred	ent = em_vendor_info_array;
35690963Sarr	while (ent->vendor_id != 0) {
35792547Sarr		if ((pci_vendor_id == ent->vendor_id) &&
35898835Sarr		    (pci_device_id == ent->device_id) &&
35990963Sarr
36092547Sarr		    ((pci_subvendor_id == ent->subvendor_id) ||
36192547Sarr		    (ent->subvendor_id == PCI_ANY_ID)) &&
36292547Sarr
36392547Sarr		    ((pci_subdevice_id == ent->subdevice_id) ||
36492547Sarr		    (ent->subdevice_id == PCI_ANY_ID))) {
365107849Salfred			sprintf(adapter_name, "%s %s",
36625537Sdfr				em_strings[ent->index],
36790963Sarr				em_driver_version);
36890963Sarr			device_set_desc_copy(dev, adapter_name);
36990963Sarr			return (BUS_PROBE_DEFAULT);
37090963Sarr		}
37198835Sarr		ent++;
37290963Sarr	}
37398835Sarr
37498835Sarr	return (ENXIO);
37590963Sarr}
37690963Sarr
37790963Sarr/*********************************************************************
37892547Sarr *  Device initialization routine
37998835Sarr *
38025537Sdfr *  The attach entry point is called when the driver is being loaded.
38192547Sarr *  This routine identifies the type of hardware, allocates all resources
38298835Sarr *  and initializes the hardware.
38392547Sarr *
38498835Sarr *  return 0 on success, positive on failure
38525537Sdfr *********************************************************************/
38690963Sarr
38790963Sarrstatic int
38890963Sarrem_attach(device_t dev)
38998835Sarr{
39092547Sarr	struct adapter	*adapter;
39192547Sarr	int		tsize, rsize;
39298835Sarr	int		error = 0;
39390963Sarr
39490980Sarr	INIT_DEBUGOUT("em_attach: begin");
39525537Sdfr
39625537Sdfr	adapter = device_get_softc(dev);
39725537Sdfr	adapter->dev = adapter->osdep.dev = dev;
39883366Sjulian	EM_LOCK_INIT(adapter, device_get_nameunit(dev));
39925537Sdfr
40090963Sarr	/* SYSCTL stuff */
40190963Sarr	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
40290963Sarr	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
40325537Sdfr	    OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
404107849Salfred	    em_sysctl_debug_info, "I", "Debug Information");
40598835Sarr
40625537Sdfr	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
40792547Sarr	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
40890963Sarr	    OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
40990963Sarr	    em_sysctl_stats, "I", "Statistics");
41090963Sarr
41190963Sarr	callout_init(&adapter->timer, CALLOUT_MPSAFE);
41292547Sarr	callout_init(&adapter->tx_fifo_timer, CALLOUT_MPSAFE);
41392547Sarr
41490980Sarr	/* Determine hardware revision */
41525537Sdfr	em_identify_hardware(adapter);
416140482Sps
417176252Sjhb	/* Set up some sysctls for the tunable interrupt delays */
418176252Sjhb	em_add_int_delay_sysctl(adapter, "rx_int_delay",
419140482Sps	    "receive interrupt delay in usecs", &adapter->rx_int_delay,
420140482Sps	    E1000_REG_OFFSET(&adapter->hw, RDTR), em_rx_int_delay_dflt);
421174377Sjhb	em_add_int_delay_sysctl(adapter, "tx_int_delay",
422140482Sps	    "transmit interrupt delay in usecs", &adapter->tx_int_delay,
423140482Sps	    E1000_REG_OFFSET(&adapter->hw, TIDV), em_tx_int_delay_dflt);
424140482Sps	if (adapter->hw.mac_type >= em_82540) {
425140482Sps		em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
426140482Sps		    "receive interrupt delay limit in usecs",
427140482Sps		    &adapter->rx_abs_int_delay,
428140482Sps		    E1000_REG_OFFSET(&adapter->hw, RADV),
429140482Sps		    em_rx_abs_int_delay_dflt);
430140482Sps		em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
431140482Sps		    "transmit interrupt delay limit in usecs",
432140482Sps		    &adapter->tx_abs_int_delay,
433140482Sps		    E1000_REG_OFFSET(&adapter->hw, TADV),
434140482Sps		    em_tx_abs_int_delay_dflt);
435140482Sps	}
436140482Sps
437140482Sps#ifndef DEVICE_POLLING
438140482Sps	/* Sysctls for limiting the amount of work done in the taskqueue */
439140482Sps	em_add_int_process_limit(adapter, "rx_processing_limit",
440140482Sps	    "max number of rx packets to process", &adapter->rx_process_limit,
441140482Sps	    em_rx_process_limit);
442140482Sps#endif
443140482Sps
444140482Sps	/*
445140482Sps	 * Validate number of transmit and receive descriptors. It
446140482Sps	 * must not exceed hardware maximum, and must be multiple
447140482Sps	 * of EM_DBA_ALIGN.
448140482Sps	 */
449140482Sps	if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 ||
450140482Sps	    (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) ||
451140482Sps	    (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) ||
452140482Sps	    (em_txd < EM_MIN_TXD)) {
453140482Sps		device_printf(dev, "Using %d TX descriptors instead of %d!\n",
454140482Sps		    EM_DEFAULT_TXD, em_txd);
455140482Sps		adapter->num_tx_desc = EM_DEFAULT_TXD;
456140482Sps	} else
457140482Sps		adapter->num_tx_desc = em_txd;
458140482Sps	if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 ||
459140482Sps	    (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) ||
460140482Sps	    (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) ||
461142067Sps	    (em_rxd < EM_MIN_RXD)) {
462142067Sps		device_printf(dev, "Using %d RX descriptors instead of %d!\n",
463142067Sps		    EM_DEFAULT_RXD, em_rxd);
464142067Sps		adapter->num_rx_desc = EM_DEFAULT_RXD;
465140482Sps	} else
466140482Sps		adapter->num_rx_desc = em_rxd;
467140482Sps
468140482Sps	adapter->hw.autoneg = DO_AUTO_NEG;
469140482Sps	adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
470140482Sps	adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
471140482Sps	adapter->hw.tbi_compatibility_en = TRUE;
472140482Sps	adapter->rx_buffer_len = EM_RXBUFFER_2048;
473140482Sps
474140482Sps	adapter->hw.phy_init_script = 1;
475140482Sps	adapter->hw.phy_reset_disable = FALSE;
476140482Sps
477140482Sps#ifndef EM_MASTER_SLAVE
478140482Sps	adapter->hw.master_slave = em_ms_hw_default;
479140482Sps#else
480140482Sps	adapter->hw.master_slave = EM_MASTER_SLAVE;
481140482Sps#endif
482140482Sps	/*
483140482Sps	 * Set the max frame size assuming standard ethernet
484140482Sps	 * sized frames.
485140482Sps	 */
486140482Sps	adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
487140482Sps
488140482Sps	adapter->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
489140482Sps
490140482Sps	/*
491140482Sps	 * This controls when hardware reports transmit completion
492140482Sps	 * status.
493140482Sps	 */
494140482Sps	adapter->hw.report_tx_early = 1;
495	if (em_allocate_pci_resources(adapter)) {
496		device_printf(dev, "Allocation of PCI resources failed\n");
497		error = ENXIO;
498		goto err_pci;
499	}
500
501	/* Initialize eeprom parameters */
502	em_init_eeprom_params(&adapter->hw);
503
504	tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc),
505	    EM_DBA_ALIGN);
506
507	/* Allocate Transmit Descriptor ring */
508	if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) {
509		device_printf(dev, "Unable to allocate tx_desc memory\n");
510		error = ENOMEM;
511		goto err_tx_desc;
512	}
513	adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr;
514
515	rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc),
516	    EM_DBA_ALIGN);
517
518	/* Allocate Receive Descriptor ring */
519	if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) {
520		device_printf(dev, "Unable to allocate rx_desc memory\n");
521		error = ENOMEM;
522		goto err_rx_desc;
523	}
524	adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr;
525
526	/* Initialize the hardware */
527	if (em_hardware_init(adapter)) {
528		device_printf(dev, "Unable to initialize the hardware\n");
529		error = EIO;
530		goto err_hw_init;
531	}
532
533	/* Copy the permanent MAC address out of the EEPROM */
534	if (em_read_mac_addr(&adapter->hw) < 0) {
535		device_printf(dev, "EEPROM read error while reading MAC"
536		    " address\n");
537		error = EIO;
538		goto err_hw_init;
539	}
540
541	if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) {
542		device_printf(dev, "Invalid MAC address\n");
543		error = EIO;
544		goto err_hw_init;
545	}
546
547	/* Setup OS specific network interface */
548	em_setup_interface(dev, adapter);
549
550	em_allocate_intr(adapter);
551
552	/* Initialize statistics */
553	em_clear_hw_cntrs(&adapter->hw);
554	em_update_stats_counters(adapter);
555	adapter->hw.get_link_status = 1;
556	em_update_link_status(adapter);
557
558	/* Indicate SOL/IDER usage */
559	if (em_check_phy_reset_block(&adapter->hw))
560		device_printf(dev,
561		    "PHY reset is blocked due to SOL/IDER session.\n");
562
563	/* Identify 82544 on PCIX */
564	em_get_bus_info(&adapter->hw);
565	if(adapter->hw.bus_type == em_bus_type_pcix && adapter->hw.mac_type == em_82544)
566		adapter->pcix_82544 = TRUE;
567	else
568		adapter->pcix_82544 = FALSE;
569
570	INIT_DEBUGOUT("em_attach: end");
571
572	return (0);
573
574err_hw_init:
575	em_dma_free(adapter, &adapter->rxdma);
576err_rx_desc:
577	em_dma_free(adapter, &adapter->txdma);
578err_tx_desc:
579err_pci:
580	em_free_intr(adapter);
581	em_free_pci_resources(adapter);
582	EM_LOCK_DESTROY(adapter);
583
584	return (error);
585}
586
587/*********************************************************************
588 *  Device removal routine
589 *
590 *  The detach entry point is called when the driver is being removed.
591 *  This routine stops the adapter and deallocates all the resources
592 *  that were allocated for driver operation.
593 *
594 *  return 0 on success, positive on failure
595 *********************************************************************/
596
597static int
598em_detach(device_t dev)
599{
600	struct adapter	*adapter = device_get_softc(dev);
601	struct ifnet	*ifp = adapter->ifp;
602
603	INIT_DEBUGOUT("em_detach: begin");
604
605#ifdef DEVICE_POLLING
606	if (ifp->if_capenable & IFCAP_POLLING)
607		ether_poll_deregister(ifp);
608#endif
609
610	em_free_intr(adapter);
611	EM_LOCK(adapter);
612	adapter->in_detach = 1;
613	em_stop(adapter);
614	em_phy_hw_reset(&adapter->hw);
615	EM_UNLOCK(adapter);
616	ether_ifdetach(adapter->ifp);
617
618	em_free_pci_resources(adapter);
619	bus_generic_detach(dev);
620	if_free(ifp);
621
622	/* Free Transmit Descriptor ring */
623	if (adapter->tx_desc_base) {
624		em_dma_free(adapter, &adapter->txdma);
625		adapter->tx_desc_base = NULL;
626	}
627
628	/* Free Receive Descriptor ring */
629	if (adapter->rx_desc_base) {
630		em_dma_free(adapter, &adapter->rxdma);
631		adapter->rx_desc_base = NULL;
632	}
633
634	EM_LOCK_DESTROY(adapter);
635
636	return (0);
637}
638
639/*********************************************************************
640 *
641 *  Shutdown entry point
642 *
643 **********************************************************************/
644
645static int
646em_shutdown(device_t dev)
647{
648	struct adapter *adapter = device_get_softc(dev);
649	EM_LOCK(adapter);
650	em_stop(adapter);
651	EM_UNLOCK(adapter);
652	return (0);
653}
654
655/*
656 * Suspend/resume device methods.
657 */
658static int
659em_suspend(device_t dev)
660{
661	struct adapter *adapter = device_get_softc(dev);
662
663	EM_LOCK(adapter);
664	em_stop(adapter);
665	EM_UNLOCK(adapter);
666
667	return bus_generic_suspend(dev);
668}
669
670static int
671em_resume(device_t dev)
672{
673	struct adapter *adapter = device_get_softc(dev);
674	struct ifnet *ifp = adapter->ifp;
675
676	EM_LOCK(adapter);
677	em_init_locked(adapter);
678	if ((ifp->if_flags & IFF_UP) &&
679	    (ifp->if_drv_flags & IFF_DRV_RUNNING))
680		em_start_locked(ifp);
681	EM_UNLOCK(adapter);
682
683	return bus_generic_resume(dev);
684}
685
686
687/*********************************************************************
688 *  Transmit entry point
689 *
690 *  em_start is called by the stack to initiate a transmit.
691 *  The driver will remain in this routine as long as there are
692 *  packets to transmit and transmit resources are available.
693 *  In case resources are not available stack is notified and
694 *  the packet is requeued.
695 **********************************************************************/
696
697static void
698em_start_locked(struct ifnet *ifp)
699{
700	struct adapter	*adapter = ifp->if_softc;
701	struct mbuf	*m_head;
702
703	EM_LOCK_ASSERT(adapter);
704
705	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
706	    IFF_DRV_RUNNING)
707		return;
708	if (!adapter->link_active)
709		return;
710
711	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
712
713		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
714		if (m_head == NULL)
715			break;
716		/*
717		 * em_encap() can modify our pointer, and or make it NULL on
718		 * failure.  In that event, we can't requeue.
719		 */
720		if (em_encap(adapter, &m_head)) {
721			if (m_head == NULL)
722				break;
723			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
724			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
725			break;
726		}
727
728		/* Send a copy of the frame to the BPF listener */
729		BPF_MTAP(ifp, m_head);
730
731		/* Set timeout in case hardware has problems transmitting. */
732		ifp->if_timer = EM_TX_TIMEOUT;
733	}
734}
735
736static void
737em_start(struct ifnet *ifp)
738{
739	struct adapter *adapter = ifp->if_softc;
740
741	EM_LOCK(adapter);
742	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
743		em_start_locked(ifp);
744	EM_UNLOCK(adapter);
745}
746
747/*********************************************************************
748 *  Ioctl entry point
749 *
750 *  em_ioctl is called when the user wants to configure the
751 *  interface.
752 *
753 *  return 0 on success, positive on failure
754 **********************************************************************/
755
756static int
757em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
758{
759	struct adapter	*adapter = ifp->if_softc;
760	struct ifreq *ifr = (struct ifreq *)data;
761	struct ifaddr *ifa = (struct ifaddr *)data;
762	int error = 0;
763
764	if (adapter->in_detach)
765		return (error);
766
767	switch (command) {
768	case SIOCSIFADDR:
769	case SIOCGIFADDR:
770		if (ifa->ifa_addr->sa_family == AF_INET) {
771			/*
772			 * XXX
773			 * Since resetting hardware takes a very long time
774			 * and results in link renegotiation we only
775			 * initialize the hardware only when it is absolutely
776			 * required.
777			 */
778			ifp->if_flags |= IFF_UP;
779			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
780				EM_LOCK(adapter);
781				em_init_locked(adapter);
782				EM_UNLOCK(adapter);
783			}
784			arp_ifinit(ifp, ifa);
785		} else
786			error = ether_ioctl(ifp, command, data);
787		break;
788	case SIOCSIFMTU:
789	    {
790		int max_frame_size;
791		uint16_t eeprom_data = 0;
792
793		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
794
795		EM_LOCK(adapter);
796		switch (adapter->hw.mac_type) {
797		case em_82573:
798			/*
799			 * 82573 only supports jumbo frames
800			 * if ASPM is disabled.
801			 */
802			em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
803			    &eeprom_data);
804			if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
805				max_frame_size = ETHER_MAX_LEN;
806				break;
807			}
808			/* Allow Jumbo frames - fall thru */
809		case em_82571:
810		case em_82572:
811		case em_80003es2lan:	/* Limit Jumbo Frame size */
812			max_frame_size = 9234;
813			break;
814		case em_ich8lan:
815			/* ICH8 does not support jumbo frames */
816			max_frame_size = ETHER_MAX_LEN;
817			break;
818		default:
819			max_frame_size = MAX_JUMBO_FRAME_SIZE;
820		}
821		if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
822		    ETHER_CRC_LEN) {
823			EM_UNLOCK(adapter);
824			error = EINVAL;
825			break;
826		}
827
828		ifp->if_mtu = ifr->ifr_mtu;
829		adapter->hw.max_frame_size =
830		ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
831		em_init_locked(adapter);
832		EM_UNLOCK(adapter);
833		break;
834	    }
835	case SIOCSIFFLAGS:
836		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
837		EM_LOCK(adapter);
838		if (ifp->if_flags & IFF_UP) {
839			if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) {
840				if ((ifp->if_flags ^ adapter->if_flags) &
841				    IFF_PROMISC) {
842					em_disable_promisc(adapter);
843					em_set_promisc(adapter);
844				}
845			} else
846				em_init_locked(adapter);
847		} else {
848			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
849				em_stop(adapter);
850			}
851		}
852		adapter->if_flags = ifp->if_flags;
853		EM_UNLOCK(adapter);
854		break;
855	case SIOCADDMULTI:
856	case SIOCDELMULTI:
857		IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
858		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
859			EM_LOCK(adapter);
860			em_disable_intr(adapter);
861			em_set_multi(adapter);
862			if (adapter->hw.mac_type == em_82542_rev2_0) {
863				em_initialize_receive_unit(adapter);
864			}
865#ifdef DEVICE_POLLING
866			if (!(ifp->if_capenable & IFCAP_POLLING))
867#endif
868				em_enable_intr(adapter);
869			EM_UNLOCK(adapter);
870		}
871		break;
872	case SIOCSIFMEDIA:
873	case SIOCGIFMEDIA:
874		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
875		error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
876		break;
877	case SIOCSIFCAP:
878	    {
879		int mask, reinit;
880
881		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
882		reinit = 0;
883		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
884#ifdef DEVICE_POLLING
885		if (mask & IFCAP_POLLING) {
886			if (ifr->ifr_reqcap & IFCAP_POLLING) {
887				error = ether_poll_register(em_poll, ifp);
888				if (error)
889					return (error);
890				EM_LOCK(adapter);
891				em_disable_intr(adapter);
892				ifp->if_capenable |= IFCAP_POLLING;
893				EM_UNLOCK(adapter);
894			} else {
895				error = ether_poll_deregister(ifp);
896				/* Enable interrupt even in error case */
897				EM_LOCK(adapter);
898				em_enable_intr(adapter);
899				ifp->if_capenable &= ~IFCAP_POLLING;
900				EM_UNLOCK(adapter);
901			}
902		}
903#endif
904		if (mask & IFCAP_HWCSUM) {
905			ifp->if_capenable ^= IFCAP_HWCSUM;
906			reinit = 1;
907		}
908		if (mask & IFCAP_VLAN_HWTAGGING) {
909			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
910			reinit = 1;
911		}
912		if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING))
913			em_init(adapter);
914		VLAN_CAPABILITIES(ifp);
915		break;
916	    }
917	default:
918		error = ether_ioctl(ifp, command, data);
919		break;
920	}
921
922	return (error);
923}
924
925/*********************************************************************
926 *  Watchdog entry point
927 *
928 *  This routine is called whenever hardware quits transmitting.
929 *
930 **********************************************************************/
931
932static void
933em_watchdog(struct ifnet *ifp)
934{
935	struct adapter *adapter = ifp->if_softc;
936
937	EM_LOCK(adapter);
938	/* If we are in this routine because of pause frames, then
939	 * don't reset the hardware.
940	 */
941	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
942		ifp->if_timer = EM_TX_TIMEOUT;
943		EM_UNLOCK(adapter);
944		return;
945	}
946
947	if (em_check_for_link(&adapter->hw) == 0)
948		device_printf(adapter->dev, "watchdog timeout -- resetting\n");
949
950	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
951	adapter->watchdog_events++;
952
953	em_init_locked(adapter);
954	EM_UNLOCK(adapter);
955}
956
957/*********************************************************************
958 *  Init entry point
959 *
960 *  This routine is used in two ways. It is used by the stack as
961 *  init entry point in network interface structure. It is also used
962 *  by the driver as a hw/sw initialization routine to get to a
963 *  consistent state.
964 *
965 *  return 0 on success, positive on failure
966 **********************************************************************/
967
968static void
969em_init_locked(struct adapter *adapter)
970{
971	struct ifnet	*ifp = adapter->ifp;
972	device_t	dev = adapter->dev;
973	uint32_t	pba;
974
975	INIT_DEBUGOUT("em_init: begin");
976
977	EM_LOCK_ASSERT(adapter);
978
979	em_stop(adapter);
980
981	/*
982	 * Packet Buffer Allocation (PBA)
983	 * Writing PBA sets the receive portion of the buffer
984	 * the remainder is used for the transmit buffer.
985	 *
986	 * Devices before the 82547 had a Packet Buffer of 64K.
987	 *   Default allocation: PBA=48K for Rx, leaving 16K for Tx.
988	 * After the 82547 the buffer was reduced to 40K.
989	 *   Default allocation: PBA=30K for Rx, leaving 10K for Tx.
990	 *   Note: default does not leave enough room for Jumbo Frame >10k.
991	 */
992	switch (adapter->hw.mac_type) {
993	case em_82547:
994	case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
995		if (adapter->hw.max_frame_size > EM_RXBUFFER_8192)
996			pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
997		else
998			pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
999		adapter->tx_fifo_head = 0;
1000		adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1001		adapter->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1002		break;
1003	case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */
1004	case em_82571: /* 82571: Total Packet Buffer is 48K */
1005	case em_82572: /* 82572: Total Packet Buffer is 48K */
1006			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1007		break;
1008	case em_82573: /* 82573: Total Packet Buffer is 32K */
1009		/* Jumbo frames not supported */
1010			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1011		break;
1012	case em_ich8lan:
1013		pba = E1000_PBA_8K;
1014		break;
1015	default:
1016		/* Devices before 82547 had a Packet Buffer of 64K.   */
1017		if(adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1018			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1019		else
1020			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1021	}
1022
1023	INIT_DEBUGOUT1("em_init: pba=%dK",pba);
1024	E1000_WRITE_REG(&adapter->hw, PBA, pba);
1025
1026	/* Get the latest mac address, User can use a LAA */
1027	bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac_addr, ETHER_ADDR_LEN);
1028
1029	/* Initialize the hardware */
1030	if (em_hardware_init(adapter)) {
1031		device_printf(dev, "Unable to initialize the hardware\n");
1032		return;
1033	}
1034	em_update_link_status(adapter);
1035
1036	if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1037		em_enable_vlans(adapter);
1038
1039	/* Prepare transmit descriptors and buffers */
1040	if (em_setup_transmit_structures(adapter)) {
1041		device_printf(dev, "Could not setup transmit structures\n");
1042		em_stop(adapter);
1043		return;
1044	}
1045	em_initialize_transmit_unit(adapter);
1046
1047	/* Setup Multicast table */
1048	em_set_multi(adapter);
1049
1050	/* Prepare receive descriptors and buffers */
1051	if (em_setup_receive_structures(adapter)) {
1052		device_printf(dev, "Could not setup receive structures\n");
1053		em_stop(adapter);
1054		return;
1055	}
1056	em_initialize_receive_unit(adapter);
1057
1058	/* Don't lose promiscuous settings */
1059	em_set_promisc(adapter);
1060
1061	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1062	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1063
1064	if (adapter->hw.mac_type >= em_82543) {
1065		if (ifp->if_capenable & IFCAP_TXCSUM)
1066			ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1067		else
1068			ifp->if_hwassist = 0;
1069	}
1070
1071	callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1072	em_clear_hw_cntrs(&adapter->hw);
1073#ifdef DEVICE_POLLING
1074	/*
1075	 * Only enable interrupts if we are not polling, make sure
1076	 * they are off otherwise.
1077	 */
1078	if (ifp->if_capenable & IFCAP_POLLING)
1079		em_disable_intr(adapter);
1080	else
1081#endif /* DEVICE_POLLING */
1082		em_enable_intr(adapter);
1083
1084	/* Don't reset the phy next time init gets called */
1085	adapter->hw.phy_reset_disable = TRUE;
1086}
1087
1088static void
1089em_init(void *arg)
1090{
1091	struct adapter *adapter = arg;
1092
1093	EM_LOCK(adapter);
1094	em_init_locked(adapter);
1095	EM_UNLOCK(adapter);
1096}
1097
1098
1099#ifdef DEVICE_POLLING
1100/*********************************************************************
1101 *
1102 *  Legacy polling routine
1103 *
1104 *********************************************************************/
1105static void
1106em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1107{
1108	struct adapter *adapter = ifp->if_softc;
1109	uint32_t reg_icr;
1110
1111	EM_LOCK(adapter);
1112	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1113		EM_UNLOCK(adapter);
1114		return;
1115	}
1116
1117	if (cmd == POLL_AND_CHECK_STATUS) {
1118		reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1119		if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1120			callout_stop(&adapter->timer);
1121			adapter->hw.get_link_status = 1;
1122			em_check_for_link(&adapter->hw);
1123			em_update_link_status(adapter);
1124			callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1125		}
1126	}
1127	em_rxeof(adapter, count);
1128	em_txeof(adapter);
1129
1130	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1131		em_start_locked(ifp);
1132	EM_UNLOCK(adapter);
1133}
1134
1135/*********************************************************************
1136 *
1137 *  Legacy Interrupt Service routine
1138 *
1139 *********************************************************************/
1140static void
1141em_intr(void *arg)
1142{
1143	struct adapter	*adapter = arg;
1144	struct ifnet	*ifp;
1145	uint32_t	reg_icr;
1146
1147	EM_LOCK(adapter);
1148
1149	ifp = adapter->ifp;
1150
1151	if (ifp->if_capenable & IFCAP_POLLING) {
1152		EM_UNLOCK(adapter);
1153		return;
1154	}
1155
1156	for (;;) {
1157		reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1158		if (adapter->hw.mac_type >= em_82571 &&
1159		    (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1160			break;
1161		else if (reg_icr == 0)
1162			break;
1163
1164		/*
1165		 * XXX: some laptops trigger several spurious interrupts
1166		 * on em(4) when in the resume cycle. The ICR register
1167		 * reports all-ones value in this case. Processing such
1168		 * interrupts would lead to a freeze. I don't know why.
1169		 */
1170		if (reg_icr == 0xffffffff)
1171			break;
1172
1173		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1174			em_rxeof(adapter, -1);
1175			em_txeof(adapter);
1176		}
1177
1178		/* Link status change */
1179		if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1180			callout_stop(&adapter->timer);
1181			adapter->hw.get_link_status = 1;
1182			em_check_for_link(&adapter->hw);
1183			em_update_link_status(adapter);
1184			callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1185		}
1186
1187		if (reg_icr & E1000_ICR_RXO)
1188			adapter->rx_overruns++;
1189	}
1190
1191	if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1192	    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1193		em_start_locked(ifp);
1194
1195	EM_UNLOCK(adapter);
1196}
1197
1198#else  /* if not DEVICE_POLLING, then fast interrupt routines only */
1199
1200static void
1201em_handle_link(void *context, int pending)
1202{
1203	struct adapter	*adapter = context;
1204	struct ifnet *ifp;
1205
1206	ifp = adapter->ifp;
1207
1208	EM_LOCK(adapter);
1209
1210	callout_stop(&adapter->timer);
1211	adapter->hw.get_link_status = 1;
1212	em_check_for_link(&adapter->hw);
1213	em_update_link_status(adapter);
1214	callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1215	EM_UNLOCK(adapter);
1216}
1217
1218static void
1219em_handle_rxtx(void *context, int pending)
1220{
1221	struct adapter	*adapter = context;
1222	struct ifnet	*ifp;
1223
1224	NET_LOCK_GIANT();
1225	ifp = adapter->ifp;
1226
1227	/*
1228	 * TODO:
1229	 * It should be possible to run the tx clean loop without the lock.
1230	 */
1231	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1232		if (em_rxeof(adapter, adapter->rx_process_limit) != 0)
1233			taskqueue_enqueue(adapter->tq, &adapter->rxtx_task);
1234		EM_LOCK(adapter);
1235		em_txeof(adapter);
1236
1237		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1238			em_start_locked(ifp);
1239		EM_UNLOCK(adapter);
1240	}
1241
1242	em_enable_intr(adapter);
1243	NET_UNLOCK_GIANT();
1244}
1245
1246/*********************************************************************
1247 *
1248 *  Fast Interrupt Service routine
1249 *
1250 *********************************************************************/
1251static void
1252em_intr_fast(void *arg)
1253{
1254	struct adapter	*adapter = arg;
1255	struct ifnet	*ifp;
1256	uint32_t	reg_icr;
1257
1258	ifp = adapter->ifp;
1259
1260	reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1261
1262	/* Hot eject?  */
1263	if (reg_icr == 0xffffffff)
1264		return;
1265
1266	/* Definitely not our interrupt.  */
1267	if (reg_icr == 0x0)
1268		return;
1269
1270	/*
1271	 * Starting with the 82571 chip, bit 31 should be used to
1272	 * determine whether the interrupt belongs to us.
1273	 */
1274	if (adapter->hw.mac_type >= em_82571 &&
1275	    (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1276		return;
1277
1278	/*
1279	 * Mask interrupts until the taskqueue is finished running.  This is
1280	 * cheap, just assume that it is needed.  This also works around the
1281	 * MSI message reordering errata on certain systems.
1282	 */
1283	em_disable_intr(adapter);
1284	taskqueue_enqueue(adapter->tq, &adapter->rxtx_task);
1285
1286	/* Link status change */
1287	if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1288		taskqueue_enqueue(taskqueue_fast, &adapter->link_task);
1289
1290	if (reg_icr & E1000_ICR_RXO)
1291		adapter->rx_overruns++;
1292}
1293#endif /* ! DEVICE_POLLING */
1294
1295/*********************************************************************
1296 *
1297 *  Media Ioctl callback
1298 *
1299 *  This routine is called whenever the user queries the status of
1300 *  the interface using ifconfig.
1301 *
1302 **********************************************************************/
1303static void
1304em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1305{
1306	struct adapter *adapter = ifp->if_softc;
1307
1308	INIT_DEBUGOUT("em_media_status: begin");
1309
1310	em_check_for_link(&adapter->hw);
1311	em_update_link_status(adapter);
1312
1313	ifmr->ifm_status = IFM_AVALID;
1314	ifmr->ifm_active = IFM_ETHER;
1315
1316	if (!adapter->link_active)
1317		return;
1318
1319	ifmr->ifm_status |= IFM_ACTIVE;
1320
1321	if (adapter->hw.media_type == em_media_type_fiber) {
1322		ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1323	} else {
1324		switch (adapter->link_speed) {
1325		case 10:
1326			ifmr->ifm_active |= IFM_10_T;
1327			break;
1328		case 100:
1329			ifmr->ifm_active |= IFM_100_TX;
1330			break;
1331		case 1000:
1332			ifmr->ifm_active |= IFM_1000_T;
1333			break;
1334		}
1335		if (adapter->link_duplex == FULL_DUPLEX)
1336			ifmr->ifm_active |= IFM_FDX;
1337		else
1338			ifmr->ifm_active |= IFM_HDX;
1339	}
1340}
1341
1342/*********************************************************************
1343 *
1344 *  Media Ioctl callback
1345 *
1346 *  This routine is called when the user changes speed/duplex using
1347 *  media/mediopt option with ifconfig.
1348 *
1349 **********************************************************************/
1350static int
1351em_media_change(struct ifnet *ifp)
1352{
1353	struct adapter *adapter = ifp->if_softc;
1354	struct ifmedia  *ifm = &adapter->media;
1355
1356	INIT_DEBUGOUT("em_media_change: begin");
1357
1358	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1359		return (EINVAL);
1360
1361	switch (IFM_SUBTYPE(ifm->ifm_media)) {
1362	case IFM_AUTO:
1363		adapter->hw.autoneg = DO_AUTO_NEG;
1364		adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1365		break;
1366	case IFM_1000_SX:
1367	case IFM_1000_T:
1368		adapter->hw.autoneg = DO_AUTO_NEG;
1369		adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1370		break;
1371	case IFM_100_TX:
1372		adapter->hw.autoneg = FALSE;
1373		adapter->hw.autoneg_advertised = 0;
1374		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1375			adapter->hw.forced_speed_duplex = em_100_full;
1376		else
1377			adapter->hw.forced_speed_duplex = em_100_half;
1378		break;
1379	case IFM_10_T:
1380		adapter->hw.autoneg = FALSE;
1381		adapter->hw.autoneg_advertised = 0;
1382		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1383			adapter->hw.forced_speed_duplex = em_10_full;
1384		else
1385			adapter->hw.forced_speed_duplex = em_10_half;
1386		break;
1387	default:
1388		device_printf(adapter->dev, "Unsupported media type\n");
1389	}
1390
1391	/* As the speed/duplex settings my have changed we need to
1392	 * reset the PHY.
1393	 */
1394	adapter->hw.phy_reset_disable = FALSE;
1395
1396	em_init(adapter);
1397
1398	return (0);
1399}
1400
1401/*********************************************************************
1402 *
1403 *  This routine maps the mbufs to tx descriptors.
1404 *
1405 *  return 0 on success, positive on failure
1406 **********************************************************************/
1407static int
1408em_encap(struct adapter *adapter, struct mbuf **m_headp)
1409{
1410	struct ifnet		*ifp = adapter->ifp;
1411	bus_dma_segment_t	segs[EM_MAX_SCATTER];
1412	bus_dmamap_t		map;
1413	struct em_buffer	*tx_buffer, *tx_buffer_last;
1414	struct em_tx_desc	*current_tx_desc;
1415	struct mbuf		*m_head;
1416	struct m_tag		*mtag;
1417	uint32_t		txd_upper, txd_lower, txd_used, txd_saved;
1418	int			nsegs, i, j;
1419	int			error;
1420
1421	m_head = *m_headp;
1422	current_tx_desc = NULL;
1423	txd_used = txd_saved = 0;
1424
1425	/*
1426	 * Force a cleanup if number of TX descriptors
1427	 * available hits the threshold.
1428	 */
1429	if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1430		em_txeof(adapter);
1431		if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1432			adapter->no_tx_desc_avail1++;
1433			return (ENOBUFS);
1434		}
1435	}
1436
1437	/* Find out if we are in vlan mode. */
1438	mtag = VLAN_OUTPUT_TAG(ifp, m_head);
1439
1440	/*
1441	 * When operating in promiscuous mode, hardware encapsulation for
1442	 * packets is disabled.  This means we have to add the vlan
1443	 * encapsulation in the driver, since it will have come down from the
1444	 * VLAN layer with a tag instead of a VLAN header.
1445	 */
1446	if (mtag != NULL && adapter->em_insert_vlan_header) {
1447		struct ether_vlan_header *evl;
1448		struct ether_header eh;
1449
1450		m_head = m_pullup(m_head, sizeof(eh));
1451		if (m_head == NULL) {
1452			*m_headp = NULL;
1453			return (ENOBUFS);
1454		}
1455		eh = *mtod(m_head, struct ether_header *);
1456		M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT);
1457		if (m_head == NULL) {
1458			*m_headp = NULL;
1459			return (ENOBUFS);
1460		}
1461		m_head = m_pullup(m_head, sizeof(*evl));
1462		if (m_head == NULL) {
1463			*m_headp = NULL;
1464			return (ENOBUFS);
1465		}
1466		evl = mtod(m_head, struct ether_vlan_header *);
1467		bcopy(&eh, evl, sizeof(*evl));
1468		evl->evl_proto = evl->evl_encap_proto;
1469		evl->evl_encap_proto = htons(ETHERTYPE_VLAN);
1470		evl->evl_tag = htons(VLAN_TAG_VALUE(mtag));
1471		m_tag_delete(m_head, mtag);
1472		mtag = NULL;
1473		*m_headp = m_head;
1474	}
1475
1476	/*
1477	 * Map the packet for DMA.
1478	 */
1479	tx_buffer = &adapter->tx_buffer_area[adapter->next_avail_tx_desc];
1480	tx_buffer_last = tx_buffer;
1481	map = tx_buffer->map;
1482	error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, m_head, segs, &nsegs,
1483	    BUS_DMA_NOWAIT);
1484	if (error != 0) {
1485		adapter->no_tx_dma_setup++;
1486		return (error);
1487	}
1488	KASSERT(nsegs != 0, ("em_encap: empty packet"));
1489
1490	if (nsegs > adapter->num_tx_desc_avail) {
1491		adapter->no_tx_desc_avail2++;
1492		error = ENOBUFS;
1493		goto encap_fail;
1494	}
1495
1496	if (ifp->if_hwassist > 0)
1497		em_transmit_checksum_setup(adapter,  m_head, &txd_upper, &txd_lower);
1498	else
1499		txd_upper = txd_lower = 0;
1500
1501	i = adapter->next_avail_tx_desc;
1502	if (adapter->pcix_82544) {
1503		txd_saved = i;
1504		txd_used = 0;
1505	}
1506	for (j = 0; j < nsegs; j++) {
1507		/* If adapter is 82544 and on PCIX bus. */
1508		if(adapter->pcix_82544) {
1509			DESC_ARRAY	desc_array;
1510			uint32_t	array_elements, counter;
1511
1512			/*
1513			 * Check the Address and Length combination and
1514			 * split the data accordingly
1515			 */
1516			array_elements = em_fill_descriptors(segs[j].ds_addr,
1517			    segs[j].ds_len, &desc_array);
1518			for (counter = 0; counter < array_elements; counter++) {
1519				if (txd_used == adapter->num_tx_desc_avail) {
1520					adapter->next_avail_tx_desc = txd_saved;
1521					adapter->no_tx_desc_avail2++;
1522					error = ENOBUFS;
1523					goto encap_fail;
1524				}
1525				tx_buffer = &adapter->tx_buffer_area[i];
1526				current_tx_desc = &adapter->tx_desc_base[i];
1527				current_tx_desc->buffer_addr = htole64(
1528					desc_array.descriptor[counter].address);
1529				current_tx_desc->lower.data = htole32(
1530					(adapter->txd_cmd | txd_lower |
1531					(uint16_t)desc_array.descriptor[counter].length));
1532				current_tx_desc->upper.data = htole32((txd_upper));
1533				if (++i == adapter->num_tx_desc)
1534					i = 0;
1535
1536				tx_buffer->m_head = NULL;
1537				txd_used++;
1538			}
1539		} else {
1540			tx_buffer = &adapter->tx_buffer_area[i];
1541			current_tx_desc = &adapter->tx_desc_base[i];
1542
1543			current_tx_desc->buffer_addr = htole64(segs[j].ds_addr);
1544			current_tx_desc->lower.data = htole32(
1545				adapter->txd_cmd | txd_lower | segs[j].ds_len);
1546			current_tx_desc->upper.data = htole32(txd_upper);
1547
1548			if (++i == adapter->num_tx_desc)
1549				i = 0;
1550
1551			tx_buffer->m_head = NULL;
1552		}
1553	}
1554
1555	adapter->next_avail_tx_desc = i;
1556	if (adapter->pcix_82544)
1557		adapter->num_tx_desc_avail -= txd_used;
1558	else
1559		adapter->num_tx_desc_avail -= nsegs;
1560
1561	if (mtag != NULL) {
1562		/* Set the vlan id. */
1563		current_tx_desc->upper.fields.special =
1564		    htole16(VLAN_TAG_VALUE(mtag));
1565
1566		/* Tell hardware to add tag. */
1567		current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1568	}
1569
1570	tx_buffer->m_head = m_head;
1571	tx_buffer_last->map = tx_buffer->map;
1572	tx_buffer->map = map;
1573	bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1574
1575	/*
1576	 * Last Descriptor of Packet needs End Of Packet (EOP).
1577	 */
1578	current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP);
1579
1580	/*
1581	 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1582	 * that this frame is available to transmit.
1583	 */
1584	bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
1585	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1586	if (adapter->hw.mac_type == em_82547 && adapter->link_duplex == HALF_DUPLEX)
1587		em_82547_move_tail_locked(adapter);
1588	else {
1589		E1000_WRITE_REG(&adapter->hw, TDT, i);
1590		if (adapter->hw.mac_type == em_82547)
1591			em_82547_update_fifo_head(adapter, m_head->m_pkthdr.len);
1592	}
1593
1594	return (0);
1595
1596encap_fail:
1597	bus_dmamap_unload(adapter->txtag, map);
1598	return (error);
1599}
1600
1601/*********************************************************************
1602 *
1603 * 82547 workaround to avoid controller hang in half-duplex environment.
1604 * The workaround is to avoid queuing a large packet that would span
1605 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1606 * in this case. We do that only when FIFO is quiescent.
1607 *
1608 **********************************************************************/
1609static void
1610em_82547_move_tail_locked(struct adapter *adapter)
1611{
1612	uint16_t hw_tdt;
1613	uint16_t sw_tdt;
1614	struct em_tx_desc *tx_desc;
1615	uint16_t length = 0;
1616	boolean_t eop = 0;
1617
1618	EM_LOCK_ASSERT(adapter);
1619
1620	hw_tdt = E1000_READ_REG(&adapter->hw, TDT);
1621	sw_tdt = adapter->next_avail_tx_desc;
1622
1623	while (hw_tdt != sw_tdt) {
1624		tx_desc = &adapter->tx_desc_base[hw_tdt];
1625		length += tx_desc->lower.flags.length;
1626		eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1627		if(++hw_tdt == adapter->num_tx_desc)
1628			hw_tdt = 0;
1629
1630		if (eop) {
1631			if (em_82547_fifo_workaround(adapter, length)) {
1632				adapter->tx_fifo_wrk_cnt++;
1633				callout_reset(&adapter->tx_fifo_timer, 1,
1634					em_82547_move_tail, adapter);
1635				break;
1636			}
1637			E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt);
1638			em_82547_update_fifo_head(adapter, length);
1639			length = 0;
1640		}
1641	}
1642}
1643
1644static void
1645em_82547_move_tail(void *arg)
1646{
1647	struct adapter *adapter = arg;
1648
1649	EM_LOCK(adapter);
1650	em_82547_move_tail_locked(adapter);
1651	EM_UNLOCK(adapter);
1652}
1653
1654static int
1655em_82547_fifo_workaround(struct adapter *adapter, int len)
1656{
1657	int fifo_space, fifo_pkt_len;
1658
1659	fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1660
1661	if (adapter->link_duplex == HALF_DUPLEX) {
1662		fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1663
1664		if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1665			if (em_82547_tx_fifo_reset(adapter))
1666				return (0);
1667			else
1668				return (1);
1669		}
1670	}
1671
1672	return (0);
1673}
1674
1675static void
1676em_82547_update_fifo_head(struct adapter *adapter, int len)
1677{
1678	int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1679
1680	/* tx_fifo_head is always 16 byte aligned */
1681	adapter->tx_fifo_head += fifo_pkt_len;
1682	if (adapter->tx_fifo_head >= adapter->tx_fifo_size) {
1683		adapter->tx_fifo_head -= adapter->tx_fifo_size;
1684	}
1685}
1686
1687
1688static int
1689em_82547_tx_fifo_reset(struct adapter *adapter)
1690{
1691	uint32_t tctl;
1692
1693	if ((E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH)) &&
1694	    (E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH)) &&
1695	    (E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS))&&
1696	    (E1000_READ_REG(&adapter->hw, TDFPC) == 0)) {
1697
1698		/* Disable TX unit */
1699		tctl = E1000_READ_REG(&adapter->hw, TCTL);
1700		E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
1701
1702		/* Reset FIFO pointers */
1703		E1000_WRITE_REG(&adapter->hw, TDFT,  adapter->tx_head_addr);
1704		E1000_WRITE_REG(&adapter->hw, TDFH,  adapter->tx_head_addr);
1705		E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
1706		E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
1707
1708		/* Re-enable TX unit */
1709		E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1710		E1000_WRITE_FLUSH(&adapter->hw);
1711
1712		adapter->tx_fifo_head = 0;
1713		adapter->tx_fifo_reset_cnt++;
1714
1715		return (TRUE);
1716	}
1717	else {
1718		return (FALSE);
1719	}
1720}
1721
1722static void
1723em_set_promisc(struct adapter *adapter)
1724{
1725	struct ifnet	*ifp = adapter->ifp;
1726	uint32_t	reg_rctl;
1727
1728	reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1729
1730	if (ifp->if_flags & IFF_PROMISC) {
1731		reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1732		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1733		/* Disable VLAN stripping in promiscous mode
1734		 * This enables bridging of vlan tagged frames to occur
1735		 * and also allows vlan tags to be seen in tcpdump
1736		 */
1737		if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1738			em_disable_vlans(adapter);
1739		adapter->em_insert_vlan_header = 1;
1740	} else if (ifp->if_flags & IFF_ALLMULTI) {
1741		reg_rctl |= E1000_RCTL_MPE;
1742		reg_rctl &= ~E1000_RCTL_UPE;
1743		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1744		adapter->em_insert_vlan_header = 0;
1745	} else
1746		adapter->em_insert_vlan_header = 0;
1747}
1748
1749static void
1750em_disable_promisc(struct adapter *adapter)
1751{
1752	struct ifnet	*ifp = adapter->ifp;
1753	uint32_t	reg_rctl;
1754
1755	reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1756
1757	reg_rctl &=  (~E1000_RCTL_UPE);
1758	reg_rctl &=  (~E1000_RCTL_MPE);
1759	E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1760
1761	if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1762		em_enable_vlans(adapter);
1763	adapter->em_insert_vlan_header = 0;
1764}
1765
1766
1767/*********************************************************************
1768 *  Multicast Update
1769 *
1770 *  This routine is called whenever multicast address list is updated.
1771 *
1772 **********************************************************************/
1773
1774static void
1775em_set_multi(struct adapter *adapter)
1776{
1777	struct ifnet	*ifp = adapter->ifp;
1778	struct ifmultiaddr *ifma;
1779	uint32_t reg_rctl = 0;
1780	uint8_t  mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1781	int mcnt = 0;
1782
1783	IOCTL_DEBUGOUT("em_set_multi: begin");
1784
1785	if (adapter->hw.mac_type == em_82542_rev2_0) {
1786		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1787		if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1788			em_pci_clear_mwi(&adapter->hw);
1789		reg_rctl |= E1000_RCTL_RST;
1790		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1791		msec_delay(5);
1792	}
1793
1794	IF_ADDR_LOCK(ifp);
1795	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1796		if (ifma->ifma_addr->sa_family != AF_LINK)
1797			continue;
1798
1799		if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1800			break;
1801
1802		bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1803		    &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1804		mcnt++;
1805	}
1806	IF_ADDR_UNLOCK(ifp);
1807
1808	if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1809		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1810		reg_rctl |= E1000_RCTL_MPE;
1811		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1812	} else
1813		em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1);
1814
1815	if (adapter->hw.mac_type == em_82542_rev2_0) {
1816		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1817		reg_rctl &= ~E1000_RCTL_RST;
1818		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1819		msec_delay(5);
1820		if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1821			em_pci_set_mwi(&adapter->hw);
1822	}
1823}
1824
1825
1826/*********************************************************************
1827 *  Timer routine
1828 *
1829 *  This routine checks for link status and updates statistics.
1830 *
1831 **********************************************************************/
1832
1833static void
1834em_local_timer(void *arg)
1835{
1836	struct adapter	*adapter = arg;
1837	struct ifnet	*ifp = adapter->ifp;
1838
1839	EM_LOCK(adapter);
1840
1841	em_check_for_link(&adapter->hw);
1842	em_update_link_status(adapter);
1843	em_update_stats_counters(adapter);
1844	if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING)
1845		em_print_hw_stats(adapter);
1846	em_smartspeed(adapter);
1847
1848	callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1849
1850	EM_UNLOCK(adapter);
1851}
1852
1853static void
1854em_update_link_status(struct adapter *adapter)
1855{
1856	struct ifnet *ifp = adapter->ifp;
1857	device_t dev = adapter->dev;
1858
1859	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1860		if (adapter->link_active == 0) {
1861			em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed,
1862			    &adapter->link_duplex);
1863			/* Check if we may set SPEED_MODE bit on PCI-E */
1864			if ((adapter->link_speed == SPEED_1000) &&
1865			    ((adapter->hw.mac_type == em_82571) ||
1866			    (adapter->hw.mac_type == em_82572))) {
1867				int tarc0;
1868
1869				tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
1870				tarc0 |= SPEED_MODE_BIT;
1871				E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
1872			}
1873			if (bootverbose)
1874				device_printf(dev, "Link is up %d Mbps %s\n",
1875				    adapter->link_speed,
1876				    ((adapter->link_duplex == FULL_DUPLEX) ?
1877				    "Full Duplex" : "Half Duplex"));
1878			adapter->link_active = 1;
1879			adapter->smartspeed = 0;
1880			ifp->if_baudrate = adapter->link_speed * 1000000;
1881			if_link_state_change(ifp, LINK_STATE_UP);
1882		}
1883	} else {
1884		if (adapter->link_active == 1) {
1885			ifp->if_baudrate = adapter->link_speed = 0;
1886			adapter->link_duplex = 0;
1887			if (bootverbose)
1888				device_printf(dev, "Link is Down\n");
1889			adapter->link_active = 0;
1890			if_link_state_change(ifp, LINK_STATE_DOWN);
1891		}
1892	}
1893}
1894
1895/*********************************************************************
1896 *
1897 *  This routine disables all traffic on the adapter by issuing a
1898 *  global reset on the MAC and deallocates TX/RX buffers.
1899 *
1900 **********************************************************************/
1901
1902static void
1903em_stop(void *arg)
1904{
1905	struct adapter	*adapter = arg;
1906	struct ifnet	*ifp = adapter->ifp;
1907
1908	EM_LOCK_ASSERT(adapter);
1909
1910	INIT_DEBUGOUT("em_stop: begin");
1911
1912	em_disable_intr(adapter);
1913	em_reset_hw(&adapter->hw);
1914	callout_stop(&adapter->timer);
1915	callout_stop(&adapter->tx_fifo_timer);
1916	em_free_transmit_structures(adapter);
1917	em_free_receive_structures(adapter);
1918
1919	/* Tell the stack that the interface is no longer active */
1920	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1921}
1922
1923
1924/*********************************************************************
1925 *
1926 *  Determine hardware revision.
1927 *
1928 **********************************************************************/
1929static void
1930em_identify_hardware(struct adapter *adapter)
1931{
1932	device_t dev = adapter->dev;
1933
1934	/* Make sure our PCI config space has the necessary stuff set */
1935	adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1936	if ((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 &&
1937	    (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN)) {
1938		device_printf(dev, "Memory Access and/or Bus Master bits "
1939		    "were not set!\n");
1940		adapter->hw.pci_cmd_word |=
1941		(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
1942		pci_write_config(dev, PCIR_COMMAND, adapter->hw.pci_cmd_word, 2);
1943	}
1944
1945	/* Save off the information about this board */
1946	adapter->hw.vendor_id = pci_get_vendor(dev);
1947	adapter->hw.device_id = pci_get_device(dev);
1948	adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1949	adapter->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
1950	adapter->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
1951
1952	/* Identify the MAC */
1953	if (em_set_mac_type(&adapter->hw))
1954		device_printf(dev, "Unknown MAC Type\n");
1955
1956	if(adapter->hw.mac_type == em_82541 || adapter->hw.mac_type == em_82541_rev_2 ||
1957	   adapter->hw.mac_type == em_82547 || adapter->hw.mac_type == em_82547_rev_2)
1958		adapter->hw.phy_init_script = TRUE;
1959}
1960
1961static int
1962em_allocate_pci_resources(struct adapter *adapter)
1963{
1964	device_t	dev = adapter->dev;
1965	int		val, rid;
1966
1967	rid = PCIR_BAR(0);
1968	adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1969	    &rid, RF_ACTIVE);
1970	if (adapter->res_memory == NULL) {
1971		device_printf(dev, "Unable to allocate bus resource: memory\n");
1972		return (ENXIO);
1973	}
1974	adapter->osdep.mem_bus_space_tag =
1975	rman_get_bustag(adapter->res_memory);
1976	adapter->osdep.mem_bus_space_handle = rman_get_bushandle(adapter->res_memory);
1977	adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
1978
1979	if (adapter->hw.mac_type > em_82543) {
1980		/* Figure our where our IO BAR is ? */
1981		for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1982			val = pci_read_config(dev, rid, 4);
1983			if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) {
1984				adapter->io_rid = rid;
1985				break;
1986			}
1987			rid += 4;
1988			/* check for 64bit BAR */
1989			if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT)
1990				rid += 4;
1991		}
1992		if (rid >= PCIR_CIS) {
1993			device_printf(dev, "Unable to locate IO BAR\n");
1994			return (ENXIO);
1995		}
1996		adapter->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1997		    &adapter->io_rid, RF_ACTIVE);
1998		if (adapter->res_ioport == NULL) {
1999			device_printf(dev, "Unable to allocate bus resource: "
2000			    "ioport\n");
2001			return (ENXIO);
2002		}
2003		adapter->hw.io_base = 0;
2004		adapter->osdep.io_bus_space_tag = rman_get_bustag(adapter->res_ioport);
2005		adapter->osdep.io_bus_space_handle =
2006		    rman_get_bushandle(adapter->res_ioport);
2007	}
2008
2009	/* For ICH8 we need to find the flash memory. */
2010	if (adapter->hw.mac_type == em_ich8lan) {
2011		rid = EM_FLASH;
2012
2013		adapter->flash_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2014		    &rid, RF_ACTIVE);
2015		adapter->osdep.flash_bus_space_tag = rman_get_bustag(adapter->flash_mem);
2016		adapter->osdep.flash_bus_space_handle =
2017		    rman_get_bushandle(adapter->flash_mem);
2018	}
2019
2020	rid = 0x0;
2021	adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2022	    RF_SHAREABLE | RF_ACTIVE);
2023	if (adapter->res_interrupt == NULL) {
2024		device_printf(dev, "Unable to allocate bus resource: "
2025		    "interrupt\n");
2026		return (ENXIO);
2027	}
2028
2029	adapter->hw.back = &adapter->osdep;
2030
2031	return (0);
2032}
2033
2034int
2035em_allocate_intr(struct adapter *adapter)
2036{
2037	device_t dev = adapter->dev;
2038	int error;
2039
2040	/* Manually turn off all interrupts */
2041	E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
2042
2043#ifdef DEVICE_POLLING
2044	if (adapter->int_handler_tag == NULL && (error = bus_setup_intr(dev,
2045	    adapter->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, adapter,
2046	    &adapter->int_handler_tag)) != 0) {
2047		device_printf(dev, "Failed to register interrupt handler");
2048		return (error);
2049	}
2050#else
2051	/*
2052	 * Try allocating a fast interrupt and the associated deferred
2053	 * processing contexts.
2054	 */
2055	TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter);
2056	TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter);
2057	adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT,
2058	    taskqueue_thread_enqueue, &adapter->tq);
2059	taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq",
2060	    device_get_nameunit(adapter->dev));
2061	if ((error = bus_setup_intr(dev, adapter->res_interrupt,
2062	    INTR_TYPE_NET | INTR_FAST, em_intr_fast, adapter,
2063	    &adapter->int_handler_tag)) != 0) {
2064		device_printf(dev, "Failed to register fast interrupt "
2065			    "handler: %d\n", error);
2066		taskqueue_free(adapter->tq);
2067		adapter->tq = NULL;
2068		return (error);
2069	}
2070#endif
2071
2072	em_enable_intr(adapter);
2073	return (0);
2074}
2075
2076static void
2077em_free_intr(struct adapter *adapter)
2078{
2079	device_t dev = adapter->dev;
2080
2081	if (adapter->res_interrupt != NULL) {
2082		bus_teardown_intr(dev, adapter->res_interrupt, adapter->int_handler_tag);
2083		adapter->int_handler_tag = NULL;
2084	}
2085	if (adapter->tq != NULL) {
2086		taskqueue_drain(adapter->tq, &adapter->rxtx_task);
2087		taskqueue_drain(taskqueue_fast, &adapter->link_task);
2088		taskqueue_free(adapter->tq);
2089		adapter->tq = NULL;
2090	}
2091}
2092
2093static void
2094em_free_pci_resources(struct adapter *adapter)
2095{
2096	device_t dev = adapter->dev;
2097
2098	if (adapter->res_interrupt != NULL)
2099		bus_release_resource(dev, SYS_RES_IRQ, 0, adapter->res_interrupt);
2100
2101	if (adapter->res_memory != NULL)
2102		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2103		    adapter->res_memory);
2104
2105	if (adapter->flash_mem != NULL)
2106		bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH,
2107		    adapter->flash_mem);
2108
2109	if (adapter->res_ioport != NULL)
2110		bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid,
2111		    adapter->res_ioport);
2112}
2113
2114/*********************************************************************
2115 *
2116 *  Initialize the hardware to a configuration as specified by the
2117 *  adapter structure. The controller is reset, the EEPROM is
2118 *  verified, the MAC address is set, then the shared initialization
2119 *  routines are called.
2120 *
2121 **********************************************************************/
2122static int
2123em_hardware_init(struct adapter *adapter)
2124{
2125	device_t dev = adapter->dev;
2126	uint16_t rx_buffer_size;
2127
2128	INIT_DEBUGOUT("em_hardware_init: begin");
2129	/* Issue a global reset */
2130	em_reset_hw(&adapter->hw);
2131
2132	/* When hardware is reset, fifo_head is also reset */
2133	adapter->tx_fifo_head = 0;
2134
2135	/* Make sure we have a good EEPROM before we read from it */
2136	if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2137		device_printf(dev, "The EEPROM Checksum Is Not Valid\n");
2138		return (EIO);
2139	}
2140
2141	if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
2142		device_printf(dev, "EEPROM read error while reading part "
2143		    "number\n");
2144		return (EIO);
2145	}
2146
2147	/* Set up smart power down as default off on newer adapters. */
2148	if (!em_smart_pwr_down &&
2149	    (adapter->hw.mac_type == em_82571 || adapter->hw.mac_type == em_82572)) {
2150		uint16_t phy_tmp = 0;
2151
2152		/* Speed up time to link by disabling smart power down. */
2153		em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2154		phy_tmp &= ~IGP02E1000_PM_SPD;
2155		em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2156	}
2157
2158	/*
2159	 * These parameters control the automatic generation (Tx) and
2160	 * response (Rx) to Ethernet PAUSE frames.
2161	 * - High water mark should allow for at least two frames to be
2162	 *   received after sending an XOFF.
2163	 * - Low water mark works best when it is very near the high water mark.
2164	 *   This allows the receiver to restart by sending XON when it has
2165	 *   drained a bit. Here we use an arbitary value of 1500 which will
2166	 *   restart after one full frame is pulled from the buffer. There
2167	 *   could be several smaller frames in the buffer and if so they will
2168	 *   not trigger the XON until their total number reduces the buffer
2169	 *   by 1500.
2170	 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2171	 */
2172	rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10 );
2173
2174	adapter->hw.fc_high_water = rx_buffer_size -
2175	    roundup2(adapter->hw.max_frame_size, 1024);
2176	adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500;
2177	if (adapter->hw.mac_type == em_80003es2lan)
2178		adapter->hw.fc_pause_time = 0xFFFF;
2179	else
2180		adapter->hw.fc_pause_time = 0x1000;
2181	adapter->hw.fc_send_xon = TRUE;
2182	adapter->hw.fc = em_fc_full;
2183
2184	if (em_init_hw(&adapter->hw) < 0) {
2185		device_printf(dev, "Hardware Initialization Failed");
2186		return (EIO);
2187	}
2188
2189	em_check_for_link(&adapter->hw);
2190
2191	return (0);
2192}
2193
2194/*********************************************************************
2195 *
2196 *  Setup networking device structure and register an interface.
2197 *
2198 **********************************************************************/
2199static void
2200em_setup_interface(device_t dev, struct adapter *adapter)
2201{
2202	struct ifnet   *ifp;
2203	INIT_DEBUGOUT("em_setup_interface: begin");
2204
2205	ifp = adapter->ifp = if_alloc(IFT_ETHER);
2206	if (ifp == NULL)
2207		panic("%s: can not if_alloc()", device_get_nameunit(dev));
2208	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2209	ifp->if_mtu = ETHERMTU;
2210	ifp->if_init =  em_init;
2211	ifp->if_softc = adapter;
2212	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2213	ifp->if_ioctl = em_ioctl;
2214	ifp->if_start = em_start;
2215	ifp->if_watchdog = em_watchdog;
2216	IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1);
2217	ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1;
2218	IFQ_SET_READY(&ifp->if_snd);
2219
2220	ether_ifattach(ifp, adapter->hw.mac_addr);
2221
2222	ifp->if_capabilities = ifp->if_capenable = 0;
2223
2224	if (adapter->hw.mac_type >= em_82543) {
2225		ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
2226		ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
2227	}
2228
2229	/*
2230	 * Tell the upper layer(s) we support long frames.
2231	 */
2232	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2233	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2234	ifp->if_capenable |= IFCAP_VLAN_MTU;
2235
2236#ifdef DEVICE_POLLING
2237	ifp->if_capabilities |= IFCAP_POLLING;
2238#endif
2239
2240	/*
2241	 * Specify the media types supported by this adapter and register
2242	 * callbacks to update media and link information
2243	 */
2244	ifmedia_init(&adapter->media, IFM_IMASK, em_media_change, em_media_status);
2245	if (adapter->hw.media_type == em_media_type_fiber) {
2246		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2247			    0, NULL);
2248		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX,
2249			    0, NULL);
2250	} else {
2251		ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2252		ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2253			    0, NULL);
2254		ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2255			    0, NULL);
2256		ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2257			    0, NULL);
2258		if (adapter->hw.phy_type != em_phy_ife) {
2259			ifmedia_add(&adapter->media,
2260				IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2261			ifmedia_add(&adapter->media,
2262				IFM_ETHER | IFM_1000_T, 0, NULL);
2263		}
2264	}
2265	ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2266	ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2267}
2268
2269
2270/*********************************************************************
2271 *
2272 *  Workaround for SmartSpeed on 82541 and 82547 controllers
2273 *
2274 **********************************************************************/
2275static void
2276em_smartspeed(struct adapter *adapter)
2277{
2278	uint16_t phy_tmp;
2279
2280	if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) ||
2281	    adapter->hw.autoneg == 0 ||
2282	    (adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2283		return;
2284
2285	if (adapter->smartspeed == 0) {
2286		/* If Master/Slave config fault is asserted twice,
2287		 * we assume back-to-back */
2288		em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2289		if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2290			return;
2291		em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2292		if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2293			em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2294			if(phy_tmp & CR_1000T_MS_ENABLE) {
2295				phy_tmp &= ~CR_1000T_MS_ENABLE;
2296				em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
2297				    phy_tmp);
2298				adapter->smartspeed++;
2299				if(adapter->hw.autoneg &&
2300				   !em_phy_setup_autoneg(&adapter->hw) &&
2301				   !em_read_phy_reg(&adapter->hw, PHY_CTRL,
2302				    &phy_tmp)) {
2303					phy_tmp |= (MII_CR_AUTO_NEG_EN |
2304						    MII_CR_RESTART_AUTO_NEG);
2305					em_write_phy_reg(&adapter->hw, PHY_CTRL,
2306					    phy_tmp);
2307				}
2308			}
2309		}
2310		return;
2311	} else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2312		/* If still no link, perhaps using 2/3 pair cable */
2313		em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2314		phy_tmp |= CR_1000T_MS_ENABLE;
2315		em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2316		if(adapter->hw.autoneg &&
2317		   !em_phy_setup_autoneg(&adapter->hw) &&
2318		   !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) {
2319			phy_tmp |= (MII_CR_AUTO_NEG_EN |
2320				    MII_CR_RESTART_AUTO_NEG);
2321			em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp);
2322		}
2323	}
2324	/* Restart process after EM_SMARTSPEED_MAX iterations */
2325	if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2326		adapter->smartspeed = 0;
2327}
2328
2329
2330/*
2331 * Manage DMA'able memory.
2332 */
2333static void
2334em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2335{
2336	if (error)
2337		return;
2338	*(bus_addr_t *) arg = segs[0].ds_addr;
2339}
2340
2341static int
2342em_dma_malloc(struct adapter *adapter, bus_size_t size, struct em_dma_alloc *dma,
2343	int mapflags)
2344{
2345	int error;
2346
2347	error = bus_dma_tag_create(NULL,		/* parent */
2348				EM_DBA_ALIGN, 0,	/* alignment, bounds */
2349				BUS_SPACE_MAXADDR,	/* lowaddr */
2350				BUS_SPACE_MAXADDR,	/* highaddr */
2351				NULL, NULL,		/* filter, filterarg */
2352				size,			/* maxsize */
2353				1,			/* nsegments */
2354				size,			/* maxsegsize */
2355				0,			/* flags */
2356				NULL,			/* lockfunc */
2357				NULL,			/* lockarg */
2358				&dma->dma_tag);
2359	if (error) {
2360		device_printf(adapter->dev, "%s: bus_dma_tag_create failed: %d\n",
2361		    __func__, error);
2362		goto fail_0;
2363	}
2364
2365	error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
2366	    BUS_DMA_NOWAIT, &dma->dma_map);
2367	if (error) {
2368		device_printf(adapter->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
2369		    __func__, (uintmax_t)size, error);
2370		goto fail_2;
2371	}
2372
2373	dma->dma_paddr = 0;
2374	error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
2375	    size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT);
2376	if (error || dma->dma_paddr == 0) {
2377		device_printf(adapter->dev, "%s: bus_dmamap_load failed: %d\n",
2378		    __func__, error);
2379		goto fail_3;
2380	}
2381
2382	return (0);
2383
2384fail_3:
2385	bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2386fail_2:
2387	bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2388	bus_dma_tag_destroy(dma->dma_tag);
2389fail_0:
2390	dma->dma_map = NULL;
2391	dma->dma_tag = NULL;
2392
2393	return (error);
2394}
2395
2396static void
2397em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2398{
2399	if (dma->dma_tag == NULL)
2400		return;
2401	if (dma->dma_map != NULL) {
2402		bus_dmamap_sync(dma->dma_tag, dma->dma_map,
2403		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2404		bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2405		bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2406		dma->dma_map = NULL;
2407	}
2408	bus_dma_tag_destroy(dma->dma_tag);
2409	dma->dma_tag = NULL;
2410}
2411
2412
2413/*********************************************************************
2414 *
2415 *  Allocate memory for tx_buffer structures. The tx_buffer stores all
2416 *  the information needed to transmit a packet on the wire.
2417 *
2418 **********************************************************************/
2419static int
2420em_allocate_transmit_structures(struct adapter *adapter)
2421{
2422	adapter->tx_buffer_area =  malloc(sizeof(struct em_buffer) *
2423	    adapter->num_tx_desc, M_DEVBUF, M_NOWAIT);
2424	if (adapter->tx_buffer_area == NULL) {
2425		device_printf(adapter->dev, "Unable to allocate tx_buffer memory\n");
2426		return (ENOMEM);
2427	}
2428
2429	bzero(adapter->tx_buffer_area, sizeof(struct em_buffer) * adapter->num_tx_desc);
2430
2431	return (0);
2432}
2433
2434/*********************************************************************
2435 *
2436 *  Allocate and initialize transmit structures.
2437 *
2438 **********************************************************************/
2439static int
2440em_setup_transmit_structures(struct adapter *adapter)
2441{
2442	device_t dev = adapter->dev;
2443	struct em_buffer *tx_buffer;
2444	bus_size_t size;
2445	int error, i;
2446
2447	/*
2448	 * Setup DMA descriptor areas.
2449	 */
2450	size = roundup2(adapter->hw.max_frame_size, MCLBYTES);
2451	if ((error = bus_dma_tag_create(NULL,		/* parent */
2452				1, 0,			/* alignment, bounds */
2453				BUS_SPACE_MAXADDR,	/* lowaddr */
2454				BUS_SPACE_MAXADDR,	/* highaddr */
2455				NULL, NULL,		/* filter, filterarg */
2456				size,			/* maxsize */
2457				EM_MAX_SCATTER,		/* nsegments */
2458				size,			/* maxsegsize */
2459				0,			/* flags */
2460				NULL,		/* lockfunc */
2461				NULL,		/* lockarg */
2462				&adapter->txtag)) != 0) {
2463		device_printf(dev, "Unable to allocate TX DMA tag\n");
2464		goto fail;
2465	}
2466
2467	if ((error = em_allocate_transmit_structures(adapter)) != 0)
2468		goto fail;
2469
2470	bzero(adapter->tx_desc_base, (sizeof(struct em_tx_desc)) * adapter->num_tx_desc);
2471	tx_buffer = adapter->tx_buffer_area;
2472	for (i = 0; i < adapter->num_tx_desc; i++) {
2473		error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map);
2474		if (error != 0) {
2475			device_printf(dev, "Unable to create TX DMA map\n");
2476			goto fail;
2477		}
2478		tx_buffer++;
2479	}
2480
2481	adapter->next_avail_tx_desc = 0;
2482	adapter->oldest_used_tx_desc = 0;
2483
2484	/* Set number of descriptors available */
2485	adapter->num_tx_desc_avail = adapter->num_tx_desc;
2486
2487	/* Set checksum context */
2488	adapter->active_checksum_context = OFFLOAD_NONE;
2489	bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2490	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2491
2492	return (0);
2493
2494fail:
2495	em_free_transmit_structures(adapter);
2496	return (error);
2497}
2498
2499/*********************************************************************
2500 *
2501 *  Enable transmit unit.
2502 *
2503 **********************************************************************/
2504static void
2505em_initialize_transmit_unit(struct adapter *adapter)
2506{
2507	uint32_t	reg_tctl, reg_tarc;
2508	uint32_t	reg_tipg = 0;
2509	uint64_t	bus_addr;
2510
2511	 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2512	/* Setup the Base and Length of the Tx Descriptor Ring */
2513	bus_addr = adapter->txdma.dma_paddr;
2514	E1000_WRITE_REG(&adapter->hw, TDLEN,
2515	    adapter->num_tx_desc * sizeof(struct em_tx_desc));
2516	E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32));
2517	E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr);
2518
2519	/* Setup the HW Tx Head and Tail descriptor pointers */
2520	E1000_WRITE_REG(&adapter->hw, TDT, 0);
2521	E1000_WRITE_REG(&adapter->hw, TDH, 0);
2522
2523
2524	HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&adapter->hw, TDBAL),
2525	    E1000_READ_REG(&adapter->hw, TDLEN));
2526
2527	/* Set the default values for the Tx Inter Packet Gap timer */
2528	switch (adapter->hw.mac_type) {
2529	case em_82542_rev2_0:
2530	case em_82542_rev2_1:
2531		reg_tipg = DEFAULT_82542_TIPG_IPGT;
2532		reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2533		reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2534		break;
2535	case em_80003es2lan:
2536		reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2537		reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2538		    E1000_TIPG_IPGR2_SHIFT;
2539		break;
2540	default:
2541		if (adapter->hw.media_type == em_media_type_fiber)
2542			reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2543		else
2544			reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2545		reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2546		reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2547	}
2548
2549	E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
2550	E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);
2551	if(adapter->hw.mac_type >= em_82540)
2552		E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay.value);
2553
2554	/* Do adapter specific tweaks before we enable the transmitter. */
2555	if (adapter->hw.mac_type == em_82571 || adapter->hw.mac_type == em_82572) {
2556		reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
2557		reg_tarc |= (1 << 25);
2558		E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
2559		reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
2560		reg_tarc |= (1 << 25);
2561		reg_tarc &= ~(1 << 28);
2562		E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
2563	} else if (adapter->hw.mac_type == em_80003es2lan) {
2564		reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
2565		reg_tarc |= 1;
2566		if (adapter->hw.media_type == em_media_type_internal_serdes)
2567		    reg_tarc |= (1 << 20);
2568		E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
2569		reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
2570		reg_tarc |= 1;
2571		E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
2572	}
2573
2574	/* Program the Transmit Control Register */
2575	reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2576		   (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2577	if (adapter->hw.mac_type >= em_82571)
2578		reg_tctl |= E1000_TCTL_MULR;
2579	if (adapter->link_duplex == 1) {
2580		reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2581	} else {
2582		reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2583	}
2584	/* This write will effectively turn on the transmit unit. */
2585	E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
2586
2587	/* Setup Transmit Descriptor Settings for this adapter */
2588	adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
2589
2590	if (adapter->tx_int_delay.value > 0)
2591		adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2592}
2593
2594/*********************************************************************
2595 *
2596 *  Free all transmit related data structures.
2597 *
2598 **********************************************************************/
2599static void
2600em_free_transmit_structures(struct adapter *adapter)
2601{
2602	struct em_buffer *tx_buffer;
2603	int i;
2604
2605	INIT_DEBUGOUT("free_transmit_structures: begin");
2606
2607	if (adapter->tx_buffer_area != NULL) {
2608		tx_buffer = adapter->tx_buffer_area;
2609		for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
2610			if (tx_buffer->m_head != NULL) {
2611				bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2612				    BUS_DMASYNC_POSTWRITE);
2613				bus_dmamap_unload(adapter->txtag,
2614				    tx_buffer->map);
2615				m_freem(tx_buffer->m_head);
2616				tx_buffer->m_head = NULL;
2617			} else if (tx_buffer->map != NULL)
2618				bus_dmamap_unload(adapter->txtag,
2619				    tx_buffer->map);
2620			if (tx_buffer->map != NULL) {
2621				bus_dmamap_destroy(adapter->txtag,
2622				    tx_buffer->map);
2623				tx_buffer->map = NULL;
2624			}
2625		}
2626	}
2627	if (adapter->tx_buffer_area != NULL) {
2628		free(adapter->tx_buffer_area, M_DEVBUF);
2629		adapter->tx_buffer_area = NULL;
2630	}
2631	if (adapter->txtag != NULL) {
2632		bus_dma_tag_destroy(adapter->txtag);
2633		adapter->txtag = NULL;
2634	}
2635}
2636
2637/*********************************************************************
2638 *
2639 *  The offload context needs to be set when we transfer the first
2640 *  packet of a particular protocol (TCP/UDP). We change the
2641 *  context only if the protocol type changes.
2642 *
2643 **********************************************************************/
2644static void
2645em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp,
2646    uint32_t *txd_upper, uint32_t *txd_lower)
2647{
2648	struct em_context_desc *TXD;
2649	struct em_buffer *tx_buffer;
2650	int curr_txd;
2651
2652	if (mp->m_pkthdr.csum_flags) {
2653
2654		if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
2655			*txd_upper = E1000_TXD_POPTS_TXSM << 8;
2656			*txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2657			if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
2658				return;
2659			else
2660				adapter->active_checksum_context = OFFLOAD_TCP_IP;
2661
2662		} else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
2663			*txd_upper = E1000_TXD_POPTS_TXSM << 8;
2664			*txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2665			if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
2666				return;
2667			else
2668				adapter->active_checksum_context = OFFLOAD_UDP_IP;
2669		} else {
2670			*txd_upper = 0;
2671			*txd_lower = 0;
2672			return;
2673		}
2674	} else {
2675		*txd_upper = 0;
2676		*txd_lower = 0;
2677		return;
2678	}
2679
2680	/* If we reach this point, the checksum offload context
2681	 * needs to be reset.
2682	 */
2683	curr_txd = adapter->next_avail_tx_desc;
2684	tx_buffer = &adapter->tx_buffer_area[curr_txd];
2685	TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd];
2686
2687	TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2688	TXD->lower_setup.ip_fields.ipcso =
2689		ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2690	TXD->lower_setup.ip_fields.ipcse =
2691		htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2692
2693	TXD->upper_setup.tcp_fields.tucss =
2694		ETHER_HDR_LEN + sizeof(struct ip);
2695	TXD->upper_setup.tcp_fields.tucse = htole16(0);
2696
2697	if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
2698		TXD->upper_setup.tcp_fields.tucso =
2699			ETHER_HDR_LEN + sizeof(struct ip) +
2700			offsetof(struct tcphdr, th_sum);
2701	} else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
2702		TXD->upper_setup.tcp_fields.tucso =
2703			ETHER_HDR_LEN + sizeof(struct ip) +
2704			offsetof(struct udphdr, uh_sum);
2705	}
2706
2707	TXD->tcp_seg_setup.data = htole32(0);
2708	TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
2709
2710	tx_buffer->m_head = NULL;
2711
2712	if (++curr_txd == adapter->num_tx_desc)
2713		curr_txd = 0;
2714
2715	adapter->num_tx_desc_avail--;
2716	adapter->next_avail_tx_desc = curr_txd;
2717}
2718
2719/**********************************************************************
2720 *
2721 *  Examine each tx_buffer in the used queue. If the hardware is done
2722 *  processing the packet then free associated resources. The
2723 *  tx_buffer is put back on the free queue.
2724 *
2725 **********************************************************************/
2726static void
2727em_txeof(struct adapter *adapter)
2728{
2729	int i, num_avail;
2730	struct em_buffer *tx_buffer;
2731	struct em_tx_desc   *tx_desc;
2732	struct ifnet   *ifp = adapter->ifp;
2733
2734	EM_LOCK_ASSERT(adapter);
2735
2736	if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2737		return;
2738
2739	num_avail = adapter->num_tx_desc_avail;
2740	i = adapter->oldest_used_tx_desc;
2741
2742	tx_buffer = &adapter->tx_buffer_area[i];
2743	tx_desc = &adapter->tx_desc_base[i];
2744
2745	bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2746	    BUS_DMASYNC_POSTREAD);
2747	while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2748
2749		tx_desc->upper.data = 0;
2750		num_avail++;
2751
2752		if (tx_buffer->m_head) {
2753			ifp->if_opackets++;
2754			bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2755			    BUS_DMASYNC_POSTWRITE);
2756			bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2757
2758			m_freem(tx_buffer->m_head);
2759			tx_buffer->m_head = NULL;
2760		}
2761
2762		if (++i == adapter->num_tx_desc)
2763			i = 0;
2764
2765		tx_buffer = &adapter->tx_buffer_area[i];
2766		tx_desc = &adapter->tx_desc_base[i];
2767	}
2768	bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2769	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2770
2771	adapter->oldest_used_tx_desc = i;
2772
2773	/*
2774	 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack
2775	 * that it is OK to send packets.
2776	 * If there are no pending descriptors, clear the timeout. Otherwise,
2777	 * if some descriptors have been freed, restart the timeout.
2778	 */
2779	if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2780		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2781		if (num_avail == adapter->num_tx_desc)
2782			ifp->if_timer = 0;
2783		else if (num_avail != adapter->num_tx_desc_avail)
2784			ifp->if_timer = EM_TX_TIMEOUT;
2785	}
2786	adapter->num_tx_desc_avail = num_avail;
2787}
2788
2789/*********************************************************************
2790 *
2791 *  Get a buffer from system mbuf buffer pool.
2792 *
2793 **********************************************************************/
2794static int
2795em_get_buf(int i, struct adapter *adapter, struct mbuf *mp)
2796{
2797	struct ifnet		*ifp = adapter->ifp;
2798	bus_dma_segment_t	segs[1];
2799	struct em_buffer	*rx_buffer;
2800	int			error, nsegs;
2801
2802	if (mp == NULL) {
2803		mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2804		if (mp == NULL) {
2805			adapter->mbuf_cluster_failed++;
2806			return (ENOBUFS);
2807		}
2808		mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2809	} else {
2810		mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2811		mp->m_data = mp->m_ext.ext_buf;
2812		mp->m_next = NULL;
2813	}
2814
2815	if (ifp->if_mtu <= ETHERMTU)
2816		m_adj(mp, ETHER_ALIGN);
2817
2818	rx_buffer = &adapter->rx_buffer_area[i];
2819
2820	/*
2821	 * Using memory from the mbuf cluster pool, invoke the
2822	 * bus_dma machinery to arrange the memory mapping.
2823	 */
2824	error = bus_dmamap_load_mbuf_sg(adapter->rxtag, rx_buffer->map,
2825	    mp, segs, &nsegs, 0);
2826	if (error != 0) {
2827		m_free(mp);
2828		return (error);
2829	}
2830	/* If nsegs is wrong then the stack is corrupt. */
2831	KASSERT(nsegs == 1, ("Too many segments returned!"));
2832	rx_buffer->m_head = mp;
2833	adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr);
2834	bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD);
2835
2836	return (0);
2837}
2838
2839/*********************************************************************
2840 *
2841 *  Allocate memory for rx_buffer structures. Since we use one
2842 *  rx_buffer per received packet, the maximum number of rx_buffer's
2843 *  that we'll need is equal to the number of receive descriptors
2844 *  that we've allocated.
2845 *
2846 **********************************************************************/
2847static int
2848em_allocate_receive_structures(struct adapter *adapter)
2849{
2850	device_t dev = adapter->dev;
2851	struct em_buffer *rx_buffer;
2852	int i, error;
2853
2854	adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
2855	    M_DEVBUF, M_NOWAIT);
2856	if (adapter->rx_buffer_area == NULL) {
2857		device_printf(dev, "Unable to allocate rx_buffer memory\n");
2858		return (ENOMEM);
2859	}
2860
2861	bzero(adapter->rx_buffer_area, sizeof(struct em_buffer) * adapter->num_rx_desc);
2862
2863	error = bus_dma_tag_create(NULL,		/* parent */
2864				1, 0,			/* alignment, bounds */
2865				BUS_SPACE_MAXADDR,	/* lowaddr */
2866				BUS_SPACE_MAXADDR,	/* highaddr */
2867				NULL, NULL,		/* filter, filterarg */
2868				MCLBYTES,		/* maxsize */
2869				1,			/* nsegments */
2870				MCLBYTES,		/* maxsegsize */
2871				0,			/* flags */
2872				NULL,			/* lockfunc */
2873				NULL,			/* lockarg */
2874				&adapter->rxtag);
2875	if (error) {
2876		device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
2877		    __func__, error);
2878		goto fail;
2879	}
2880
2881	rx_buffer = adapter->rx_buffer_area;
2882	for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2883		error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT,
2884		    &rx_buffer->map);
2885		if (error) {
2886			device_printf(dev, "%s: bus_dmamap_create failed: %d\n",
2887			    __func__, error);
2888			goto fail;
2889		}
2890	}
2891
2892	for (i = 0; i < adapter->num_rx_desc; i++) {
2893		error = em_get_buf(i, adapter, NULL);
2894		if (error)
2895			goto fail;
2896	}
2897	bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2898	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2899
2900	return (0);
2901
2902fail:
2903	em_free_receive_structures(adapter);
2904	return (error);
2905}
2906
2907/*********************************************************************
2908 *
2909 *  Allocate and initialize receive structures.
2910 *
2911 **********************************************************************/
2912static int
2913em_setup_receive_structures(struct adapter *adapter)
2914{
2915	int error;
2916
2917	bzero(adapter->rx_desc_base, (sizeof(struct em_rx_desc)) * adapter->num_rx_desc);
2918
2919	if ((error = em_allocate_receive_structures(adapter)) != 0)
2920		return (error);
2921
2922	/* Setup our descriptor pointers */
2923	adapter->next_rx_desc_to_check = 0;
2924
2925	return (0);
2926}
2927
2928/*********************************************************************
2929 *
2930 *  Enable receive unit.
2931 *
2932 **********************************************************************/
2933static void
2934em_initialize_receive_unit(struct adapter *adapter)
2935{
2936	struct ifnet	*ifp = adapter->ifp;
2937	uint64_t	bus_addr;
2938	uint32_t	reg_rctl;
2939	uint32_t	reg_rxcsum;
2940
2941	INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2942
2943	/*
2944	 * Make sure receives are disabled while setting
2945	 * up the descriptor ring
2946	 */
2947	E1000_WRITE_REG(&adapter->hw, RCTL, 0);
2948
2949	/* Set the Receive Delay Timer Register */
2950	E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay.value | E1000_RDT_FPDB);
2951
2952	if(adapter->hw.mac_type >= em_82540) {
2953		E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay.value);
2954
2955		/*
2956		 * Set the interrupt throttling rate. Value is calculated
2957		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
2958		 */
2959#define MAX_INTS_PER_SEC	8000
2960#define DEFAULT_ITR	     1000000000/(MAX_INTS_PER_SEC * 256)
2961		E1000_WRITE_REG(&adapter->hw, ITR, DEFAULT_ITR);
2962	}
2963
2964	/* Setup the Base and Length of the Rx Descriptor Ring */
2965	bus_addr = adapter->rxdma.dma_paddr;
2966	E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
2967			sizeof(struct em_rx_desc));
2968	E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
2969	E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
2970
2971	/* Setup the HW Rx Head and Tail Descriptor Pointers */
2972	E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
2973	E1000_WRITE_REG(&adapter->hw, RDH, 0);
2974
2975	/* Setup the Receive Control Register */
2976	reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2977		   E1000_RCTL_RDMTS_HALF |
2978		   (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
2979
2980	if (adapter->hw.tbi_compatibility_on == TRUE)
2981		reg_rctl |= E1000_RCTL_SBP;
2982
2983
2984	switch (adapter->rx_buffer_len) {
2985	default:
2986	case EM_RXBUFFER_2048:
2987		reg_rctl |= E1000_RCTL_SZ_2048;
2988		break;
2989	case EM_RXBUFFER_4096:
2990		reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2991		break;
2992	case EM_RXBUFFER_8192:
2993		reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2994		break;
2995	case EM_RXBUFFER_16384:
2996		reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2997		break;
2998	}
2999
3000	if (ifp->if_mtu > ETHERMTU)
3001		reg_rctl |= E1000_RCTL_LPE;
3002
3003	/* Enable 82543 Receive Checksum Offload for TCP and UDP */
3004	if ((adapter->hw.mac_type >= em_82543) &&
3005	    (ifp->if_capenable & IFCAP_RXCSUM)) {
3006		reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
3007		reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3008		E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
3009	}
3010
3011	/* Enable Receives */
3012	E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
3013}
3014
3015/*********************************************************************
3016 *
3017 *  Free receive related data structures.
3018 *
3019 **********************************************************************/
3020static void
3021em_free_receive_structures(struct adapter *adapter)
3022{
3023	struct em_buffer *rx_buffer;
3024	int i;
3025
3026	INIT_DEBUGOUT("free_receive_structures: begin");
3027
3028	if (adapter->rx_buffer_area != NULL) {
3029		rx_buffer = adapter->rx_buffer_area;
3030		for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
3031			if (rx_buffer->m_head != NULL) {
3032				bus_dmamap_sync(adapter->rxtag, rx_buffer->map,
3033				    BUS_DMASYNC_POSTREAD);
3034				bus_dmamap_unload(adapter->rxtag,
3035				    rx_buffer->map);
3036				m_freem(rx_buffer->m_head);
3037				rx_buffer->m_head = NULL;
3038			} else if (rx_buffer->map != NULL)
3039				bus_dmamap_unload(adapter->rxtag,
3040				    rx_buffer->map);
3041			if (rx_buffer->map != NULL) {
3042				bus_dmamap_destroy(adapter->rxtag,
3043				    rx_buffer->map);
3044				rx_buffer->map = NULL;
3045			}
3046		}
3047	}
3048	if (adapter->rx_buffer_area != NULL) {
3049		free(adapter->rx_buffer_area, M_DEVBUF);
3050		adapter->rx_buffer_area = NULL;
3051	}
3052	if (adapter->rxtag != NULL) {
3053		bus_dma_tag_destroy(adapter->rxtag);
3054		adapter->rxtag = NULL;
3055	}
3056}
3057
3058/*********************************************************************
3059 *
3060 *  This routine executes in interrupt context. It replenishes
3061 *  the mbufs in the descriptor and sends data which has been
3062 *  dma'ed into host memory to upper layer.
3063 *
3064 *  We loop at most count times if count is > 0, or until done if
3065 *  count < 0.
3066 *
3067 *********************************************************************/
3068static int
3069em_rxeof(struct adapter *adapter, int count)
3070{
3071	struct ifnet	*ifp;
3072	struct mbuf	*mp;
3073	uint8_t		accept_frame = 0;
3074	uint8_t		eop = 0;
3075	uint16_t 	len, desc_len, prev_len_adj;
3076	int		i;
3077
3078	/* Pointer to the receive descriptor being examined. */
3079	struct em_rx_desc   *current_desc;
3080
3081	ifp = adapter->ifp;
3082	i = adapter->next_rx_desc_to_check;
3083	current_desc = &adapter->rx_desc_base[i];
3084	bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3085	    BUS_DMASYNC_POSTREAD);
3086
3087	if (!((current_desc->status) & E1000_RXD_STAT_DD))
3088		return (0);
3089
3090	while ((current_desc->status & E1000_RXD_STAT_DD) &&
3091	    (count != 0) &&
3092	    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3093		struct mbuf *m = NULL;
3094
3095		mp = adapter->rx_buffer_area[i].m_head;
3096		bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3097		    BUS_DMASYNC_POSTREAD);
3098		bus_dmamap_unload(adapter->rxtag,
3099		    adapter->rx_buffer_area[i].map);
3100
3101		accept_frame = 1;
3102		prev_len_adj = 0;
3103		desc_len = le16toh(current_desc->length);
3104		if (current_desc->status & E1000_RXD_STAT_EOP) {
3105			count--;
3106			eop = 1;
3107			if (desc_len < ETHER_CRC_LEN) {
3108				len = 0;
3109				prev_len_adj = ETHER_CRC_LEN - desc_len;
3110			} else
3111				len = desc_len - ETHER_CRC_LEN;
3112		} else {
3113			eop = 0;
3114			len = desc_len;
3115		}
3116
3117		if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3118			uint8_t		last_byte;
3119			uint32_t	pkt_len = desc_len;
3120
3121			if (adapter->fmp != NULL)
3122				pkt_len += adapter->fmp->m_pkthdr.len;
3123
3124			last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3125			if (TBI_ACCEPT(&adapter->hw, current_desc->status,
3126			    current_desc->errors,
3127			    pkt_len, last_byte)) {
3128				em_tbi_adjust_stats(&adapter->hw,
3129				    &adapter->stats, pkt_len,
3130				    adapter->hw.mac_addr);
3131				if (len > 0)
3132					len--;
3133			} else
3134				accept_frame = 0;
3135		}
3136
3137		if (accept_frame) {
3138			if (em_get_buf(i, adapter, NULL) == ENOBUFS) {
3139				adapter->dropped_pkts++;
3140				em_get_buf(i, adapter, mp);
3141				if (adapter->fmp != NULL)
3142					m_freem(adapter->fmp);
3143				adapter->fmp = NULL;
3144				adapter->lmp = NULL;
3145				break;
3146			}
3147
3148			/* Assign correct length to the current fragment */
3149			mp->m_len = len;
3150
3151			if (adapter->fmp == NULL) {
3152				mp->m_pkthdr.len = len;
3153				adapter->fmp = mp; /* Store the first mbuf */
3154				adapter->lmp = mp;
3155			} else {
3156				/* Chain mbuf's together */
3157				mp->m_flags &= ~M_PKTHDR;
3158				/*
3159				 * Adjust length of previous mbuf in chain if
3160				 * we received less than 4 bytes in the last
3161				 * descriptor.
3162				 */
3163				if (prev_len_adj > 0) {
3164					adapter->lmp->m_len -= prev_len_adj;
3165					adapter->fmp->m_pkthdr.len -=
3166					    prev_len_adj;
3167				}
3168				adapter->lmp->m_next = mp;
3169				adapter->lmp = adapter->lmp->m_next;
3170				adapter->fmp->m_pkthdr.len += len;
3171			}
3172
3173			if (eop) {
3174				adapter->fmp->m_pkthdr.rcvif = ifp;
3175				ifp->if_ipackets++;
3176				em_receive_checksum(adapter, current_desc,
3177				    adapter->fmp);
3178#ifndef __NO_STRICT_ALIGNMENT
3179				if (ifp->if_mtu > ETHERMTU &&
3180				    em_fixup_rx(adapter) != 0)
3181					goto skip;
3182#endif
3183				if (current_desc->status & E1000_RXD_STAT_VP)
3184					VLAN_INPUT_TAG(ifp, adapter->fmp,
3185					    (le16toh(current_desc->special) &
3186					    E1000_RXD_SPC_VLAN_MASK));
3187#ifndef __NO_STRICT_ALIGNMENT
3188skip:
3189#endif
3190				m = adapter->fmp;
3191				adapter->fmp = NULL;
3192				adapter->lmp = NULL;
3193			}
3194		} else {
3195			adapter->dropped_pkts++;
3196			em_get_buf(i, adapter, mp);
3197			if (adapter->fmp != NULL)
3198				m_freem(adapter->fmp);
3199			adapter->fmp = NULL;
3200			adapter->lmp = NULL;
3201		}
3202
3203		/* Zero out the receive descriptors status. */
3204		current_desc->status = 0;
3205		bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3206		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3207
3208		/* Advance our pointers to the next descriptor. */
3209		if (++i == adapter->num_rx_desc)
3210			i = 0;
3211		if (m != NULL) {
3212			adapter->next_rx_desc_to_check = i;
3213#ifdef DEVICE_POLLING
3214			EM_UNLOCK(adapter);
3215			(*ifp->if_input)(ifp, m);
3216			EM_LOCK(adapter);
3217#else
3218			(*ifp->if_input)(ifp, m);
3219#endif
3220			i = adapter->next_rx_desc_to_check;
3221		}
3222		current_desc = &adapter->rx_desc_base[i];
3223	}
3224	adapter->next_rx_desc_to_check = i;
3225
3226	/* Advance the E1000's Receive Queue #0  "Tail Pointer". */
3227	if (--i < 0)
3228		i = adapter->num_rx_desc - 1;
3229	E1000_WRITE_REG(&adapter->hw, RDT, i);
3230	if (!((current_desc->status) & E1000_RXD_STAT_DD))
3231		return (0);
3232
3233	return (1);
3234}
3235
3236#ifndef __NO_STRICT_ALIGNMENT
3237/*
3238 * When jumbo frames are enabled we should realign entire payload on
3239 * architecures with strict alignment. This is serious design mistake of 8254x
3240 * as it nullifies DMA operations. 8254x just allows RX buffer size to be
3241 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its
3242 * payload. On architecures without strict alignment restrictions 8254x still
3243 * performs unaligned memory access which would reduce the performance too.
3244 * To avoid copying over an entire frame to align, we allocate a new mbuf and
3245 * copy ethernet header to the new mbuf. The new mbuf is prepended into the
3246 * existing mbuf chain.
3247 *
3248 * Be aware, best performance of the 8254x is achived only when jumbo frame is
3249 * not used at all on architectures with strict alignment.
3250 */
3251static int
3252em_fixup_rx(struct adapter *adapter)
3253{
3254	struct mbuf *m, *n;
3255	int error;
3256
3257	error = 0;
3258	m = adapter->fmp;
3259	if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
3260		bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
3261		m->m_data += ETHER_HDR_LEN;
3262	} else {
3263		MGETHDR(n, M_DONTWAIT, MT_DATA);
3264		if (n != NULL) {
3265			bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
3266			m->m_data += ETHER_HDR_LEN;
3267			m->m_len -= ETHER_HDR_LEN;
3268			n->m_len = ETHER_HDR_LEN;
3269			M_MOVE_PKTHDR(n, m);
3270			n->m_next = m;
3271			adapter->fmp = n;
3272		} else {
3273			adapter->dropped_pkts++;
3274			m_freem(adapter->fmp);
3275			adapter->fmp = NULL;
3276			error = ENOMEM;
3277		}
3278	}
3279
3280	return (error);
3281}
3282#endif
3283
3284/*********************************************************************
3285 *
3286 *  Verify that the hardware indicated that the checksum is valid.
3287 *  Inform the stack about the status of checksum so that stack
3288 *  doesn't spend time verifying the checksum.
3289 *
3290 *********************************************************************/
3291static void
3292em_receive_checksum(struct adapter *adapter, struct em_rx_desc *rx_desc,
3293		    struct mbuf *mp)
3294{
3295	/* 82543 or newer only */
3296	if ((adapter->hw.mac_type < em_82543) ||
3297	    /* Ignore Checksum bit is set */
3298	    (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3299		mp->m_pkthdr.csum_flags = 0;
3300		return;
3301	}
3302
3303	if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3304		/* Did it pass? */
3305		if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3306			/* IP Checksum Good */
3307			mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
3308			mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3309
3310		} else {
3311			mp->m_pkthdr.csum_flags = 0;
3312		}
3313	}
3314
3315	if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3316		/* Did it pass? */
3317		if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3318			mp->m_pkthdr.csum_flags |=
3319			(CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
3320			mp->m_pkthdr.csum_data = htons(0xffff);
3321		}
3322	}
3323}
3324
3325
3326static void
3327em_enable_vlans(struct adapter *adapter)
3328{
3329	uint32_t ctrl;
3330
3331	E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN);
3332
3333	ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3334	ctrl |= E1000_CTRL_VME;
3335	E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3336}
3337
3338static void
3339em_disable_vlans(struct adapter *adapter)
3340{
3341	uint32_t ctrl;
3342
3343	ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3344	ctrl &= ~E1000_CTRL_VME;
3345	E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3346}
3347
3348static void
3349em_enable_intr(struct adapter *adapter)
3350{
3351	E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
3352}
3353
3354static void
3355em_disable_intr(struct adapter *adapter)
3356{
3357	/*
3358	 * The first version of 82542 had an errata where when link was forced
3359	 * it would stay up even up even if the cable was disconnected.
3360	 * Sequence errors were used to detect the disconnect and then the
3361	 * driver would unforce the link. This code in the in the ISR. For this
3362	 * to work correctly the Sequence error interrupt had to be enabled
3363	 * all the time.
3364	 */
3365
3366	if (adapter->hw.mac_type == em_82542_rev2_0)
3367	    E1000_WRITE_REG(&adapter->hw, IMC,
3368		(0xffffffff & ~E1000_IMC_RXSEQ));
3369	else
3370	    E1000_WRITE_REG(&adapter->hw, IMC,
3371		0xffffffff);
3372}
3373
3374static int
3375em_is_valid_ether_addr(uint8_t *addr)
3376{
3377	char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3378
3379	if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3380		return (FALSE);
3381	}
3382
3383	return (TRUE);
3384}
3385
3386void
3387em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3388{
3389	pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2);
3390}
3391
3392void
3393em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3394{
3395	*value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2);
3396}
3397
3398void
3399em_pci_set_mwi(struct em_hw *hw)
3400{
3401	pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3402	    (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
3403}
3404
3405void
3406em_pci_clear_mwi(struct em_hw *hw)
3407{
3408	pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3409	    (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
3410}
3411
3412/*********************************************************************
3413* 82544 Coexistence issue workaround.
3414*    There are 2 issues.
3415*       1. Transmit Hang issue.
3416*    To detect this issue, following equation can be used...
3417*	  SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3418*	  If SUM[3:0] is in between 1 to 4, we will have this issue.
3419*
3420*       2. DAC issue.
3421*    To detect this issue, following equation can be used...
3422*	  SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3423*	  If SUM[3:0] is in between 9 to c, we will have this issue.
3424*
3425*
3426*    WORKAROUND:
3427*	  Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3428*
3429*** *********************************************************************/
3430static uint32_t
3431em_fill_descriptors (bus_addr_t address, uint32_t length,
3432		PDESC_ARRAY desc_array)
3433{
3434	/* Since issue is sensitive to length and address.*/
3435	/* Let us first check the address...*/
3436	uint32_t safe_terminator;
3437	if (length <= 4) {
3438		desc_array->descriptor[0].address = address;
3439		desc_array->descriptor[0].length = length;
3440		desc_array->elements = 1;
3441		return (desc_array->elements);
3442	}
3443	safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3444	/* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3445	if (safe_terminator == 0   ||
3446	(safe_terminator > 4   &&
3447	safe_terminator < 9)   ||
3448	(safe_terminator > 0xC &&
3449	safe_terminator <= 0xF)) {
3450		desc_array->descriptor[0].address = address;
3451		desc_array->descriptor[0].length = length;
3452		desc_array->elements = 1;
3453		return (desc_array->elements);
3454	}
3455
3456	desc_array->descriptor[0].address = address;
3457	desc_array->descriptor[0].length = length - 4;
3458	desc_array->descriptor[1].address = address + (length - 4);
3459	desc_array->descriptor[1].length = 4;
3460	desc_array->elements = 2;
3461	return (desc_array->elements);
3462}
3463
3464/**********************************************************************
3465 *
3466 *  Update the board statistics counters.
3467 *
3468 **********************************************************************/
3469static void
3470em_update_stats_counters(struct adapter *adapter)
3471{
3472	struct ifnet   *ifp;
3473
3474	if(adapter->hw.media_type == em_media_type_copper ||
3475	   (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
3476		adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
3477		adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
3478	}
3479	adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
3480	adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
3481	adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
3482	adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
3483
3484	adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
3485	adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
3486	adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
3487	adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
3488	adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
3489	adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
3490	adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
3491	adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
3492	adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
3493	adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
3494	adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
3495	adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
3496	adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
3497	adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
3498	adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
3499	adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
3500	adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
3501	adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
3502	adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
3503	adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
3504
3505	/* For the 64-bit byte counters the low dword must be read first. */
3506	/* Both registers clear on the read of the high dword */
3507
3508	adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL);
3509	adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
3510	adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
3511	adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
3512
3513	adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
3514	adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
3515	adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
3516	adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
3517	adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
3518
3519	adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
3520	adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
3521	adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
3522	adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
3523
3524	adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
3525	adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
3526	adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
3527	adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
3528	adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
3529	adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
3530	adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
3531	adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
3532	adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
3533	adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
3534
3535	if (adapter->hw.mac_type >= em_82543) {
3536		adapter->stats.algnerrc += E1000_READ_REG(&adapter->hw, ALGNERRC);
3537		adapter->stats.rxerrc += E1000_READ_REG(&adapter->hw, RXERRC);
3538		adapter->stats.tncrs += E1000_READ_REG(&adapter->hw, TNCRS);
3539		adapter->stats.cexterr += E1000_READ_REG(&adapter->hw, CEXTERR);
3540		adapter->stats.tsctc += E1000_READ_REG(&adapter->hw, TSCTC);
3541		adapter->stats.tsctfc += E1000_READ_REG(&adapter->hw, TSCTFC);
3542	}
3543	ifp = adapter->ifp;
3544
3545	ifp->if_collisions = adapter->stats.colc;
3546
3547	/* Rx Errors */
3548	ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc +
3549	    adapter->stats.crcerrs + adapter->stats.algnerrc + adapter->stats.ruc +
3550	    adapter->stats.roc + adapter->stats.mpc + adapter->stats.cexterr;
3551
3552	/* Tx Errors */
3553	ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol +
3554	    adapter->watchdog_events;
3555}
3556
3557
3558/**********************************************************************
3559 *
3560 *  This routine is called only when em_display_debug_stats is enabled.
3561 *  This routine provides a way to take a look at important statistics
3562 *  maintained by the driver and hardware.
3563 *
3564 **********************************************************************/
3565static void
3566em_print_debug_info(struct adapter *adapter)
3567{
3568	device_t dev = adapter->dev;
3569	uint8_t *hw_addr = adapter->hw.hw_addr;
3570
3571	device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3572	device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3573	    E1000_READ_REG(&adapter->hw, CTRL),
3574	    E1000_READ_REG(&adapter->hw, RCTL));
3575	device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3576	    ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),\
3577	    (E1000_READ_REG(&adapter->hw, PBA) & 0xffff) );
3578	device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3579	    adapter->hw.fc_high_water,
3580	    adapter->hw.fc_low_water);
3581	device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3582	    E1000_READ_REG(&adapter->hw, TIDV),
3583	    E1000_READ_REG(&adapter->hw, TADV));
3584	device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3585	    E1000_READ_REG(&adapter->hw, RDTR),
3586	    E1000_READ_REG(&adapter->hw, RADV));
3587	device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3588	    (long long)adapter->tx_fifo_wrk_cnt,
3589	    (long long)adapter->tx_fifo_reset_cnt);
3590	device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3591	    E1000_READ_REG(&adapter->hw, TDH),
3592	    E1000_READ_REG(&adapter->hw, TDT));
3593	device_printf(dev, "Num Tx descriptors avail = %d\n",
3594	    adapter->num_tx_desc_avail);
3595	device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3596	    adapter->no_tx_desc_avail1);
3597	device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3598	    adapter->no_tx_desc_avail2);
3599	device_printf(dev, "Std mbuf failed = %ld\n",
3600	    adapter->mbuf_alloc_failed);
3601	device_printf(dev, "Std mbuf cluster failed = %ld\n",
3602	    adapter->mbuf_cluster_failed);
3603	device_printf(dev, "Driver dropped packets = %ld\n",
3604	    adapter->dropped_pkts);
3605}
3606
3607static void
3608em_print_hw_stats(struct adapter *adapter)
3609{
3610	device_t dev = adapter->dev;
3611
3612	device_printf(dev, "Excessive collisions = %lld\n",
3613	    (long long)adapter->stats.ecol);
3614	device_printf(dev, "Symbol errors = %lld\n",
3615	    (long long)adapter->stats.symerrs);
3616	device_printf(dev, "Sequence errors = %lld\n",
3617	    (long long)adapter->stats.sec);
3618	device_printf(dev, "Defer count = %lld\n", (long long)adapter->stats.dc);
3619
3620	device_printf(dev, "Missed Packets = %lld\n", (long long)adapter->stats.mpc);
3621	device_printf(dev, "Receive No Buffers = %lld\n",
3622	    (long long)adapter->stats.rnbc);
3623	/* RLEC is inaccurate on some hardware, calculate our own. */
3624	device_printf(dev, "Receive Length Errors = %lld\n",
3625	    ((long long)adapter->stats.roc + (long long)adapter->stats.ruc));
3626	device_printf(dev, "Receive errors = %lld\n",
3627	    (long long)adapter->stats.rxerrc);
3628	device_printf(dev, "Crc errors = %lld\n", (long long)adapter->stats.crcerrs);
3629	device_printf(dev, "Alignment errors = %lld\n",
3630	    (long long)adapter->stats.algnerrc);
3631	device_printf(dev, "Carrier extension errors = %lld\n",
3632	    (long long)adapter->stats.cexterr);
3633	device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns);
3634	device_printf(dev, "watchdog timeouts = %ld\n", adapter->watchdog_events);
3635
3636	device_printf(dev, "XON Rcvd = %lld\n", (long long)adapter->stats.xonrxc);
3637	device_printf(dev, "XON Xmtd = %lld\n", (long long)adapter->stats.xontxc);
3638	device_printf(dev, "XOFF Rcvd = %lld\n", (long long)adapter->stats.xoffrxc);
3639	device_printf(dev, "XOFF Xmtd = %lld\n", (long long)adapter->stats.xofftxc);
3640
3641	device_printf(dev, "Good Packets Rcvd = %lld\n",
3642	    (long long)adapter->stats.gprc);
3643	device_printf(dev, "Good Packets Xmtd = %lld\n",
3644	    (long long)adapter->stats.gptc);
3645}
3646
3647static int
3648em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3649{
3650	struct adapter *adapter;
3651	int error;
3652	int result;
3653
3654	result = -1;
3655	error = sysctl_handle_int(oidp, &result, 0, req);
3656
3657	if (error || !req->newptr)
3658		return (error);
3659
3660	if (result == 1) {
3661		adapter = (struct adapter *)arg1;
3662		em_print_debug_info(adapter);
3663	}
3664
3665	return (error);
3666}
3667
3668
3669static int
3670em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3671{
3672	struct adapter *adapter;
3673	int error;
3674	int result;
3675
3676	result = -1;
3677	error = sysctl_handle_int(oidp, &result, 0, req);
3678
3679	if (error || !req->newptr)
3680		return (error);
3681
3682	if (result == 1) {
3683		adapter = (struct adapter *)arg1;
3684		em_print_hw_stats(adapter);
3685	}
3686
3687	return (error);
3688}
3689
3690static int
3691em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3692{
3693	struct em_int_delay_info *info;
3694	struct adapter *adapter;
3695	uint32_t regval;
3696	int error;
3697	int usecs;
3698	int ticks;
3699
3700	info = (struct em_int_delay_info *)arg1;
3701	usecs = info->value;
3702	error = sysctl_handle_int(oidp, &usecs, 0, req);
3703	if (error != 0 || req->newptr == NULL)
3704		return (error);
3705	if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3706		return (EINVAL);
3707	info->value = usecs;
3708	ticks = E1000_USECS_TO_TICKS(usecs);
3709
3710	adapter = info->adapter;
3711
3712	EM_LOCK(adapter);
3713	regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
3714	regval = (regval & ~0xffff) | (ticks & 0xffff);
3715	/* Handle a few special cases. */
3716	switch (info->offset) {
3717	case E1000_RDTR:
3718	case E1000_82542_RDTR:
3719		regval |= E1000_RDT_FPDB;
3720		break;
3721	case E1000_TIDV:
3722	case E1000_82542_TIDV:
3723		if (ticks == 0) {
3724			adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
3725			/* Don't write 0 into the TIDV register. */
3726			regval++;
3727		} else
3728			adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3729		break;
3730	}
3731	E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
3732	EM_UNLOCK(adapter);
3733	return (0);
3734}
3735
3736static void
3737em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
3738	const char *description, struct em_int_delay_info *info,
3739	int offset, int value)
3740{
3741	info->adapter = adapter;
3742	info->offset = offset;
3743	info->value = value;
3744	SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
3745	    SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
3746	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3747	    info, 0, em_sysctl_int_delay, "I", description);
3748}
3749
3750#ifndef DEVICE_POLLING
3751static void
3752em_add_int_process_limit(struct adapter *adapter, const char *name,
3753	const char *description, int *limit, int value)
3754{
3755	*limit = value;
3756	SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev),
3757	    SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
3758	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description);
3759}
3760#endif
3761