if_em.c revision 160733
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 160733 2006-07-27 00:29:44Z yongari $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/if_ether.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcivar.h> 76#include <dev/pci/pcireg.h> 77#include <dev/em/if_em_hw.h> 78#include <dev/em/if_em.h> 79 80/********************************************************************* 81 * Set this to one to display debug statistics 82 *********************************************************************/ 83int em_display_debug_stats = 0; 84 85/********************************************************************* 86 * Driver version 87 *********************************************************************/ 88 89char em_driver_version[] = "Version - 5.1.5"; 90 91 92/********************************************************************* 93 * PCI Device ID Table 94 * 95 * Used by probe to select devices to load on 96 * Last field stores an index into em_strings 97 * Last entry must be all 0s 98 * 99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 100 *********************************************************************/ 101 102static em_vendor_info_t em_vendor_info_array[] = 103{ 104 /* Intel(R) PRO/1000 Network Connection */ 105 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 110 111 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 118 119 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 120 121 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 124 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 128 129 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 135 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 144 PCI_ANY_ID, PCI_ANY_ID, 0}, 145 146 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 150 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 154 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 162 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 163 PCI_ANY_ID, PCI_ANY_ID, 0}, 164 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 165 PCI_ANY_ID, PCI_ANY_ID, 0}, 166 167 /* required last entry */ 168 { 0, 0, 0, 0, 0} 169}; 170 171/********************************************************************* 172 * Table of branding strings for all supported NICs. 173 *********************************************************************/ 174 175static char *em_strings[] = { 176 "Intel(R) PRO/1000 Network Connection" 177}; 178 179/********************************************************************* 180 * Function prototypes 181 *********************************************************************/ 182static int em_probe(device_t); 183static int em_attach(device_t); 184static int em_detach(device_t); 185static int em_shutdown(device_t); 186static int em_suspend(device_t); 187static int em_resume(device_t); 188static void em_start(struct ifnet *); 189static void em_start_locked(struct ifnet *ifp); 190static int em_ioctl(struct ifnet *, u_long, caddr_t); 191static void em_watchdog(struct ifnet *); 192static void em_init(void *); 193static void em_init_locked(struct em_softc *); 194static void em_stop(void *); 195static void em_media_status(struct ifnet *, struct ifmediareq *); 196static int em_media_change(struct ifnet *); 197static void em_identify_hardware(struct em_softc *); 198static int em_allocate_pci_resources(struct em_softc *); 199static int em_allocate_intr(struct em_softc *); 200static void em_free_intr(struct em_softc *); 201static void em_free_pci_resources(struct em_softc *); 202static void em_local_timer(void *); 203static int em_hardware_init(struct em_softc *); 204static void em_setup_interface(device_t, struct em_softc *); 205static int em_setup_transmit_structures(struct em_softc *); 206static void em_initialize_transmit_unit(struct em_softc *); 207static int em_setup_receive_structures(struct em_softc *); 208static void em_initialize_receive_unit(struct em_softc *); 209static void em_enable_intr(struct em_softc *); 210static void em_disable_intr(struct em_softc *); 211static void em_free_transmit_structures(struct em_softc *); 212static void em_free_receive_structures(struct em_softc *); 213static void em_update_stats_counters(struct em_softc *); 214static void em_txeof(struct em_softc *); 215static int em_allocate_receive_structures(struct em_softc *); 216static int em_allocate_transmit_structures(struct em_softc *); 217static int em_rxeof(struct em_softc *, int); 218#ifndef __NO_STRICT_ALIGNMENT 219static int em_fixup_rx(struct em_softc *); 220#endif 221static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 222 struct mbuf *); 223static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 224 uint32_t *, uint32_t *); 225static void em_set_promisc(struct em_softc *); 226static void em_disable_promisc(struct em_softc *); 227static void em_set_multi(struct em_softc *); 228static void em_print_hw_stats(struct em_softc *); 229static void em_update_link_status(struct em_softc *); 230static int em_get_buf(int i, struct em_softc *, struct mbuf *); 231static void em_enable_vlans(struct em_softc *); 232static void em_disable_vlans(struct em_softc *); 233static int em_encap(struct em_softc *, struct mbuf **); 234static void em_smartspeed(struct em_softc *); 235static int em_82547_fifo_workaround(struct em_softc *, int); 236static void em_82547_update_fifo_head(struct em_softc *, int); 237static int em_82547_tx_fifo_reset(struct em_softc *); 238static void em_82547_move_tail(void *arg); 239static void em_82547_move_tail_locked(struct em_softc *); 240static int em_dma_malloc(struct em_softc *, bus_size_t, 241 struct em_dma_alloc *, int); 242static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 243static void em_print_debug_info(struct em_softc *); 244static int em_is_valid_ether_addr(uint8_t *); 245static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 246static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 247static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 248 PDESC_ARRAY desc_array); 249static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 250static void em_add_int_delay_sysctl(struct em_softc *, const char *, 251 const char *, struct em_int_delay_info *, int, int); 252 253/* 254 * Fast interrupt handler and legacy ithread/polling modes are 255 * mutually exclusive. 256 */ 257#ifdef DEVICE_POLLING 258static poll_handler_t em_poll; 259static void em_intr(void *); 260#else 261static void em_intr_fast(void *); 262static void em_add_int_process_limit(struct em_softc *, const char *, 263 const char *, int *, int); 264static void em_handle_rxtx(void *context, int pending); 265static void em_handle_link(void *context, int pending); 266#endif 267 268/********************************************************************* 269 * FreeBSD Device Interface Entry Points 270 *********************************************************************/ 271 272static device_method_t em_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, em_probe), 275 DEVMETHOD(device_attach, em_attach), 276 DEVMETHOD(device_detach, em_detach), 277 DEVMETHOD(device_shutdown, em_shutdown), 278 DEVMETHOD(device_suspend, em_suspend), 279 DEVMETHOD(device_resume, em_resume), 280 {0, 0} 281}; 282 283static driver_t em_driver = { 284 "em", em_methods, sizeof(struct em_softc), 285}; 286 287static devclass_t em_devclass; 288DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 289MODULE_DEPEND(em, pci, 1, 1, 1); 290MODULE_DEPEND(em, ether, 1, 1, 1); 291 292/********************************************************************* 293 * Tunable default values. 294 *********************************************************************/ 295 296#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 297#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 298 299static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 300static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 301static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 302static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 303static int em_rxd = EM_DEFAULT_RXD; 304static int em_txd = EM_DEFAULT_TXD; 305 306TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 307TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 308TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 309TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 310TUNABLE_INT("hw.em.rxd", &em_rxd); 311TUNABLE_INT("hw.em.txd", &em_txd); 312#ifndef DEVICE_POLLING 313static int em_rx_process_limit = 100; 314TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 315#endif 316 317/********************************************************************* 318 * Device identification routine 319 * 320 * em_probe determines if the driver should be loaded on 321 * adapter based on PCI vendor/device id of the adapter. 322 * 323 * return BUS_PROBE_DEFAULT on success, positive on failure 324 *********************************************************************/ 325 326static int 327em_probe(device_t dev) 328{ 329 char adapter_name[60]; 330 uint16_t pci_vendor_id = 0; 331 uint16_t pci_device_id = 0; 332 uint16_t pci_subvendor_id = 0; 333 uint16_t pci_subdevice_id = 0; 334 em_vendor_info_t *ent; 335 336 INIT_DEBUGOUT("em_probe: begin"); 337 338 pci_vendor_id = pci_get_vendor(dev); 339 if (pci_vendor_id != EM_VENDOR_ID) 340 return (ENXIO); 341 342 pci_device_id = pci_get_device(dev); 343 pci_subvendor_id = pci_get_subvendor(dev); 344 pci_subdevice_id = pci_get_subdevice(dev); 345 346 ent = em_vendor_info_array; 347 while (ent->vendor_id != 0) { 348 if ((pci_vendor_id == ent->vendor_id) && 349 (pci_device_id == ent->device_id) && 350 351 ((pci_subvendor_id == ent->subvendor_id) || 352 (ent->subvendor_id == PCI_ANY_ID)) && 353 354 ((pci_subdevice_id == ent->subdevice_id) || 355 (ent->subdevice_id == PCI_ANY_ID))) { 356 sprintf(adapter_name, "%s %s", 357 em_strings[ent->index], 358 em_driver_version); 359 device_set_desc_copy(dev, adapter_name); 360 return (BUS_PROBE_DEFAULT); 361 } 362 ent++; 363 } 364 365 return (ENXIO); 366} 367 368/********************************************************************* 369 * Device initialization routine 370 * 371 * The attach entry point is called when the driver is being loaded. 372 * This routine identifies the type of hardware, allocates all resources 373 * and initializes the hardware. 374 * 375 * return 0 on success, positive on failure 376 *********************************************************************/ 377 378static int 379em_attach(device_t dev) 380{ 381 struct em_softc *sc; 382 int tsize, rsize; 383 int error = 0; 384 385 INIT_DEBUGOUT("em_attach: begin"); 386 387 sc = device_get_softc(dev); 388 sc->dev = sc->osdep.dev = dev; 389 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 390 391 /* SYSCTL stuff */ 392 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 393 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 394 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 395 em_sysctl_debug_info, "I", "Debug Information"); 396 397 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 398 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 399 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 400 em_sysctl_stats, "I", "Statistics"); 401 402 callout_init(&sc->timer, CALLOUT_MPSAFE); 403 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 404 405 /* Determine hardware revision */ 406 em_identify_hardware(sc); 407 408 /* Set up some sysctls for the tunable interrupt delays */ 409 em_add_int_delay_sysctl(sc, "rx_int_delay", 410 "receive interrupt delay in usecs", &sc->rx_int_delay, 411 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 412 em_add_int_delay_sysctl(sc, "tx_int_delay", 413 "transmit interrupt delay in usecs", &sc->tx_int_delay, 414 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 415 if (sc->hw.mac_type >= em_82540) { 416 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 417 "receive interrupt delay limit in usecs", 418 &sc->rx_abs_int_delay, 419 E1000_REG_OFFSET(&sc->hw, RADV), 420 em_rx_abs_int_delay_dflt); 421 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 422 "transmit interrupt delay limit in usecs", 423 &sc->tx_abs_int_delay, 424 E1000_REG_OFFSET(&sc->hw, TADV), 425 em_tx_abs_int_delay_dflt); 426 } 427 428#ifndef DEVICE_POLLING 429 /* Sysctls for limiting the amount of work done in the taskqueue */ 430 em_add_int_process_limit(sc, "rx_processing_limit", 431 "max number of rx packets to process", &sc->rx_process_limit, 432 em_rx_process_limit); 433#endif 434 435 /* 436 * Validate number of transmit and receive descriptors. It 437 * must not exceed hardware maximum, and must be multiple 438 * of E1000_DBA_ALIGN. 439 */ 440 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 441 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 442 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 443 (em_txd < EM_MIN_TXD)) { 444 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 445 EM_DEFAULT_TXD, em_txd); 446 sc->num_tx_desc = EM_DEFAULT_TXD; 447 } else 448 sc->num_tx_desc = em_txd; 449 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 450 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 451 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 452 (em_rxd < EM_MIN_RXD)) { 453 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 454 EM_DEFAULT_RXD, em_rxd); 455 sc->num_rx_desc = EM_DEFAULT_RXD; 456 } else 457 sc->num_rx_desc = em_rxd; 458 459 sc->hw.autoneg = DO_AUTO_NEG; 460 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 461 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 462 sc->hw.tbi_compatibility_en = TRUE; 463 sc->rx_buffer_len = EM_RXBUFFER_2048; 464 465 sc->hw.phy_init_script = 1; 466 sc->hw.phy_reset_disable = FALSE; 467 468#ifndef EM_MASTER_SLAVE 469 sc->hw.master_slave = em_ms_hw_default; 470#else 471 sc->hw.master_slave = EM_MASTER_SLAVE; 472#endif 473 /* 474 * Set the max frame size assuming standard ethernet 475 * sized frames. 476 */ 477 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 478 479 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 480 481 /* 482 * This controls when hardware reports transmit completion 483 * status. 484 */ 485 sc->hw.report_tx_early = 1; 486 if (em_allocate_pci_resources(sc)) { 487 device_printf(dev, "Allocation of PCI resources failed\n"); 488 error = ENXIO; 489 goto err_pci; 490 } 491 492 /* Initialize eeprom parameters */ 493 em_init_eeprom_params(&sc->hw); 494 495 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 496 E1000_DBA_ALIGN); 497 498 /* Allocate Transmit Descriptor ring */ 499 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 500 device_printf(dev, "Unable to allocate tx_desc memory\n"); 501 error = ENOMEM; 502 goto err_tx_desc; 503 } 504 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 505 506 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 507 E1000_DBA_ALIGN); 508 509 /* Allocate Receive Descriptor ring */ 510 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 511 device_printf(dev, "Unable to allocate rx_desc memory\n"); 512 error = ENOMEM; 513 goto err_rx_desc; 514 } 515 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 516 517 /* Initialize the hardware */ 518 if (em_hardware_init(sc)) { 519 device_printf(dev, "Unable to initialize the hardware\n"); 520 error = EIO; 521 goto err_hw_init; 522 } 523 524 /* Copy the permanent MAC address out of the EEPROM */ 525 if (em_read_mac_addr(&sc->hw) < 0) { 526 device_printf(dev, "EEPROM read error while reading MAC" 527 " address\n"); 528 error = EIO; 529 goto err_hw_init; 530 } 531 532 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 533 device_printf(dev, "Invalid MAC address\n"); 534 error = EIO; 535 goto err_hw_init; 536 } 537 538 /* Setup OS specific network interface */ 539 em_setup_interface(dev, sc); 540 541 em_allocate_intr(sc); 542 543 /* Initialize statistics */ 544 em_clear_hw_cntrs(&sc->hw); 545 em_update_stats_counters(sc); 546 sc->hw.get_link_status = 1; 547 em_update_link_status(sc); 548 549 /* Indicate SOL/IDER usage */ 550 if (em_check_phy_reset_block(&sc->hw)) 551 device_printf(dev, 552 "PHY reset is blocked due to SOL/IDER session.\n"); 553 554 /* Identify 82544 on PCIX */ 555 em_get_bus_info(&sc->hw); 556 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 557 sc->pcix_82544 = TRUE; 558 else 559 sc->pcix_82544 = FALSE; 560 561 INIT_DEBUGOUT("em_attach: end"); 562 563 return (0); 564 565err_hw_init: 566 em_dma_free(sc, &sc->rxdma); 567err_rx_desc: 568 em_dma_free(sc, &sc->txdma); 569err_tx_desc: 570err_pci: 571 em_free_intr(sc); 572 em_free_pci_resources(sc); 573 EM_LOCK_DESTROY(sc); 574 575 return (error); 576} 577 578/********************************************************************* 579 * Device removal routine 580 * 581 * The detach entry point is called when the driver is being removed. 582 * This routine stops the adapter and deallocates all the resources 583 * that were allocated for driver operation. 584 * 585 * return 0 on success, positive on failure 586 *********************************************************************/ 587 588static int 589em_detach(device_t dev) 590{ 591 struct em_softc *sc = device_get_softc(dev); 592 struct ifnet *ifp = sc->ifp; 593 594 INIT_DEBUGOUT("em_detach: begin"); 595 596#ifdef DEVICE_POLLING 597 if (ifp->if_capenable & IFCAP_POLLING) 598 ether_poll_deregister(ifp); 599#endif 600 601 em_free_intr(sc); 602 EM_LOCK(sc); 603 sc->in_detach = 1; 604 em_stop(sc); 605 em_phy_hw_reset(&sc->hw); 606 EM_UNLOCK(sc); 607 ether_ifdetach(sc->ifp); 608 609 em_free_pci_resources(sc); 610 bus_generic_detach(dev); 611 if_free(ifp); 612 613 /* Free Transmit Descriptor ring */ 614 if (sc->tx_desc_base) { 615 em_dma_free(sc, &sc->txdma); 616 sc->tx_desc_base = NULL; 617 } 618 619 /* Free Receive Descriptor ring */ 620 if (sc->rx_desc_base) { 621 em_dma_free(sc, &sc->rxdma); 622 sc->rx_desc_base = NULL; 623 } 624 625 EM_LOCK_DESTROY(sc); 626 627 return (0); 628} 629 630/********************************************************************* 631 * 632 * Shutdown entry point 633 * 634 **********************************************************************/ 635 636static int 637em_shutdown(device_t dev) 638{ 639 struct em_softc *sc = device_get_softc(dev); 640 EM_LOCK(sc); 641 em_stop(sc); 642 EM_UNLOCK(sc); 643 return (0); 644} 645 646/* 647 * Suspend/resume device methods. 648 */ 649static int 650em_suspend(device_t dev) 651{ 652 struct em_softc *sc = device_get_softc(dev); 653 654 EM_LOCK(sc); 655 em_stop(sc); 656 EM_UNLOCK(sc); 657 658 return bus_generic_suspend(dev); 659} 660 661static int 662em_resume(device_t dev) 663{ 664 struct em_softc *sc = device_get_softc(dev); 665 struct ifnet *ifp = sc->ifp; 666 667 EM_LOCK(sc); 668 em_init_locked(sc); 669 if ((ifp->if_flags & IFF_UP) && 670 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 671 em_start_locked(ifp); 672 EM_UNLOCK(sc); 673 674 return bus_generic_resume(dev); 675} 676 677 678/********************************************************************* 679 * Transmit entry point 680 * 681 * em_start is called by the stack to initiate a transmit. 682 * The driver will remain in this routine as long as there are 683 * packets to transmit and transmit resources are available. 684 * In case resources are not available stack is notified and 685 * the packet is requeued. 686 **********************************************************************/ 687 688static void 689em_start_locked(struct ifnet *ifp) 690{ 691 struct em_softc *sc = ifp->if_softc; 692 struct mbuf *m_head; 693 694 EM_LOCK_ASSERT(sc); 695 696 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 697 IFF_DRV_RUNNING) 698 return; 699 if (!sc->link_active) 700 return; 701 702 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 703 704 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 705 if (m_head == NULL) 706 break; 707 /* 708 * em_encap() can modify our pointer, and or make it NULL on 709 * failure. In that event, we can't requeue. 710 */ 711 if (em_encap(sc, &m_head)) { 712 if (m_head == NULL) 713 break; 714 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 715 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 716 break; 717 } 718 719 /* Send a copy of the frame to the BPF listener */ 720 BPF_MTAP(ifp, m_head); 721 722 /* Set timeout in case hardware has problems transmitting. */ 723 ifp->if_timer = EM_TX_TIMEOUT; 724 } 725} 726 727static void 728em_start(struct ifnet *ifp) 729{ 730 struct em_softc *sc = ifp->if_softc; 731 732 EM_LOCK(sc); 733 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 734 em_start_locked(ifp); 735 EM_UNLOCK(sc); 736} 737 738/********************************************************************* 739 * Ioctl entry point 740 * 741 * em_ioctl is called when the user wants to configure the 742 * interface. 743 * 744 * return 0 on success, positive on failure 745 **********************************************************************/ 746 747static int 748em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 749{ 750 struct em_softc *sc = ifp->if_softc; 751 struct ifreq *ifr = (struct ifreq *)data; 752 struct ifaddr *ifa = (struct ifaddr *)data; 753 int error = 0; 754 755 if (sc->in_detach) 756 return (error); 757 758 switch (command) { 759 case SIOCSIFADDR: 760 case SIOCGIFADDR: 761 if (ifa->ifa_addr->sa_family == AF_INET) { 762 /* 763 * XXX 764 * Since resetting hardware takes a very long time 765 * and results in link renegotiation we only 766 * initialize the hardware only when it is absolutely 767 * required. 768 */ 769 ifp->if_flags |= IFF_UP; 770 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 771 EM_LOCK(sc); 772 em_init_locked(sc); 773 EM_UNLOCK(sc); 774 } 775 arp_ifinit(ifp, ifa); 776 } else 777 error = ether_ioctl(ifp, command, data); 778 break; 779 case SIOCSIFMTU: 780 { 781 int max_frame_size; 782 uint16_t eeprom_data = 0; 783 784 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 785 786 EM_LOCK(sc); 787 switch (sc->hw.mac_type) { 788 case em_82573: 789 /* 790 * 82573 only supports jumbo frames 791 * if ASPM is disabled. 792 */ 793 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1, 794 &eeprom_data); 795 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 796 max_frame_size = ETHER_MAX_LEN; 797 break; 798 } 799 /* Allow Jumbo frames - fall thru */ 800 case em_82571: 801 case em_82572: 802 case em_80003es2lan: /* Limit Jumbo Frame size */ 803 max_frame_size = 9234; 804 break; 805 default: 806 max_frame_size = MAX_JUMBO_FRAME_SIZE; 807 } 808 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 809 ETHER_CRC_LEN) { 810 EM_UNLOCK(sc); 811 error = EINVAL; 812 break; 813 } 814 815 ifp->if_mtu = ifr->ifr_mtu; 816 sc->hw.max_frame_size = 817 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 818 em_init_locked(sc); 819 EM_UNLOCK(sc); 820 break; 821 } 822 case SIOCSIFFLAGS: 823 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 824 EM_LOCK(sc); 825 if (ifp->if_flags & IFF_UP) { 826 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 827 if ((ifp->if_flags ^ sc->if_flags) & 828 IFF_PROMISC) { 829 em_disable_promisc(sc); 830 em_set_promisc(sc); 831 } 832 } else 833 em_init_locked(sc); 834 } else { 835 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 836 em_stop(sc); 837 } 838 } 839 sc->if_flags = ifp->if_flags; 840 EM_UNLOCK(sc); 841 break; 842 case SIOCADDMULTI: 843 case SIOCDELMULTI: 844 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 845 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 846 EM_LOCK(sc); 847 em_disable_intr(sc); 848 em_set_multi(sc); 849 if (sc->hw.mac_type == em_82542_rev2_0) { 850 em_initialize_receive_unit(sc); 851 } 852#ifdef DEVICE_POLLING 853 if (!(ifp->if_capenable & IFCAP_POLLING)) 854#endif 855 em_enable_intr(sc); 856 EM_UNLOCK(sc); 857 } 858 break; 859 case SIOCSIFMEDIA: 860 case SIOCGIFMEDIA: 861 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 862 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 863 break; 864 case SIOCSIFCAP: 865 { 866 int mask, reinit; 867 868 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 869 reinit = 0; 870 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 871#ifdef DEVICE_POLLING 872 if (mask & IFCAP_POLLING) { 873 if (ifr->ifr_reqcap & IFCAP_POLLING) { 874 error = ether_poll_register(em_poll, ifp); 875 if (error) 876 return (error); 877 EM_LOCK(sc); 878 em_disable_intr(sc); 879 ifp->if_capenable |= IFCAP_POLLING; 880 EM_UNLOCK(sc); 881 } else { 882 error = ether_poll_deregister(ifp); 883 /* Enable interrupt even in error case */ 884 EM_LOCK(sc); 885 em_enable_intr(sc); 886 ifp->if_capenable &= ~IFCAP_POLLING; 887 EM_UNLOCK(sc); 888 } 889 } 890#endif 891 if (mask & IFCAP_HWCSUM) { 892 ifp->if_capenable ^= IFCAP_HWCSUM; 893 reinit = 1; 894 } 895 if (mask & IFCAP_VLAN_HWTAGGING) { 896 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 897 reinit = 1; 898 } 899 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 900 em_init(sc); 901 VLAN_CAPABILITIES(ifp); 902 break; 903 } 904 default: 905 error = ether_ioctl(ifp, command, data); 906 break; 907 } 908 909 return (error); 910} 911 912/********************************************************************* 913 * Watchdog entry point 914 * 915 * This routine is called whenever hardware quits transmitting. 916 * 917 **********************************************************************/ 918 919static void 920em_watchdog(struct ifnet *ifp) 921{ 922 struct em_softc *sc = ifp->if_softc; 923 924 EM_LOCK(sc); 925 /* If we are in this routine because of pause frames, then 926 * don't reset the hardware. 927 */ 928 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 929 ifp->if_timer = EM_TX_TIMEOUT; 930 EM_UNLOCK(sc); 931 return; 932 } 933 934 if (em_check_for_link(&sc->hw) == 0) 935 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 936 937 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 938 sc->watchdog_events++; 939 940 em_init_locked(sc); 941 EM_UNLOCK(sc); 942} 943 944/********************************************************************* 945 * Init entry point 946 * 947 * This routine is used in two ways. It is used by the stack as 948 * init entry point in network interface structure. It is also used 949 * by the driver as a hw/sw initialization routine to get to a 950 * consistent state. 951 * 952 * return 0 on success, positive on failure 953 **********************************************************************/ 954 955static void 956em_init_locked(struct em_softc *sc) 957{ 958 struct ifnet *ifp = sc->ifp; 959 device_t dev = sc->dev; 960 uint32_t pba; 961 962 INIT_DEBUGOUT("em_init: begin"); 963 964 EM_LOCK_ASSERT(sc); 965 966 em_stop(sc); 967 968 /* 969 * Packet Buffer Allocation (PBA) 970 * Writing PBA sets the receive portion of the buffer 971 * the remainder is used for the transmit buffer. 972 */ 973 switch (sc->hw.mac_type) { 974 case em_82547: 975 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 976 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 977 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 978 else 979 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 980 sc->tx_fifo_head = 0; 981 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 982 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 983 break; 984 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */ 985 case em_82571: /* 82571: Total Packet Buffer is 48K */ 986 case em_82572: /* 82572: Total Packet Buffer is 48K */ 987 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 988 break; 989 case em_82573: /* 82573: Total Packet Buffer is 32K */ 990 /* Jumbo frames not supported */ 991 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 992 break; 993 default: 994 /* Devices before 82547 had a Packet Buffer of 64K. */ 995 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 996 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 997 else 998 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 999 } 1000 1001 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1002 E1000_WRITE_REG(&sc->hw, PBA, pba); 1003 1004 /* Get the latest mac address, User can use a LAA */ 1005 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 1006 1007 /* Initialize the hardware */ 1008 if (em_hardware_init(sc)) { 1009 device_printf(dev, "Unable to initialize the hardware\n"); 1010 return; 1011 } 1012 em_update_link_status(sc); 1013 1014 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1015 em_enable_vlans(sc); 1016 1017 /* Prepare transmit descriptors and buffers */ 1018 if (em_setup_transmit_structures(sc)) { 1019 device_printf(dev, "Could not setup transmit structures\n"); 1020 em_stop(sc); 1021 return; 1022 } 1023 em_initialize_transmit_unit(sc); 1024 1025 /* Setup Multicast table */ 1026 em_set_multi(sc); 1027 1028 /* Prepare receive descriptors and buffers */ 1029 if (em_setup_receive_structures(sc)) { 1030 device_printf(dev, "Could not setup receive structures\n"); 1031 em_stop(sc); 1032 return; 1033 } 1034 em_initialize_receive_unit(sc); 1035 1036 /* Don't loose promiscuous settings */ 1037 em_set_promisc(sc); 1038 1039 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1040 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1041 1042 if (sc->hw.mac_type >= em_82543) { 1043 if (ifp->if_capenable & IFCAP_TXCSUM) 1044 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1045 else 1046 ifp->if_hwassist = 0; 1047 } 1048 1049 callout_reset(&sc->timer, hz, em_local_timer, sc); 1050 em_clear_hw_cntrs(&sc->hw); 1051#ifdef DEVICE_POLLING 1052 /* 1053 * Only enable interrupts if we are not polling, make sure 1054 * they are off otherwise. 1055 */ 1056 if (ifp->if_capenable & IFCAP_POLLING) 1057 em_disable_intr(sc); 1058 else 1059#endif /* DEVICE_POLLING */ 1060 em_enable_intr(sc); 1061 1062 /* Don't reset the phy next time init gets called */ 1063 sc->hw.phy_reset_disable = TRUE; 1064} 1065 1066static void 1067em_init(void *arg) 1068{ 1069 struct em_softc *sc = arg; 1070 1071 EM_LOCK(sc); 1072 em_init_locked(sc); 1073 EM_UNLOCK(sc); 1074} 1075 1076 1077#ifdef DEVICE_POLLING 1078/********************************************************************* 1079 * 1080 * Legacy polling routine 1081 * 1082 *********************************************************************/ 1083static void 1084em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1085{ 1086 struct em_softc *sc = ifp->if_softc; 1087 uint32_t reg_icr; 1088 1089 EM_LOCK(sc); 1090 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1091 EM_UNLOCK(sc); 1092 return; 1093 } 1094 1095 if (cmd == POLL_AND_CHECK_STATUS) { 1096 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1097 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1098 callout_stop(&sc->timer); 1099 sc->hw.get_link_status = 1; 1100 em_check_for_link(&sc->hw); 1101 em_update_link_status(sc); 1102 callout_reset(&sc->timer, hz, em_local_timer, sc); 1103 } 1104 } 1105 em_rxeof(sc, count); 1106 em_txeof(sc); 1107 1108 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1109 em_start_locked(ifp); 1110 EM_UNLOCK(sc); 1111} 1112 1113/********************************************************************* 1114 * 1115 * Legacy Interrupt Service routine 1116 * 1117 *********************************************************************/ 1118static void 1119em_intr(void *arg) 1120{ 1121 struct em_softc *sc = arg; 1122 struct ifnet *ifp; 1123 uint32_t reg_icr; 1124 1125 EM_LOCK(sc); 1126 1127 ifp = sc->ifp; 1128 1129 if (ifp->if_capenable & IFCAP_POLLING) { 1130 EM_UNLOCK(sc); 1131 return; 1132 } 1133 1134 for (;;) { 1135 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1136 if (sc->hw.mac_type >= em_82571 && 1137 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1138 break; 1139 else if (reg_icr == 0) 1140 break; 1141 1142 /* 1143 * XXX: some laptops trigger several spurious interrupts 1144 * on em(4) when in the resume cycle. The ICR register 1145 * reports all-ones value in this case. Processing such 1146 * interrupts would lead to a freeze. I don't know why. 1147 */ 1148 if (reg_icr == 0xffffffff) 1149 break; 1150 1151 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1152 em_rxeof(sc, -1); 1153 em_txeof(sc); 1154 } 1155 1156 /* Link status change */ 1157 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1158 callout_stop(&sc->timer); 1159 sc->hw.get_link_status = 1; 1160 em_check_for_link(&sc->hw); 1161 em_update_link_status(sc); 1162 callout_reset(&sc->timer, hz, em_local_timer, sc); 1163 } 1164 1165 if (reg_icr & E1000_ICR_RXO) 1166 sc->rx_overruns++; 1167 } 1168 1169 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1170 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1171 em_start_locked(ifp); 1172 1173 EM_UNLOCK(sc); 1174} 1175 1176#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1177 1178static void 1179em_handle_link(void *context, int pending) 1180{ 1181 struct em_softc *sc = context; 1182 struct ifnet *ifp; 1183 1184 ifp = sc->ifp; 1185 1186 EM_LOCK(sc); 1187 1188 callout_stop(&sc->timer); 1189 sc->hw.get_link_status = 1; 1190 em_check_for_link(&sc->hw); 1191 em_update_link_status(sc); 1192 callout_reset(&sc->timer, hz, em_local_timer, sc); 1193 EM_UNLOCK(sc); 1194} 1195 1196static void 1197em_handle_rxtx(void *context, int pending) 1198{ 1199 struct em_softc *sc = context; 1200 struct ifnet *ifp; 1201 1202 NET_LOCK_GIANT(); 1203 ifp = sc->ifp; 1204 1205 /* 1206 * TODO: 1207 * It should be possible to run the tx clean loop without the lock. 1208 */ 1209 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1210 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1211 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1212 EM_LOCK(sc); 1213 em_txeof(sc); 1214 1215 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1216 em_start_locked(ifp); 1217 EM_UNLOCK(sc); 1218 } 1219 1220 em_enable_intr(sc); 1221 NET_UNLOCK_GIANT(); 1222} 1223 1224/********************************************************************* 1225 * 1226 * Fast Interrupt Service routine 1227 * 1228 *********************************************************************/ 1229static void 1230em_intr_fast(void *arg) 1231{ 1232 struct em_softc *sc = arg; 1233 struct ifnet *ifp; 1234 uint32_t reg_icr; 1235 1236 ifp = sc->ifp; 1237 1238 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1239 1240 /* Hot eject? */ 1241 if (reg_icr == 0xffffffff) 1242 return; 1243 1244 /* Definitely not our interrupt. */ 1245 if (reg_icr == 0x0) 1246 return; 1247 1248 /* 1249 * Starting with the 82571 chip, bit 31 should be used to 1250 * determine whether the interrupt belongs to us. 1251 */ 1252 if (sc->hw.mac_type >= em_82571 && 1253 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1254 return; 1255 1256 /* 1257 * Mask interrupts until the taskqueue is finished running. This is 1258 * cheap, just assume that it is needed. This also works around the 1259 * MSI message reordering errata on certain systems. 1260 */ 1261 em_disable_intr(sc); 1262 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1263 1264 /* Link status change */ 1265 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1266 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1267 1268 if (reg_icr & E1000_ICR_RXO) 1269 sc->rx_overruns++; 1270} 1271#endif /* ! DEVICE_POLLING */ 1272 1273/********************************************************************* 1274 * 1275 * Media Ioctl callback 1276 * 1277 * This routine is called whenever the user queries the status of 1278 * the interface using ifconfig. 1279 * 1280 **********************************************************************/ 1281static void 1282em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1283{ 1284 struct em_softc *sc = ifp->if_softc; 1285 1286 INIT_DEBUGOUT("em_media_status: begin"); 1287 1288 em_check_for_link(&sc->hw); 1289 em_update_link_status(sc); 1290 1291 ifmr->ifm_status = IFM_AVALID; 1292 ifmr->ifm_active = IFM_ETHER; 1293 1294 if (!sc->link_active) 1295 return; 1296 1297 ifmr->ifm_status |= IFM_ACTIVE; 1298 1299 if (sc->hw.media_type == em_media_type_fiber) { 1300 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1301 } else { 1302 switch (sc->link_speed) { 1303 case 10: 1304 ifmr->ifm_active |= IFM_10_T; 1305 break; 1306 case 100: 1307 ifmr->ifm_active |= IFM_100_TX; 1308 break; 1309 case 1000: 1310 ifmr->ifm_active |= IFM_1000_T; 1311 break; 1312 } 1313 if (sc->link_duplex == FULL_DUPLEX) 1314 ifmr->ifm_active |= IFM_FDX; 1315 else 1316 ifmr->ifm_active |= IFM_HDX; 1317 } 1318} 1319 1320/********************************************************************* 1321 * 1322 * Media Ioctl callback 1323 * 1324 * This routine is called when the user changes speed/duplex using 1325 * media/mediopt option with ifconfig. 1326 * 1327 **********************************************************************/ 1328static int 1329em_media_change(struct ifnet *ifp) 1330{ 1331 struct em_softc *sc = ifp->if_softc; 1332 struct ifmedia *ifm = &sc->media; 1333 1334 INIT_DEBUGOUT("em_media_change: begin"); 1335 1336 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1337 return (EINVAL); 1338 1339 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1340 case IFM_AUTO: 1341 sc->hw.autoneg = DO_AUTO_NEG; 1342 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1343 break; 1344 case IFM_1000_SX: 1345 case IFM_1000_T: 1346 sc->hw.autoneg = DO_AUTO_NEG; 1347 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1348 break; 1349 case IFM_100_TX: 1350 sc->hw.autoneg = FALSE; 1351 sc->hw.autoneg_advertised = 0; 1352 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1353 sc->hw.forced_speed_duplex = em_100_full; 1354 else 1355 sc->hw.forced_speed_duplex = em_100_half; 1356 break; 1357 case IFM_10_T: 1358 sc->hw.autoneg = FALSE; 1359 sc->hw.autoneg_advertised = 0; 1360 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1361 sc->hw.forced_speed_duplex = em_10_full; 1362 else 1363 sc->hw.forced_speed_duplex = em_10_half; 1364 break; 1365 default: 1366 device_printf(sc->dev, "Unsupported media type\n"); 1367 } 1368 1369 /* As the speed/duplex settings my have changed we need to 1370 * reset the PHY. 1371 */ 1372 sc->hw.phy_reset_disable = FALSE; 1373 1374 em_init(sc); 1375 1376 return (0); 1377} 1378 1379/********************************************************************* 1380 * 1381 * This routine maps the mbufs to tx descriptors. 1382 * 1383 * return 0 on success, positive on failure 1384 **********************************************************************/ 1385static int 1386em_encap(struct em_softc *sc, struct mbuf **m_headp) 1387{ 1388 struct ifnet *ifp = sc->ifp; 1389 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1390 bus_dmamap_t map; 1391 struct em_buffer *tx_buffer, *tx_buffer_last; 1392 struct em_tx_desc *current_tx_desc; 1393 struct mbuf *m_head; 1394 struct m_tag *mtag; 1395 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1396 int nsegs, i, j; 1397 int error; 1398 1399 m_head = *m_headp; 1400 current_tx_desc = NULL; 1401 txd_used = txd_saved = 0; 1402 1403 /* 1404 * Force a cleanup if number of TX descriptors 1405 * available hits the threshold. 1406 */ 1407 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1408 em_txeof(sc); 1409 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1410 sc->no_tx_desc_avail1++; 1411 return (ENOBUFS); 1412 } 1413 } 1414 1415 /* 1416 * Map the packet for DMA. 1417 */ 1418 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1419 tx_buffer_last = tx_buffer; 1420 map = tx_buffer->map; 1421 error = bus_dmamap_load_mbuf_sg(sc->txtag, map, m_head, segs, &nsegs, 1422 BUS_DMA_NOWAIT); 1423 if (error != 0) { 1424 sc->no_tx_dma_setup++; 1425 return (error); 1426 } 1427 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1428 1429 if (nsegs > sc->num_tx_desc_avail) { 1430 sc->no_tx_desc_avail2++; 1431 error = ENOBUFS; 1432 goto encap_fail; 1433 } 1434 1435 if (ifp->if_hwassist > 0) 1436 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1437 else 1438 txd_upper = txd_lower = 0; 1439 1440 /* Find out if we are in vlan mode. */ 1441 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1442 1443 /* 1444 * When operating in promiscuous mode, hardware encapsulation for 1445 * packets is disabled. This means we have to add the vlan 1446 * encapsulation in the driver, since it will have come down from the 1447 * VLAN layer with a tag instead of a VLAN header. 1448 */ 1449 if (mtag != NULL && sc->em_insert_vlan_header) { 1450 struct ether_vlan_header *evl; 1451 struct ether_header eh; 1452 1453 m_head = m_pullup(m_head, sizeof(eh)); 1454 if (m_head == NULL) { 1455 *m_headp = NULL; 1456 error = ENOBUFS; 1457 goto encap_fail; 1458 } 1459 eh = *mtod(m_head, struct ether_header *); 1460 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1461 if (m_head == NULL) { 1462 *m_headp = NULL; 1463 error = ENOBUFS; 1464 goto encap_fail; 1465 } 1466 m_head = m_pullup(m_head, sizeof(*evl)); 1467 if (m_head == NULL) { 1468 *m_headp = NULL; 1469 error = ENOBUFS; 1470 goto encap_fail; 1471 } 1472 evl = mtod(m_head, struct ether_vlan_header *); 1473 bcopy(&eh, evl, sizeof(*evl)); 1474 evl->evl_proto = evl->evl_encap_proto; 1475 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1476 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1477 m_tag_delete(m_head, mtag); 1478 mtag = NULL; 1479 *m_headp = m_head; 1480 } 1481 1482 i = sc->next_avail_tx_desc; 1483 if (sc->pcix_82544) { 1484 txd_saved = i; 1485 txd_used = 0; 1486 } 1487 for (j = 0; j < nsegs; j++) { 1488 /* If adapter is 82544 and on PCIX bus. */ 1489 if(sc->pcix_82544) { 1490 DESC_ARRAY desc_array; 1491 uint32_t array_elements, counter; 1492 1493 /* 1494 * Check the Address and Length combination and 1495 * split the data accordingly 1496 */ 1497 array_elements = em_fill_descriptors(segs[j].ds_addr, 1498 segs[j].ds_len, &desc_array); 1499 for (counter = 0; counter < array_elements; counter++) { 1500 if (txd_used == sc->num_tx_desc_avail) { 1501 sc->next_avail_tx_desc = txd_saved; 1502 sc->no_tx_desc_avail2++; 1503 error = ENOBUFS; 1504 goto encap_fail; 1505 } 1506 tx_buffer = &sc->tx_buffer_area[i]; 1507 current_tx_desc = &sc->tx_desc_base[i]; 1508 current_tx_desc->buffer_addr = htole64( 1509 desc_array.descriptor[counter].address); 1510 current_tx_desc->lower.data = htole32( 1511 (sc->txd_cmd | txd_lower | 1512 (uint16_t)desc_array.descriptor[counter].length)); 1513 current_tx_desc->upper.data = htole32((txd_upper)); 1514 if (++i == sc->num_tx_desc) 1515 i = 0; 1516 1517 tx_buffer->m_head = NULL; 1518 txd_used++; 1519 } 1520 } else { 1521 tx_buffer = &sc->tx_buffer_area[i]; 1522 current_tx_desc = &sc->tx_desc_base[i]; 1523 1524 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1525 current_tx_desc->lower.data = htole32( 1526 sc->txd_cmd | txd_lower | segs[j].ds_len); 1527 current_tx_desc->upper.data = htole32(txd_upper); 1528 1529 if (++i == sc->num_tx_desc) 1530 i = 0; 1531 1532 tx_buffer->m_head = NULL; 1533 } 1534 } 1535 1536 sc->next_avail_tx_desc = i; 1537 if (sc->pcix_82544) 1538 sc->num_tx_desc_avail -= txd_used; 1539 else 1540 sc->num_tx_desc_avail -= nsegs; 1541 1542 if (mtag != NULL) { 1543 /* Set the vlan id. */ 1544 current_tx_desc->upper.fields.special = 1545 htole16(VLAN_TAG_VALUE(mtag)); 1546 1547 /* Tell hardware to add tag. */ 1548 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1549 } 1550 1551 tx_buffer->m_head = m_head; 1552 tx_buffer_last->map = tx_buffer->map; 1553 tx_buffer->map = map; 1554 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1555 1556 /* 1557 * Last Descriptor of Packet needs End Of Packet (EOP). 1558 */ 1559 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1560 1561 /* 1562 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1563 * that this frame is available to transmit. 1564 */ 1565 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1566 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1567 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1568 em_82547_move_tail_locked(sc); 1569 else { 1570 E1000_WRITE_REG(&sc->hw, TDT, i); 1571 if (sc->hw.mac_type == em_82547) 1572 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1573 } 1574 1575 return (0); 1576 1577encap_fail: 1578 bus_dmamap_unload(sc->txtag, map); 1579 return (error); 1580} 1581 1582/********************************************************************* 1583 * 1584 * 82547 workaround to avoid controller hang in half-duplex environment. 1585 * The workaround is to avoid queuing a large packet that would span 1586 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1587 * in this case. We do that only when FIFO is quiescent. 1588 * 1589 **********************************************************************/ 1590static void 1591em_82547_move_tail_locked(struct em_softc *sc) 1592{ 1593 uint16_t hw_tdt; 1594 uint16_t sw_tdt; 1595 struct em_tx_desc *tx_desc; 1596 uint16_t length = 0; 1597 boolean_t eop = 0; 1598 1599 EM_LOCK_ASSERT(sc); 1600 1601 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1602 sw_tdt = sc->next_avail_tx_desc; 1603 1604 while (hw_tdt != sw_tdt) { 1605 tx_desc = &sc->tx_desc_base[hw_tdt]; 1606 length += tx_desc->lower.flags.length; 1607 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1608 if(++hw_tdt == sc->num_tx_desc) 1609 hw_tdt = 0; 1610 1611 if (eop) { 1612 if (em_82547_fifo_workaround(sc, length)) { 1613 sc->tx_fifo_wrk_cnt++; 1614 callout_reset(&sc->tx_fifo_timer, 1, 1615 em_82547_move_tail, sc); 1616 break; 1617 } 1618 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1619 em_82547_update_fifo_head(sc, length); 1620 length = 0; 1621 } 1622 } 1623} 1624 1625static void 1626em_82547_move_tail(void *arg) 1627{ 1628 struct em_softc *sc = arg; 1629 1630 EM_LOCK(sc); 1631 em_82547_move_tail_locked(sc); 1632 EM_UNLOCK(sc); 1633} 1634 1635static int 1636em_82547_fifo_workaround(struct em_softc *sc, int len) 1637{ 1638 int fifo_space, fifo_pkt_len; 1639 1640 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1641 1642 if (sc->link_duplex == HALF_DUPLEX) { 1643 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1644 1645 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1646 if (em_82547_tx_fifo_reset(sc)) 1647 return (0); 1648 else 1649 return (1); 1650 } 1651 } 1652 1653 return (0); 1654} 1655 1656static void 1657em_82547_update_fifo_head(struct em_softc *sc, int len) 1658{ 1659 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1660 1661 /* tx_fifo_head is always 16 byte aligned */ 1662 sc->tx_fifo_head += fifo_pkt_len; 1663 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1664 sc->tx_fifo_head -= sc->tx_fifo_size; 1665 } 1666} 1667 1668 1669static int 1670em_82547_tx_fifo_reset(struct em_softc *sc) 1671{ 1672 uint32_t tctl; 1673 1674 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1675 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1676 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1677 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1678 1679 /* Disable TX unit */ 1680 tctl = E1000_READ_REG(&sc->hw, TCTL); 1681 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1682 1683 /* Reset FIFO pointers */ 1684 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1685 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1686 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1687 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1688 1689 /* Re-enable TX unit */ 1690 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1691 E1000_WRITE_FLUSH(&sc->hw); 1692 1693 sc->tx_fifo_head = 0; 1694 sc->tx_fifo_reset_cnt++; 1695 1696 return (TRUE); 1697 } 1698 else { 1699 return (FALSE); 1700 } 1701} 1702 1703static void 1704em_set_promisc(struct em_softc *sc) 1705{ 1706 struct ifnet *ifp = sc->ifp; 1707 uint32_t reg_rctl; 1708 1709 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1710 1711 if (ifp->if_flags & IFF_PROMISC) { 1712 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1713 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1714 /* Disable VLAN stripping in promiscous mode 1715 * This enables bridging of vlan tagged frames to occur 1716 * and also allows vlan tags to be seen in tcpdump 1717 */ 1718 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1719 em_disable_vlans(sc); 1720 sc->em_insert_vlan_header = 1; 1721 } else if (ifp->if_flags & IFF_ALLMULTI) { 1722 reg_rctl |= E1000_RCTL_MPE; 1723 reg_rctl &= ~E1000_RCTL_UPE; 1724 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1725 sc->em_insert_vlan_header = 0; 1726 } else 1727 sc->em_insert_vlan_header = 0; 1728} 1729 1730static void 1731em_disable_promisc(struct em_softc *sc) 1732{ 1733 struct ifnet *ifp = sc->ifp; 1734 uint32_t reg_rctl; 1735 1736 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1737 1738 reg_rctl &= (~E1000_RCTL_UPE); 1739 reg_rctl &= (~E1000_RCTL_MPE); 1740 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1741 1742 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1743 em_enable_vlans(sc); 1744 sc->em_insert_vlan_header = 0; 1745} 1746 1747 1748/********************************************************************* 1749 * Multicast Update 1750 * 1751 * This routine is called whenever multicast address list is updated. 1752 * 1753 **********************************************************************/ 1754 1755static void 1756em_set_multi(struct em_softc *sc) 1757{ 1758 struct ifnet *ifp = sc->ifp; 1759 struct ifmultiaddr *ifma; 1760 uint32_t reg_rctl = 0; 1761 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1762 int mcnt = 0; 1763 1764 IOCTL_DEBUGOUT("em_set_multi: begin"); 1765 1766 if (sc->hw.mac_type == em_82542_rev2_0) { 1767 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1768 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1769 em_pci_clear_mwi(&sc->hw); 1770 reg_rctl |= E1000_RCTL_RST; 1771 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1772 msec_delay(5); 1773 } 1774 1775 IF_ADDR_LOCK(ifp); 1776 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1777 if (ifma->ifma_addr->sa_family != AF_LINK) 1778 continue; 1779 1780 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1781 break; 1782 1783 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1784 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1785 mcnt++; 1786 } 1787 IF_ADDR_UNLOCK(ifp); 1788 1789 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1790 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1791 reg_rctl |= E1000_RCTL_MPE; 1792 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1793 } else 1794 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1795 1796 if (sc->hw.mac_type == em_82542_rev2_0) { 1797 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1798 reg_rctl &= ~E1000_RCTL_RST; 1799 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1800 msec_delay(5); 1801 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1802 em_pci_set_mwi(&sc->hw); 1803 } 1804} 1805 1806 1807/********************************************************************* 1808 * Timer routine 1809 * 1810 * This routine checks for link status and updates statistics. 1811 * 1812 **********************************************************************/ 1813 1814static void 1815em_local_timer(void *arg) 1816{ 1817 struct em_softc *sc = arg; 1818 struct ifnet *ifp = sc->ifp; 1819 1820 EM_LOCK(sc); 1821 1822 em_check_for_link(&sc->hw); 1823 em_update_link_status(sc); 1824 em_update_stats_counters(sc); 1825 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1826 em_print_hw_stats(sc); 1827 em_smartspeed(sc); 1828 1829 callout_reset(&sc->timer, hz, em_local_timer, sc); 1830 1831 EM_UNLOCK(sc); 1832} 1833 1834static void 1835em_update_link_status(struct em_softc *sc) 1836{ 1837 struct ifnet *ifp = sc->ifp; 1838 device_t dev = sc->dev; 1839 1840 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1841 if (sc->link_active == 0) { 1842 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1843 &sc->link_duplex); 1844 if (bootverbose) 1845 device_printf(dev, "Link is up %d Mbps %s\n", 1846 sc->link_speed, 1847 ((sc->link_duplex == FULL_DUPLEX) ? 1848 "Full Duplex" : "Half Duplex")); 1849 sc->link_active = 1; 1850 sc->smartspeed = 0; 1851 ifp->if_baudrate = sc->link_speed * 1000000; 1852 if_link_state_change(ifp, LINK_STATE_UP); 1853 } 1854 } else { 1855 if (sc->link_active == 1) { 1856 ifp->if_baudrate = sc->link_speed = 0; 1857 sc->link_duplex = 0; 1858 if (bootverbose) 1859 device_printf(dev, "Link is Down\n"); 1860 sc->link_active = 0; 1861 if_link_state_change(ifp, LINK_STATE_DOWN); 1862 } 1863 } 1864} 1865 1866/********************************************************************* 1867 * 1868 * This routine disables all traffic on the adapter by issuing a 1869 * global reset on the MAC and deallocates TX/RX buffers. 1870 * 1871 **********************************************************************/ 1872 1873static void 1874em_stop(void *arg) 1875{ 1876 struct em_softc *sc = arg; 1877 struct ifnet *ifp = sc->ifp; 1878 1879 EM_LOCK_ASSERT(sc); 1880 1881 INIT_DEBUGOUT("em_stop: begin"); 1882 1883 em_disable_intr(sc); 1884 em_reset_hw(&sc->hw); 1885 callout_stop(&sc->timer); 1886 callout_stop(&sc->tx_fifo_timer); 1887 em_free_transmit_structures(sc); 1888 em_free_receive_structures(sc); 1889 1890 /* Tell the stack that the interface is no longer active */ 1891 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1892} 1893 1894 1895/********************************************************************* 1896 * 1897 * Determine hardware revision. 1898 * 1899 **********************************************************************/ 1900static void 1901em_identify_hardware(struct em_softc *sc) 1902{ 1903 device_t dev = sc->dev; 1904 1905 /* Make sure our PCI config space has the necessary stuff set */ 1906 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1907 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1908 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1909 device_printf(dev, "Memory Access and/or Bus Master bits " 1910 "were not set!\n"); 1911 sc->hw.pci_cmd_word |= 1912 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1913 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1914 } 1915 1916 /* Save off the information about this board */ 1917 sc->hw.vendor_id = pci_get_vendor(dev); 1918 sc->hw.device_id = pci_get_device(dev); 1919 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1920 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1921 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1922 1923 /* Identify the MAC */ 1924 if (em_set_mac_type(&sc->hw)) 1925 device_printf(dev, "Unknown MAC Type\n"); 1926 1927 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1928 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1929 sc->hw.phy_init_script = TRUE; 1930} 1931 1932static int 1933em_allocate_pci_resources(struct em_softc *sc) 1934{ 1935 device_t dev = sc->dev; 1936 int val, rid; 1937 1938 rid = PCIR_BAR(0); 1939 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1940 &rid, RF_ACTIVE); 1941 if (sc->res_memory == NULL) { 1942 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1943 return (ENXIO); 1944 } 1945 sc->osdep.mem_bus_space_tag = 1946 rman_get_bustag(sc->res_memory); 1947 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1948 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1949 1950 if (sc->hw.mac_type > em_82543) { 1951 /* Figure our where our IO BAR is ? */ 1952 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1953 val = pci_read_config(dev, rid, 4); 1954 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1955 sc->io_rid = rid; 1956 break; 1957 } 1958 rid += 4; 1959 /* check for 64bit BAR */ 1960 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1961 rid += 4; 1962 } 1963 if (rid >= PCIR_CIS) { 1964 device_printf(dev, "Unable to locate IO BAR\n"); 1965 return (ENXIO); 1966 } 1967 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1968 &sc->io_rid, RF_ACTIVE); 1969 if (sc->res_ioport == NULL) { 1970 device_printf(dev, "Unable to allocate bus resource: " 1971 "ioport\n"); 1972 return (ENXIO); 1973 } 1974 sc->hw.io_base = 0; 1975 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1976 sc->osdep.io_bus_space_handle = 1977 rman_get_bushandle(sc->res_ioport); 1978 } 1979 1980 rid = 0x0; 1981 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1982 RF_SHAREABLE | RF_ACTIVE); 1983 if (sc->res_interrupt == NULL) { 1984 device_printf(dev, "Unable to allocate bus resource: " 1985 "interrupt\n"); 1986 return (ENXIO); 1987 } 1988 1989 sc->hw.back = &sc->osdep; 1990 1991 return (0); 1992} 1993 1994int 1995em_allocate_intr(struct em_softc *sc) 1996{ 1997 device_t dev = sc->dev; 1998 int error; 1999 2000 /* Manually turn off all interrupts */ 2001 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2002 2003#ifdef DEVICE_POLLING 2004 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 2005 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 2006 &sc->int_handler_tag)) != 0) { 2007 device_printf(dev, "Failed to register interrupt handler"); 2008 return (error); 2009 } 2010#else 2011 /* 2012 * Try allocating a fast interrupt and the associated deferred 2013 * processing contexts. 2014 */ 2015 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 2016 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 2017 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2018 taskqueue_thread_enqueue, &sc->tq); 2019 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 2020 device_get_nameunit(sc->dev)); 2021 if ((error = bus_setup_intr(dev, sc->res_interrupt, 2022 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 2023 &sc->int_handler_tag)) != 0) { 2024 device_printf(dev, "Failed to register fast interrupt " 2025 "handler: %d\n", error); 2026 taskqueue_free(sc->tq); 2027 sc->tq = NULL; 2028 return (error); 2029 } 2030#endif 2031 2032 em_enable_intr(sc); 2033 return (0); 2034} 2035 2036static void 2037em_free_intr(struct em_softc *sc) 2038{ 2039 device_t dev = sc->dev; 2040 2041 if (sc->res_interrupt != NULL) { 2042 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2043 sc->int_handler_tag = NULL; 2044 } 2045 if (sc->tq != NULL) { 2046 taskqueue_drain(sc->tq, &sc->rxtx_task); 2047 taskqueue_drain(taskqueue_fast, &sc->link_task); 2048 taskqueue_free(sc->tq); 2049 sc->tq = NULL; 2050 } 2051} 2052 2053static void 2054em_free_pci_resources(struct em_softc *sc) 2055{ 2056 device_t dev = sc->dev; 2057 2058 if (sc->res_interrupt != NULL) 2059 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2060 2061 if (sc->res_memory != NULL) 2062 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2063 sc->res_memory); 2064 2065 if (sc->res_ioport != NULL) 2066 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2067 sc->res_ioport); 2068} 2069 2070/********************************************************************* 2071 * 2072 * Initialize the hardware to a configuration as specified by the 2073 * adapter structure. The controller is reset, the EEPROM is 2074 * verified, the MAC address is set, then the shared initialization 2075 * routines are called. 2076 * 2077 **********************************************************************/ 2078static int 2079em_hardware_init(struct em_softc *sc) 2080{ 2081 device_t dev = sc->dev; 2082 uint16_t rx_buffer_size; 2083 2084 INIT_DEBUGOUT("em_hardware_init: begin"); 2085 /* Issue a global reset */ 2086 em_reset_hw(&sc->hw); 2087 2088 /* When hardware is reset, fifo_head is also reset */ 2089 sc->tx_fifo_head = 0; 2090 2091 /* Make sure we have a good EEPROM before we read from it */ 2092 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2093 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2094 return (EIO); 2095 } 2096 2097 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2098 device_printf(dev, "EEPROM read error while reading part " 2099 "number\n"); 2100 return (EIO); 2101 } 2102 2103 /* 2104 * These parameters control the automatic generation (Tx) and 2105 * response (Rx) to Ethernet PAUSE frames. 2106 * - High water mark should allow for at least two frames to be 2107 * received after sending an XOFF. 2108 * - Low water mark works best when it is very near the high water mark. 2109 * This allows the receiver to restart by sending XON when it has 2110 * drained a bit. Here we use an arbitary value of 1500 which will 2111 * restart after one full frame is pulled from the buffer. There 2112 * could be several smaller frames in the buffer and if so they will 2113 * not trigger the XON until their total number reduces the buffer 2114 * by 1500. 2115 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2116 */ 2117 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2118 2119 sc->hw.fc_high_water = rx_buffer_size - 2120 roundup2(sc->hw.max_frame_size, 1024); 2121 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2122 if (sc->hw.mac_type == em_80003es2lan) 2123 sc->hw.fc_pause_time = 0xFFFF; 2124 else 2125 sc->hw.fc_pause_time = 0x1000; 2126 sc->hw.fc_send_xon = TRUE; 2127 sc->hw.fc = em_fc_full; 2128 2129 if (em_init_hw(&sc->hw) < 0) { 2130 device_printf(dev, "Hardware Initialization Failed"); 2131 return (EIO); 2132 } 2133 2134 em_check_for_link(&sc->hw); 2135 2136 return (0); 2137} 2138 2139/********************************************************************* 2140 * 2141 * Setup networking device structure and register an interface. 2142 * 2143 **********************************************************************/ 2144static void 2145em_setup_interface(device_t dev, struct em_softc *sc) 2146{ 2147 struct ifnet *ifp; 2148 INIT_DEBUGOUT("em_setup_interface: begin"); 2149 2150 ifp = sc->ifp = if_alloc(IFT_ETHER); 2151 if (ifp == NULL) 2152 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2153 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2154 ifp->if_mtu = ETHERMTU; 2155 ifp->if_init = em_init; 2156 ifp->if_softc = sc; 2157 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2158 ifp->if_ioctl = em_ioctl; 2159 ifp->if_start = em_start; 2160 ifp->if_watchdog = em_watchdog; 2161 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2162 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2163 IFQ_SET_READY(&ifp->if_snd); 2164 2165 ether_ifattach(ifp, sc->hw.mac_addr); 2166 2167 ifp->if_capabilities = ifp->if_capenable = 0; 2168 2169 if (sc->hw.mac_type >= em_82543) { 2170 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2171 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2172 } 2173 2174 /* 2175 * Tell the upper layer(s) we support long frames. 2176 */ 2177 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2178 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2179 ifp->if_capenable |= IFCAP_VLAN_MTU; 2180 2181#ifdef DEVICE_POLLING 2182 ifp->if_capabilities |= IFCAP_POLLING; 2183#endif 2184 2185 /* 2186 * Specify the media types supported by this adapter and register 2187 * callbacks to update media and link information 2188 */ 2189 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2190 if (sc->hw.media_type == em_media_type_fiber) { 2191 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2192 0, NULL); 2193 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2194 0, NULL); 2195 } else { 2196 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2197 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2198 0, NULL); 2199 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2200 0, NULL); 2201 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2202 0, NULL); 2203 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2204 0, NULL); 2205 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2206 } 2207 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2208 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2209} 2210 2211 2212/********************************************************************* 2213 * 2214 * Workaround for SmartSpeed on 82541 and 82547 controllers 2215 * 2216 **********************************************************************/ 2217static void 2218em_smartspeed(struct em_softc *sc) 2219{ 2220 uint16_t phy_tmp; 2221 2222 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2223 sc->hw.autoneg == 0 || 2224 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2225 return; 2226 2227 if (sc->smartspeed == 0) { 2228 /* If Master/Slave config fault is asserted twice, 2229 * we assume back-to-back */ 2230 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2231 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2232 return; 2233 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2234 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2235 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2236 if(phy_tmp & CR_1000T_MS_ENABLE) { 2237 phy_tmp &= ~CR_1000T_MS_ENABLE; 2238 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2239 phy_tmp); 2240 sc->smartspeed++; 2241 if(sc->hw.autoneg && 2242 !em_phy_setup_autoneg(&sc->hw) && 2243 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2244 &phy_tmp)) { 2245 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2246 MII_CR_RESTART_AUTO_NEG); 2247 em_write_phy_reg(&sc->hw, PHY_CTRL, 2248 phy_tmp); 2249 } 2250 } 2251 } 2252 return; 2253 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2254 /* If still no link, perhaps using 2/3 pair cable */ 2255 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2256 phy_tmp |= CR_1000T_MS_ENABLE; 2257 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2258 if(sc->hw.autoneg && 2259 !em_phy_setup_autoneg(&sc->hw) && 2260 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2261 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2262 MII_CR_RESTART_AUTO_NEG); 2263 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2264 } 2265 } 2266 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2267 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2268 sc->smartspeed = 0; 2269} 2270 2271 2272/* 2273 * Manage DMA'able memory. 2274 */ 2275static void 2276em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2277{ 2278 if (error) 2279 return; 2280 *(bus_addr_t *) arg = segs[0].ds_addr; 2281} 2282 2283static int 2284em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2285 int mapflags) 2286{ 2287 int error; 2288 2289 error = bus_dma_tag_create(NULL, /* parent */ 2290 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2291 BUS_SPACE_MAXADDR, /* lowaddr */ 2292 BUS_SPACE_MAXADDR, /* highaddr */ 2293 NULL, NULL, /* filter, filterarg */ 2294 size, /* maxsize */ 2295 1, /* nsegments */ 2296 size, /* maxsegsize */ 2297 0, /* flags */ 2298 NULL, /* lockfunc */ 2299 NULL, /* lockarg */ 2300 &dma->dma_tag); 2301 if (error) { 2302 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2303 __func__, error); 2304 goto fail_0; 2305 } 2306 2307 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2308 BUS_DMA_NOWAIT, &dma->dma_map); 2309 if (error) { 2310 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2311 __func__, (uintmax_t)size, error); 2312 goto fail_2; 2313 } 2314 2315 dma->dma_paddr = 0; 2316 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2317 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2318 if (error || dma->dma_paddr == 0) { 2319 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2320 __func__, error); 2321 goto fail_3; 2322 } 2323 2324 return (0); 2325 2326fail_3: 2327 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2328fail_2: 2329 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2330 bus_dma_tag_destroy(dma->dma_tag); 2331fail_0: 2332 dma->dma_map = NULL; 2333 dma->dma_tag = NULL; 2334 2335 return (error); 2336} 2337 2338static void 2339em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2340{ 2341 if (dma->dma_tag == NULL) 2342 return; 2343 if (dma->dma_map != NULL) { 2344 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2345 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2346 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2347 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2348 dma->dma_map = NULL; 2349 } 2350 bus_dma_tag_destroy(dma->dma_tag); 2351 dma->dma_tag = NULL; 2352} 2353 2354 2355/********************************************************************* 2356 * 2357 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2358 * the information needed to transmit a packet on the wire. 2359 * 2360 **********************************************************************/ 2361static int 2362em_allocate_transmit_structures(struct em_softc *sc) 2363{ 2364 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2365 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2366 if (sc->tx_buffer_area == NULL) { 2367 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2368 return (ENOMEM); 2369 } 2370 2371 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2372 2373 return (0); 2374} 2375 2376/********************************************************************* 2377 * 2378 * Allocate and initialize transmit structures. 2379 * 2380 **********************************************************************/ 2381static int 2382em_setup_transmit_structures(struct em_softc *sc) 2383{ 2384 device_t dev = sc->dev; 2385 struct em_buffer *tx_buffer; 2386 bus_size_t size; 2387 int error, i; 2388 2389 /* 2390 * Setup DMA descriptor areas. 2391 */ 2392 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2393 if ((error = bus_dma_tag_create(NULL, /* parent */ 2394 1, 0, /* alignment, bounds */ 2395 BUS_SPACE_MAXADDR, /* lowaddr */ 2396 BUS_SPACE_MAXADDR, /* highaddr */ 2397 NULL, NULL, /* filter, filterarg */ 2398 size, /* maxsize */ 2399 EM_MAX_SCATTER, /* nsegments */ 2400 size, /* maxsegsize */ 2401 0, /* flags */ 2402 NULL, /* lockfunc */ 2403 NULL, /* lockarg */ 2404 &sc->txtag)) != 0) { 2405 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2406 goto fail; 2407 } 2408 2409 if ((error = em_allocate_transmit_structures(sc)) != 0) 2410 goto fail; 2411 2412 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2413 tx_buffer = sc->tx_buffer_area; 2414 for (i = 0; i < sc->num_tx_desc; i++) { 2415 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2416 if (error != 0) { 2417 device_printf(dev, "Unable to create TX DMA map\n"); 2418 goto fail; 2419 } 2420 tx_buffer++; 2421 } 2422 2423 sc->next_avail_tx_desc = 0; 2424 sc->oldest_used_tx_desc = 0; 2425 2426 /* Set number of descriptors available */ 2427 sc->num_tx_desc_avail = sc->num_tx_desc; 2428 2429 /* Set checksum context */ 2430 sc->active_checksum_context = OFFLOAD_NONE; 2431 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2432 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2433 2434 return (0); 2435 2436fail: 2437 em_free_transmit_structures(sc); 2438 return (error); 2439} 2440 2441/********************************************************************* 2442 * 2443 * Enable transmit unit. 2444 * 2445 **********************************************************************/ 2446static void 2447em_initialize_transmit_unit(struct em_softc *sc) 2448{ 2449 uint32_t reg_tctl, tarc; 2450 uint32_t reg_tipg = 0; 2451 uint64_t bus_addr; 2452 2453 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2454 /* Setup the Base and Length of the Tx Descriptor Ring */ 2455 bus_addr = sc->txdma.dma_paddr; 2456 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2457 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2458 E1000_WRITE_REG(&sc->hw, TDLEN, 2459 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2460 2461 /* Setup the HW Tx Head and Tail descriptor pointers */ 2462 E1000_WRITE_REG(&sc->hw, TDH, 0); 2463 E1000_WRITE_REG(&sc->hw, TDT, 0); 2464 2465 2466 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2467 E1000_READ_REG(&sc->hw, TDLEN)); 2468 2469 /* Set the default values for the Tx Inter Packet Gap timer */ 2470 switch (sc->hw.mac_type) { 2471 case em_82542_rev2_0: 2472 case em_82542_rev2_1: 2473 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2474 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2475 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2476 break; 2477 case em_80003es2lan: 2478 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2479 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2480 E1000_TIPG_IPGR2_SHIFT; 2481 break; 2482 default: 2483 if (sc->hw.media_type == em_media_type_fiber) 2484 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2485 else 2486 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2487 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2488 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2489 } 2490 2491 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2492 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2493 if(sc->hw.mac_type >= em_82540) 2494 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2495 2496 /* Program the Transmit Control Register */ 2497 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2498 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2499 if (sc->hw.mac_type >= em_82571) 2500 reg_tctl |= E1000_TCTL_MULR; 2501 if (sc->link_duplex == 1) { 2502 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2503 } else { 2504 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2505 } 2506 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2507 2508 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) { 2509 tarc = E1000_READ_REG(&sc->hw, TARC0); 2510 tarc |= ((1 << 25) | (1 << 21)); 2511 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2512 tarc = E1000_READ_REG(&sc->hw, TARC1); 2513 tarc |= (1 << 25); 2514 if (reg_tctl & E1000_TCTL_MULR) 2515 tarc &= ~(1 << 28); 2516 else 2517 tarc |= (1 << 28); 2518 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2519 } else if (sc->hw.mac_type == em_80003es2lan) { 2520 tarc = E1000_READ_REG(&sc->hw, TARC0); 2521 tarc |= 1; 2522 if (sc->hw.media_type == em_media_type_internal_serdes) 2523 tarc |= (1 << 20); 2524 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2525 tarc = E1000_READ_REG(&sc->hw, TARC1); 2526 tarc |= 1; 2527 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2528 } 2529 2530 /* Setup Transmit Descriptor Settings for this adapter */ 2531 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2532 2533 if (sc->tx_int_delay.value > 0) 2534 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2535} 2536 2537/********************************************************************* 2538 * 2539 * Free all transmit related data structures. 2540 * 2541 **********************************************************************/ 2542static void 2543em_free_transmit_structures(struct em_softc *sc) 2544{ 2545 struct em_buffer *tx_buffer; 2546 int i; 2547 2548 INIT_DEBUGOUT("free_transmit_structures: begin"); 2549 2550 if (sc->tx_buffer_area != NULL) { 2551 tx_buffer = sc->tx_buffer_area; 2552 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2553 if (tx_buffer->m_head != NULL) { 2554 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2555 BUS_DMASYNC_POSTWRITE); 2556 bus_dmamap_unload(sc->txtag, 2557 tx_buffer->map); 2558 m_freem(tx_buffer->m_head); 2559 tx_buffer->m_head = NULL; 2560 } else if (tx_buffer->map != NULL) 2561 bus_dmamap_unload(sc->txtag, 2562 tx_buffer->map); 2563 if (tx_buffer->map != NULL) { 2564 bus_dmamap_destroy(sc->txtag, 2565 tx_buffer->map); 2566 tx_buffer->map = NULL; 2567 } 2568 } 2569 } 2570 if (sc->tx_buffer_area != NULL) { 2571 free(sc->tx_buffer_area, M_DEVBUF); 2572 sc->tx_buffer_area = NULL; 2573 } 2574 if (sc->txtag != NULL) { 2575 bus_dma_tag_destroy(sc->txtag); 2576 sc->txtag = NULL; 2577 } 2578} 2579 2580/********************************************************************* 2581 * 2582 * The offload context needs to be set when we transfer the first 2583 * packet of a particular protocol (TCP/UDP). We change the 2584 * context only if the protocol type changes. 2585 * 2586 **********************************************************************/ 2587static void 2588em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2589 uint32_t *txd_upper, uint32_t *txd_lower) 2590{ 2591 struct em_context_desc *TXD; 2592 struct em_buffer *tx_buffer; 2593 int curr_txd; 2594 2595 if (mp->m_pkthdr.csum_flags) { 2596 2597 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2598 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2599 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2600 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2601 return; 2602 else 2603 sc->active_checksum_context = OFFLOAD_TCP_IP; 2604 2605 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2606 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2607 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2608 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2609 return; 2610 else 2611 sc->active_checksum_context = OFFLOAD_UDP_IP; 2612 } else { 2613 *txd_upper = 0; 2614 *txd_lower = 0; 2615 return; 2616 } 2617 } else { 2618 *txd_upper = 0; 2619 *txd_lower = 0; 2620 return; 2621 } 2622 2623 /* If we reach this point, the checksum offload context 2624 * needs to be reset. 2625 */ 2626 curr_txd = sc->next_avail_tx_desc; 2627 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2628 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2629 2630 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2631 TXD->lower_setup.ip_fields.ipcso = 2632 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2633 TXD->lower_setup.ip_fields.ipcse = 2634 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2635 2636 TXD->upper_setup.tcp_fields.tucss = 2637 ETHER_HDR_LEN + sizeof(struct ip); 2638 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2639 2640 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2641 TXD->upper_setup.tcp_fields.tucso = 2642 ETHER_HDR_LEN + sizeof(struct ip) + 2643 offsetof(struct tcphdr, th_sum); 2644 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2645 TXD->upper_setup.tcp_fields.tucso = 2646 ETHER_HDR_LEN + sizeof(struct ip) + 2647 offsetof(struct udphdr, uh_sum); 2648 } 2649 2650 TXD->tcp_seg_setup.data = htole32(0); 2651 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2652 2653 tx_buffer->m_head = NULL; 2654 2655 if (++curr_txd == sc->num_tx_desc) 2656 curr_txd = 0; 2657 2658 sc->num_tx_desc_avail--; 2659 sc->next_avail_tx_desc = curr_txd; 2660} 2661 2662/********************************************************************** 2663 * 2664 * Examine each tx_buffer in the used queue. If the hardware is done 2665 * processing the packet then free associated resources. The 2666 * tx_buffer is put back on the free queue. 2667 * 2668 **********************************************************************/ 2669static void 2670em_txeof(struct em_softc *sc) 2671{ 2672 int i, num_avail; 2673 struct em_buffer *tx_buffer; 2674 struct em_tx_desc *tx_desc; 2675 struct ifnet *ifp = sc->ifp; 2676 2677 EM_LOCK_ASSERT(sc); 2678 2679 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2680 return; 2681 2682 num_avail = sc->num_tx_desc_avail; 2683 i = sc->oldest_used_tx_desc; 2684 2685 tx_buffer = &sc->tx_buffer_area[i]; 2686 tx_desc = &sc->tx_desc_base[i]; 2687 2688 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2689 BUS_DMASYNC_POSTREAD); 2690 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2691 2692 tx_desc->upper.data = 0; 2693 num_avail++; 2694 2695 if (tx_buffer->m_head) { 2696 ifp->if_opackets++; 2697 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2698 BUS_DMASYNC_POSTWRITE); 2699 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2700 2701 m_freem(tx_buffer->m_head); 2702 tx_buffer->m_head = NULL; 2703 } 2704 2705 if (++i == sc->num_tx_desc) 2706 i = 0; 2707 2708 tx_buffer = &sc->tx_buffer_area[i]; 2709 tx_desc = &sc->tx_desc_base[i]; 2710 } 2711 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2713 2714 sc->oldest_used_tx_desc = i; 2715 2716 /* 2717 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2718 * that it is OK to send packets. 2719 * If there are no pending descriptors, clear the timeout. Otherwise, 2720 * if some descriptors have been freed, restart the timeout. 2721 */ 2722 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2723 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2724 if (num_avail == sc->num_tx_desc) 2725 ifp->if_timer = 0; 2726 else if (num_avail != sc->num_tx_desc_avail) 2727 ifp->if_timer = EM_TX_TIMEOUT; 2728 } 2729 sc->num_tx_desc_avail = num_avail; 2730} 2731 2732/********************************************************************* 2733 * 2734 * Get a buffer from system mbuf buffer pool. 2735 * 2736 **********************************************************************/ 2737static int 2738em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2739{ 2740 struct ifnet *ifp = sc->ifp; 2741 bus_dma_segment_t segs[1]; 2742 struct em_buffer *rx_buffer; 2743 int error, nsegs; 2744 2745 if (mp == NULL) { 2746 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2747 if (mp == NULL) { 2748 sc->mbuf_cluster_failed++; 2749 return (ENOBUFS); 2750 } 2751 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2752 } else { 2753 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2754 mp->m_data = mp->m_ext.ext_buf; 2755 mp->m_next = NULL; 2756 } 2757 2758 if (ifp->if_mtu <= ETHERMTU) 2759 m_adj(mp, ETHER_ALIGN); 2760 2761 rx_buffer = &sc->rx_buffer_area[i]; 2762 2763 /* 2764 * Using memory from the mbuf cluster pool, invoke the 2765 * bus_dma machinery to arrange the memory mapping. 2766 */ 2767 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2768 mp, segs, &nsegs, 0); 2769 if (error != 0) { 2770 m_free(mp); 2771 return (error); 2772 } 2773 /* If nsegs is wrong then the stack is corrupt. */ 2774 KASSERT(nsegs == 1, ("Too many segments returned!")); 2775 rx_buffer->m_head = mp; 2776 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2777 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2778 2779 return (0); 2780} 2781 2782/********************************************************************* 2783 * 2784 * Allocate memory for rx_buffer structures. Since we use one 2785 * rx_buffer per received packet, the maximum number of rx_buffer's 2786 * that we'll need is equal to the number of receive descriptors 2787 * that we've allocated. 2788 * 2789 **********************************************************************/ 2790static int 2791em_allocate_receive_structures(struct em_softc *sc) 2792{ 2793 device_t dev = sc->dev; 2794 struct em_buffer *rx_buffer; 2795 int i, error; 2796 2797 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2798 M_DEVBUF, M_NOWAIT); 2799 if (sc->rx_buffer_area == NULL) { 2800 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2801 return (ENOMEM); 2802 } 2803 2804 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2805 2806 error = bus_dma_tag_create(NULL, /* parent */ 2807 1, 0, /* alignment, bounds */ 2808 BUS_SPACE_MAXADDR, /* lowaddr */ 2809 BUS_SPACE_MAXADDR, /* highaddr */ 2810 NULL, NULL, /* filter, filterarg */ 2811 MCLBYTES, /* maxsize */ 2812 1, /* nsegments */ 2813 MCLBYTES, /* maxsegsize */ 2814 0, /* flags */ 2815 NULL, /* lockfunc */ 2816 NULL, /* lockarg */ 2817 &sc->rxtag); 2818 if (error) { 2819 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2820 __func__, error); 2821 goto fail; 2822 } 2823 2824 rx_buffer = sc->rx_buffer_area; 2825 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2826 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2827 &rx_buffer->map); 2828 if (error) { 2829 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2830 __func__, error); 2831 goto fail; 2832 } 2833 } 2834 2835 for (i = 0; i < sc->num_rx_desc; i++) { 2836 error = em_get_buf(i, sc, NULL); 2837 if (error) 2838 goto fail; 2839 } 2840 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2841 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2842 2843 return (0); 2844 2845fail: 2846 em_free_receive_structures(sc); 2847 return (error); 2848} 2849 2850/********************************************************************* 2851 * 2852 * Allocate and initialize receive structures. 2853 * 2854 **********************************************************************/ 2855static int 2856em_setup_receive_structures(struct em_softc *sc) 2857{ 2858 int error; 2859 2860 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2861 2862 if ((error = em_allocate_receive_structures(sc)) != 0) 2863 return (error); 2864 2865 /* Setup our descriptor pointers */ 2866 sc->next_rx_desc_to_check = 0; 2867 2868 return (0); 2869} 2870 2871/********************************************************************* 2872 * 2873 * Enable receive unit. 2874 * 2875 **********************************************************************/ 2876static void 2877em_initialize_receive_unit(struct em_softc *sc) 2878{ 2879 struct ifnet *ifp = sc->ifp; 2880 uint64_t bus_addr; 2881 uint32_t reg_rctl; 2882 uint32_t reg_rxcsum; 2883 2884 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2885 2886 /* 2887 * Make sure receives are disabled while setting 2888 * up the descriptor ring 2889 */ 2890 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2891 2892 /* Set the Receive Delay Timer Register */ 2893 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2894 2895 if(sc->hw.mac_type >= em_82540) { 2896 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2897 2898 /* 2899 * Set the interrupt throttling rate. Value is calculated 2900 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2901 */ 2902#define MAX_INTS_PER_SEC 8000 2903#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2904 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2905 } 2906 2907 /* Setup the Base and Length of the Rx Descriptor Ring */ 2908 bus_addr = sc->rxdma.dma_paddr; 2909 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2910 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2911 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2912 sizeof(struct em_rx_desc)); 2913 2914 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2915 E1000_WRITE_REG(&sc->hw, RDH, 0); 2916 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2917 2918 /* Setup the Receive Control Register */ 2919 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2920 E1000_RCTL_RDMTS_HALF | 2921 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2922 2923 if (sc->hw.tbi_compatibility_on == TRUE) 2924 reg_rctl |= E1000_RCTL_SBP; 2925 2926 2927 switch (sc->rx_buffer_len) { 2928 default: 2929 case EM_RXBUFFER_2048: 2930 reg_rctl |= E1000_RCTL_SZ_2048; 2931 break; 2932 case EM_RXBUFFER_4096: 2933 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2934 break; 2935 case EM_RXBUFFER_8192: 2936 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2937 break; 2938 case EM_RXBUFFER_16384: 2939 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2940 break; 2941 } 2942 2943 if (ifp->if_mtu > ETHERMTU) 2944 reg_rctl |= E1000_RCTL_LPE; 2945 2946 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2947 if ((sc->hw.mac_type >= em_82543) && 2948 (ifp->if_capenable & IFCAP_RXCSUM)) { 2949 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2950 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2951 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2952 } 2953 2954 /* Enable Receives */ 2955 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2956} 2957 2958/********************************************************************* 2959 * 2960 * Free receive related data structures. 2961 * 2962 **********************************************************************/ 2963static void 2964em_free_receive_structures(struct em_softc *sc) 2965{ 2966 struct em_buffer *rx_buffer; 2967 int i; 2968 2969 INIT_DEBUGOUT("free_receive_structures: begin"); 2970 2971 if (sc->rx_buffer_area != NULL) { 2972 rx_buffer = sc->rx_buffer_area; 2973 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2974 if (rx_buffer->m_head != NULL) { 2975 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2976 BUS_DMASYNC_POSTREAD); 2977 bus_dmamap_unload(sc->rxtag, 2978 rx_buffer->map); 2979 m_freem(rx_buffer->m_head); 2980 rx_buffer->m_head = NULL; 2981 } else if (rx_buffer->map != NULL) 2982 bus_dmamap_unload(sc->rxtag, 2983 rx_buffer->map); 2984 if (rx_buffer->map != NULL) { 2985 bus_dmamap_destroy(sc->rxtag, 2986 rx_buffer->map); 2987 rx_buffer->map = NULL; 2988 } 2989 } 2990 } 2991 if (sc->rx_buffer_area != NULL) { 2992 free(sc->rx_buffer_area, M_DEVBUF); 2993 sc->rx_buffer_area = NULL; 2994 } 2995 if (sc->rxtag != NULL) { 2996 bus_dma_tag_destroy(sc->rxtag); 2997 sc->rxtag = NULL; 2998 } 2999} 3000 3001/********************************************************************* 3002 * 3003 * This routine executes in interrupt context. It replenishes 3004 * the mbufs in the descriptor and sends data which has been 3005 * dma'ed into host memory to upper layer. 3006 * 3007 * We loop at most count times if count is > 0, or until done if 3008 * count < 0. 3009 * 3010 *********************************************************************/ 3011static int 3012em_rxeof(struct em_softc *sc, int count) 3013{ 3014 struct ifnet *ifp; 3015 struct mbuf *mp; 3016 uint8_t accept_frame = 0; 3017 uint8_t eop = 0; 3018 uint16_t len, desc_len, prev_len_adj; 3019 int i; 3020 3021 /* Pointer to the receive descriptor being examined. */ 3022 struct em_rx_desc *current_desc; 3023 3024 ifp = sc->ifp; 3025 i = sc->next_rx_desc_to_check; 3026 current_desc = &sc->rx_desc_base[i]; 3027 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3028 BUS_DMASYNC_POSTREAD); 3029 3030 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3031 return (0); 3032 3033 while ((current_desc->status & E1000_RXD_STAT_DD) && 3034 (count != 0) && 3035 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3036 struct mbuf *m = NULL; 3037 3038 mp = sc->rx_buffer_area[i].m_head; 3039 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3040 BUS_DMASYNC_POSTREAD); 3041 bus_dmamap_unload(sc->rxtag, 3042 sc->rx_buffer_area[i].map); 3043 3044 accept_frame = 1; 3045 prev_len_adj = 0; 3046 desc_len = le16toh(current_desc->length); 3047 if (current_desc->status & E1000_RXD_STAT_EOP) { 3048 count--; 3049 eop = 1; 3050 if (desc_len < ETHER_CRC_LEN) { 3051 len = 0; 3052 prev_len_adj = ETHER_CRC_LEN - desc_len; 3053 } else 3054 len = desc_len - ETHER_CRC_LEN; 3055 } else { 3056 eop = 0; 3057 len = desc_len; 3058 } 3059 3060 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3061 uint8_t last_byte; 3062 uint32_t pkt_len = desc_len; 3063 3064 if (sc->fmp != NULL) 3065 pkt_len += sc->fmp->m_pkthdr.len; 3066 3067 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3068 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3069 current_desc->errors, 3070 pkt_len, last_byte)) { 3071 em_tbi_adjust_stats(&sc->hw, 3072 &sc->stats, pkt_len, 3073 sc->hw.mac_addr); 3074 if (len > 0) 3075 len--; 3076 } else 3077 accept_frame = 0; 3078 } 3079 3080 if (accept_frame) { 3081 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3082 sc->dropped_pkts++; 3083 em_get_buf(i, sc, mp); 3084 if (sc->fmp != NULL) 3085 m_freem(sc->fmp); 3086 sc->fmp = NULL; 3087 sc->lmp = NULL; 3088 break; 3089 } 3090 3091 /* Assign correct length to the current fragment */ 3092 mp->m_len = len; 3093 3094 if (sc->fmp == NULL) { 3095 mp->m_pkthdr.len = len; 3096 sc->fmp = mp; /* Store the first mbuf */ 3097 sc->lmp = mp; 3098 } else { 3099 /* Chain mbuf's together */ 3100 mp->m_flags &= ~M_PKTHDR; 3101 /* 3102 * Adjust length of previous mbuf in chain if 3103 * we received less than 4 bytes in the last 3104 * descriptor. 3105 */ 3106 if (prev_len_adj > 0) { 3107 sc->lmp->m_len -= prev_len_adj; 3108 sc->fmp->m_pkthdr.len -= 3109 prev_len_adj; 3110 } 3111 sc->lmp->m_next = mp; 3112 sc->lmp = sc->lmp->m_next; 3113 sc->fmp->m_pkthdr.len += len; 3114 } 3115 3116 if (eop) { 3117 sc->fmp->m_pkthdr.rcvif = ifp; 3118 ifp->if_ipackets++; 3119 em_receive_checksum(sc, current_desc, 3120 sc->fmp); 3121#ifndef __NO_STRICT_ALIGNMENT 3122 if (ifp->if_mtu > ETHERMTU && 3123 em_fixup_rx(sc) != 0) 3124 goto skip; 3125#endif 3126 if (current_desc->status & E1000_RXD_STAT_VP) 3127 VLAN_INPUT_TAG(ifp, sc->fmp, 3128 (le16toh(current_desc->special) & 3129 E1000_RXD_SPC_VLAN_MASK)); 3130#ifndef __NO_STRICT_ALIGNMENT 3131skip: 3132#endif 3133 m = sc->fmp; 3134 sc->fmp = NULL; 3135 sc->lmp = NULL; 3136 } 3137 } else { 3138 sc->dropped_pkts++; 3139 em_get_buf(i, sc, mp); 3140 if (sc->fmp != NULL) 3141 m_freem(sc->fmp); 3142 sc->fmp = NULL; 3143 sc->lmp = NULL; 3144 } 3145 3146 /* Zero out the receive descriptors status. */ 3147 current_desc->status = 0; 3148 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3149 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3150 3151 /* Advance our pointers to the next descriptor. */ 3152 if (++i == sc->num_rx_desc) 3153 i = 0; 3154 if (m != NULL) { 3155 sc->next_rx_desc_to_check = i; 3156#ifdef DEVICE_POLLING 3157 EM_UNLOCK(sc); 3158 (*ifp->if_input)(ifp, m); 3159 EM_LOCK(sc); 3160#else 3161 (*ifp->if_input)(ifp, m); 3162#endif 3163 i = sc->next_rx_desc_to_check; 3164 } 3165 current_desc = &sc->rx_desc_base[i]; 3166 } 3167 sc->next_rx_desc_to_check = i; 3168 3169 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3170 if (--i < 0) 3171 i = sc->num_rx_desc - 1; 3172 E1000_WRITE_REG(&sc->hw, RDT, i); 3173 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3174 return (0); 3175 3176 return (1); 3177} 3178 3179#ifndef __NO_STRICT_ALIGNMENT 3180/* 3181 * When jumbo frames are enabled we should realign entire payload on 3182 * architecures with strict alignment. This is serious design mistake of 8254x 3183 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3184 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3185 * payload. On architecures without strict alignment restrictions 8254x still 3186 * performs unaligned memory access which would reduce the performance too. 3187 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3188 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3189 * existing mbuf chain. 3190 * 3191 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3192 * not used at all on architectures with strict alignment. 3193 */ 3194static int 3195em_fixup_rx(struct em_softc *sc) 3196{ 3197 struct mbuf *m, *n; 3198 int error; 3199 3200 error = 0; 3201 m = sc->fmp; 3202 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3203 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3204 m->m_data += ETHER_HDR_LEN; 3205 } else { 3206 MGETHDR(n, M_DONTWAIT, MT_DATA); 3207 if (n != NULL) { 3208 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3209 m->m_data += ETHER_HDR_LEN; 3210 m->m_len -= ETHER_HDR_LEN; 3211 n->m_len = ETHER_HDR_LEN; 3212 M_MOVE_PKTHDR(n, m); 3213 n->m_next = m; 3214 sc->fmp = n; 3215 } else { 3216 sc->dropped_pkts++; 3217 m_freem(sc->fmp); 3218 sc->fmp = NULL; 3219 error = ENOMEM; 3220 } 3221 } 3222 3223 return (error); 3224} 3225#endif 3226 3227/********************************************************************* 3228 * 3229 * Verify that the hardware indicated that the checksum is valid. 3230 * Inform the stack about the status of checksum so that stack 3231 * doesn't spend time verifying the checksum. 3232 * 3233 *********************************************************************/ 3234static void 3235em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3236 struct mbuf *mp) 3237{ 3238 /* 82543 or newer only */ 3239 if ((sc->hw.mac_type < em_82543) || 3240 /* Ignore Checksum bit is set */ 3241 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3242 mp->m_pkthdr.csum_flags = 0; 3243 return; 3244 } 3245 3246 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3247 /* Did it pass? */ 3248 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3249 /* IP Checksum Good */ 3250 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3251 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3252 3253 } else { 3254 mp->m_pkthdr.csum_flags = 0; 3255 } 3256 } 3257 3258 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3259 /* Did it pass? */ 3260 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3261 mp->m_pkthdr.csum_flags |= 3262 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3263 mp->m_pkthdr.csum_data = htons(0xffff); 3264 } 3265 } 3266} 3267 3268 3269static void 3270em_enable_vlans(struct em_softc *sc) 3271{ 3272 uint32_t ctrl; 3273 3274 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3275 3276 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3277 ctrl |= E1000_CTRL_VME; 3278 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3279} 3280 3281static void 3282em_disable_vlans(struct em_softc *sc) 3283{ 3284 uint32_t ctrl; 3285 3286 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3287 ctrl &= ~E1000_CTRL_VME; 3288 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3289} 3290 3291static void 3292em_enable_intr(struct em_softc *sc) 3293{ 3294 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3295} 3296 3297static void 3298em_disable_intr(struct em_softc *sc) 3299{ 3300 /* 3301 * The first version of 82542 had an errata where when link was forced 3302 * it would stay up even up even if the cable was disconnected. 3303 * Sequence errors were used to detect the disconnect and then the 3304 * driver would unforce the link. This code in the in the ISR. For this 3305 * to work correctly the Sequence error interrupt had to be enabled 3306 * all the time. 3307 */ 3308 3309 if (sc->hw.mac_type == em_82542_rev2_0) 3310 E1000_WRITE_REG(&sc->hw, IMC, 3311 (0xffffffff & ~E1000_IMC_RXSEQ)); 3312 else 3313 E1000_WRITE_REG(&sc->hw, IMC, 3314 0xffffffff); 3315} 3316 3317static int 3318em_is_valid_ether_addr(uint8_t *addr) 3319{ 3320 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3321 3322 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3323 return (FALSE); 3324 } 3325 3326 return (TRUE); 3327} 3328 3329void 3330em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3331{ 3332 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3333} 3334 3335void 3336em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3337{ 3338 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3339} 3340 3341void 3342em_pci_set_mwi(struct em_hw *hw) 3343{ 3344 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3345 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3346} 3347 3348void 3349em_pci_clear_mwi(struct em_hw *hw) 3350{ 3351 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3352 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3353} 3354 3355/********************************************************************* 3356* 82544 Coexistence issue workaround. 3357* There are 2 issues. 3358* 1. Transmit Hang issue. 3359* To detect this issue, following equation can be used... 3360* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3361* If SUM[3:0] is in between 1 to 4, we will have this issue. 3362* 3363* 2. DAC issue. 3364* To detect this issue, following equation can be used... 3365* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3366* If SUM[3:0] is in between 9 to c, we will have this issue. 3367* 3368* 3369* WORKAROUND: 3370* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3371* 3372*** *********************************************************************/ 3373static uint32_t 3374em_fill_descriptors (bus_addr_t address, uint32_t length, 3375 PDESC_ARRAY desc_array) 3376{ 3377 /* Since issue is sensitive to length and address.*/ 3378 /* Let us first check the address...*/ 3379 uint32_t safe_terminator; 3380 if (length <= 4) { 3381 desc_array->descriptor[0].address = address; 3382 desc_array->descriptor[0].length = length; 3383 desc_array->elements = 1; 3384 return (desc_array->elements); 3385 } 3386 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3387 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3388 if (safe_terminator == 0 || 3389 (safe_terminator > 4 && 3390 safe_terminator < 9) || 3391 (safe_terminator > 0xC && 3392 safe_terminator <= 0xF)) { 3393 desc_array->descriptor[0].address = address; 3394 desc_array->descriptor[0].length = length; 3395 desc_array->elements = 1; 3396 return (desc_array->elements); 3397 } 3398 3399 desc_array->descriptor[0].address = address; 3400 desc_array->descriptor[0].length = length - 4; 3401 desc_array->descriptor[1].address = address + (length - 4); 3402 desc_array->descriptor[1].length = 4; 3403 desc_array->elements = 2; 3404 return (desc_array->elements); 3405} 3406 3407/********************************************************************** 3408 * 3409 * Update the board statistics counters. 3410 * 3411 **********************************************************************/ 3412static void 3413em_update_stats_counters(struct em_softc *sc) 3414{ 3415 struct ifnet *ifp; 3416 3417 if(sc->hw.media_type == em_media_type_copper || 3418 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3419 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3420 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3421 } 3422 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3423 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3424 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3425 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3426 3427 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3428 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3429 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3430 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3431 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3432 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3433 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3434 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3435 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3436 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3437 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3438 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3439 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3440 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3441 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3442 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3443 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3444 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3445 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3446 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3447 3448 /* For the 64-bit byte counters the low dword must be read first. */ 3449 /* Both registers clear on the read of the high dword */ 3450 3451 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3452 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3453 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3454 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3455 3456 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3457 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3458 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3459 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3460 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3461 3462 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3463 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3464 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3465 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3466 3467 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3468 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3469 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3470 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3471 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3472 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3473 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3474 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3475 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3476 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3477 3478 if (sc->hw.mac_type >= em_82543) { 3479 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3480 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3481 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3482 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3483 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3484 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3485 } 3486 ifp = sc->ifp; 3487 3488 ifp->if_collisions = sc->stats.colc; 3489 3490 /* Rx Errors */ 3491 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3492 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3493 sc->stats.mpc + sc->stats.cexterr; 3494 3495 /* Tx Errors */ 3496 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3497 sc->watchdog_events; 3498} 3499 3500 3501/********************************************************************** 3502 * 3503 * This routine is called only when em_display_debug_stats is enabled. 3504 * This routine provides a way to take a look at important statistics 3505 * maintained by the driver and hardware. 3506 * 3507 **********************************************************************/ 3508static void 3509em_print_debug_info(struct em_softc *sc) 3510{ 3511 device_t dev = sc->dev; 3512 uint8_t *hw_addr = sc->hw.hw_addr; 3513 3514 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3515 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3516 E1000_READ_REG(&sc->hw, CTRL), 3517 E1000_READ_REG(&sc->hw, RCTL)); 3518 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3519 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3520 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3521 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3522 sc->hw.fc_high_water, 3523 sc->hw.fc_low_water); 3524 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3525 E1000_READ_REG(&sc->hw, TIDV), 3526 E1000_READ_REG(&sc->hw, TADV)); 3527 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3528 E1000_READ_REG(&sc->hw, RDTR), 3529 E1000_READ_REG(&sc->hw, RADV)); 3530 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3531 (long long)sc->tx_fifo_wrk_cnt, 3532 (long long)sc->tx_fifo_reset_cnt); 3533 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3534 E1000_READ_REG(&sc->hw, TDH), 3535 E1000_READ_REG(&sc->hw, TDT)); 3536 device_printf(dev, "Num Tx descriptors avail = %d\n", 3537 sc->num_tx_desc_avail); 3538 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3539 sc->no_tx_desc_avail1); 3540 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3541 sc->no_tx_desc_avail2); 3542 device_printf(dev, "Std mbuf failed = %ld\n", 3543 sc->mbuf_alloc_failed); 3544 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3545 sc->mbuf_cluster_failed); 3546 device_printf(dev, "Driver dropped packets = %ld\n", 3547 sc->dropped_pkts); 3548} 3549 3550static void 3551em_print_hw_stats(struct em_softc *sc) 3552{ 3553 device_t dev = sc->dev; 3554 3555 device_printf(dev, "Excessive collisions = %lld\n", 3556 (long long)sc->stats.ecol); 3557 device_printf(dev, "Symbol errors = %lld\n", 3558 (long long)sc->stats.symerrs); 3559 device_printf(dev, "Sequence errors = %lld\n", 3560 (long long)sc->stats.sec); 3561 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3562 3563 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3564 device_printf(dev, "Receive No Buffers = %lld\n", 3565 (long long)sc->stats.rnbc); 3566 device_printf(dev, "Receive length errors = %lld\n", 3567 (long long)sc->stats.rlec); 3568 device_printf(dev, "Receive errors = %lld\n", 3569 (long long)sc->stats.rxerrc); 3570 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3571 device_printf(dev, "Alignment errors = %lld\n", 3572 (long long)sc->stats.algnerrc); 3573 device_printf(dev, "Carrier extension errors = %lld\n", 3574 (long long)sc->stats.cexterr); 3575 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3576 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3577 3578 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3579 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3580 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3581 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3582 3583 device_printf(dev, "Good Packets Rcvd = %lld\n", 3584 (long long)sc->stats.gprc); 3585 device_printf(dev, "Good Packets Xmtd = %lld\n", 3586 (long long)sc->stats.gptc); 3587} 3588 3589static int 3590em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3591{ 3592 struct em_softc *sc; 3593 int error; 3594 int result; 3595 3596 result = -1; 3597 error = sysctl_handle_int(oidp, &result, 0, req); 3598 3599 if (error || !req->newptr) 3600 return (error); 3601 3602 if (result == 1) { 3603 sc = (struct em_softc *)arg1; 3604 em_print_debug_info(sc); 3605 } 3606 3607 return (error); 3608} 3609 3610 3611static int 3612em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3613{ 3614 struct em_softc *sc; 3615 int error; 3616 int result; 3617 3618 result = -1; 3619 error = sysctl_handle_int(oidp, &result, 0, req); 3620 3621 if (error || !req->newptr) 3622 return (error); 3623 3624 if (result == 1) { 3625 sc = (struct em_softc *)arg1; 3626 em_print_hw_stats(sc); 3627 } 3628 3629 return (error); 3630} 3631 3632static int 3633em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3634{ 3635 struct em_int_delay_info *info; 3636 struct em_softc *sc; 3637 uint32_t regval; 3638 int error; 3639 int usecs; 3640 int ticks; 3641 3642 info = (struct em_int_delay_info *)arg1; 3643 usecs = info->value; 3644 error = sysctl_handle_int(oidp, &usecs, 0, req); 3645 if (error != 0 || req->newptr == NULL) 3646 return (error); 3647 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3648 return (EINVAL); 3649 info->value = usecs; 3650 ticks = E1000_USECS_TO_TICKS(usecs); 3651 3652 sc = info->sc; 3653 3654 EM_LOCK(sc); 3655 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3656 regval = (regval & ~0xffff) | (ticks & 0xffff); 3657 /* Handle a few special cases. */ 3658 switch (info->offset) { 3659 case E1000_RDTR: 3660 case E1000_82542_RDTR: 3661 regval |= E1000_RDT_FPDB; 3662 break; 3663 case E1000_TIDV: 3664 case E1000_82542_TIDV: 3665 if (ticks == 0) { 3666 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3667 /* Don't write 0 into the TIDV register. */ 3668 regval++; 3669 } else 3670 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3671 break; 3672 } 3673 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3674 EM_UNLOCK(sc); 3675 return (0); 3676} 3677 3678static void 3679em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3680 const char *description, struct em_int_delay_info *info, 3681 int offset, int value) 3682{ 3683 info->sc = sc; 3684 info->offset = offset; 3685 info->value = value; 3686 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3687 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3688 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3689 info, 0, em_sysctl_int_delay, "I", description); 3690} 3691 3692#ifndef DEVICE_POLLING 3693static void 3694em_add_int_process_limit(struct em_softc *sc, const char *name, 3695 const char *description, int *limit, int value) 3696{ 3697 *limit = value; 3698 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3699 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3700 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3701} 3702#endif 3703