if_em.c revision 160519
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 160519 2006-07-20 04:18:45Z yongari $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/if_ether.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcivar.h> 76#include <dev/pci/pcireg.h> 77#include <dev/em/if_em_hw.h> 78#include <dev/em/if_em.h> 79 80/********************************************************************* 81 * Set this to one to display debug statistics 82 *********************************************************************/ 83int em_display_debug_stats = 0; 84 85/********************************************************************* 86 * Driver version 87 *********************************************************************/ 88 89char em_driver_version[] = "Version - 5.1.5"; 90 91 92/********************************************************************* 93 * PCI Device ID Table 94 * 95 * Used by probe to select devices to load on 96 * Last field stores an index into em_strings 97 * Last entry must be all 0s 98 * 99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 100 *********************************************************************/ 101 102static em_vendor_info_t em_vendor_info_array[] = 103{ 104 /* Intel(R) PRO/1000 Network Connection */ 105 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 110 111 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 118 119 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 120 121 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 124 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 128 129 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 135 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 144 PCI_ANY_ID, PCI_ANY_ID, 0}, 145 146 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 150 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 154 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 162 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 163 PCI_ANY_ID, PCI_ANY_ID, 0}, 164 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 165 PCI_ANY_ID, PCI_ANY_ID, 0}, 166 167 /* required last entry */ 168 { 0, 0, 0, 0, 0} 169}; 170 171/********************************************************************* 172 * Table of branding strings for all supported NICs. 173 *********************************************************************/ 174 175static char *em_strings[] = { 176 "Intel(R) PRO/1000 Network Connection" 177}; 178 179/********************************************************************* 180 * Function prototypes 181 *********************************************************************/ 182static int em_probe(device_t); 183static int em_attach(device_t); 184static int em_detach(device_t); 185static int em_shutdown(device_t); 186static int em_suspend(device_t); 187static int em_resume(device_t); 188static void em_start(struct ifnet *); 189static void em_start_locked(struct ifnet *ifp); 190static int em_ioctl(struct ifnet *, u_long, caddr_t); 191static void em_watchdog(struct ifnet *); 192static void em_init(void *); 193static void em_init_locked(struct em_softc *); 194static void em_stop(void *); 195static void em_media_status(struct ifnet *, struct ifmediareq *); 196static int em_media_change(struct ifnet *); 197static void em_identify_hardware(struct em_softc *); 198static int em_allocate_pci_resources(struct em_softc *); 199static int em_allocate_intr(struct em_softc *); 200static void em_free_intr(struct em_softc *); 201static void em_free_pci_resources(struct em_softc *); 202static void em_local_timer(void *); 203static int em_hardware_init(struct em_softc *); 204static void em_setup_interface(device_t, struct em_softc *); 205static int em_setup_transmit_structures(struct em_softc *); 206static void em_initialize_transmit_unit(struct em_softc *); 207static int em_setup_receive_structures(struct em_softc *); 208static void em_initialize_receive_unit(struct em_softc *); 209static void em_enable_intr(struct em_softc *); 210static void em_disable_intr(struct em_softc *); 211static void em_free_transmit_structures(struct em_softc *); 212static void em_free_receive_structures(struct em_softc *); 213static void em_update_stats_counters(struct em_softc *); 214static void em_txeof(struct em_softc *); 215static int em_allocate_receive_structures(struct em_softc *); 216static int em_allocate_transmit_structures(struct em_softc *); 217static int em_rxeof(struct em_softc *, int); 218#ifndef __NO_STRICT_ALIGNMENT 219static int em_fixup_rx(struct em_softc *); 220#endif 221static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 222 struct mbuf *); 223static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 224 uint32_t *, uint32_t *); 225static void em_set_promisc(struct em_softc *); 226static void em_disable_promisc(struct em_softc *); 227static void em_set_multi(struct em_softc *); 228static void em_print_hw_stats(struct em_softc *); 229static void em_update_link_status(struct em_softc *); 230static int em_get_buf(int i, struct em_softc *, struct mbuf *); 231static void em_enable_vlans(struct em_softc *); 232static void em_disable_vlans(struct em_softc *); 233static int em_encap(struct em_softc *, struct mbuf **); 234static void em_smartspeed(struct em_softc *); 235static int em_82547_fifo_workaround(struct em_softc *, int); 236static void em_82547_update_fifo_head(struct em_softc *, int); 237static int em_82547_tx_fifo_reset(struct em_softc *); 238static void em_82547_move_tail(void *arg); 239static void em_82547_move_tail_locked(struct em_softc *); 240static int em_dma_malloc(struct em_softc *, bus_size_t, 241 struct em_dma_alloc *, int); 242static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 243static void em_print_debug_info(struct em_softc *); 244static int em_is_valid_ether_addr(uint8_t *); 245static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 246static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 247static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 248 PDESC_ARRAY desc_array); 249static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 250static void em_add_int_delay_sysctl(struct em_softc *, const char *, 251 const char *, struct em_int_delay_info *, int, int); 252 253/* 254 * Fast interrupt handler and legacy ithread/polling modes are 255 * mutually exclusive. 256 */ 257#ifdef DEVICE_POLLING 258static poll_handler_t em_poll; 259static void em_intr(void *); 260#else 261static void em_intr_fast(void *); 262static void em_add_int_process_limit(struct em_softc *, const char *, 263 const char *, int *, int); 264static void em_handle_rxtx(void *context, int pending); 265static void em_handle_link(void *context, int pending); 266#endif 267 268/********************************************************************* 269 * FreeBSD Device Interface Entry Points 270 *********************************************************************/ 271 272static device_method_t em_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, em_probe), 275 DEVMETHOD(device_attach, em_attach), 276 DEVMETHOD(device_detach, em_detach), 277 DEVMETHOD(device_shutdown, em_shutdown), 278 DEVMETHOD(device_suspend, em_suspend), 279 DEVMETHOD(device_resume, em_resume), 280 {0, 0} 281}; 282 283static driver_t em_driver = { 284 "em", em_methods, sizeof(struct em_softc), 285}; 286 287static devclass_t em_devclass; 288DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 289MODULE_DEPEND(em, pci, 1, 1, 1); 290MODULE_DEPEND(em, ether, 1, 1, 1); 291 292/********************************************************************* 293 * Tunable default values. 294 *********************************************************************/ 295 296#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 297#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 298 299static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 300static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 301static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 302static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 303static int em_rxd = EM_DEFAULT_RXD; 304static int em_txd = EM_DEFAULT_TXD; 305 306TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 307TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 308TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 309TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 310TUNABLE_INT("hw.em.rxd", &em_rxd); 311TUNABLE_INT("hw.em.txd", &em_txd); 312#ifndef DEVICE_POLLING 313static int em_rx_process_limit = 100; 314TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 315#endif 316 317/********************************************************************* 318 * Device identification routine 319 * 320 * em_probe determines if the driver should be loaded on 321 * adapter based on PCI vendor/device id of the adapter. 322 * 323 * return BUS_PROBE_DEFAULT on success, positive on failure 324 *********************************************************************/ 325 326static int 327em_probe(device_t dev) 328{ 329 char adapter_name[60]; 330 uint16_t pci_vendor_id = 0; 331 uint16_t pci_device_id = 0; 332 uint16_t pci_subvendor_id = 0; 333 uint16_t pci_subdevice_id = 0; 334 em_vendor_info_t *ent; 335 336 INIT_DEBUGOUT("em_probe: begin"); 337 338 pci_vendor_id = pci_get_vendor(dev); 339 if (pci_vendor_id != EM_VENDOR_ID) 340 return (ENXIO); 341 342 pci_device_id = pci_get_device(dev); 343 pci_subvendor_id = pci_get_subvendor(dev); 344 pci_subdevice_id = pci_get_subdevice(dev); 345 346 ent = em_vendor_info_array; 347 while (ent->vendor_id != 0) { 348 if ((pci_vendor_id == ent->vendor_id) && 349 (pci_device_id == ent->device_id) && 350 351 ((pci_subvendor_id == ent->subvendor_id) || 352 (ent->subvendor_id == PCI_ANY_ID)) && 353 354 ((pci_subdevice_id == ent->subdevice_id) || 355 (ent->subdevice_id == PCI_ANY_ID))) { 356 sprintf(adapter_name, "%s %s", 357 em_strings[ent->index], 358 em_driver_version); 359 device_set_desc_copy(dev, adapter_name); 360 return (BUS_PROBE_DEFAULT); 361 } 362 ent++; 363 } 364 365 return (ENXIO); 366} 367 368/********************************************************************* 369 * Device initialization routine 370 * 371 * The attach entry point is called when the driver is being loaded. 372 * This routine identifies the type of hardware, allocates all resources 373 * and initializes the hardware. 374 * 375 * return 0 on success, positive on failure 376 *********************************************************************/ 377 378static int 379em_attach(device_t dev) 380{ 381 struct em_softc *sc; 382 int tsize, rsize; 383 int error = 0; 384 385 INIT_DEBUGOUT("em_attach: begin"); 386 387 sc = device_get_softc(dev); 388 sc->dev = sc->osdep.dev = dev; 389 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 390 391 /* SYSCTL stuff */ 392 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 393 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 394 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 395 em_sysctl_debug_info, "I", "Debug Information"); 396 397 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 398 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 399 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 400 em_sysctl_stats, "I", "Statistics"); 401 402 callout_init(&sc->timer, CALLOUT_MPSAFE); 403 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 404 405 /* Determine hardware revision */ 406 em_identify_hardware(sc); 407 408 /* Set up some sysctls for the tunable interrupt delays */ 409 em_add_int_delay_sysctl(sc, "rx_int_delay", 410 "receive interrupt delay in usecs", &sc->rx_int_delay, 411 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 412 em_add_int_delay_sysctl(sc, "tx_int_delay", 413 "transmit interrupt delay in usecs", &sc->tx_int_delay, 414 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 415 if (sc->hw.mac_type >= em_82540) { 416 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 417 "receive interrupt delay limit in usecs", 418 &sc->rx_abs_int_delay, 419 E1000_REG_OFFSET(&sc->hw, RADV), 420 em_rx_abs_int_delay_dflt); 421 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 422 "transmit interrupt delay limit in usecs", 423 &sc->tx_abs_int_delay, 424 E1000_REG_OFFSET(&sc->hw, TADV), 425 em_tx_abs_int_delay_dflt); 426 } 427 428#ifndef DEVICE_POLLING 429 /* Sysctls for limiting the amount of work done in the taskqueue */ 430 em_add_int_process_limit(sc, "rx_processing_limit", 431 "max number of rx packets to process", &sc->rx_process_limit, 432 em_rx_process_limit); 433#endif 434 435 /* 436 * Validate number of transmit and receive descriptors. It 437 * must not exceed hardware maximum, and must be multiple 438 * of E1000_DBA_ALIGN. 439 */ 440 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 441 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 442 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 443 (em_txd < EM_MIN_TXD)) { 444 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 445 EM_DEFAULT_TXD, em_txd); 446 sc->num_tx_desc = EM_DEFAULT_TXD; 447 } else 448 sc->num_tx_desc = em_txd; 449 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 450 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 451 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 452 (em_rxd < EM_MIN_RXD)) { 453 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 454 EM_DEFAULT_RXD, em_rxd); 455 sc->num_rx_desc = EM_DEFAULT_RXD; 456 } else 457 sc->num_rx_desc = em_rxd; 458 459 sc->hw.autoneg = DO_AUTO_NEG; 460 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 461 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 462 sc->hw.tbi_compatibility_en = TRUE; 463 sc->rx_buffer_len = EM_RXBUFFER_2048; 464 465 sc->hw.phy_init_script = 1; 466 sc->hw.phy_reset_disable = FALSE; 467 468#ifndef EM_MASTER_SLAVE 469 sc->hw.master_slave = em_ms_hw_default; 470#else 471 sc->hw.master_slave = EM_MASTER_SLAVE; 472#endif 473 /* 474 * Set the max frame size assuming standard ethernet 475 * sized frames. 476 */ 477 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 478 479 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 480 481 /* 482 * This controls when hardware reports transmit completion 483 * status. 484 */ 485 sc->hw.report_tx_early = 1; 486 if (em_allocate_pci_resources(sc)) { 487 device_printf(dev, "Allocation of PCI resources failed\n"); 488 error = ENXIO; 489 goto err_pci; 490 } 491 492 /* Initialize eeprom parameters */ 493 em_init_eeprom_params(&sc->hw); 494 495 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 496 E1000_DBA_ALIGN); 497 498 /* Allocate Transmit Descriptor ring */ 499 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 500 device_printf(dev, "Unable to allocate tx_desc memory\n"); 501 error = ENOMEM; 502 goto err_tx_desc; 503 } 504 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 505 506 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 507 E1000_DBA_ALIGN); 508 509 /* Allocate Receive Descriptor ring */ 510 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 511 device_printf(dev, "Unable to allocate rx_desc memory\n"); 512 error = ENOMEM; 513 goto err_rx_desc; 514 } 515 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 516 517 /* Initialize the hardware */ 518 if (em_hardware_init(sc)) { 519 device_printf(dev, "Unable to initialize the hardware\n"); 520 error = EIO; 521 goto err_hw_init; 522 } 523 524 /* Copy the permanent MAC address out of the EEPROM */ 525 if (em_read_mac_addr(&sc->hw) < 0) { 526 device_printf(dev, "EEPROM read error while reading MAC" 527 " address\n"); 528 error = EIO; 529 goto err_hw_init; 530 } 531 532 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 533 device_printf(dev, "Invalid MAC address\n"); 534 error = EIO; 535 goto err_hw_init; 536 } 537 538 /* Setup OS specific network interface */ 539 em_setup_interface(dev, sc); 540 541 em_allocate_intr(sc); 542 543 /* Initialize statistics */ 544 em_clear_hw_cntrs(&sc->hw); 545 em_update_stats_counters(sc); 546 sc->hw.get_link_status = 1; 547 em_update_link_status(sc); 548 549 /* Indicate SOL/IDER usage */ 550 if (em_check_phy_reset_block(&sc->hw)) 551 device_printf(dev, 552 "PHY reset is blocked due to SOL/IDER session.\n"); 553 554 /* Identify 82544 on PCIX */ 555 em_get_bus_info(&sc->hw); 556 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 557 sc->pcix_82544 = TRUE; 558 else 559 sc->pcix_82544 = FALSE; 560 561 INIT_DEBUGOUT("em_attach: end"); 562 563 return (0); 564 565err_hw_init: 566 em_dma_free(sc, &sc->rxdma); 567err_rx_desc: 568 em_dma_free(sc, &sc->txdma); 569err_tx_desc: 570err_pci: 571 em_free_intr(sc); 572 em_free_pci_resources(sc); 573 EM_LOCK_DESTROY(sc); 574 575 return (error); 576} 577 578/********************************************************************* 579 * Device removal routine 580 * 581 * The detach entry point is called when the driver is being removed. 582 * This routine stops the adapter and deallocates all the resources 583 * that were allocated for driver operation. 584 * 585 * return 0 on success, positive on failure 586 *********************************************************************/ 587 588static int 589em_detach(device_t dev) 590{ 591 struct em_softc *sc = device_get_softc(dev); 592 struct ifnet *ifp = sc->ifp; 593 594 INIT_DEBUGOUT("em_detach: begin"); 595 596#ifdef DEVICE_POLLING 597 if (ifp->if_capenable & IFCAP_POLLING) 598 ether_poll_deregister(ifp); 599#endif 600 601 em_free_intr(sc); 602 EM_LOCK(sc); 603 sc->in_detach = 1; 604 em_stop(sc); 605 em_phy_hw_reset(&sc->hw); 606 EM_UNLOCK(sc); 607 ether_ifdetach(sc->ifp); 608 609 em_free_pci_resources(sc); 610 bus_generic_detach(dev); 611 if_free(ifp); 612 613 /* Free Transmit Descriptor ring */ 614 if (sc->tx_desc_base) { 615 em_dma_free(sc, &sc->txdma); 616 sc->tx_desc_base = NULL; 617 } 618 619 /* Free Receive Descriptor ring */ 620 if (sc->rx_desc_base) { 621 em_dma_free(sc, &sc->rxdma); 622 sc->rx_desc_base = NULL; 623 } 624 625 EM_LOCK_DESTROY(sc); 626 627 return (0); 628} 629 630/********************************************************************* 631 * 632 * Shutdown entry point 633 * 634 **********************************************************************/ 635 636static int 637em_shutdown(device_t dev) 638{ 639 struct em_softc *sc = device_get_softc(dev); 640 EM_LOCK(sc); 641 em_stop(sc); 642 EM_UNLOCK(sc); 643 return (0); 644} 645 646/* 647 * Suspend/resume device methods. 648 */ 649static int 650em_suspend(device_t dev) 651{ 652 struct em_softc *sc = device_get_softc(dev); 653 654 EM_LOCK(sc); 655 em_stop(sc); 656 EM_UNLOCK(sc); 657 658 return bus_generic_suspend(dev); 659} 660 661static int 662em_resume(device_t dev) 663{ 664 struct em_softc *sc = device_get_softc(dev); 665 struct ifnet *ifp = sc->ifp; 666 667 EM_LOCK(sc); 668 em_init_locked(sc); 669 if ((ifp->if_flags & IFF_UP) && 670 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 671 em_start_locked(ifp); 672 EM_UNLOCK(sc); 673 674 return bus_generic_resume(dev); 675} 676 677 678/********************************************************************* 679 * Transmit entry point 680 * 681 * em_start is called by the stack to initiate a transmit. 682 * The driver will remain in this routine as long as there are 683 * packets to transmit and transmit resources are available. 684 * In case resources are not available stack is notified and 685 * the packet is requeued. 686 **********************************************************************/ 687 688static void 689em_start_locked(struct ifnet *ifp) 690{ 691 struct em_softc *sc = ifp->if_softc; 692 struct mbuf *m_head; 693 694 EM_LOCK_ASSERT(sc); 695 696 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 697 IFF_DRV_RUNNING) 698 return; 699 if (!sc->link_active) 700 return; 701 702 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 703 704 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 705 if (m_head == NULL) 706 break; 707 /* 708 * em_encap() can modify our pointer, and or make it NULL on 709 * failure. In that event, we can't requeue. 710 */ 711 if (em_encap(sc, &m_head)) { 712 if (m_head == NULL) 713 break; 714 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 715 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 716 break; 717 } 718 719 /* Send a copy of the frame to the BPF listener */ 720 BPF_MTAP(ifp, m_head); 721 722 /* Set timeout in case hardware has problems transmitting. */ 723 ifp->if_timer = EM_TX_TIMEOUT; 724 } 725} 726 727static void 728em_start(struct ifnet *ifp) 729{ 730 struct em_softc *sc = ifp->if_softc; 731 732 EM_LOCK(sc); 733 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 734 em_start_locked(ifp); 735 EM_UNLOCK(sc); 736} 737 738/********************************************************************* 739 * Ioctl entry point 740 * 741 * em_ioctl is called when the user wants to configure the 742 * interface. 743 * 744 * return 0 on success, positive on failure 745 **********************************************************************/ 746 747static int 748em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 749{ 750 struct em_softc *sc = ifp->if_softc; 751 struct ifreq *ifr = (struct ifreq *)data; 752 struct ifaddr *ifa = (struct ifaddr *)data; 753 int error = 0; 754 755 if (sc->in_detach) 756 return (error); 757 758 switch (command) { 759 case SIOCSIFADDR: 760 case SIOCGIFADDR: 761 if (ifa->ifa_addr->sa_family == AF_INET) { 762 /* 763 * XXX 764 * Since resetting hardware takes a very long time 765 * and results in link renegotiation we only 766 * initialize the hardware only when it is absolutely 767 * required. 768 */ 769 ifp->if_flags |= IFF_UP; 770 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 771 EM_LOCK(sc); 772 em_init_locked(sc); 773 EM_UNLOCK(sc); 774 } 775 arp_ifinit(ifp, ifa); 776 } else 777 error = ether_ioctl(ifp, command, data); 778 break; 779 case SIOCSIFMTU: 780 { 781 int max_frame_size; 782 uint16_t eeprom_data = 0; 783 784 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 785 786 EM_LOCK(sc); 787 switch (sc->hw.mac_type) { 788 case em_82573: 789 /* 790 * 82573 only supports jumbo frames 791 * if ASPM is disabled. 792 */ 793 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1, 794 &eeprom_data); 795 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 796 max_frame_size = ETHER_MAX_LEN; 797 break; 798 } 799 /* Allow Jumbo frames - fall thru */ 800 case em_82571: 801 case em_82572: 802 case em_80003es2lan: /* Limit Jumbo Frame size */ 803 max_frame_size = 9234; 804 break; 805 default: 806 max_frame_size = MAX_JUMBO_FRAME_SIZE; 807 } 808 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 809 ETHER_CRC_LEN) { 810 EM_UNLOCK(sc); 811 error = EINVAL; 812 break; 813 } 814 815 ifp->if_mtu = ifr->ifr_mtu; 816 sc->hw.max_frame_size = 817 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 818 em_init_locked(sc); 819 EM_UNLOCK(sc); 820 break; 821 } 822 case SIOCSIFFLAGS: 823 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 824 EM_LOCK(sc); 825 if (ifp->if_flags & IFF_UP) { 826 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 827 if ((ifp->if_flags ^ sc->if_flags) & 828 IFF_PROMISC) { 829 em_disable_promisc(sc); 830 em_set_promisc(sc); 831 } 832 } else 833 em_init_locked(sc); 834 } else { 835 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 836 em_stop(sc); 837 } 838 } 839 sc->if_flags = ifp->if_flags; 840 EM_UNLOCK(sc); 841 break; 842 case SIOCADDMULTI: 843 case SIOCDELMULTI: 844 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 845 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 846 EM_LOCK(sc); 847 em_disable_intr(sc); 848 em_set_multi(sc); 849 if (sc->hw.mac_type == em_82542_rev2_0) { 850 em_initialize_receive_unit(sc); 851 } 852#ifdef DEVICE_POLLING 853 if (!(ifp->if_capenable & IFCAP_POLLING)) 854#endif 855 em_enable_intr(sc); 856 EM_UNLOCK(sc); 857 } 858 break; 859 case SIOCSIFMEDIA: 860 case SIOCGIFMEDIA: 861 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 862 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 863 break; 864 case SIOCSIFCAP: 865 { 866 int mask, reinit; 867 868 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 869 reinit = 0; 870 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 871#ifdef DEVICE_POLLING 872 if (mask & IFCAP_POLLING) { 873 if (ifr->ifr_reqcap & IFCAP_POLLING) { 874 error = ether_poll_register(em_poll, ifp); 875 if (error) 876 return (error); 877 EM_LOCK(sc); 878 em_disable_intr(sc); 879 ifp->if_capenable |= IFCAP_POLLING; 880 EM_UNLOCK(sc); 881 } else { 882 error = ether_poll_deregister(ifp); 883 /* Enable interrupt even in error case */ 884 EM_LOCK(sc); 885 em_enable_intr(sc); 886 ifp->if_capenable &= ~IFCAP_POLLING; 887 EM_UNLOCK(sc); 888 } 889 } 890#endif 891 if (mask & IFCAP_HWCSUM) { 892 ifp->if_capenable ^= IFCAP_HWCSUM; 893 reinit = 1; 894 } 895 if (mask & IFCAP_VLAN_HWTAGGING) { 896 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 897 reinit = 1; 898 } 899 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 900 em_init(sc); 901 VLAN_CAPABILITIES(ifp); 902 break; 903 } 904 default: 905 error = ether_ioctl(ifp, command, data); 906 break; 907 } 908 909 return (error); 910} 911 912/********************************************************************* 913 * Watchdog entry point 914 * 915 * This routine is called whenever hardware quits transmitting. 916 * 917 **********************************************************************/ 918 919static void 920em_watchdog(struct ifnet *ifp) 921{ 922 struct em_softc *sc = ifp->if_softc; 923 924 EM_LOCK(sc); 925 /* If we are in this routine because of pause frames, then 926 * don't reset the hardware. 927 */ 928 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 929 ifp->if_timer = EM_TX_TIMEOUT; 930 EM_UNLOCK(sc); 931 return; 932 } 933 934 if (em_check_for_link(&sc->hw) == 0) 935 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 936 937 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 938 sc->watchdog_events++; 939 940 em_init_locked(sc); 941 EM_UNLOCK(sc); 942} 943 944/********************************************************************* 945 * Init entry point 946 * 947 * This routine is used in two ways. It is used by the stack as 948 * init entry point in network interface structure. It is also used 949 * by the driver as a hw/sw initialization routine to get to a 950 * consistent state. 951 * 952 * return 0 on success, positive on failure 953 **********************************************************************/ 954 955static void 956em_init_locked(struct em_softc *sc) 957{ 958 struct ifnet *ifp = sc->ifp; 959 device_t dev = sc->dev; 960 uint32_t pba; 961 962 INIT_DEBUGOUT("em_init: begin"); 963 964 EM_LOCK_ASSERT(sc); 965 966 em_stop(sc); 967 968 /* 969 * Packet Buffer Allocation (PBA) 970 * Writing PBA sets the receive portion of the buffer 971 * the remainder is used for the transmit buffer. 972 */ 973 switch (sc->hw.mac_type) { 974 case em_82547: 975 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 976 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 977 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 978 else 979 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 980 sc->tx_fifo_head = 0; 981 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 982 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 983 break; 984 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */ 985 case em_82571: /* 82571: Total Packet Buffer is 48K */ 986 case em_82572: /* 82572: Total Packet Buffer is 48K */ 987 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 988 break; 989 case em_82573: /* 82573: Total Packet Buffer is 32K */ 990 /* Jumbo frames not supported */ 991 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 992 break; 993 default: 994 /* Devices before 82547 had a Packet Buffer of 64K. */ 995 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 996 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 997 else 998 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 999 } 1000 1001 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1002 E1000_WRITE_REG(&sc->hw, PBA, pba); 1003 1004 /* Get the latest mac address, User can use a LAA */ 1005 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 1006 1007 /* Initialize the hardware */ 1008 if (em_hardware_init(sc)) { 1009 device_printf(dev, "Unable to initialize the hardware\n"); 1010 return; 1011 } 1012 em_update_link_status(sc); 1013 1014 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1015 em_enable_vlans(sc); 1016 1017 /* Prepare transmit descriptors and buffers */ 1018 if (em_setup_transmit_structures(sc)) { 1019 device_printf(dev, "Could not setup transmit structures\n"); 1020 em_stop(sc); 1021 return; 1022 } 1023 em_initialize_transmit_unit(sc); 1024 1025 /* Setup Multicast table */ 1026 em_set_multi(sc); 1027 1028 /* Prepare receive descriptors and buffers */ 1029 if (em_setup_receive_structures(sc)) { 1030 device_printf(dev, "Could not setup receive structures\n"); 1031 em_stop(sc); 1032 return; 1033 } 1034 em_initialize_receive_unit(sc); 1035 1036 /* Don't loose promiscuous settings */ 1037 em_set_promisc(sc); 1038 1039 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1040 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1041 1042 if (sc->hw.mac_type >= em_82543) { 1043 if (ifp->if_capenable & IFCAP_TXCSUM) 1044 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1045 else 1046 ifp->if_hwassist = 0; 1047 } 1048 1049 callout_reset(&sc->timer, hz, em_local_timer, sc); 1050 em_clear_hw_cntrs(&sc->hw); 1051#ifdef DEVICE_POLLING 1052 /* 1053 * Only enable interrupts if we are not polling, make sure 1054 * they are off otherwise. 1055 */ 1056 if (ifp->if_capenable & IFCAP_POLLING) 1057 em_disable_intr(sc); 1058 else 1059#endif /* DEVICE_POLLING */ 1060 em_enable_intr(sc); 1061 1062 /* Don't reset the phy next time init gets called */ 1063 sc->hw.phy_reset_disable = TRUE; 1064} 1065 1066static void 1067em_init(void *arg) 1068{ 1069 struct em_softc *sc = arg; 1070 1071 EM_LOCK(sc); 1072 em_init_locked(sc); 1073 EM_UNLOCK(sc); 1074} 1075 1076 1077#ifdef DEVICE_POLLING 1078/********************************************************************* 1079 * 1080 * Legacy polling routine 1081 * 1082 *********************************************************************/ 1083static void 1084em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1085{ 1086 struct em_softc *sc = ifp->if_softc; 1087 uint32_t reg_icr; 1088 1089 EM_LOCK(sc); 1090 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1091 EM_UNLOCK(sc); 1092 return; 1093 } 1094 1095 if (cmd == POLL_AND_CHECK_STATUS) { 1096 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1097 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1098 callout_stop(&sc->timer); 1099 sc->hw.get_link_status = 1; 1100 em_check_for_link(&sc->hw); 1101 em_update_link_status(sc); 1102 callout_reset(&sc->timer, hz, em_local_timer, sc); 1103 } 1104 } 1105 em_rxeof(sc, count); 1106 em_txeof(sc); 1107 1108 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1109 em_start_locked(ifp); 1110 EM_UNLOCK(sc); 1111} 1112 1113/********************************************************************* 1114 * 1115 * Legacy Interrupt Service routine 1116 * 1117 *********************************************************************/ 1118static void 1119em_intr(void *arg) 1120{ 1121 struct em_softc *sc = arg; 1122 struct ifnet *ifp; 1123 uint32_t reg_icr; 1124 1125 EM_LOCK(sc); 1126 1127 ifp = sc->ifp; 1128 1129 if (ifp->if_capenable & IFCAP_POLLING) { 1130 EM_UNLOCK(sc); 1131 return; 1132 } 1133 1134 for (;;) { 1135 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1136 if (sc->hw.mac_type >= em_82571 && 1137 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1138 break; 1139 else if (reg_icr == 0) 1140 break; 1141 1142 /* 1143 * XXX: some laptops trigger several spurious interrupts 1144 * on em(4) when in the resume cycle. The ICR register 1145 * reports all-ones value in this case. Processing such 1146 * interrupts would lead to a freeze. I don't know why. 1147 */ 1148 if (reg_icr == 0xffffffff) 1149 break; 1150 1151 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1152 em_rxeof(sc, -1); 1153 em_txeof(sc); 1154 } 1155 1156 /* Link status change */ 1157 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1158 callout_stop(&sc->timer); 1159 sc->hw.get_link_status = 1; 1160 em_check_for_link(&sc->hw); 1161 em_update_link_status(sc); 1162 callout_reset(&sc->timer, hz, em_local_timer, sc); 1163 } 1164 1165 if (reg_icr & E1000_ICR_RXO) 1166 sc->rx_overruns++; 1167 } 1168 1169 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1170 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1171 em_start_locked(ifp); 1172 1173 EM_UNLOCK(sc); 1174} 1175 1176#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1177 1178static void 1179em_handle_link(void *context, int pending) 1180{ 1181 struct em_softc *sc = context; 1182 struct ifnet *ifp; 1183 1184 ifp = sc->ifp; 1185 1186 EM_LOCK(sc); 1187 1188 callout_stop(&sc->timer); 1189 sc->hw.get_link_status = 1; 1190 em_check_for_link(&sc->hw); 1191 em_update_link_status(sc); 1192 callout_reset(&sc->timer, hz, em_local_timer, sc); 1193 EM_UNLOCK(sc); 1194} 1195 1196static void 1197em_handle_rxtx(void *context, int pending) 1198{ 1199 struct em_softc *sc = context; 1200 struct ifnet *ifp; 1201 1202 NET_LOCK_GIANT(); 1203 ifp = sc->ifp; 1204 1205 /* 1206 * TODO: 1207 * It should be possible to run the tx clean loop without the lock. 1208 */ 1209 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1210 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1211 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1212 EM_LOCK(sc); 1213 em_txeof(sc); 1214 1215 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1216 em_start_locked(ifp); 1217 EM_UNLOCK(sc); 1218 } 1219 1220 em_enable_intr(sc); 1221 NET_UNLOCK_GIANT(); 1222} 1223 1224/********************************************************************* 1225 * 1226 * Fast Interrupt Service routine 1227 * 1228 *********************************************************************/ 1229static void 1230em_intr_fast(void *arg) 1231{ 1232 struct em_softc *sc = arg; 1233 struct ifnet *ifp; 1234 uint32_t reg_icr; 1235 1236 ifp = sc->ifp; 1237 1238 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1239 1240 /* Hot eject? */ 1241 if (reg_icr == 0xffffffff) 1242 return; 1243 1244 /* Definitely not our interrupt. */ 1245 if (reg_icr == 0x0) 1246 return; 1247 1248 /* 1249 * Starting with the 82571 chip, bit 31 should be used to 1250 * determine whether the interrupt belongs to us. 1251 */ 1252 if (sc->hw.mac_type >= em_82571 && 1253 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1254 return; 1255 1256 /* 1257 * Mask interrupts until the taskqueue is finished running. This is 1258 * cheap, just assume that it is needed. This also works around the 1259 * MSI message reordering errata on certain systems. 1260 */ 1261 em_disable_intr(sc); 1262 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1263 1264 /* Link status change */ 1265 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1266 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1267 1268 if (reg_icr & E1000_ICR_RXO) 1269 sc->rx_overruns++; 1270} 1271#endif /* ! DEVICE_POLLING */ 1272 1273/********************************************************************* 1274 * 1275 * Media Ioctl callback 1276 * 1277 * This routine is called whenever the user queries the status of 1278 * the interface using ifconfig. 1279 * 1280 **********************************************************************/ 1281static void 1282em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1283{ 1284 struct em_softc *sc = ifp->if_softc; 1285 1286 INIT_DEBUGOUT("em_media_status: begin"); 1287 1288 em_check_for_link(&sc->hw); 1289 em_update_link_status(sc); 1290 1291 ifmr->ifm_status = IFM_AVALID; 1292 ifmr->ifm_active = IFM_ETHER; 1293 1294 if (!sc->link_active) 1295 return; 1296 1297 ifmr->ifm_status |= IFM_ACTIVE; 1298 1299 if (sc->hw.media_type == em_media_type_fiber) { 1300 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1301 } else { 1302 switch (sc->link_speed) { 1303 case 10: 1304 ifmr->ifm_active |= IFM_10_T; 1305 break; 1306 case 100: 1307 ifmr->ifm_active |= IFM_100_TX; 1308 break; 1309 case 1000: 1310 ifmr->ifm_active |= IFM_1000_T; 1311 break; 1312 } 1313 if (sc->link_duplex == FULL_DUPLEX) 1314 ifmr->ifm_active |= IFM_FDX; 1315 else 1316 ifmr->ifm_active |= IFM_HDX; 1317 } 1318} 1319 1320/********************************************************************* 1321 * 1322 * Media Ioctl callback 1323 * 1324 * This routine is called when the user changes speed/duplex using 1325 * media/mediopt option with ifconfig. 1326 * 1327 **********************************************************************/ 1328static int 1329em_media_change(struct ifnet *ifp) 1330{ 1331 struct em_softc *sc = ifp->if_softc; 1332 struct ifmedia *ifm = &sc->media; 1333 1334 INIT_DEBUGOUT("em_media_change: begin"); 1335 1336 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1337 return (EINVAL); 1338 1339 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1340 case IFM_AUTO: 1341 sc->hw.autoneg = DO_AUTO_NEG; 1342 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1343 break; 1344 case IFM_1000_SX: 1345 case IFM_1000_T: 1346 sc->hw.autoneg = DO_AUTO_NEG; 1347 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1348 break; 1349 case IFM_100_TX: 1350 sc->hw.autoneg = FALSE; 1351 sc->hw.autoneg_advertised = 0; 1352 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1353 sc->hw.forced_speed_duplex = em_100_full; 1354 else 1355 sc->hw.forced_speed_duplex = em_100_half; 1356 break; 1357 case IFM_10_T: 1358 sc->hw.autoneg = FALSE; 1359 sc->hw.autoneg_advertised = 0; 1360 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1361 sc->hw.forced_speed_duplex = em_10_full; 1362 else 1363 sc->hw.forced_speed_duplex = em_10_half; 1364 break; 1365 default: 1366 device_printf(sc->dev, "Unsupported media type\n"); 1367 } 1368 1369 /* As the speed/duplex settings my have changed we need to 1370 * reset the PHY. 1371 */ 1372 sc->hw.phy_reset_disable = FALSE; 1373 1374 em_init(sc); 1375 1376 return (0); 1377} 1378 1379/********************************************************************* 1380 * 1381 * This routine maps the mbufs to tx descriptors. 1382 * 1383 * return 0 on success, positive on failure 1384 **********************************************************************/ 1385static int 1386em_encap(struct em_softc *sc, struct mbuf **m_headp) 1387{ 1388 struct ifnet *ifp = sc->ifp; 1389 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1390 bus_dmamap_t map; 1391 struct em_buffer *tx_buffer; 1392 struct em_tx_desc *current_tx_desc; 1393 struct mbuf *m_head; 1394 struct m_tag *mtag; 1395 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1396 int nsegs, i, j; 1397 int error = 0; 1398 1399 m_head = *m_headp; 1400 current_tx_desc = NULL; 1401 txd_used = txd_saved = 0; 1402 1403 /* 1404 * Force a cleanup if number of TX descriptors 1405 * available hits the threshold. 1406 */ 1407 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1408 em_txeof(sc); 1409 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1410 sc->no_tx_desc_avail1++; 1411 return (ENOBUFS); 1412 } 1413 } 1414 1415 /* 1416 * Map the packet for DMA. 1417 */ 1418 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1419 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1420 segs, &nsegs, BUS_DMA_NOWAIT); 1421 map = tx_buffer->map; 1422 if (error != 0) { 1423 sc->no_tx_dma_setup++; 1424 return (error); 1425 } 1426 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1427 1428 if (nsegs > sc->num_tx_desc_avail) { 1429 sc->no_tx_desc_avail2++; 1430 error = ENOBUFS; 1431 goto encap_fail; 1432 } 1433 1434 if (ifp->if_hwassist > 0) 1435 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1436 else 1437 txd_upper = txd_lower = 0; 1438 1439 /* Find out if we are in vlan mode. */ 1440 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1441 1442 /* 1443 * When operating in promiscuous mode, hardware encapsulation for 1444 * packets is disabled. This means we have to add the vlan 1445 * encapsulation in the driver, since it will have come down from the 1446 * VLAN layer with a tag instead of a VLAN header. 1447 */ 1448 if (mtag != NULL && sc->em_insert_vlan_header) { 1449 struct ether_vlan_header *evl; 1450 struct ether_header eh; 1451 1452 m_head = m_pullup(m_head, sizeof(eh)); 1453 if (m_head == NULL) { 1454 *m_headp = NULL; 1455 error = ENOBUFS; 1456 goto encap_fail; 1457 } 1458 eh = *mtod(m_head, struct ether_header *); 1459 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1460 if (m_head == NULL) { 1461 *m_headp = NULL; 1462 error = ENOBUFS; 1463 goto encap_fail; 1464 } 1465 m_head = m_pullup(m_head, sizeof(*evl)); 1466 if (m_head == NULL) { 1467 *m_headp = NULL; 1468 error = ENOBUFS; 1469 goto encap_fail; 1470 } 1471 evl = mtod(m_head, struct ether_vlan_header *); 1472 bcopy(&eh, evl, sizeof(*evl)); 1473 evl->evl_proto = evl->evl_encap_proto; 1474 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1475 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1476 m_tag_delete(m_head, mtag); 1477 mtag = NULL; 1478 *m_headp = m_head; 1479 } 1480 1481 i = sc->next_avail_tx_desc; 1482 if (sc->pcix_82544) { 1483 txd_saved = i; 1484 txd_used = 0; 1485 } 1486 for (j = 0; j < nsegs; j++) { 1487 /* If adapter is 82544 and on PCIX bus. */ 1488 if(sc->pcix_82544) { 1489 DESC_ARRAY desc_array; 1490 uint32_t array_elements, counter; 1491 1492 /* 1493 * Check the Address and Length combination and 1494 * split the data accordingly 1495 */ 1496 array_elements = em_fill_descriptors(segs[j].ds_addr, 1497 segs[j].ds_len, &desc_array); 1498 for (counter = 0; counter < array_elements; counter++) { 1499 if (txd_used == sc->num_tx_desc_avail) { 1500 sc->next_avail_tx_desc = txd_saved; 1501 sc->no_tx_desc_avail2++; 1502 error = ENOBUFS; 1503 goto encap_fail; 1504 } 1505 tx_buffer = &sc->tx_buffer_area[i]; 1506 current_tx_desc = &sc->tx_desc_base[i]; 1507 current_tx_desc->buffer_addr = htole64( 1508 desc_array.descriptor[counter].address); 1509 current_tx_desc->lower.data = htole32( 1510 (sc->txd_cmd | txd_lower | 1511 (uint16_t)desc_array.descriptor[counter].length)); 1512 current_tx_desc->upper.data = htole32((txd_upper)); 1513 if (++i == sc->num_tx_desc) 1514 i = 0; 1515 1516 tx_buffer->m_head = NULL; 1517 txd_used++; 1518 } 1519 } else { 1520 tx_buffer = &sc->tx_buffer_area[i]; 1521 current_tx_desc = &sc->tx_desc_base[i]; 1522 1523 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1524 current_tx_desc->lower.data = htole32( 1525 sc->txd_cmd | txd_lower | segs[j].ds_len); 1526 current_tx_desc->upper.data = htole32(txd_upper); 1527 1528 if (++i == sc->num_tx_desc) 1529 i = 0; 1530 1531 tx_buffer->m_head = NULL; 1532 } 1533 } 1534 1535 sc->next_avail_tx_desc = i; 1536 if (sc->pcix_82544) 1537 sc->num_tx_desc_avail -= txd_used; 1538 else 1539 sc->num_tx_desc_avail -= nsegs; 1540 1541 if (mtag != NULL) { 1542 /* Set the vlan id. */ 1543 current_tx_desc->upper.fields.special = 1544 htole16(VLAN_TAG_VALUE(mtag)); 1545 1546 /* Tell hardware to add tag. */ 1547 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1548 } 1549 1550 tx_buffer->m_head = m_head; 1551 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1552 1553 /* 1554 * Last Descriptor of Packet needs End Of Packet (EOP). 1555 */ 1556 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1557 1558 /* 1559 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1560 * that this frame is available to transmit. 1561 */ 1562 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1564 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1565 em_82547_move_tail_locked(sc); 1566 else { 1567 E1000_WRITE_REG(&sc->hw, TDT, i); 1568 if (sc->hw.mac_type == em_82547) 1569 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1570 } 1571 1572 return (0); 1573 1574encap_fail: 1575 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1576 return (error); 1577} 1578 1579/********************************************************************* 1580 * 1581 * 82547 workaround to avoid controller hang in half-duplex environment. 1582 * The workaround is to avoid queuing a large packet that would span 1583 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1584 * in this case. We do that only when FIFO is quiescent. 1585 * 1586 **********************************************************************/ 1587static void 1588em_82547_move_tail_locked(struct em_softc *sc) 1589{ 1590 uint16_t hw_tdt; 1591 uint16_t sw_tdt; 1592 struct em_tx_desc *tx_desc; 1593 uint16_t length = 0; 1594 boolean_t eop = 0; 1595 1596 EM_LOCK_ASSERT(sc); 1597 1598 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1599 sw_tdt = sc->next_avail_tx_desc; 1600 1601 while (hw_tdt != sw_tdt) { 1602 tx_desc = &sc->tx_desc_base[hw_tdt]; 1603 length += tx_desc->lower.flags.length; 1604 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1605 if(++hw_tdt == sc->num_tx_desc) 1606 hw_tdt = 0; 1607 1608 if (eop) { 1609 if (em_82547_fifo_workaround(sc, length)) { 1610 sc->tx_fifo_wrk_cnt++; 1611 callout_reset(&sc->tx_fifo_timer, 1, 1612 em_82547_move_tail, sc); 1613 break; 1614 } 1615 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1616 em_82547_update_fifo_head(sc, length); 1617 length = 0; 1618 } 1619 } 1620} 1621 1622static void 1623em_82547_move_tail(void *arg) 1624{ 1625 struct em_softc *sc = arg; 1626 1627 EM_LOCK(sc); 1628 em_82547_move_tail_locked(sc); 1629 EM_UNLOCK(sc); 1630} 1631 1632static int 1633em_82547_fifo_workaround(struct em_softc *sc, int len) 1634{ 1635 int fifo_space, fifo_pkt_len; 1636 1637 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1638 1639 if (sc->link_duplex == HALF_DUPLEX) { 1640 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1641 1642 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1643 if (em_82547_tx_fifo_reset(sc)) 1644 return (0); 1645 else 1646 return (1); 1647 } 1648 } 1649 1650 return (0); 1651} 1652 1653static void 1654em_82547_update_fifo_head(struct em_softc *sc, int len) 1655{ 1656 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1657 1658 /* tx_fifo_head is always 16 byte aligned */ 1659 sc->tx_fifo_head += fifo_pkt_len; 1660 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1661 sc->tx_fifo_head -= sc->tx_fifo_size; 1662 } 1663} 1664 1665 1666static int 1667em_82547_tx_fifo_reset(struct em_softc *sc) 1668{ 1669 uint32_t tctl; 1670 1671 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1672 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1673 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1674 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1675 1676 /* Disable TX unit */ 1677 tctl = E1000_READ_REG(&sc->hw, TCTL); 1678 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1679 1680 /* Reset FIFO pointers */ 1681 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1682 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1683 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1684 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1685 1686 /* Re-enable TX unit */ 1687 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1688 E1000_WRITE_FLUSH(&sc->hw); 1689 1690 sc->tx_fifo_head = 0; 1691 sc->tx_fifo_reset_cnt++; 1692 1693 return (TRUE); 1694 } 1695 else { 1696 return (FALSE); 1697 } 1698} 1699 1700static void 1701em_set_promisc(struct em_softc *sc) 1702{ 1703 struct ifnet *ifp = sc->ifp; 1704 uint32_t reg_rctl; 1705 1706 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1707 1708 if (ifp->if_flags & IFF_PROMISC) { 1709 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1710 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1711 /* Disable VLAN stripping in promiscous mode 1712 * This enables bridging of vlan tagged frames to occur 1713 * and also allows vlan tags to be seen in tcpdump 1714 */ 1715 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1716 em_disable_vlans(sc); 1717 sc->em_insert_vlan_header = 1; 1718 } else if (ifp->if_flags & IFF_ALLMULTI) { 1719 reg_rctl |= E1000_RCTL_MPE; 1720 reg_rctl &= ~E1000_RCTL_UPE; 1721 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1722 sc->em_insert_vlan_header = 0; 1723 } else 1724 sc->em_insert_vlan_header = 0; 1725} 1726 1727static void 1728em_disable_promisc(struct em_softc *sc) 1729{ 1730 struct ifnet *ifp = sc->ifp; 1731 uint32_t reg_rctl; 1732 1733 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1734 1735 reg_rctl &= (~E1000_RCTL_UPE); 1736 reg_rctl &= (~E1000_RCTL_MPE); 1737 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1738 1739 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1740 em_enable_vlans(sc); 1741 sc->em_insert_vlan_header = 0; 1742} 1743 1744 1745/********************************************************************* 1746 * Multicast Update 1747 * 1748 * This routine is called whenever multicast address list is updated. 1749 * 1750 **********************************************************************/ 1751 1752static void 1753em_set_multi(struct em_softc *sc) 1754{ 1755 struct ifnet *ifp = sc->ifp; 1756 struct ifmultiaddr *ifma; 1757 uint32_t reg_rctl = 0; 1758 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1759 int mcnt = 0; 1760 1761 IOCTL_DEBUGOUT("em_set_multi: begin"); 1762 1763 if (sc->hw.mac_type == em_82542_rev2_0) { 1764 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1765 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1766 em_pci_clear_mwi(&sc->hw); 1767 reg_rctl |= E1000_RCTL_RST; 1768 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1769 msec_delay(5); 1770 } 1771 1772 IF_ADDR_LOCK(ifp); 1773 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1774 if (ifma->ifma_addr->sa_family != AF_LINK) 1775 continue; 1776 1777 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1778 break; 1779 1780 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1781 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1782 mcnt++; 1783 } 1784 IF_ADDR_UNLOCK(ifp); 1785 1786 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1787 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1788 reg_rctl |= E1000_RCTL_MPE; 1789 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1790 } else 1791 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1792 1793 if (sc->hw.mac_type == em_82542_rev2_0) { 1794 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1795 reg_rctl &= ~E1000_RCTL_RST; 1796 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1797 msec_delay(5); 1798 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1799 em_pci_set_mwi(&sc->hw); 1800 } 1801} 1802 1803 1804/********************************************************************* 1805 * Timer routine 1806 * 1807 * This routine checks for link status and updates statistics. 1808 * 1809 **********************************************************************/ 1810 1811static void 1812em_local_timer(void *arg) 1813{ 1814 struct em_softc *sc = arg; 1815 struct ifnet *ifp = sc->ifp; 1816 1817 EM_LOCK(sc); 1818 1819 em_check_for_link(&sc->hw); 1820 em_update_link_status(sc); 1821 em_update_stats_counters(sc); 1822 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1823 em_print_hw_stats(sc); 1824 em_smartspeed(sc); 1825 1826 callout_reset(&sc->timer, hz, em_local_timer, sc); 1827 1828 EM_UNLOCK(sc); 1829} 1830 1831static void 1832em_update_link_status(struct em_softc *sc) 1833{ 1834 struct ifnet *ifp = sc->ifp; 1835 device_t dev = sc->dev; 1836 1837 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1838 if (sc->link_active == 0) { 1839 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1840 &sc->link_duplex); 1841 if (bootverbose) 1842 device_printf(dev, "Link is up %d Mbps %s\n", 1843 sc->link_speed, 1844 ((sc->link_duplex == FULL_DUPLEX) ? 1845 "Full Duplex" : "Half Duplex")); 1846 sc->link_active = 1; 1847 sc->smartspeed = 0; 1848 ifp->if_baudrate = sc->link_speed * 1000000; 1849 if_link_state_change(ifp, LINK_STATE_UP); 1850 } 1851 } else { 1852 if (sc->link_active == 1) { 1853 ifp->if_baudrate = sc->link_speed = 0; 1854 sc->link_duplex = 0; 1855 if (bootverbose) 1856 device_printf(dev, "Link is Down\n"); 1857 sc->link_active = 0; 1858 if_link_state_change(ifp, LINK_STATE_DOWN); 1859 } 1860 } 1861} 1862 1863/********************************************************************* 1864 * 1865 * This routine disables all traffic on the adapter by issuing a 1866 * global reset on the MAC and deallocates TX/RX buffers. 1867 * 1868 **********************************************************************/ 1869 1870static void 1871em_stop(void *arg) 1872{ 1873 struct em_softc *sc = arg; 1874 struct ifnet *ifp = sc->ifp; 1875 1876 EM_LOCK_ASSERT(sc); 1877 1878 INIT_DEBUGOUT("em_stop: begin"); 1879 1880 em_disable_intr(sc); 1881 em_reset_hw(&sc->hw); 1882 callout_stop(&sc->timer); 1883 callout_stop(&sc->tx_fifo_timer); 1884 em_free_transmit_structures(sc); 1885 em_free_receive_structures(sc); 1886 1887 /* Tell the stack that the interface is no longer active */ 1888 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1889} 1890 1891 1892/********************************************************************* 1893 * 1894 * Determine hardware revision. 1895 * 1896 **********************************************************************/ 1897static void 1898em_identify_hardware(struct em_softc *sc) 1899{ 1900 device_t dev = sc->dev; 1901 1902 /* Make sure our PCI config space has the necessary stuff set */ 1903 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1904 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1905 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1906 device_printf(dev, "Memory Access and/or Bus Master bits " 1907 "were not set!\n"); 1908 sc->hw.pci_cmd_word |= 1909 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1910 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1911 } 1912 1913 /* Save off the information about this board */ 1914 sc->hw.vendor_id = pci_get_vendor(dev); 1915 sc->hw.device_id = pci_get_device(dev); 1916 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1917 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1918 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1919 1920 /* Identify the MAC */ 1921 if (em_set_mac_type(&sc->hw)) 1922 device_printf(dev, "Unknown MAC Type\n"); 1923 1924 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1925 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1926 sc->hw.phy_init_script = TRUE; 1927} 1928 1929static int 1930em_allocate_pci_resources(struct em_softc *sc) 1931{ 1932 device_t dev = sc->dev; 1933 int val, rid; 1934 1935 rid = PCIR_BAR(0); 1936 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1937 &rid, RF_ACTIVE); 1938 if (sc->res_memory == NULL) { 1939 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1940 return (ENXIO); 1941 } 1942 sc->osdep.mem_bus_space_tag = 1943 rman_get_bustag(sc->res_memory); 1944 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1945 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1946 1947 if (sc->hw.mac_type > em_82543) { 1948 /* Figure our where our IO BAR is ? */ 1949 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1950 val = pci_read_config(dev, rid, 4); 1951 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1952 sc->io_rid = rid; 1953 break; 1954 } 1955 rid += 4; 1956 /* check for 64bit BAR */ 1957 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1958 rid += 4; 1959 } 1960 if (rid >= PCIR_CIS) { 1961 device_printf(dev, "Unable to locate IO BAR\n"); 1962 return (ENXIO); 1963 } 1964 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1965 &sc->io_rid, RF_ACTIVE); 1966 if (sc->res_ioport == NULL) { 1967 device_printf(dev, "Unable to allocate bus resource: " 1968 "ioport\n"); 1969 return (ENXIO); 1970 } 1971 sc->hw.io_base = 0; 1972 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1973 sc->osdep.io_bus_space_handle = 1974 rman_get_bushandle(sc->res_ioport); 1975 } 1976 1977 rid = 0x0; 1978 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1979 RF_SHAREABLE | RF_ACTIVE); 1980 if (sc->res_interrupt == NULL) { 1981 device_printf(dev, "Unable to allocate bus resource: " 1982 "interrupt\n"); 1983 return (ENXIO); 1984 } 1985 1986 sc->hw.back = &sc->osdep; 1987 1988 return (0); 1989} 1990 1991int 1992em_allocate_intr(struct em_softc *sc) 1993{ 1994 device_t dev = sc->dev; 1995 int error; 1996 1997 /* Manually turn off all interrupts */ 1998 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1999 2000#ifdef DEVICE_POLLING 2001 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 2002 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 2003 &sc->int_handler_tag)) != 0) { 2004 device_printf(dev, "Failed to register interrupt handler"); 2005 return (error); 2006 } 2007#else 2008 /* 2009 * Try allocating a fast interrupt and the associated deferred 2010 * processing contexts. 2011 */ 2012 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 2013 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 2014 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2015 taskqueue_thread_enqueue, &sc->tq); 2016 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 2017 device_get_nameunit(sc->dev)); 2018 if ((error = bus_setup_intr(dev, sc->res_interrupt, 2019 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 2020 &sc->int_handler_tag)) != 0) { 2021 device_printf(dev, "Failed to register fast interrupt " 2022 "handler: %d\n", error); 2023 taskqueue_free(sc->tq); 2024 sc->tq = NULL; 2025 return (error); 2026 } 2027#endif 2028 2029 em_enable_intr(sc); 2030 return (0); 2031} 2032 2033static void 2034em_free_intr(struct em_softc *sc) 2035{ 2036 device_t dev = sc->dev; 2037 2038 if (sc->res_interrupt != NULL) { 2039 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2040 sc->int_handler_tag = NULL; 2041 } 2042 if (sc->tq != NULL) { 2043 taskqueue_drain(sc->tq, &sc->rxtx_task); 2044 taskqueue_drain(taskqueue_fast, &sc->link_task); 2045 taskqueue_free(sc->tq); 2046 sc->tq = NULL; 2047 } 2048} 2049 2050static void 2051em_free_pci_resources(struct em_softc *sc) 2052{ 2053 device_t dev = sc->dev; 2054 2055 if (sc->res_interrupt != NULL) 2056 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2057 2058 if (sc->res_memory != NULL) 2059 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2060 sc->res_memory); 2061 2062 if (sc->res_ioport != NULL) 2063 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2064 sc->res_ioport); 2065} 2066 2067/********************************************************************* 2068 * 2069 * Initialize the hardware to a configuration as specified by the 2070 * adapter structure. The controller is reset, the EEPROM is 2071 * verified, the MAC address is set, then the shared initialization 2072 * routines are called. 2073 * 2074 **********************************************************************/ 2075static int 2076em_hardware_init(struct em_softc *sc) 2077{ 2078 device_t dev = sc->dev; 2079 uint16_t rx_buffer_size; 2080 2081 INIT_DEBUGOUT("em_hardware_init: begin"); 2082 /* Issue a global reset */ 2083 em_reset_hw(&sc->hw); 2084 2085 /* When hardware is reset, fifo_head is also reset */ 2086 sc->tx_fifo_head = 0; 2087 2088 /* Make sure we have a good EEPROM before we read from it */ 2089 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2090 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2091 return (EIO); 2092 } 2093 2094 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2095 device_printf(dev, "EEPROM read error while reading part " 2096 "number\n"); 2097 return (EIO); 2098 } 2099 2100 /* 2101 * These parameters control the automatic generation (Tx) and 2102 * response (Rx) to Ethernet PAUSE frames. 2103 * - High water mark should allow for at least two frames to be 2104 * received after sending an XOFF. 2105 * - Low water mark works best when it is very near the high water mark. 2106 * This allows the receiver to restart by sending XON when it has 2107 * drained a bit. Here we use an arbitary value of 1500 which will 2108 * restart after one full frame is pulled from the buffer. There 2109 * could be several smaller frames in the buffer and if so they will 2110 * not trigger the XON until their total number reduces the buffer 2111 * by 1500. 2112 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2113 */ 2114 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2115 2116 sc->hw.fc_high_water = rx_buffer_size - 2117 roundup2(sc->hw.max_frame_size, 1024); 2118 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2119 if (sc->hw.mac_type == em_80003es2lan) 2120 sc->hw.fc_pause_time = 0xFFFF; 2121 else 2122 sc->hw.fc_pause_time = 0x1000; 2123 sc->hw.fc_send_xon = TRUE; 2124 sc->hw.fc = em_fc_full; 2125 2126 if (em_init_hw(&sc->hw) < 0) { 2127 device_printf(dev, "Hardware Initialization Failed"); 2128 return (EIO); 2129 } 2130 2131 em_check_for_link(&sc->hw); 2132 2133 return (0); 2134} 2135 2136/********************************************************************* 2137 * 2138 * Setup networking device structure and register an interface. 2139 * 2140 **********************************************************************/ 2141static void 2142em_setup_interface(device_t dev, struct em_softc *sc) 2143{ 2144 struct ifnet *ifp; 2145 INIT_DEBUGOUT("em_setup_interface: begin"); 2146 2147 ifp = sc->ifp = if_alloc(IFT_ETHER); 2148 if (ifp == NULL) 2149 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2150 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2151 ifp->if_mtu = ETHERMTU; 2152 ifp->if_init = em_init; 2153 ifp->if_softc = sc; 2154 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2155 ifp->if_ioctl = em_ioctl; 2156 ifp->if_start = em_start; 2157 ifp->if_watchdog = em_watchdog; 2158 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2159 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2160 IFQ_SET_READY(&ifp->if_snd); 2161 2162 ether_ifattach(ifp, sc->hw.mac_addr); 2163 2164 ifp->if_capabilities = ifp->if_capenable = 0; 2165 2166 if (sc->hw.mac_type >= em_82543) { 2167 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2168 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2169 } 2170 2171 /* 2172 * Tell the upper layer(s) we support long frames. 2173 */ 2174 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2175 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2176 ifp->if_capenable |= IFCAP_VLAN_MTU; 2177 2178#ifdef DEVICE_POLLING 2179 ifp->if_capabilities |= IFCAP_POLLING; 2180#endif 2181 2182 /* 2183 * Specify the media types supported by this adapter and register 2184 * callbacks to update media and link information 2185 */ 2186 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2187 if (sc->hw.media_type == em_media_type_fiber) { 2188 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2189 0, NULL); 2190 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2191 0, NULL); 2192 } else { 2193 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2194 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2195 0, NULL); 2196 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2197 0, NULL); 2198 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2199 0, NULL); 2200 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2201 0, NULL); 2202 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2203 } 2204 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2205 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2206} 2207 2208 2209/********************************************************************* 2210 * 2211 * Workaround for SmartSpeed on 82541 and 82547 controllers 2212 * 2213 **********************************************************************/ 2214static void 2215em_smartspeed(struct em_softc *sc) 2216{ 2217 uint16_t phy_tmp; 2218 2219 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2220 sc->hw.autoneg == 0 || 2221 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2222 return; 2223 2224 if (sc->smartspeed == 0) { 2225 /* If Master/Slave config fault is asserted twice, 2226 * we assume back-to-back */ 2227 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2228 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2229 return; 2230 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2231 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2232 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2233 if(phy_tmp & CR_1000T_MS_ENABLE) { 2234 phy_tmp &= ~CR_1000T_MS_ENABLE; 2235 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2236 phy_tmp); 2237 sc->smartspeed++; 2238 if(sc->hw.autoneg && 2239 !em_phy_setup_autoneg(&sc->hw) && 2240 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2241 &phy_tmp)) { 2242 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2243 MII_CR_RESTART_AUTO_NEG); 2244 em_write_phy_reg(&sc->hw, PHY_CTRL, 2245 phy_tmp); 2246 } 2247 } 2248 } 2249 return; 2250 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2251 /* If still no link, perhaps using 2/3 pair cable */ 2252 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2253 phy_tmp |= CR_1000T_MS_ENABLE; 2254 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2255 if(sc->hw.autoneg && 2256 !em_phy_setup_autoneg(&sc->hw) && 2257 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2258 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2259 MII_CR_RESTART_AUTO_NEG); 2260 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2261 } 2262 } 2263 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2264 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2265 sc->smartspeed = 0; 2266} 2267 2268 2269/* 2270 * Manage DMA'able memory. 2271 */ 2272static void 2273em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2274{ 2275 if (error) 2276 return; 2277 *(bus_addr_t *) arg = segs[0].ds_addr; 2278} 2279 2280static int 2281em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2282 int mapflags) 2283{ 2284 int error; 2285 2286 error = bus_dma_tag_create(NULL, /* parent */ 2287 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2288 BUS_SPACE_MAXADDR, /* lowaddr */ 2289 BUS_SPACE_MAXADDR, /* highaddr */ 2290 NULL, NULL, /* filter, filterarg */ 2291 size, /* maxsize */ 2292 1, /* nsegments */ 2293 size, /* maxsegsize */ 2294 0, /* flags */ 2295 NULL, /* lockfunc */ 2296 NULL, /* lockarg */ 2297 &dma->dma_tag); 2298 if (error) { 2299 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2300 __func__, error); 2301 goto fail_0; 2302 } 2303 2304 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2305 BUS_DMA_NOWAIT, &dma->dma_map); 2306 if (error) { 2307 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2308 __func__, (uintmax_t)size, error); 2309 goto fail_2; 2310 } 2311 2312 dma->dma_paddr = 0; 2313 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2314 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2315 if (error || dma->dma_paddr == 0) { 2316 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2317 __func__, error); 2318 goto fail_3; 2319 } 2320 2321 return (0); 2322 2323fail_3: 2324 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2325fail_2: 2326 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2327 bus_dma_tag_destroy(dma->dma_tag); 2328fail_0: 2329 dma->dma_map = NULL; 2330 dma->dma_tag = NULL; 2331 2332 return (error); 2333} 2334 2335static void 2336em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2337{ 2338 if (dma->dma_tag == NULL) 2339 return; 2340 if (dma->dma_map != NULL) { 2341 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2342 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2343 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2344 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2345 dma->dma_map = NULL; 2346 } 2347 bus_dma_tag_destroy(dma->dma_tag); 2348 dma->dma_tag = NULL; 2349} 2350 2351 2352/********************************************************************* 2353 * 2354 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2355 * the information needed to transmit a packet on the wire. 2356 * 2357 **********************************************************************/ 2358static int 2359em_allocate_transmit_structures(struct em_softc *sc) 2360{ 2361 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2362 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2363 if (sc->tx_buffer_area == NULL) { 2364 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2365 return (ENOMEM); 2366 } 2367 2368 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2369 2370 return (0); 2371} 2372 2373/********************************************************************* 2374 * 2375 * Allocate and initialize transmit structures. 2376 * 2377 **********************************************************************/ 2378static int 2379em_setup_transmit_structures(struct em_softc *sc) 2380{ 2381 device_t dev = sc->dev; 2382 struct em_buffer *tx_buffer; 2383 bus_size_t size; 2384 int error, i; 2385 2386 /* 2387 * Setup DMA descriptor areas. 2388 */ 2389 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2390 if ((error = bus_dma_tag_create(NULL, /* parent */ 2391 1, 0, /* alignment, bounds */ 2392 BUS_SPACE_MAXADDR, /* lowaddr */ 2393 BUS_SPACE_MAXADDR, /* highaddr */ 2394 NULL, NULL, /* filter, filterarg */ 2395 size, /* maxsize */ 2396 EM_MAX_SCATTER, /* nsegments */ 2397 size, /* maxsegsize */ 2398 0, /* flags */ 2399 NULL, /* lockfunc */ 2400 NULL, /* lockarg */ 2401 &sc->txtag)) != 0) { 2402 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2403 goto fail; 2404 } 2405 2406 if ((error = em_allocate_transmit_structures(sc)) != 0) 2407 goto fail; 2408 2409 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2410 tx_buffer = sc->tx_buffer_area; 2411 for (i = 0; i < sc->num_tx_desc; i++) { 2412 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2413 if (error != 0) { 2414 device_printf(dev, "Unable to create TX DMA map\n"); 2415 goto fail; 2416 } 2417 tx_buffer++; 2418 } 2419 2420 sc->next_avail_tx_desc = 0; 2421 sc->oldest_used_tx_desc = 0; 2422 2423 /* Set number of descriptors available */ 2424 sc->num_tx_desc_avail = sc->num_tx_desc; 2425 2426 /* Set checksum context */ 2427 sc->active_checksum_context = OFFLOAD_NONE; 2428 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2429 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2430 2431 return (0); 2432 2433fail: 2434 em_free_transmit_structures(sc); 2435 return (error); 2436} 2437 2438/********************************************************************* 2439 * 2440 * Enable transmit unit. 2441 * 2442 **********************************************************************/ 2443static void 2444em_initialize_transmit_unit(struct em_softc *sc) 2445{ 2446 uint32_t reg_tctl, tarc; 2447 uint32_t reg_tipg = 0; 2448 uint64_t bus_addr; 2449 2450 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2451 /* Setup the Base and Length of the Tx Descriptor Ring */ 2452 bus_addr = sc->txdma.dma_paddr; 2453 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2454 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2455 E1000_WRITE_REG(&sc->hw, TDLEN, 2456 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2457 2458 /* Setup the HW Tx Head and Tail descriptor pointers */ 2459 E1000_WRITE_REG(&sc->hw, TDH, 0); 2460 E1000_WRITE_REG(&sc->hw, TDT, 0); 2461 2462 2463 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2464 E1000_READ_REG(&sc->hw, TDLEN)); 2465 2466 /* Set the default values for the Tx Inter Packet Gap timer */ 2467 switch (sc->hw.mac_type) { 2468 case em_82542_rev2_0: 2469 case em_82542_rev2_1: 2470 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2471 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2472 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2473 break; 2474 case em_80003es2lan: 2475 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2476 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2477 E1000_TIPG_IPGR2_SHIFT; 2478 break; 2479 default: 2480 if (sc->hw.media_type == em_media_type_fiber) 2481 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2482 else 2483 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2484 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2485 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2486 } 2487 2488 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2489 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2490 if(sc->hw.mac_type >= em_82540) 2491 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2492 2493 /* Program the Transmit Control Register */ 2494 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2495 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2496 if (sc->hw.mac_type >= em_82571) 2497 reg_tctl |= E1000_TCTL_MULR; 2498 if (sc->link_duplex == 1) { 2499 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2500 } else { 2501 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2502 } 2503 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2504 2505 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) { 2506 tarc = E1000_READ_REG(&sc->hw, TARC0); 2507 tarc |= ((1 << 25) | (1 << 21)); 2508 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2509 tarc = E1000_READ_REG(&sc->hw, TARC1); 2510 tarc |= (1 << 25); 2511 if (reg_tctl & E1000_TCTL_MULR) 2512 tarc &= ~(1 << 28); 2513 else 2514 tarc |= (1 << 28); 2515 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2516 } else if (sc->hw.mac_type == em_80003es2lan) { 2517 tarc = E1000_READ_REG(&sc->hw, TARC0); 2518 tarc |= 1; 2519 if (sc->hw.media_type == em_media_type_internal_serdes) 2520 tarc |= (1 << 20); 2521 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2522 tarc = E1000_READ_REG(&sc->hw, TARC1); 2523 tarc |= 1; 2524 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2525 } 2526 2527 /* Setup Transmit Descriptor Settings for this adapter */ 2528 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2529 2530 if (sc->tx_int_delay.value > 0) 2531 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2532} 2533 2534/********************************************************************* 2535 * 2536 * Free all transmit related data structures. 2537 * 2538 **********************************************************************/ 2539static void 2540em_free_transmit_structures(struct em_softc *sc) 2541{ 2542 struct em_buffer *tx_buffer; 2543 int i; 2544 2545 INIT_DEBUGOUT("free_transmit_structures: begin"); 2546 2547 if (sc->tx_buffer_area != NULL) { 2548 tx_buffer = sc->tx_buffer_area; 2549 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2550 if (tx_buffer->m_head != NULL) { 2551 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2552 BUS_DMASYNC_POSTWRITE); 2553 bus_dmamap_unload(sc->txtag, 2554 tx_buffer->map); 2555 m_freem(tx_buffer->m_head); 2556 tx_buffer->m_head = NULL; 2557 } else if (tx_buffer->map != NULL) 2558 bus_dmamap_unload(sc->txtag, 2559 tx_buffer->map); 2560 if (tx_buffer->map != NULL) { 2561 bus_dmamap_destroy(sc->txtag, 2562 tx_buffer->map); 2563 tx_buffer->map = NULL; 2564 } 2565 } 2566 } 2567 if (sc->tx_buffer_area != NULL) { 2568 free(sc->tx_buffer_area, M_DEVBUF); 2569 sc->tx_buffer_area = NULL; 2570 } 2571 if (sc->txtag != NULL) { 2572 bus_dma_tag_destroy(sc->txtag); 2573 sc->txtag = NULL; 2574 } 2575} 2576 2577/********************************************************************* 2578 * 2579 * The offload context needs to be set when we transfer the first 2580 * packet of a particular protocol (TCP/UDP). We change the 2581 * context only if the protocol type changes. 2582 * 2583 **********************************************************************/ 2584static void 2585em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2586 uint32_t *txd_upper, uint32_t *txd_lower) 2587{ 2588 struct em_context_desc *TXD; 2589 struct em_buffer *tx_buffer; 2590 int curr_txd; 2591 2592 if (mp->m_pkthdr.csum_flags) { 2593 2594 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2595 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2596 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2597 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2598 return; 2599 else 2600 sc->active_checksum_context = OFFLOAD_TCP_IP; 2601 2602 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2603 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2604 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2605 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2606 return; 2607 else 2608 sc->active_checksum_context = OFFLOAD_UDP_IP; 2609 } else { 2610 *txd_upper = 0; 2611 *txd_lower = 0; 2612 return; 2613 } 2614 } else { 2615 *txd_upper = 0; 2616 *txd_lower = 0; 2617 return; 2618 } 2619 2620 /* If we reach this point, the checksum offload context 2621 * needs to be reset. 2622 */ 2623 curr_txd = sc->next_avail_tx_desc; 2624 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2625 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2626 2627 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2628 TXD->lower_setup.ip_fields.ipcso = 2629 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2630 TXD->lower_setup.ip_fields.ipcse = 2631 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2632 2633 TXD->upper_setup.tcp_fields.tucss = 2634 ETHER_HDR_LEN + sizeof(struct ip); 2635 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2636 2637 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2638 TXD->upper_setup.tcp_fields.tucso = 2639 ETHER_HDR_LEN + sizeof(struct ip) + 2640 offsetof(struct tcphdr, th_sum); 2641 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2642 TXD->upper_setup.tcp_fields.tucso = 2643 ETHER_HDR_LEN + sizeof(struct ip) + 2644 offsetof(struct udphdr, uh_sum); 2645 } 2646 2647 TXD->tcp_seg_setup.data = htole32(0); 2648 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2649 2650 tx_buffer->m_head = NULL; 2651 2652 if (++curr_txd == sc->num_tx_desc) 2653 curr_txd = 0; 2654 2655 sc->num_tx_desc_avail--; 2656 sc->next_avail_tx_desc = curr_txd; 2657} 2658 2659/********************************************************************** 2660 * 2661 * Examine each tx_buffer in the used queue. If the hardware is done 2662 * processing the packet then free associated resources. The 2663 * tx_buffer is put back on the free queue. 2664 * 2665 **********************************************************************/ 2666static void 2667em_txeof(struct em_softc *sc) 2668{ 2669 int i, num_avail; 2670 struct em_buffer *tx_buffer; 2671 struct em_tx_desc *tx_desc; 2672 struct ifnet *ifp = sc->ifp; 2673 2674 EM_LOCK_ASSERT(sc); 2675 2676 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2677 return; 2678 2679 num_avail = sc->num_tx_desc_avail; 2680 i = sc->oldest_used_tx_desc; 2681 2682 tx_buffer = &sc->tx_buffer_area[i]; 2683 tx_desc = &sc->tx_desc_base[i]; 2684 2685 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2686 BUS_DMASYNC_POSTREAD); 2687 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2688 2689 tx_desc->upper.data = 0; 2690 num_avail++; 2691 2692 if (tx_buffer->m_head) { 2693 ifp->if_opackets++; 2694 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2695 BUS_DMASYNC_POSTWRITE); 2696 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2697 2698 m_freem(tx_buffer->m_head); 2699 tx_buffer->m_head = NULL; 2700 } 2701 2702 if (++i == sc->num_tx_desc) 2703 i = 0; 2704 2705 tx_buffer = &sc->tx_buffer_area[i]; 2706 tx_desc = &sc->tx_desc_base[i]; 2707 } 2708 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2710 2711 sc->oldest_used_tx_desc = i; 2712 2713 /* 2714 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2715 * that it is OK to send packets. 2716 * If there are no pending descriptors, clear the timeout. Otherwise, 2717 * if some descriptors have been freed, restart the timeout. 2718 */ 2719 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2720 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2721 if (num_avail == sc->num_tx_desc) 2722 ifp->if_timer = 0; 2723 else if (num_avail != sc->num_tx_desc_avail) 2724 ifp->if_timer = EM_TX_TIMEOUT; 2725 } 2726 sc->num_tx_desc_avail = num_avail; 2727} 2728 2729/********************************************************************* 2730 * 2731 * Get a buffer from system mbuf buffer pool. 2732 * 2733 **********************************************************************/ 2734static int 2735em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2736{ 2737 struct ifnet *ifp = sc->ifp; 2738 bus_dma_segment_t segs[1]; 2739 struct em_buffer *rx_buffer; 2740 int error, nsegs; 2741 2742 if (mp == NULL) { 2743 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2744 if (mp == NULL) { 2745 sc->mbuf_cluster_failed++; 2746 return (ENOBUFS); 2747 } 2748 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2749 } else { 2750 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2751 mp->m_data = mp->m_ext.ext_buf; 2752 mp->m_next = NULL; 2753 } 2754 2755 if (ifp->if_mtu <= ETHERMTU) 2756 m_adj(mp, ETHER_ALIGN); 2757 2758 rx_buffer = &sc->rx_buffer_area[i]; 2759 2760 /* 2761 * Using memory from the mbuf cluster pool, invoke the 2762 * bus_dma machinery to arrange the memory mapping. 2763 */ 2764 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2765 mp, segs, &nsegs, 0); 2766 if (error != 0) { 2767 m_free(mp); 2768 return (error); 2769 } 2770 /* If nsegs is wrong then the stack is corrupt. */ 2771 KASSERT(nsegs == 1, ("Too many segments returned!")); 2772 rx_buffer->m_head = mp; 2773 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2774 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2775 2776 return (0); 2777} 2778 2779/********************************************************************* 2780 * 2781 * Allocate memory for rx_buffer structures. Since we use one 2782 * rx_buffer per received packet, the maximum number of rx_buffer's 2783 * that we'll need is equal to the number of receive descriptors 2784 * that we've allocated. 2785 * 2786 **********************************************************************/ 2787static int 2788em_allocate_receive_structures(struct em_softc *sc) 2789{ 2790 device_t dev = sc->dev; 2791 struct em_buffer *rx_buffer; 2792 int i, error; 2793 2794 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2795 M_DEVBUF, M_NOWAIT); 2796 if (sc->rx_buffer_area == NULL) { 2797 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2798 return (ENOMEM); 2799 } 2800 2801 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2802 2803 error = bus_dma_tag_create(NULL, /* parent */ 2804 1, 0, /* alignment, bounds */ 2805 BUS_SPACE_MAXADDR, /* lowaddr */ 2806 BUS_SPACE_MAXADDR, /* highaddr */ 2807 NULL, NULL, /* filter, filterarg */ 2808 MCLBYTES, /* maxsize */ 2809 1, /* nsegments */ 2810 MCLBYTES, /* maxsegsize */ 2811 BUS_DMA_ALLOCNOW, /* flags */ 2812 NULL, /* lockfunc */ 2813 NULL, /* lockarg */ 2814 &sc->rxtag); 2815 if (error) { 2816 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2817 __func__, error); 2818 goto fail; 2819 } 2820 2821 rx_buffer = sc->rx_buffer_area; 2822 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2823 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2824 &rx_buffer->map); 2825 if (error) { 2826 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2827 __func__, error); 2828 goto fail; 2829 } 2830 } 2831 2832 for (i = 0; i < sc->num_rx_desc; i++) { 2833 error = em_get_buf(i, sc, NULL); 2834 if (error) 2835 goto fail; 2836 } 2837 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2839 2840 return (0); 2841 2842fail: 2843 em_free_receive_structures(sc); 2844 return (error); 2845} 2846 2847/********************************************************************* 2848 * 2849 * Allocate and initialize receive structures. 2850 * 2851 **********************************************************************/ 2852static int 2853em_setup_receive_structures(struct em_softc *sc) 2854{ 2855 int error; 2856 2857 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2858 2859 if ((error = em_allocate_receive_structures(sc)) != 0) 2860 return (error); 2861 2862 /* Setup our descriptor pointers */ 2863 sc->next_rx_desc_to_check = 0; 2864 2865 return (0); 2866} 2867 2868/********************************************************************* 2869 * 2870 * Enable receive unit. 2871 * 2872 **********************************************************************/ 2873static void 2874em_initialize_receive_unit(struct em_softc *sc) 2875{ 2876 struct ifnet *ifp = sc->ifp; 2877 uint64_t bus_addr; 2878 uint32_t reg_rctl; 2879 uint32_t reg_rxcsum; 2880 2881 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2882 2883 /* 2884 * Make sure receives are disabled while setting 2885 * up the descriptor ring 2886 */ 2887 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2888 2889 /* Set the Receive Delay Timer Register */ 2890 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2891 2892 if(sc->hw.mac_type >= em_82540) { 2893 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2894 2895 /* 2896 * Set the interrupt throttling rate. Value is calculated 2897 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2898 */ 2899#define MAX_INTS_PER_SEC 8000 2900#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2901 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2902 } 2903 2904 /* Setup the Base and Length of the Rx Descriptor Ring */ 2905 bus_addr = sc->rxdma.dma_paddr; 2906 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2907 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2908 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2909 sizeof(struct em_rx_desc)); 2910 2911 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2912 E1000_WRITE_REG(&sc->hw, RDH, 0); 2913 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2914 2915 /* Setup the Receive Control Register */ 2916 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2917 E1000_RCTL_RDMTS_HALF | 2918 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2919 2920 if (sc->hw.tbi_compatibility_on == TRUE) 2921 reg_rctl |= E1000_RCTL_SBP; 2922 2923 2924 switch (sc->rx_buffer_len) { 2925 default: 2926 case EM_RXBUFFER_2048: 2927 reg_rctl |= E1000_RCTL_SZ_2048; 2928 break; 2929 case EM_RXBUFFER_4096: 2930 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2931 break; 2932 case EM_RXBUFFER_8192: 2933 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2934 break; 2935 case EM_RXBUFFER_16384: 2936 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2937 break; 2938 } 2939 2940 if (ifp->if_mtu > ETHERMTU) 2941 reg_rctl |= E1000_RCTL_LPE; 2942 2943 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2944 if ((sc->hw.mac_type >= em_82543) && 2945 (ifp->if_capenable & IFCAP_RXCSUM)) { 2946 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2947 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2948 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2949 } 2950 2951 /* Enable Receives */ 2952 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2953} 2954 2955/********************************************************************* 2956 * 2957 * Free receive related data structures. 2958 * 2959 **********************************************************************/ 2960static void 2961em_free_receive_structures(struct em_softc *sc) 2962{ 2963 struct em_buffer *rx_buffer; 2964 int i; 2965 2966 INIT_DEBUGOUT("free_receive_structures: begin"); 2967 2968 if (sc->rx_buffer_area != NULL) { 2969 rx_buffer = sc->rx_buffer_area; 2970 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2971 if (rx_buffer->m_head != NULL) { 2972 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2973 BUS_DMASYNC_POSTREAD); 2974 bus_dmamap_unload(sc->rxtag, 2975 rx_buffer->map); 2976 m_freem(rx_buffer->m_head); 2977 rx_buffer->m_head = NULL; 2978 } else if (rx_buffer->map != NULL) 2979 bus_dmamap_unload(sc->rxtag, 2980 rx_buffer->map); 2981 if (rx_buffer->map != NULL) { 2982 bus_dmamap_destroy(sc->rxtag, 2983 rx_buffer->map); 2984 rx_buffer->map = NULL; 2985 } 2986 } 2987 } 2988 if (sc->rx_buffer_area != NULL) { 2989 free(sc->rx_buffer_area, M_DEVBUF); 2990 sc->rx_buffer_area = NULL; 2991 } 2992 if (sc->rxtag != NULL) { 2993 bus_dma_tag_destroy(sc->rxtag); 2994 sc->rxtag = NULL; 2995 } 2996} 2997 2998/********************************************************************* 2999 * 3000 * This routine executes in interrupt context. It replenishes 3001 * the mbufs in the descriptor and sends data which has been 3002 * dma'ed into host memory to upper layer. 3003 * 3004 * We loop at most count times if count is > 0, or until done if 3005 * count < 0. 3006 * 3007 *********************************************************************/ 3008static int 3009em_rxeof(struct em_softc *sc, int count) 3010{ 3011 struct ifnet *ifp; 3012 struct mbuf *mp; 3013 uint8_t accept_frame = 0; 3014 uint8_t eop = 0; 3015 uint16_t len, desc_len, prev_len_adj; 3016 int i; 3017 3018 /* Pointer to the receive descriptor being examined. */ 3019 struct em_rx_desc *current_desc; 3020 3021 ifp = sc->ifp; 3022 i = sc->next_rx_desc_to_check; 3023 current_desc = &sc->rx_desc_base[i]; 3024 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3025 BUS_DMASYNC_POSTREAD); 3026 3027 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3028 return (0); 3029 3030 while ((current_desc->status & E1000_RXD_STAT_DD) && 3031 (count != 0) && 3032 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3033 struct mbuf *m = NULL; 3034 3035 mp = sc->rx_buffer_area[i].m_head; 3036 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3037 BUS_DMASYNC_POSTREAD); 3038 bus_dmamap_unload(sc->rxtag, 3039 sc->rx_buffer_area[i].map); 3040 3041 accept_frame = 1; 3042 prev_len_adj = 0; 3043 desc_len = le16toh(current_desc->length); 3044 if (current_desc->status & E1000_RXD_STAT_EOP) { 3045 count--; 3046 eop = 1; 3047 if (desc_len < ETHER_CRC_LEN) { 3048 len = 0; 3049 prev_len_adj = ETHER_CRC_LEN - desc_len; 3050 } else 3051 len = desc_len - ETHER_CRC_LEN; 3052 } else { 3053 eop = 0; 3054 len = desc_len; 3055 } 3056 3057 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3058 uint8_t last_byte; 3059 uint32_t pkt_len = desc_len; 3060 3061 if (sc->fmp != NULL) 3062 pkt_len += sc->fmp->m_pkthdr.len; 3063 3064 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3065 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3066 current_desc->errors, 3067 pkt_len, last_byte)) { 3068 em_tbi_adjust_stats(&sc->hw, 3069 &sc->stats, pkt_len, 3070 sc->hw.mac_addr); 3071 if (len > 0) 3072 len--; 3073 } else 3074 accept_frame = 0; 3075 } 3076 3077 if (accept_frame) { 3078 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3079 sc->dropped_pkts++; 3080 em_get_buf(i, sc, mp); 3081 if (sc->fmp != NULL) 3082 m_freem(sc->fmp); 3083 sc->fmp = NULL; 3084 sc->lmp = NULL; 3085 break; 3086 } 3087 3088 /* Assign correct length to the current fragment */ 3089 mp->m_len = len; 3090 3091 if (sc->fmp == NULL) { 3092 mp->m_pkthdr.len = len; 3093 sc->fmp = mp; /* Store the first mbuf */ 3094 sc->lmp = mp; 3095 } else { 3096 /* Chain mbuf's together */ 3097 mp->m_flags &= ~M_PKTHDR; 3098 /* 3099 * Adjust length of previous mbuf in chain if 3100 * we received less than 4 bytes in the last 3101 * descriptor. 3102 */ 3103 if (prev_len_adj > 0) { 3104 sc->lmp->m_len -= prev_len_adj; 3105 sc->fmp->m_pkthdr.len -= 3106 prev_len_adj; 3107 } 3108 sc->lmp->m_next = mp; 3109 sc->lmp = sc->lmp->m_next; 3110 sc->fmp->m_pkthdr.len += len; 3111 } 3112 3113 if (eop) { 3114 sc->fmp->m_pkthdr.rcvif = ifp; 3115 ifp->if_ipackets++; 3116 em_receive_checksum(sc, current_desc, 3117 sc->fmp); 3118#ifndef __NO_STRICT_ALIGNMENT 3119 if (ifp->if_mtu > ETHERMTU && 3120 em_fixup_rx(sc) != 0) 3121 goto skip; 3122#endif 3123 if (current_desc->status & E1000_RXD_STAT_VP) 3124 VLAN_INPUT_TAG(ifp, sc->fmp, 3125 (le16toh(current_desc->special) & 3126 E1000_RXD_SPC_VLAN_MASK)); 3127#ifndef __NO_STRICT_ALIGNMENT 3128skip: 3129#endif 3130 m = sc->fmp; 3131 sc->fmp = NULL; 3132 sc->lmp = NULL; 3133 } 3134 } else { 3135 sc->dropped_pkts++; 3136 em_get_buf(i, sc, mp); 3137 if (sc->fmp != NULL) 3138 m_freem(sc->fmp); 3139 sc->fmp = NULL; 3140 sc->lmp = NULL; 3141 } 3142 3143 /* Zero out the receive descriptors status. */ 3144 current_desc->status = 0; 3145 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3147 3148 /* Advance our pointers to the next descriptor. */ 3149 if (++i == sc->num_rx_desc) 3150 i = 0; 3151 if (m != NULL) { 3152 sc->next_rx_desc_to_check = i; 3153#ifdef DEVICE_POLLING 3154 EM_UNLOCK(sc); 3155 (*ifp->if_input)(ifp, m); 3156 EM_LOCK(sc); 3157#else 3158 (*ifp->if_input)(ifp, m); 3159#endif 3160 i = sc->next_rx_desc_to_check; 3161 } 3162 current_desc = &sc->rx_desc_base[i]; 3163 } 3164 sc->next_rx_desc_to_check = i; 3165 3166 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3167 if (--i < 0) 3168 i = sc->num_rx_desc - 1; 3169 E1000_WRITE_REG(&sc->hw, RDT, i); 3170 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3171 return (0); 3172 3173 return (1); 3174} 3175 3176#ifndef __NO_STRICT_ALIGNMENT 3177/* 3178 * When jumbo frames are enabled we should realign entire payload on 3179 * architecures with strict alignment. This is serious design mistake of 8254x 3180 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3181 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3182 * payload. On architecures without strict alignment restrictions 8254x still 3183 * performs unaligned memory access which would reduce the performance too. 3184 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3185 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3186 * existing mbuf chain. 3187 * 3188 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3189 * not used at all on architectures with strict alignment. 3190 */ 3191static int 3192em_fixup_rx(struct em_softc *sc) 3193{ 3194 struct mbuf *m, *n; 3195 int error; 3196 3197 error = 0; 3198 m = sc->fmp; 3199 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3200 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3201 m->m_data += ETHER_HDR_LEN; 3202 } else { 3203 MGETHDR(n, M_DONTWAIT, MT_DATA); 3204 if (n != NULL) { 3205 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3206 m->m_data += ETHER_HDR_LEN; 3207 m->m_len -= ETHER_HDR_LEN; 3208 n->m_len = ETHER_HDR_LEN; 3209 M_MOVE_PKTHDR(n, m); 3210 n->m_next = m; 3211 sc->fmp = n; 3212 } else { 3213 sc->dropped_pkts++; 3214 m_freem(sc->fmp); 3215 sc->fmp = NULL; 3216 error = ENOMEM; 3217 } 3218 } 3219 3220 return (error); 3221} 3222#endif 3223 3224/********************************************************************* 3225 * 3226 * Verify that the hardware indicated that the checksum is valid. 3227 * Inform the stack about the status of checksum so that stack 3228 * doesn't spend time verifying the checksum. 3229 * 3230 *********************************************************************/ 3231static void 3232em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3233 struct mbuf *mp) 3234{ 3235 /* 82543 or newer only */ 3236 if ((sc->hw.mac_type < em_82543) || 3237 /* Ignore Checksum bit is set */ 3238 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3239 mp->m_pkthdr.csum_flags = 0; 3240 return; 3241 } 3242 3243 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3244 /* Did it pass? */ 3245 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3246 /* IP Checksum Good */ 3247 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3248 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3249 3250 } else { 3251 mp->m_pkthdr.csum_flags = 0; 3252 } 3253 } 3254 3255 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3256 /* Did it pass? */ 3257 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3258 mp->m_pkthdr.csum_flags |= 3259 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3260 mp->m_pkthdr.csum_data = htons(0xffff); 3261 } 3262 } 3263} 3264 3265 3266static void 3267em_enable_vlans(struct em_softc *sc) 3268{ 3269 uint32_t ctrl; 3270 3271 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3272 3273 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3274 ctrl |= E1000_CTRL_VME; 3275 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3276} 3277 3278static void 3279em_disable_vlans(struct em_softc *sc) 3280{ 3281 uint32_t ctrl; 3282 3283 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3284 ctrl &= ~E1000_CTRL_VME; 3285 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3286} 3287 3288static void 3289em_enable_intr(struct em_softc *sc) 3290{ 3291 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3292} 3293 3294static void 3295em_disable_intr(struct em_softc *sc) 3296{ 3297 /* 3298 * The first version of 82542 had an errata where when link was forced 3299 * it would stay up even up even if the cable was disconnected. 3300 * Sequence errors were used to detect the disconnect and then the 3301 * driver would unforce the link. This code in the in the ISR. For this 3302 * to work correctly the Sequence error interrupt had to be enabled 3303 * all the time. 3304 */ 3305 3306 if (sc->hw.mac_type == em_82542_rev2_0) 3307 E1000_WRITE_REG(&sc->hw, IMC, 3308 (0xffffffff & ~E1000_IMC_RXSEQ)); 3309 else 3310 E1000_WRITE_REG(&sc->hw, IMC, 3311 0xffffffff); 3312} 3313 3314static int 3315em_is_valid_ether_addr(uint8_t *addr) 3316{ 3317 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3318 3319 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3320 return (FALSE); 3321 } 3322 3323 return (TRUE); 3324} 3325 3326void 3327em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3328{ 3329 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3330} 3331 3332void 3333em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3334{ 3335 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3336} 3337 3338void 3339em_pci_set_mwi(struct em_hw *hw) 3340{ 3341 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3342 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3343} 3344 3345void 3346em_pci_clear_mwi(struct em_hw *hw) 3347{ 3348 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3349 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3350} 3351 3352/********************************************************************* 3353* 82544 Coexistence issue workaround. 3354* There are 2 issues. 3355* 1. Transmit Hang issue. 3356* To detect this issue, following equation can be used... 3357* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3358* If SUM[3:0] is in between 1 to 4, we will have this issue. 3359* 3360* 2. DAC issue. 3361* To detect this issue, following equation can be used... 3362* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3363* If SUM[3:0] is in between 9 to c, we will have this issue. 3364* 3365* 3366* WORKAROUND: 3367* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3368* 3369*** *********************************************************************/ 3370static uint32_t 3371em_fill_descriptors (bus_addr_t address, uint32_t length, 3372 PDESC_ARRAY desc_array) 3373{ 3374 /* Since issue is sensitive to length and address.*/ 3375 /* Let us first check the address...*/ 3376 uint32_t safe_terminator; 3377 if (length <= 4) { 3378 desc_array->descriptor[0].address = address; 3379 desc_array->descriptor[0].length = length; 3380 desc_array->elements = 1; 3381 return (desc_array->elements); 3382 } 3383 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3384 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3385 if (safe_terminator == 0 || 3386 (safe_terminator > 4 && 3387 safe_terminator < 9) || 3388 (safe_terminator > 0xC && 3389 safe_terminator <= 0xF)) { 3390 desc_array->descriptor[0].address = address; 3391 desc_array->descriptor[0].length = length; 3392 desc_array->elements = 1; 3393 return (desc_array->elements); 3394 } 3395 3396 desc_array->descriptor[0].address = address; 3397 desc_array->descriptor[0].length = length - 4; 3398 desc_array->descriptor[1].address = address + (length - 4); 3399 desc_array->descriptor[1].length = 4; 3400 desc_array->elements = 2; 3401 return (desc_array->elements); 3402} 3403 3404/********************************************************************** 3405 * 3406 * Update the board statistics counters. 3407 * 3408 **********************************************************************/ 3409static void 3410em_update_stats_counters(struct em_softc *sc) 3411{ 3412 struct ifnet *ifp; 3413 3414 if(sc->hw.media_type == em_media_type_copper || 3415 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3416 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3417 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3418 } 3419 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3420 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3421 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3422 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3423 3424 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3425 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3426 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3427 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3428 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3429 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3430 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3431 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3432 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3433 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3434 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3435 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3436 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3437 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3438 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3439 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3440 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3441 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3442 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3443 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3444 3445 /* For the 64-bit byte counters the low dword must be read first. */ 3446 /* Both registers clear on the read of the high dword */ 3447 3448 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3449 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3450 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3451 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3452 3453 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3454 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3455 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3456 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3457 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3458 3459 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3460 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3461 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3462 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3463 3464 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3465 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3466 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3467 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3468 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3469 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3470 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3471 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3472 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3473 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3474 3475 if (sc->hw.mac_type >= em_82543) { 3476 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3477 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3478 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3479 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3480 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3481 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3482 } 3483 ifp = sc->ifp; 3484 3485 ifp->if_collisions = sc->stats.colc; 3486 3487 /* Rx Errors */ 3488 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3489 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3490 sc->stats.mpc + sc->stats.cexterr; 3491 3492 /* Tx Errors */ 3493 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3494 sc->watchdog_events; 3495} 3496 3497 3498/********************************************************************** 3499 * 3500 * This routine is called only when em_display_debug_stats is enabled. 3501 * This routine provides a way to take a look at important statistics 3502 * maintained by the driver and hardware. 3503 * 3504 **********************************************************************/ 3505static void 3506em_print_debug_info(struct em_softc *sc) 3507{ 3508 device_t dev = sc->dev; 3509 uint8_t *hw_addr = sc->hw.hw_addr; 3510 3511 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3512 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3513 E1000_READ_REG(&sc->hw, CTRL), 3514 E1000_READ_REG(&sc->hw, RCTL)); 3515 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3516 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3517 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3518 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3519 sc->hw.fc_high_water, 3520 sc->hw.fc_low_water); 3521 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3522 E1000_READ_REG(&sc->hw, TIDV), 3523 E1000_READ_REG(&sc->hw, TADV)); 3524 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3525 E1000_READ_REG(&sc->hw, RDTR), 3526 E1000_READ_REG(&sc->hw, RADV)); 3527 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3528 (long long)sc->tx_fifo_wrk_cnt, 3529 (long long)sc->tx_fifo_reset_cnt); 3530 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3531 E1000_READ_REG(&sc->hw, TDH), 3532 E1000_READ_REG(&sc->hw, TDT)); 3533 device_printf(dev, "Num Tx descriptors avail = %d\n", 3534 sc->num_tx_desc_avail); 3535 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3536 sc->no_tx_desc_avail1); 3537 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3538 sc->no_tx_desc_avail2); 3539 device_printf(dev, "Std mbuf failed = %ld\n", 3540 sc->mbuf_alloc_failed); 3541 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3542 sc->mbuf_cluster_failed); 3543 device_printf(dev, "Driver dropped packets = %ld\n", 3544 sc->dropped_pkts); 3545} 3546 3547static void 3548em_print_hw_stats(struct em_softc *sc) 3549{ 3550 device_t dev = sc->dev; 3551 3552 device_printf(dev, "Excessive collisions = %lld\n", 3553 (long long)sc->stats.ecol); 3554 device_printf(dev, "Symbol errors = %lld\n", 3555 (long long)sc->stats.symerrs); 3556 device_printf(dev, "Sequence errors = %lld\n", 3557 (long long)sc->stats.sec); 3558 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3559 3560 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3561 device_printf(dev, "Receive No Buffers = %lld\n", 3562 (long long)sc->stats.rnbc); 3563 device_printf(dev, "Receive length errors = %lld\n", 3564 (long long)sc->stats.rlec); 3565 device_printf(dev, "Receive errors = %lld\n", 3566 (long long)sc->stats.rxerrc); 3567 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3568 device_printf(dev, "Alignment errors = %lld\n", 3569 (long long)sc->stats.algnerrc); 3570 device_printf(dev, "Carrier extension errors = %lld\n", 3571 (long long)sc->stats.cexterr); 3572 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3573 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3574 3575 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3576 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3577 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3578 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3579 3580 device_printf(dev, "Good Packets Rcvd = %lld\n", 3581 (long long)sc->stats.gprc); 3582 device_printf(dev, "Good Packets Xmtd = %lld\n", 3583 (long long)sc->stats.gptc); 3584} 3585 3586static int 3587em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3588{ 3589 struct em_softc *sc; 3590 int error; 3591 int result; 3592 3593 result = -1; 3594 error = sysctl_handle_int(oidp, &result, 0, req); 3595 3596 if (error || !req->newptr) 3597 return (error); 3598 3599 if (result == 1) { 3600 sc = (struct em_softc *)arg1; 3601 em_print_debug_info(sc); 3602 } 3603 3604 return (error); 3605} 3606 3607 3608static int 3609em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3610{ 3611 struct em_softc *sc; 3612 int error; 3613 int result; 3614 3615 result = -1; 3616 error = sysctl_handle_int(oidp, &result, 0, req); 3617 3618 if (error || !req->newptr) 3619 return (error); 3620 3621 if (result == 1) { 3622 sc = (struct em_softc *)arg1; 3623 em_print_hw_stats(sc); 3624 } 3625 3626 return (error); 3627} 3628 3629static int 3630em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3631{ 3632 struct em_int_delay_info *info; 3633 struct em_softc *sc; 3634 uint32_t regval; 3635 int error; 3636 int usecs; 3637 int ticks; 3638 3639 info = (struct em_int_delay_info *)arg1; 3640 usecs = info->value; 3641 error = sysctl_handle_int(oidp, &usecs, 0, req); 3642 if (error != 0 || req->newptr == NULL) 3643 return (error); 3644 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3645 return (EINVAL); 3646 info->value = usecs; 3647 ticks = E1000_USECS_TO_TICKS(usecs); 3648 3649 sc = info->sc; 3650 3651 EM_LOCK(sc); 3652 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3653 regval = (regval & ~0xffff) | (ticks & 0xffff); 3654 /* Handle a few special cases. */ 3655 switch (info->offset) { 3656 case E1000_RDTR: 3657 case E1000_82542_RDTR: 3658 regval |= E1000_RDT_FPDB; 3659 break; 3660 case E1000_TIDV: 3661 case E1000_82542_TIDV: 3662 if (ticks == 0) { 3663 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3664 /* Don't write 0 into the TIDV register. */ 3665 regval++; 3666 } else 3667 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3668 break; 3669 } 3670 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3671 EM_UNLOCK(sc); 3672 return (0); 3673} 3674 3675static void 3676em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3677 const char *description, struct em_int_delay_info *info, 3678 int offset, int value) 3679{ 3680 info->sc = sc; 3681 info->offset = offset; 3682 info->value = value; 3683 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3684 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3685 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3686 info, 0, em_sysctl_int_delay, "I", description); 3687} 3688 3689#ifndef DEVICE_POLLING 3690static void 3691em_add_int_process_limit(struct em_softc *sc, const char *name, 3692 const char *description, int *limit, int value) 3693{ 3694 *limit = value; 3695 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3696 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3697 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3698} 3699#endif 3700