if_em.c revision 160518
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 160518 2006-07-20 04:01:54Z yongari $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 5.1.5"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 143 PCI_ANY_ID, PCI_ANY_ID, 0}, 144 145 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 149 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 153 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 158 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 159 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 162 PCI_ANY_ID, PCI_ANY_ID, 0}, 163 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 164 PCI_ANY_ID, PCI_ANY_ID, 0}, 165 166 /* required last entry */ 167 { 0, 0, 0, 0, 0} 168}; 169 170/********************************************************************* 171 * Table of branding strings for all supported NICs. 172 *********************************************************************/ 173 174static char *em_strings[] = { 175 "Intel(R) PRO/1000 Network Connection" 176}; 177 178/********************************************************************* 179 * Function prototypes 180 *********************************************************************/ 181static int em_probe(device_t); 182static int em_attach(device_t); 183static int em_detach(device_t); 184static int em_shutdown(device_t); 185static int em_suspend(device_t); 186static int em_resume(device_t); 187static void em_start(struct ifnet *); 188static void em_start_locked(struct ifnet *ifp); 189static int em_ioctl(struct ifnet *, u_long, caddr_t); 190static void em_watchdog(struct ifnet *); 191static void em_init(void *); 192static void em_init_locked(struct em_softc *); 193static void em_stop(void *); 194static void em_media_status(struct ifnet *, struct ifmediareq *); 195static int em_media_change(struct ifnet *); 196static void em_identify_hardware(struct em_softc *); 197static int em_allocate_pci_resources(struct em_softc *); 198static int em_allocate_intr(struct em_softc *); 199static void em_free_intr(struct em_softc *); 200static void em_free_pci_resources(struct em_softc *); 201static void em_local_timer(void *); 202static int em_hardware_init(struct em_softc *); 203static void em_setup_interface(device_t, struct em_softc *); 204static int em_setup_transmit_structures(struct em_softc *); 205static void em_initialize_transmit_unit(struct em_softc *); 206static int em_setup_receive_structures(struct em_softc *); 207static void em_initialize_receive_unit(struct em_softc *); 208static void em_enable_intr(struct em_softc *); 209static void em_disable_intr(struct em_softc *); 210static void em_free_transmit_structures(struct em_softc *); 211static void em_free_receive_structures(struct em_softc *); 212static void em_update_stats_counters(struct em_softc *); 213static void em_txeof(struct em_softc *); 214static int em_allocate_receive_structures(struct em_softc *); 215static int em_allocate_transmit_structures(struct em_softc *); 216static int em_rxeof(struct em_softc *, int); 217#ifndef __NO_STRICT_ALIGNMENT 218static int em_fixup_rx(struct em_softc *); 219#endif 220static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 221 struct mbuf *); 222static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 223 uint32_t *, uint32_t *); 224static void em_set_promisc(struct em_softc *); 225static void em_disable_promisc(struct em_softc *); 226static void em_set_multi(struct em_softc *); 227static void em_print_hw_stats(struct em_softc *); 228static void em_update_link_status(struct em_softc *); 229static int em_get_buf(int i, struct em_softc *, struct mbuf *); 230static void em_enable_vlans(struct em_softc *); 231static void em_disable_vlans(struct em_softc *); 232static int em_encap(struct em_softc *, struct mbuf **); 233static void em_smartspeed(struct em_softc *); 234static int em_82547_fifo_workaround(struct em_softc *, int); 235static void em_82547_update_fifo_head(struct em_softc *, int); 236static int em_82547_tx_fifo_reset(struct em_softc *); 237static void em_82547_move_tail(void *arg); 238static void em_82547_move_tail_locked(struct em_softc *); 239static int em_dma_malloc(struct em_softc *, bus_size_t, 240 struct em_dma_alloc *, int); 241static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 242static void em_print_debug_info(struct em_softc *); 243static int em_is_valid_ether_addr(uint8_t *); 244static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 245static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 246static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 247 PDESC_ARRAY desc_array); 248static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 249static void em_add_int_delay_sysctl(struct em_softc *, const char *, 250 const char *, struct em_int_delay_info *, int, int); 251 252/* 253 * Fast interrupt handler and legacy ithread/polling modes are 254 * mutually exclusive. 255 */ 256#ifdef DEVICE_POLLING 257static poll_handler_t em_poll; 258static void em_intr(void *); 259#else 260static void em_intr_fast(void *); 261static void em_add_int_process_limit(struct em_softc *, const char *, 262 const char *, int *, int); 263static void em_handle_rxtx(void *context, int pending); 264static void em_handle_link(void *context, int pending); 265#endif 266 267/********************************************************************* 268 * FreeBSD Device Interface Entry Points 269 *********************************************************************/ 270 271static device_method_t em_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, em_probe), 274 DEVMETHOD(device_attach, em_attach), 275 DEVMETHOD(device_detach, em_detach), 276 DEVMETHOD(device_shutdown, em_shutdown), 277 DEVMETHOD(device_suspend, em_suspend), 278 DEVMETHOD(device_resume, em_resume), 279 {0, 0} 280}; 281 282static driver_t em_driver = { 283 "em", em_methods, sizeof(struct em_softc), 284}; 285 286static devclass_t em_devclass; 287DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 288MODULE_DEPEND(em, pci, 1, 1, 1); 289MODULE_DEPEND(em, ether, 1, 1, 1); 290 291/********************************************************************* 292 * Tunable default values. 293 *********************************************************************/ 294 295#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 296#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 297 298static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 299static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 300static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 301static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 302static int em_rxd = EM_DEFAULT_RXD; 303static int em_txd = EM_DEFAULT_TXD; 304 305TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 306TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 307TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 308TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 309TUNABLE_INT("hw.em.rxd", &em_rxd); 310TUNABLE_INT("hw.em.txd", &em_txd); 311#ifndef DEVICE_POLLING 312static int em_rx_process_limit = 100; 313TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 314#endif 315 316/********************************************************************* 317 * Device identification routine 318 * 319 * em_probe determines if the driver should be loaded on 320 * adapter based on PCI vendor/device id of the adapter. 321 * 322 * return BUS_PROBE_DEFAULT on success, positive on failure 323 *********************************************************************/ 324 325static int 326em_probe(device_t dev) 327{ 328 char adapter_name[60]; 329 uint16_t pci_vendor_id = 0; 330 uint16_t pci_device_id = 0; 331 uint16_t pci_subvendor_id = 0; 332 uint16_t pci_subdevice_id = 0; 333 em_vendor_info_t *ent; 334 335 INIT_DEBUGOUT("em_probe: begin"); 336 337 pci_vendor_id = pci_get_vendor(dev); 338 if (pci_vendor_id != EM_VENDOR_ID) 339 return (ENXIO); 340 341 pci_device_id = pci_get_device(dev); 342 pci_subvendor_id = pci_get_subvendor(dev); 343 pci_subdevice_id = pci_get_subdevice(dev); 344 345 ent = em_vendor_info_array; 346 while (ent->vendor_id != 0) { 347 if ((pci_vendor_id == ent->vendor_id) && 348 (pci_device_id == ent->device_id) && 349 350 ((pci_subvendor_id == ent->subvendor_id) || 351 (ent->subvendor_id == PCI_ANY_ID)) && 352 353 ((pci_subdevice_id == ent->subdevice_id) || 354 (ent->subdevice_id == PCI_ANY_ID))) { 355 sprintf(adapter_name, "%s %s", 356 em_strings[ent->index], 357 em_driver_version); 358 device_set_desc_copy(dev, adapter_name); 359 return (BUS_PROBE_DEFAULT); 360 } 361 ent++; 362 } 363 364 return (ENXIO); 365} 366 367/********************************************************************* 368 * Device initialization routine 369 * 370 * The attach entry point is called when the driver is being loaded. 371 * This routine identifies the type of hardware, allocates all resources 372 * and initializes the hardware. 373 * 374 * return 0 on success, positive on failure 375 *********************************************************************/ 376 377static int 378em_attach(device_t dev) 379{ 380 struct em_softc *sc; 381 int tsize, rsize; 382 int error = 0; 383 384 INIT_DEBUGOUT("em_attach: begin"); 385 386 sc = device_get_softc(dev); 387 sc->dev = sc->osdep.dev = dev; 388 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 389 390 /* SYSCTL stuff */ 391 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 392 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 393 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 394 em_sysctl_debug_info, "I", "Debug Information"); 395 396 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 397 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 398 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 399 em_sysctl_stats, "I", "Statistics"); 400 401 callout_init(&sc->timer, CALLOUT_MPSAFE); 402 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 403 404 /* Determine hardware revision */ 405 em_identify_hardware(sc); 406 407 /* Set up some sysctls for the tunable interrupt delays */ 408 em_add_int_delay_sysctl(sc, "rx_int_delay", 409 "receive interrupt delay in usecs", &sc->rx_int_delay, 410 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 411 em_add_int_delay_sysctl(sc, "tx_int_delay", 412 "transmit interrupt delay in usecs", &sc->tx_int_delay, 413 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 414 if (sc->hw.mac_type >= em_82540) { 415 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 416 "receive interrupt delay limit in usecs", 417 &sc->rx_abs_int_delay, 418 E1000_REG_OFFSET(&sc->hw, RADV), 419 em_rx_abs_int_delay_dflt); 420 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 421 "transmit interrupt delay limit in usecs", 422 &sc->tx_abs_int_delay, 423 E1000_REG_OFFSET(&sc->hw, TADV), 424 em_tx_abs_int_delay_dflt); 425 } 426 427#ifndef DEVICE_POLLING 428 /* Sysctls for limiting the amount of work done in the taskqueue */ 429 em_add_int_process_limit(sc, "rx_processing_limit", 430 "max number of rx packets to process", &sc->rx_process_limit, 431 em_rx_process_limit); 432#endif 433 434 /* 435 * Validate number of transmit and receive descriptors. It 436 * must not exceed hardware maximum, and must be multiple 437 * of E1000_DBA_ALIGN. 438 */ 439 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 440 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 441 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 442 (em_txd < EM_MIN_TXD)) { 443 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 444 EM_DEFAULT_TXD, em_txd); 445 sc->num_tx_desc = EM_DEFAULT_TXD; 446 } else 447 sc->num_tx_desc = em_txd; 448 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 449 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 450 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 451 (em_rxd < EM_MIN_RXD)) { 452 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 453 EM_DEFAULT_RXD, em_rxd); 454 sc->num_rx_desc = EM_DEFAULT_RXD; 455 } else 456 sc->num_rx_desc = em_rxd; 457 458 sc->hw.autoneg = DO_AUTO_NEG; 459 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 460 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 461 sc->hw.tbi_compatibility_en = TRUE; 462 sc->rx_buffer_len = EM_RXBUFFER_2048; 463 464 sc->hw.phy_init_script = 1; 465 sc->hw.phy_reset_disable = FALSE; 466 467#ifndef EM_MASTER_SLAVE 468 sc->hw.master_slave = em_ms_hw_default; 469#else 470 sc->hw.master_slave = EM_MASTER_SLAVE; 471#endif 472 /* 473 * Set the max frame size assuming standard ethernet 474 * sized frames. 475 */ 476 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 477 478 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 479 480 /* 481 * This controls when hardware reports transmit completion 482 * status. 483 */ 484 sc->hw.report_tx_early = 1; 485 if (em_allocate_pci_resources(sc)) { 486 device_printf(dev, "Allocation of PCI resources failed\n"); 487 error = ENXIO; 488 goto err_pci; 489 } 490 491 /* Initialize eeprom parameters */ 492 em_init_eeprom_params(&sc->hw); 493 494 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 495 E1000_DBA_ALIGN); 496 497 /* Allocate Transmit Descriptor ring */ 498 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 499 device_printf(dev, "Unable to allocate tx_desc memory\n"); 500 error = ENOMEM; 501 goto err_tx_desc; 502 } 503 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 504 505 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 506 E1000_DBA_ALIGN); 507 508 /* Allocate Receive Descriptor ring */ 509 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 510 device_printf(dev, "Unable to allocate rx_desc memory\n"); 511 error = ENOMEM; 512 goto err_rx_desc; 513 } 514 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 515 516 /* Initialize the hardware */ 517 if (em_hardware_init(sc)) { 518 device_printf(dev, "Unable to initialize the hardware\n"); 519 error = EIO; 520 goto err_hw_init; 521 } 522 523 /* Copy the permanent MAC address out of the EEPROM */ 524 if (em_read_mac_addr(&sc->hw) < 0) { 525 device_printf(dev, "EEPROM read error while reading MAC" 526 " address\n"); 527 error = EIO; 528 goto err_hw_init; 529 } 530 531 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 532 device_printf(dev, "Invalid MAC address\n"); 533 error = EIO; 534 goto err_hw_init; 535 } 536 537 /* Setup OS specific network interface */ 538 em_setup_interface(dev, sc); 539 540 em_allocate_intr(sc); 541 542 /* Initialize statistics */ 543 em_clear_hw_cntrs(&sc->hw); 544 em_update_stats_counters(sc); 545 sc->hw.get_link_status = 1; 546 em_update_link_status(sc); 547 548 /* Indicate SOL/IDER usage */ 549 if (em_check_phy_reset_block(&sc->hw)) 550 device_printf(dev, 551 "PHY reset is blocked due to SOL/IDER session.\n"); 552 553 /* Identify 82544 on PCIX */ 554 em_get_bus_info(&sc->hw); 555 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 556 sc->pcix_82544 = TRUE; 557 else 558 sc->pcix_82544 = FALSE; 559 560 INIT_DEBUGOUT("em_attach: end"); 561 562 return (0); 563 564err_hw_init: 565 em_dma_free(sc, &sc->rxdma); 566err_rx_desc: 567 em_dma_free(sc, &sc->txdma); 568err_tx_desc: 569err_pci: 570 em_free_intr(sc); 571 em_free_pci_resources(sc); 572 EM_LOCK_DESTROY(sc); 573 574 return (error); 575} 576 577/********************************************************************* 578 * Device removal routine 579 * 580 * The detach entry point is called when the driver is being removed. 581 * This routine stops the adapter and deallocates all the resources 582 * that were allocated for driver operation. 583 * 584 * return 0 on success, positive on failure 585 *********************************************************************/ 586 587static int 588em_detach(device_t dev) 589{ 590 struct em_softc *sc = device_get_softc(dev); 591 struct ifnet *ifp = sc->ifp; 592 593 INIT_DEBUGOUT("em_detach: begin"); 594 595#ifdef DEVICE_POLLING 596 if (ifp->if_capenable & IFCAP_POLLING) 597 ether_poll_deregister(ifp); 598#endif 599 600 em_free_intr(sc); 601 EM_LOCK(sc); 602 sc->in_detach = 1; 603 em_stop(sc); 604 em_phy_hw_reset(&sc->hw); 605 EM_UNLOCK(sc); 606 ether_ifdetach(sc->ifp); 607 608 em_free_pci_resources(sc); 609 bus_generic_detach(dev); 610 if_free(ifp); 611 612 /* Free Transmit Descriptor ring */ 613 if (sc->tx_desc_base) { 614 em_dma_free(sc, &sc->txdma); 615 sc->tx_desc_base = NULL; 616 } 617 618 /* Free Receive Descriptor ring */ 619 if (sc->rx_desc_base) { 620 em_dma_free(sc, &sc->rxdma); 621 sc->rx_desc_base = NULL; 622 } 623 624 EM_LOCK_DESTROY(sc); 625 626 return (0); 627} 628 629/********************************************************************* 630 * 631 * Shutdown entry point 632 * 633 **********************************************************************/ 634 635static int 636em_shutdown(device_t dev) 637{ 638 struct em_softc *sc = device_get_softc(dev); 639 EM_LOCK(sc); 640 em_stop(sc); 641 EM_UNLOCK(sc); 642 return (0); 643} 644 645/* 646 * Suspend/resume device methods. 647 */ 648static int 649em_suspend(device_t dev) 650{ 651 struct em_softc *sc = device_get_softc(dev); 652 653 EM_LOCK(sc); 654 em_stop(sc); 655 EM_UNLOCK(sc); 656 657 return bus_generic_suspend(dev); 658} 659 660static int 661em_resume(device_t dev) 662{ 663 struct em_softc *sc = device_get_softc(dev); 664 struct ifnet *ifp = sc->ifp; 665 666 EM_LOCK(sc); 667 em_init_locked(sc); 668 if ((ifp->if_flags & IFF_UP) && 669 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 670 em_start_locked(ifp); 671 EM_UNLOCK(sc); 672 673 return bus_generic_resume(dev); 674} 675 676 677/********************************************************************* 678 * Transmit entry point 679 * 680 * em_start is called by the stack to initiate a transmit. 681 * The driver will remain in this routine as long as there are 682 * packets to transmit and transmit resources are available. 683 * In case resources are not available stack is notified and 684 * the packet is requeued. 685 **********************************************************************/ 686 687static void 688em_start_locked(struct ifnet *ifp) 689{ 690 struct em_softc *sc = ifp->if_softc; 691 struct mbuf *m_head; 692 693 EM_LOCK_ASSERT(sc); 694 695 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 696 IFF_DRV_RUNNING) 697 return; 698 if (!sc->link_active) 699 return; 700 701 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 702 703 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 704 if (m_head == NULL) 705 break; 706 /* 707 * em_encap() can modify our pointer, and or make it NULL on 708 * failure. In that event, we can't requeue. 709 */ 710 if (em_encap(sc, &m_head)) { 711 if (m_head == NULL) 712 break; 713 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 714 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 715 break; 716 } 717 718 /* Send a copy of the frame to the BPF listener */ 719 BPF_MTAP(ifp, m_head); 720 721 /* Set timeout in case hardware has problems transmitting. */ 722 ifp->if_timer = EM_TX_TIMEOUT; 723 } 724} 725 726static void 727em_start(struct ifnet *ifp) 728{ 729 struct em_softc *sc = ifp->if_softc; 730 731 EM_LOCK(sc); 732 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 733 em_start_locked(ifp); 734 EM_UNLOCK(sc); 735} 736 737/********************************************************************* 738 * Ioctl entry point 739 * 740 * em_ioctl is called when the user wants to configure the 741 * interface. 742 * 743 * return 0 on success, positive on failure 744 **********************************************************************/ 745 746static int 747em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 748{ 749 struct em_softc *sc = ifp->if_softc; 750 struct ifreq *ifr = (struct ifreq *)data; 751 int error = 0; 752 753 if (sc->in_detach) 754 return (error); 755 756 switch (command) { 757 case SIOCSIFADDR: 758 case SIOCGIFADDR: 759 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 760 ether_ioctl(ifp, command, data); 761 break; 762 case SIOCSIFMTU: 763 { 764 int max_frame_size; 765 uint16_t eeprom_data = 0; 766 767 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 768 769 EM_LOCK(sc); 770 switch (sc->hw.mac_type) { 771 case em_82573: 772 /* 773 * 82573 only supports jumbo frames 774 * if ASPM is disabled. 775 */ 776 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1, 777 &eeprom_data); 778 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 779 max_frame_size = ETHER_MAX_LEN; 780 break; 781 } 782 /* Allow Jumbo frames - fall thru */ 783 case em_82571: 784 case em_82572: 785 case em_80003es2lan: /* Limit Jumbo Frame size */ 786 max_frame_size = 9234; 787 break; 788 default: 789 max_frame_size = MAX_JUMBO_FRAME_SIZE; 790 } 791 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 792 ETHER_CRC_LEN) { 793 EM_UNLOCK(sc); 794 error = EINVAL; 795 break; 796 } 797 798 ifp->if_mtu = ifr->ifr_mtu; 799 sc->hw.max_frame_size = 800 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 801 em_init_locked(sc); 802 EM_UNLOCK(sc); 803 break; 804 } 805 case SIOCSIFFLAGS: 806 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 807 EM_LOCK(sc); 808 if (ifp->if_flags & IFF_UP) { 809 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 810 em_init_locked(sc); 811 } 812 813 em_disable_promisc(sc); 814 em_set_promisc(sc); 815 } else { 816 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 817 em_stop(sc); 818 } 819 } 820 EM_UNLOCK(sc); 821 break; 822 case SIOCADDMULTI: 823 case SIOCDELMULTI: 824 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 825 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 826 EM_LOCK(sc); 827 em_disable_intr(sc); 828 em_set_multi(sc); 829 if (sc->hw.mac_type == em_82542_rev2_0) { 830 em_initialize_receive_unit(sc); 831 } 832#ifdef DEVICE_POLLING 833 if (!(ifp->if_capenable & IFCAP_POLLING)) 834#endif 835 em_enable_intr(sc); 836 EM_UNLOCK(sc); 837 } 838 break; 839 case SIOCSIFMEDIA: 840 case SIOCGIFMEDIA: 841 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 842 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 843 break; 844 case SIOCSIFCAP: 845 { 846 int mask, reinit; 847 848 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 849 reinit = 0; 850 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 851#ifdef DEVICE_POLLING 852 if (mask & IFCAP_POLLING) { 853 if (ifr->ifr_reqcap & IFCAP_POLLING) { 854 error = ether_poll_register(em_poll, ifp); 855 if (error) 856 return (error); 857 EM_LOCK(sc); 858 em_disable_intr(sc); 859 ifp->if_capenable |= IFCAP_POLLING; 860 EM_UNLOCK(sc); 861 } else { 862 error = ether_poll_deregister(ifp); 863 /* Enable interrupt even in error case */ 864 EM_LOCK(sc); 865 em_enable_intr(sc); 866 ifp->if_capenable &= ~IFCAP_POLLING; 867 EM_UNLOCK(sc); 868 } 869 } 870#endif 871 if (mask & IFCAP_HWCSUM) { 872 ifp->if_capenable ^= IFCAP_HWCSUM; 873 reinit = 1; 874 } 875 if (mask & IFCAP_VLAN_HWTAGGING) { 876 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 877 reinit = 1; 878 } 879 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 880 em_init(sc); 881 VLAN_CAPABILITIES(ifp); 882 break; 883 } 884 default: 885 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 886 error = EINVAL; 887 } 888 889 return (error); 890} 891 892/********************************************************************* 893 * Watchdog entry point 894 * 895 * This routine is called whenever hardware quits transmitting. 896 * 897 **********************************************************************/ 898 899static void 900em_watchdog(struct ifnet *ifp) 901{ 902 struct em_softc *sc = ifp->if_softc; 903 904 EM_LOCK(sc); 905 /* If we are in this routine because of pause frames, then 906 * don't reset the hardware. 907 */ 908 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 909 ifp->if_timer = EM_TX_TIMEOUT; 910 EM_UNLOCK(sc); 911 return; 912 } 913 914 if (em_check_for_link(&sc->hw) == 0) 915 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 916 917 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 918 sc->watchdog_events++; 919 920 em_init_locked(sc); 921 EM_UNLOCK(sc); 922} 923 924/********************************************************************* 925 * Init entry point 926 * 927 * This routine is used in two ways. It is used by the stack as 928 * init entry point in network interface structure. It is also used 929 * by the driver as a hw/sw initialization routine to get to a 930 * consistent state. 931 * 932 * return 0 on success, positive on failure 933 **********************************************************************/ 934 935static void 936em_init_locked(struct em_softc *sc) 937{ 938 struct ifnet *ifp = sc->ifp; 939 device_t dev = sc->dev; 940 uint32_t pba; 941 942 INIT_DEBUGOUT("em_init: begin"); 943 944 EM_LOCK_ASSERT(sc); 945 946 em_stop(sc); 947 948 /* 949 * Packet Buffer Allocation (PBA) 950 * Writing PBA sets the receive portion of the buffer 951 * the remainder is used for the transmit buffer. 952 */ 953 switch (sc->hw.mac_type) { 954 case em_82547: 955 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 956 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 957 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 958 else 959 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 960 sc->tx_fifo_head = 0; 961 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 962 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 963 break; 964 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */ 965 case em_82571: /* 82571: Total Packet Buffer is 48K */ 966 case em_82572: /* 82572: Total Packet Buffer is 48K */ 967 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 968 break; 969 case em_82573: /* 82573: Total Packet Buffer is 32K */ 970 /* Jumbo frames not supported */ 971 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 972 break; 973 default: 974 /* Devices before 82547 had a Packet Buffer of 64K. */ 975 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 976 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 977 else 978 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 979 } 980 981 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 982 E1000_WRITE_REG(&sc->hw, PBA, pba); 983 984 /* Get the latest mac address, User can use a LAA */ 985 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 986 987 /* Initialize the hardware */ 988 if (em_hardware_init(sc)) { 989 device_printf(dev, "Unable to initialize the hardware\n"); 990 return; 991 } 992 em_update_link_status(sc); 993 994 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 995 em_enable_vlans(sc); 996 997 /* Prepare transmit descriptors and buffers */ 998 if (em_setup_transmit_structures(sc)) { 999 device_printf(dev, "Could not setup transmit structures\n"); 1000 em_stop(sc); 1001 return; 1002 } 1003 em_initialize_transmit_unit(sc); 1004 1005 /* Setup Multicast table */ 1006 em_set_multi(sc); 1007 1008 /* Prepare receive descriptors and buffers */ 1009 if (em_setup_receive_structures(sc)) { 1010 device_printf(dev, "Could not setup receive structures\n"); 1011 em_stop(sc); 1012 return; 1013 } 1014 em_initialize_receive_unit(sc); 1015 1016 /* Don't loose promiscuous settings */ 1017 em_set_promisc(sc); 1018 1019 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1020 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1021 1022 if (sc->hw.mac_type >= em_82543) { 1023 if (ifp->if_capenable & IFCAP_TXCSUM) 1024 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1025 else 1026 ifp->if_hwassist = 0; 1027 } 1028 1029 callout_reset(&sc->timer, hz, em_local_timer, sc); 1030 em_clear_hw_cntrs(&sc->hw); 1031#ifdef DEVICE_POLLING 1032 /* 1033 * Only enable interrupts if we are not polling, make sure 1034 * they are off otherwise. 1035 */ 1036 if (ifp->if_capenable & IFCAP_POLLING) 1037 em_disable_intr(sc); 1038 else 1039#endif /* DEVICE_POLLING */ 1040 em_enable_intr(sc); 1041 1042 /* Don't reset the phy next time init gets called */ 1043 sc->hw.phy_reset_disable = TRUE; 1044} 1045 1046static void 1047em_init(void *arg) 1048{ 1049 struct em_softc *sc = arg; 1050 1051 EM_LOCK(sc); 1052 em_init_locked(sc); 1053 EM_UNLOCK(sc); 1054} 1055 1056 1057#ifdef DEVICE_POLLING 1058/********************************************************************* 1059 * 1060 * Legacy polling routine 1061 * 1062 *********************************************************************/ 1063static void 1064em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1065{ 1066 struct em_softc *sc = ifp->if_softc; 1067 uint32_t reg_icr; 1068 1069 EM_LOCK(sc); 1070 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1071 EM_UNLOCK(sc); 1072 return; 1073 } 1074 1075 if (cmd == POLL_AND_CHECK_STATUS) { 1076 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1077 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1078 callout_stop(&sc->timer); 1079 sc->hw.get_link_status = 1; 1080 em_check_for_link(&sc->hw); 1081 em_update_link_status(sc); 1082 callout_reset(&sc->timer, hz, em_local_timer, sc); 1083 } 1084 } 1085 em_rxeof(sc, count); 1086 em_txeof(sc); 1087 1088 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1089 em_start_locked(ifp); 1090 EM_UNLOCK(sc); 1091} 1092 1093/********************************************************************* 1094 * 1095 * Legacy Interrupt Service routine 1096 * 1097 *********************************************************************/ 1098static void 1099em_intr(void *arg) 1100{ 1101 struct em_softc *sc = arg; 1102 struct ifnet *ifp; 1103 uint32_t reg_icr; 1104 1105 EM_LOCK(sc); 1106 1107 ifp = sc->ifp; 1108 1109 if (ifp->if_capenable & IFCAP_POLLING) { 1110 EM_UNLOCK(sc); 1111 return; 1112 } 1113 1114 for (;;) { 1115 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1116 if (sc->hw.mac_type >= em_82571 && 1117 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1118 break; 1119 else if (reg_icr == 0) 1120 break; 1121 1122 /* 1123 * XXX: some laptops trigger several spurious interrupts 1124 * on em(4) when in the resume cycle. The ICR register 1125 * reports all-ones value in this case. Processing such 1126 * interrupts would lead to a freeze. I don't know why. 1127 */ 1128 if (reg_icr == 0xffffffff) 1129 break; 1130 1131 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1132 em_rxeof(sc, -1); 1133 em_txeof(sc); 1134 } 1135 1136 /* Link status change */ 1137 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1138 callout_stop(&sc->timer); 1139 sc->hw.get_link_status = 1; 1140 em_check_for_link(&sc->hw); 1141 em_update_link_status(sc); 1142 callout_reset(&sc->timer, hz, em_local_timer, sc); 1143 } 1144 1145 if (reg_icr & E1000_ICR_RXO) 1146 sc->rx_overruns++; 1147 } 1148 1149 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1150 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1151 em_start_locked(ifp); 1152 1153 EM_UNLOCK(sc); 1154} 1155 1156#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1157 1158static void 1159em_handle_link(void *context, int pending) 1160{ 1161 struct em_softc *sc = context; 1162 struct ifnet *ifp; 1163 1164 ifp = sc->ifp; 1165 1166 EM_LOCK(sc); 1167 1168 callout_stop(&sc->timer); 1169 sc->hw.get_link_status = 1; 1170 em_check_for_link(&sc->hw); 1171 em_update_link_status(sc); 1172 callout_reset(&sc->timer, hz, em_local_timer, sc); 1173 EM_UNLOCK(sc); 1174} 1175 1176static void 1177em_handle_rxtx(void *context, int pending) 1178{ 1179 struct em_softc *sc = context; 1180 struct ifnet *ifp; 1181 1182 NET_LOCK_GIANT(); 1183 ifp = sc->ifp; 1184 1185 /* 1186 * TODO: 1187 * It should be possible to run the tx clean loop without the lock. 1188 */ 1189 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1190 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1191 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1192 EM_LOCK(sc); 1193 em_txeof(sc); 1194 1195 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1196 em_start_locked(ifp); 1197 EM_UNLOCK(sc); 1198 } 1199 1200 em_enable_intr(sc); 1201 NET_UNLOCK_GIANT(); 1202} 1203 1204/********************************************************************* 1205 * 1206 * Fast Interrupt Service routine 1207 * 1208 *********************************************************************/ 1209static void 1210em_intr_fast(void *arg) 1211{ 1212 struct em_softc *sc = arg; 1213 struct ifnet *ifp; 1214 uint32_t reg_icr; 1215 1216 ifp = sc->ifp; 1217 1218 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1219 1220 /* Hot eject? */ 1221 if (reg_icr == 0xffffffff) 1222 return; 1223 1224 /* Definitely not our interrupt. */ 1225 if (reg_icr == 0x0) 1226 return; 1227 1228 /* 1229 * Starting with the 82571 chip, bit 31 should be used to 1230 * determine whether the interrupt belongs to us. 1231 */ 1232 if (sc->hw.mac_type >= em_82571 && 1233 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1234 return; 1235 1236 /* 1237 * Mask interrupts until the taskqueue is finished running. This is 1238 * cheap, just assume that it is needed. This also works around the 1239 * MSI message reordering errata on certain systems. 1240 */ 1241 em_disable_intr(sc); 1242 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1243 1244 /* Link status change */ 1245 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1246 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1247 1248 if (reg_icr & E1000_ICR_RXO) 1249 sc->rx_overruns++; 1250} 1251#endif /* ! DEVICE_POLLING */ 1252 1253/********************************************************************* 1254 * 1255 * Media Ioctl callback 1256 * 1257 * This routine is called whenever the user queries the status of 1258 * the interface using ifconfig. 1259 * 1260 **********************************************************************/ 1261static void 1262em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1263{ 1264 struct em_softc *sc = ifp->if_softc; 1265 1266 INIT_DEBUGOUT("em_media_status: begin"); 1267 1268 em_check_for_link(&sc->hw); 1269 em_update_link_status(sc); 1270 1271 ifmr->ifm_status = IFM_AVALID; 1272 ifmr->ifm_active = IFM_ETHER; 1273 1274 if (!sc->link_active) 1275 return; 1276 1277 ifmr->ifm_status |= IFM_ACTIVE; 1278 1279 if (sc->hw.media_type == em_media_type_fiber) { 1280 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1281 } else { 1282 switch (sc->link_speed) { 1283 case 10: 1284 ifmr->ifm_active |= IFM_10_T; 1285 break; 1286 case 100: 1287 ifmr->ifm_active |= IFM_100_TX; 1288 break; 1289 case 1000: 1290 ifmr->ifm_active |= IFM_1000_T; 1291 break; 1292 } 1293 if (sc->link_duplex == FULL_DUPLEX) 1294 ifmr->ifm_active |= IFM_FDX; 1295 else 1296 ifmr->ifm_active |= IFM_HDX; 1297 } 1298} 1299 1300/********************************************************************* 1301 * 1302 * Media Ioctl callback 1303 * 1304 * This routine is called when the user changes speed/duplex using 1305 * media/mediopt option with ifconfig. 1306 * 1307 **********************************************************************/ 1308static int 1309em_media_change(struct ifnet *ifp) 1310{ 1311 struct em_softc *sc = ifp->if_softc; 1312 struct ifmedia *ifm = &sc->media; 1313 1314 INIT_DEBUGOUT("em_media_change: begin"); 1315 1316 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1317 return (EINVAL); 1318 1319 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1320 case IFM_AUTO: 1321 sc->hw.autoneg = DO_AUTO_NEG; 1322 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1323 break; 1324 case IFM_1000_SX: 1325 case IFM_1000_T: 1326 sc->hw.autoneg = DO_AUTO_NEG; 1327 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1328 break; 1329 case IFM_100_TX: 1330 sc->hw.autoneg = FALSE; 1331 sc->hw.autoneg_advertised = 0; 1332 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1333 sc->hw.forced_speed_duplex = em_100_full; 1334 else 1335 sc->hw.forced_speed_duplex = em_100_half; 1336 break; 1337 case IFM_10_T: 1338 sc->hw.autoneg = FALSE; 1339 sc->hw.autoneg_advertised = 0; 1340 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1341 sc->hw.forced_speed_duplex = em_10_full; 1342 else 1343 sc->hw.forced_speed_duplex = em_10_half; 1344 break; 1345 default: 1346 device_printf(sc->dev, "Unsupported media type\n"); 1347 } 1348 1349 /* As the speed/duplex settings my have changed we need to 1350 * reset the PHY. 1351 */ 1352 sc->hw.phy_reset_disable = FALSE; 1353 1354 em_init(sc); 1355 1356 return (0); 1357} 1358 1359/********************************************************************* 1360 * 1361 * This routine maps the mbufs to tx descriptors. 1362 * 1363 * return 0 on success, positive on failure 1364 **********************************************************************/ 1365static int 1366em_encap(struct em_softc *sc, struct mbuf **m_headp) 1367{ 1368 struct ifnet *ifp = sc->ifp; 1369 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1370 bus_dmamap_t map; 1371 struct em_buffer *tx_buffer; 1372 struct em_tx_desc *current_tx_desc; 1373 struct mbuf *m_head; 1374 struct m_tag *mtag; 1375 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1376 int nsegs, i, j; 1377 int error = 0; 1378 1379 m_head = *m_headp; 1380 current_tx_desc = NULL; 1381 txd_used = txd_saved = 0; 1382 1383 /* 1384 * Force a cleanup if number of TX descriptors 1385 * available hits the threshold. 1386 */ 1387 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1388 em_txeof(sc); 1389 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1390 sc->no_tx_desc_avail1++; 1391 return (ENOBUFS); 1392 } 1393 } 1394 1395 /* 1396 * Map the packet for DMA. 1397 */ 1398 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1399 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1400 segs, &nsegs, BUS_DMA_NOWAIT); 1401 map = tx_buffer->map; 1402 if (error != 0) { 1403 sc->no_tx_dma_setup++; 1404 return (error); 1405 } 1406 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1407 1408 if (nsegs > sc->num_tx_desc_avail) { 1409 sc->no_tx_desc_avail2++; 1410 error = ENOBUFS; 1411 goto encap_fail; 1412 } 1413 1414 if (ifp->if_hwassist > 0) 1415 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1416 else 1417 txd_upper = txd_lower = 0; 1418 1419 /* Find out if we are in vlan mode. */ 1420 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1421 1422 /* 1423 * When operating in promiscuous mode, hardware encapsulation for 1424 * packets is disabled. This means we have to add the vlan 1425 * encapsulation in the driver, since it will have come down from the 1426 * VLAN layer with a tag instead of a VLAN header. 1427 */ 1428 if (mtag != NULL && sc->em_insert_vlan_header) { 1429 struct ether_vlan_header *evl; 1430 struct ether_header eh; 1431 1432 m_head = m_pullup(m_head, sizeof(eh)); 1433 if (m_head == NULL) { 1434 *m_headp = NULL; 1435 error = ENOBUFS; 1436 goto encap_fail; 1437 } 1438 eh = *mtod(m_head, struct ether_header *); 1439 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1440 if (m_head == NULL) { 1441 *m_headp = NULL; 1442 error = ENOBUFS; 1443 goto encap_fail; 1444 } 1445 m_head = m_pullup(m_head, sizeof(*evl)); 1446 if (m_head == NULL) { 1447 *m_headp = NULL; 1448 error = ENOBUFS; 1449 goto encap_fail; 1450 } 1451 evl = mtod(m_head, struct ether_vlan_header *); 1452 bcopy(&eh, evl, sizeof(*evl)); 1453 evl->evl_proto = evl->evl_encap_proto; 1454 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1455 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1456 m_tag_delete(m_head, mtag); 1457 mtag = NULL; 1458 *m_headp = m_head; 1459 } 1460 1461 i = sc->next_avail_tx_desc; 1462 if (sc->pcix_82544) { 1463 txd_saved = i; 1464 txd_used = 0; 1465 } 1466 for (j = 0; j < nsegs; j++) { 1467 /* If adapter is 82544 and on PCIX bus. */ 1468 if(sc->pcix_82544) { 1469 DESC_ARRAY desc_array; 1470 uint32_t array_elements, counter; 1471 1472 /* 1473 * Check the Address and Length combination and 1474 * split the data accordingly 1475 */ 1476 array_elements = em_fill_descriptors(segs[j].ds_addr, 1477 segs[j].ds_len, &desc_array); 1478 for (counter = 0; counter < array_elements; counter++) { 1479 if (txd_used == sc->num_tx_desc_avail) { 1480 sc->next_avail_tx_desc = txd_saved; 1481 sc->no_tx_desc_avail2++; 1482 error = ENOBUFS; 1483 goto encap_fail; 1484 } 1485 tx_buffer = &sc->tx_buffer_area[i]; 1486 current_tx_desc = &sc->tx_desc_base[i]; 1487 current_tx_desc->buffer_addr = htole64( 1488 desc_array.descriptor[counter].address); 1489 current_tx_desc->lower.data = htole32( 1490 (sc->txd_cmd | txd_lower | 1491 (uint16_t)desc_array.descriptor[counter].length)); 1492 current_tx_desc->upper.data = htole32((txd_upper)); 1493 if (++i == sc->num_tx_desc) 1494 i = 0; 1495 1496 tx_buffer->m_head = NULL; 1497 txd_used++; 1498 } 1499 } else { 1500 tx_buffer = &sc->tx_buffer_area[i]; 1501 current_tx_desc = &sc->tx_desc_base[i]; 1502 1503 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1504 current_tx_desc->lower.data = htole32( 1505 sc->txd_cmd | txd_lower | segs[j].ds_len); 1506 current_tx_desc->upper.data = htole32(txd_upper); 1507 1508 if (++i == sc->num_tx_desc) 1509 i = 0; 1510 1511 tx_buffer->m_head = NULL; 1512 } 1513 } 1514 1515 sc->next_avail_tx_desc = i; 1516 if (sc->pcix_82544) 1517 sc->num_tx_desc_avail -= txd_used; 1518 else 1519 sc->num_tx_desc_avail -= nsegs; 1520 1521 if (mtag != NULL) { 1522 /* Set the vlan id. */ 1523 current_tx_desc->upper.fields.special = 1524 htole16(VLAN_TAG_VALUE(mtag)); 1525 1526 /* Tell hardware to add tag. */ 1527 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1528 } 1529 1530 tx_buffer->m_head = m_head; 1531 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1532 1533 /* 1534 * Last Descriptor of Packet needs End Of Packet (EOP). 1535 */ 1536 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1537 1538 /* 1539 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1540 * that this frame is available to transmit. 1541 */ 1542 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1544 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1545 em_82547_move_tail_locked(sc); 1546 else { 1547 E1000_WRITE_REG(&sc->hw, TDT, i); 1548 if (sc->hw.mac_type == em_82547) 1549 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1550 } 1551 1552 return (0); 1553 1554encap_fail: 1555 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1556 return (error); 1557} 1558 1559/********************************************************************* 1560 * 1561 * 82547 workaround to avoid controller hang in half-duplex environment. 1562 * The workaround is to avoid queuing a large packet that would span 1563 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1564 * in this case. We do that only when FIFO is quiescent. 1565 * 1566 **********************************************************************/ 1567static void 1568em_82547_move_tail_locked(struct em_softc *sc) 1569{ 1570 uint16_t hw_tdt; 1571 uint16_t sw_tdt; 1572 struct em_tx_desc *tx_desc; 1573 uint16_t length = 0; 1574 boolean_t eop = 0; 1575 1576 EM_LOCK_ASSERT(sc); 1577 1578 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1579 sw_tdt = sc->next_avail_tx_desc; 1580 1581 while (hw_tdt != sw_tdt) { 1582 tx_desc = &sc->tx_desc_base[hw_tdt]; 1583 length += tx_desc->lower.flags.length; 1584 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1585 if(++hw_tdt == sc->num_tx_desc) 1586 hw_tdt = 0; 1587 1588 if (eop) { 1589 if (em_82547_fifo_workaround(sc, length)) { 1590 sc->tx_fifo_wrk_cnt++; 1591 callout_reset(&sc->tx_fifo_timer, 1, 1592 em_82547_move_tail, sc); 1593 break; 1594 } 1595 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1596 em_82547_update_fifo_head(sc, length); 1597 length = 0; 1598 } 1599 } 1600} 1601 1602static void 1603em_82547_move_tail(void *arg) 1604{ 1605 struct em_softc *sc = arg; 1606 1607 EM_LOCK(sc); 1608 em_82547_move_tail_locked(sc); 1609 EM_UNLOCK(sc); 1610} 1611 1612static int 1613em_82547_fifo_workaround(struct em_softc *sc, int len) 1614{ 1615 int fifo_space, fifo_pkt_len; 1616 1617 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1618 1619 if (sc->link_duplex == HALF_DUPLEX) { 1620 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1621 1622 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1623 if (em_82547_tx_fifo_reset(sc)) 1624 return (0); 1625 else 1626 return (1); 1627 } 1628 } 1629 1630 return (0); 1631} 1632 1633static void 1634em_82547_update_fifo_head(struct em_softc *sc, int len) 1635{ 1636 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1637 1638 /* tx_fifo_head is always 16 byte aligned */ 1639 sc->tx_fifo_head += fifo_pkt_len; 1640 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1641 sc->tx_fifo_head -= sc->tx_fifo_size; 1642 } 1643} 1644 1645 1646static int 1647em_82547_tx_fifo_reset(struct em_softc *sc) 1648{ 1649 uint32_t tctl; 1650 1651 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1652 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1653 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1654 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1655 1656 /* Disable TX unit */ 1657 tctl = E1000_READ_REG(&sc->hw, TCTL); 1658 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1659 1660 /* Reset FIFO pointers */ 1661 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1662 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1663 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1664 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1665 1666 /* Re-enable TX unit */ 1667 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1668 E1000_WRITE_FLUSH(&sc->hw); 1669 1670 sc->tx_fifo_head = 0; 1671 sc->tx_fifo_reset_cnt++; 1672 1673 return (TRUE); 1674 } 1675 else { 1676 return (FALSE); 1677 } 1678} 1679 1680static void 1681em_set_promisc(struct em_softc *sc) 1682{ 1683 struct ifnet *ifp = sc->ifp; 1684 uint32_t reg_rctl; 1685 1686 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1687 1688 if (ifp->if_flags & IFF_PROMISC) { 1689 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1690 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1691 /* Disable VLAN stripping in promiscous mode 1692 * This enables bridging of vlan tagged frames to occur 1693 * and also allows vlan tags to be seen in tcpdump 1694 */ 1695 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1696 em_disable_vlans(sc); 1697 sc->em_insert_vlan_header = 1; 1698 } else if (ifp->if_flags & IFF_ALLMULTI) { 1699 reg_rctl |= E1000_RCTL_MPE; 1700 reg_rctl &= ~E1000_RCTL_UPE; 1701 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1702 sc->em_insert_vlan_header = 0; 1703 } else 1704 sc->em_insert_vlan_header = 0; 1705} 1706 1707static void 1708em_disable_promisc(struct em_softc *sc) 1709{ 1710 struct ifnet *ifp = sc->ifp; 1711 uint32_t reg_rctl; 1712 1713 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1714 1715 reg_rctl &= (~E1000_RCTL_UPE); 1716 reg_rctl &= (~E1000_RCTL_MPE); 1717 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1718 1719 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1720 em_enable_vlans(sc); 1721 sc->em_insert_vlan_header = 0; 1722} 1723 1724 1725/********************************************************************* 1726 * Multicast Update 1727 * 1728 * This routine is called whenever multicast address list is updated. 1729 * 1730 **********************************************************************/ 1731 1732static void 1733em_set_multi(struct em_softc *sc) 1734{ 1735 struct ifnet *ifp = sc->ifp; 1736 struct ifmultiaddr *ifma; 1737 uint32_t reg_rctl = 0; 1738 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1739 int mcnt = 0; 1740 1741 IOCTL_DEBUGOUT("em_set_multi: begin"); 1742 1743 if (sc->hw.mac_type == em_82542_rev2_0) { 1744 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1745 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1746 em_pci_clear_mwi(&sc->hw); 1747 reg_rctl |= E1000_RCTL_RST; 1748 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1749 msec_delay(5); 1750 } 1751 1752 IF_ADDR_LOCK(ifp); 1753 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1754 if (ifma->ifma_addr->sa_family != AF_LINK) 1755 continue; 1756 1757 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1758 break; 1759 1760 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1761 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1762 mcnt++; 1763 } 1764 IF_ADDR_UNLOCK(ifp); 1765 1766 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1767 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1768 reg_rctl |= E1000_RCTL_MPE; 1769 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1770 } else 1771 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1772 1773 if (sc->hw.mac_type == em_82542_rev2_0) { 1774 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1775 reg_rctl &= ~E1000_RCTL_RST; 1776 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1777 msec_delay(5); 1778 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1779 em_pci_set_mwi(&sc->hw); 1780 } 1781} 1782 1783 1784/********************************************************************* 1785 * Timer routine 1786 * 1787 * This routine checks for link status and updates statistics. 1788 * 1789 **********************************************************************/ 1790 1791static void 1792em_local_timer(void *arg) 1793{ 1794 struct em_softc *sc = arg; 1795 struct ifnet *ifp = sc->ifp; 1796 1797 EM_LOCK(sc); 1798 1799 em_check_for_link(&sc->hw); 1800 em_update_link_status(sc); 1801 em_update_stats_counters(sc); 1802 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1803 em_print_hw_stats(sc); 1804 em_smartspeed(sc); 1805 1806 callout_reset(&sc->timer, hz, em_local_timer, sc); 1807 1808 EM_UNLOCK(sc); 1809} 1810 1811static void 1812em_update_link_status(struct em_softc *sc) 1813{ 1814 struct ifnet *ifp = sc->ifp; 1815 device_t dev = sc->dev; 1816 1817 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1818 if (sc->link_active == 0) { 1819 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1820 &sc->link_duplex); 1821 if (bootverbose) 1822 device_printf(dev, "Link is up %d Mbps %s\n", 1823 sc->link_speed, 1824 ((sc->link_duplex == FULL_DUPLEX) ? 1825 "Full Duplex" : "Half Duplex")); 1826 sc->link_active = 1; 1827 sc->smartspeed = 0; 1828 ifp->if_baudrate = sc->link_speed * 1000000; 1829 if_link_state_change(ifp, LINK_STATE_UP); 1830 } 1831 } else { 1832 if (sc->link_active == 1) { 1833 ifp->if_baudrate = sc->link_speed = 0; 1834 sc->link_duplex = 0; 1835 if (bootverbose) 1836 device_printf(dev, "Link is Down\n"); 1837 sc->link_active = 0; 1838 if_link_state_change(ifp, LINK_STATE_DOWN); 1839 } 1840 } 1841} 1842 1843/********************************************************************* 1844 * 1845 * This routine disables all traffic on the adapter by issuing a 1846 * global reset on the MAC and deallocates TX/RX buffers. 1847 * 1848 **********************************************************************/ 1849 1850static void 1851em_stop(void *arg) 1852{ 1853 struct em_softc *sc = arg; 1854 struct ifnet *ifp = sc->ifp; 1855 1856 EM_LOCK_ASSERT(sc); 1857 1858 INIT_DEBUGOUT("em_stop: begin"); 1859 1860 em_disable_intr(sc); 1861 em_reset_hw(&sc->hw); 1862 callout_stop(&sc->timer); 1863 callout_stop(&sc->tx_fifo_timer); 1864 em_free_transmit_structures(sc); 1865 em_free_receive_structures(sc); 1866 1867 /* Tell the stack that the interface is no longer active */ 1868 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1869} 1870 1871 1872/********************************************************************* 1873 * 1874 * Determine hardware revision. 1875 * 1876 **********************************************************************/ 1877static void 1878em_identify_hardware(struct em_softc *sc) 1879{ 1880 device_t dev = sc->dev; 1881 1882 /* Make sure our PCI config space has the necessary stuff set */ 1883 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1884 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1885 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1886 device_printf(dev, "Memory Access and/or Bus Master bits " 1887 "were not set!\n"); 1888 sc->hw.pci_cmd_word |= 1889 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1890 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1891 } 1892 1893 /* Save off the information about this board */ 1894 sc->hw.vendor_id = pci_get_vendor(dev); 1895 sc->hw.device_id = pci_get_device(dev); 1896 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1897 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1898 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1899 1900 /* Identify the MAC */ 1901 if (em_set_mac_type(&sc->hw)) 1902 device_printf(dev, "Unknown MAC Type\n"); 1903 1904 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1905 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1906 sc->hw.phy_init_script = TRUE; 1907} 1908 1909static int 1910em_allocate_pci_resources(struct em_softc *sc) 1911{ 1912 device_t dev = sc->dev; 1913 int val, rid; 1914 1915 rid = PCIR_BAR(0); 1916 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1917 &rid, RF_ACTIVE); 1918 if (sc->res_memory == NULL) { 1919 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1920 return (ENXIO); 1921 } 1922 sc->osdep.mem_bus_space_tag = 1923 rman_get_bustag(sc->res_memory); 1924 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1925 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1926 1927 if (sc->hw.mac_type > em_82543) { 1928 /* Figure our where our IO BAR is ? */ 1929 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1930 val = pci_read_config(dev, rid, 4); 1931 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1932 sc->io_rid = rid; 1933 break; 1934 } 1935 rid += 4; 1936 /* check for 64bit BAR */ 1937 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1938 rid += 4; 1939 } 1940 if (rid >= PCIR_CIS) { 1941 device_printf(dev, "Unable to locate IO BAR\n"); 1942 return (ENXIO); 1943 } 1944 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1945 &sc->io_rid, RF_ACTIVE); 1946 if (sc->res_ioport == NULL) { 1947 device_printf(dev, "Unable to allocate bus resource: " 1948 "ioport\n"); 1949 return (ENXIO); 1950 } 1951 sc->hw.io_base = 0; 1952 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1953 sc->osdep.io_bus_space_handle = 1954 rman_get_bushandle(sc->res_ioport); 1955 } 1956 1957 rid = 0x0; 1958 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1959 RF_SHAREABLE | RF_ACTIVE); 1960 if (sc->res_interrupt == NULL) { 1961 device_printf(dev, "Unable to allocate bus resource: " 1962 "interrupt\n"); 1963 return (ENXIO); 1964 } 1965 1966 sc->hw.back = &sc->osdep; 1967 1968 return (0); 1969} 1970 1971int 1972em_allocate_intr(struct em_softc *sc) 1973{ 1974 device_t dev = sc->dev; 1975 int error; 1976 1977 /* Manually turn off all interrupts */ 1978 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1979 1980#ifdef DEVICE_POLLING 1981 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 1982 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 1983 &sc->int_handler_tag)) != 0) { 1984 device_printf(dev, "Failed to register interrupt handler"); 1985 return (error); 1986 } 1987#else 1988 /* 1989 * Try allocating a fast interrupt and the associated deferred 1990 * processing contexts. 1991 */ 1992 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1993 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1994 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1995 taskqueue_thread_enqueue, &sc->tq); 1996 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1997 device_get_nameunit(sc->dev)); 1998 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1999 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 2000 &sc->int_handler_tag)) != 0) { 2001 device_printf(dev, "Failed to register fast interrupt " 2002 "handler: %d\n", error); 2003 taskqueue_free(sc->tq); 2004 sc->tq = NULL; 2005 return (error); 2006 } 2007#endif 2008 2009 em_enable_intr(sc); 2010 return (0); 2011} 2012 2013static void 2014em_free_intr(struct em_softc *sc) 2015{ 2016 device_t dev = sc->dev; 2017 2018 if (sc->res_interrupt != NULL) { 2019 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2020 sc->int_handler_tag = NULL; 2021 } 2022 if (sc->tq != NULL) { 2023 taskqueue_drain(sc->tq, &sc->rxtx_task); 2024 taskqueue_drain(taskqueue_fast, &sc->link_task); 2025 taskqueue_free(sc->tq); 2026 sc->tq = NULL; 2027 } 2028} 2029 2030static void 2031em_free_pci_resources(struct em_softc *sc) 2032{ 2033 device_t dev = sc->dev; 2034 2035 if (sc->res_interrupt != NULL) 2036 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2037 2038 if (sc->res_memory != NULL) 2039 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2040 sc->res_memory); 2041 2042 if (sc->res_ioport != NULL) 2043 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2044 sc->res_ioport); 2045} 2046 2047/********************************************************************* 2048 * 2049 * Initialize the hardware to a configuration as specified by the 2050 * adapter structure. The controller is reset, the EEPROM is 2051 * verified, the MAC address is set, then the shared initialization 2052 * routines are called. 2053 * 2054 **********************************************************************/ 2055static int 2056em_hardware_init(struct em_softc *sc) 2057{ 2058 device_t dev = sc->dev; 2059 uint16_t rx_buffer_size; 2060 2061 INIT_DEBUGOUT("em_hardware_init: begin"); 2062 /* Issue a global reset */ 2063 em_reset_hw(&sc->hw); 2064 2065 /* When hardware is reset, fifo_head is also reset */ 2066 sc->tx_fifo_head = 0; 2067 2068 /* Make sure we have a good EEPROM before we read from it */ 2069 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2070 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2071 return (EIO); 2072 } 2073 2074 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2075 device_printf(dev, "EEPROM read error while reading part " 2076 "number\n"); 2077 return (EIO); 2078 } 2079 2080 /* 2081 * These parameters control the automatic generation (Tx) and 2082 * response (Rx) to Ethernet PAUSE frames. 2083 * - High water mark should allow for at least two frames to be 2084 * received after sending an XOFF. 2085 * - Low water mark works best when it is very near the high water mark. 2086 * This allows the receiver to restart by sending XON when it has 2087 * drained a bit. Here we use an arbitary value of 1500 which will 2088 * restart after one full frame is pulled from the buffer. There 2089 * could be several smaller frames in the buffer and if so they will 2090 * not trigger the XON until their total number reduces the buffer 2091 * by 1500. 2092 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2093 */ 2094 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2095 2096 sc->hw.fc_high_water = rx_buffer_size - 2097 roundup2(sc->hw.max_frame_size, 1024); 2098 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2099 if (sc->hw.mac_type == em_80003es2lan) 2100 sc->hw.fc_pause_time = 0xFFFF; 2101 else 2102 sc->hw.fc_pause_time = 0x1000; 2103 sc->hw.fc_send_xon = TRUE; 2104 sc->hw.fc = em_fc_full; 2105 2106 if (em_init_hw(&sc->hw) < 0) { 2107 device_printf(dev, "Hardware Initialization Failed"); 2108 return (EIO); 2109 } 2110 2111 em_check_for_link(&sc->hw); 2112 2113 return (0); 2114} 2115 2116/********************************************************************* 2117 * 2118 * Setup networking device structure and register an interface. 2119 * 2120 **********************************************************************/ 2121static void 2122em_setup_interface(device_t dev, struct em_softc *sc) 2123{ 2124 struct ifnet *ifp; 2125 INIT_DEBUGOUT("em_setup_interface: begin"); 2126 2127 ifp = sc->ifp = if_alloc(IFT_ETHER); 2128 if (ifp == NULL) 2129 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2130 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2131 ifp->if_mtu = ETHERMTU; 2132 ifp->if_init = em_init; 2133 ifp->if_softc = sc; 2134 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2135 ifp->if_ioctl = em_ioctl; 2136 ifp->if_start = em_start; 2137 ifp->if_watchdog = em_watchdog; 2138 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2139 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2140 IFQ_SET_READY(&ifp->if_snd); 2141 2142 ether_ifattach(ifp, sc->hw.mac_addr); 2143 2144 ifp->if_capabilities = ifp->if_capenable = 0; 2145 2146 if (sc->hw.mac_type >= em_82543) { 2147 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2148 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2149 } 2150 2151 /* 2152 * Tell the upper layer(s) we support long frames. 2153 */ 2154 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2155 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2156 ifp->if_capenable |= IFCAP_VLAN_MTU; 2157 2158#ifdef DEVICE_POLLING 2159 ifp->if_capabilities |= IFCAP_POLLING; 2160#endif 2161 2162 /* 2163 * Specify the media types supported by this adapter and register 2164 * callbacks to update media and link information 2165 */ 2166 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2167 if (sc->hw.media_type == em_media_type_fiber) { 2168 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2169 0, NULL); 2170 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2171 0, NULL); 2172 } else { 2173 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2174 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2175 0, NULL); 2176 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2177 0, NULL); 2178 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2179 0, NULL); 2180 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2181 0, NULL); 2182 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2183 } 2184 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2185 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2186} 2187 2188 2189/********************************************************************* 2190 * 2191 * Workaround for SmartSpeed on 82541 and 82547 controllers 2192 * 2193 **********************************************************************/ 2194static void 2195em_smartspeed(struct em_softc *sc) 2196{ 2197 uint16_t phy_tmp; 2198 2199 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2200 sc->hw.autoneg == 0 || 2201 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2202 return; 2203 2204 if (sc->smartspeed == 0) { 2205 /* If Master/Slave config fault is asserted twice, 2206 * we assume back-to-back */ 2207 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2208 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2209 return; 2210 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2211 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2212 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2213 if(phy_tmp & CR_1000T_MS_ENABLE) { 2214 phy_tmp &= ~CR_1000T_MS_ENABLE; 2215 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2216 phy_tmp); 2217 sc->smartspeed++; 2218 if(sc->hw.autoneg && 2219 !em_phy_setup_autoneg(&sc->hw) && 2220 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2221 &phy_tmp)) { 2222 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2223 MII_CR_RESTART_AUTO_NEG); 2224 em_write_phy_reg(&sc->hw, PHY_CTRL, 2225 phy_tmp); 2226 } 2227 } 2228 } 2229 return; 2230 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2231 /* If still no link, perhaps using 2/3 pair cable */ 2232 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2233 phy_tmp |= CR_1000T_MS_ENABLE; 2234 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2235 if(sc->hw.autoneg && 2236 !em_phy_setup_autoneg(&sc->hw) && 2237 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2238 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2239 MII_CR_RESTART_AUTO_NEG); 2240 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2241 } 2242 } 2243 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2244 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2245 sc->smartspeed = 0; 2246} 2247 2248 2249/* 2250 * Manage DMA'able memory. 2251 */ 2252static void 2253em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2254{ 2255 if (error) 2256 return; 2257 *(bus_addr_t *) arg = segs[0].ds_addr; 2258} 2259 2260static int 2261em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2262 int mapflags) 2263{ 2264 int error; 2265 2266 error = bus_dma_tag_create(NULL, /* parent */ 2267 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2268 BUS_SPACE_MAXADDR, /* lowaddr */ 2269 BUS_SPACE_MAXADDR, /* highaddr */ 2270 NULL, NULL, /* filter, filterarg */ 2271 size, /* maxsize */ 2272 1, /* nsegments */ 2273 size, /* maxsegsize */ 2274 0, /* flags */ 2275 NULL, /* lockfunc */ 2276 NULL, /* lockarg */ 2277 &dma->dma_tag); 2278 if (error) { 2279 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2280 __func__, error); 2281 goto fail_0; 2282 } 2283 2284 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2285 BUS_DMA_NOWAIT, &dma->dma_map); 2286 if (error) { 2287 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2288 __func__, (uintmax_t)size, error); 2289 goto fail_2; 2290 } 2291 2292 dma->dma_paddr = 0; 2293 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2294 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2295 if (error || dma->dma_paddr == 0) { 2296 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2297 __func__, error); 2298 goto fail_3; 2299 } 2300 2301 return (0); 2302 2303fail_3: 2304 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2305fail_2: 2306 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2307 bus_dma_tag_destroy(dma->dma_tag); 2308fail_0: 2309 dma->dma_map = NULL; 2310 dma->dma_tag = NULL; 2311 2312 return (error); 2313} 2314 2315static void 2316em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2317{ 2318 if (dma->dma_tag == NULL) 2319 return; 2320 if (dma->dma_map != NULL) { 2321 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2323 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2324 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2325 dma->dma_map = NULL; 2326 } 2327 bus_dma_tag_destroy(dma->dma_tag); 2328 dma->dma_tag = NULL; 2329} 2330 2331 2332/********************************************************************* 2333 * 2334 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2335 * the information needed to transmit a packet on the wire. 2336 * 2337 **********************************************************************/ 2338static int 2339em_allocate_transmit_structures(struct em_softc *sc) 2340{ 2341 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2342 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2343 if (sc->tx_buffer_area == NULL) { 2344 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2345 return (ENOMEM); 2346 } 2347 2348 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2349 2350 return (0); 2351} 2352 2353/********************************************************************* 2354 * 2355 * Allocate and initialize transmit structures. 2356 * 2357 **********************************************************************/ 2358static int 2359em_setup_transmit_structures(struct em_softc *sc) 2360{ 2361 device_t dev = sc->dev; 2362 struct em_buffer *tx_buffer; 2363 bus_size_t size; 2364 int error, i; 2365 2366 /* 2367 * Setup DMA descriptor areas. 2368 */ 2369 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2370 if ((error = bus_dma_tag_create(NULL, /* parent */ 2371 1, 0, /* alignment, bounds */ 2372 BUS_SPACE_MAXADDR, /* lowaddr */ 2373 BUS_SPACE_MAXADDR, /* highaddr */ 2374 NULL, NULL, /* filter, filterarg */ 2375 size, /* maxsize */ 2376 EM_MAX_SCATTER, /* nsegments */ 2377 size, /* maxsegsize */ 2378 0, /* flags */ 2379 NULL, /* lockfunc */ 2380 NULL, /* lockarg */ 2381 &sc->txtag)) != 0) { 2382 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2383 goto fail; 2384 } 2385 2386 if ((error = em_allocate_transmit_structures(sc)) != 0) 2387 goto fail; 2388 2389 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2390 tx_buffer = sc->tx_buffer_area; 2391 for (i = 0; i < sc->num_tx_desc; i++) { 2392 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2393 if (error != 0) { 2394 device_printf(dev, "Unable to create TX DMA map\n"); 2395 goto fail; 2396 } 2397 tx_buffer++; 2398 } 2399 2400 sc->next_avail_tx_desc = 0; 2401 sc->oldest_used_tx_desc = 0; 2402 2403 /* Set number of descriptors available */ 2404 sc->num_tx_desc_avail = sc->num_tx_desc; 2405 2406 /* Set checksum context */ 2407 sc->active_checksum_context = OFFLOAD_NONE; 2408 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2410 2411 return (0); 2412 2413fail: 2414 em_free_transmit_structures(sc); 2415 return (error); 2416} 2417 2418/********************************************************************* 2419 * 2420 * Enable transmit unit. 2421 * 2422 **********************************************************************/ 2423static void 2424em_initialize_transmit_unit(struct em_softc *sc) 2425{ 2426 uint32_t reg_tctl, tarc; 2427 uint32_t reg_tipg = 0; 2428 uint64_t bus_addr; 2429 2430 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2431 /* Setup the Base and Length of the Tx Descriptor Ring */ 2432 bus_addr = sc->txdma.dma_paddr; 2433 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2434 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2435 E1000_WRITE_REG(&sc->hw, TDLEN, 2436 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2437 2438 /* Setup the HW Tx Head and Tail descriptor pointers */ 2439 E1000_WRITE_REG(&sc->hw, TDH, 0); 2440 E1000_WRITE_REG(&sc->hw, TDT, 0); 2441 2442 2443 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2444 E1000_READ_REG(&sc->hw, TDLEN)); 2445 2446 /* Set the default values for the Tx Inter Packet Gap timer */ 2447 switch (sc->hw.mac_type) { 2448 case em_82542_rev2_0: 2449 case em_82542_rev2_1: 2450 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2451 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2452 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2453 break; 2454 case em_80003es2lan: 2455 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2456 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2457 E1000_TIPG_IPGR2_SHIFT; 2458 break; 2459 default: 2460 if (sc->hw.media_type == em_media_type_fiber) 2461 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2462 else 2463 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2464 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2465 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2466 } 2467 2468 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2469 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2470 if(sc->hw.mac_type >= em_82540) 2471 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2472 2473 /* Program the Transmit Control Register */ 2474 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2475 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2476 if (sc->hw.mac_type >= em_82571) 2477 reg_tctl |= E1000_TCTL_MULR; 2478 if (sc->link_duplex == 1) { 2479 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2480 } else { 2481 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2482 } 2483 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2484 2485 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) { 2486 tarc = E1000_READ_REG(&sc->hw, TARC0); 2487 tarc |= ((1 << 25) | (1 << 21)); 2488 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2489 tarc = E1000_READ_REG(&sc->hw, TARC1); 2490 tarc |= (1 << 25); 2491 if (reg_tctl & E1000_TCTL_MULR) 2492 tarc &= ~(1 << 28); 2493 else 2494 tarc |= (1 << 28); 2495 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2496 } else if (sc->hw.mac_type == em_80003es2lan) { 2497 tarc = E1000_READ_REG(&sc->hw, TARC0); 2498 tarc |= 1; 2499 if (sc->hw.media_type == em_media_type_internal_serdes) 2500 tarc |= (1 << 20); 2501 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2502 tarc = E1000_READ_REG(&sc->hw, TARC1); 2503 tarc |= 1; 2504 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2505 } 2506 2507 /* Setup Transmit Descriptor Settings for this adapter */ 2508 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2509 2510 if (sc->tx_int_delay.value > 0) 2511 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2512} 2513 2514/********************************************************************* 2515 * 2516 * Free all transmit related data structures. 2517 * 2518 **********************************************************************/ 2519static void 2520em_free_transmit_structures(struct em_softc *sc) 2521{ 2522 struct em_buffer *tx_buffer; 2523 int i; 2524 2525 INIT_DEBUGOUT("free_transmit_structures: begin"); 2526 2527 if (sc->tx_buffer_area != NULL) { 2528 tx_buffer = sc->tx_buffer_area; 2529 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2530 if (tx_buffer->m_head != NULL) { 2531 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2532 BUS_DMASYNC_POSTWRITE); 2533 bus_dmamap_unload(sc->txtag, 2534 tx_buffer->map); 2535 m_freem(tx_buffer->m_head); 2536 tx_buffer->m_head = NULL; 2537 } else if (tx_buffer->map != NULL) 2538 bus_dmamap_unload(sc->txtag, 2539 tx_buffer->map); 2540 if (tx_buffer->map != NULL) { 2541 bus_dmamap_destroy(sc->txtag, 2542 tx_buffer->map); 2543 tx_buffer->map = NULL; 2544 } 2545 } 2546 } 2547 if (sc->tx_buffer_area != NULL) { 2548 free(sc->tx_buffer_area, M_DEVBUF); 2549 sc->tx_buffer_area = NULL; 2550 } 2551 if (sc->txtag != NULL) { 2552 bus_dma_tag_destroy(sc->txtag); 2553 sc->txtag = NULL; 2554 } 2555} 2556 2557/********************************************************************* 2558 * 2559 * The offload context needs to be set when we transfer the first 2560 * packet of a particular protocol (TCP/UDP). We change the 2561 * context only if the protocol type changes. 2562 * 2563 **********************************************************************/ 2564static void 2565em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2566 uint32_t *txd_upper, uint32_t *txd_lower) 2567{ 2568 struct em_context_desc *TXD; 2569 struct em_buffer *tx_buffer; 2570 int curr_txd; 2571 2572 if (mp->m_pkthdr.csum_flags) { 2573 2574 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2575 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2576 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2577 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2578 return; 2579 else 2580 sc->active_checksum_context = OFFLOAD_TCP_IP; 2581 2582 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2583 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2584 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2585 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2586 return; 2587 else 2588 sc->active_checksum_context = OFFLOAD_UDP_IP; 2589 } else { 2590 *txd_upper = 0; 2591 *txd_lower = 0; 2592 return; 2593 } 2594 } else { 2595 *txd_upper = 0; 2596 *txd_lower = 0; 2597 return; 2598 } 2599 2600 /* If we reach this point, the checksum offload context 2601 * needs to be reset. 2602 */ 2603 curr_txd = sc->next_avail_tx_desc; 2604 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2605 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2606 2607 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2608 TXD->lower_setup.ip_fields.ipcso = 2609 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2610 TXD->lower_setup.ip_fields.ipcse = 2611 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2612 2613 TXD->upper_setup.tcp_fields.tucss = 2614 ETHER_HDR_LEN + sizeof(struct ip); 2615 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2616 2617 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2618 TXD->upper_setup.tcp_fields.tucso = 2619 ETHER_HDR_LEN + sizeof(struct ip) + 2620 offsetof(struct tcphdr, th_sum); 2621 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2622 TXD->upper_setup.tcp_fields.tucso = 2623 ETHER_HDR_LEN + sizeof(struct ip) + 2624 offsetof(struct udphdr, uh_sum); 2625 } 2626 2627 TXD->tcp_seg_setup.data = htole32(0); 2628 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2629 2630 tx_buffer->m_head = NULL; 2631 2632 if (++curr_txd == sc->num_tx_desc) 2633 curr_txd = 0; 2634 2635 sc->num_tx_desc_avail--; 2636 sc->next_avail_tx_desc = curr_txd; 2637} 2638 2639/********************************************************************** 2640 * 2641 * Examine each tx_buffer in the used queue. If the hardware is done 2642 * processing the packet then free associated resources. The 2643 * tx_buffer is put back on the free queue. 2644 * 2645 **********************************************************************/ 2646static void 2647em_txeof(struct em_softc *sc) 2648{ 2649 int i, num_avail; 2650 struct em_buffer *tx_buffer; 2651 struct em_tx_desc *tx_desc; 2652 struct ifnet *ifp = sc->ifp; 2653 2654 EM_LOCK_ASSERT(sc); 2655 2656 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2657 return; 2658 2659 num_avail = sc->num_tx_desc_avail; 2660 i = sc->oldest_used_tx_desc; 2661 2662 tx_buffer = &sc->tx_buffer_area[i]; 2663 tx_desc = &sc->tx_desc_base[i]; 2664 2665 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2666 BUS_DMASYNC_POSTREAD); 2667 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2668 2669 tx_desc->upper.data = 0; 2670 num_avail++; 2671 2672 if (tx_buffer->m_head) { 2673 ifp->if_opackets++; 2674 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2675 BUS_DMASYNC_POSTWRITE); 2676 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2677 2678 m_freem(tx_buffer->m_head); 2679 tx_buffer->m_head = NULL; 2680 } 2681 2682 if (++i == sc->num_tx_desc) 2683 i = 0; 2684 2685 tx_buffer = &sc->tx_buffer_area[i]; 2686 tx_desc = &sc->tx_desc_base[i]; 2687 } 2688 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2689 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2690 2691 sc->oldest_used_tx_desc = i; 2692 2693 /* 2694 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2695 * that it is OK to send packets. 2696 * If there are no pending descriptors, clear the timeout. Otherwise, 2697 * if some descriptors have been freed, restart the timeout. 2698 */ 2699 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2700 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2701 if (num_avail == sc->num_tx_desc) 2702 ifp->if_timer = 0; 2703 else if (num_avail != sc->num_tx_desc_avail) 2704 ifp->if_timer = EM_TX_TIMEOUT; 2705 } 2706 sc->num_tx_desc_avail = num_avail; 2707} 2708 2709/********************************************************************* 2710 * 2711 * Get a buffer from system mbuf buffer pool. 2712 * 2713 **********************************************************************/ 2714static int 2715em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2716{ 2717 struct ifnet *ifp = sc->ifp; 2718 bus_dma_segment_t segs[1]; 2719 struct em_buffer *rx_buffer; 2720 int error, nsegs; 2721 2722 if (mp == NULL) { 2723 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2724 if (mp == NULL) { 2725 sc->mbuf_cluster_failed++; 2726 return (ENOBUFS); 2727 } 2728 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2729 } else { 2730 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2731 mp->m_data = mp->m_ext.ext_buf; 2732 mp->m_next = NULL; 2733 } 2734 2735 if (ifp->if_mtu <= ETHERMTU) 2736 m_adj(mp, ETHER_ALIGN); 2737 2738 rx_buffer = &sc->rx_buffer_area[i]; 2739 2740 /* 2741 * Using memory from the mbuf cluster pool, invoke the 2742 * bus_dma machinery to arrange the memory mapping. 2743 */ 2744 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2745 mp, segs, &nsegs, 0); 2746 if (error != 0) { 2747 m_free(mp); 2748 return (error); 2749 } 2750 /* If nsegs is wrong then the stack is corrupt. */ 2751 KASSERT(nsegs == 1, ("Too many segments returned!")); 2752 rx_buffer->m_head = mp; 2753 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2754 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2755 2756 return (0); 2757} 2758 2759/********************************************************************* 2760 * 2761 * Allocate memory for rx_buffer structures. Since we use one 2762 * rx_buffer per received packet, the maximum number of rx_buffer's 2763 * that we'll need is equal to the number of receive descriptors 2764 * that we've allocated. 2765 * 2766 **********************************************************************/ 2767static int 2768em_allocate_receive_structures(struct em_softc *sc) 2769{ 2770 device_t dev = sc->dev; 2771 struct em_buffer *rx_buffer; 2772 int i, error; 2773 2774 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2775 M_DEVBUF, M_NOWAIT); 2776 if (sc->rx_buffer_area == NULL) { 2777 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2778 return (ENOMEM); 2779 } 2780 2781 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2782 2783 error = bus_dma_tag_create(NULL, /* parent */ 2784 1, 0, /* alignment, bounds */ 2785 BUS_SPACE_MAXADDR, /* lowaddr */ 2786 BUS_SPACE_MAXADDR, /* highaddr */ 2787 NULL, NULL, /* filter, filterarg */ 2788 MCLBYTES, /* maxsize */ 2789 1, /* nsegments */ 2790 MCLBYTES, /* maxsegsize */ 2791 BUS_DMA_ALLOCNOW, /* flags */ 2792 NULL, /* lockfunc */ 2793 NULL, /* lockarg */ 2794 &sc->rxtag); 2795 if (error) { 2796 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2797 __func__, error); 2798 goto fail; 2799 } 2800 2801 rx_buffer = sc->rx_buffer_area; 2802 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2803 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2804 &rx_buffer->map); 2805 if (error) { 2806 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2807 __func__, error); 2808 goto fail; 2809 } 2810 } 2811 2812 for (i = 0; i < sc->num_rx_desc; i++) { 2813 error = em_get_buf(i, sc, NULL); 2814 if (error) 2815 goto fail; 2816 } 2817 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2818 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2819 2820 return (0); 2821 2822fail: 2823 em_free_receive_structures(sc); 2824 return (error); 2825} 2826 2827/********************************************************************* 2828 * 2829 * Allocate and initialize receive structures. 2830 * 2831 **********************************************************************/ 2832static int 2833em_setup_receive_structures(struct em_softc *sc) 2834{ 2835 int error; 2836 2837 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2838 2839 if ((error = em_allocate_receive_structures(sc)) != 0) 2840 return (error); 2841 2842 /* Setup our descriptor pointers */ 2843 sc->next_rx_desc_to_check = 0; 2844 2845 return (0); 2846} 2847 2848/********************************************************************* 2849 * 2850 * Enable receive unit. 2851 * 2852 **********************************************************************/ 2853static void 2854em_initialize_receive_unit(struct em_softc *sc) 2855{ 2856 struct ifnet *ifp = sc->ifp; 2857 uint64_t bus_addr; 2858 uint32_t reg_rctl; 2859 uint32_t reg_rxcsum; 2860 2861 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2862 2863 /* 2864 * Make sure receives are disabled while setting 2865 * up the descriptor ring 2866 */ 2867 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2868 2869 /* Set the Receive Delay Timer Register */ 2870 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2871 2872 if(sc->hw.mac_type >= em_82540) { 2873 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2874 2875 /* 2876 * Set the interrupt throttling rate. Value is calculated 2877 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2878 */ 2879#define MAX_INTS_PER_SEC 8000 2880#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2881 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2882 } 2883 2884 /* Setup the Base and Length of the Rx Descriptor Ring */ 2885 bus_addr = sc->rxdma.dma_paddr; 2886 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2887 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2888 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2889 sizeof(struct em_rx_desc)); 2890 2891 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2892 E1000_WRITE_REG(&sc->hw, RDH, 0); 2893 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2894 2895 /* Setup the Receive Control Register */ 2896 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2897 E1000_RCTL_RDMTS_HALF | 2898 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2899 2900 if (sc->hw.tbi_compatibility_on == TRUE) 2901 reg_rctl |= E1000_RCTL_SBP; 2902 2903 2904 switch (sc->rx_buffer_len) { 2905 default: 2906 case EM_RXBUFFER_2048: 2907 reg_rctl |= E1000_RCTL_SZ_2048; 2908 break; 2909 case EM_RXBUFFER_4096: 2910 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2911 break; 2912 case EM_RXBUFFER_8192: 2913 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2914 break; 2915 case EM_RXBUFFER_16384: 2916 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2917 break; 2918 } 2919 2920 if (ifp->if_mtu > ETHERMTU) 2921 reg_rctl |= E1000_RCTL_LPE; 2922 2923 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2924 if ((sc->hw.mac_type >= em_82543) && 2925 (ifp->if_capenable & IFCAP_RXCSUM)) { 2926 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2927 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2928 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2929 } 2930 2931 /* Enable Receives */ 2932 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2933} 2934 2935/********************************************************************* 2936 * 2937 * Free receive related data structures. 2938 * 2939 **********************************************************************/ 2940static void 2941em_free_receive_structures(struct em_softc *sc) 2942{ 2943 struct em_buffer *rx_buffer; 2944 int i; 2945 2946 INIT_DEBUGOUT("free_receive_structures: begin"); 2947 2948 if (sc->rx_buffer_area != NULL) { 2949 rx_buffer = sc->rx_buffer_area; 2950 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2951 if (rx_buffer->m_head != NULL) { 2952 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2953 BUS_DMASYNC_POSTREAD); 2954 bus_dmamap_unload(sc->rxtag, 2955 rx_buffer->map); 2956 m_freem(rx_buffer->m_head); 2957 rx_buffer->m_head = NULL; 2958 } else if (rx_buffer->map != NULL) 2959 bus_dmamap_unload(sc->rxtag, 2960 rx_buffer->map); 2961 if (rx_buffer->map != NULL) { 2962 bus_dmamap_destroy(sc->rxtag, 2963 rx_buffer->map); 2964 rx_buffer->map = NULL; 2965 } 2966 } 2967 } 2968 if (sc->rx_buffer_area != NULL) { 2969 free(sc->rx_buffer_area, M_DEVBUF); 2970 sc->rx_buffer_area = NULL; 2971 } 2972 if (sc->rxtag != NULL) { 2973 bus_dma_tag_destroy(sc->rxtag); 2974 sc->rxtag = NULL; 2975 } 2976} 2977 2978/********************************************************************* 2979 * 2980 * This routine executes in interrupt context. It replenishes 2981 * the mbufs in the descriptor and sends data which has been 2982 * dma'ed into host memory to upper layer. 2983 * 2984 * We loop at most count times if count is > 0, or until done if 2985 * count < 0. 2986 * 2987 *********************************************************************/ 2988static int 2989em_rxeof(struct em_softc *sc, int count) 2990{ 2991 struct ifnet *ifp; 2992 struct mbuf *mp; 2993 uint8_t accept_frame = 0; 2994 uint8_t eop = 0; 2995 uint16_t len, desc_len, prev_len_adj; 2996 int i; 2997 2998 /* Pointer to the receive descriptor being examined. */ 2999 struct em_rx_desc *current_desc; 3000 3001 ifp = sc->ifp; 3002 i = sc->next_rx_desc_to_check; 3003 current_desc = &sc->rx_desc_base[i]; 3004 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3005 BUS_DMASYNC_POSTREAD); 3006 3007 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3008 return (0); 3009 3010 while ((current_desc->status & E1000_RXD_STAT_DD) && 3011 (count != 0) && 3012 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3013 struct mbuf *m = NULL; 3014 3015 mp = sc->rx_buffer_area[i].m_head; 3016 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3017 BUS_DMASYNC_POSTREAD); 3018 bus_dmamap_unload(sc->rxtag, 3019 sc->rx_buffer_area[i].map); 3020 3021 accept_frame = 1; 3022 prev_len_adj = 0; 3023 desc_len = le16toh(current_desc->length); 3024 if (current_desc->status & E1000_RXD_STAT_EOP) { 3025 count--; 3026 eop = 1; 3027 if (desc_len < ETHER_CRC_LEN) { 3028 len = 0; 3029 prev_len_adj = ETHER_CRC_LEN - desc_len; 3030 } else 3031 len = desc_len - ETHER_CRC_LEN; 3032 } else { 3033 eop = 0; 3034 len = desc_len; 3035 } 3036 3037 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3038 uint8_t last_byte; 3039 uint32_t pkt_len = desc_len; 3040 3041 if (sc->fmp != NULL) 3042 pkt_len += sc->fmp->m_pkthdr.len; 3043 3044 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3045 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3046 current_desc->errors, 3047 pkt_len, last_byte)) { 3048 em_tbi_adjust_stats(&sc->hw, 3049 &sc->stats, pkt_len, 3050 sc->hw.mac_addr); 3051 if (len > 0) 3052 len--; 3053 } else 3054 accept_frame = 0; 3055 } 3056 3057 if (accept_frame) { 3058 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3059 sc->dropped_pkts++; 3060 em_get_buf(i, sc, mp); 3061 if (sc->fmp != NULL) 3062 m_freem(sc->fmp); 3063 sc->fmp = NULL; 3064 sc->lmp = NULL; 3065 break; 3066 } 3067 3068 /* Assign correct length to the current fragment */ 3069 mp->m_len = len; 3070 3071 if (sc->fmp == NULL) { 3072 mp->m_pkthdr.len = len; 3073 sc->fmp = mp; /* Store the first mbuf */ 3074 sc->lmp = mp; 3075 } else { 3076 /* Chain mbuf's together */ 3077 mp->m_flags &= ~M_PKTHDR; 3078 /* 3079 * Adjust length of previous mbuf in chain if 3080 * we received less than 4 bytes in the last 3081 * descriptor. 3082 */ 3083 if (prev_len_adj > 0) { 3084 sc->lmp->m_len -= prev_len_adj; 3085 sc->fmp->m_pkthdr.len -= 3086 prev_len_adj; 3087 } 3088 sc->lmp->m_next = mp; 3089 sc->lmp = sc->lmp->m_next; 3090 sc->fmp->m_pkthdr.len += len; 3091 } 3092 3093 if (eop) { 3094 sc->fmp->m_pkthdr.rcvif = ifp; 3095 ifp->if_ipackets++; 3096 em_receive_checksum(sc, current_desc, 3097 sc->fmp); 3098#ifndef __NO_STRICT_ALIGNMENT 3099 if (ifp->if_mtu > ETHERMTU && 3100 em_fixup_rx(sc) != 0) 3101 goto skip; 3102#endif 3103 if (current_desc->status & E1000_RXD_STAT_VP) 3104 VLAN_INPUT_TAG(ifp, sc->fmp, 3105 (le16toh(current_desc->special) & 3106 E1000_RXD_SPC_VLAN_MASK)); 3107#ifndef __NO_STRICT_ALIGNMENT 3108skip: 3109#endif 3110 m = sc->fmp; 3111 sc->fmp = NULL; 3112 sc->lmp = NULL; 3113 } 3114 } else { 3115 sc->dropped_pkts++; 3116 em_get_buf(i, sc, mp); 3117 if (sc->fmp != NULL) 3118 m_freem(sc->fmp); 3119 sc->fmp = NULL; 3120 sc->lmp = NULL; 3121 } 3122 3123 /* Zero out the receive descriptors status. */ 3124 current_desc->status = 0; 3125 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3126 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3127 3128 /* Advance our pointers to the next descriptor. */ 3129 if (++i == sc->num_rx_desc) 3130 i = 0; 3131 if (m != NULL) { 3132 sc->next_rx_desc_to_check = i; 3133#ifdef DEVICE_POLLING 3134 EM_UNLOCK(sc); 3135 (*ifp->if_input)(ifp, m); 3136 EM_LOCK(sc); 3137#else 3138 (*ifp->if_input)(ifp, m); 3139#endif 3140 i = sc->next_rx_desc_to_check; 3141 } 3142 current_desc = &sc->rx_desc_base[i]; 3143 } 3144 sc->next_rx_desc_to_check = i; 3145 3146 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3147 if (--i < 0) 3148 i = sc->num_rx_desc - 1; 3149 E1000_WRITE_REG(&sc->hw, RDT, i); 3150 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3151 return (0); 3152 3153 return (1); 3154} 3155 3156#ifndef __NO_STRICT_ALIGNMENT 3157/* 3158 * When jumbo frames are enabled we should realign entire payload on 3159 * architecures with strict alignment. This is serious design mistake of 8254x 3160 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3161 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3162 * payload. On architecures without strict alignment restrictions 8254x still 3163 * performs unaligned memory access which would reduce the performance too. 3164 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3165 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3166 * existing mbuf chain. 3167 * 3168 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3169 * not used at all on architectures with strict alignment. 3170 */ 3171static int 3172em_fixup_rx(struct em_softc *sc) 3173{ 3174 struct mbuf *m, *n; 3175 int error; 3176 3177 error = 0; 3178 m = sc->fmp; 3179 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3180 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3181 m->m_data += ETHER_HDR_LEN; 3182 } else { 3183 MGETHDR(n, M_DONTWAIT, MT_DATA); 3184 if (n != NULL) { 3185 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3186 m->m_data += ETHER_HDR_LEN; 3187 m->m_len -= ETHER_HDR_LEN; 3188 n->m_len = ETHER_HDR_LEN; 3189 M_MOVE_PKTHDR(n, m); 3190 n->m_next = m; 3191 sc->fmp = n; 3192 } else { 3193 sc->dropped_pkts++; 3194 m_freem(sc->fmp); 3195 sc->fmp = NULL; 3196 error = ENOMEM; 3197 } 3198 } 3199 3200 return (error); 3201} 3202#endif 3203 3204/********************************************************************* 3205 * 3206 * Verify that the hardware indicated that the checksum is valid. 3207 * Inform the stack about the status of checksum so that stack 3208 * doesn't spend time verifying the checksum. 3209 * 3210 *********************************************************************/ 3211static void 3212em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3213 struct mbuf *mp) 3214{ 3215 /* 82543 or newer only */ 3216 if ((sc->hw.mac_type < em_82543) || 3217 /* Ignore Checksum bit is set */ 3218 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3219 mp->m_pkthdr.csum_flags = 0; 3220 return; 3221 } 3222 3223 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3224 /* Did it pass? */ 3225 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3226 /* IP Checksum Good */ 3227 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3228 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3229 3230 } else { 3231 mp->m_pkthdr.csum_flags = 0; 3232 } 3233 } 3234 3235 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3236 /* Did it pass? */ 3237 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3238 mp->m_pkthdr.csum_flags |= 3239 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3240 mp->m_pkthdr.csum_data = htons(0xffff); 3241 } 3242 } 3243} 3244 3245 3246static void 3247em_enable_vlans(struct em_softc *sc) 3248{ 3249 uint32_t ctrl; 3250 3251 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3252 3253 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3254 ctrl |= E1000_CTRL_VME; 3255 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3256} 3257 3258static void 3259em_disable_vlans(struct em_softc *sc) 3260{ 3261 uint32_t ctrl; 3262 3263 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3264 ctrl &= ~E1000_CTRL_VME; 3265 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3266} 3267 3268static void 3269em_enable_intr(struct em_softc *sc) 3270{ 3271 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3272} 3273 3274static void 3275em_disable_intr(struct em_softc *sc) 3276{ 3277 /* 3278 * The first version of 82542 had an errata where when link was forced 3279 * it would stay up even up even if the cable was disconnected. 3280 * Sequence errors were used to detect the disconnect and then the 3281 * driver would unforce the link. This code in the in the ISR. For this 3282 * to work correctly the Sequence error interrupt had to be enabled 3283 * all the time. 3284 */ 3285 3286 if (sc->hw.mac_type == em_82542_rev2_0) 3287 E1000_WRITE_REG(&sc->hw, IMC, 3288 (0xffffffff & ~E1000_IMC_RXSEQ)); 3289 else 3290 E1000_WRITE_REG(&sc->hw, IMC, 3291 0xffffffff); 3292} 3293 3294static int 3295em_is_valid_ether_addr(uint8_t *addr) 3296{ 3297 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3298 3299 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3300 return (FALSE); 3301 } 3302 3303 return (TRUE); 3304} 3305 3306void 3307em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3308{ 3309 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3310} 3311 3312void 3313em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3314{ 3315 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3316} 3317 3318void 3319em_pci_set_mwi(struct em_hw *hw) 3320{ 3321 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3322 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3323} 3324 3325void 3326em_pci_clear_mwi(struct em_hw *hw) 3327{ 3328 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3329 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3330} 3331 3332/********************************************************************* 3333* 82544 Coexistence issue workaround. 3334* There are 2 issues. 3335* 1. Transmit Hang issue. 3336* To detect this issue, following equation can be used... 3337* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3338* If SUM[3:0] is in between 1 to 4, we will have this issue. 3339* 3340* 2. DAC issue. 3341* To detect this issue, following equation can be used... 3342* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3343* If SUM[3:0] is in between 9 to c, we will have this issue. 3344* 3345* 3346* WORKAROUND: 3347* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3348* 3349*** *********************************************************************/ 3350static uint32_t 3351em_fill_descriptors (bus_addr_t address, uint32_t length, 3352 PDESC_ARRAY desc_array) 3353{ 3354 /* Since issue is sensitive to length and address.*/ 3355 /* Let us first check the address...*/ 3356 uint32_t safe_terminator; 3357 if (length <= 4) { 3358 desc_array->descriptor[0].address = address; 3359 desc_array->descriptor[0].length = length; 3360 desc_array->elements = 1; 3361 return (desc_array->elements); 3362 } 3363 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3364 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3365 if (safe_terminator == 0 || 3366 (safe_terminator > 4 && 3367 safe_terminator < 9) || 3368 (safe_terminator > 0xC && 3369 safe_terminator <= 0xF)) { 3370 desc_array->descriptor[0].address = address; 3371 desc_array->descriptor[0].length = length; 3372 desc_array->elements = 1; 3373 return (desc_array->elements); 3374 } 3375 3376 desc_array->descriptor[0].address = address; 3377 desc_array->descriptor[0].length = length - 4; 3378 desc_array->descriptor[1].address = address + (length - 4); 3379 desc_array->descriptor[1].length = 4; 3380 desc_array->elements = 2; 3381 return (desc_array->elements); 3382} 3383 3384/********************************************************************** 3385 * 3386 * Update the board statistics counters. 3387 * 3388 **********************************************************************/ 3389static void 3390em_update_stats_counters(struct em_softc *sc) 3391{ 3392 struct ifnet *ifp; 3393 3394 if(sc->hw.media_type == em_media_type_copper || 3395 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3396 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3397 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3398 } 3399 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3400 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3401 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3402 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3403 3404 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3405 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3406 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3407 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3408 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3409 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3410 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3411 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3412 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3413 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3414 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3415 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3416 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3417 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3418 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3419 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3420 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3421 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3422 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3423 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3424 3425 /* For the 64-bit byte counters the low dword must be read first. */ 3426 /* Both registers clear on the read of the high dword */ 3427 3428 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3429 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3430 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3431 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3432 3433 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3434 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3435 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3436 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3437 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3438 3439 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3440 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3441 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3442 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3443 3444 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3445 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3446 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3447 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3448 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3449 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3450 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3451 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3452 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3453 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3454 3455 if (sc->hw.mac_type >= em_82543) { 3456 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3457 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3458 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3459 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3460 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3461 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3462 } 3463 ifp = sc->ifp; 3464 3465 ifp->if_collisions = sc->stats.colc; 3466 3467 /* Rx Errors */ 3468 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3469 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3470 sc->stats.mpc + sc->stats.cexterr; 3471 3472 /* Tx Errors */ 3473 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3474 sc->watchdog_events; 3475} 3476 3477 3478/********************************************************************** 3479 * 3480 * This routine is called only when em_display_debug_stats is enabled. 3481 * This routine provides a way to take a look at important statistics 3482 * maintained by the driver and hardware. 3483 * 3484 **********************************************************************/ 3485static void 3486em_print_debug_info(struct em_softc *sc) 3487{ 3488 device_t dev = sc->dev; 3489 uint8_t *hw_addr = sc->hw.hw_addr; 3490 3491 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3492 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3493 E1000_READ_REG(&sc->hw, CTRL), 3494 E1000_READ_REG(&sc->hw, RCTL)); 3495 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3496 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3497 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3498 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3499 sc->hw.fc_high_water, 3500 sc->hw.fc_low_water); 3501 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3502 E1000_READ_REG(&sc->hw, TIDV), 3503 E1000_READ_REG(&sc->hw, TADV)); 3504 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3505 E1000_READ_REG(&sc->hw, RDTR), 3506 E1000_READ_REG(&sc->hw, RADV)); 3507 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3508 (long long)sc->tx_fifo_wrk_cnt, 3509 (long long)sc->tx_fifo_reset_cnt); 3510 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3511 E1000_READ_REG(&sc->hw, TDH), 3512 E1000_READ_REG(&sc->hw, TDT)); 3513 device_printf(dev, "Num Tx descriptors avail = %d\n", 3514 sc->num_tx_desc_avail); 3515 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3516 sc->no_tx_desc_avail1); 3517 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3518 sc->no_tx_desc_avail2); 3519 device_printf(dev, "Std mbuf failed = %ld\n", 3520 sc->mbuf_alloc_failed); 3521 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3522 sc->mbuf_cluster_failed); 3523 device_printf(dev, "Driver dropped packets = %ld\n", 3524 sc->dropped_pkts); 3525} 3526 3527static void 3528em_print_hw_stats(struct em_softc *sc) 3529{ 3530 device_t dev = sc->dev; 3531 3532 device_printf(dev, "Excessive collisions = %lld\n", 3533 (long long)sc->stats.ecol); 3534 device_printf(dev, "Symbol errors = %lld\n", 3535 (long long)sc->stats.symerrs); 3536 device_printf(dev, "Sequence errors = %lld\n", 3537 (long long)sc->stats.sec); 3538 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3539 3540 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3541 device_printf(dev, "Receive No Buffers = %lld\n", 3542 (long long)sc->stats.rnbc); 3543 device_printf(dev, "Receive length errors = %lld\n", 3544 (long long)sc->stats.rlec); 3545 device_printf(dev, "Receive errors = %lld\n", 3546 (long long)sc->stats.rxerrc); 3547 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3548 device_printf(dev, "Alignment errors = %lld\n", 3549 (long long)sc->stats.algnerrc); 3550 device_printf(dev, "Carrier extension errors = %lld\n", 3551 (long long)sc->stats.cexterr); 3552 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3553 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3554 3555 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3556 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3557 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3558 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3559 3560 device_printf(dev, "Good Packets Rcvd = %lld\n", 3561 (long long)sc->stats.gprc); 3562 device_printf(dev, "Good Packets Xmtd = %lld\n", 3563 (long long)sc->stats.gptc); 3564} 3565 3566static int 3567em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3568{ 3569 struct em_softc *sc; 3570 int error; 3571 int result; 3572 3573 result = -1; 3574 error = sysctl_handle_int(oidp, &result, 0, req); 3575 3576 if (error || !req->newptr) 3577 return (error); 3578 3579 if (result == 1) { 3580 sc = (struct em_softc *)arg1; 3581 em_print_debug_info(sc); 3582 } 3583 3584 return (error); 3585} 3586 3587 3588static int 3589em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3590{ 3591 struct em_softc *sc; 3592 int error; 3593 int result; 3594 3595 result = -1; 3596 error = sysctl_handle_int(oidp, &result, 0, req); 3597 3598 if (error || !req->newptr) 3599 return (error); 3600 3601 if (result == 1) { 3602 sc = (struct em_softc *)arg1; 3603 em_print_hw_stats(sc); 3604 } 3605 3606 return (error); 3607} 3608 3609static int 3610em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3611{ 3612 struct em_int_delay_info *info; 3613 struct em_softc *sc; 3614 uint32_t regval; 3615 int error; 3616 int usecs; 3617 int ticks; 3618 3619 info = (struct em_int_delay_info *)arg1; 3620 usecs = info->value; 3621 error = sysctl_handle_int(oidp, &usecs, 0, req); 3622 if (error != 0 || req->newptr == NULL) 3623 return (error); 3624 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3625 return (EINVAL); 3626 info->value = usecs; 3627 ticks = E1000_USECS_TO_TICKS(usecs); 3628 3629 sc = info->sc; 3630 3631 EM_LOCK(sc); 3632 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3633 regval = (regval & ~0xffff) | (ticks & 0xffff); 3634 /* Handle a few special cases. */ 3635 switch (info->offset) { 3636 case E1000_RDTR: 3637 case E1000_82542_RDTR: 3638 regval |= E1000_RDT_FPDB; 3639 break; 3640 case E1000_TIDV: 3641 case E1000_82542_TIDV: 3642 if (ticks == 0) { 3643 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3644 /* Don't write 0 into the TIDV register. */ 3645 regval++; 3646 } else 3647 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3648 break; 3649 } 3650 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3651 EM_UNLOCK(sc); 3652 return (0); 3653} 3654 3655static void 3656em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3657 const char *description, struct em_int_delay_info *info, 3658 int offset, int value) 3659{ 3660 info->sc = sc; 3661 info->offset = offset; 3662 info->value = value; 3663 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3664 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3665 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3666 info, 0, em_sysctl_int_delay, "I", description); 3667} 3668 3669#ifndef DEVICE_POLLING 3670static void 3671em_add_int_process_limit(struct em_softc *sc, const char *name, 3672 const char *description, int *limit, int value) 3673{ 3674 *limit = value; 3675 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3676 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3677 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3678} 3679#endif 3680