if_em.c revision 159330
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 159330 2006-06-06 08:03:49Z glebius $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 5.1.5"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 143 PCI_ANY_ID, PCI_ANY_ID, 0}, 144 145 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 149 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 153 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 158 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 159 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 162 PCI_ANY_ID, PCI_ANY_ID, 0}, 163 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 164 PCI_ANY_ID, PCI_ANY_ID, 0}, 165 166 /* required last entry */ 167 { 0, 0, 0, 0, 0} 168}; 169 170/********************************************************************* 171 * Table of branding strings for all supported NICs. 172 *********************************************************************/ 173 174static char *em_strings[] = { 175 "Intel(R) PRO/1000 Network Connection" 176}; 177 178/********************************************************************* 179 * Function prototypes 180 *********************************************************************/ 181static int em_probe(device_t); 182static int em_attach(device_t); 183static int em_detach(device_t); 184static int em_shutdown(device_t); 185static int em_suspend(device_t); 186static int em_resume(device_t); 187static void em_start(struct ifnet *); 188static void em_start_locked(struct ifnet *ifp); 189static int em_ioctl(struct ifnet *, u_long, caddr_t); 190static void em_watchdog(struct ifnet *); 191static void em_init(void *); 192static void em_init_locked(struct em_softc *); 193static void em_stop(void *); 194static void em_media_status(struct ifnet *, struct ifmediareq *); 195static int em_media_change(struct ifnet *); 196static void em_identify_hardware(struct em_softc *); 197static int em_allocate_pci_resources(struct em_softc *); 198static int em_allocate_intr(struct em_softc *); 199static void em_free_intr(struct em_softc *); 200static void em_free_pci_resources(struct em_softc *); 201static void em_local_timer(void *); 202static int em_hardware_init(struct em_softc *); 203static void em_setup_interface(device_t, struct em_softc *); 204static int em_setup_transmit_structures(struct em_softc *); 205static void em_initialize_transmit_unit(struct em_softc *); 206static int em_setup_receive_structures(struct em_softc *); 207static void em_initialize_receive_unit(struct em_softc *); 208static void em_enable_intr(struct em_softc *); 209static void em_disable_intr(struct em_softc *); 210static void em_free_transmit_structures(struct em_softc *); 211static void em_free_receive_structures(struct em_softc *); 212static void em_update_stats_counters(struct em_softc *); 213static void em_txeof(struct em_softc *); 214static int em_allocate_receive_structures(struct em_softc *); 215static int em_allocate_transmit_structures(struct em_softc *); 216static int em_rxeof(struct em_softc *, int); 217#ifndef __NO_STRICT_ALIGNMENT 218static int em_fixup_rx(struct em_softc *); 219#endif 220static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 221 struct mbuf *); 222static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 223 uint32_t *, uint32_t *); 224static void em_set_promisc(struct em_softc *); 225static void em_disable_promisc(struct em_softc *); 226static void em_set_multi(struct em_softc *); 227static void em_print_hw_stats(struct em_softc *); 228static void em_update_link_status(struct em_softc *); 229static int em_get_buf(int i, struct em_softc *, struct mbuf *); 230static void em_enable_vlans(struct em_softc *); 231static void em_disable_vlans(struct em_softc *); 232static int em_encap(struct em_softc *, struct mbuf **); 233static void em_smartspeed(struct em_softc *); 234static int em_82547_fifo_workaround(struct em_softc *, int); 235static void em_82547_update_fifo_head(struct em_softc *, int); 236static int em_82547_tx_fifo_reset(struct em_softc *); 237static void em_82547_move_tail(void *arg); 238static void em_82547_move_tail_locked(struct em_softc *); 239static int em_dma_malloc(struct em_softc *, bus_size_t, 240 struct em_dma_alloc *, int); 241static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 242static void em_print_debug_info(struct em_softc *); 243static int em_is_valid_ether_addr(uint8_t *); 244static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 245static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 246static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 247 PDESC_ARRAY desc_array); 248static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 249static void em_add_int_delay_sysctl(struct em_softc *, const char *, 250 const char *, struct em_int_delay_info *, int, int); 251 252/* 253 * Fast interrupt handler and legacy ithread/polling modes are 254 * mutually exclusive. 255 */ 256#ifdef DEVICE_POLLING 257static poll_handler_t em_poll; 258static void em_intr(void *); 259#else 260static void em_intr_fast(void *); 261static void em_add_int_process_limit(struct em_softc *, const char *, 262 const char *, int *, int); 263static void em_handle_rxtx(void *context, int pending); 264static void em_handle_link(void *context, int pending); 265#endif 266 267/********************************************************************* 268 * FreeBSD Device Interface Entry Points 269 *********************************************************************/ 270 271static device_method_t em_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, em_probe), 274 DEVMETHOD(device_attach, em_attach), 275 DEVMETHOD(device_detach, em_detach), 276 DEVMETHOD(device_shutdown, em_shutdown), 277 DEVMETHOD(device_suspend, em_suspend), 278 DEVMETHOD(device_resume, em_resume), 279 {0, 0} 280}; 281 282static driver_t em_driver = { 283 "em", em_methods, sizeof(struct em_softc), 284}; 285 286static devclass_t em_devclass; 287DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 288MODULE_DEPEND(em, pci, 1, 1, 1); 289MODULE_DEPEND(em, ether, 1, 1, 1); 290 291/********************************************************************* 292 * Tunable default values. 293 *********************************************************************/ 294 295#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 296#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 297 298static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 299static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 300static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 301static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 302static int em_rxd = EM_DEFAULT_RXD; 303static int em_txd = EM_DEFAULT_TXD; 304 305TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 306TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 307TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 308TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 309TUNABLE_INT("hw.em.rxd", &em_rxd); 310TUNABLE_INT("hw.em.txd", &em_txd); 311#ifndef DEVICE_POLLING 312static int em_rx_process_limit = 100; 313TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 314#endif 315 316/********************************************************************* 317 * Device identification routine 318 * 319 * em_probe determines if the driver should be loaded on 320 * adapter based on PCI vendor/device id of the adapter. 321 * 322 * return BUS_PROBE_DEFAULT on success, positive on failure 323 *********************************************************************/ 324 325static int 326em_probe(device_t dev) 327{ 328 char adapter_name[60]; 329 uint16_t pci_vendor_id = 0; 330 uint16_t pci_device_id = 0; 331 uint16_t pci_subvendor_id = 0; 332 uint16_t pci_subdevice_id = 0; 333 em_vendor_info_t *ent; 334 335 INIT_DEBUGOUT("em_probe: begin"); 336 337 pci_vendor_id = pci_get_vendor(dev); 338 if (pci_vendor_id != EM_VENDOR_ID) 339 return (ENXIO); 340 341 pci_device_id = pci_get_device(dev); 342 pci_subvendor_id = pci_get_subvendor(dev); 343 pci_subdevice_id = pci_get_subdevice(dev); 344 345 ent = em_vendor_info_array; 346 while (ent->vendor_id != 0) { 347 if ((pci_vendor_id == ent->vendor_id) && 348 (pci_device_id == ent->device_id) && 349 350 ((pci_subvendor_id == ent->subvendor_id) || 351 (ent->subvendor_id == PCI_ANY_ID)) && 352 353 ((pci_subdevice_id == ent->subdevice_id) || 354 (ent->subdevice_id == PCI_ANY_ID))) { 355 sprintf(adapter_name, "%s %s", 356 em_strings[ent->index], 357 em_driver_version); 358 device_set_desc_copy(dev, adapter_name); 359 return (BUS_PROBE_DEFAULT); 360 } 361 ent++; 362 } 363 364 return (ENXIO); 365} 366 367/********************************************************************* 368 * Device initialization routine 369 * 370 * The attach entry point is called when the driver is being loaded. 371 * This routine identifies the type of hardware, allocates all resources 372 * and initializes the hardware. 373 * 374 * return 0 on success, positive on failure 375 *********************************************************************/ 376 377static int 378em_attach(device_t dev) 379{ 380 struct em_softc *sc; 381 int tsize, rsize; 382 int error = 0; 383 384 INIT_DEBUGOUT("em_attach: begin"); 385 386 sc = device_get_softc(dev); 387 sc->dev = sc->osdep.dev = dev; 388 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 389 390 /* SYSCTL stuff */ 391 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 392 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 393 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 394 em_sysctl_debug_info, "I", "Debug Information"); 395 396 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 397 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 398 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 399 em_sysctl_stats, "I", "Statistics"); 400 401 callout_init(&sc->timer, CALLOUT_MPSAFE); 402 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 403 404 /* Determine hardware revision */ 405 em_identify_hardware(sc); 406 407 /* Set up some sysctls for the tunable interrupt delays */ 408 em_add_int_delay_sysctl(sc, "rx_int_delay", 409 "receive interrupt delay in usecs", &sc->rx_int_delay, 410 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 411 em_add_int_delay_sysctl(sc, "tx_int_delay", 412 "transmit interrupt delay in usecs", &sc->tx_int_delay, 413 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 414 if (sc->hw.mac_type >= em_82540) { 415 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 416 "receive interrupt delay limit in usecs", 417 &sc->rx_abs_int_delay, 418 E1000_REG_OFFSET(&sc->hw, RADV), 419 em_rx_abs_int_delay_dflt); 420 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 421 "transmit interrupt delay limit in usecs", 422 &sc->tx_abs_int_delay, 423 E1000_REG_OFFSET(&sc->hw, TADV), 424 em_tx_abs_int_delay_dflt); 425 } 426 427#ifndef DEVICE_POLLING 428 /* Sysctls for limiting the amount of work done in the taskqueue */ 429 em_add_int_process_limit(sc, "rx_processing_limit", 430 "max number of rx packets to process", &sc->rx_process_limit, 431 em_rx_process_limit); 432#endif 433 434 /* 435 * Validate number of transmit and receive descriptors. It 436 * must not exceed hardware maximum, and must be multiple 437 * of E1000_DBA_ALIGN. 438 */ 439 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 440 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 441 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 442 (em_txd < EM_MIN_TXD)) { 443 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 444 EM_DEFAULT_TXD, em_txd); 445 sc->num_tx_desc = EM_DEFAULT_TXD; 446 } else 447 sc->num_tx_desc = em_txd; 448 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 449 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 450 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 451 (em_rxd < EM_MIN_RXD)) { 452 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 453 EM_DEFAULT_RXD, em_rxd); 454 sc->num_rx_desc = EM_DEFAULT_RXD; 455 } else 456 sc->num_rx_desc = em_rxd; 457 458 sc->hw.autoneg = DO_AUTO_NEG; 459 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 460 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 461 sc->hw.tbi_compatibility_en = TRUE; 462 sc->rx_buffer_len = EM_RXBUFFER_2048; 463 464 sc->hw.phy_init_script = 1; 465 sc->hw.phy_reset_disable = FALSE; 466 467#ifndef EM_MASTER_SLAVE 468 sc->hw.master_slave = em_ms_hw_default; 469#else 470 sc->hw.master_slave = EM_MASTER_SLAVE; 471#endif 472 /* 473 * Set the max frame size assuming standard ethernet 474 * sized frames. 475 */ 476 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 477 478 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 479 480 /* 481 * This controls when hardware reports transmit completion 482 * status. 483 */ 484 sc->hw.report_tx_early = 1; 485 if (em_allocate_pci_resources(sc)) { 486 device_printf(dev, "Allocation of PCI resources failed\n"); 487 error = ENXIO; 488 goto err_pci; 489 } 490 491 /* Initialize eeprom parameters */ 492 em_init_eeprom_params(&sc->hw); 493 494 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 495 E1000_DBA_ALIGN); 496 497 /* Allocate Transmit Descriptor ring */ 498 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 499 device_printf(dev, "Unable to allocate tx_desc memory\n"); 500 error = ENOMEM; 501 goto err_tx_desc; 502 } 503 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 504 505 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 506 E1000_DBA_ALIGN); 507 508 /* Allocate Receive Descriptor ring */ 509 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 510 device_printf(dev, "Unable to allocate rx_desc memory\n"); 511 error = ENOMEM; 512 goto err_rx_desc; 513 } 514 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 515 516 /* Initialize the hardware */ 517 if (em_hardware_init(sc)) { 518 device_printf(dev, "Unable to initialize the hardware\n"); 519 error = EIO; 520 goto err_hw_init; 521 } 522 523 /* Copy the permanent MAC address out of the EEPROM */ 524 if (em_read_mac_addr(&sc->hw) < 0) { 525 device_printf(dev, "EEPROM read error while reading MAC" 526 " address\n"); 527 error = EIO; 528 goto err_hw_init; 529 } 530 531 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 532 device_printf(dev, "Invalid MAC address\n"); 533 error = EIO; 534 goto err_hw_init; 535 } 536 537 /* Setup OS specific network interface */ 538 em_setup_interface(dev, sc); 539 540 em_allocate_intr(sc); 541 542 /* Initialize statistics */ 543 em_clear_hw_cntrs(&sc->hw); 544 em_update_stats_counters(sc); 545 sc->hw.get_link_status = 1; 546 em_update_link_status(sc); 547 548 /* Indicate SOL/IDER usage */ 549 if (em_check_phy_reset_block(&sc->hw)) 550 device_printf(dev, 551 "PHY reset is blocked due to SOL/IDER session.\n"); 552 553 /* Identify 82544 on PCIX */ 554 em_get_bus_info(&sc->hw); 555 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 556 sc->pcix_82544 = TRUE; 557 else 558 sc->pcix_82544 = FALSE; 559 560 INIT_DEBUGOUT("em_attach: end"); 561 562 return (0); 563 564err_hw_init: 565 em_dma_free(sc, &sc->rxdma); 566err_rx_desc: 567 em_dma_free(sc, &sc->txdma); 568err_tx_desc: 569err_pci: 570 em_free_intr(sc); 571 em_free_pci_resources(sc); 572 EM_LOCK_DESTROY(sc); 573 574 return (error); 575} 576 577/********************************************************************* 578 * Device removal routine 579 * 580 * The detach entry point is called when the driver is being removed. 581 * This routine stops the adapter and deallocates all the resources 582 * that were allocated for driver operation. 583 * 584 * return 0 on success, positive on failure 585 *********************************************************************/ 586 587static int 588em_detach(device_t dev) 589{ 590 struct em_softc *sc = device_get_softc(dev); 591 struct ifnet *ifp = sc->ifp; 592 593 INIT_DEBUGOUT("em_detach: begin"); 594 595#ifdef DEVICE_POLLING 596 if (ifp->if_capenable & IFCAP_POLLING) 597 ether_poll_deregister(ifp); 598#endif 599 600 em_free_intr(sc); 601 EM_LOCK(sc); 602 sc->in_detach = 1; 603 em_stop(sc); 604 em_phy_hw_reset(&sc->hw); 605 EM_UNLOCK(sc); 606 ether_ifdetach(sc->ifp); 607 608 em_free_pci_resources(sc); 609 bus_generic_detach(dev); 610 if_free(ifp); 611 612 /* Free Transmit Descriptor ring */ 613 if (sc->tx_desc_base) { 614 em_dma_free(sc, &sc->txdma); 615 sc->tx_desc_base = NULL; 616 } 617 618 /* Free Receive Descriptor ring */ 619 if (sc->rx_desc_base) { 620 em_dma_free(sc, &sc->rxdma); 621 sc->rx_desc_base = NULL; 622 } 623 624 EM_LOCK_DESTROY(sc); 625 626 return (0); 627} 628 629/********************************************************************* 630 * 631 * Shutdown entry point 632 * 633 **********************************************************************/ 634 635static int 636em_shutdown(device_t dev) 637{ 638 struct em_softc *sc = device_get_softc(dev); 639 EM_LOCK(sc); 640 em_stop(sc); 641 EM_UNLOCK(sc); 642 return (0); 643} 644 645/* 646 * Suspend/resume device methods. 647 */ 648static int 649em_suspend(device_t dev) 650{ 651 struct em_softc *sc = device_get_softc(dev); 652 653 EM_LOCK(sc); 654 em_stop(sc); 655 EM_UNLOCK(sc); 656 657 return bus_generic_suspend(dev); 658} 659 660static int 661em_resume(device_t dev) 662{ 663 struct em_softc *sc = device_get_softc(dev); 664 struct ifnet *ifp = sc->ifp; 665 666 EM_LOCK(sc); 667 em_init_locked(sc); 668 if ((ifp->if_flags & IFF_UP) && 669 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 670 em_start_locked(ifp); 671 EM_UNLOCK(sc); 672 673 return bus_generic_resume(dev); 674} 675 676 677/********************************************************************* 678 * Transmit entry point 679 * 680 * em_start is called by the stack to initiate a transmit. 681 * The driver will remain in this routine as long as there are 682 * packets to transmit and transmit resources are available. 683 * In case resources are not available stack is notified and 684 * the packet is requeued. 685 **********************************************************************/ 686 687static void 688em_start_locked(struct ifnet *ifp) 689{ 690 struct em_softc *sc = ifp->if_softc; 691 struct mbuf *m_head; 692 693 EM_LOCK_ASSERT(sc); 694 695 if (!sc->link_active) 696 return; 697 698 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 699 700 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 701 if (m_head == NULL) 702 break; 703 /* 704 * em_encap() can modify our pointer, and or make it NULL on 705 * failure. In that event, we can't requeue. 706 */ 707 if (em_encap(sc, &m_head)) { 708 if (m_head == NULL) 709 break; 710 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 711 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 712 break; 713 } 714 715 /* Send a copy of the frame to the BPF listener */ 716 BPF_MTAP(ifp, m_head); 717 718 /* Set timeout in case hardware has problems transmitting. */ 719 ifp->if_timer = EM_TX_TIMEOUT; 720 } 721} 722 723static void 724em_start(struct ifnet *ifp) 725{ 726 struct em_softc *sc = ifp->if_softc; 727 728 EM_LOCK(sc); 729 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 730 em_start_locked(ifp); 731 EM_UNLOCK(sc); 732} 733 734/********************************************************************* 735 * Ioctl entry point 736 * 737 * em_ioctl is called when the user wants to configure the 738 * interface. 739 * 740 * return 0 on success, positive on failure 741 **********************************************************************/ 742 743static int 744em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 745{ 746 struct em_softc *sc = ifp->if_softc; 747 struct ifreq *ifr = (struct ifreq *)data; 748 int error = 0; 749 750 if (sc->in_detach) 751 return (error); 752 753 switch (command) { 754 case SIOCSIFADDR: 755 case SIOCGIFADDR: 756 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 757 ether_ioctl(ifp, command, data); 758 break; 759 case SIOCSIFMTU: 760 { 761 int max_frame_size; 762 uint16_t eeprom_data = 0; 763 764 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 765 766 switch (sc->hw.mac_type) { 767 case em_82573: 768 /* 769 * 82573 only supports jumbo frames 770 * if ASPM is disabled. 771 */ 772 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1, 773 &eeprom_data); 774 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 775 max_frame_size = ETHER_MAX_LEN; 776 break; 777 } 778 /* Allow Jumbo frames - fall thru */ 779 case em_82571: 780 case em_82572: 781 case em_80003es2lan: /* Limit Jumbo Frame size */ 782 max_frame_size = 9234; 783 break; 784 default: 785 max_frame_size = MAX_JUMBO_FRAME_SIZE; 786 } 787 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 788 ETHER_CRC_LEN) { 789 error = EINVAL; 790 break; 791 } 792 793 EM_LOCK(sc); 794 ifp->if_mtu = ifr->ifr_mtu; 795 sc->hw.max_frame_size = 796 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 797 em_init_locked(sc); 798 EM_UNLOCK(sc); 799 break; 800 } 801 case SIOCSIFFLAGS: 802 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 803 EM_LOCK(sc); 804 if (ifp->if_flags & IFF_UP) { 805 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 806 em_init_locked(sc); 807 } 808 809 em_disable_promisc(sc); 810 em_set_promisc(sc); 811 } else { 812 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 813 em_stop(sc); 814 } 815 } 816 EM_UNLOCK(sc); 817 break; 818 case SIOCADDMULTI: 819 case SIOCDELMULTI: 820 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 821 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 822 EM_LOCK(sc); 823 em_disable_intr(sc); 824 em_set_multi(sc); 825 if (sc->hw.mac_type == em_82542_rev2_0) { 826 em_initialize_receive_unit(sc); 827 } 828#ifdef DEVICE_POLLING 829 if (!(ifp->if_capenable & IFCAP_POLLING)) 830#endif 831 em_enable_intr(sc); 832 EM_UNLOCK(sc); 833 } 834 break; 835 case SIOCSIFMEDIA: 836 case SIOCGIFMEDIA: 837 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 838 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 839 break; 840 case SIOCSIFCAP: 841 { 842 int mask, reinit; 843 844 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 845 reinit = 0; 846 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 847#ifdef DEVICE_POLLING 848 if (mask & IFCAP_POLLING) { 849 if (ifr->ifr_reqcap & IFCAP_POLLING) { 850 error = ether_poll_register(em_poll, ifp); 851 if (error) 852 return (error); 853 EM_LOCK(sc); 854 em_disable_intr(sc); 855 ifp->if_capenable |= IFCAP_POLLING; 856 EM_UNLOCK(sc); 857 } else { 858 error = ether_poll_deregister(ifp); 859 /* Enable interrupt even in error case */ 860 EM_LOCK(sc); 861 em_enable_intr(sc); 862 ifp->if_capenable &= ~IFCAP_POLLING; 863 EM_UNLOCK(sc); 864 } 865 } 866#endif 867 if (mask & IFCAP_HWCSUM) { 868 ifp->if_capenable ^= IFCAP_HWCSUM; 869 reinit = 1; 870 } 871 if (mask & IFCAP_VLAN_HWTAGGING) { 872 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 873 reinit = 1; 874 } 875 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 876 em_init(sc); 877 VLAN_CAPABILITIES(ifp); 878 break; 879 } 880 default: 881 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 882 error = EINVAL; 883 } 884 885 return (error); 886} 887 888/********************************************************************* 889 * Watchdog entry point 890 * 891 * This routine is called whenever hardware quits transmitting. 892 * 893 **********************************************************************/ 894 895static void 896em_watchdog(struct ifnet *ifp) 897{ 898 struct em_softc *sc = ifp->if_softc; 899 900 EM_LOCK(sc); 901 /* If we are in this routine because of pause frames, then 902 * don't reset the hardware. 903 */ 904 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 905 ifp->if_timer = EM_TX_TIMEOUT; 906 EM_UNLOCK(sc); 907 return; 908 } 909 910 if (em_check_for_link(&sc->hw) == 0) 911 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 912 913 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 914 sc->watchdog_events++; 915 916 em_init_locked(sc); 917 EM_UNLOCK(sc); 918} 919 920/********************************************************************* 921 * Init entry point 922 * 923 * This routine is used in two ways. It is used by the stack as 924 * init entry point in network interface structure. It is also used 925 * by the driver as a hw/sw initialization routine to get to a 926 * consistent state. 927 * 928 * return 0 on success, positive on failure 929 **********************************************************************/ 930 931static void 932em_init_locked(struct em_softc *sc) 933{ 934 struct ifnet *ifp = sc->ifp; 935 device_t dev = sc->dev; 936 uint32_t pba; 937 938 INIT_DEBUGOUT("em_init: begin"); 939 940 EM_LOCK_ASSERT(sc); 941 942 em_stop(sc); 943 944 /* 945 * Packet Buffer Allocation (PBA) 946 * Writing PBA sets the receive portion of the buffer 947 * the remainder is used for the transmit buffer. 948 */ 949 switch (sc->hw.mac_type) { 950 case em_82547: 951 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 952 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 953 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 954 else 955 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 956 sc->tx_fifo_head = 0; 957 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 958 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 959 break; 960 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */ 961 case em_82571: /* 82571: Total Packet Buffer is 48K */ 962 case em_82572: /* 82572: Total Packet Buffer is 48K */ 963 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 964 break; 965 case em_82573: /* 82573: Total Packet Buffer is 32K */ 966 /* Jumbo frames not supported */ 967 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 968 break; 969 default: 970 /* Devices before 82547 had a Packet Buffer of 64K. */ 971 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 972 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 973 else 974 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 975 } 976 977 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 978 E1000_WRITE_REG(&sc->hw, PBA, pba); 979 980 /* Get the latest mac address, User can use a LAA */ 981 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 982 983 /* Initialize the hardware */ 984 if (em_hardware_init(sc)) { 985 device_printf(dev, "Unable to initialize the hardware\n"); 986 return; 987 } 988 em_update_link_status(sc); 989 990 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 991 em_enable_vlans(sc); 992 993 /* Prepare transmit descriptors and buffers */ 994 if (em_setup_transmit_structures(sc)) { 995 device_printf(dev, "Could not setup transmit structures\n"); 996 em_stop(sc); 997 return; 998 } 999 em_initialize_transmit_unit(sc); 1000 1001 /* Setup Multicast table */ 1002 em_set_multi(sc); 1003 1004 /* Prepare receive descriptors and buffers */ 1005 if (em_setup_receive_structures(sc)) { 1006 device_printf(dev, "Could not setup receive structures\n"); 1007 em_stop(sc); 1008 return; 1009 } 1010 em_initialize_receive_unit(sc); 1011 1012 /* Don't loose promiscuous settings */ 1013 em_set_promisc(sc); 1014 1015 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1016 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1017 1018 if (sc->hw.mac_type >= em_82543) { 1019 if (ifp->if_capenable & IFCAP_TXCSUM) 1020 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1021 else 1022 ifp->if_hwassist = 0; 1023 } 1024 1025 callout_reset(&sc->timer, hz, em_local_timer, sc); 1026 em_clear_hw_cntrs(&sc->hw); 1027#ifdef DEVICE_POLLING 1028 /* 1029 * Only enable interrupts if we are not polling, make sure 1030 * they are off otherwise. 1031 */ 1032 if (ifp->if_capenable & IFCAP_POLLING) 1033 em_disable_intr(sc); 1034 else 1035#endif /* DEVICE_POLLING */ 1036 em_enable_intr(sc); 1037 1038 /* Don't reset the phy next time init gets called */ 1039 sc->hw.phy_reset_disable = TRUE; 1040} 1041 1042static void 1043em_init(void *arg) 1044{ 1045 struct em_softc *sc = arg; 1046 1047 EM_LOCK(sc); 1048 em_init_locked(sc); 1049 EM_UNLOCK(sc); 1050} 1051 1052 1053#ifdef DEVICE_POLLING 1054/********************************************************************* 1055 * 1056 * Legacy polling routine 1057 * 1058 *********************************************************************/ 1059static void 1060em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1061{ 1062 struct em_softc *sc = ifp->if_softc; 1063 uint32_t reg_icr; 1064 1065 EM_LOCK(sc); 1066 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1067 EM_UNLOCK(sc); 1068 return; 1069 } 1070 1071 if (cmd == POLL_AND_CHECK_STATUS) { 1072 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1073 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1074 callout_stop(&sc->timer); 1075 sc->hw.get_link_status = 1; 1076 em_check_for_link(&sc->hw); 1077 em_update_link_status(sc); 1078 callout_reset(&sc->timer, hz, em_local_timer, sc); 1079 } 1080 } 1081 em_rxeof(sc, count); 1082 em_txeof(sc); 1083 1084 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1085 em_start_locked(ifp); 1086 EM_UNLOCK(sc); 1087} 1088 1089/********************************************************************* 1090 * 1091 * Legacy Interrupt Service routine 1092 * 1093 *********************************************************************/ 1094static void 1095em_intr(void *arg) 1096{ 1097 struct em_softc *sc = arg; 1098 struct ifnet *ifp; 1099 uint32_t reg_icr; 1100 1101 EM_LOCK(sc); 1102 1103 ifp = sc->ifp; 1104 1105 if (ifp->if_capenable & IFCAP_POLLING) { 1106 EM_UNLOCK(sc); 1107 return; 1108 } 1109 1110 for (;;) { 1111 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1112 if (sc->hw.mac_type >= em_82571 && 1113 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1114 break; 1115 else if (reg_icr == 0) 1116 break; 1117 1118 /* 1119 * XXX: some laptops trigger several spurious interrupts 1120 * on em(4) when in the resume cycle. The ICR register 1121 * reports all-ones value in this case. Processing such 1122 * interrupts would lead to a freeze. I don't know why. 1123 */ 1124 if (reg_icr == 0xffffffff) 1125 break; 1126 1127 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1128 em_rxeof(sc, -1); 1129 em_txeof(sc); 1130 } 1131 1132 /* Link status change */ 1133 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1134 callout_stop(&sc->timer); 1135 sc->hw.get_link_status = 1; 1136 em_check_for_link(&sc->hw); 1137 em_update_link_status(sc); 1138 callout_reset(&sc->timer, hz, em_local_timer, sc); 1139 } 1140 1141 if (reg_icr & E1000_ICR_RXO) 1142 sc->rx_overruns++; 1143 } 1144 1145 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1146 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1147 em_start_locked(ifp); 1148 1149 EM_UNLOCK(sc); 1150} 1151 1152#else /* if not DEVICE_POLLING, then fast interrupt routines only */ 1153 1154static void 1155em_handle_link(void *context, int pending) 1156{ 1157 struct em_softc *sc = context; 1158 struct ifnet *ifp; 1159 1160 ifp = sc->ifp; 1161 1162 EM_LOCK(sc); 1163 1164 callout_stop(&sc->timer); 1165 sc->hw.get_link_status = 1; 1166 em_check_for_link(&sc->hw); 1167 em_update_link_status(sc); 1168 callout_reset(&sc->timer, hz, em_local_timer, sc); 1169 EM_UNLOCK(sc); 1170} 1171 1172static void 1173em_handle_rxtx(void *context, int pending) 1174{ 1175 struct em_softc *sc = context; 1176 struct ifnet *ifp; 1177 1178 NET_LOCK_GIANT(); 1179 ifp = sc->ifp; 1180 1181 /* 1182 * TODO: 1183 * It should be possible to run the tx clean loop without the lock. 1184 */ 1185 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1186 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1187 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1188 EM_LOCK(sc); 1189 em_txeof(sc); 1190 1191 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1192 em_start_locked(ifp); 1193 EM_UNLOCK(sc); 1194 } 1195 1196 em_enable_intr(sc); 1197 NET_UNLOCK_GIANT(); 1198} 1199 1200/********************************************************************* 1201 * 1202 * Fast Interrupt Service routine 1203 * 1204 *********************************************************************/ 1205static void 1206em_intr_fast(void *arg) 1207{ 1208 struct em_softc *sc = arg; 1209 struct ifnet *ifp; 1210 uint32_t reg_icr; 1211 1212 ifp = sc->ifp; 1213 1214 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1215 1216 /* Hot eject? */ 1217 if (reg_icr == 0xffffffff) 1218 return; 1219 1220 /* Definitely not our interrupt. */ 1221 if (reg_icr == 0x0) 1222 return; 1223 1224 /* 1225 * Starting with the 82571 chip, bit 31 should be used to 1226 * determine whether the interrupt belongs to us. 1227 */ 1228 if (sc->hw.mac_type >= em_82571 && 1229 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1230 return; 1231 1232 /* 1233 * Mask interrupts until the taskqueue is finished running. This is 1234 * cheap, just assume that it is needed. This also works around the 1235 * MSI message reordering errata on certain systems. 1236 */ 1237 em_disable_intr(sc); 1238 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1239 1240 /* Link status change */ 1241 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1242 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1243 1244 if (reg_icr & E1000_ICR_RXO) 1245 sc->rx_overruns++; 1246} 1247#endif /* ! DEVICE_POLLING */ 1248 1249/********************************************************************* 1250 * 1251 * Media Ioctl callback 1252 * 1253 * This routine is called whenever the user queries the status of 1254 * the interface using ifconfig. 1255 * 1256 **********************************************************************/ 1257static void 1258em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1259{ 1260 struct em_softc *sc = ifp->if_softc; 1261 1262 INIT_DEBUGOUT("em_media_status: begin"); 1263 1264 em_check_for_link(&sc->hw); 1265 em_update_link_status(sc); 1266 1267 ifmr->ifm_status = IFM_AVALID; 1268 ifmr->ifm_active = IFM_ETHER; 1269 1270 if (!sc->link_active) 1271 return; 1272 1273 ifmr->ifm_status |= IFM_ACTIVE; 1274 1275 if (sc->hw.media_type == em_media_type_fiber) { 1276 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1277 } else { 1278 switch (sc->link_speed) { 1279 case 10: 1280 ifmr->ifm_active |= IFM_10_T; 1281 break; 1282 case 100: 1283 ifmr->ifm_active |= IFM_100_TX; 1284 break; 1285 case 1000: 1286 ifmr->ifm_active |= IFM_1000_T; 1287 break; 1288 } 1289 if (sc->link_duplex == FULL_DUPLEX) 1290 ifmr->ifm_active |= IFM_FDX; 1291 else 1292 ifmr->ifm_active |= IFM_HDX; 1293 } 1294} 1295 1296/********************************************************************* 1297 * 1298 * Media Ioctl callback 1299 * 1300 * This routine is called when the user changes speed/duplex using 1301 * media/mediopt option with ifconfig. 1302 * 1303 **********************************************************************/ 1304static int 1305em_media_change(struct ifnet *ifp) 1306{ 1307 struct em_softc *sc = ifp->if_softc; 1308 struct ifmedia *ifm = &sc->media; 1309 1310 INIT_DEBUGOUT("em_media_change: begin"); 1311 1312 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1313 return (EINVAL); 1314 1315 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1316 case IFM_AUTO: 1317 sc->hw.autoneg = DO_AUTO_NEG; 1318 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1319 break; 1320 case IFM_1000_SX: 1321 case IFM_1000_T: 1322 sc->hw.autoneg = DO_AUTO_NEG; 1323 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1324 break; 1325 case IFM_100_TX: 1326 sc->hw.autoneg = FALSE; 1327 sc->hw.autoneg_advertised = 0; 1328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1329 sc->hw.forced_speed_duplex = em_100_full; 1330 else 1331 sc->hw.forced_speed_duplex = em_100_half; 1332 break; 1333 case IFM_10_T: 1334 sc->hw.autoneg = FALSE; 1335 sc->hw.autoneg_advertised = 0; 1336 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1337 sc->hw.forced_speed_duplex = em_10_full; 1338 else 1339 sc->hw.forced_speed_duplex = em_10_half; 1340 break; 1341 default: 1342 device_printf(sc->dev, "Unsupported media type\n"); 1343 } 1344 1345 /* As the speed/duplex settings my have changed we need to 1346 * reset the PHY. 1347 */ 1348 sc->hw.phy_reset_disable = FALSE; 1349 1350 em_init(sc); 1351 1352 return (0); 1353} 1354 1355/********************************************************************* 1356 * 1357 * This routine maps the mbufs to tx descriptors. 1358 * 1359 * return 0 on success, positive on failure 1360 **********************************************************************/ 1361static int 1362em_encap(struct em_softc *sc, struct mbuf **m_headp) 1363{ 1364 struct ifnet *ifp = sc->ifp; 1365 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1366 bus_dmamap_t map; 1367 struct em_buffer *tx_buffer; 1368 struct em_tx_desc *current_tx_desc; 1369 struct mbuf *m_head; 1370 struct m_tag *mtag; 1371 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1372 int nsegs, i, j; 1373 int error = 0; 1374 1375 m_head = *m_headp; 1376 current_tx_desc = NULL; 1377 txd_used = txd_saved = 0; 1378 1379 /* 1380 * Force a cleanup if number of TX descriptors 1381 * available hits the threshold. 1382 */ 1383 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1384 em_txeof(sc); 1385 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1386 sc->no_tx_desc_avail1++; 1387 return (ENOBUFS); 1388 } 1389 } 1390 1391 /* 1392 * Map the packet for DMA. 1393 */ 1394 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1395 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1396 segs, &nsegs, BUS_DMA_NOWAIT); 1397 map = tx_buffer->map; 1398 if (error != 0) { 1399 sc->no_tx_dma_setup++; 1400 return (error); 1401 } 1402 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1403 1404 if (nsegs > sc->num_tx_desc_avail) { 1405 sc->no_tx_desc_avail2++; 1406 error = ENOBUFS; 1407 goto encap_fail; 1408 } 1409 1410 if (ifp->if_hwassist > 0) 1411 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1412 else 1413 txd_upper = txd_lower = 0; 1414 1415 /* Find out if we are in vlan mode. */ 1416 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1417 1418 /* 1419 * When operating in promiscuous mode, hardware encapsulation for 1420 * packets is disabled. This means we have to add the vlan 1421 * encapsulation in the driver, since it will have come down from the 1422 * VLAN layer with a tag instead of a VLAN header. 1423 */ 1424 if (mtag != NULL && sc->em_insert_vlan_header) { 1425 struct ether_vlan_header *evl; 1426 struct ether_header eh; 1427 1428 m_head = m_pullup(m_head, sizeof(eh)); 1429 if (m_head == NULL) { 1430 *m_headp = NULL; 1431 error = ENOBUFS; 1432 goto encap_fail; 1433 } 1434 eh = *mtod(m_head, struct ether_header *); 1435 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1436 if (m_head == NULL) { 1437 *m_headp = NULL; 1438 error = ENOBUFS; 1439 goto encap_fail; 1440 } 1441 m_head = m_pullup(m_head, sizeof(*evl)); 1442 if (m_head == NULL) { 1443 *m_headp = NULL; 1444 error = ENOBUFS; 1445 goto encap_fail; 1446 } 1447 evl = mtod(m_head, struct ether_vlan_header *); 1448 bcopy(&eh, evl, sizeof(*evl)); 1449 evl->evl_proto = evl->evl_encap_proto; 1450 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1451 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1452 m_tag_delete(m_head, mtag); 1453 mtag = NULL; 1454 *m_headp = m_head; 1455 } 1456 1457 i = sc->next_avail_tx_desc; 1458 if (sc->pcix_82544) { 1459 txd_saved = i; 1460 txd_used = 0; 1461 } 1462 for (j = 0; j < nsegs; j++) { 1463 /* If adapter is 82544 and on PCIX bus. */ 1464 if(sc->pcix_82544) { 1465 DESC_ARRAY desc_array; 1466 uint32_t array_elements, counter; 1467 1468 /* 1469 * Check the Address and Length combination and 1470 * split the data accordingly 1471 */ 1472 array_elements = em_fill_descriptors(segs[j].ds_addr, 1473 segs[j].ds_len, &desc_array); 1474 for (counter = 0; counter < array_elements; counter++) { 1475 if (txd_used == sc->num_tx_desc_avail) { 1476 sc->next_avail_tx_desc = txd_saved; 1477 sc->no_tx_desc_avail2++; 1478 error = ENOBUFS; 1479 goto encap_fail; 1480 } 1481 tx_buffer = &sc->tx_buffer_area[i]; 1482 current_tx_desc = &sc->tx_desc_base[i]; 1483 current_tx_desc->buffer_addr = htole64( 1484 desc_array.descriptor[counter].address); 1485 current_tx_desc->lower.data = htole32( 1486 (sc->txd_cmd | txd_lower | 1487 (uint16_t)desc_array.descriptor[counter].length)); 1488 current_tx_desc->upper.data = htole32((txd_upper)); 1489 if (++i == sc->num_tx_desc) 1490 i = 0; 1491 1492 tx_buffer->m_head = NULL; 1493 txd_used++; 1494 } 1495 } else { 1496 tx_buffer = &sc->tx_buffer_area[i]; 1497 current_tx_desc = &sc->tx_desc_base[i]; 1498 1499 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1500 current_tx_desc->lower.data = htole32( 1501 sc->txd_cmd | txd_lower | segs[j].ds_len); 1502 current_tx_desc->upper.data = htole32(txd_upper); 1503 1504 if (++i == sc->num_tx_desc) 1505 i = 0; 1506 1507 tx_buffer->m_head = NULL; 1508 } 1509 } 1510 1511 sc->next_avail_tx_desc = i; 1512 if (sc->pcix_82544) 1513 sc->num_tx_desc_avail -= txd_used; 1514 else 1515 sc->num_tx_desc_avail -= nsegs; 1516 1517 if (mtag != NULL) { 1518 /* Set the vlan id. */ 1519 current_tx_desc->upper.fields.special = 1520 htole16(VLAN_TAG_VALUE(mtag)); 1521 1522 /* Tell hardware to add tag. */ 1523 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1524 } 1525 1526 tx_buffer->m_head = m_head; 1527 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1528 1529 /* 1530 * Last Descriptor of Packet needs End Of Packet (EOP). 1531 */ 1532 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1533 1534 /* 1535 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1536 * that this frame is available to transmit. 1537 */ 1538 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1540 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1541 em_82547_move_tail_locked(sc); 1542 else { 1543 E1000_WRITE_REG(&sc->hw, TDT, i); 1544 if (sc->hw.mac_type == em_82547) 1545 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1546 } 1547 1548 return (0); 1549 1550encap_fail: 1551 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1552 return (error); 1553} 1554 1555/********************************************************************* 1556 * 1557 * 82547 workaround to avoid controller hang in half-duplex environment. 1558 * The workaround is to avoid queuing a large packet that would span 1559 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1560 * in this case. We do that only when FIFO is quiescent. 1561 * 1562 **********************************************************************/ 1563static void 1564em_82547_move_tail_locked(struct em_softc *sc) 1565{ 1566 uint16_t hw_tdt; 1567 uint16_t sw_tdt; 1568 struct em_tx_desc *tx_desc; 1569 uint16_t length = 0; 1570 boolean_t eop = 0; 1571 1572 EM_LOCK_ASSERT(sc); 1573 1574 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1575 sw_tdt = sc->next_avail_tx_desc; 1576 1577 while (hw_tdt != sw_tdt) { 1578 tx_desc = &sc->tx_desc_base[hw_tdt]; 1579 length += tx_desc->lower.flags.length; 1580 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1581 if(++hw_tdt == sc->num_tx_desc) 1582 hw_tdt = 0; 1583 1584 if (eop) { 1585 if (em_82547_fifo_workaround(sc, length)) { 1586 sc->tx_fifo_wrk_cnt++; 1587 callout_reset(&sc->tx_fifo_timer, 1, 1588 em_82547_move_tail, sc); 1589 break; 1590 } 1591 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1592 em_82547_update_fifo_head(sc, length); 1593 length = 0; 1594 } 1595 } 1596} 1597 1598static void 1599em_82547_move_tail(void *arg) 1600{ 1601 struct em_softc *sc = arg; 1602 1603 EM_LOCK(sc); 1604 em_82547_move_tail_locked(sc); 1605 EM_UNLOCK(sc); 1606} 1607 1608static int 1609em_82547_fifo_workaround(struct em_softc *sc, int len) 1610{ 1611 int fifo_space, fifo_pkt_len; 1612 1613 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1614 1615 if (sc->link_duplex == HALF_DUPLEX) { 1616 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1617 1618 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1619 if (em_82547_tx_fifo_reset(sc)) 1620 return (0); 1621 else 1622 return (1); 1623 } 1624 } 1625 1626 return (0); 1627} 1628 1629static void 1630em_82547_update_fifo_head(struct em_softc *sc, int len) 1631{ 1632 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1633 1634 /* tx_fifo_head is always 16 byte aligned */ 1635 sc->tx_fifo_head += fifo_pkt_len; 1636 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1637 sc->tx_fifo_head -= sc->tx_fifo_size; 1638 } 1639} 1640 1641 1642static int 1643em_82547_tx_fifo_reset(struct em_softc *sc) 1644{ 1645 uint32_t tctl; 1646 1647 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1648 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1649 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1650 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1651 1652 /* Disable TX unit */ 1653 tctl = E1000_READ_REG(&sc->hw, TCTL); 1654 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1655 1656 /* Reset FIFO pointers */ 1657 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1658 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1659 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1660 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1661 1662 /* Re-enable TX unit */ 1663 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1664 E1000_WRITE_FLUSH(&sc->hw); 1665 1666 sc->tx_fifo_head = 0; 1667 sc->tx_fifo_reset_cnt++; 1668 1669 return (TRUE); 1670 } 1671 else { 1672 return (FALSE); 1673 } 1674} 1675 1676static void 1677em_set_promisc(struct em_softc *sc) 1678{ 1679 struct ifnet *ifp = sc->ifp; 1680 uint32_t reg_rctl; 1681 1682 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1683 1684 if (ifp->if_flags & IFF_PROMISC) { 1685 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1686 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1687 /* Disable VLAN stripping in promiscous mode 1688 * This enables bridging of vlan tagged frames to occur 1689 * and also allows vlan tags to be seen in tcpdump 1690 */ 1691 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1692 em_disable_vlans(sc); 1693 sc->em_insert_vlan_header = 1; 1694 } else if (ifp->if_flags & IFF_ALLMULTI) { 1695 reg_rctl |= E1000_RCTL_MPE; 1696 reg_rctl &= ~E1000_RCTL_UPE; 1697 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1698 sc->em_insert_vlan_header = 0; 1699 } else 1700 sc->em_insert_vlan_header = 0; 1701} 1702 1703static void 1704em_disable_promisc(struct em_softc *sc) 1705{ 1706 struct ifnet *ifp = sc->ifp; 1707 uint32_t reg_rctl; 1708 1709 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1710 1711 reg_rctl &= (~E1000_RCTL_UPE); 1712 reg_rctl &= (~E1000_RCTL_MPE); 1713 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1714 1715 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1716 em_enable_vlans(sc); 1717 sc->em_insert_vlan_header = 0; 1718} 1719 1720 1721/********************************************************************* 1722 * Multicast Update 1723 * 1724 * This routine is called whenever multicast address list is updated. 1725 * 1726 **********************************************************************/ 1727 1728static void 1729em_set_multi(struct em_softc *sc) 1730{ 1731 struct ifnet *ifp = sc->ifp; 1732 struct ifmultiaddr *ifma; 1733 uint32_t reg_rctl = 0; 1734 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1735 int mcnt = 0; 1736 1737 IOCTL_DEBUGOUT("em_set_multi: begin"); 1738 1739 if (sc->hw.mac_type == em_82542_rev2_0) { 1740 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1741 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1742 em_pci_clear_mwi(&sc->hw); 1743 reg_rctl |= E1000_RCTL_RST; 1744 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1745 msec_delay(5); 1746 } 1747 1748 IF_ADDR_LOCK(ifp); 1749 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1750 if (ifma->ifma_addr->sa_family != AF_LINK) 1751 continue; 1752 1753 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1754 break; 1755 1756 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1757 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1758 mcnt++; 1759 } 1760 IF_ADDR_UNLOCK(ifp); 1761 1762 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1763 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1764 reg_rctl |= E1000_RCTL_MPE; 1765 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1766 } else 1767 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1768 1769 if (sc->hw.mac_type == em_82542_rev2_0) { 1770 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1771 reg_rctl &= ~E1000_RCTL_RST; 1772 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1773 msec_delay(5); 1774 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1775 em_pci_set_mwi(&sc->hw); 1776 } 1777} 1778 1779 1780/********************************************************************* 1781 * Timer routine 1782 * 1783 * This routine checks for link status and updates statistics. 1784 * 1785 **********************************************************************/ 1786 1787static void 1788em_local_timer(void *arg) 1789{ 1790 struct em_softc *sc = arg; 1791 struct ifnet *ifp = sc->ifp; 1792 1793 EM_LOCK(sc); 1794 1795 em_check_for_link(&sc->hw); 1796 em_update_link_status(sc); 1797 em_update_stats_counters(sc); 1798 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1799 em_print_hw_stats(sc); 1800 em_smartspeed(sc); 1801 1802 callout_reset(&sc->timer, hz, em_local_timer, sc); 1803 1804 EM_UNLOCK(sc); 1805} 1806 1807static void 1808em_update_link_status(struct em_softc *sc) 1809{ 1810 struct ifnet *ifp = sc->ifp; 1811 device_t dev = sc->dev; 1812 1813 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1814 if (sc->link_active == 0) { 1815 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1816 &sc->link_duplex); 1817 if (bootverbose) 1818 device_printf(dev, "Link is up %d Mbps %s\n", 1819 sc->link_speed, 1820 ((sc->link_duplex == FULL_DUPLEX) ? 1821 "Full Duplex" : "Half Duplex")); 1822 sc->link_active = 1; 1823 sc->smartspeed = 0; 1824 ifp->if_baudrate = sc->link_speed * 1000000; 1825 if_link_state_change(ifp, LINK_STATE_UP); 1826 } 1827 } else { 1828 if (sc->link_active == 1) { 1829 ifp->if_baudrate = sc->link_speed = 0; 1830 sc->link_duplex = 0; 1831 if (bootverbose) 1832 device_printf(dev, "Link is Down\n"); 1833 sc->link_active = 0; 1834 if_link_state_change(ifp, LINK_STATE_DOWN); 1835 } 1836 } 1837} 1838 1839/********************************************************************* 1840 * 1841 * This routine disables all traffic on the adapter by issuing a 1842 * global reset on the MAC and deallocates TX/RX buffers. 1843 * 1844 **********************************************************************/ 1845 1846static void 1847em_stop(void *arg) 1848{ 1849 struct em_softc *sc = arg; 1850 struct ifnet *ifp = sc->ifp; 1851 1852 EM_LOCK_ASSERT(sc); 1853 1854 INIT_DEBUGOUT("em_stop: begin"); 1855 1856 em_disable_intr(sc); 1857 em_reset_hw(&sc->hw); 1858 callout_stop(&sc->timer); 1859 callout_stop(&sc->tx_fifo_timer); 1860 em_free_transmit_structures(sc); 1861 em_free_receive_structures(sc); 1862 1863 /* Tell the stack that the interface is no longer active */ 1864 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1865} 1866 1867 1868/********************************************************************* 1869 * 1870 * Determine hardware revision. 1871 * 1872 **********************************************************************/ 1873static void 1874em_identify_hardware(struct em_softc *sc) 1875{ 1876 device_t dev = sc->dev; 1877 1878 /* Make sure our PCI config space has the necessary stuff set */ 1879 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1880 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1881 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1882 device_printf(dev, "Memory Access and/or Bus Master bits " 1883 "were not set!\n"); 1884 sc->hw.pci_cmd_word |= 1885 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1886 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1887 } 1888 1889 /* Save off the information about this board */ 1890 sc->hw.vendor_id = pci_get_vendor(dev); 1891 sc->hw.device_id = pci_get_device(dev); 1892 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1893 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1894 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1895 1896 /* Identify the MAC */ 1897 if (em_set_mac_type(&sc->hw)) 1898 device_printf(dev, "Unknown MAC Type\n"); 1899 1900 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1901 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1902 sc->hw.phy_init_script = TRUE; 1903} 1904 1905static int 1906em_allocate_pci_resources(struct em_softc *sc) 1907{ 1908 device_t dev = sc->dev; 1909 int val, rid; 1910 1911 rid = PCIR_BAR(0); 1912 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1913 &rid, RF_ACTIVE); 1914 if (sc->res_memory == NULL) { 1915 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1916 return (ENXIO); 1917 } 1918 sc->osdep.mem_bus_space_tag = 1919 rman_get_bustag(sc->res_memory); 1920 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1921 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1922 1923 if (sc->hw.mac_type > em_82543) { 1924 /* Figure our where our IO BAR is ? */ 1925 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1926 val = pci_read_config(dev, rid, 4); 1927 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1928 sc->io_rid = rid; 1929 break; 1930 } 1931 rid += 4; 1932 /* check for 64bit BAR */ 1933 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1934 rid += 4; 1935 } 1936 if (rid >= PCIR_CIS) { 1937 device_printf(dev, "Unable to locate IO BAR\n"); 1938 return (ENXIO); 1939 } 1940 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1941 &sc->io_rid, RF_ACTIVE); 1942 if (sc->res_ioport == NULL) { 1943 device_printf(dev, "Unable to allocate bus resource: " 1944 "ioport\n"); 1945 return (ENXIO); 1946 } 1947 sc->hw.io_base = 0; 1948 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1949 sc->osdep.io_bus_space_handle = 1950 rman_get_bushandle(sc->res_ioport); 1951 } 1952 1953 rid = 0x0; 1954 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1955 RF_SHAREABLE | RF_ACTIVE); 1956 if (sc->res_interrupt == NULL) { 1957 device_printf(dev, "Unable to allocate bus resource: " 1958 "interrupt\n"); 1959 return (ENXIO); 1960 } 1961 1962 sc->hw.back = &sc->osdep; 1963 1964 return (0); 1965} 1966 1967int 1968em_allocate_intr(struct em_softc *sc) 1969{ 1970 device_t dev = sc->dev; 1971 int error; 1972 1973 /* Manually turn off all interrupts */ 1974 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1975 1976#ifdef DEVICE_POLLING 1977 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 1978 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 1979 &sc->int_handler_tag)) != 0) { 1980 device_printf(dev, "Failed to register interrupt handler"); 1981 return (error); 1982 } 1983#else 1984 /* 1985 * Try allocating a fast interrupt and the associated deferred 1986 * processing contexts. 1987 */ 1988 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1989 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1990 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1991 taskqueue_thread_enqueue, &sc->tq); 1992 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1993 device_get_nameunit(sc->dev)); 1994 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1995 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 1996 &sc->int_handler_tag)) != 0) { 1997 device_printf(dev, "Failed to register fast interrupt " 1998 "handler: %d\n", error); 1999 taskqueue_free(sc->tq); 2000 sc->tq = NULL; 2001 return (error); 2002 } 2003#endif 2004 2005 em_enable_intr(sc); 2006 return (0); 2007} 2008 2009static void 2010em_free_intr(struct em_softc *sc) 2011{ 2012 device_t dev = sc->dev; 2013 2014 if (sc->res_interrupt != NULL) { 2015 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2016 sc->int_handler_tag = NULL; 2017 } 2018 if (sc->tq != NULL) { 2019 taskqueue_drain(sc->tq, &sc->rxtx_task); 2020 taskqueue_drain(taskqueue_fast, &sc->link_task); 2021 taskqueue_free(sc->tq); 2022 sc->tq = NULL; 2023 } 2024} 2025 2026static void 2027em_free_pci_resources(struct em_softc *sc) 2028{ 2029 device_t dev = sc->dev; 2030 2031 if (sc->res_interrupt != NULL) 2032 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2033 2034 if (sc->res_memory != NULL) 2035 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2036 sc->res_memory); 2037 2038 if (sc->res_ioport != NULL) 2039 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2040 sc->res_ioport); 2041} 2042 2043/********************************************************************* 2044 * 2045 * Initialize the hardware to a configuration as specified by the 2046 * adapter structure. The controller is reset, the EEPROM is 2047 * verified, the MAC address is set, then the shared initialization 2048 * routines are called. 2049 * 2050 **********************************************************************/ 2051static int 2052em_hardware_init(struct em_softc *sc) 2053{ 2054 device_t dev = sc->dev; 2055 uint16_t rx_buffer_size; 2056 2057 INIT_DEBUGOUT("em_hardware_init: begin"); 2058 /* Issue a global reset */ 2059 em_reset_hw(&sc->hw); 2060 2061 /* When hardware is reset, fifo_head is also reset */ 2062 sc->tx_fifo_head = 0; 2063 2064 /* Make sure we have a good EEPROM before we read from it */ 2065 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2066 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2067 return (EIO); 2068 } 2069 2070 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2071 device_printf(dev, "EEPROM read error while reading part " 2072 "number\n"); 2073 return (EIO); 2074 } 2075 2076 /* 2077 * These parameters control the automatic generation (Tx) and 2078 * response (Rx) to Ethernet PAUSE frames. 2079 * - High water mark should allow for at least two frames to be 2080 * received after sending an XOFF. 2081 * - Low water mark works best when it is very near the high water mark. 2082 * This allows the receiver to restart by sending XON when it has 2083 * drained a bit. Here we use an arbitary value of 1500 which will 2084 * restart after one full frame is pulled from the buffer. There 2085 * could be several smaller frames in the buffer and if so they will 2086 * not trigger the XON until their total number reduces the buffer 2087 * by 1500. 2088 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2089 */ 2090 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2091 2092 sc->hw.fc_high_water = rx_buffer_size - 2093 roundup2(sc->hw.max_frame_size, 1024); 2094 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2095 if (sc->hw.mac_type == em_80003es2lan) 2096 sc->hw.fc_pause_time = 0xFFFF; 2097 else 2098 sc->hw.fc_pause_time = 0x1000; 2099 sc->hw.fc_send_xon = TRUE; 2100 sc->hw.fc = em_fc_full; 2101 2102 if (em_init_hw(&sc->hw) < 0) { 2103 device_printf(dev, "Hardware Initialization Failed"); 2104 return (EIO); 2105 } 2106 2107 em_check_for_link(&sc->hw); 2108 2109 return (0); 2110} 2111 2112/********************************************************************* 2113 * 2114 * Setup networking device structure and register an interface. 2115 * 2116 **********************************************************************/ 2117static void 2118em_setup_interface(device_t dev, struct em_softc *sc) 2119{ 2120 struct ifnet *ifp; 2121 INIT_DEBUGOUT("em_setup_interface: begin"); 2122 2123 ifp = sc->ifp = if_alloc(IFT_ETHER); 2124 if (ifp == NULL) 2125 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2126 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2127 ifp->if_mtu = ETHERMTU; 2128 ifp->if_init = em_init; 2129 ifp->if_softc = sc; 2130 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2131 ifp->if_ioctl = em_ioctl; 2132 ifp->if_start = em_start; 2133 ifp->if_watchdog = em_watchdog; 2134 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2135 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2136 IFQ_SET_READY(&ifp->if_snd); 2137 2138 ether_ifattach(ifp, sc->hw.mac_addr); 2139 2140 ifp->if_capabilities = ifp->if_capenable = 0; 2141 2142 if (sc->hw.mac_type >= em_82543) { 2143 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2144 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2145 } 2146 2147 /* 2148 * Tell the upper layer(s) we support long frames. 2149 */ 2150 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2151 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2152 ifp->if_capenable |= IFCAP_VLAN_MTU; 2153 2154#ifdef DEVICE_POLLING 2155 ifp->if_capabilities |= IFCAP_POLLING; 2156#endif 2157 2158 /* 2159 * Specify the media types supported by this adapter and register 2160 * callbacks to update media and link information 2161 */ 2162 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2163 if (sc->hw.media_type == em_media_type_fiber) { 2164 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2165 0, NULL); 2166 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2167 0, NULL); 2168 } else { 2169 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2170 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2171 0, NULL); 2172 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2173 0, NULL); 2174 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2175 0, NULL); 2176 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2177 0, NULL); 2178 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2179 } 2180 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2181 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2182} 2183 2184 2185/********************************************************************* 2186 * 2187 * Workaround for SmartSpeed on 82541 and 82547 controllers 2188 * 2189 **********************************************************************/ 2190static void 2191em_smartspeed(struct em_softc *sc) 2192{ 2193 uint16_t phy_tmp; 2194 2195 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2196 sc->hw.autoneg == 0 || 2197 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2198 return; 2199 2200 if (sc->smartspeed == 0) { 2201 /* If Master/Slave config fault is asserted twice, 2202 * we assume back-to-back */ 2203 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2204 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2205 return; 2206 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2207 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2208 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2209 if(phy_tmp & CR_1000T_MS_ENABLE) { 2210 phy_tmp &= ~CR_1000T_MS_ENABLE; 2211 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2212 phy_tmp); 2213 sc->smartspeed++; 2214 if(sc->hw.autoneg && 2215 !em_phy_setup_autoneg(&sc->hw) && 2216 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2217 &phy_tmp)) { 2218 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2219 MII_CR_RESTART_AUTO_NEG); 2220 em_write_phy_reg(&sc->hw, PHY_CTRL, 2221 phy_tmp); 2222 } 2223 } 2224 } 2225 return; 2226 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2227 /* If still no link, perhaps using 2/3 pair cable */ 2228 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2229 phy_tmp |= CR_1000T_MS_ENABLE; 2230 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2231 if(sc->hw.autoneg && 2232 !em_phy_setup_autoneg(&sc->hw) && 2233 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2234 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2235 MII_CR_RESTART_AUTO_NEG); 2236 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2237 } 2238 } 2239 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2240 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2241 sc->smartspeed = 0; 2242} 2243 2244 2245/* 2246 * Manage DMA'able memory. 2247 */ 2248static void 2249em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2250{ 2251 if (error) 2252 return; 2253 *(bus_addr_t *) arg = segs[0].ds_addr; 2254} 2255 2256static int 2257em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2258 int mapflags) 2259{ 2260 int error; 2261 2262 error = bus_dma_tag_create(NULL, /* parent */ 2263 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2264 BUS_SPACE_MAXADDR, /* lowaddr */ 2265 BUS_SPACE_MAXADDR, /* highaddr */ 2266 NULL, NULL, /* filter, filterarg */ 2267 size, /* maxsize */ 2268 1, /* nsegments */ 2269 size, /* maxsegsize */ 2270 0, /* flags */ 2271 NULL, /* lockfunc */ 2272 NULL, /* lockarg */ 2273 &dma->dma_tag); 2274 if (error) { 2275 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2276 __func__, error); 2277 goto fail_0; 2278 } 2279 2280 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2281 BUS_DMA_NOWAIT, &dma->dma_map); 2282 if (error) { 2283 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2284 __func__, (uintmax_t)size, error); 2285 goto fail_2; 2286 } 2287 2288 dma->dma_paddr = 0; 2289 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2290 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2291 if (error || dma->dma_paddr == 0) { 2292 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2293 __func__, error); 2294 goto fail_3; 2295 } 2296 2297 return (0); 2298 2299fail_3: 2300 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2301fail_2: 2302 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2303 bus_dma_tag_destroy(dma->dma_tag); 2304fail_0: 2305 dma->dma_map = NULL; 2306 dma->dma_tag = NULL; 2307 2308 return (error); 2309} 2310 2311static void 2312em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2313{ 2314 if (dma->dma_tag == NULL) 2315 return; 2316 if (dma->dma_map != NULL) { 2317 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2318 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2319 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2320 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2321 dma->dma_map = NULL; 2322 } 2323 bus_dma_tag_destroy(dma->dma_tag); 2324 dma->dma_tag = NULL; 2325} 2326 2327 2328/********************************************************************* 2329 * 2330 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2331 * the information needed to transmit a packet on the wire. 2332 * 2333 **********************************************************************/ 2334static int 2335em_allocate_transmit_structures(struct em_softc *sc) 2336{ 2337 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2338 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2339 if (sc->tx_buffer_area == NULL) { 2340 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2341 return (ENOMEM); 2342 } 2343 2344 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2345 2346 return (0); 2347} 2348 2349/********************************************************************* 2350 * 2351 * Allocate and initialize transmit structures. 2352 * 2353 **********************************************************************/ 2354static int 2355em_setup_transmit_structures(struct em_softc *sc) 2356{ 2357 device_t dev = sc->dev; 2358 struct em_buffer *tx_buffer; 2359 bus_size_t size; 2360 int error, i; 2361 2362 /* 2363 * Setup DMA descriptor areas. 2364 */ 2365 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2366 if ((error = bus_dma_tag_create(NULL, /* parent */ 2367 1, 0, /* alignment, bounds */ 2368 BUS_SPACE_MAXADDR, /* lowaddr */ 2369 BUS_SPACE_MAXADDR, /* highaddr */ 2370 NULL, NULL, /* filter, filterarg */ 2371 size, /* maxsize */ 2372 EM_MAX_SCATTER, /* nsegments */ 2373 size, /* maxsegsize */ 2374 0, /* flags */ 2375 NULL, /* lockfunc */ 2376 NULL, /* lockarg */ 2377 &sc->txtag)) != 0) { 2378 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2379 goto fail; 2380 } 2381 2382 if ((error = em_allocate_transmit_structures(sc)) != 0) 2383 goto fail; 2384 2385 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2386 tx_buffer = sc->tx_buffer_area; 2387 for (i = 0; i < sc->num_tx_desc; i++) { 2388 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2389 if (error != 0) { 2390 device_printf(dev, "Unable to create TX DMA map\n"); 2391 goto fail; 2392 } 2393 tx_buffer++; 2394 } 2395 2396 sc->next_avail_tx_desc = 0; 2397 sc->oldest_used_tx_desc = 0; 2398 2399 /* Set number of descriptors available */ 2400 sc->num_tx_desc_avail = sc->num_tx_desc; 2401 2402 /* Set checksum context */ 2403 sc->active_checksum_context = OFFLOAD_NONE; 2404 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2405 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2406 2407 return (0); 2408 2409fail: 2410 em_free_transmit_structures(sc); 2411 return (error); 2412} 2413 2414/********************************************************************* 2415 * 2416 * Enable transmit unit. 2417 * 2418 **********************************************************************/ 2419static void 2420em_initialize_transmit_unit(struct em_softc *sc) 2421{ 2422 uint32_t reg_tctl, tarc; 2423 uint32_t reg_tipg = 0; 2424 uint64_t bus_addr; 2425 2426 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2427 /* Setup the Base and Length of the Tx Descriptor Ring */ 2428 bus_addr = sc->txdma.dma_paddr; 2429 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2430 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2431 E1000_WRITE_REG(&sc->hw, TDLEN, 2432 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2433 2434 /* Setup the HW Tx Head and Tail descriptor pointers */ 2435 E1000_WRITE_REG(&sc->hw, TDH, 0); 2436 E1000_WRITE_REG(&sc->hw, TDT, 0); 2437 2438 2439 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2440 E1000_READ_REG(&sc->hw, TDLEN)); 2441 2442 /* Set the default values for the Tx Inter Packet Gap timer */ 2443 switch (sc->hw.mac_type) { 2444 case em_82542_rev2_0: 2445 case em_82542_rev2_1: 2446 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2447 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2448 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2449 break; 2450 case em_80003es2lan: 2451 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2452 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2453 E1000_TIPG_IPGR2_SHIFT; 2454 break; 2455 default: 2456 if (sc->hw.media_type == em_media_type_fiber) 2457 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2458 else 2459 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2460 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2461 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2462 } 2463 2464 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2465 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2466 if(sc->hw.mac_type >= em_82540) 2467 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2468 2469 /* Program the Transmit Control Register */ 2470 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2471 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2472 if (sc->hw.mac_type >= em_82571) 2473 reg_tctl |= E1000_TCTL_MULR; 2474 if (sc->link_duplex == 1) { 2475 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2476 } else { 2477 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2478 } 2479 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2480 2481 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) { 2482 tarc = E1000_READ_REG(&sc->hw, TARC0); 2483 tarc |= ((1 << 25) | (1 << 21)); 2484 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2485 tarc = E1000_READ_REG(&sc->hw, TARC1); 2486 tarc |= (1 << 25); 2487 if (reg_tctl & E1000_TCTL_MULR) 2488 tarc &= ~(1 << 28); 2489 else 2490 tarc |= (1 << 28); 2491 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2492 } else if (sc->hw.mac_type == em_80003es2lan) { 2493 tarc = E1000_READ_REG(&sc->hw, TARC0); 2494 tarc |= 1; 2495 if (sc->hw.media_type == em_media_type_internal_serdes) 2496 tarc |= (1 << 20); 2497 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2498 tarc = E1000_READ_REG(&sc->hw, TARC1); 2499 tarc |= 1; 2500 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2501 } 2502 2503 /* Setup Transmit Descriptor Settings for this adapter */ 2504 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2505 2506 if (sc->tx_int_delay.value > 0) 2507 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2508} 2509 2510/********************************************************************* 2511 * 2512 * Free all transmit related data structures. 2513 * 2514 **********************************************************************/ 2515static void 2516em_free_transmit_structures(struct em_softc *sc) 2517{ 2518 struct em_buffer *tx_buffer; 2519 int i; 2520 2521 INIT_DEBUGOUT("free_transmit_structures: begin"); 2522 2523 if (sc->tx_buffer_area != NULL) { 2524 tx_buffer = sc->tx_buffer_area; 2525 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2526 if (tx_buffer->m_head != NULL) { 2527 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2528 BUS_DMASYNC_POSTWRITE); 2529 bus_dmamap_unload(sc->txtag, 2530 tx_buffer->map); 2531 m_freem(tx_buffer->m_head); 2532 tx_buffer->m_head = NULL; 2533 } else if (tx_buffer->map != NULL) 2534 bus_dmamap_unload(sc->txtag, 2535 tx_buffer->map); 2536 if (tx_buffer->map != NULL) { 2537 bus_dmamap_destroy(sc->txtag, 2538 tx_buffer->map); 2539 tx_buffer->map = NULL; 2540 } 2541 } 2542 } 2543 if (sc->tx_buffer_area != NULL) { 2544 free(sc->tx_buffer_area, M_DEVBUF); 2545 sc->tx_buffer_area = NULL; 2546 } 2547 if (sc->txtag != NULL) { 2548 bus_dma_tag_destroy(sc->txtag); 2549 sc->txtag = NULL; 2550 } 2551} 2552 2553/********************************************************************* 2554 * 2555 * The offload context needs to be set when we transfer the first 2556 * packet of a particular protocol (TCP/UDP). We change the 2557 * context only if the protocol type changes. 2558 * 2559 **********************************************************************/ 2560static void 2561em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2562 uint32_t *txd_upper, uint32_t *txd_lower) 2563{ 2564 struct em_context_desc *TXD; 2565 struct em_buffer *tx_buffer; 2566 int curr_txd; 2567 2568 if (mp->m_pkthdr.csum_flags) { 2569 2570 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2571 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2572 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2573 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2574 return; 2575 else 2576 sc->active_checksum_context = OFFLOAD_TCP_IP; 2577 2578 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2579 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2580 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2581 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2582 return; 2583 else 2584 sc->active_checksum_context = OFFLOAD_UDP_IP; 2585 } else { 2586 *txd_upper = 0; 2587 *txd_lower = 0; 2588 return; 2589 } 2590 } else { 2591 *txd_upper = 0; 2592 *txd_lower = 0; 2593 return; 2594 } 2595 2596 /* If we reach this point, the checksum offload context 2597 * needs to be reset. 2598 */ 2599 curr_txd = sc->next_avail_tx_desc; 2600 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2601 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2602 2603 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2604 TXD->lower_setup.ip_fields.ipcso = 2605 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2606 TXD->lower_setup.ip_fields.ipcse = 2607 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2608 2609 TXD->upper_setup.tcp_fields.tucss = 2610 ETHER_HDR_LEN + sizeof(struct ip); 2611 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2612 2613 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2614 TXD->upper_setup.tcp_fields.tucso = 2615 ETHER_HDR_LEN + sizeof(struct ip) + 2616 offsetof(struct tcphdr, th_sum); 2617 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2618 TXD->upper_setup.tcp_fields.tucso = 2619 ETHER_HDR_LEN + sizeof(struct ip) + 2620 offsetof(struct udphdr, uh_sum); 2621 } 2622 2623 TXD->tcp_seg_setup.data = htole32(0); 2624 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2625 2626 tx_buffer->m_head = NULL; 2627 2628 if (++curr_txd == sc->num_tx_desc) 2629 curr_txd = 0; 2630 2631 sc->num_tx_desc_avail--; 2632 sc->next_avail_tx_desc = curr_txd; 2633} 2634 2635/********************************************************************** 2636 * 2637 * Examine each tx_buffer in the used queue. If the hardware is done 2638 * processing the packet then free associated resources. The 2639 * tx_buffer is put back on the free queue. 2640 * 2641 **********************************************************************/ 2642static void 2643em_txeof(struct em_softc *sc) 2644{ 2645 int i, num_avail; 2646 struct em_buffer *tx_buffer; 2647 struct em_tx_desc *tx_desc; 2648 struct ifnet *ifp = sc->ifp; 2649 2650 EM_LOCK_ASSERT(sc); 2651 2652 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2653 return; 2654 2655 num_avail = sc->num_tx_desc_avail; 2656 i = sc->oldest_used_tx_desc; 2657 2658 tx_buffer = &sc->tx_buffer_area[i]; 2659 tx_desc = &sc->tx_desc_base[i]; 2660 2661 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2662 BUS_DMASYNC_POSTREAD); 2663 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2664 2665 tx_desc->upper.data = 0; 2666 num_avail++; 2667 2668 if (tx_buffer->m_head) { 2669 ifp->if_opackets++; 2670 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2671 BUS_DMASYNC_POSTWRITE); 2672 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2673 2674 m_freem(tx_buffer->m_head); 2675 tx_buffer->m_head = NULL; 2676 } 2677 2678 if (++i == sc->num_tx_desc) 2679 i = 0; 2680 2681 tx_buffer = &sc->tx_buffer_area[i]; 2682 tx_desc = &sc->tx_desc_base[i]; 2683 } 2684 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2686 2687 sc->oldest_used_tx_desc = i; 2688 2689 /* 2690 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2691 * that it is OK to send packets. 2692 * If there are no pending descriptors, clear the timeout. Otherwise, 2693 * if some descriptors have been freed, restart the timeout. 2694 */ 2695 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2696 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2697 if (num_avail == sc->num_tx_desc) 2698 ifp->if_timer = 0; 2699 else if (num_avail != sc->num_tx_desc_avail) 2700 ifp->if_timer = EM_TX_TIMEOUT; 2701 } 2702 sc->num_tx_desc_avail = num_avail; 2703} 2704 2705/********************************************************************* 2706 * 2707 * Get a buffer from system mbuf buffer pool. 2708 * 2709 **********************************************************************/ 2710static int 2711em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2712{ 2713 struct ifnet *ifp = sc->ifp; 2714 bus_dma_segment_t segs[1]; 2715 struct em_buffer *rx_buffer; 2716 int error, nsegs; 2717 2718 if (mp == NULL) { 2719 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2720 if (mp == NULL) { 2721 sc->mbuf_cluster_failed++; 2722 return (ENOBUFS); 2723 } 2724 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2725 } else { 2726 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2727 mp->m_data = mp->m_ext.ext_buf; 2728 mp->m_next = NULL; 2729 } 2730 2731 if (ifp->if_mtu <= ETHERMTU) 2732 m_adj(mp, ETHER_ALIGN); 2733 2734 rx_buffer = &sc->rx_buffer_area[i]; 2735 2736 /* 2737 * Using memory from the mbuf cluster pool, invoke the 2738 * bus_dma machinery to arrange the memory mapping. 2739 */ 2740 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2741 mp, segs, &nsegs, 0); 2742 if (error != 0) { 2743 m_free(mp); 2744 return (error); 2745 } 2746 /* If nsegs is wrong then the stack is corrupt. */ 2747 KASSERT(nsegs == 1, ("Too many segments returned!")); 2748 rx_buffer->m_head = mp; 2749 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2750 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2751 2752 return (0); 2753} 2754 2755/********************************************************************* 2756 * 2757 * Allocate memory for rx_buffer structures. Since we use one 2758 * rx_buffer per received packet, the maximum number of rx_buffer's 2759 * that we'll need is equal to the number of receive descriptors 2760 * that we've allocated. 2761 * 2762 **********************************************************************/ 2763static int 2764em_allocate_receive_structures(struct em_softc *sc) 2765{ 2766 device_t dev = sc->dev; 2767 struct em_buffer *rx_buffer; 2768 int i, error; 2769 2770 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2771 M_DEVBUF, M_NOWAIT); 2772 if (sc->rx_buffer_area == NULL) { 2773 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2774 return (ENOMEM); 2775 } 2776 2777 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2778 2779 error = bus_dma_tag_create(NULL, /* parent */ 2780 1, 0, /* alignment, bounds */ 2781 BUS_SPACE_MAXADDR, /* lowaddr */ 2782 BUS_SPACE_MAXADDR, /* highaddr */ 2783 NULL, NULL, /* filter, filterarg */ 2784 MCLBYTES, /* maxsize */ 2785 1, /* nsegments */ 2786 MCLBYTES, /* maxsegsize */ 2787 BUS_DMA_ALLOCNOW, /* flags */ 2788 NULL, /* lockfunc */ 2789 NULL, /* lockarg */ 2790 &sc->rxtag); 2791 if (error) { 2792 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2793 __func__, error); 2794 goto fail; 2795 } 2796 2797 rx_buffer = sc->rx_buffer_area; 2798 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2799 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2800 &rx_buffer->map); 2801 if (error) { 2802 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2803 __func__, error); 2804 goto fail; 2805 } 2806 } 2807 2808 for (i = 0; i < sc->num_rx_desc; i++) { 2809 error = em_get_buf(i, sc, NULL); 2810 if (error) 2811 goto fail; 2812 } 2813 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2815 2816 return (0); 2817 2818fail: 2819 em_free_receive_structures(sc); 2820 return (error); 2821} 2822 2823/********************************************************************* 2824 * 2825 * Allocate and initialize receive structures. 2826 * 2827 **********************************************************************/ 2828static int 2829em_setup_receive_structures(struct em_softc *sc) 2830{ 2831 int error; 2832 2833 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2834 2835 if ((error = em_allocate_receive_structures(sc)) != 0) 2836 return (error); 2837 2838 /* Setup our descriptor pointers */ 2839 sc->next_rx_desc_to_check = 0; 2840 2841 return (0); 2842} 2843 2844/********************************************************************* 2845 * 2846 * Enable receive unit. 2847 * 2848 **********************************************************************/ 2849static void 2850em_initialize_receive_unit(struct em_softc *sc) 2851{ 2852 struct ifnet *ifp = sc->ifp; 2853 uint64_t bus_addr; 2854 uint32_t reg_rctl; 2855 uint32_t reg_rxcsum; 2856 2857 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2858 2859 /* 2860 * Make sure receives are disabled while setting 2861 * up the descriptor ring 2862 */ 2863 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2864 2865 /* Set the Receive Delay Timer Register */ 2866 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2867 2868 if(sc->hw.mac_type >= em_82540) { 2869 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2870 2871 /* 2872 * Set the interrupt throttling rate. Value is calculated 2873 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2874 */ 2875#define MAX_INTS_PER_SEC 8000 2876#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2877 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2878 } 2879 2880 /* Setup the Base and Length of the Rx Descriptor Ring */ 2881 bus_addr = sc->rxdma.dma_paddr; 2882 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2883 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2884 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2885 sizeof(struct em_rx_desc)); 2886 2887 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2888 E1000_WRITE_REG(&sc->hw, RDH, 0); 2889 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2890 2891 /* Setup the Receive Control Register */ 2892 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2893 E1000_RCTL_RDMTS_HALF | 2894 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2895 2896 if (sc->hw.tbi_compatibility_on == TRUE) 2897 reg_rctl |= E1000_RCTL_SBP; 2898 2899 2900 switch (sc->rx_buffer_len) { 2901 default: 2902 case EM_RXBUFFER_2048: 2903 reg_rctl |= E1000_RCTL_SZ_2048; 2904 break; 2905 case EM_RXBUFFER_4096: 2906 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2907 break; 2908 case EM_RXBUFFER_8192: 2909 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2910 break; 2911 case EM_RXBUFFER_16384: 2912 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2913 break; 2914 } 2915 2916 if (ifp->if_mtu > ETHERMTU) 2917 reg_rctl |= E1000_RCTL_LPE; 2918 2919 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2920 if ((sc->hw.mac_type >= em_82543) && 2921 (ifp->if_capenable & IFCAP_RXCSUM)) { 2922 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2923 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2924 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2925 } 2926 2927 /* Enable Receives */ 2928 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2929} 2930 2931/********************************************************************* 2932 * 2933 * Free receive related data structures. 2934 * 2935 **********************************************************************/ 2936static void 2937em_free_receive_structures(struct em_softc *sc) 2938{ 2939 struct em_buffer *rx_buffer; 2940 int i; 2941 2942 INIT_DEBUGOUT("free_receive_structures: begin"); 2943 2944 if (sc->rx_buffer_area != NULL) { 2945 rx_buffer = sc->rx_buffer_area; 2946 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2947 if (rx_buffer->m_head != NULL) { 2948 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2949 BUS_DMASYNC_POSTREAD); 2950 bus_dmamap_unload(sc->rxtag, 2951 rx_buffer->map); 2952 m_freem(rx_buffer->m_head); 2953 rx_buffer->m_head = NULL; 2954 } else if (rx_buffer->map != NULL) 2955 bus_dmamap_unload(sc->rxtag, 2956 rx_buffer->map); 2957 if (rx_buffer->map != NULL) { 2958 bus_dmamap_destroy(sc->rxtag, 2959 rx_buffer->map); 2960 rx_buffer->map = NULL; 2961 } 2962 } 2963 } 2964 if (sc->rx_buffer_area != NULL) { 2965 free(sc->rx_buffer_area, M_DEVBUF); 2966 sc->rx_buffer_area = NULL; 2967 } 2968 if (sc->rxtag != NULL) { 2969 bus_dma_tag_destroy(sc->rxtag); 2970 sc->rxtag = NULL; 2971 } 2972} 2973 2974/********************************************************************* 2975 * 2976 * This routine executes in interrupt context. It replenishes 2977 * the mbufs in the descriptor and sends data which has been 2978 * dma'ed into host memory to upper layer. 2979 * 2980 * We loop at most count times if count is > 0, or until done if 2981 * count < 0. 2982 * 2983 *********************************************************************/ 2984static int 2985em_rxeof(struct em_softc *sc, int count) 2986{ 2987 struct ifnet *ifp; 2988 struct mbuf *mp; 2989 uint8_t accept_frame = 0; 2990 uint8_t eop = 0; 2991 uint16_t len, desc_len, prev_len_adj; 2992 int i; 2993 2994 /* Pointer to the receive descriptor being examined. */ 2995 struct em_rx_desc *current_desc; 2996 2997 ifp = sc->ifp; 2998 i = sc->next_rx_desc_to_check; 2999 current_desc = &sc->rx_desc_base[i]; 3000 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3001 BUS_DMASYNC_POSTREAD); 3002 3003 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3004 return (0); 3005 3006 while ((current_desc->status & E1000_RXD_STAT_DD) && 3007 (count != 0) && 3008 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3009 struct mbuf *m = NULL; 3010 3011 mp = sc->rx_buffer_area[i].m_head; 3012 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3013 BUS_DMASYNC_POSTREAD); 3014 bus_dmamap_unload(sc->rxtag, 3015 sc->rx_buffer_area[i].map); 3016 3017 accept_frame = 1; 3018 prev_len_adj = 0; 3019 desc_len = le16toh(current_desc->length); 3020 if (current_desc->status & E1000_RXD_STAT_EOP) { 3021 count--; 3022 eop = 1; 3023 if (desc_len < ETHER_CRC_LEN) { 3024 len = 0; 3025 prev_len_adj = ETHER_CRC_LEN - desc_len; 3026 } else 3027 len = desc_len - ETHER_CRC_LEN; 3028 } else { 3029 eop = 0; 3030 len = desc_len; 3031 } 3032 3033 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3034 uint8_t last_byte; 3035 uint32_t pkt_len = desc_len; 3036 3037 if (sc->fmp != NULL) 3038 pkt_len += sc->fmp->m_pkthdr.len; 3039 3040 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3041 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3042 current_desc->errors, 3043 pkt_len, last_byte)) { 3044 em_tbi_adjust_stats(&sc->hw, 3045 &sc->stats, pkt_len, 3046 sc->hw.mac_addr); 3047 if (len > 0) 3048 len--; 3049 } else 3050 accept_frame = 0; 3051 } 3052 3053 if (accept_frame) { 3054 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3055 sc->dropped_pkts++; 3056 em_get_buf(i, sc, mp); 3057 if (sc->fmp != NULL) 3058 m_freem(sc->fmp); 3059 sc->fmp = NULL; 3060 sc->lmp = NULL; 3061 break; 3062 } 3063 3064 /* Assign correct length to the current fragment */ 3065 mp->m_len = len; 3066 3067 if (sc->fmp == NULL) { 3068 mp->m_pkthdr.len = len; 3069 sc->fmp = mp; /* Store the first mbuf */ 3070 sc->lmp = mp; 3071 } else { 3072 /* Chain mbuf's together */ 3073 mp->m_flags &= ~M_PKTHDR; 3074 /* 3075 * Adjust length of previous mbuf in chain if 3076 * we received less than 4 bytes in the last 3077 * descriptor. 3078 */ 3079 if (prev_len_adj > 0) { 3080 sc->lmp->m_len -= prev_len_adj; 3081 sc->fmp->m_pkthdr.len -= 3082 prev_len_adj; 3083 } 3084 sc->lmp->m_next = mp; 3085 sc->lmp = sc->lmp->m_next; 3086 sc->fmp->m_pkthdr.len += len; 3087 } 3088 3089 if (eop) { 3090 sc->fmp->m_pkthdr.rcvif = ifp; 3091 ifp->if_ipackets++; 3092 em_receive_checksum(sc, current_desc, 3093 sc->fmp); 3094#ifndef __NO_STRICT_ALIGNMENT 3095 if (ifp->if_mtu > ETHERMTU && 3096 em_fixup_rx(sc) != 0) 3097 goto skip; 3098#endif 3099 if (current_desc->status & E1000_RXD_STAT_VP) 3100 VLAN_INPUT_TAG(ifp, sc->fmp, 3101 (le16toh(current_desc->special) & 3102 E1000_RXD_SPC_VLAN_MASK)); 3103#ifndef __NO_STRICT_ALIGNMENT 3104skip: 3105#endif 3106 m = sc->fmp; 3107 sc->fmp = NULL; 3108 sc->lmp = NULL; 3109 } 3110 } else { 3111 sc->dropped_pkts++; 3112 em_get_buf(i, sc, mp); 3113 if (sc->fmp != NULL) 3114 m_freem(sc->fmp); 3115 sc->fmp = NULL; 3116 sc->lmp = NULL; 3117 } 3118 3119 /* Zero out the receive descriptors status. */ 3120 current_desc->status = 0; 3121 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3122 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3123 3124 /* Advance our pointers to the next descriptor. */ 3125 if (++i == sc->num_rx_desc) 3126 i = 0; 3127 if (m != NULL) { 3128 sc->next_rx_desc_to_check = i; 3129#ifdef DEVICE_POLLING 3130 EM_UNLOCK(sc); 3131 (*ifp->if_input)(ifp, m); 3132 EM_LOCK(sc); 3133#else 3134 (*ifp->if_input)(ifp, m); 3135#endif 3136 i = sc->next_rx_desc_to_check; 3137 } 3138 current_desc = &sc->rx_desc_base[i]; 3139 } 3140 sc->next_rx_desc_to_check = i; 3141 3142 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3143 if (--i < 0) 3144 i = sc->num_rx_desc - 1; 3145 E1000_WRITE_REG(&sc->hw, RDT, i); 3146 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3147 return (0); 3148 3149 return (1); 3150} 3151 3152#ifndef __NO_STRICT_ALIGNMENT 3153/* 3154 * When jumbo frames are enabled we should realign entire payload on 3155 * architecures with strict alignment. This is serious design mistake of 8254x 3156 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3157 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3158 * payload. On architecures without strict alignment restrictions 8254x still 3159 * performs unaligned memory access which would reduce the performance too. 3160 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3161 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3162 * existing mbuf chain. 3163 * 3164 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3165 * not used at all on architectures with strict alignment. 3166 */ 3167static int 3168em_fixup_rx(struct em_softc *sc) 3169{ 3170 struct mbuf *m, *n; 3171 int error; 3172 3173 error = 0; 3174 m = sc->fmp; 3175 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3176 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3177 m->m_data += ETHER_HDR_LEN; 3178 } else { 3179 MGETHDR(n, M_DONTWAIT, MT_DATA); 3180 if (n != NULL) { 3181 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3182 m->m_data += ETHER_HDR_LEN; 3183 m->m_len -= ETHER_HDR_LEN; 3184 n->m_len = ETHER_HDR_LEN; 3185 M_MOVE_PKTHDR(n, m); 3186 n->m_next = m; 3187 sc->fmp = n; 3188 } else { 3189 sc->dropped_pkts++; 3190 m_freem(sc->fmp); 3191 sc->fmp = NULL; 3192 error = ENOMEM; 3193 } 3194 } 3195 3196 return (error); 3197} 3198#endif 3199 3200/********************************************************************* 3201 * 3202 * Verify that the hardware indicated that the checksum is valid. 3203 * Inform the stack about the status of checksum so that stack 3204 * doesn't spend time verifying the checksum. 3205 * 3206 *********************************************************************/ 3207static void 3208em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3209 struct mbuf *mp) 3210{ 3211 /* 82543 or newer only */ 3212 if ((sc->hw.mac_type < em_82543) || 3213 /* Ignore Checksum bit is set */ 3214 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3215 mp->m_pkthdr.csum_flags = 0; 3216 return; 3217 } 3218 3219 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3220 /* Did it pass? */ 3221 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3222 /* IP Checksum Good */ 3223 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3224 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3225 3226 } else { 3227 mp->m_pkthdr.csum_flags = 0; 3228 } 3229 } 3230 3231 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3232 /* Did it pass? */ 3233 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3234 mp->m_pkthdr.csum_flags |= 3235 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3236 mp->m_pkthdr.csum_data = htons(0xffff); 3237 } 3238 } 3239} 3240 3241 3242static void 3243em_enable_vlans(struct em_softc *sc) 3244{ 3245 uint32_t ctrl; 3246 3247 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3248 3249 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3250 ctrl |= E1000_CTRL_VME; 3251 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3252} 3253 3254static void 3255em_disable_vlans(struct em_softc *sc) 3256{ 3257 uint32_t ctrl; 3258 3259 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3260 ctrl &= ~E1000_CTRL_VME; 3261 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3262} 3263 3264static void 3265em_enable_intr(struct em_softc *sc) 3266{ 3267 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3268} 3269 3270static void 3271em_disable_intr(struct em_softc *sc) 3272{ 3273 /* 3274 * The first version of 82542 had an errata where when link was forced 3275 * it would stay up even up even if the cable was disconnected. 3276 * Sequence errors were used to detect the disconnect and then the 3277 * driver would unforce the link. This code in the in the ISR. For this 3278 * to work correctly the Sequence error interrupt had to be enabled 3279 * all the time. 3280 */ 3281 3282 if (sc->hw.mac_type == em_82542_rev2_0) 3283 E1000_WRITE_REG(&sc->hw, IMC, 3284 (0xffffffff & ~E1000_IMC_RXSEQ)); 3285 else 3286 E1000_WRITE_REG(&sc->hw, IMC, 3287 0xffffffff); 3288} 3289 3290static int 3291em_is_valid_ether_addr(uint8_t *addr) 3292{ 3293 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3294 3295 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3296 return (FALSE); 3297 } 3298 3299 return (TRUE); 3300} 3301 3302void 3303em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3304{ 3305 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3306} 3307 3308void 3309em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3310{ 3311 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3312} 3313 3314void 3315em_pci_set_mwi(struct em_hw *hw) 3316{ 3317 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3318 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3319} 3320 3321void 3322em_pci_clear_mwi(struct em_hw *hw) 3323{ 3324 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3325 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3326} 3327 3328/********************************************************************* 3329* 82544 Coexistence issue workaround. 3330* There are 2 issues. 3331* 1. Transmit Hang issue. 3332* To detect this issue, following equation can be used... 3333* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3334* If SUM[3:0] is in between 1 to 4, we will have this issue. 3335* 3336* 2. DAC issue. 3337* To detect this issue, following equation can be used... 3338* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3339* If SUM[3:0] is in between 9 to c, we will have this issue. 3340* 3341* 3342* WORKAROUND: 3343* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3344* 3345*** *********************************************************************/ 3346static uint32_t 3347em_fill_descriptors (bus_addr_t address, uint32_t length, 3348 PDESC_ARRAY desc_array) 3349{ 3350 /* Since issue is sensitive to length and address.*/ 3351 /* Let us first check the address...*/ 3352 uint32_t safe_terminator; 3353 if (length <= 4) { 3354 desc_array->descriptor[0].address = address; 3355 desc_array->descriptor[0].length = length; 3356 desc_array->elements = 1; 3357 return (desc_array->elements); 3358 } 3359 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3360 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3361 if (safe_terminator == 0 || 3362 (safe_terminator > 4 && 3363 safe_terminator < 9) || 3364 (safe_terminator > 0xC && 3365 safe_terminator <= 0xF)) { 3366 desc_array->descriptor[0].address = address; 3367 desc_array->descriptor[0].length = length; 3368 desc_array->elements = 1; 3369 return (desc_array->elements); 3370 } 3371 3372 desc_array->descriptor[0].address = address; 3373 desc_array->descriptor[0].length = length - 4; 3374 desc_array->descriptor[1].address = address + (length - 4); 3375 desc_array->descriptor[1].length = 4; 3376 desc_array->elements = 2; 3377 return (desc_array->elements); 3378} 3379 3380/********************************************************************** 3381 * 3382 * Update the board statistics counters. 3383 * 3384 **********************************************************************/ 3385static void 3386em_update_stats_counters(struct em_softc *sc) 3387{ 3388 struct ifnet *ifp; 3389 3390 if(sc->hw.media_type == em_media_type_copper || 3391 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3392 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3393 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3394 } 3395 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3396 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3397 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3398 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3399 3400 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3401 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3402 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3403 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3404 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3405 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3406 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3407 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3408 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3409 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3410 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3411 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3412 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3413 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3414 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3415 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3416 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3417 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3418 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3419 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3420 3421 /* For the 64-bit byte counters the low dword must be read first. */ 3422 /* Both registers clear on the read of the high dword */ 3423 3424 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3425 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3426 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3427 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3428 3429 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3430 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3431 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3432 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3433 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3434 3435 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3436 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3437 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3438 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3439 3440 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3441 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3442 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3443 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3444 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3445 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3446 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3447 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3448 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3449 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3450 3451 if (sc->hw.mac_type >= em_82543) { 3452 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3453 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3454 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3455 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3456 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3457 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3458 } 3459 ifp = sc->ifp; 3460 3461 ifp->if_collisions = sc->stats.colc; 3462 3463 /* Rx Errors */ 3464 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3465 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3466 sc->stats.mpc + sc->stats.cexterr; 3467 3468 /* Tx Errors */ 3469 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3470 sc->watchdog_events; 3471} 3472 3473 3474/********************************************************************** 3475 * 3476 * This routine is called only when em_display_debug_stats is enabled. 3477 * This routine provides a way to take a look at important statistics 3478 * maintained by the driver and hardware. 3479 * 3480 **********************************************************************/ 3481static void 3482em_print_debug_info(struct em_softc *sc) 3483{ 3484 device_t dev = sc->dev; 3485 uint8_t *hw_addr = sc->hw.hw_addr; 3486 3487 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3488 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3489 E1000_READ_REG(&sc->hw, CTRL), 3490 E1000_READ_REG(&sc->hw, RCTL)); 3491 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3492 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3493 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3494 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3495 sc->hw.fc_high_water, 3496 sc->hw.fc_low_water); 3497 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3498 E1000_READ_REG(&sc->hw, TIDV), 3499 E1000_READ_REG(&sc->hw, TADV)); 3500 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3501 E1000_READ_REG(&sc->hw, RDTR), 3502 E1000_READ_REG(&sc->hw, RADV)); 3503 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3504 (long long)sc->tx_fifo_wrk_cnt, 3505 (long long)sc->tx_fifo_reset_cnt); 3506 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3507 E1000_READ_REG(&sc->hw, TDH), 3508 E1000_READ_REG(&sc->hw, TDT)); 3509 device_printf(dev, "Num Tx descriptors avail = %d\n", 3510 sc->num_tx_desc_avail); 3511 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3512 sc->no_tx_desc_avail1); 3513 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3514 sc->no_tx_desc_avail2); 3515 device_printf(dev, "Std mbuf failed = %ld\n", 3516 sc->mbuf_alloc_failed); 3517 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3518 sc->mbuf_cluster_failed); 3519 device_printf(dev, "Driver dropped packets = %ld\n", 3520 sc->dropped_pkts); 3521} 3522 3523static void 3524em_print_hw_stats(struct em_softc *sc) 3525{ 3526 device_t dev = sc->dev; 3527 3528 device_printf(dev, "Excessive collisions = %lld\n", 3529 (long long)sc->stats.ecol); 3530 device_printf(dev, "Symbol errors = %lld\n", 3531 (long long)sc->stats.symerrs); 3532 device_printf(dev, "Sequence errors = %lld\n", 3533 (long long)sc->stats.sec); 3534 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3535 3536 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3537 device_printf(dev, "Receive No Buffers = %lld\n", 3538 (long long)sc->stats.rnbc); 3539 device_printf(dev, "Receive length errors = %lld\n", 3540 (long long)sc->stats.rlec); 3541 device_printf(dev, "Receive errors = %lld\n", 3542 (long long)sc->stats.rxerrc); 3543 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3544 device_printf(dev, "Alignment errors = %lld\n", 3545 (long long)sc->stats.algnerrc); 3546 device_printf(dev, "Carrier extension errors = %lld\n", 3547 (long long)sc->stats.cexterr); 3548 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3549 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3550 3551 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3552 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3553 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3554 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3555 3556 device_printf(dev, "Good Packets Rcvd = %lld\n", 3557 (long long)sc->stats.gprc); 3558 device_printf(dev, "Good Packets Xmtd = %lld\n", 3559 (long long)sc->stats.gptc); 3560} 3561 3562static int 3563em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3564{ 3565 struct em_softc *sc; 3566 int error; 3567 int result; 3568 3569 result = -1; 3570 error = sysctl_handle_int(oidp, &result, 0, req); 3571 3572 if (error || !req->newptr) 3573 return (error); 3574 3575 if (result == 1) { 3576 sc = (struct em_softc *)arg1; 3577 em_print_debug_info(sc); 3578 } 3579 3580 return (error); 3581} 3582 3583 3584static int 3585em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3586{ 3587 struct em_softc *sc; 3588 int error; 3589 int result; 3590 3591 result = -1; 3592 error = sysctl_handle_int(oidp, &result, 0, req); 3593 3594 if (error || !req->newptr) 3595 return (error); 3596 3597 if (result == 1) { 3598 sc = (struct em_softc *)arg1; 3599 em_print_hw_stats(sc); 3600 } 3601 3602 return (error); 3603} 3604 3605static int 3606em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3607{ 3608 struct em_int_delay_info *info; 3609 struct em_softc *sc; 3610 uint32_t regval; 3611 int error; 3612 int usecs; 3613 int ticks; 3614 3615 info = (struct em_int_delay_info *)arg1; 3616 usecs = info->value; 3617 error = sysctl_handle_int(oidp, &usecs, 0, req); 3618 if (error != 0 || req->newptr == NULL) 3619 return (error); 3620 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3621 return (EINVAL); 3622 info->value = usecs; 3623 ticks = E1000_USECS_TO_TICKS(usecs); 3624 3625 sc = info->sc; 3626 3627 EM_LOCK(sc); 3628 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3629 regval = (regval & ~0xffff) | (ticks & 0xffff); 3630 /* Handle a few special cases. */ 3631 switch (info->offset) { 3632 case E1000_RDTR: 3633 case E1000_82542_RDTR: 3634 regval |= E1000_RDT_FPDB; 3635 break; 3636 case E1000_TIDV: 3637 case E1000_82542_TIDV: 3638 if (ticks == 0) { 3639 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3640 /* Don't write 0 into the TIDV register. */ 3641 regval++; 3642 } else 3643 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3644 break; 3645 } 3646 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3647 EM_UNLOCK(sc); 3648 return (0); 3649} 3650 3651static void 3652em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3653 const char *description, struct em_int_delay_info *info, 3654 int offset, int value) 3655{ 3656 info->sc = sc; 3657 info->offset = offset; 3658 info->value = value; 3659 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3660 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3661 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3662 info, 0, em_sysctl_int_delay, "I", description); 3663} 3664 3665#ifndef DEVICE_POLLING 3666static void 3667em_add_int_process_limit(struct em_softc *sc, const char *name, 3668 const char *description, int *limit, int value) 3669{ 3670 *limit = value; 3671 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3672 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3673 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3674} 3675#endif 3676