if_em.c revision 157566
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 157566 2006-04-06 17:09:03Z glebius $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 5.1.5"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 143 PCI_ANY_ID, PCI_ANY_ID, 0}, 144 145 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 149 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 153 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 158 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 159 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 162 PCI_ANY_ID, PCI_ANY_ID, 0}, 163 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 164 PCI_ANY_ID, PCI_ANY_ID, 0}, 165 166 /* required last entry */ 167 { 0, 0, 0, 0, 0} 168}; 169 170/********************************************************************* 171 * Table of branding strings for all supported NICs. 172 *********************************************************************/ 173 174static char *em_strings[] = { 175 "Intel(R) PRO/1000 Network Connection" 176}; 177 178/********************************************************************* 179 * Function prototypes 180 *********************************************************************/ 181static int em_probe(device_t); 182static int em_attach(device_t); 183static int em_detach(device_t); 184static int em_shutdown(device_t); 185static int em_suspend(device_t); 186static int em_resume(device_t); 187static void em_intr(void *); 188#ifndef NO_EM_FASTINTR 189static void em_intr_fast(void *); 190#endif 191static void em_start(struct ifnet *); 192static void em_start_locked(struct ifnet *ifp); 193static int em_ioctl(struct ifnet *, u_long, caddr_t); 194static void em_watchdog(struct ifnet *); 195static void em_init(void *); 196static void em_init_locked(struct em_softc *); 197static void em_stop(void *); 198static void em_media_status(struct ifnet *, struct ifmediareq *); 199static int em_media_change(struct ifnet *); 200static void em_identify_hardware(struct em_softc *); 201static int em_allocate_pci_resources(struct em_softc *); 202static int em_allocate_intr(struct em_softc *); 203static void em_free_intr(struct em_softc *); 204static void em_free_pci_resources(struct em_softc *); 205static void em_local_timer(void *); 206static int em_hardware_init(struct em_softc *); 207static void em_setup_interface(device_t, struct em_softc *); 208static int em_setup_transmit_structures(struct em_softc *); 209static void em_initialize_transmit_unit(struct em_softc *); 210static int em_setup_receive_structures(struct em_softc *); 211static void em_initialize_receive_unit(struct em_softc *); 212static void em_enable_intr(struct em_softc *); 213static void em_disable_intr(struct em_softc *); 214static void em_free_transmit_structures(struct em_softc *); 215static void em_free_receive_structures(struct em_softc *); 216static void em_update_stats_counters(struct em_softc *); 217static void em_txeof(struct em_softc *); 218static int em_allocate_receive_structures(struct em_softc *); 219static int em_allocate_transmit_structures(struct em_softc *); 220static int em_rxeof(struct em_softc *, int); 221#ifndef __NO_STRICT_ALIGNMENT 222static int em_fixup_rx(struct em_softc *); 223#endif 224static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 225 struct mbuf *); 226static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 227 uint32_t *, uint32_t *); 228static void em_set_promisc(struct em_softc *); 229static void em_disable_promisc(struct em_softc *); 230static void em_set_multi(struct em_softc *); 231static void em_print_hw_stats(struct em_softc *); 232static void em_update_link_status(struct em_softc *); 233static int em_get_buf(int i, struct em_softc *, struct mbuf *); 234static void em_enable_vlans(struct em_softc *); 235static void em_disable_vlans(struct em_softc *); 236static int em_encap(struct em_softc *, struct mbuf **); 237static void em_smartspeed(struct em_softc *); 238static int em_82547_fifo_workaround(struct em_softc *, int); 239static void em_82547_update_fifo_head(struct em_softc *, int); 240static int em_82547_tx_fifo_reset(struct em_softc *); 241static void em_82547_move_tail(void *arg); 242static void em_82547_move_tail_locked(struct em_softc *); 243static int em_dma_malloc(struct em_softc *, bus_size_t, 244 struct em_dma_alloc *, int); 245static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 246static void em_print_debug_info(struct em_softc *); 247static int em_is_valid_ether_addr(uint8_t *); 248static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 249static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 250static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 251 PDESC_ARRAY desc_array); 252static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 253static void em_add_int_delay_sysctl(struct em_softc *, const char *, 254 const char *, struct em_int_delay_info *, int, int); 255#ifndef NO_EM_FASTINTR 256static void em_add_int_process_limit(struct em_softc *, const char *, 257 const char *, int *, int); 258static void em_handle_rxtx(void *context, int pending); 259static void em_handle_link(void *context, int pending); 260#endif 261#ifdef DEVICE_POLLING 262static poll_handler_t em_poll; 263#endif 264 265/********************************************************************* 266 * FreeBSD Device Interface Entry Points 267 *********************************************************************/ 268 269static device_method_t em_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, em_probe), 272 DEVMETHOD(device_attach, em_attach), 273 DEVMETHOD(device_detach, em_detach), 274 DEVMETHOD(device_shutdown, em_shutdown), 275 DEVMETHOD(device_suspend, em_suspend), 276 DEVMETHOD(device_resume, em_resume), 277 {0, 0} 278}; 279 280static driver_t em_driver = { 281 "em", em_methods, sizeof(struct em_softc), 282}; 283 284static devclass_t em_devclass; 285DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 286MODULE_DEPEND(em, pci, 1, 1, 1); 287MODULE_DEPEND(em, ether, 1, 1, 1); 288 289/********************************************************************* 290 * Tunable default values. 291 *********************************************************************/ 292 293#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 294#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 295 296static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 297static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 298static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 299static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 300static int em_rxd = EM_DEFAULT_RXD; 301static int em_txd = EM_DEFAULT_TXD; 302 303TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 304TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 305TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 306TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 307TUNABLE_INT("hw.em.rxd", &em_rxd); 308TUNABLE_INT("hw.em.txd", &em_txd); 309#ifndef NO_EM_FASTINTR 310static int em_rx_process_limit = 100; 311TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 312#endif 313 314/********************************************************************* 315 * Device identification routine 316 * 317 * em_probe determines if the driver should be loaded on 318 * adapter based on PCI vendor/device id of the adapter. 319 * 320 * return BUS_PROBE_DEFAULT on success, positive on failure 321 *********************************************************************/ 322 323static int 324em_probe(device_t dev) 325{ 326 char adapter_name[60]; 327 uint16_t pci_vendor_id = 0; 328 uint16_t pci_device_id = 0; 329 uint16_t pci_subvendor_id = 0; 330 uint16_t pci_subdevice_id = 0; 331 em_vendor_info_t *ent; 332 333 INIT_DEBUGOUT("em_probe: begin"); 334 335 pci_vendor_id = pci_get_vendor(dev); 336 if (pci_vendor_id != EM_VENDOR_ID) 337 return (ENXIO); 338 339 pci_device_id = pci_get_device(dev); 340 pci_subvendor_id = pci_get_subvendor(dev); 341 pci_subdevice_id = pci_get_subdevice(dev); 342 343 ent = em_vendor_info_array; 344 while (ent->vendor_id != 0) { 345 if ((pci_vendor_id == ent->vendor_id) && 346 (pci_device_id == ent->device_id) && 347 348 ((pci_subvendor_id == ent->subvendor_id) || 349 (ent->subvendor_id == PCI_ANY_ID)) && 350 351 ((pci_subdevice_id == ent->subdevice_id) || 352 (ent->subdevice_id == PCI_ANY_ID))) { 353 sprintf(adapter_name, "%s %s", 354 em_strings[ent->index], 355 em_driver_version); 356 device_set_desc_copy(dev, adapter_name); 357 return (BUS_PROBE_DEFAULT); 358 } 359 ent++; 360 } 361 362 return (ENXIO); 363} 364 365/********************************************************************* 366 * Device initialization routine 367 * 368 * The attach entry point is called when the driver is being loaded. 369 * This routine identifies the type of hardware, allocates all resources 370 * and initializes the hardware. 371 * 372 * return 0 on success, positive on failure 373 *********************************************************************/ 374 375static int 376em_attach(device_t dev) 377{ 378 struct em_softc *sc; 379 int tsize, rsize; 380 int error = 0; 381 382 INIT_DEBUGOUT("em_attach: begin"); 383 384 sc = device_get_softc(dev); 385 sc->dev = sc->osdep.dev = dev; 386 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 387 388 /* SYSCTL stuff */ 389 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 390 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 391 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 392 em_sysctl_debug_info, "I", "Debug Information"); 393 394 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 395 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 396 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 397 em_sysctl_stats, "I", "Statistics"); 398 399 callout_init(&sc->timer, CALLOUT_MPSAFE); 400 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 401 402 /* Determine hardware revision */ 403 em_identify_hardware(sc); 404 405 /* Set up some sysctls for the tunable interrupt delays */ 406 em_add_int_delay_sysctl(sc, "rx_int_delay", 407 "receive interrupt delay in usecs", &sc->rx_int_delay, 408 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 409 em_add_int_delay_sysctl(sc, "tx_int_delay", 410 "transmit interrupt delay in usecs", &sc->tx_int_delay, 411 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 412 if (sc->hw.mac_type >= em_82540) { 413 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 414 "receive interrupt delay limit in usecs", 415 &sc->rx_abs_int_delay, 416 E1000_REG_OFFSET(&sc->hw, RADV), 417 em_rx_abs_int_delay_dflt); 418 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 419 "transmit interrupt delay limit in usecs", 420 &sc->tx_abs_int_delay, 421 E1000_REG_OFFSET(&sc->hw, TADV), 422 em_tx_abs_int_delay_dflt); 423 } 424 425 /* Sysctls for limiting the amount of work done in the taskqueue */ 426#ifndef NO_EM_FASTINTR 427 em_add_int_process_limit(sc, "rx_processing_limit", 428 "max number of rx packets to process", &sc->rx_process_limit, 429 em_rx_process_limit); 430#endif 431 432 /* 433 * Validate number of transmit and receive descriptors. It 434 * must not exceed hardware maximum, and must be multiple 435 * of E1000_DBA_ALIGN. 436 */ 437 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 438 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 439 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 440 (em_txd < EM_MIN_TXD)) { 441 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 442 EM_DEFAULT_TXD, em_txd); 443 sc->num_tx_desc = EM_DEFAULT_TXD; 444 } else 445 sc->num_tx_desc = em_txd; 446 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 447 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 448 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 449 (em_rxd < EM_MIN_RXD)) { 450 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 451 EM_DEFAULT_RXD, em_rxd); 452 sc->num_rx_desc = EM_DEFAULT_RXD; 453 } else 454 sc->num_rx_desc = em_rxd; 455 456 sc->hw.autoneg = DO_AUTO_NEG; 457 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 458 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 459 sc->hw.tbi_compatibility_en = TRUE; 460 sc->rx_buffer_len = EM_RXBUFFER_2048; 461 462 sc->hw.phy_init_script = 1; 463 sc->hw.phy_reset_disable = FALSE; 464 465#ifndef EM_MASTER_SLAVE 466 sc->hw.master_slave = em_ms_hw_default; 467#else 468 sc->hw.master_slave = EM_MASTER_SLAVE; 469#endif 470 /* 471 * Set the max frame size assuming standard ethernet 472 * sized frames. 473 */ 474 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 475 476 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 477 478 /* 479 * This controls when hardware reports transmit completion 480 * status. 481 */ 482 sc->hw.report_tx_early = 1; 483 if (em_allocate_pci_resources(sc)) { 484 device_printf(dev, "Allocation of PCI resources failed\n"); 485 error = ENXIO; 486 goto err_pci; 487 } 488 489 /* Initialize eeprom parameters */ 490 em_init_eeprom_params(&sc->hw); 491 492 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 493 E1000_DBA_ALIGN); 494 495 /* Allocate Transmit Descriptor ring */ 496 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 497 device_printf(dev, "Unable to allocate tx_desc memory\n"); 498 error = ENOMEM; 499 goto err_tx_desc; 500 } 501 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 502 503 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 504 E1000_DBA_ALIGN); 505 506 /* Allocate Receive Descriptor ring */ 507 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 508 device_printf(dev, "Unable to allocate rx_desc memory\n"); 509 error = ENOMEM; 510 goto err_rx_desc; 511 } 512 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 513 514 /* Initialize the hardware */ 515 if (em_hardware_init(sc)) { 516 device_printf(dev, "Unable to initialize the hardware\n"); 517 error = EIO; 518 goto err_hw_init; 519 } 520 521 /* Copy the permanent MAC address out of the EEPROM */ 522 if (em_read_mac_addr(&sc->hw) < 0) { 523 device_printf(dev, "EEPROM read error while reading MAC" 524 " address\n"); 525 error = EIO; 526 goto err_hw_init; 527 } 528 529 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 530 device_printf(dev, "Invalid MAC address\n"); 531 error = EIO; 532 goto err_hw_init; 533 } 534 535 /* Setup OS specific network interface */ 536 em_setup_interface(dev, sc); 537 538 em_allocate_intr(sc); 539 540 /* Initialize statistics */ 541 em_clear_hw_cntrs(&sc->hw); 542 em_update_stats_counters(sc); 543 sc->hw.get_link_status = 1; 544 em_update_link_status(sc); 545 546 /* Indicate SOL/IDER usage */ 547 if (em_check_phy_reset_block(&sc->hw)) 548 device_printf(dev, 549 "PHY reset is blocked due to SOL/IDER session.\n"); 550 551 /* Identify 82544 on PCIX */ 552 em_get_bus_info(&sc->hw); 553 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 554 sc->pcix_82544 = TRUE; 555 else 556 sc->pcix_82544 = FALSE; 557 558 INIT_DEBUGOUT("em_attach: end"); 559 560 return (0); 561 562err_hw_init: 563 em_dma_free(sc, &sc->rxdma); 564err_rx_desc: 565 em_dma_free(sc, &sc->txdma); 566err_tx_desc: 567err_pci: 568 em_free_intr(sc); 569 em_free_pci_resources(sc); 570 EM_LOCK_DESTROY(sc); 571 572 return (error); 573} 574 575/********************************************************************* 576 * Device removal routine 577 * 578 * The detach entry point is called when the driver is being removed. 579 * This routine stops the adapter and deallocates all the resources 580 * that were allocated for driver operation. 581 * 582 * return 0 on success, positive on failure 583 *********************************************************************/ 584 585static int 586em_detach(device_t dev) 587{ 588 struct em_softc *sc = device_get_softc(dev); 589 struct ifnet *ifp = sc->ifp; 590 591 INIT_DEBUGOUT("em_detach: begin"); 592 593#ifdef DEVICE_POLLING 594 if (ifp->if_capenable & IFCAP_POLLING) 595 ether_poll_deregister(ifp); 596#endif 597 598 em_free_intr(sc); 599 EM_LOCK(sc); 600 sc->in_detach = 1; 601 em_stop(sc); 602 em_phy_hw_reset(&sc->hw); 603 EM_UNLOCK(sc); 604 ether_ifdetach(sc->ifp); 605 606 em_free_pci_resources(sc); 607 bus_generic_detach(dev); 608 if_free(ifp); 609 610 /* Free Transmit Descriptor ring */ 611 if (sc->tx_desc_base) { 612 em_dma_free(sc, &sc->txdma); 613 sc->tx_desc_base = NULL; 614 } 615 616 /* Free Receive Descriptor ring */ 617 if (sc->rx_desc_base) { 618 em_dma_free(sc, &sc->rxdma); 619 sc->rx_desc_base = NULL; 620 } 621 622 EM_LOCK_DESTROY(sc); 623 624 return (0); 625} 626 627/********************************************************************* 628 * 629 * Shutdown entry point 630 * 631 **********************************************************************/ 632 633static int 634em_shutdown(device_t dev) 635{ 636 struct em_softc *sc = device_get_softc(dev); 637 EM_LOCK(sc); 638 em_stop(sc); 639 EM_UNLOCK(sc); 640 return (0); 641} 642 643/* 644 * Suspend/resume device methods. 645 */ 646static int 647em_suspend(device_t dev) 648{ 649 struct em_softc *sc = device_get_softc(dev); 650 651 EM_LOCK(sc); 652 em_stop(sc); 653 EM_UNLOCK(sc); 654 655 return bus_generic_suspend(dev); 656} 657 658static int 659em_resume(device_t dev) 660{ 661 struct em_softc *sc = device_get_softc(dev); 662 struct ifnet *ifp = sc->ifp; 663 664 EM_LOCK(sc); 665 em_init_locked(sc); 666 if ((ifp->if_flags & IFF_UP) && 667 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 668 em_start_locked(ifp); 669 EM_UNLOCK(sc); 670 671 return bus_generic_resume(dev); 672} 673 674 675/********************************************************************* 676 * Transmit entry point 677 * 678 * em_start is called by the stack to initiate a transmit. 679 * The driver will remain in this routine as long as there are 680 * packets to transmit and transmit resources are available. 681 * In case resources are not available stack is notified and 682 * the packet is requeued. 683 **********************************************************************/ 684 685static void 686em_start_locked(struct ifnet *ifp) 687{ 688 struct em_softc *sc = ifp->if_softc; 689 struct mbuf *m_head; 690 691 EM_LOCK_ASSERT(sc); 692 693 if (!sc->link_active) 694 return; 695 696 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 697 698 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 699 if (m_head == NULL) 700 break; 701 /* 702 * em_encap() can modify our pointer, and or make it NULL on 703 * failure. In that event, we can't requeue. 704 */ 705 if (em_encap(sc, &m_head)) { 706 if (m_head == NULL) 707 break; 708 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 709 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 710 break; 711 } 712 713 /* Send a copy of the frame to the BPF listener */ 714 BPF_MTAP(ifp, m_head); 715 716 /* Set timeout in case hardware has problems transmitting. */ 717 ifp->if_timer = EM_TX_TIMEOUT; 718 } 719} 720 721static void 722em_start(struct ifnet *ifp) 723{ 724 struct em_softc *sc = ifp->if_softc; 725 726 EM_LOCK(sc); 727 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 728 em_start_locked(ifp); 729 EM_UNLOCK(sc); 730} 731 732/********************************************************************* 733 * Ioctl entry point 734 * 735 * em_ioctl is called when the user wants to configure the 736 * interface. 737 * 738 * return 0 on success, positive on failure 739 **********************************************************************/ 740 741static int 742em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 743{ 744 struct em_softc *sc = ifp->if_softc; 745 struct ifreq *ifr = (struct ifreq *)data; 746 int error = 0; 747 748 if (sc->in_detach) 749 return (error); 750 751 switch (command) { 752 case SIOCSIFADDR: 753 case SIOCGIFADDR: 754 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 755 ether_ioctl(ifp, command, data); 756 break; 757 case SIOCSIFMTU: 758 { 759 int max_frame_size; 760 uint16_t eeprom_data = 0; 761 762 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 763 764 switch (sc->hw.mac_type) { 765 case em_82573: 766 /* 767 * 82573 only supports jumbo frames 768 * if ASPM is disabled. 769 */ 770 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1, 771 &eeprom_data); 772 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 773 max_frame_size = ETHER_MAX_LEN; 774 break; 775 } 776 /* Allow Jumbo frames - fall thru */ 777 case em_82571: 778 case em_82572: 779 case em_80003es2lan: /* Limit Jumbo Frame size */ 780 max_frame_size = 9234; 781 break; 782 default: 783 max_frame_size = MAX_JUMBO_FRAME_SIZE; 784 } 785 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 786 ETHER_CRC_LEN) { 787 error = EINVAL; 788 break; 789 } 790 791 EM_LOCK(sc); 792 ifp->if_mtu = ifr->ifr_mtu; 793 sc->hw.max_frame_size = 794 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 795 em_init_locked(sc); 796 EM_UNLOCK(sc); 797 break; 798 } 799 case SIOCSIFFLAGS: 800 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 801 EM_LOCK(sc); 802 if (ifp->if_flags & IFF_UP) { 803 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 804 em_init_locked(sc); 805 } 806 807 em_disable_promisc(sc); 808 em_set_promisc(sc); 809 } else { 810 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 811 em_stop(sc); 812 } 813 } 814 EM_UNLOCK(sc); 815 break; 816 case SIOCADDMULTI: 817 case SIOCDELMULTI: 818 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 819 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 820 EM_LOCK(sc); 821 em_disable_intr(sc); 822 em_set_multi(sc); 823 if (sc->hw.mac_type == em_82542_rev2_0) { 824 em_initialize_receive_unit(sc); 825 } 826#ifdef DEVICE_POLLING 827 if (!(ifp->if_capenable & IFCAP_POLLING)) 828#endif 829 em_enable_intr(sc); 830 EM_UNLOCK(sc); 831 } 832 break; 833 case SIOCSIFMEDIA: 834 case SIOCGIFMEDIA: 835 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 836 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 837 break; 838 case SIOCSIFCAP: 839 { 840 int mask, reinit; 841 842 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 843 reinit = 0; 844 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 845#ifdef DEVICE_POLLING 846 if (mask & IFCAP_POLLING) { 847 if (ifr->ifr_reqcap & IFCAP_POLLING) { 848 error = ether_poll_register(em_poll, ifp); 849 if (error) 850 return (error); 851 EM_LOCK(sc); 852 em_disable_intr(sc); 853 ifp->if_capenable |= IFCAP_POLLING; 854 EM_UNLOCK(sc); 855 } else { 856 error = ether_poll_deregister(ifp); 857 /* Enable interrupt even in error case */ 858 EM_LOCK(sc); 859 em_enable_intr(sc); 860 ifp->if_capenable &= ~IFCAP_POLLING; 861 EM_UNLOCK(sc); 862 } 863 } 864#endif 865 if (mask & IFCAP_HWCSUM) { 866 ifp->if_capenable ^= IFCAP_HWCSUM; 867 reinit = 1; 868 } 869 if (mask & IFCAP_VLAN_HWTAGGING) { 870 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 871 reinit = 1; 872 } 873 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 874 em_init(sc); 875 VLAN_CAPABILITIES(ifp); 876 break; 877 } 878 default: 879 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 880 error = EINVAL; 881 } 882 883 return (error); 884} 885 886/********************************************************************* 887 * Watchdog entry point 888 * 889 * This routine is called whenever hardware quits transmitting. 890 * 891 **********************************************************************/ 892 893static void 894em_watchdog(struct ifnet *ifp) 895{ 896 struct em_softc *sc = ifp->if_softc; 897 898 EM_LOCK(sc); 899 /* If we are in this routine because of pause frames, then 900 * don't reset the hardware. 901 */ 902 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 903 ifp->if_timer = EM_TX_TIMEOUT; 904 EM_UNLOCK(sc); 905 return; 906 } 907 908 if (em_check_for_link(&sc->hw) == 0) 909 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 910 911 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 912 sc->watchdog_events++; 913 914 em_init_locked(sc); 915 EM_UNLOCK(sc); 916} 917 918/********************************************************************* 919 * Init entry point 920 * 921 * This routine is used in two ways. It is used by the stack as 922 * init entry point in network interface structure. It is also used 923 * by the driver as a hw/sw initialization routine to get to a 924 * consistent state. 925 * 926 * return 0 on success, positive on failure 927 **********************************************************************/ 928 929static void 930em_init_locked(struct em_softc *sc) 931{ 932 struct ifnet *ifp = sc->ifp; 933 device_t dev = sc->dev; 934 uint32_t pba; 935 936 INIT_DEBUGOUT("em_init: begin"); 937 938 EM_LOCK_ASSERT(sc); 939 940 em_stop(sc); 941 942 /* 943 * Packet Buffer Allocation (PBA) 944 * Writing PBA sets the receive portion of the buffer 945 * the remainder is used for the transmit buffer. 946 */ 947 switch (sc->hw.mac_type) { 948 case em_82547: 949 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 950 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 951 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 952 else 953 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 954 sc->tx_fifo_head = 0; 955 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 956 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 957 break; 958 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */ 959 case em_82571: /* 82571: Total Packet Buffer is 48K */ 960 case em_82572: /* 82572: Total Packet Buffer is 48K */ 961 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 962 break; 963 case em_82573: /* 82573: Total Packet Buffer is 32K */ 964 /* Jumbo frames not supported */ 965 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 966 break; 967 default: 968 /* Devices before 82547 had a Packet Buffer of 64K. */ 969 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 970 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 971 else 972 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 973 } 974 975 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 976 E1000_WRITE_REG(&sc->hw, PBA, pba); 977 978 /* Get the latest mac address, User can use a LAA */ 979 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 980 981 /* Initialize the hardware */ 982 if (em_hardware_init(sc)) { 983 device_printf(dev, "Unable to initialize the hardware\n"); 984 return; 985 } 986 em_update_link_status(sc); 987 988 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 989 em_enable_vlans(sc); 990 991 /* Prepare transmit descriptors and buffers */ 992 if (em_setup_transmit_structures(sc)) { 993 device_printf(dev, "Could not setup transmit structures\n"); 994 em_stop(sc); 995 return; 996 } 997 em_initialize_transmit_unit(sc); 998 999 /* Setup Multicast table */ 1000 em_set_multi(sc); 1001 1002 /* Prepare receive descriptors and buffers */ 1003 if (em_setup_receive_structures(sc)) { 1004 device_printf(dev, "Could not setup receive structures\n"); 1005 em_stop(sc); 1006 return; 1007 } 1008 em_initialize_receive_unit(sc); 1009 1010 /* Don't loose promiscuous settings */ 1011 em_set_promisc(sc); 1012 1013 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1014 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1015 1016 if (sc->hw.mac_type >= em_82543) { 1017 if (ifp->if_capenable & IFCAP_TXCSUM) 1018 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1019 else 1020 ifp->if_hwassist = 0; 1021 } 1022 1023 callout_reset(&sc->timer, hz, em_local_timer, sc); 1024 em_clear_hw_cntrs(&sc->hw); 1025#ifdef DEVICE_POLLING 1026 /* 1027 * Only enable interrupts if we are not polling, make sure 1028 * they are off otherwise. 1029 */ 1030 if (ifp->if_capenable & IFCAP_POLLING) 1031 em_disable_intr(sc); 1032 else 1033#endif /* DEVICE_POLLING */ 1034 em_enable_intr(sc); 1035 1036 /* Don't reset the phy next time init gets called */ 1037 sc->hw.phy_reset_disable = TRUE; 1038} 1039 1040static void 1041em_init(void *arg) 1042{ 1043 struct em_softc *sc = arg; 1044 1045 EM_LOCK(sc); 1046 em_init_locked(sc); 1047 EM_UNLOCK(sc); 1048} 1049 1050 1051#ifdef DEVICE_POLLING 1052static void 1053em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1054{ 1055 struct em_softc *sc = ifp->if_softc; 1056 uint32_t reg_icr; 1057 1058 EM_LOCK_ASSERT(sc); 1059 1060 if (cmd == POLL_AND_CHECK_STATUS) { 1061 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1062 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1063 callout_stop(&sc->timer); 1064 sc->hw.get_link_status = 1; 1065 em_check_for_link(&sc->hw); 1066 em_update_link_status(sc); 1067 callout_reset(&sc->timer, hz, em_local_timer, sc); 1068 } 1069 } 1070 em_rxeof(sc, count); 1071 em_txeof(sc); 1072 1073 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1074 em_start_locked(ifp); 1075} 1076 1077static void 1078em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1079{ 1080 struct em_softc *sc = ifp->if_softc; 1081 1082 EM_LOCK(sc); 1083 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1084 em_poll_locked(ifp, cmd, count); 1085 EM_UNLOCK(sc); 1086} 1087#endif /* DEVICE_POLLING */ 1088 1089#ifndef NO_EM_FASTINTR 1090static void 1091em_handle_link(void *context, int pending) 1092{ 1093 struct em_softc *sc = context; 1094 struct ifnet *ifp; 1095 1096 ifp = sc->ifp; 1097 1098 EM_LOCK(sc); 1099 1100 callout_stop(&sc->timer); 1101 sc->hw.get_link_status = 1; 1102 em_check_for_link(&sc->hw); 1103 em_update_link_status(sc); 1104 callout_reset(&sc->timer, hz, em_local_timer, sc); 1105 EM_UNLOCK(sc); 1106} 1107 1108static void 1109em_handle_rxtx(void *context, int pending) 1110{ 1111 struct em_softc *sc = context; 1112 struct ifnet *ifp; 1113 1114 NET_LOCK_GIANT(); 1115 ifp = sc->ifp; 1116 1117 /* 1118 * TODO: 1119 * It should be possible to run the tx clean loop without the lock. 1120 */ 1121 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1122 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1123 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1124 EM_LOCK(sc); 1125 em_txeof(sc); 1126 1127 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1128 em_start_locked(ifp); 1129 EM_UNLOCK(sc); 1130 } 1131 1132 em_enable_intr(sc); 1133 NET_UNLOCK_GIANT(); 1134} 1135#endif 1136 1137/********************************************************************* 1138 * 1139 * Interrupt Service routine 1140 * 1141 **********************************************************************/ 1142#ifndef NO_EM_FASTINTR 1143static void 1144em_intr_fast(void *arg) 1145{ 1146 struct em_softc *sc = arg; 1147 struct ifnet *ifp; 1148 uint32_t reg_icr; 1149 1150 ifp = sc->ifp; 1151 1152#ifdef DEVICE_POLLING 1153 if (ifp->if_capenable & IFCAP_POLLING) 1154 return; 1155#endif /* DEVICE_POLLING */ 1156 1157 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1158 1159 /* Hot eject? */ 1160 if (reg_icr == 0xffffffff) 1161 return; 1162 1163 /* Definitely not our interrupt. */ 1164 if (reg_icr == 0x0) 1165 return; 1166 1167 /* 1168 * Starting with the 82571 chip, bit 31 should be used to 1169 * determine whether the interrupt belongs to us. 1170 */ 1171 if (sc->hw.mac_type >= em_82571 && 1172 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1173 return; 1174 1175 /* 1176 * Mask interrupts until the taskqueue is finished running. This is 1177 * cheap, just assume that it is needed. This also works around the 1178 * MSI message reordering errata on certain systems. 1179 */ 1180 em_disable_intr(sc); 1181 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1182 1183 /* Link status change */ 1184 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1185 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1186 1187 if (reg_icr & E1000_ICR_RXO) 1188 sc->rx_overruns++; 1189} 1190#endif 1191 1192static void 1193em_intr(void *arg) 1194{ 1195 struct em_softc *sc = arg; 1196 struct ifnet *ifp; 1197 uint32_t reg_icr; 1198 int wantinit = 0; 1199 1200 EM_LOCK(sc); 1201 1202 ifp = sc->ifp; 1203 1204#ifdef DEVICE_POLLING 1205 if (ifp->if_capenable & IFCAP_POLLING) { 1206 EM_UNLOCK(sc); 1207 return; 1208 } 1209#endif 1210 1211 for (;;) { 1212 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1213 if (sc->hw.mac_type >= em_82571 && 1214 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1215 break; 1216 else if (reg_icr == 0) 1217 break; 1218 1219 /* 1220 * XXX: some laptops trigger several spurious interrupts 1221 * on em(4) when in the resume cycle. The ICR register 1222 * reports all-ones value in this case. Processing such 1223 * interrupts would lead to a freeze. I don't know why. 1224 */ 1225 if (reg_icr == 0xffffffff) 1226 break; 1227 1228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1229 em_rxeof(sc, -1); 1230 em_txeof(sc); 1231 } 1232 1233 /* Link status change */ 1234 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1235 callout_stop(&sc->timer); 1236 sc->hw.get_link_status = 1; 1237 em_check_for_link(&sc->hw); 1238 em_update_link_status(sc); 1239 callout_reset(&sc->timer, hz, em_local_timer, sc); 1240 } 1241 1242 if (reg_icr & E1000_ICR_RXO) { 1243 sc->rx_overruns++; 1244 wantinit = 1; 1245 } 1246 } 1247#if 0 1248 if (wantinit) 1249 em_init_locked(sc); 1250#endif 1251 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1252 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1253 em_start_locked(ifp); 1254 1255 EM_UNLOCK(sc); 1256} 1257 1258/********************************************************************* 1259 * 1260 * Media Ioctl callback 1261 * 1262 * This routine is called whenever the user queries the status of 1263 * the interface using ifconfig. 1264 * 1265 **********************************************************************/ 1266static void 1267em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1268{ 1269 struct em_softc *sc = ifp->if_softc; 1270 1271 INIT_DEBUGOUT("em_media_status: begin"); 1272 1273 em_check_for_link(&sc->hw); 1274 em_update_link_status(sc); 1275 1276 ifmr->ifm_status = IFM_AVALID; 1277 ifmr->ifm_active = IFM_ETHER; 1278 1279 if (!sc->link_active) 1280 return; 1281 1282 ifmr->ifm_status |= IFM_ACTIVE; 1283 1284 if (sc->hw.media_type == em_media_type_fiber) { 1285 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1286 } else { 1287 switch (sc->link_speed) { 1288 case 10: 1289 ifmr->ifm_active |= IFM_10_T; 1290 break; 1291 case 100: 1292 ifmr->ifm_active |= IFM_100_TX; 1293 break; 1294 case 1000: 1295 ifmr->ifm_active |= IFM_1000_T; 1296 break; 1297 } 1298 if (sc->link_duplex == FULL_DUPLEX) 1299 ifmr->ifm_active |= IFM_FDX; 1300 else 1301 ifmr->ifm_active |= IFM_HDX; 1302 } 1303} 1304 1305/********************************************************************* 1306 * 1307 * Media Ioctl callback 1308 * 1309 * This routine is called when the user changes speed/duplex using 1310 * media/mediopt option with ifconfig. 1311 * 1312 **********************************************************************/ 1313static int 1314em_media_change(struct ifnet *ifp) 1315{ 1316 struct em_softc *sc = ifp->if_softc; 1317 struct ifmedia *ifm = &sc->media; 1318 1319 INIT_DEBUGOUT("em_media_change: begin"); 1320 1321 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1322 return (EINVAL); 1323 1324 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1325 case IFM_AUTO: 1326 sc->hw.autoneg = DO_AUTO_NEG; 1327 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1328 break; 1329 case IFM_1000_SX: 1330 case IFM_1000_T: 1331 sc->hw.autoneg = DO_AUTO_NEG; 1332 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1333 break; 1334 case IFM_100_TX: 1335 sc->hw.autoneg = FALSE; 1336 sc->hw.autoneg_advertised = 0; 1337 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1338 sc->hw.forced_speed_duplex = em_100_full; 1339 else 1340 sc->hw.forced_speed_duplex = em_100_half; 1341 break; 1342 case IFM_10_T: 1343 sc->hw.autoneg = FALSE; 1344 sc->hw.autoneg_advertised = 0; 1345 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1346 sc->hw.forced_speed_duplex = em_10_full; 1347 else 1348 sc->hw.forced_speed_duplex = em_10_half; 1349 break; 1350 default: 1351 device_printf(sc->dev, "Unsupported media type\n"); 1352 } 1353 1354 /* As the speed/duplex settings my have changed we need to 1355 * reset the PHY. 1356 */ 1357 sc->hw.phy_reset_disable = FALSE; 1358 1359 em_init(sc); 1360 1361 return (0); 1362} 1363 1364/********************************************************************* 1365 * 1366 * This routine maps the mbufs to tx descriptors. 1367 * 1368 * return 0 on success, positive on failure 1369 **********************************************************************/ 1370static int 1371em_encap(struct em_softc *sc, struct mbuf **m_headp) 1372{ 1373 struct ifnet *ifp = sc->ifp; 1374 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1375 bus_dmamap_t map; 1376 struct em_buffer *tx_buffer; 1377 struct em_tx_desc *current_tx_desc; 1378 struct mbuf *m_head; 1379 struct m_tag *mtag; 1380 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1381 int nsegs, i, j; 1382 int error = 0; 1383 1384 m_head = *m_headp; 1385 current_tx_desc = NULL; 1386 txd_used = txd_saved = 0; 1387 1388 /* 1389 * Force a cleanup if number of TX descriptors 1390 * available hits the threshold. 1391 */ 1392 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1393 em_txeof(sc); 1394 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1395 sc->no_tx_desc_avail1++; 1396 return (ENOBUFS); 1397 } 1398 } 1399 1400 /* 1401 * Map the packet for DMA. 1402 */ 1403 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1404 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1405 segs, &nsegs, BUS_DMA_NOWAIT); 1406 map = tx_buffer->map; 1407 if (error != 0) { 1408 sc->no_tx_dma_setup++; 1409 return (error); 1410 } 1411 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1412 1413 if (nsegs > sc->num_tx_desc_avail) { 1414 sc->no_tx_desc_avail2++; 1415 error = ENOBUFS; 1416 goto encap_fail; 1417 } 1418 1419 if (ifp->if_hwassist > 0) 1420 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1421 else 1422 txd_upper = txd_lower = 0; 1423 1424 /* Find out if we are in vlan mode. */ 1425 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1426 1427 /* 1428 * When operating in promiscuous mode, hardware encapsulation for 1429 * packets is disabled. This means we have to add the vlan 1430 * encapsulation in the driver, since it will have come down from the 1431 * VLAN layer with a tag instead of a VLAN header. 1432 */ 1433 if (mtag != NULL && sc->em_insert_vlan_header) { 1434 struct ether_vlan_header *evl; 1435 struct ether_header eh; 1436 1437 m_head = m_pullup(m_head, sizeof(eh)); 1438 if (m_head == NULL) { 1439 *m_headp = NULL; 1440 error = ENOBUFS; 1441 goto encap_fail; 1442 } 1443 eh = *mtod(m_head, struct ether_header *); 1444 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1445 if (m_head == NULL) { 1446 *m_headp = NULL; 1447 error = ENOBUFS; 1448 goto encap_fail; 1449 } 1450 m_head = m_pullup(m_head, sizeof(*evl)); 1451 if (m_head == NULL) { 1452 *m_headp = NULL; 1453 error = ENOBUFS; 1454 goto encap_fail; 1455 } 1456 evl = mtod(m_head, struct ether_vlan_header *); 1457 bcopy(&eh, evl, sizeof(*evl)); 1458 evl->evl_proto = evl->evl_encap_proto; 1459 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1460 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1461 m_tag_delete(m_head, mtag); 1462 mtag = NULL; 1463 *m_headp = m_head; 1464 } 1465 1466 i = sc->next_avail_tx_desc; 1467 if (sc->pcix_82544) { 1468 txd_saved = i; 1469 txd_used = 0; 1470 } 1471 for (j = 0; j < nsegs; j++) { 1472 /* If adapter is 82544 and on PCIX bus. */ 1473 if(sc->pcix_82544) { 1474 DESC_ARRAY desc_array; 1475 uint32_t array_elements, counter; 1476 1477 /* 1478 * Check the Address and Length combination and 1479 * split the data accordingly 1480 */ 1481 array_elements = em_fill_descriptors(segs[j].ds_addr, 1482 segs[j].ds_len, &desc_array); 1483 for (counter = 0; counter < array_elements; counter++) { 1484 if (txd_used == sc->num_tx_desc_avail) { 1485 sc->next_avail_tx_desc = txd_saved; 1486 sc->no_tx_desc_avail2++; 1487 error = ENOBUFS; 1488 goto encap_fail; 1489 } 1490 tx_buffer = &sc->tx_buffer_area[i]; 1491 current_tx_desc = &sc->tx_desc_base[i]; 1492 current_tx_desc->buffer_addr = htole64( 1493 desc_array.descriptor[counter].address); 1494 current_tx_desc->lower.data = htole32( 1495 (sc->txd_cmd | txd_lower | 1496 (uint16_t)desc_array.descriptor[counter].length)); 1497 current_tx_desc->upper.data = htole32((txd_upper)); 1498 if (++i == sc->num_tx_desc) 1499 i = 0; 1500 1501 tx_buffer->m_head = NULL; 1502 txd_used++; 1503 } 1504 } else { 1505 tx_buffer = &sc->tx_buffer_area[i]; 1506 current_tx_desc = &sc->tx_desc_base[i]; 1507 1508 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1509 current_tx_desc->lower.data = htole32( 1510 sc->txd_cmd | txd_lower | segs[j].ds_len); 1511 current_tx_desc->upper.data = htole32(txd_upper); 1512 1513 if (++i == sc->num_tx_desc) 1514 i = 0; 1515 1516 tx_buffer->m_head = NULL; 1517 } 1518 } 1519 1520 sc->next_avail_tx_desc = i; 1521 if (sc->pcix_82544) 1522 sc->num_tx_desc_avail -= txd_used; 1523 else 1524 sc->num_tx_desc_avail -= nsegs; 1525 1526 if (mtag != NULL) { 1527 /* Set the vlan id. */ 1528 current_tx_desc->upper.fields.special = 1529 htole16(VLAN_TAG_VALUE(mtag)); 1530 1531 /* Tell hardware to add tag. */ 1532 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1533 } 1534 1535 tx_buffer->m_head = m_head; 1536 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1537 1538 /* 1539 * Last Descriptor of Packet needs End Of Packet (EOP). 1540 */ 1541 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1542 1543 /* 1544 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1545 * that this frame is available to transmit. 1546 */ 1547 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1549 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1550 em_82547_move_tail_locked(sc); 1551 else { 1552 E1000_WRITE_REG(&sc->hw, TDT, i); 1553 if (sc->hw.mac_type == em_82547) 1554 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1555 } 1556 1557 return (0); 1558 1559encap_fail: 1560 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1561 return (error); 1562} 1563 1564/********************************************************************* 1565 * 1566 * 82547 workaround to avoid controller hang in half-duplex environment. 1567 * The workaround is to avoid queuing a large packet that would span 1568 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1569 * in this case. We do that only when FIFO is quiescent. 1570 * 1571 **********************************************************************/ 1572static void 1573em_82547_move_tail_locked(struct em_softc *sc) 1574{ 1575 uint16_t hw_tdt; 1576 uint16_t sw_tdt; 1577 struct em_tx_desc *tx_desc; 1578 uint16_t length = 0; 1579 boolean_t eop = 0; 1580 1581 EM_LOCK_ASSERT(sc); 1582 1583 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1584 sw_tdt = sc->next_avail_tx_desc; 1585 1586 while (hw_tdt != sw_tdt) { 1587 tx_desc = &sc->tx_desc_base[hw_tdt]; 1588 length += tx_desc->lower.flags.length; 1589 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1590 if(++hw_tdt == sc->num_tx_desc) 1591 hw_tdt = 0; 1592 1593 if (eop) { 1594 if (em_82547_fifo_workaround(sc, length)) { 1595 sc->tx_fifo_wrk_cnt++; 1596 callout_reset(&sc->tx_fifo_timer, 1, 1597 em_82547_move_tail, sc); 1598 break; 1599 } 1600 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1601 em_82547_update_fifo_head(sc, length); 1602 length = 0; 1603 } 1604 } 1605} 1606 1607static void 1608em_82547_move_tail(void *arg) 1609{ 1610 struct em_softc *sc = arg; 1611 1612 EM_LOCK(sc); 1613 em_82547_move_tail_locked(sc); 1614 EM_UNLOCK(sc); 1615} 1616 1617static int 1618em_82547_fifo_workaround(struct em_softc *sc, int len) 1619{ 1620 int fifo_space, fifo_pkt_len; 1621 1622 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1623 1624 if (sc->link_duplex == HALF_DUPLEX) { 1625 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1626 1627 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1628 if (em_82547_tx_fifo_reset(sc)) 1629 return (0); 1630 else 1631 return (1); 1632 } 1633 } 1634 1635 return (0); 1636} 1637 1638static void 1639em_82547_update_fifo_head(struct em_softc *sc, int len) 1640{ 1641 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1642 1643 /* tx_fifo_head is always 16 byte aligned */ 1644 sc->tx_fifo_head += fifo_pkt_len; 1645 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1646 sc->tx_fifo_head -= sc->tx_fifo_size; 1647 } 1648} 1649 1650 1651static int 1652em_82547_tx_fifo_reset(struct em_softc *sc) 1653{ 1654 uint32_t tctl; 1655 1656 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1657 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1658 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1659 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1660 1661 /* Disable TX unit */ 1662 tctl = E1000_READ_REG(&sc->hw, TCTL); 1663 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1664 1665 /* Reset FIFO pointers */ 1666 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1667 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1668 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1669 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1670 1671 /* Re-enable TX unit */ 1672 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1673 E1000_WRITE_FLUSH(&sc->hw); 1674 1675 sc->tx_fifo_head = 0; 1676 sc->tx_fifo_reset_cnt++; 1677 1678 return (TRUE); 1679 } 1680 else { 1681 return (FALSE); 1682 } 1683} 1684 1685static void 1686em_set_promisc(struct em_softc *sc) 1687{ 1688 struct ifnet *ifp = sc->ifp; 1689 uint32_t reg_rctl; 1690 1691 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1692 1693 if (ifp->if_flags & IFF_PROMISC) { 1694 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1695 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1696 /* Disable VLAN stripping in promiscous mode 1697 * This enables bridging of vlan tagged frames to occur 1698 * and also allows vlan tags to be seen in tcpdump 1699 */ 1700 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1701 em_disable_vlans(sc); 1702 sc->em_insert_vlan_header = 1; 1703 } else if (ifp->if_flags & IFF_ALLMULTI) { 1704 reg_rctl |= E1000_RCTL_MPE; 1705 reg_rctl &= ~E1000_RCTL_UPE; 1706 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1707 sc->em_insert_vlan_header = 0; 1708 } else 1709 sc->em_insert_vlan_header = 0; 1710} 1711 1712static void 1713em_disable_promisc(struct em_softc *sc) 1714{ 1715 struct ifnet *ifp = sc->ifp; 1716 uint32_t reg_rctl; 1717 1718 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1719 1720 reg_rctl &= (~E1000_RCTL_UPE); 1721 reg_rctl &= (~E1000_RCTL_MPE); 1722 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1723 1724 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1725 em_enable_vlans(sc); 1726 sc->em_insert_vlan_header = 0; 1727} 1728 1729 1730/********************************************************************* 1731 * Multicast Update 1732 * 1733 * This routine is called whenever multicast address list is updated. 1734 * 1735 **********************************************************************/ 1736 1737static void 1738em_set_multi(struct em_softc *sc) 1739{ 1740 struct ifnet *ifp = sc->ifp; 1741 struct ifmultiaddr *ifma; 1742 uint32_t reg_rctl = 0; 1743 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1744 int mcnt = 0; 1745 1746 IOCTL_DEBUGOUT("em_set_multi: begin"); 1747 1748 if (sc->hw.mac_type == em_82542_rev2_0) { 1749 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1750 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1751 em_pci_clear_mwi(&sc->hw); 1752 reg_rctl |= E1000_RCTL_RST; 1753 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1754 msec_delay(5); 1755 } 1756 1757 IF_ADDR_LOCK(ifp); 1758 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1759 if (ifma->ifma_addr->sa_family != AF_LINK) 1760 continue; 1761 1762 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1763 break; 1764 1765 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1766 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1767 mcnt++; 1768 } 1769 IF_ADDR_UNLOCK(ifp); 1770 1771 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1772 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1773 reg_rctl |= E1000_RCTL_MPE; 1774 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1775 } else 1776 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1777 1778 if (sc->hw.mac_type == em_82542_rev2_0) { 1779 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1780 reg_rctl &= ~E1000_RCTL_RST; 1781 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1782 msec_delay(5); 1783 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1784 em_pci_set_mwi(&sc->hw); 1785 } 1786} 1787 1788 1789/********************************************************************* 1790 * Timer routine 1791 * 1792 * This routine checks for link status and updates statistics. 1793 * 1794 **********************************************************************/ 1795 1796static void 1797em_local_timer(void *arg) 1798{ 1799 struct em_softc *sc = arg; 1800 struct ifnet *ifp = sc->ifp; 1801 1802 EM_LOCK(sc); 1803 1804 em_check_for_link(&sc->hw); 1805 em_update_link_status(sc); 1806 em_update_stats_counters(sc); 1807 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1808 em_print_hw_stats(sc); 1809 em_smartspeed(sc); 1810 1811 callout_reset(&sc->timer, hz, em_local_timer, sc); 1812 1813 EM_UNLOCK(sc); 1814} 1815 1816static void 1817em_update_link_status(struct em_softc *sc) 1818{ 1819 struct ifnet *ifp = sc->ifp; 1820 device_t dev = sc->dev; 1821 1822 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1823 if (sc->link_active == 0) { 1824 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1825 &sc->link_duplex); 1826 if (bootverbose) 1827 device_printf(dev, "Link is up %d Mbps %s\n", 1828 sc->link_speed, 1829 ((sc->link_duplex == FULL_DUPLEX) ? 1830 "Full Duplex" : "Half Duplex")); 1831 sc->link_active = 1; 1832 sc->smartspeed = 0; 1833 ifp->if_baudrate = sc->link_speed * 1000000; 1834 if_link_state_change(ifp, LINK_STATE_UP); 1835 } 1836 } else { 1837 if (sc->link_active == 1) { 1838 ifp->if_baudrate = sc->link_speed = 0; 1839 sc->link_duplex = 0; 1840 if (bootverbose) 1841 device_printf(dev, "Link is Down\n"); 1842 sc->link_active = 0; 1843 if_link_state_change(ifp, LINK_STATE_DOWN); 1844 } 1845 } 1846} 1847 1848/********************************************************************* 1849 * 1850 * This routine disables all traffic on the adapter by issuing a 1851 * global reset on the MAC and deallocates TX/RX buffers. 1852 * 1853 **********************************************************************/ 1854 1855static void 1856em_stop(void *arg) 1857{ 1858 struct em_softc *sc = arg; 1859 struct ifnet *ifp = sc->ifp; 1860 1861 EM_LOCK_ASSERT(sc); 1862 1863 INIT_DEBUGOUT("em_stop: begin"); 1864 1865 em_disable_intr(sc); 1866 em_reset_hw(&sc->hw); 1867 callout_stop(&sc->timer); 1868 callout_stop(&sc->tx_fifo_timer); 1869 em_free_transmit_structures(sc); 1870 em_free_receive_structures(sc); 1871 1872 /* Tell the stack that the interface is no longer active */ 1873 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1874} 1875 1876 1877/********************************************************************* 1878 * 1879 * Determine hardware revision. 1880 * 1881 **********************************************************************/ 1882static void 1883em_identify_hardware(struct em_softc *sc) 1884{ 1885 device_t dev = sc->dev; 1886 1887 /* Make sure our PCI config space has the necessary stuff set */ 1888 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1889 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1890 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1891 device_printf(dev, "Memory Access and/or Bus Master bits " 1892 "were not set!\n"); 1893 sc->hw.pci_cmd_word |= 1894 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1895 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1896 } 1897 1898 /* Save off the information about this board */ 1899 sc->hw.vendor_id = pci_get_vendor(dev); 1900 sc->hw.device_id = pci_get_device(dev); 1901 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1902 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1903 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1904 1905 /* Identify the MAC */ 1906 if (em_set_mac_type(&sc->hw)) 1907 device_printf(dev, "Unknown MAC Type\n"); 1908 1909 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1910 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1911 sc->hw.phy_init_script = TRUE; 1912} 1913 1914static int 1915em_allocate_pci_resources(struct em_softc *sc) 1916{ 1917 device_t dev = sc->dev; 1918 int val, rid; 1919 1920 rid = PCIR_BAR(0); 1921 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1922 &rid, RF_ACTIVE); 1923 if (sc->res_memory == NULL) { 1924 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1925 return (ENXIO); 1926 } 1927 sc->osdep.mem_bus_space_tag = 1928 rman_get_bustag(sc->res_memory); 1929 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1930 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1931 1932 if (sc->hw.mac_type > em_82543) { 1933 /* Figure our where our IO BAR is ? */ 1934 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1935 val = pci_read_config(dev, rid, 4); 1936 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1937 sc->io_rid = rid; 1938 break; 1939 } 1940 rid += 4; 1941 /* check for 64bit BAR */ 1942 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1943 rid += 4; 1944 } 1945 if (rid >= PCIR_CIS) { 1946 device_printf(dev, "Unable to locate IO BAR\n"); 1947 return (ENXIO); 1948 } 1949 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1950 &sc->io_rid, RF_ACTIVE); 1951 if (sc->res_ioport == NULL) { 1952 device_printf(dev, "Unable to allocate bus resource: " 1953 "ioport\n"); 1954 return (ENXIO); 1955 } 1956 sc->hw.io_base = 0; 1957 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1958 sc->osdep.io_bus_space_handle = 1959 rman_get_bushandle(sc->res_ioport); 1960 } 1961 1962 rid = 0x0; 1963 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1964 RF_SHAREABLE | RF_ACTIVE); 1965 if (sc->res_interrupt == NULL) { 1966 device_printf(dev, "Unable to allocate bus resource: " 1967 "interrupt\n"); 1968 return (ENXIO); 1969 } 1970 1971 sc->hw.back = &sc->osdep; 1972 1973 return (0); 1974} 1975 1976int 1977em_allocate_intr(struct em_softc *sc) 1978{ 1979 device_t dev = sc->dev; 1980 int error; 1981 1982 /* Manually turn off all interrupts */ 1983 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1984 1985 /* 1986 * Try allocating a fast interrupt and the associated deferred 1987 * processing contexts. If that doesn't work, try just using an 1988 * ithread. 1989 */ 1990#ifndef NO_EM_FASTINTR 1991 /* Init the deferred processing contexts. */ 1992 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1993 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1994 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1995 taskqueue_thread_enqueue, &sc->tq); 1996 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1997 device_get_nameunit(sc->dev)); 1998 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1999 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 2000 &sc->int_handler_tag)) != 0) { 2001 device_printf(dev, "Failed to register fast interrupt " 2002 "handler: %d\n", error); 2003 taskqueue_free(sc->tq); 2004 sc->tq = NULL; 2005 } 2006#endif 2007 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 2008 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 2009 &sc->int_handler_tag)) != 0) { 2010 device_printf(dev, "Failed to register interrupt handler"); 2011 return (error); 2012 } 2013 2014 em_enable_intr(sc); 2015 return (0); 2016} 2017 2018static void 2019em_free_intr(struct em_softc *sc) 2020{ 2021 device_t dev = sc->dev; 2022 2023 if (sc->res_interrupt != NULL) { 2024 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2025 sc->int_handler_tag = NULL; 2026 } 2027 if (sc->tq != NULL) { 2028 taskqueue_drain(sc->tq, &sc->rxtx_task); 2029 taskqueue_drain(taskqueue_fast, &sc->link_task); 2030 taskqueue_free(sc->tq); 2031 sc->tq = NULL; 2032 } 2033} 2034 2035static void 2036em_free_pci_resources(struct em_softc *sc) 2037{ 2038 device_t dev = sc->dev; 2039 2040 if (sc->res_interrupt != NULL) 2041 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2042 2043 if (sc->res_memory != NULL) 2044 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2045 sc->res_memory); 2046 2047 if (sc->res_ioport != NULL) 2048 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2049 sc->res_ioport); 2050} 2051 2052/********************************************************************* 2053 * 2054 * Initialize the hardware to a configuration as specified by the 2055 * adapter structure. The controller is reset, the EEPROM is 2056 * verified, the MAC address is set, then the shared initialization 2057 * routines are called. 2058 * 2059 **********************************************************************/ 2060static int 2061em_hardware_init(struct em_softc *sc) 2062{ 2063 device_t dev = sc->dev; 2064 uint16_t rx_buffer_size; 2065 2066 INIT_DEBUGOUT("em_hardware_init: begin"); 2067 /* Issue a global reset */ 2068 em_reset_hw(&sc->hw); 2069 2070 /* When hardware is reset, fifo_head is also reset */ 2071 sc->tx_fifo_head = 0; 2072 2073 /* Make sure we have a good EEPROM before we read from it */ 2074 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2075 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2076 return (EIO); 2077 } 2078 2079 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2080 device_printf(dev, "EEPROM read error while reading part " 2081 "number\n"); 2082 return (EIO); 2083 } 2084 2085 /* 2086 * These parameters control the automatic generation (Tx) and 2087 * response (Rx) to Ethernet PAUSE frames. 2088 * - High water mark should allow for at least two frames to be 2089 * received after sending an XOFF. 2090 * - Low water mark works best when it is very near the high water mark. 2091 * This allows the receiver to restart by sending XON when it has 2092 * drained a bit. Here we use an arbitary value of 1500 which will 2093 * restart after one full frame is pulled from the buffer. There 2094 * could be several smaller frames in the buffer and if so they will 2095 * not trigger the XON until their total number reduces the buffer 2096 * by 1500. 2097 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2098 */ 2099 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2100 2101 sc->hw.fc_high_water = rx_buffer_size - 2102 roundup2(sc->hw.max_frame_size, 1024); 2103 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2104 if (sc->hw.mac_type == em_80003es2lan) 2105 sc->hw.fc_pause_time = 0xFFFF; 2106 else 2107 sc->hw.fc_pause_time = 0x1000; 2108 sc->hw.fc_send_xon = TRUE; 2109 sc->hw.fc = em_fc_full; 2110 2111 if (em_init_hw(&sc->hw) < 0) { 2112 device_printf(dev, "Hardware Initialization Failed"); 2113 return (EIO); 2114 } 2115 2116 em_check_for_link(&sc->hw); 2117 2118 return (0); 2119} 2120 2121/********************************************************************* 2122 * 2123 * Setup networking device structure and register an interface. 2124 * 2125 **********************************************************************/ 2126static void 2127em_setup_interface(device_t dev, struct em_softc *sc) 2128{ 2129 struct ifnet *ifp; 2130 INIT_DEBUGOUT("em_setup_interface: begin"); 2131 2132 ifp = sc->ifp = if_alloc(IFT_ETHER); 2133 if (ifp == NULL) 2134 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2135 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2136 ifp->if_mtu = ETHERMTU; 2137 ifp->if_init = em_init; 2138 ifp->if_softc = sc; 2139 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2140 ifp->if_ioctl = em_ioctl; 2141 ifp->if_start = em_start; 2142 ifp->if_watchdog = em_watchdog; 2143 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2144 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2145 IFQ_SET_READY(&ifp->if_snd); 2146 2147 ether_ifattach(ifp, sc->hw.mac_addr); 2148 2149 ifp->if_capabilities = ifp->if_capenable = 0; 2150 2151 if (sc->hw.mac_type >= em_82543) { 2152 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2153 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2154 } 2155 2156 /* 2157 * Tell the upper layer(s) we support long frames. 2158 */ 2159 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2160 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2161 ifp->if_capenable |= IFCAP_VLAN_MTU; 2162 2163#ifdef DEVICE_POLLING 2164 ifp->if_capabilities |= IFCAP_POLLING; 2165#endif 2166 2167 /* 2168 * Specify the media types supported by this adapter and register 2169 * callbacks to update media and link information 2170 */ 2171 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2172 if (sc->hw.media_type == em_media_type_fiber) { 2173 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2174 0, NULL); 2175 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2176 0, NULL); 2177 } else { 2178 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2179 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2180 0, NULL); 2181 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2182 0, NULL); 2183 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2184 0, NULL); 2185 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2186 0, NULL); 2187 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2188 } 2189 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2190 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2191} 2192 2193 2194/********************************************************************* 2195 * 2196 * Workaround for SmartSpeed on 82541 and 82547 controllers 2197 * 2198 **********************************************************************/ 2199static void 2200em_smartspeed(struct em_softc *sc) 2201{ 2202 uint16_t phy_tmp; 2203 2204 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2205 sc->hw.autoneg == 0 || 2206 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2207 return; 2208 2209 if (sc->smartspeed == 0) { 2210 /* If Master/Slave config fault is asserted twice, 2211 * we assume back-to-back */ 2212 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2213 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2214 return; 2215 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2216 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2217 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2218 if(phy_tmp & CR_1000T_MS_ENABLE) { 2219 phy_tmp &= ~CR_1000T_MS_ENABLE; 2220 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2221 phy_tmp); 2222 sc->smartspeed++; 2223 if(sc->hw.autoneg && 2224 !em_phy_setup_autoneg(&sc->hw) && 2225 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2226 &phy_tmp)) { 2227 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2228 MII_CR_RESTART_AUTO_NEG); 2229 em_write_phy_reg(&sc->hw, PHY_CTRL, 2230 phy_tmp); 2231 } 2232 } 2233 } 2234 return; 2235 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2236 /* If still no link, perhaps using 2/3 pair cable */ 2237 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2238 phy_tmp |= CR_1000T_MS_ENABLE; 2239 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2240 if(sc->hw.autoneg && 2241 !em_phy_setup_autoneg(&sc->hw) && 2242 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2243 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2244 MII_CR_RESTART_AUTO_NEG); 2245 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2246 } 2247 } 2248 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2249 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2250 sc->smartspeed = 0; 2251} 2252 2253 2254/* 2255 * Manage DMA'able memory. 2256 */ 2257static void 2258em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2259{ 2260 if (error) 2261 return; 2262 *(bus_addr_t *) arg = segs[0].ds_addr; 2263} 2264 2265static int 2266em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2267 int mapflags) 2268{ 2269 int error; 2270 2271 error = bus_dma_tag_create(NULL, /* parent */ 2272 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2273 BUS_SPACE_MAXADDR, /* lowaddr */ 2274 BUS_SPACE_MAXADDR, /* highaddr */ 2275 NULL, NULL, /* filter, filterarg */ 2276 size, /* maxsize */ 2277 1, /* nsegments */ 2278 size, /* maxsegsize */ 2279 0, /* flags */ 2280 NULL, /* lockfunc */ 2281 NULL, /* lockarg */ 2282 &dma->dma_tag); 2283 if (error) { 2284 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2285 __func__, error); 2286 goto fail_0; 2287 } 2288 2289 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2290 BUS_DMA_NOWAIT, &dma->dma_map); 2291 if (error) { 2292 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2293 __func__, (uintmax_t)size, error); 2294 goto fail_2; 2295 } 2296 2297 dma->dma_paddr = 0; 2298 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2299 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2300 if (error || dma->dma_paddr == 0) { 2301 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2302 __func__, error); 2303 goto fail_3; 2304 } 2305 2306 return (0); 2307 2308fail_3: 2309 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2310fail_2: 2311 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2312 bus_dma_tag_destroy(dma->dma_tag); 2313fail_0: 2314 dma->dma_map = NULL; 2315 dma->dma_tag = NULL; 2316 2317 return (error); 2318} 2319 2320static void 2321em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2322{ 2323 if (dma->dma_tag == NULL) 2324 return; 2325 if (dma->dma_map != NULL) { 2326 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2328 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2329 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2330 dma->dma_map = NULL; 2331 } 2332 bus_dma_tag_destroy(dma->dma_tag); 2333 dma->dma_tag = NULL; 2334} 2335 2336 2337/********************************************************************* 2338 * 2339 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2340 * the information needed to transmit a packet on the wire. 2341 * 2342 **********************************************************************/ 2343static int 2344em_allocate_transmit_structures(struct em_softc *sc) 2345{ 2346 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2347 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2348 if (sc->tx_buffer_area == NULL) { 2349 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2350 return (ENOMEM); 2351 } 2352 2353 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2354 2355 return (0); 2356} 2357 2358/********************************************************************* 2359 * 2360 * Allocate and initialize transmit structures. 2361 * 2362 **********************************************************************/ 2363static int 2364em_setup_transmit_structures(struct em_softc *sc) 2365{ 2366 device_t dev = sc->dev; 2367 struct em_buffer *tx_buffer; 2368 bus_size_t size; 2369 int error, i; 2370 2371 /* 2372 * Setup DMA descriptor areas. 2373 */ 2374 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2375 if ((error = bus_dma_tag_create(NULL, /* parent */ 2376 1, 0, /* alignment, bounds */ 2377 BUS_SPACE_MAXADDR, /* lowaddr */ 2378 BUS_SPACE_MAXADDR, /* highaddr */ 2379 NULL, NULL, /* filter, filterarg */ 2380 size, /* maxsize */ 2381 EM_MAX_SCATTER, /* nsegments */ 2382 size, /* maxsegsize */ 2383 0, /* flags */ 2384 NULL, /* lockfunc */ 2385 NULL, /* lockarg */ 2386 &sc->txtag)) != 0) { 2387 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2388 goto fail; 2389 } 2390 2391 if ((error = em_allocate_transmit_structures(sc)) != 0) 2392 goto fail; 2393 2394 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2395 tx_buffer = sc->tx_buffer_area; 2396 for (i = 0; i < sc->num_tx_desc; i++) { 2397 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2398 if (error != 0) { 2399 device_printf(dev, "Unable to create TX DMA map\n"); 2400 goto fail; 2401 } 2402 tx_buffer++; 2403 } 2404 2405 sc->next_avail_tx_desc = 0; 2406 sc->oldest_used_tx_desc = 0; 2407 2408 /* Set number of descriptors available */ 2409 sc->num_tx_desc_avail = sc->num_tx_desc; 2410 2411 /* Set checksum context */ 2412 sc->active_checksum_context = OFFLOAD_NONE; 2413 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2415 2416 return (0); 2417 2418fail: 2419 em_free_transmit_structures(sc); 2420 return (error); 2421} 2422 2423/********************************************************************* 2424 * 2425 * Enable transmit unit. 2426 * 2427 **********************************************************************/ 2428static void 2429em_initialize_transmit_unit(struct em_softc *sc) 2430{ 2431 uint32_t reg_tctl, tarc; 2432 uint32_t reg_tipg = 0; 2433 uint64_t bus_addr; 2434 2435 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2436 /* Setup the Base and Length of the Tx Descriptor Ring */ 2437 bus_addr = sc->txdma.dma_paddr; 2438 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2439 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2440 E1000_WRITE_REG(&sc->hw, TDLEN, 2441 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2442 2443 /* Setup the HW Tx Head and Tail descriptor pointers */ 2444 E1000_WRITE_REG(&sc->hw, TDH, 0); 2445 E1000_WRITE_REG(&sc->hw, TDT, 0); 2446 2447 2448 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2449 E1000_READ_REG(&sc->hw, TDLEN)); 2450 2451 /* Set the default values for the Tx Inter Packet Gap timer */ 2452 switch (sc->hw.mac_type) { 2453 case em_82542_rev2_0: 2454 case em_82542_rev2_1: 2455 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2456 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2457 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2458 break; 2459 case em_80003es2lan: 2460 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2461 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2462 E1000_TIPG_IPGR2_SHIFT; 2463 break; 2464 default: 2465 if (sc->hw.media_type == em_media_type_fiber) 2466 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2467 else 2468 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2469 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2470 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2471 } 2472 2473 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2474 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2475 if(sc->hw.mac_type >= em_82540) 2476 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2477 2478 /* Program the Transmit Control Register */ 2479 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2480 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2481 if (sc->hw.mac_type >= em_82571) 2482 reg_tctl |= E1000_TCTL_MULR; 2483 if (sc->link_duplex == 1) { 2484 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2485 } else { 2486 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2487 } 2488 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2489 2490 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) { 2491 tarc = E1000_READ_REG(&sc->hw, TARC0); 2492 tarc |= ((1 << 25) | (1 << 21)); 2493 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2494 tarc = E1000_READ_REG(&sc->hw, TARC1); 2495 tarc |= (1 << 25); 2496 if (reg_tctl & E1000_TCTL_MULR) 2497 tarc &= ~(1 << 28); 2498 else 2499 tarc |= (1 << 28); 2500 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2501 } else if (sc->hw.mac_type == em_80003es2lan) { 2502 tarc = E1000_READ_REG(&sc->hw, TARC0); 2503 tarc |= 1; 2504 if (sc->hw.media_type == em_media_type_internal_serdes) 2505 tarc |= (1 << 20); 2506 E1000_WRITE_REG(&sc->hw, TARC0, tarc); 2507 tarc = E1000_READ_REG(&sc->hw, TARC1); 2508 tarc |= 1; 2509 E1000_WRITE_REG(&sc->hw, TARC1, tarc); 2510 } 2511 2512 /* Setup Transmit Descriptor Settings for this adapter */ 2513 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2514 2515 if (sc->tx_int_delay.value > 0) 2516 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2517} 2518 2519/********************************************************************* 2520 * 2521 * Free all transmit related data structures. 2522 * 2523 **********************************************************************/ 2524static void 2525em_free_transmit_structures(struct em_softc *sc) 2526{ 2527 struct em_buffer *tx_buffer; 2528 int i; 2529 2530 INIT_DEBUGOUT("free_transmit_structures: begin"); 2531 2532 if (sc->tx_buffer_area != NULL) { 2533 tx_buffer = sc->tx_buffer_area; 2534 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2535 if (tx_buffer->m_head != NULL) { 2536 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2537 BUS_DMASYNC_POSTWRITE); 2538 bus_dmamap_unload(sc->txtag, 2539 tx_buffer->map); 2540 m_freem(tx_buffer->m_head); 2541 tx_buffer->m_head = NULL; 2542 } else if (tx_buffer->map != NULL) 2543 bus_dmamap_unload(sc->txtag, 2544 tx_buffer->map); 2545 if (tx_buffer->map != NULL) { 2546 bus_dmamap_destroy(sc->txtag, 2547 tx_buffer->map); 2548 tx_buffer->map = NULL; 2549 } 2550 } 2551 } 2552 if (sc->tx_buffer_area != NULL) { 2553 free(sc->tx_buffer_area, M_DEVBUF); 2554 sc->tx_buffer_area = NULL; 2555 } 2556 if (sc->txtag != NULL) { 2557 bus_dma_tag_destroy(sc->txtag); 2558 sc->txtag = NULL; 2559 } 2560} 2561 2562/********************************************************************* 2563 * 2564 * The offload context needs to be set when we transfer the first 2565 * packet of a particular protocol (TCP/UDP). We change the 2566 * context only if the protocol type changes. 2567 * 2568 **********************************************************************/ 2569static void 2570em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2571 uint32_t *txd_upper, uint32_t *txd_lower) 2572{ 2573 struct em_context_desc *TXD; 2574 struct em_buffer *tx_buffer; 2575 int curr_txd; 2576 2577 if (mp->m_pkthdr.csum_flags) { 2578 2579 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2580 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2581 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2582 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2583 return; 2584 else 2585 sc->active_checksum_context = OFFLOAD_TCP_IP; 2586 2587 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2588 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2589 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2590 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2591 return; 2592 else 2593 sc->active_checksum_context = OFFLOAD_UDP_IP; 2594 } else { 2595 *txd_upper = 0; 2596 *txd_lower = 0; 2597 return; 2598 } 2599 } else { 2600 *txd_upper = 0; 2601 *txd_lower = 0; 2602 return; 2603 } 2604 2605 /* If we reach this point, the checksum offload context 2606 * needs to be reset. 2607 */ 2608 curr_txd = sc->next_avail_tx_desc; 2609 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2610 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2611 2612 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2613 TXD->lower_setup.ip_fields.ipcso = 2614 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2615 TXD->lower_setup.ip_fields.ipcse = 2616 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2617 2618 TXD->upper_setup.tcp_fields.tucss = 2619 ETHER_HDR_LEN + sizeof(struct ip); 2620 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2621 2622 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2623 TXD->upper_setup.tcp_fields.tucso = 2624 ETHER_HDR_LEN + sizeof(struct ip) + 2625 offsetof(struct tcphdr, th_sum); 2626 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2627 TXD->upper_setup.tcp_fields.tucso = 2628 ETHER_HDR_LEN + sizeof(struct ip) + 2629 offsetof(struct udphdr, uh_sum); 2630 } 2631 2632 TXD->tcp_seg_setup.data = htole32(0); 2633 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2634 2635 tx_buffer->m_head = NULL; 2636 2637 if (++curr_txd == sc->num_tx_desc) 2638 curr_txd = 0; 2639 2640 sc->num_tx_desc_avail--; 2641 sc->next_avail_tx_desc = curr_txd; 2642} 2643 2644/********************************************************************** 2645 * 2646 * Examine each tx_buffer in the used queue. If the hardware is done 2647 * processing the packet then free associated resources. The 2648 * tx_buffer is put back on the free queue. 2649 * 2650 **********************************************************************/ 2651static void 2652em_txeof(struct em_softc *sc) 2653{ 2654 int i, num_avail; 2655 struct em_buffer *tx_buffer; 2656 struct em_tx_desc *tx_desc; 2657 struct ifnet *ifp = sc->ifp; 2658 2659 EM_LOCK_ASSERT(sc); 2660 2661 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2662 return; 2663 2664 num_avail = sc->num_tx_desc_avail; 2665 i = sc->oldest_used_tx_desc; 2666 2667 tx_buffer = &sc->tx_buffer_area[i]; 2668 tx_desc = &sc->tx_desc_base[i]; 2669 2670 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2671 BUS_DMASYNC_POSTREAD); 2672 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2673 2674 tx_desc->upper.data = 0; 2675 num_avail++; 2676 2677 if (tx_buffer->m_head) { 2678 ifp->if_opackets++; 2679 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2680 BUS_DMASYNC_POSTWRITE); 2681 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2682 2683 m_freem(tx_buffer->m_head); 2684 tx_buffer->m_head = NULL; 2685 } 2686 2687 if (++i == sc->num_tx_desc) 2688 i = 0; 2689 2690 tx_buffer = &sc->tx_buffer_area[i]; 2691 tx_desc = &sc->tx_desc_base[i]; 2692 } 2693 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2695 2696 sc->oldest_used_tx_desc = i; 2697 2698 /* 2699 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2700 * that it is OK to send packets. 2701 * If there are no pending descriptors, clear the timeout. Otherwise, 2702 * if some descriptors have been freed, restart the timeout. 2703 */ 2704 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2705 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2706 if (num_avail == sc->num_tx_desc) 2707 ifp->if_timer = 0; 2708 else if (num_avail != sc->num_tx_desc_avail) 2709 ifp->if_timer = EM_TX_TIMEOUT; 2710 } 2711 sc->num_tx_desc_avail = num_avail; 2712} 2713 2714/********************************************************************* 2715 * 2716 * Get a buffer from system mbuf buffer pool. 2717 * 2718 **********************************************************************/ 2719static int 2720em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2721{ 2722 struct ifnet *ifp = sc->ifp; 2723 bus_dma_segment_t segs[1]; 2724 struct em_buffer *rx_buffer; 2725 int error, nsegs; 2726 2727 if (mp == NULL) { 2728 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2729 if (mp == NULL) { 2730 sc->mbuf_cluster_failed++; 2731 return (ENOBUFS); 2732 } 2733 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2734 } else { 2735 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2736 mp->m_data = mp->m_ext.ext_buf; 2737 mp->m_next = NULL; 2738 } 2739 2740 if (ifp->if_mtu <= ETHERMTU) 2741 m_adj(mp, ETHER_ALIGN); 2742 2743 rx_buffer = &sc->rx_buffer_area[i]; 2744 2745 /* 2746 * Using memory from the mbuf cluster pool, invoke the 2747 * bus_dma machinery to arrange the memory mapping. 2748 */ 2749 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2750 mp, segs, &nsegs, 0); 2751 if (error != 0) { 2752 m_free(mp); 2753 return (error); 2754 } 2755 /* If nsegs is wrong then the stack is corrupt. */ 2756 KASSERT(nsegs == 1, ("Too many segments returned!")); 2757 rx_buffer->m_head = mp; 2758 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2759 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2760 2761 return (0); 2762} 2763 2764/********************************************************************* 2765 * 2766 * Allocate memory for rx_buffer structures. Since we use one 2767 * rx_buffer per received packet, the maximum number of rx_buffer's 2768 * that we'll need is equal to the number of receive descriptors 2769 * that we've allocated. 2770 * 2771 **********************************************************************/ 2772static int 2773em_allocate_receive_structures(struct em_softc *sc) 2774{ 2775 device_t dev = sc->dev; 2776 struct em_buffer *rx_buffer; 2777 int i, error; 2778 2779 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2780 M_DEVBUF, M_NOWAIT); 2781 if (sc->rx_buffer_area == NULL) { 2782 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2783 return (ENOMEM); 2784 } 2785 2786 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2787 2788 error = bus_dma_tag_create(NULL, /* parent */ 2789 1, 0, /* alignment, bounds */ 2790 BUS_SPACE_MAXADDR, /* lowaddr */ 2791 BUS_SPACE_MAXADDR, /* highaddr */ 2792 NULL, NULL, /* filter, filterarg */ 2793 MCLBYTES, /* maxsize */ 2794 1, /* nsegments */ 2795 MCLBYTES, /* maxsegsize */ 2796 BUS_DMA_ALLOCNOW, /* flags */ 2797 NULL, /* lockfunc */ 2798 NULL, /* lockarg */ 2799 &sc->rxtag); 2800 if (error) { 2801 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2802 __func__, error); 2803 goto fail; 2804 } 2805 2806 rx_buffer = sc->rx_buffer_area; 2807 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2808 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2809 &rx_buffer->map); 2810 if (error) { 2811 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2812 __func__, error); 2813 goto fail; 2814 } 2815 } 2816 2817 for (i = 0; i < sc->num_rx_desc; i++) { 2818 error = em_get_buf(i, sc, NULL); 2819 if (error) 2820 goto fail; 2821 } 2822 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2823 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2824 2825 return (0); 2826 2827fail: 2828 em_free_receive_structures(sc); 2829 return (error); 2830} 2831 2832/********************************************************************* 2833 * 2834 * Allocate and initialize receive structures. 2835 * 2836 **********************************************************************/ 2837static int 2838em_setup_receive_structures(struct em_softc *sc) 2839{ 2840 int error; 2841 2842 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2843 2844 if ((error = em_allocate_receive_structures(sc)) != 0) 2845 return (error); 2846 2847 /* Setup our descriptor pointers */ 2848 sc->next_rx_desc_to_check = 0; 2849 2850 return (0); 2851} 2852 2853/********************************************************************* 2854 * 2855 * Enable receive unit. 2856 * 2857 **********************************************************************/ 2858static void 2859em_initialize_receive_unit(struct em_softc *sc) 2860{ 2861 struct ifnet *ifp = sc->ifp; 2862 uint64_t bus_addr; 2863 uint32_t reg_rctl; 2864 uint32_t reg_rxcsum; 2865 2866 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2867 2868 /* 2869 * Make sure receives are disabled while setting 2870 * up the descriptor ring 2871 */ 2872 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2873 2874 /* Set the Receive Delay Timer Register */ 2875 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2876 2877 if(sc->hw.mac_type >= em_82540) { 2878 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2879 2880 /* 2881 * Set the interrupt throttling rate. Value is calculated 2882 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2883 */ 2884#define MAX_INTS_PER_SEC 8000 2885#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2886 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2887 } 2888 2889 /* Setup the Base and Length of the Rx Descriptor Ring */ 2890 bus_addr = sc->rxdma.dma_paddr; 2891 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2892 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2893 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2894 sizeof(struct em_rx_desc)); 2895 2896 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2897 E1000_WRITE_REG(&sc->hw, RDH, 0); 2898 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2899 2900 /* Setup the Receive Control Register */ 2901 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2902 E1000_RCTL_RDMTS_HALF | 2903 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2904 2905 if (sc->hw.tbi_compatibility_on == TRUE) 2906 reg_rctl |= E1000_RCTL_SBP; 2907 2908 2909 switch (sc->rx_buffer_len) { 2910 default: 2911 case EM_RXBUFFER_2048: 2912 reg_rctl |= E1000_RCTL_SZ_2048; 2913 break; 2914 case EM_RXBUFFER_4096: 2915 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2916 break; 2917 case EM_RXBUFFER_8192: 2918 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2919 break; 2920 case EM_RXBUFFER_16384: 2921 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2922 break; 2923 } 2924 2925 if (ifp->if_mtu > ETHERMTU) 2926 reg_rctl |= E1000_RCTL_LPE; 2927 2928 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2929 if ((sc->hw.mac_type >= em_82543) && 2930 (ifp->if_capenable & IFCAP_RXCSUM)) { 2931 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2932 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2933 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2934 } 2935 2936 /* Enable Receives */ 2937 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2938} 2939 2940/********************************************************************* 2941 * 2942 * Free receive related data structures. 2943 * 2944 **********************************************************************/ 2945static void 2946em_free_receive_structures(struct em_softc *sc) 2947{ 2948 struct em_buffer *rx_buffer; 2949 int i; 2950 2951 INIT_DEBUGOUT("free_receive_structures: begin"); 2952 2953 if (sc->rx_buffer_area != NULL) { 2954 rx_buffer = sc->rx_buffer_area; 2955 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2956 if (rx_buffer->m_head != NULL) { 2957 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2958 BUS_DMASYNC_POSTREAD); 2959 bus_dmamap_unload(sc->rxtag, 2960 rx_buffer->map); 2961 m_freem(rx_buffer->m_head); 2962 rx_buffer->m_head = NULL; 2963 } else if (rx_buffer->map != NULL) 2964 bus_dmamap_unload(sc->rxtag, 2965 rx_buffer->map); 2966 if (rx_buffer->map != NULL) { 2967 bus_dmamap_destroy(sc->rxtag, 2968 rx_buffer->map); 2969 rx_buffer->map = NULL; 2970 } 2971 } 2972 } 2973 if (sc->rx_buffer_area != NULL) { 2974 free(sc->rx_buffer_area, M_DEVBUF); 2975 sc->rx_buffer_area = NULL; 2976 } 2977 if (sc->rxtag != NULL) { 2978 bus_dma_tag_destroy(sc->rxtag); 2979 sc->rxtag = NULL; 2980 } 2981} 2982 2983/********************************************************************* 2984 * 2985 * This routine executes in interrupt context. It replenishes 2986 * the mbufs in the descriptor and sends data which has been 2987 * dma'ed into host memory to upper layer. 2988 * 2989 * We loop at most count times if count is > 0, or until done if 2990 * count < 0. 2991 * 2992 *********************************************************************/ 2993static int 2994em_rxeof(struct em_softc *sc, int count) 2995{ 2996 struct ifnet *ifp; 2997 struct mbuf *mp; 2998 uint8_t accept_frame = 0; 2999 uint8_t eop = 0; 3000 uint16_t len, desc_len, prev_len_adj; 3001 int i; 3002 3003 /* Pointer to the receive descriptor being examined. */ 3004 struct em_rx_desc *current_desc; 3005 3006 ifp = sc->ifp; 3007 i = sc->next_rx_desc_to_check; 3008 current_desc = &sc->rx_desc_base[i]; 3009 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3010 BUS_DMASYNC_POSTREAD); 3011 3012 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3013 return (0); 3014 3015 while ((current_desc->status & E1000_RXD_STAT_DD) && 3016 (count != 0) && 3017 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3018 struct mbuf *m = NULL; 3019 3020 mp = sc->rx_buffer_area[i].m_head; 3021 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3022 BUS_DMASYNC_POSTREAD); 3023 bus_dmamap_unload(sc->rxtag, 3024 sc->rx_buffer_area[i].map); 3025 3026 accept_frame = 1; 3027 prev_len_adj = 0; 3028 desc_len = le16toh(current_desc->length); 3029 if (current_desc->status & E1000_RXD_STAT_EOP) { 3030 count--; 3031 eop = 1; 3032 if (desc_len < ETHER_CRC_LEN) { 3033 len = 0; 3034 prev_len_adj = ETHER_CRC_LEN - desc_len; 3035 } else 3036 len = desc_len - ETHER_CRC_LEN; 3037 } else { 3038 eop = 0; 3039 len = desc_len; 3040 } 3041 3042 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3043 uint8_t last_byte; 3044 uint32_t pkt_len = desc_len; 3045 3046 if (sc->fmp != NULL) 3047 pkt_len += sc->fmp->m_pkthdr.len; 3048 3049 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3050 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3051 current_desc->errors, 3052 pkt_len, last_byte)) { 3053 em_tbi_adjust_stats(&sc->hw, 3054 &sc->stats, pkt_len, 3055 sc->hw.mac_addr); 3056 if (len > 0) 3057 len--; 3058 } else 3059 accept_frame = 0; 3060 } 3061 3062 if (accept_frame) { 3063 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3064 sc->dropped_pkts++; 3065 em_get_buf(i, sc, mp); 3066 if (sc->fmp != NULL) 3067 m_freem(sc->fmp); 3068 sc->fmp = NULL; 3069 sc->lmp = NULL; 3070 break; 3071 } 3072 3073 /* Assign correct length to the current fragment */ 3074 mp->m_len = len; 3075 3076 if (sc->fmp == NULL) { 3077 mp->m_pkthdr.len = len; 3078 sc->fmp = mp; /* Store the first mbuf */ 3079 sc->lmp = mp; 3080 } else { 3081 /* Chain mbuf's together */ 3082 mp->m_flags &= ~M_PKTHDR; 3083 /* 3084 * Adjust length of previous mbuf in chain if 3085 * we received less than 4 bytes in the last 3086 * descriptor. 3087 */ 3088 if (prev_len_adj > 0) { 3089 sc->lmp->m_len -= prev_len_adj; 3090 sc->fmp->m_pkthdr.len -= 3091 prev_len_adj; 3092 } 3093 sc->lmp->m_next = mp; 3094 sc->lmp = sc->lmp->m_next; 3095 sc->fmp->m_pkthdr.len += len; 3096 } 3097 3098 if (eop) { 3099 sc->fmp->m_pkthdr.rcvif = ifp; 3100 ifp->if_ipackets++; 3101 em_receive_checksum(sc, current_desc, 3102 sc->fmp); 3103#ifndef __NO_STRICT_ALIGNMENT 3104 if (ifp->if_mtu > ETHERMTU && 3105 em_fixup_rx(sc) != 0) 3106 goto skip; 3107#endif 3108 if (current_desc->status & E1000_RXD_STAT_VP) 3109 VLAN_INPUT_TAG(ifp, sc->fmp, 3110 (le16toh(current_desc->special) & 3111 E1000_RXD_SPC_VLAN_MASK)); 3112#ifndef __NO_STRICT_ALIGNMENT 3113skip: 3114#endif 3115 m = sc->fmp; 3116 sc->fmp = NULL; 3117 sc->lmp = NULL; 3118 } 3119 } else { 3120 sc->dropped_pkts++; 3121 em_get_buf(i, sc, mp); 3122 if (sc->fmp != NULL) 3123 m_freem(sc->fmp); 3124 sc->fmp = NULL; 3125 sc->lmp = NULL; 3126 } 3127 3128 /* Zero out the receive descriptors status. */ 3129 current_desc->status = 0; 3130 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3131 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3132 3133 /* Advance our pointers to the next descriptor. */ 3134 if (++i == sc->num_rx_desc) 3135 i = 0; 3136 if (m != NULL) { 3137 sc->next_rx_desc_to_check = i; 3138 (*ifp->if_input)(ifp, m); 3139 i = sc->next_rx_desc_to_check; 3140 } 3141 current_desc = &sc->rx_desc_base[i]; 3142 } 3143 sc->next_rx_desc_to_check = i; 3144 3145 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3146 if (--i < 0) 3147 i = sc->num_rx_desc - 1; 3148 E1000_WRITE_REG(&sc->hw, RDT, i); 3149 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3150 return (0); 3151 3152 return (1); 3153} 3154 3155#ifndef __NO_STRICT_ALIGNMENT 3156/* 3157 * When jumbo frames are enabled we should realign entire payload on 3158 * architecures with strict alignment. This is serious design mistake of 8254x 3159 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3160 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3161 * payload. On architecures without strict alignment restrictions 8254x still 3162 * performs unaligned memory access which would reduce the performance too. 3163 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3164 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3165 * existing mbuf chain. 3166 * 3167 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3168 * not used at all on architectures with strict alignment. 3169 */ 3170static int 3171em_fixup_rx(struct em_softc *sc) 3172{ 3173 struct mbuf *m, *n; 3174 int error; 3175 3176 error = 0; 3177 m = sc->fmp; 3178 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3179 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3180 m->m_data += ETHER_HDR_LEN; 3181 } else { 3182 MGETHDR(n, M_DONTWAIT, MT_DATA); 3183 if (n != NULL) { 3184 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3185 m->m_data += ETHER_HDR_LEN; 3186 m->m_len -= ETHER_HDR_LEN; 3187 n->m_len = ETHER_HDR_LEN; 3188 M_MOVE_PKTHDR(n, m); 3189 n->m_next = m; 3190 sc->fmp = n; 3191 } else { 3192 sc->dropped_pkts++; 3193 m_freem(sc->fmp); 3194 sc->fmp = NULL; 3195 error = ENOMEM; 3196 } 3197 } 3198 3199 return (error); 3200} 3201#endif 3202 3203/********************************************************************* 3204 * 3205 * Verify that the hardware indicated that the checksum is valid. 3206 * Inform the stack about the status of checksum so that stack 3207 * doesn't spend time verifying the checksum. 3208 * 3209 *********************************************************************/ 3210static void 3211em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3212 struct mbuf *mp) 3213{ 3214 /* 82543 or newer only */ 3215 if ((sc->hw.mac_type < em_82543) || 3216 /* Ignore Checksum bit is set */ 3217 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3218 mp->m_pkthdr.csum_flags = 0; 3219 return; 3220 } 3221 3222 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3223 /* Did it pass? */ 3224 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3225 /* IP Checksum Good */ 3226 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3227 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3228 3229 } else { 3230 mp->m_pkthdr.csum_flags = 0; 3231 } 3232 } 3233 3234 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3235 /* Did it pass? */ 3236 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3237 mp->m_pkthdr.csum_flags |= 3238 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3239 mp->m_pkthdr.csum_data = htons(0xffff); 3240 } 3241 } 3242} 3243 3244 3245static void 3246em_enable_vlans(struct em_softc *sc) 3247{ 3248 uint32_t ctrl; 3249 3250 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3251 3252 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3253 ctrl |= E1000_CTRL_VME; 3254 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3255} 3256 3257static void 3258em_disable_vlans(struct em_softc *sc) 3259{ 3260 uint32_t ctrl; 3261 3262 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3263 ctrl &= ~E1000_CTRL_VME; 3264 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3265} 3266 3267static void 3268em_enable_intr(struct em_softc *sc) 3269{ 3270 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3271} 3272 3273static void 3274em_disable_intr(struct em_softc *sc) 3275{ 3276 /* 3277 * The first version of 82542 had an errata where when link was forced 3278 * it would stay up even up even if the cable was disconnected. 3279 * Sequence errors were used to detect the disconnect and then the 3280 * driver would unforce the link. This code in the in the ISR. For this 3281 * to work correctly the Sequence error interrupt had to be enabled 3282 * all the time. 3283 */ 3284 3285 if (sc->hw.mac_type == em_82542_rev2_0) 3286 E1000_WRITE_REG(&sc->hw, IMC, 3287 (0xffffffff & ~E1000_IMC_RXSEQ)); 3288 else 3289 E1000_WRITE_REG(&sc->hw, IMC, 3290 0xffffffff); 3291} 3292 3293static int 3294em_is_valid_ether_addr(uint8_t *addr) 3295{ 3296 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3297 3298 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3299 return (FALSE); 3300 } 3301 3302 return (TRUE); 3303} 3304 3305void 3306em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3307{ 3308 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3309} 3310 3311void 3312em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3313{ 3314 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3315} 3316 3317void 3318em_pci_set_mwi(struct em_hw *hw) 3319{ 3320 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3321 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3322} 3323 3324void 3325em_pci_clear_mwi(struct em_hw *hw) 3326{ 3327 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3328 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3329} 3330 3331/********************************************************************* 3332* 82544 Coexistence issue workaround. 3333* There are 2 issues. 3334* 1. Transmit Hang issue. 3335* To detect this issue, following equation can be used... 3336* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3337* If SUM[3:0] is in between 1 to 4, we will have this issue. 3338* 3339* 2. DAC issue. 3340* To detect this issue, following equation can be used... 3341* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3342* If SUM[3:0] is in between 9 to c, we will have this issue. 3343* 3344* 3345* WORKAROUND: 3346* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3347* 3348*** *********************************************************************/ 3349static uint32_t 3350em_fill_descriptors (bus_addr_t address, uint32_t length, 3351 PDESC_ARRAY desc_array) 3352{ 3353 /* Since issue is sensitive to length and address.*/ 3354 /* Let us first check the address...*/ 3355 uint32_t safe_terminator; 3356 if (length <= 4) { 3357 desc_array->descriptor[0].address = address; 3358 desc_array->descriptor[0].length = length; 3359 desc_array->elements = 1; 3360 return (desc_array->elements); 3361 } 3362 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3363 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3364 if (safe_terminator == 0 || 3365 (safe_terminator > 4 && 3366 safe_terminator < 9) || 3367 (safe_terminator > 0xC && 3368 safe_terminator <= 0xF)) { 3369 desc_array->descriptor[0].address = address; 3370 desc_array->descriptor[0].length = length; 3371 desc_array->elements = 1; 3372 return (desc_array->elements); 3373 } 3374 3375 desc_array->descriptor[0].address = address; 3376 desc_array->descriptor[0].length = length - 4; 3377 desc_array->descriptor[1].address = address + (length - 4); 3378 desc_array->descriptor[1].length = 4; 3379 desc_array->elements = 2; 3380 return (desc_array->elements); 3381} 3382 3383/********************************************************************** 3384 * 3385 * Update the board statistics counters. 3386 * 3387 **********************************************************************/ 3388static void 3389em_update_stats_counters(struct em_softc *sc) 3390{ 3391 struct ifnet *ifp; 3392 3393 if(sc->hw.media_type == em_media_type_copper || 3394 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3395 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3396 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3397 } 3398 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3399 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3400 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3401 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3402 3403 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3404 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3405 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3406 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3407 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3408 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3409 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3410 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3411 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3412 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3413 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3414 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3415 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3416 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3417 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3418 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3419 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3420 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3421 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3422 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3423 3424 /* For the 64-bit byte counters the low dword must be read first. */ 3425 /* Both registers clear on the read of the high dword */ 3426 3427 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3428 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3429 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3430 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3431 3432 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3433 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3434 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3435 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3436 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3437 3438 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3439 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3440 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3441 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3442 3443 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3444 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3445 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3446 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3447 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3448 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3449 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3450 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3451 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3452 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3453 3454 if (sc->hw.mac_type >= em_82543) { 3455 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3456 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3457 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3458 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3459 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3460 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3461 } 3462 ifp = sc->ifp; 3463 3464 ifp->if_collisions = sc->stats.colc; 3465 3466 /* Rx Errors */ 3467 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3468 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3469 sc->stats.mpc + sc->stats.cexterr; 3470 3471 /* Tx Errors */ 3472 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3473 sc->watchdog_events; 3474} 3475 3476 3477/********************************************************************** 3478 * 3479 * This routine is called only when em_display_debug_stats is enabled. 3480 * This routine provides a way to take a look at important statistics 3481 * maintained by the driver and hardware. 3482 * 3483 **********************************************************************/ 3484static void 3485em_print_debug_info(struct em_softc *sc) 3486{ 3487 device_t dev = sc->dev; 3488 uint8_t *hw_addr = sc->hw.hw_addr; 3489 3490 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3491 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3492 E1000_READ_REG(&sc->hw, CTRL), 3493 E1000_READ_REG(&sc->hw, RCTL)); 3494 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3495 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3496 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3497 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3498 sc->hw.fc_high_water, 3499 sc->hw.fc_low_water); 3500 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3501 E1000_READ_REG(&sc->hw, TIDV), 3502 E1000_READ_REG(&sc->hw, TADV)); 3503 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3504 E1000_READ_REG(&sc->hw, RDTR), 3505 E1000_READ_REG(&sc->hw, RADV)); 3506 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3507 (long long)sc->tx_fifo_wrk_cnt, 3508 (long long)sc->tx_fifo_reset_cnt); 3509 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3510 E1000_READ_REG(&sc->hw, TDH), 3511 E1000_READ_REG(&sc->hw, TDT)); 3512 device_printf(dev, "Num Tx descriptors avail = %d\n", 3513 sc->num_tx_desc_avail); 3514 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3515 sc->no_tx_desc_avail1); 3516 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3517 sc->no_tx_desc_avail2); 3518 device_printf(dev, "Std mbuf failed = %ld\n", 3519 sc->mbuf_alloc_failed); 3520 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3521 sc->mbuf_cluster_failed); 3522 device_printf(dev, "Driver dropped packets = %ld\n", 3523 sc->dropped_pkts); 3524} 3525 3526static void 3527em_print_hw_stats(struct em_softc *sc) 3528{ 3529 device_t dev = sc->dev; 3530 3531 device_printf(dev, "Excessive collisions = %lld\n", 3532 (long long)sc->stats.ecol); 3533 device_printf(dev, "Symbol errors = %lld\n", 3534 (long long)sc->stats.symerrs); 3535 device_printf(dev, "Sequence errors = %lld\n", 3536 (long long)sc->stats.sec); 3537 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3538 3539 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3540 device_printf(dev, "Receive No Buffers = %lld\n", 3541 (long long)sc->stats.rnbc); 3542 device_printf(dev, "Receive length errors = %lld\n", 3543 (long long)sc->stats.rlec); 3544 device_printf(dev, "Receive errors = %lld\n", 3545 (long long)sc->stats.rxerrc); 3546 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3547 device_printf(dev, "Alignment errors = %lld\n", 3548 (long long)sc->stats.algnerrc); 3549 device_printf(dev, "Carrier extension errors = %lld\n", 3550 (long long)sc->stats.cexterr); 3551 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3552 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3553 3554 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3555 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3556 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3557 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3558 3559 device_printf(dev, "Good Packets Rcvd = %lld\n", 3560 (long long)sc->stats.gprc); 3561 device_printf(dev, "Good Packets Xmtd = %lld\n", 3562 (long long)sc->stats.gptc); 3563} 3564 3565static int 3566em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3567{ 3568 struct em_softc *sc; 3569 int error; 3570 int result; 3571 3572 result = -1; 3573 error = sysctl_handle_int(oidp, &result, 0, req); 3574 3575 if (error || !req->newptr) 3576 return (error); 3577 3578 if (result == 1) { 3579 sc = (struct em_softc *)arg1; 3580 em_print_debug_info(sc); 3581 } 3582 3583 return (error); 3584} 3585 3586 3587static int 3588em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3589{ 3590 struct em_softc *sc; 3591 int error; 3592 int result; 3593 3594 result = -1; 3595 error = sysctl_handle_int(oidp, &result, 0, req); 3596 3597 if (error || !req->newptr) 3598 return (error); 3599 3600 if (result == 1) { 3601 sc = (struct em_softc *)arg1; 3602 em_print_hw_stats(sc); 3603 } 3604 3605 return (error); 3606} 3607 3608static int 3609em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3610{ 3611 struct em_int_delay_info *info; 3612 struct em_softc *sc; 3613 uint32_t regval; 3614 int error; 3615 int usecs; 3616 int ticks; 3617 3618 info = (struct em_int_delay_info *)arg1; 3619 usecs = info->value; 3620 error = sysctl_handle_int(oidp, &usecs, 0, req); 3621 if (error != 0 || req->newptr == NULL) 3622 return (error); 3623 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3624 return (EINVAL); 3625 info->value = usecs; 3626 ticks = E1000_USECS_TO_TICKS(usecs); 3627 3628 sc = info->sc; 3629 3630 EM_LOCK(sc); 3631 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3632 regval = (regval & ~0xffff) | (ticks & 0xffff); 3633 /* Handle a few special cases. */ 3634 switch (info->offset) { 3635 case E1000_RDTR: 3636 case E1000_82542_RDTR: 3637 regval |= E1000_RDT_FPDB; 3638 break; 3639 case E1000_TIDV: 3640 case E1000_82542_TIDV: 3641 if (ticks == 0) { 3642 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3643 /* Don't write 0 into the TIDV register. */ 3644 regval++; 3645 } else 3646 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3647 break; 3648 } 3649 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3650 EM_UNLOCK(sc); 3651 return (0); 3652} 3653 3654static void 3655em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3656 const char *description, struct em_int_delay_info *info, 3657 int offset, int value) 3658{ 3659 info->sc = sc; 3660 info->offset = offset; 3661 info->value = value; 3662 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3663 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3664 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3665 info, 0, em_sysctl_int_delay, "I", description); 3666} 3667 3668#ifndef NO_EM_FASTINTR 3669static void 3670em_add_int_process_limit(struct em_softc *sc, const char *name, 3671 const char *description, int *limit, int value) 3672{ 3673 *limit = value; 3674 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3675 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3676 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3677} 3678#endif 3679