if_em.c revision 155718
150479Speter/************************************************************************** 22751Swollman 38050SwollmanCopyright (c) 2001-2005, Intel Corporation 474816SruAll rights reserved. 518035Sbde 665911SacheRedistribution and use in source and binary forms, with or without 765911Sachemodification, are permitted provided that the following conditions are met: 82751Swollman 92751Swollman 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 155718 2006-02-15 14:27:38Z glebius $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 3.2.18"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 143 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 147 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 151 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 155 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 /* required last entry */ 160 { 0, 0, 0, 0, 0} 161}; 162 163/********************************************************************* 164 * Table of branding strings for all supported NICs. 165 *********************************************************************/ 166 167static char *em_strings[] = { 168 "Intel(R) PRO/1000 Network Connection" 169}; 170 171/********************************************************************* 172 * Function prototypes 173 *********************************************************************/ 174static int em_probe(device_t); 175static int em_attach(device_t); 176static int em_detach(device_t); 177static int em_shutdown(device_t); 178static int em_suspend(device_t); 179static int em_resume(device_t); 180static void em_intr(void *); 181#ifndef NO_EM_FASTINTR 182static void em_intr_fast(void *); 183#endif 184static void em_start(struct ifnet *); 185static void em_start_locked(struct ifnet *ifp); 186static int em_ioctl(struct ifnet *, u_long, caddr_t); 187static void em_watchdog(struct ifnet *); 188static void em_init(void *); 189static void em_init_locked(struct em_softc *); 190static void em_stop(void *); 191static void em_media_status(struct ifnet *, struct ifmediareq *); 192static int em_media_change(struct ifnet *); 193static void em_identify_hardware(struct em_softc *); 194static int em_allocate_pci_resources(struct em_softc *); 195static int em_allocate_intr(struct em_softc *); 196static void em_free_intr(struct em_softc *); 197static void em_free_pci_resources(struct em_softc *); 198static void em_local_timer(void *); 199static int em_hardware_init(struct em_softc *); 200static void em_setup_interface(device_t, struct em_softc *); 201static int em_setup_transmit_structures(struct em_softc *); 202static void em_initialize_transmit_unit(struct em_softc *); 203static int em_setup_receive_structures(struct em_softc *); 204static void em_initialize_receive_unit(struct em_softc *); 205static void em_enable_intr(struct em_softc *); 206static void em_disable_intr(struct em_softc *); 207static void em_free_transmit_structures(struct em_softc *); 208static void em_free_receive_structures(struct em_softc *); 209static void em_update_stats_counters(struct em_softc *); 210static void em_txeof(struct em_softc *); 211static int em_allocate_receive_structures(struct em_softc *); 212static int em_allocate_transmit_structures(struct em_softc *); 213static int em_rxeof(struct em_softc *, int); 214#ifndef __NO_STRICT_ALIGNMENT 215static int em_fixup_rx(struct em_softc *); 216#endif 217static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 218 struct mbuf *); 219static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 220 uint32_t *, uint32_t *); 221static void em_set_promisc(struct em_softc *); 222static void em_disable_promisc(struct em_softc *); 223static void em_set_multi(struct em_softc *); 224static void em_print_hw_stats(struct em_softc *); 225static void em_update_link_status(struct em_softc *); 226static int em_get_buf(int i, struct em_softc *, struct mbuf *); 227static void em_enable_vlans(struct em_softc *); 228static void em_disable_vlans(struct em_softc *); 229static int em_encap(struct em_softc *, struct mbuf **); 230static void em_smartspeed(struct em_softc *); 231static int em_82547_fifo_workaround(struct em_softc *, int); 232static void em_82547_update_fifo_head(struct em_softc *, int); 233static int em_82547_tx_fifo_reset(struct em_softc *); 234static void em_82547_move_tail(void *arg); 235static void em_82547_move_tail_locked(struct em_softc *); 236static int em_dma_malloc(struct em_softc *, bus_size_t, 237 struct em_dma_alloc *, int); 238static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 239static void em_print_debug_info(struct em_softc *); 240static int em_is_valid_ether_addr(uint8_t *); 241static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 242static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 243static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 244 PDESC_ARRAY desc_array); 245static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 246static void em_add_int_delay_sysctl(struct em_softc *, const char *, 247 const char *, struct em_int_delay_info *, int, int); 248#ifndef NO_EM_FASTINTR 249static void em_add_int_process_limit(struct em_softc *, const char *, 250 const char *, int *, int); 251static void em_handle_rxtx(void *context, int pending); 252static void em_handle_link(void *context, int pending); 253#endif 254#ifdef DEVICE_POLLING 255static poll_handler_t em_poll; 256#endif 257 258/********************************************************************* 259 * FreeBSD Device Interface Entry Points 260 *********************************************************************/ 261 262static device_method_t em_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, em_probe), 265 DEVMETHOD(device_attach, em_attach), 266 DEVMETHOD(device_detach, em_detach), 267 DEVMETHOD(device_shutdown, em_shutdown), 268 DEVMETHOD(device_suspend, em_suspend), 269 DEVMETHOD(device_resume, em_resume), 270 {0, 0} 271}; 272 273static driver_t em_driver = { 274 "em", em_methods, sizeof(struct em_softc), 275}; 276 277static devclass_t em_devclass; 278DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 279MODULE_DEPEND(em, pci, 1, 1, 1); 280MODULE_DEPEND(em, ether, 1, 1, 1); 281 282/********************************************************************* 283 * Tunable default values. 284 *********************************************************************/ 285 286#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 287#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 288 289static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 290static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 291static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 292static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 293static int em_rxd = EM_DEFAULT_RXD; 294static int em_txd = EM_DEFAULT_TXD; 295 296TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 297TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 298TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 299TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 300TUNABLE_INT("hw.em.rxd", &em_rxd); 301TUNABLE_INT("hw.em.txd", &em_txd); 302#ifndef NO_EM_FASTINTR 303static int em_rx_process_limit = 100; 304TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 305#endif 306 307/********************************************************************* 308 * Device identification routine 309 * 310 * em_probe determines if the driver should be loaded on 311 * adapter based on PCI vendor/device id of the adapter. 312 * 313 * return BUS_PROBE_DEFAULT on success, positive on failure 314 *********************************************************************/ 315 316static int 317em_probe(device_t dev) 318{ 319 char adapter_name[60]; 320 uint16_t pci_vendor_id = 0; 321 uint16_t pci_device_id = 0; 322 uint16_t pci_subvendor_id = 0; 323 uint16_t pci_subdevice_id = 0; 324 em_vendor_info_t *ent; 325 326 INIT_DEBUGOUT("em_probe: begin"); 327 328 pci_vendor_id = pci_get_vendor(dev); 329 if (pci_vendor_id != EM_VENDOR_ID) 330 return (ENXIO); 331 332 pci_device_id = pci_get_device(dev); 333 pci_subvendor_id = pci_get_subvendor(dev); 334 pci_subdevice_id = pci_get_subdevice(dev); 335 336 ent = em_vendor_info_array; 337 while (ent->vendor_id != 0) { 338 if ((pci_vendor_id == ent->vendor_id) && 339 (pci_device_id == ent->device_id) && 340 341 ((pci_subvendor_id == ent->subvendor_id) || 342 (ent->subvendor_id == PCI_ANY_ID)) && 343 344 ((pci_subdevice_id == ent->subdevice_id) || 345 (ent->subdevice_id == PCI_ANY_ID))) { 346 sprintf(adapter_name, "%s %s", 347 em_strings[ent->index], 348 em_driver_version); 349 device_set_desc_copy(dev, adapter_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 ent++; 353 } 354 355 return (ENXIO); 356} 357 358/********************************************************************* 359 * Device initialization routine 360 * 361 * The attach entry point is called when the driver is being loaded. 362 * This routine identifies the type of hardware, allocates all resources 363 * and initializes the hardware. 364 * 365 * return 0 on success, positive on failure 366 *********************************************************************/ 367 368static int 369em_attach(device_t dev) 370{ 371 struct em_softc *sc; 372 int tsize, rsize; 373 int error = 0; 374 375 INIT_DEBUGOUT("em_attach: begin"); 376 377 sc = device_get_softc(dev); 378 sc->dev = sc->osdep.dev = dev; 379 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 380 381 /* SYSCTL stuff */ 382 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 383 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 384 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 385 em_sysctl_debug_info, "I", "Debug Information"); 386 387 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 388 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 389 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 390 em_sysctl_stats, "I", "Statistics"); 391 392 callout_init(&sc->timer, CALLOUT_MPSAFE); 393 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 394 395 /* Determine hardware revision */ 396 em_identify_hardware(sc); 397 398 /* Set up some sysctls for the tunable interrupt delays */ 399 em_add_int_delay_sysctl(sc, "rx_int_delay", 400 "receive interrupt delay in usecs", &sc->rx_int_delay, 401 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 402 em_add_int_delay_sysctl(sc, "tx_int_delay", 403 "transmit interrupt delay in usecs", &sc->tx_int_delay, 404 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 405 if (sc->hw.mac_type >= em_82540) { 406 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 407 "receive interrupt delay limit in usecs", 408 &sc->rx_abs_int_delay, 409 E1000_REG_OFFSET(&sc->hw, RADV), 410 em_rx_abs_int_delay_dflt); 411 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 412 "transmit interrupt delay limit in usecs", 413 &sc->tx_abs_int_delay, 414 E1000_REG_OFFSET(&sc->hw, TADV), 415 em_tx_abs_int_delay_dflt); 416 } 417 418 /* Sysctls for limiting the amount of work done in the taskqueue */ 419#ifndef NO_EM_FASTINTR 420 em_add_int_process_limit(sc, "rx_processing_limit", 421 "max number of rx packets to process", &sc->rx_process_limit, 422 em_rx_process_limit); 423#endif 424 425 /* 426 * Validate number of transmit and receive descriptors. It 427 * must not exceed hardware maximum, and must be multiple 428 * of E1000_DBA_ALIGN. 429 */ 430 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 431 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 432 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 433 (em_txd < EM_MIN_TXD)) { 434 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 435 EM_DEFAULT_TXD, em_txd); 436 sc->num_tx_desc = EM_DEFAULT_TXD; 437 } else 438 sc->num_tx_desc = em_txd; 439 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 440 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 441 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 442 (em_rxd < EM_MIN_RXD)) { 443 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 444 EM_DEFAULT_RXD, em_rxd); 445 sc->num_rx_desc = EM_DEFAULT_RXD; 446 } else 447 sc->num_rx_desc = em_rxd; 448 449 sc->hw.autoneg = DO_AUTO_NEG; 450 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 451 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 452 sc->hw.tbi_compatibility_en = TRUE; 453 sc->rx_buffer_len = EM_RXBUFFER_2048; 454 455 sc->hw.phy_init_script = 1; 456 sc->hw.phy_reset_disable = FALSE; 457 458#ifndef EM_MASTER_SLAVE 459 sc->hw.master_slave = em_ms_hw_default; 460#else 461 sc->hw.master_slave = EM_MASTER_SLAVE; 462#endif 463 /* 464 * Set the max frame size assuming standard ethernet 465 * sized frames. 466 */ 467 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 468 469 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 470 471 /* 472 * This controls when hardware reports transmit completion 473 * status. 474 */ 475 sc->hw.report_tx_early = 1; 476 if (em_allocate_pci_resources(sc)) { 477 device_printf(dev, "Allocation of PCI resources failed\n"); 478 error = ENXIO; 479 goto err_pci; 480 } 481 482 /* Initialize eeprom parameters */ 483 em_init_eeprom_params(&sc->hw); 484 485 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 486 E1000_DBA_ALIGN); 487 488 /* Allocate Transmit Descriptor ring */ 489 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 490 device_printf(dev, "Unable to allocate tx_desc memory\n"); 491 error = ENOMEM; 492 goto err_tx_desc; 493 } 494 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 495 496 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 497 E1000_DBA_ALIGN); 498 499 /* Allocate Receive Descriptor ring */ 500 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 501 device_printf(dev, "Unable to allocate rx_desc memory\n"); 502 error = ENOMEM; 503 goto err_rx_desc; 504 } 505 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 506 507 /* Initialize the hardware */ 508 if (em_hardware_init(sc)) { 509 device_printf(dev, "Unable to initialize the hardware\n"); 510 error = EIO; 511 goto err_hw_init; 512 } 513 514 /* Copy the permanent MAC address out of the EEPROM */ 515 if (em_read_mac_addr(&sc->hw) < 0) { 516 device_printf(dev, "EEPROM read error while reading MAC" 517 " address\n"); 518 error = EIO; 519 goto err_hw_init; 520 } 521 522 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 523 device_printf(dev, "Invalid MAC address\n"); 524 error = EIO; 525 goto err_hw_init; 526 } 527 528 /* Setup OS specific network interface */ 529 em_setup_interface(dev, sc); 530 531 em_allocate_intr(sc); 532 533 /* Initialize statistics */ 534 em_clear_hw_cntrs(&sc->hw); 535 em_update_stats_counters(sc); 536 sc->hw.get_link_status = 1; 537 em_update_link_status(sc); 538 539 /* Identify 82544 on PCIX */ 540 em_get_bus_info(&sc->hw); 541 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 542 sc->pcix_82544 = TRUE; 543 else 544 sc->pcix_82544 = FALSE; 545 546 INIT_DEBUGOUT("em_attach: end"); 547 548 return (0); 549 550err_hw_init: 551 em_dma_free(sc, &sc->rxdma); 552err_rx_desc: 553 em_dma_free(sc, &sc->txdma); 554err_tx_desc: 555err_pci: 556 em_free_intr(sc); 557 em_free_pci_resources(sc); 558 EM_LOCK_DESTROY(sc); 559 560 return (error); 561} 562 563/********************************************************************* 564 * Device removal routine 565 * 566 * The detach entry point is called when the driver is being removed. 567 * This routine stops the adapter and deallocates all the resources 568 * that were allocated for driver operation. 569 * 570 * return 0 on success, positive on failure 571 *********************************************************************/ 572 573static int 574em_detach(device_t dev) 575{ 576 struct em_softc *sc = device_get_softc(dev); 577 struct ifnet *ifp = sc->ifp; 578 579 INIT_DEBUGOUT("em_detach: begin"); 580 581#ifdef DEVICE_POLLING 582 if (ifp->if_capenable & IFCAP_POLLING) 583 ether_poll_deregister(ifp); 584#endif 585 586 em_free_intr(sc); 587 EM_LOCK(sc); 588 sc->in_detach = 1; 589 em_stop(sc); 590 em_phy_hw_reset(&sc->hw); 591 EM_UNLOCK(sc); 592 ether_ifdetach(sc->ifp); 593 594 em_free_pci_resources(sc); 595 bus_generic_detach(dev); 596 if_free(ifp); 597 598 /* Free Transmit Descriptor ring */ 599 if (sc->tx_desc_base) { 600 em_dma_free(sc, &sc->txdma); 601 sc->tx_desc_base = NULL; 602 } 603 604 /* Free Receive Descriptor ring */ 605 if (sc->rx_desc_base) { 606 em_dma_free(sc, &sc->rxdma); 607 sc->rx_desc_base = NULL; 608 } 609 610 EM_LOCK_DESTROY(sc); 611 612 return (0); 613} 614 615/********************************************************************* 616 * 617 * Shutdown entry point 618 * 619 **********************************************************************/ 620 621static int 622em_shutdown(device_t dev) 623{ 624 struct em_softc *sc = device_get_softc(dev); 625 EM_LOCK(sc); 626 em_stop(sc); 627 EM_UNLOCK(sc); 628 return (0); 629} 630 631/* 632 * Suspend/resume device methods. 633 */ 634static int 635em_suspend(device_t dev) 636{ 637 struct em_softc *sc = device_get_softc(dev); 638 639 EM_LOCK(sc); 640 em_stop(sc); 641 EM_UNLOCK(sc); 642 643 return bus_generic_suspend(dev); 644} 645 646static int 647em_resume(device_t dev) 648{ 649 struct em_softc *sc = device_get_softc(dev); 650 struct ifnet *ifp = sc->ifp; 651 652 EM_LOCK(sc); 653 em_init_locked(sc); 654 if ((ifp->if_flags & IFF_UP) && 655 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 656 em_start_locked(ifp); 657 EM_UNLOCK(sc); 658 659 return bus_generic_resume(dev); 660} 661 662 663/********************************************************************* 664 * Transmit entry point 665 * 666 * em_start is called by the stack to initiate a transmit. 667 * The driver will remain in this routine as long as there are 668 * packets to transmit and transmit resources are available. 669 * In case resources are not available stack is notified and 670 * the packet is requeued. 671 **********************************************************************/ 672 673static void 674em_start_locked(struct ifnet *ifp) 675{ 676 struct em_softc *sc = ifp->if_softc; 677 struct mbuf *m_head; 678 679 EM_LOCK_ASSERT(sc); 680 681 if (!sc->link_active) 682 return; 683 684 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 685 686 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 687 if (m_head == NULL) 688 break; 689 /* 690 * em_encap() can modify our pointer, and or make it NULL on 691 * failure. In that event, we can't requeue. 692 */ 693 if (em_encap(sc, &m_head)) { 694 if (m_head == NULL) 695 break; 696 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 697 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 698 break; 699 } 700 701 /* Send a copy of the frame to the BPF listener */ 702 BPF_MTAP(ifp, m_head); 703 704 /* Set timeout in case hardware has problems transmitting. */ 705 ifp->if_timer = EM_TX_TIMEOUT; 706 } 707} 708 709static void 710em_start(struct ifnet *ifp) 711{ 712 struct em_softc *sc = ifp->if_softc; 713 714 EM_LOCK(sc); 715 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 716 em_start_locked(ifp); 717 EM_UNLOCK(sc); 718} 719 720/********************************************************************* 721 * Ioctl entry point 722 * 723 * em_ioctl is called when the user wants to configure the 724 * interface. 725 * 726 * return 0 on success, positive on failure 727 **********************************************************************/ 728 729static int 730em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 731{ 732 struct em_softc *sc = ifp->if_softc; 733 struct ifreq *ifr = (struct ifreq *)data; 734 int error = 0; 735 736 if (sc->in_detach) 737 return (error); 738 739 switch (command) { 740 case SIOCSIFADDR: 741 case SIOCGIFADDR: 742 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 743 ether_ioctl(ifp, command, data); 744 break; 745 case SIOCSIFMTU: 746 { 747 int max_frame_size; 748 749 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 750 751 switch (sc->hw.mac_type) { 752 case em_82571: 753 case em_82572: 754 max_frame_size = 10500; 755 break; 756 case em_82573: 757 /* 82573 does not support jumbo frames. */ 758 max_frame_size = ETHER_MAX_LEN; 759 break; 760 default: 761 max_frame_size = MAX_JUMBO_FRAME_SIZE; 762 } 763 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 764 ETHER_CRC_LEN) { 765 error = EINVAL; 766 break; 767 } 768 769 EM_LOCK(sc); 770 ifp->if_mtu = ifr->ifr_mtu; 771 sc->hw.max_frame_size = 772 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 773 em_init_locked(sc); 774 EM_UNLOCK(sc); 775 break; 776 } 777 case SIOCSIFFLAGS: 778 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 779 EM_LOCK(sc); 780 if (ifp->if_flags & IFF_UP) { 781 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 782 em_init_locked(sc); 783 } 784 785 em_disable_promisc(sc); 786 em_set_promisc(sc); 787 } else { 788 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 789 em_stop(sc); 790 } 791 } 792 EM_UNLOCK(sc); 793 break; 794 case SIOCADDMULTI: 795 case SIOCDELMULTI: 796 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 797 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 798 EM_LOCK(sc); 799 em_disable_intr(sc); 800 em_set_multi(sc); 801 if (sc->hw.mac_type == em_82542_rev2_0) { 802 em_initialize_receive_unit(sc); 803 } 804#ifdef DEVICE_POLLING 805 if (!(ifp->if_capenable & IFCAP_POLLING)) 806#endif 807 em_enable_intr(sc); 808 EM_UNLOCK(sc); 809 } 810 break; 811 case SIOCSIFMEDIA: 812 case SIOCGIFMEDIA: 813 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 814 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 815 break; 816 case SIOCSIFCAP: 817 { 818 int mask, reinit; 819 820 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 821 reinit = 0; 822 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 823#ifdef DEVICE_POLLING 824 if (mask & IFCAP_POLLING) { 825 if (ifr->ifr_reqcap & IFCAP_POLLING) { 826 error = ether_poll_register(em_poll, ifp); 827 if (error) 828 return (error); 829 EM_LOCK(sc); 830 em_disable_intr(sc); 831 ifp->if_capenable |= IFCAP_POLLING; 832 EM_UNLOCK(sc); 833 } else { 834 error = ether_poll_deregister(ifp); 835 /* Enable interrupt even in error case */ 836 EM_LOCK(sc); 837 em_enable_intr(sc); 838 ifp->if_capenable &= ~IFCAP_POLLING; 839 EM_UNLOCK(sc); 840 } 841 } 842#endif 843 if (mask & IFCAP_HWCSUM) { 844 ifp->if_capenable ^= IFCAP_HWCSUM; 845 reinit = 1; 846 } 847 if (mask & IFCAP_VLAN_HWTAGGING) { 848 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 849 reinit = 1; 850 } 851 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 852 em_init(sc); 853 VLAN_CAPABILITIES(ifp); 854 break; 855 } 856 default: 857 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 858 error = EINVAL; 859 } 860 861 return (error); 862} 863 864/********************************************************************* 865 * Watchdog entry point 866 * 867 * This routine is called whenever hardware quits transmitting. 868 * 869 **********************************************************************/ 870 871static void 872em_watchdog(struct ifnet *ifp) 873{ 874 struct em_softc *sc = ifp->if_softc; 875 876 EM_LOCK(sc); 877 /* If we are in this routine because of pause frames, then 878 * don't reset the hardware. 879 */ 880 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 881 ifp->if_timer = EM_TX_TIMEOUT; 882 EM_UNLOCK(sc); 883 return; 884 } 885 886 if (em_check_for_link(&sc->hw) == 0) 887 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 888 889 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 890 sc->watchdog_events++; 891 892 em_init_locked(sc); 893 EM_UNLOCK(sc); 894} 895 896/********************************************************************* 897 * Init entry point 898 * 899 * This routine is used in two ways. It is used by the stack as 900 * init entry point in network interface structure. It is also used 901 * by the driver as a hw/sw initialization routine to get to a 902 * consistent state. 903 * 904 * return 0 on success, positive on failure 905 **********************************************************************/ 906 907static void 908em_init_locked(struct em_softc *sc) 909{ 910 struct ifnet *ifp = sc->ifp; 911 device_t dev = sc->dev; 912 uint32_t pba; 913 914 INIT_DEBUGOUT("em_init: begin"); 915 916 EM_LOCK_ASSERT(sc); 917 918 em_stop(sc); 919 920 /* 921 * Packet Buffer Allocation (PBA) 922 * Writing PBA sets the receive portion of the buffer 923 * the remainder is used for the transmit buffer. 924 */ 925 switch (sc->hw.mac_type) { 926 case em_82547: 927 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 928 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 929 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 930 else 931 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 932 sc->tx_fifo_head = 0; 933 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 934 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 935 break; 936 case em_82571: /* 82571: Total Packet Buffer is 48K */ 937 case em_82572: /* 82572: Total Packet Buffer is 48K */ 938 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 939 break; 940 case em_82573: /* 82573: Total Packet Buffer is 32K */ 941 /* Jumbo frames not supported */ 942 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 943 break; 944 default: 945 /* Devices before 82547 had a Packet Buffer of 64K. */ 946 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 947 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 948 else 949 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 950 } 951 952 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 953 E1000_WRITE_REG(&sc->hw, PBA, pba); 954 955 /* Get the latest mac address, User can use a LAA */ 956 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 957 em_init_rx_addrs(&sc->hw); 958 959 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 960 em_enable_vlans(sc); 961 962 /* Prepare transmit descriptors and buffers */ 963 if (em_setup_transmit_structures(sc)) { 964 device_printf(dev, "Could not setup transmit structures\n"); 965 em_stop(sc); 966 return; 967 } 968 em_initialize_transmit_unit(sc); 969 970 /* Setup Multicast table */ 971 em_set_multi(sc); 972 973 /* Prepare receive descriptors and buffers */ 974 if (em_setup_receive_structures(sc)) { 975 device_printf(dev, "Could not setup receive structures\n"); 976 em_stop(sc); 977 return; 978 } 979 em_initialize_receive_unit(sc); 980 981 /* Don't loose promiscuous settings */ 982 em_set_promisc(sc); 983 984 ifp->if_drv_flags |= IFF_DRV_RUNNING; 985 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 986 987 if (sc->hw.mac_type >= em_82543) { 988 if (ifp->if_capenable & IFCAP_TXCSUM) 989 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 990 else 991 ifp->if_hwassist = 0; 992 } 993 994 callout_reset(&sc->timer, hz, em_local_timer, sc); 995 em_clear_hw_cntrs(&sc->hw); 996#ifdef DEVICE_POLLING 997 /* 998 * Only enable interrupts if we are not polling, make sure 999 * they are off otherwise. 1000 */ 1001 if (ifp->if_capenable & IFCAP_POLLING) 1002 em_disable_intr(sc); 1003 else 1004#endif /* DEVICE_POLLING */ 1005 em_enable_intr(sc); 1006 1007 /* Don't reset the phy next time init gets called */ 1008 sc->hw.phy_reset_disable = TRUE; 1009} 1010 1011static void 1012em_init(void *arg) 1013{ 1014 struct em_softc *sc = arg; 1015 1016 EM_LOCK(sc); 1017 em_init_locked(sc); 1018 EM_UNLOCK(sc); 1019} 1020 1021 1022#ifdef DEVICE_POLLING 1023static void 1024em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1025{ 1026 struct em_softc *sc = ifp->if_softc; 1027 uint32_t reg_icr; 1028 1029 EM_LOCK_ASSERT(sc); 1030 1031 if (cmd == POLL_AND_CHECK_STATUS) { 1032 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1033 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1034 callout_stop(&sc->timer); 1035 sc->hw.get_link_status = 1; 1036 em_check_for_link(&sc->hw); 1037 em_update_link_status(sc); 1038 callout_reset(&sc->timer, hz, em_local_timer, sc); 1039 } 1040 } 1041 em_rxeof(sc, count); 1042 em_txeof(sc); 1043 1044 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1045 em_start_locked(ifp); 1046} 1047 1048static void 1049em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1050{ 1051 struct em_softc *sc = ifp->if_softc; 1052 1053 EM_LOCK(sc); 1054 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1055 em_poll_locked(ifp, cmd, count); 1056 EM_UNLOCK(sc); 1057} 1058#endif /* DEVICE_POLLING */ 1059 1060#ifndef NO_EM_FASTINTR 1061static void 1062em_handle_link(void *context, int pending) 1063{ 1064 struct em_softc *sc = context; 1065 struct ifnet *ifp; 1066 1067 ifp = sc->ifp; 1068 1069 EM_LOCK(sc); 1070 1071 callout_stop(&sc->timer); 1072 sc->hw.get_link_status = 1; 1073 em_check_for_link(&sc->hw); 1074 em_update_link_status(sc); 1075 callout_reset(&sc->timer, hz, em_local_timer, sc); 1076 EM_UNLOCK(sc); 1077} 1078 1079static void 1080em_handle_rxtx(void *context, int pending) 1081{ 1082 struct em_softc *sc = context; 1083 struct ifnet *ifp; 1084 1085 NET_LOCK_GIANT(); 1086 ifp = sc->ifp; 1087 1088 /* 1089 * TODO: 1090 * It should be possible to run the tx clean loop without the lock. 1091 */ 1092 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1093 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1094 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1095 EM_LOCK(sc); 1096 em_txeof(sc); 1097 1098 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1099 em_start_locked(ifp); 1100 EM_UNLOCK(sc); 1101 } 1102 1103 em_enable_intr(sc); 1104 NET_UNLOCK_GIANT(); 1105} 1106#endif 1107 1108/********************************************************************* 1109 * 1110 * Interrupt Service routine 1111 * 1112 **********************************************************************/ 1113#ifndef NO_EM_FASTINTR 1114static void 1115em_intr_fast(void *arg) 1116{ 1117 struct em_softc *sc = arg; 1118 struct ifnet *ifp; 1119 uint32_t reg_icr; 1120 1121 ifp = sc->ifp; 1122 1123#ifdef DEVICE_POLLING 1124 if (ifp->if_capenable & IFCAP_POLLING) 1125 return; 1126#endif /* DEVICE_POLLING */ 1127 1128 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1129 1130 /* Hot eject? */ 1131 if (reg_icr == 0xffffffff) 1132 return; 1133 1134 /* Definitely not our interrupt. */ 1135 if (reg_icr == 0x0) 1136 return; 1137 1138 /* 1139 * Starting with the 82571 chip, bit 31 should be used to 1140 * determine whether the interrupt belongs to us. 1141 */ 1142 if (sc->hw.mac_type >= em_82571 && 1143 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1144 return; 1145 1146 /* 1147 * Mask interrupts until the taskqueue is finished running. This is 1148 * cheap, just assume that it is needed. This also works around the 1149 * MSI message reordering errata on certain systems. 1150 */ 1151 em_disable_intr(sc); 1152 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1153 1154 /* Link status change */ 1155 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1156 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1157 1158 if (reg_icr & E1000_ICR_RXO) 1159 sc->rx_overruns++; 1160} 1161#endif 1162 1163static void 1164em_intr(void *arg) 1165{ 1166 struct em_softc *sc = arg; 1167 struct ifnet *ifp; 1168 uint32_t reg_icr; 1169 int wantinit = 0; 1170 1171 EM_LOCK(sc); 1172 1173 ifp = sc->ifp; 1174 1175#ifdef DEVICE_POLLING 1176 if (ifp->if_capenable & IFCAP_POLLING) { 1177 EM_UNLOCK(sc); 1178 return; 1179 } 1180#endif 1181 1182 for (;;) { 1183 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1184 if (sc->hw.mac_type >= em_82571 && 1185 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1186 break; 1187 else if (reg_icr == 0) 1188 break; 1189 1190 /* 1191 * XXX: some laptops trigger several spurious interrupts 1192 * on em(4) when in the resume cycle. The ICR register 1193 * reports all-ones value in this case. Processing such 1194 * interrupts would lead to a freeze. I don't know why. 1195 */ 1196 if (reg_icr == 0xffffffff) 1197 break; 1198 1199 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1200 em_rxeof(sc, -1); 1201 em_txeof(sc); 1202 } 1203 1204 /* Link status change */ 1205 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1206 callout_stop(&sc->timer); 1207 sc->hw.get_link_status = 1; 1208 em_check_for_link(&sc->hw); 1209 em_update_link_status(sc); 1210 callout_reset(&sc->timer, hz, em_local_timer, sc); 1211 } 1212 1213 if (reg_icr & E1000_ICR_RXO) { 1214 sc->rx_overruns++; 1215 wantinit = 1; 1216 } 1217 } 1218#if 0 1219 if (wantinit) 1220 em_init_locked(sc); 1221#endif 1222 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1223 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1224 em_start_locked(ifp); 1225 1226 EM_UNLOCK(sc); 1227} 1228 1229/********************************************************************* 1230 * 1231 * Media Ioctl callback 1232 * 1233 * This routine is called whenever the user queries the status of 1234 * the interface using ifconfig. 1235 * 1236 **********************************************************************/ 1237static void 1238em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1239{ 1240 struct em_softc *sc = ifp->if_softc; 1241 1242 INIT_DEBUGOUT("em_media_status: begin"); 1243 1244 em_check_for_link(&sc->hw); 1245 em_update_link_status(sc); 1246 1247 ifmr->ifm_status = IFM_AVALID; 1248 ifmr->ifm_active = IFM_ETHER; 1249 1250 if (!sc->link_active) 1251 return; 1252 1253 ifmr->ifm_status |= IFM_ACTIVE; 1254 1255 if (sc->hw.media_type == em_media_type_fiber) { 1256 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1257 } else { 1258 switch (sc->link_speed) { 1259 case 10: 1260 ifmr->ifm_active |= IFM_10_T; 1261 break; 1262 case 100: 1263 ifmr->ifm_active |= IFM_100_TX; 1264 break; 1265 case 1000: 1266 ifmr->ifm_active |= IFM_1000_T; 1267 break; 1268 } 1269 if (sc->link_duplex == FULL_DUPLEX) 1270 ifmr->ifm_active |= IFM_FDX; 1271 else 1272 ifmr->ifm_active |= IFM_HDX; 1273 } 1274} 1275 1276/********************************************************************* 1277 * 1278 * Media Ioctl callback 1279 * 1280 * This routine is called when the user changes speed/duplex using 1281 * media/mediopt option with ifconfig. 1282 * 1283 **********************************************************************/ 1284static int 1285em_media_change(struct ifnet *ifp) 1286{ 1287 struct em_softc *sc = ifp->if_softc; 1288 struct ifmedia *ifm = &sc->media; 1289 1290 INIT_DEBUGOUT("em_media_change: begin"); 1291 1292 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1293 return (EINVAL); 1294 1295 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1296 case IFM_AUTO: 1297 sc->hw.autoneg = DO_AUTO_NEG; 1298 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1299 break; 1300 case IFM_1000_SX: 1301 case IFM_1000_T: 1302 sc->hw.autoneg = DO_AUTO_NEG; 1303 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1304 break; 1305 case IFM_100_TX: 1306 sc->hw.autoneg = FALSE; 1307 sc->hw.autoneg_advertised = 0; 1308 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1309 sc->hw.forced_speed_duplex = em_100_full; 1310 else 1311 sc->hw.forced_speed_duplex = em_100_half; 1312 break; 1313 case IFM_10_T: 1314 sc->hw.autoneg = FALSE; 1315 sc->hw.autoneg_advertised = 0; 1316 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1317 sc->hw.forced_speed_duplex = em_10_full; 1318 else 1319 sc->hw.forced_speed_duplex = em_10_half; 1320 break; 1321 default: 1322 device_printf(sc->dev, "Unsupported media type\n"); 1323 } 1324 1325 /* As the speed/duplex settings my have changed we need to 1326 * reset the PHY. 1327 */ 1328 sc->hw.phy_reset_disable = FALSE; 1329 1330 em_init(sc); 1331 1332 return (0); 1333} 1334 1335/********************************************************************* 1336 * 1337 * This routine maps the mbufs to tx descriptors. 1338 * 1339 * return 0 on success, positive on failure 1340 **********************************************************************/ 1341static int 1342em_encap(struct em_softc *sc, struct mbuf **m_headp) 1343{ 1344 struct ifnet *ifp = sc->ifp; 1345 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1346 bus_dmamap_t map; 1347 struct em_buffer *tx_buffer; 1348 struct em_tx_desc *current_tx_desc; 1349 struct mbuf *m_head; 1350 struct m_tag *mtag; 1351 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1352 int nsegs, i, j; 1353 int error = 0; 1354 1355 m_head = *m_headp; 1356 current_tx_desc = NULL; 1357 txd_used = txd_saved = 0; 1358 1359 /* 1360 * Force a cleanup if number of TX descriptors 1361 * available hits the threshold. 1362 */ 1363 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1364 em_txeof(sc); 1365 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1366 sc->no_tx_desc_avail1++; 1367 return (ENOBUFS); 1368 } 1369 } 1370 1371 /* 1372 * Map the packet for DMA. 1373 */ 1374 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1375 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1376 segs, &nsegs, BUS_DMA_NOWAIT); 1377 map = tx_buffer->map; 1378 if (error != 0) { 1379 sc->no_tx_dma_setup++; 1380 return (error); 1381 } 1382 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1383 1384 if (nsegs > sc->num_tx_desc_avail) { 1385 sc->no_tx_desc_avail2++; 1386 error = ENOBUFS; 1387 goto encap_fail; 1388 } 1389 1390 if (ifp->if_hwassist > 0) 1391 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1392 else 1393 txd_upper = txd_lower = 0; 1394 1395 /* Find out if we are in vlan mode. */ 1396 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1397 1398 /* 1399 * When operating in promiscuous mode, hardware encapsulation for 1400 * packets is disabled. This means we have to add the vlan 1401 * encapsulation in the driver, since it will have come down from the 1402 * VLAN layer with a tag instead of a VLAN header. 1403 */ 1404 if (mtag != NULL && sc->em_insert_vlan_header) { 1405 struct ether_vlan_header *evl; 1406 struct ether_header eh; 1407 1408 m_head = m_pullup(m_head, sizeof(eh)); 1409 if (m_head == NULL) { 1410 *m_headp = NULL; 1411 error = ENOBUFS; 1412 goto encap_fail; 1413 } 1414 eh = *mtod(m_head, struct ether_header *); 1415 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1416 if (m_head == NULL) { 1417 *m_headp = NULL; 1418 error = ENOBUFS; 1419 goto encap_fail; 1420 } 1421 m_head = m_pullup(m_head, sizeof(*evl)); 1422 if (m_head == NULL) { 1423 *m_headp = NULL; 1424 error = ENOBUFS; 1425 goto encap_fail; 1426 } 1427 evl = mtod(m_head, struct ether_vlan_header *); 1428 bcopy(&eh, evl, sizeof(*evl)); 1429 evl->evl_proto = evl->evl_encap_proto; 1430 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1431 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1432 m_tag_delete(m_head, mtag); 1433 mtag = NULL; 1434 *m_headp = m_head; 1435 } 1436 1437 i = sc->next_avail_tx_desc; 1438 if (sc->pcix_82544) { 1439 txd_saved = i; 1440 txd_used = 0; 1441 } 1442 for (j = 0; j < nsegs; j++) { 1443 /* If adapter is 82544 and on PCIX bus. */ 1444 if(sc->pcix_82544) { 1445 DESC_ARRAY desc_array; 1446 uint32_t array_elements, counter; 1447 1448 /* 1449 * Check the Address and Length combination and 1450 * split the data accordingly 1451 */ 1452 array_elements = em_fill_descriptors(segs[j].ds_addr, 1453 segs[j].ds_len, &desc_array); 1454 for (counter = 0; counter < array_elements; counter++) { 1455 if (txd_used == sc->num_tx_desc_avail) { 1456 sc->next_avail_tx_desc = txd_saved; 1457 sc->no_tx_desc_avail2++; 1458 error = ENOBUFS; 1459 goto encap_fail; 1460 } 1461 tx_buffer = &sc->tx_buffer_area[i]; 1462 current_tx_desc = &sc->tx_desc_base[i]; 1463 current_tx_desc->buffer_addr = htole64( 1464 desc_array.descriptor[counter].address); 1465 current_tx_desc->lower.data = htole32( 1466 (sc->txd_cmd | txd_lower | 1467 (uint16_t)desc_array.descriptor[counter].length)); 1468 current_tx_desc->upper.data = htole32((txd_upper)); 1469 if (++i == sc->num_tx_desc) 1470 i = 0; 1471 1472 tx_buffer->m_head = NULL; 1473 txd_used++; 1474 } 1475 } else { 1476 tx_buffer = &sc->tx_buffer_area[i]; 1477 current_tx_desc = &sc->tx_desc_base[i]; 1478 1479 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1480 current_tx_desc->lower.data = htole32( 1481 sc->txd_cmd | txd_lower | segs[j].ds_len); 1482 current_tx_desc->upper.data = htole32(txd_upper); 1483 1484 if (++i == sc->num_tx_desc) 1485 i = 0; 1486 1487 tx_buffer->m_head = NULL; 1488 } 1489 } 1490 1491 sc->next_avail_tx_desc = i; 1492 if (sc->pcix_82544) 1493 sc->num_tx_desc_avail -= txd_used; 1494 else 1495 sc->num_tx_desc_avail -= nsegs; 1496 1497 if (mtag != NULL) { 1498 /* Set the vlan id. */ 1499 current_tx_desc->upper.fields.special = 1500 htole16(VLAN_TAG_VALUE(mtag)); 1501 1502 /* Tell hardware to add tag. */ 1503 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1504 } 1505 1506 tx_buffer->m_head = m_head; 1507 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1508 1509 /* 1510 * Last Descriptor of Packet needs End Of Packet (EOP). 1511 */ 1512 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1513 1514 /* 1515 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1516 * that this frame is available to transmit. 1517 */ 1518 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1519 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1520 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1521 em_82547_move_tail_locked(sc); 1522 else { 1523 E1000_WRITE_REG(&sc->hw, TDT, i); 1524 if (sc->hw.mac_type == em_82547) 1525 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1526 } 1527 1528 return (0); 1529 1530encap_fail: 1531 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1532 return (error); 1533} 1534 1535/********************************************************************* 1536 * 1537 * 82547 workaround to avoid controller hang in half-duplex environment. 1538 * The workaround is to avoid queuing a large packet that would span 1539 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1540 * in this case. We do that only when FIFO is quiescent. 1541 * 1542 **********************************************************************/ 1543static void 1544em_82547_move_tail_locked(struct em_softc *sc) 1545{ 1546 uint16_t hw_tdt; 1547 uint16_t sw_tdt; 1548 struct em_tx_desc *tx_desc; 1549 uint16_t length = 0; 1550 boolean_t eop = 0; 1551 1552 EM_LOCK_ASSERT(sc); 1553 1554 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1555 sw_tdt = sc->next_avail_tx_desc; 1556 1557 while (hw_tdt != sw_tdt) { 1558 tx_desc = &sc->tx_desc_base[hw_tdt]; 1559 length += tx_desc->lower.flags.length; 1560 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1561 if(++hw_tdt == sc->num_tx_desc) 1562 hw_tdt = 0; 1563 1564 if (eop) { 1565 if (em_82547_fifo_workaround(sc, length)) { 1566 sc->tx_fifo_wrk_cnt++; 1567 callout_reset(&sc->tx_fifo_timer, 1, 1568 em_82547_move_tail, sc); 1569 break; 1570 } 1571 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1572 em_82547_update_fifo_head(sc, length); 1573 length = 0; 1574 } 1575 } 1576} 1577 1578static void 1579em_82547_move_tail(void *arg) 1580{ 1581 struct em_softc *sc = arg; 1582 1583 EM_LOCK(sc); 1584 em_82547_move_tail_locked(sc); 1585 EM_UNLOCK(sc); 1586} 1587 1588static int 1589em_82547_fifo_workaround(struct em_softc *sc, int len) 1590{ 1591 int fifo_space, fifo_pkt_len; 1592 1593 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1594 1595 if (sc->link_duplex == HALF_DUPLEX) { 1596 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1597 1598 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1599 if (em_82547_tx_fifo_reset(sc)) 1600 return (0); 1601 else 1602 return (1); 1603 } 1604 } 1605 1606 return (0); 1607} 1608 1609static void 1610em_82547_update_fifo_head(struct em_softc *sc, int len) 1611{ 1612 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1613 1614 /* tx_fifo_head is always 16 byte aligned */ 1615 sc->tx_fifo_head += fifo_pkt_len; 1616 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1617 sc->tx_fifo_head -= sc->tx_fifo_size; 1618 } 1619} 1620 1621 1622static int 1623em_82547_tx_fifo_reset(struct em_softc *sc) 1624{ 1625 uint32_t tctl; 1626 1627 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1628 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1629 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1630 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1631 1632 /* Disable TX unit */ 1633 tctl = E1000_READ_REG(&sc->hw, TCTL); 1634 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1635 1636 /* Reset FIFO pointers */ 1637 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1638 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1639 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1640 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1641 1642 /* Re-enable TX unit */ 1643 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1644 E1000_WRITE_FLUSH(&sc->hw); 1645 1646 sc->tx_fifo_head = 0; 1647 sc->tx_fifo_reset_cnt++; 1648 1649 return (TRUE); 1650 } 1651 else { 1652 return (FALSE); 1653 } 1654} 1655 1656static void 1657em_set_promisc(struct em_softc *sc) 1658{ 1659 struct ifnet *ifp = sc->ifp; 1660 uint32_t reg_rctl; 1661 1662 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1663 1664 if (ifp->if_flags & IFF_PROMISC) { 1665 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1666 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1667 /* Disable VLAN stripping in promiscous mode 1668 * This enables bridging of vlan tagged frames to occur 1669 * and also allows vlan tags to be seen in tcpdump 1670 */ 1671 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1672 em_disable_vlans(sc); 1673 sc->em_insert_vlan_header = 1; 1674 } else if (ifp->if_flags & IFF_ALLMULTI) { 1675 reg_rctl |= E1000_RCTL_MPE; 1676 reg_rctl &= ~E1000_RCTL_UPE; 1677 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1678 sc->em_insert_vlan_header = 0; 1679 } else 1680 sc->em_insert_vlan_header = 0; 1681} 1682 1683static void 1684em_disable_promisc(struct em_softc *sc) 1685{ 1686 struct ifnet *ifp = sc->ifp; 1687 uint32_t reg_rctl; 1688 1689 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1690 1691 reg_rctl &= (~E1000_RCTL_UPE); 1692 reg_rctl &= (~E1000_RCTL_MPE); 1693 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1694 1695 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1696 em_enable_vlans(sc); 1697 sc->em_insert_vlan_header = 0; 1698} 1699 1700 1701/********************************************************************* 1702 * Multicast Update 1703 * 1704 * This routine is called whenever multicast address list is updated. 1705 * 1706 **********************************************************************/ 1707 1708static void 1709em_set_multi(struct em_softc *sc) 1710{ 1711 struct ifnet *ifp = sc->ifp; 1712 struct ifmultiaddr *ifma; 1713 uint32_t reg_rctl = 0; 1714 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1715 int mcnt = 0; 1716 1717 IOCTL_DEBUGOUT("em_set_multi: begin"); 1718 1719 if (sc->hw.mac_type == em_82542_rev2_0) { 1720 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1721 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1722 em_pci_clear_mwi(&sc->hw); 1723 reg_rctl |= E1000_RCTL_RST; 1724 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1725 msec_delay(5); 1726 } 1727 1728 IF_ADDR_LOCK(ifp); 1729 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1730 if (ifma->ifma_addr->sa_family != AF_LINK) 1731 continue; 1732 1733 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1734 break; 1735 1736 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1737 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1738 mcnt++; 1739 } 1740 IF_ADDR_UNLOCK(ifp); 1741 1742 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1743 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1744 reg_rctl |= E1000_RCTL_MPE; 1745 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1746 } else 1747 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1748 1749 if (sc->hw.mac_type == em_82542_rev2_0) { 1750 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1751 reg_rctl &= ~E1000_RCTL_RST; 1752 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1753 msec_delay(5); 1754 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1755 em_pci_set_mwi(&sc->hw); 1756 } 1757} 1758 1759 1760/********************************************************************* 1761 * Timer routine 1762 * 1763 * This routine checks for link status and updates statistics. 1764 * 1765 **********************************************************************/ 1766 1767static void 1768em_local_timer(void *arg) 1769{ 1770 struct em_softc *sc = arg; 1771 struct ifnet *ifp = sc->ifp; 1772 1773 EM_LOCK(sc); 1774 1775 em_check_for_link(&sc->hw); 1776 em_update_link_status(sc); 1777 em_update_stats_counters(sc); 1778 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1779 em_print_hw_stats(sc); 1780 em_smartspeed(sc); 1781 1782 callout_reset(&sc->timer, hz, em_local_timer, sc); 1783 1784 EM_UNLOCK(sc); 1785} 1786 1787static void 1788em_update_link_status(struct em_softc *sc) 1789{ 1790 struct ifnet *ifp = sc->ifp; 1791 device_t dev = sc->dev; 1792 1793 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1794 if (sc->link_active == 0) { 1795 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1796 &sc->link_duplex); 1797 if (bootverbose) 1798 device_printf(dev, "Link is up %d Mbps %s\n", 1799 sc->link_speed, 1800 ((sc->link_duplex == FULL_DUPLEX) ? 1801 "Full Duplex" : "Half Duplex")); 1802 sc->link_active = 1; 1803 sc->smartspeed = 0; 1804 ifp->if_baudrate = sc->link_speed * 1000000; 1805 if_link_state_change(ifp, LINK_STATE_UP); 1806 } 1807 } else { 1808 if (sc->link_active == 1) { 1809 ifp->if_baudrate = sc->link_speed = 0; 1810 sc->link_duplex = 0; 1811 if (bootverbose) 1812 device_printf(dev, "Link is Down\n"); 1813 sc->link_active = 0; 1814 if_link_state_change(ifp, LINK_STATE_DOWN); 1815 } 1816 } 1817} 1818 1819/********************************************************************* 1820 * 1821 * This routine disables all traffic on the adapter by issuing a 1822 * global reset on the MAC and deallocates TX/RX buffers. 1823 * 1824 **********************************************************************/ 1825 1826static void 1827em_stop(void *arg) 1828{ 1829 struct em_softc *sc = arg; 1830 struct ifnet *ifp = sc->ifp; 1831 1832 EM_LOCK_ASSERT(sc); 1833 1834 INIT_DEBUGOUT("em_stop: begin"); 1835 1836 em_disable_intr(sc); 1837 em_reset_hw(&sc->hw); 1838 callout_stop(&sc->timer); 1839 callout_stop(&sc->tx_fifo_timer); 1840 em_free_transmit_structures(sc); 1841 em_free_receive_structures(sc); 1842 1843 /* Tell the stack that the interface is no longer active */ 1844 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1845} 1846 1847 1848/********************************************************************* 1849 * 1850 * Determine hardware revision. 1851 * 1852 **********************************************************************/ 1853static void 1854em_identify_hardware(struct em_softc *sc) 1855{ 1856 device_t dev = sc->dev; 1857 1858 /* Make sure our PCI config space has the necessary stuff set */ 1859 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1860 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1861 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1862 device_printf(dev, "Memory Access and/or Bus Master bits " 1863 "were not set!\n"); 1864 sc->hw.pci_cmd_word |= 1865 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1866 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1867 } 1868 1869 /* Save off the information about this board */ 1870 sc->hw.vendor_id = pci_get_vendor(dev); 1871 sc->hw.device_id = pci_get_device(dev); 1872 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1873 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1874 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1875 1876 /* Identify the MAC */ 1877 if (em_set_mac_type(&sc->hw)) 1878 device_printf(dev, "Unknown MAC Type\n"); 1879 1880 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1881 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1882 sc->hw.phy_init_script = TRUE; 1883} 1884 1885static int 1886em_allocate_pci_resources(struct em_softc *sc) 1887{ 1888 device_t dev = sc->dev; 1889 int val, rid; 1890 1891 rid = PCIR_BAR(0); 1892 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1893 &rid, RF_ACTIVE); 1894 if (sc->res_memory == NULL) { 1895 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1896 return (ENXIO); 1897 } 1898 sc->osdep.mem_bus_space_tag = 1899 rman_get_bustag(sc->res_memory); 1900 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1901 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1902 1903 if (sc->hw.mac_type > em_82543) { 1904 /* Figure our where our IO BAR is ? */ 1905 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1906 val = pci_read_config(dev, rid, 4); 1907 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1908 sc->io_rid = rid; 1909 break; 1910 } 1911 rid += 4; 1912 /* check for 64bit BAR */ 1913 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1914 rid += 4; 1915 } 1916 if (rid >= PCIR_CIS) { 1917 device_printf(dev, "Unable to locate IO BAR\n"); 1918 return (ENXIO); 1919 } 1920 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1921 &sc->io_rid, RF_ACTIVE); 1922 if (sc->res_ioport == NULL) { 1923 device_printf(dev, "Unable to allocate bus resource: " 1924 "ioport\n"); 1925 return (ENXIO); 1926 } 1927 sc->hw.io_base = 0; 1928 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1929 sc->osdep.io_bus_space_handle = 1930 rman_get_bushandle(sc->res_ioport); 1931 } 1932 1933 rid = 0x0; 1934 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1935 RF_SHAREABLE | RF_ACTIVE); 1936 if (sc->res_interrupt == NULL) { 1937 device_printf(dev, "Unable to allocate bus resource: " 1938 "interrupt\n"); 1939 return (ENXIO); 1940 } 1941 1942 sc->hw.back = &sc->osdep; 1943 1944 return (0); 1945} 1946 1947int 1948em_allocate_intr(struct em_softc *sc) 1949{ 1950 device_t dev = sc->dev; 1951 int error; 1952 1953 /* Manually turn off all interrupts */ 1954 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1955 1956 /* 1957 * Try allocating a fast interrupt and the associated deferred 1958 * processing contexts. If that doesn't work, try just using an 1959 * ithread. 1960 */ 1961#ifndef NO_EM_FASTINTR 1962 /* Init the deferred processing contexts. */ 1963 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1964 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1965 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1966 taskqueue_thread_enqueue, &sc->tq); 1967 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1968 device_get_nameunit(sc->dev)); 1969 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1970 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 1971 &sc->int_handler_tag)) != 0) { 1972 device_printf(dev, "Failed to register fast interrupt " 1973 "handler: %d\n", error); 1974 taskqueue_free(sc->tq); 1975 sc->tq = NULL; 1976 } 1977#endif 1978 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 1979 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 1980 &sc->int_handler_tag)) != 0) { 1981 device_printf(dev, "Failed to register interrupt handler"); 1982 return (error); 1983 } 1984 1985 em_enable_intr(sc); 1986 return (0); 1987} 1988 1989static void 1990em_free_intr(struct em_softc *sc) 1991{ 1992 device_t dev = sc->dev; 1993 1994 if (sc->res_interrupt != NULL) { 1995 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 1996 sc->int_handler_tag = NULL; 1997 } 1998 if (sc->tq != NULL) { 1999 taskqueue_drain(sc->tq, &sc->rxtx_task); 2000 taskqueue_drain(taskqueue_fast, &sc->link_task); 2001 taskqueue_free(sc->tq); 2002 sc->tq = NULL; 2003 } 2004} 2005 2006static void 2007em_free_pci_resources(struct em_softc *sc) 2008{ 2009 device_t dev = sc->dev; 2010 2011 if (sc->res_interrupt != NULL) 2012 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2013 2014 if (sc->res_memory != NULL) 2015 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2016 sc->res_memory); 2017 2018 if (sc->res_ioport != NULL) 2019 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2020 sc->res_ioport); 2021} 2022 2023/********************************************************************* 2024 * 2025 * Initialize the hardware to a configuration as specified by the 2026 * adapter structure. The controller is reset, the EEPROM is 2027 * verified, the MAC address is set, then the shared initialization 2028 * routines are called. 2029 * 2030 **********************************************************************/ 2031static int 2032em_hardware_init(struct em_softc *sc) 2033{ 2034 device_t dev = sc->dev; 2035 uint16_t rx_buffer_size; 2036 2037 INIT_DEBUGOUT("em_hardware_init: begin"); 2038 /* Issue a global reset */ 2039 em_reset_hw(&sc->hw); 2040 2041 /* When hardware is reset, fifo_head is also reset */ 2042 sc->tx_fifo_head = 0; 2043 2044 /* Make sure we have a good EEPROM before we read from it */ 2045 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2046 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2047 return (EIO); 2048 } 2049 2050 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2051 device_printf(dev, "EEPROM read error while reading part " 2052 "number\n"); 2053 return (EIO); 2054 } 2055 2056 /* 2057 * These parameters control the automatic generation (Tx) and 2058 * response (Rx) to Ethernet PAUSE frames. 2059 * - High water mark should allow for at least two frames to be 2060 * received after sending an XOFF. 2061 * - Low water mark works best when it is very near the high water mark. 2062 * This allows the receiver to restart by sending XON when it has 2063 * drained a bit. Here we use an arbitary value of 1500 which will 2064 * restart after one full frame is pulled from the buffer. There 2065 * could be several smaller frames in the buffer and if so they will 2066 * not trigger the XON until their total number reduces the buffer 2067 * by 1500. 2068 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2069 */ 2070 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2071 2072 sc->hw.fc_high_water = rx_buffer_size - 2073 roundup2(sc->hw.max_frame_size, 1024); 2074 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2075 sc->hw.fc_pause_time = 0x1000; 2076 sc->hw.fc_send_xon = TRUE; 2077 sc->hw.fc = em_fc_full; 2078 2079 if (em_init_hw(&sc->hw) < 0) { 2080 device_printf(dev, "Hardware Initialization Failed"); 2081 return (EIO); 2082 } 2083 2084 em_check_for_link(&sc->hw); 2085 2086 return (0); 2087} 2088 2089/********************************************************************* 2090 * 2091 * Setup networking device structure and register an interface. 2092 * 2093 **********************************************************************/ 2094static void 2095em_setup_interface(device_t dev, struct em_softc *sc) 2096{ 2097 struct ifnet *ifp; 2098 INIT_DEBUGOUT("em_setup_interface: begin"); 2099 2100 ifp = sc->ifp = if_alloc(IFT_ETHER); 2101 if (ifp == NULL) 2102 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2103 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2104 ifp->if_mtu = ETHERMTU; 2105 ifp->if_init = em_init; 2106 ifp->if_softc = sc; 2107 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2108 ifp->if_ioctl = em_ioctl; 2109 ifp->if_start = em_start; 2110 ifp->if_watchdog = em_watchdog; 2111 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2112 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2113 IFQ_SET_READY(&ifp->if_snd); 2114 2115 ether_ifattach(ifp, sc->hw.mac_addr); 2116 2117 ifp->if_capabilities = ifp->if_capenable = 0; 2118 2119 if (sc->hw.mac_type >= em_82543) { 2120 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2121 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2122 } 2123 2124 /* 2125 * Tell the upper layer(s) we support long frames. 2126 */ 2127 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2128 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2129 ifp->if_capenable |= IFCAP_VLAN_MTU; 2130 2131#ifdef DEVICE_POLLING 2132 ifp->if_capabilities |= IFCAP_POLLING; 2133#endif 2134 2135 /* 2136 * Specify the media types supported by this adapter and register 2137 * callbacks to update media and link information 2138 */ 2139 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2140 if (sc->hw.media_type == em_media_type_fiber) { 2141 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2142 0, NULL); 2143 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2144 0, NULL); 2145 } else { 2146 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2147 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2148 0, NULL); 2149 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2150 0, NULL); 2151 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2152 0, NULL); 2153 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2154 0, NULL); 2155 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2156 } 2157 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2158 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2159} 2160 2161 2162/********************************************************************* 2163 * 2164 * Workaround for SmartSpeed on 82541 and 82547 controllers 2165 * 2166 **********************************************************************/ 2167static void 2168em_smartspeed(struct em_softc *sc) 2169{ 2170 uint16_t phy_tmp; 2171 2172 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2173 sc->hw.autoneg == 0 || 2174 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2175 return; 2176 2177 if (sc->smartspeed == 0) { 2178 /* If Master/Slave config fault is asserted twice, 2179 * we assume back-to-back */ 2180 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2181 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2182 return; 2183 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2184 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2185 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2186 if(phy_tmp & CR_1000T_MS_ENABLE) { 2187 phy_tmp &= ~CR_1000T_MS_ENABLE; 2188 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2189 phy_tmp); 2190 sc->smartspeed++; 2191 if(sc->hw.autoneg && 2192 !em_phy_setup_autoneg(&sc->hw) && 2193 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2194 &phy_tmp)) { 2195 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2196 MII_CR_RESTART_AUTO_NEG); 2197 em_write_phy_reg(&sc->hw, PHY_CTRL, 2198 phy_tmp); 2199 } 2200 } 2201 } 2202 return; 2203 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2204 /* If still no link, perhaps using 2/3 pair cable */ 2205 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2206 phy_tmp |= CR_1000T_MS_ENABLE; 2207 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2208 if(sc->hw.autoneg && 2209 !em_phy_setup_autoneg(&sc->hw) && 2210 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2211 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2212 MII_CR_RESTART_AUTO_NEG); 2213 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2214 } 2215 } 2216 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2217 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2218 sc->smartspeed = 0; 2219} 2220 2221 2222/* 2223 * Manage DMA'able memory. 2224 */ 2225static void 2226em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2227{ 2228 if (error) 2229 return; 2230 *(bus_addr_t *) arg = segs[0].ds_addr; 2231} 2232 2233static int 2234em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2235 int mapflags) 2236{ 2237 int error; 2238 2239 error = bus_dma_tag_create(NULL, /* parent */ 2240 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2241 BUS_SPACE_MAXADDR, /* lowaddr */ 2242 BUS_SPACE_MAXADDR, /* highaddr */ 2243 NULL, NULL, /* filter, filterarg */ 2244 size, /* maxsize */ 2245 1, /* nsegments */ 2246 size, /* maxsegsize */ 2247 0, /* flags */ 2248 NULL, /* lockfunc */ 2249 NULL, /* lockarg */ 2250 &dma->dma_tag); 2251 if (error) { 2252 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2253 __func__, error); 2254 goto fail_0; 2255 } 2256 2257 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2258 BUS_DMA_NOWAIT, &dma->dma_map); 2259 if (error) { 2260 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2261 __func__, (uintmax_t)size, error); 2262 goto fail_2; 2263 } 2264 2265 dma->dma_paddr = 0; 2266 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2267 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2268 if (error || dma->dma_paddr == 0) { 2269 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2270 __func__, error); 2271 goto fail_3; 2272 } 2273 2274 return (0); 2275 2276fail_3: 2277 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2278fail_2: 2279 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2280 bus_dma_tag_destroy(dma->dma_tag); 2281fail_0: 2282 dma->dma_map = NULL; 2283 dma->dma_tag = NULL; 2284 2285 return (error); 2286} 2287 2288static void 2289em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2290{ 2291 if (dma->dma_tag == NULL) 2292 return; 2293 if (dma->dma_map != NULL) { 2294 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2295 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2296 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2297 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2298 dma->dma_map = NULL; 2299 } 2300 bus_dma_tag_destroy(dma->dma_tag); 2301 dma->dma_tag = NULL; 2302} 2303 2304 2305/********************************************************************* 2306 * 2307 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2308 * the information needed to transmit a packet on the wire. 2309 * 2310 **********************************************************************/ 2311static int 2312em_allocate_transmit_structures(struct em_softc *sc) 2313{ 2314 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2315 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2316 if (sc->tx_buffer_area == NULL) { 2317 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2318 return (ENOMEM); 2319 } 2320 2321 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2322 2323 return (0); 2324} 2325 2326/********************************************************************* 2327 * 2328 * Allocate and initialize transmit structures. 2329 * 2330 **********************************************************************/ 2331static int 2332em_setup_transmit_structures(struct em_softc *sc) 2333{ 2334 device_t dev = sc->dev; 2335 struct em_buffer *tx_buffer; 2336 bus_size_t size; 2337 int error, i; 2338 2339 /* 2340 * Setup DMA descriptor areas. 2341 */ 2342 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2343 if ((error = bus_dma_tag_create(NULL, /* parent */ 2344 1, 0, /* alignment, bounds */ 2345 BUS_SPACE_MAXADDR, /* lowaddr */ 2346 BUS_SPACE_MAXADDR, /* highaddr */ 2347 NULL, NULL, /* filter, filterarg */ 2348 size, /* maxsize */ 2349 EM_MAX_SCATTER, /* nsegments */ 2350 size, /* maxsegsize */ 2351 0, /* flags */ 2352 NULL, /* lockfunc */ 2353 NULL, /* lockarg */ 2354 &sc->txtag)) != 0) { 2355 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2356 goto fail; 2357 } 2358 2359 if ((error = em_allocate_transmit_structures(sc)) != 0) 2360 goto fail; 2361 2362 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2363 tx_buffer = sc->tx_buffer_area; 2364 for (i = 0; i < sc->num_tx_desc; i++) { 2365 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2366 if (error != 0) { 2367 device_printf(dev, "Unable to create TX DMA map\n"); 2368 goto fail; 2369 } 2370 tx_buffer++; 2371 } 2372 2373 sc->next_avail_tx_desc = 0; 2374 sc->oldest_used_tx_desc = 0; 2375 2376 /* Set number of descriptors available */ 2377 sc->num_tx_desc_avail = sc->num_tx_desc; 2378 2379 /* Set checksum context */ 2380 sc->active_checksum_context = OFFLOAD_NONE; 2381 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2383 2384 return (0); 2385 2386fail: 2387 em_free_transmit_structures(sc); 2388 return (error); 2389} 2390 2391/********************************************************************* 2392 * 2393 * Enable transmit unit. 2394 * 2395 **********************************************************************/ 2396static void 2397em_initialize_transmit_unit(struct em_softc *sc) 2398{ 2399 uint32_t reg_tctl; 2400 uint32_t reg_tipg = 0; 2401 uint64_t bus_addr; 2402 2403 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2404 /* Setup the Base and Length of the Tx Descriptor Ring */ 2405 bus_addr = sc->txdma.dma_paddr; 2406 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2407 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2408 E1000_WRITE_REG(&sc->hw, TDLEN, 2409 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2410 2411 /* Setup the HW Tx Head and Tail descriptor pointers */ 2412 E1000_WRITE_REG(&sc->hw, TDH, 0); 2413 E1000_WRITE_REG(&sc->hw, TDT, 0); 2414 2415 2416 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2417 E1000_READ_REG(&sc->hw, TDLEN)); 2418 2419 /* Set the default values for the Tx Inter Packet Gap timer */ 2420 switch (sc->hw.mac_type) { 2421 case em_82542_rev2_0: 2422 case em_82542_rev2_1: 2423 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2424 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2425 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2426 break; 2427 default: 2428 if (sc->hw.media_type == em_media_type_fiber) 2429 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2430 else 2431 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2432 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2433 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2434 } 2435 2436 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2437 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2438 if(sc->hw.mac_type >= em_82540) 2439 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2440 2441 /* Program the Transmit Control Register */ 2442 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2443 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2444 if (sc->hw.mac_type >= em_82571) 2445 reg_tctl |= E1000_TCTL_MULR; 2446 if (sc->link_duplex == 1) { 2447 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2448 } else { 2449 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2450 } 2451 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2452 2453 /* Setup Transmit Descriptor Settings for this adapter */ 2454 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2455 2456 if (sc->tx_int_delay.value > 0) 2457 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2458} 2459 2460/********************************************************************* 2461 * 2462 * Free all transmit related data structures. 2463 * 2464 **********************************************************************/ 2465static void 2466em_free_transmit_structures(struct em_softc *sc) 2467{ 2468 struct em_buffer *tx_buffer; 2469 int i; 2470 2471 INIT_DEBUGOUT("free_transmit_structures: begin"); 2472 2473 if (sc->tx_buffer_area != NULL) { 2474 tx_buffer = sc->tx_buffer_area; 2475 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2476 if (tx_buffer->m_head != NULL) { 2477 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2478 BUS_DMASYNC_POSTWRITE); 2479 bus_dmamap_unload(sc->txtag, 2480 tx_buffer->map); 2481 m_freem(tx_buffer->m_head); 2482 tx_buffer->m_head = NULL; 2483 } else if (tx_buffer->map != NULL) 2484 bus_dmamap_unload(sc->txtag, 2485 tx_buffer->map); 2486 if (tx_buffer->map != NULL) { 2487 bus_dmamap_destroy(sc->txtag, 2488 tx_buffer->map); 2489 tx_buffer->map = NULL; 2490 } 2491 } 2492 } 2493 if (sc->tx_buffer_area != NULL) { 2494 free(sc->tx_buffer_area, M_DEVBUF); 2495 sc->tx_buffer_area = NULL; 2496 } 2497 if (sc->txtag != NULL) { 2498 bus_dma_tag_destroy(sc->txtag); 2499 sc->txtag = NULL; 2500 } 2501} 2502 2503/********************************************************************* 2504 * 2505 * The offload context needs to be set when we transfer the first 2506 * packet of a particular protocol (TCP/UDP). We change the 2507 * context only if the protocol type changes. 2508 * 2509 **********************************************************************/ 2510static void 2511em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2512 uint32_t *txd_upper, uint32_t *txd_lower) 2513{ 2514 struct em_context_desc *TXD; 2515 struct em_buffer *tx_buffer; 2516 int curr_txd; 2517 2518 if (mp->m_pkthdr.csum_flags) { 2519 2520 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2521 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2522 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2523 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2524 return; 2525 else 2526 sc->active_checksum_context = OFFLOAD_TCP_IP; 2527 2528 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2529 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2530 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2531 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2532 return; 2533 else 2534 sc->active_checksum_context = OFFLOAD_UDP_IP; 2535 } else { 2536 *txd_upper = 0; 2537 *txd_lower = 0; 2538 return; 2539 } 2540 } else { 2541 *txd_upper = 0; 2542 *txd_lower = 0; 2543 return; 2544 } 2545 2546 /* If we reach this point, the checksum offload context 2547 * needs to be reset. 2548 */ 2549 curr_txd = sc->next_avail_tx_desc; 2550 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2551 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2552 2553 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2554 TXD->lower_setup.ip_fields.ipcso = 2555 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2556 TXD->lower_setup.ip_fields.ipcse = 2557 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2558 2559 TXD->upper_setup.tcp_fields.tucss = 2560 ETHER_HDR_LEN + sizeof(struct ip); 2561 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2562 2563 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2564 TXD->upper_setup.tcp_fields.tucso = 2565 ETHER_HDR_LEN + sizeof(struct ip) + 2566 offsetof(struct tcphdr, th_sum); 2567 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2568 TXD->upper_setup.tcp_fields.tucso = 2569 ETHER_HDR_LEN + sizeof(struct ip) + 2570 offsetof(struct udphdr, uh_sum); 2571 } 2572 2573 TXD->tcp_seg_setup.data = htole32(0); 2574 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2575 2576 tx_buffer->m_head = NULL; 2577 2578 if (++curr_txd == sc->num_tx_desc) 2579 curr_txd = 0; 2580 2581 sc->num_tx_desc_avail--; 2582 sc->next_avail_tx_desc = curr_txd; 2583} 2584 2585/********************************************************************** 2586 * 2587 * Examine each tx_buffer in the used queue. If the hardware is done 2588 * processing the packet then free associated resources. The 2589 * tx_buffer is put back on the free queue. 2590 * 2591 **********************************************************************/ 2592static void 2593em_txeof(struct em_softc *sc) 2594{ 2595 int i, num_avail; 2596 struct em_buffer *tx_buffer; 2597 struct em_tx_desc *tx_desc; 2598 struct ifnet *ifp = sc->ifp; 2599 2600 EM_LOCK_ASSERT(sc); 2601 2602 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2603 return; 2604 2605 num_avail = sc->num_tx_desc_avail; 2606 i = sc->oldest_used_tx_desc; 2607 2608 tx_buffer = &sc->tx_buffer_area[i]; 2609 tx_desc = &sc->tx_desc_base[i]; 2610 2611 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2612 BUS_DMASYNC_POSTREAD); 2613 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2614 2615 tx_desc->upper.data = 0; 2616 num_avail++; 2617 2618 if (tx_buffer->m_head) { 2619 ifp->if_opackets++; 2620 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2621 BUS_DMASYNC_POSTWRITE); 2622 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2623 2624 m_freem(tx_buffer->m_head); 2625 tx_buffer->m_head = NULL; 2626 } 2627 2628 if (++i == sc->num_tx_desc) 2629 i = 0; 2630 2631 tx_buffer = &sc->tx_buffer_area[i]; 2632 tx_desc = &sc->tx_desc_base[i]; 2633 } 2634 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2635 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2636 2637 sc->oldest_used_tx_desc = i; 2638 2639 /* 2640 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2641 * that it is OK to send packets. 2642 * If there are no pending descriptors, clear the timeout. Otherwise, 2643 * if some descriptors have been freed, restart the timeout. 2644 */ 2645 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2646 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2647 if (num_avail == sc->num_tx_desc) 2648 ifp->if_timer = 0; 2649 else if (num_avail != sc->num_tx_desc_avail) 2650 ifp->if_timer = EM_TX_TIMEOUT; 2651 } 2652 sc->num_tx_desc_avail = num_avail; 2653} 2654 2655/********************************************************************* 2656 * 2657 * Get a buffer from system mbuf buffer pool. 2658 * 2659 **********************************************************************/ 2660static int 2661em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2662{ 2663 struct ifnet *ifp = sc->ifp; 2664 bus_dma_segment_t segs[1]; 2665 struct em_buffer *rx_buffer; 2666 int error, nsegs; 2667 2668 if (mp == NULL) { 2669 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2670 if (mp == NULL) { 2671 sc->mbuf_cluster_failed++; 2672 return (ENOBUFS); 2673 } 2674 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2675 } else { 2676 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2677 mp->m_data = mp->m_ext.ext_buf; 2678 mp->m_next = NULL; 2679 } 2680 2681 if (ifp->if_mtu <= ETHERMTU) 2682 m_adj(mp, ETHER_ALIGN); 2683 2684 rx_buffer = &sc->rx_buffer_area[i]; 2685 2686 /* 2687 * Using memory from the mbuf cluster pool, invoke the 2688 * bus_dma machinery to arrange the memory mapping. 2689 */ 2690 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2691 mp, segs, &nsegs, 0); 2692 if (error != 0) { 2693 m_free(mp); 2694 return (error); 2695 } 2696 /* If nsegs is wrong then the stack is corrupt. */ 2697 KASSERT(nsegs == 1, ("Too many segments returned!")); 2698 rx_buffer->m_head = mp; 2699 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2700 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2701 2702 return (0); 2703} 2704 2705/********************************************************************* 2706 * 2707 * Allocate memory for rx_buffer structures. Since we use one 2708 * rx_buffer per received packet, the maximum number of rx_buffer's 2709 * that we'll need is equal to the number of receive descriptors 2710 * that we've allocated. 2711 * 2712 **********************************************************************/ 2713static int 2714em_allocate_receive_structures(struct em_softc *sc) 2715{ 2716 device_t dev = sc->dev; 2717 struct em_buffer *rx_buffer; 2718 int i, error; 2719 2720 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2721 M_DEVBUF, M_NOWAIT); 2722 if (sc->rx_buffer_area == NULL) { 2723 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2724 return (ENOMEM); 2725 } 2726 2727 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2728 2729 error = bus_dma_tag_create(NULL, /* parent */ 2730 1, 0, /* alignment, bounds */ 2731 BUS_SPACE_MAXADDR, /* lowaddr */ 2732 BUS_SPACE_MAXADDR, /* highaddr */ 2733 NULL, NULL, /* filter, filterarg */ 2734 MCLBYTES, /* maxsize */ 2735 1, /* nsegments */ 2736 MCLBYTES, /* maxsegsize */ 2737 BUS_DMA_ALLOCNOW, /* flags */ 2738 NULL, /* lockfunc */ 2739 NULL, /* lockarg */ 2740 &sc->rxtag); 2741 if (error) { 2742 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2743 __func__, error); 2744 goto fail; 2745 } 2746 2747 rx_buffer = sc->rx_buffer_area; 2748 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2749 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2750 &rx_buffer->map); 2751 if (error) { 2752 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2753 __func__, error); 2754 goto fail; 2755 } 2756 } 2757 2758 for (i = 0; i < sc->num_rx_desc; i++) { 2759 error = em_get_buf(i, sc, NULL); 2760 if (error) 2761 goto fail; 2762 } 2763 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2764 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2765 2766 return (0); 2767 2768fail: 2769 em_free_receive_structures(sc); 2770 return (error); 2771} 2772 2773/********************************************************************* 2774 * 2775 * Allocate and initialize receive structures. 2776 * 2777 **********************************************************************/ 2778static int 2779em_setup_receive_structures(struct em_softc *sc) 2780{ 2781 int error; 2782 2783 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2784 2785 if ((error = em_allocate_receive_structures(sc)) != 0) 2786 return (error); 2787 2788 /* Setup our descriptor pointers */ 2789 sc->next_rx_desc_to_check = 0; 2790 2791 return (0); 2792} 2793 2794/********************************************************************* 2795 * 2796 * Enable receive unit. 2797 * 2798 **********************************************************************/ 2799static void 2800em_initialize_receive_unit(struct em_softc *sc) 2801{ 2802 struct ifnet *ifp = sc->ifp; 2803 uint64_t bus_addr; 2804 uint32_t reg_rctl; 2805 uint32_t reg_rxcsum; 2806 2807 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2808 2809 /* 2810 * Make sure receives are disabled while setting 2811 * up the descriptor ring 2812 */ 2813 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2814 2815 /* Set the Receive Delay Timer Register */ 2816 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2817 2818 if(sc->hw.mac_type >= em_82540) { 2819 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2820 2821 /* 2822 * Set the interrupt throttling rate. Value is calculated 2823 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2824 */ 2825#define MAX_INTS_PER_SEC 8000 2826#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2827 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2828 } 2829 2830 /* Setup the Base and Length of the Rx Descriptor Ring */ 2831 bus_addr = sc->rxdma.dma_paddr; 2832 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2833 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2834 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2835 sizeof(struct em_rx_desc)); 2836 2837 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2838 E1000_WRITE_REG(&sc->hw, RDH, 0); 2839 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2840 2841 /* Setup the Receive Control Register */ 2842 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2843 E1000_RCTL_RDMTS_HALF | 2844 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2845 2846 if (sc->hw.tbi_compatibility_on == TRUE) 2847 reg_rctl |= E1000_RCTL_SBP; 2848 2849 2850 switch (sc->rx_buffer_len) { 2851 default: 2852 case EM_RXBUFFER_2048: 2853 reg_rctl |= E1000_RCTL_SZ_2048; 2854 break; 2855 case EM_RXBUFFER_4096: 2856 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2857 break; 2858 case EM_RXBUFFER_8192: 2859 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2860 break; 2861 case EM_RXBUFFER_16384: 2862 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2863 break; 2864 } 2865 2866 if (ifp->if_mtu > ETHERMTU) 2867 reg_rctl |= E1000_RCTL_LPE; 2868 2869 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2870 if ((sc->hw.mac_type >= em_82543) && 2871 (ifp->if_capenable & IFCAP_RXCSUM)) { 2872 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2873 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2874 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2875 } 2876 2877 /* Enable Receives */ 2878 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2879} 2880 2881/********************************************************************* 2882 * 2883 * Free receive related data structures. 2884 * 2885 **********************************************************************/ 2886static void 2887em_free_receive_structures(struct em_softc *sc) 2888{ 2889 struct em_buffer *rx_buffer; 2890 int i; 2891 2892 INIT_DEBUGOUT("free_receive_structures: begin"); 2893 2894 if (sc->rx_buffer_area != NULL) { 2895 rx_buffer = sc->rx_buffer_area; 2896 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2897 if (rx_buffer->m_head != NULL) { 2898 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2899 BUS_DMASYNC_POSTREAD); 2900 bus_dmamap_unload(sc->rxtag, 2901 rx_buffer->map); 2902 m_freem(rx_buffer->m_head); 2903 rx_buffer->m_head = NULL; 2904 } else if (rx_buffer->map != NULL) 2905 bus_dmamap_unload(sc->rxtag, 2906 rx_buffer->map); 2907 if (rx_buffer->map != NULL) { 2908 bus_dmamap_destroy(sc->rxtag, 2909 rx_buffer->map); 2910 rx_buffer->map = NULL; 2911 } 2912 } 2913 } 2914 if (sc->rx_buffer_area != NULL) { 2915 free(sc->rx_buffer_area, M_DEVBUF); 2916 sc->rx_buffer_area = NULL; 2917 } 2918 if (sc->rxtag != NULL) { 2919 bus_dma_tag_destroy(sc->rxtag); 2920 sc->rxtag = NULL; 2921 } 2922} 2923 2924/********************************************************************* 2925 * 2926 * This routine executes in interrupt context. It replenishes 2927 * the mbufs in the descriptor and sends data which has been 2928 * dma'ed into host memory to upper layer. 2929 * 2930 * We loop at most count times if count is > 0, or until done if 2931 * count < 0. 2932 * 2933 *********************************************************************/ 2934static int 2935em_rxeof(struct em_softc *sc, int count) 2936{ 2937 struct ifnet *ifp; 2938 struct mbuf *mp; 2939 uint8_t accept_frame = 0; 2940 uint8_t eop = 0; 2941 uint16_t len, desc_len, prev_len_adj; 2942 int i; 2943 2944 /* Pointer to the receive descriptor being examined. */ 2945 struct em_rx_desc *current_desc; 2946 2947 ifp = sc->ifp; 2948 i = sc->next_rx_desc_to_check; 2949 current_desc = &sc->rx_desc_base[i]; 2950 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2951 BUS_DMASYNC_POSTREAD); 2952 2953 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 2954 return (0); 2955 2956 while ((current_desc->status & E1000_RXD_STAT_DD) && 2957 (count != 0) && 2958 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2959 struct mbuf *m = NULL; 2960 2961 mp = sc->rx_buffer_area[i].m_head; 2962 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 2963 BUS_DMASYNC_POSTREAD); 2964 bus_dmamap_unload(sc->rxtag, 2965 sc->rx_buffer_area[i].map); 2966 2967 accept_frame = 1; 2968 prev_len_adj = 0; 2969 desc_len = le16toh(current_desc->length); 2970 if (current_desc->status & E1000_RXD_STAT_EOP) { 2971 count--; 2972 eop = 1; 2973 if (desc_len < ETHER_CRC_LEN) { 2974 len = 0; 2975 prev_len_adj = ETHER_CRC_LEN - desc_len; 2976 } else 2977 len = desc_len - ETHER_CRC_LEN; 2978 } else { 2979 eop = 0; 2980 len = desc_len; 2981 } 2982 2983 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2984 uint8_t last_byte; 2985 uint32_t pkt_len = desc_len; 2986 2987 if (sc->fmp != NULL) 2988 pkt_len += sc->fmp->m_pkthdr.len; 2989 2990 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 2991 if (TBI_ACCEPT(&sc->hw, current_desc->status, 2992 current_desc->errors, 2993 pkt_len, last_byte)) { 2994 em_tbi_adjust_stats(&sc->hw, 2995 &sc->stats, pkt_len, 2996 sc->hw.mac_addr); 2997 if (len > 0) 2998 len--; 2999 } else 3000 accept_frame = 0; 3001 } 3002 3003 if (accept_frame) { 3004 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3005 sc->dropped_pkts++; 3006 em_get_buf(i, sc, mp); 3007 if (sc->fmp != NULL) 3008 m_freem(sc->fmp); 3009 sc->fmp = NULL; 3010 sc->lmp = NULL; 3011 break; 3012 } 3013 3014 /* Assign correct length to the current fragment */ 3015 mp->m_len = len; 3016 3017 if (sc->fmp == NULL) { 3018 mp->m_pkthdr.len = len; 3019 sc->fmp = mp; /* Store the first mbuf */ 3020 sc->lmp = mp; 3021 } else { 3022 /* Chain mbuf's together */ 3023 mp->m_flags &= ~M_PKTHDR; 3024 /* 3025 * Adjust length of previous mbuf in chain if 3026 * we received less than 4 bytes in the last 3027 * descriptor. 3028 */ 3029 if (prev_len_adj > 0) { 3030 sc->lmp->m_len -= prev_len_adj; 3031 sc->fmp->m_pkthdr.len -= 3032 prev_len_adj; 3033 } 3034 sc->lmp->m_next = mp; 3035 sc->lmp = sc->lmp->m_next; 3036 sc->fmp->m_pkthdr.len += len; 3037 } 3038 3039 if (eop) { 3040 sc->fmp->m_pkthdr.rcvif = ifp; 3041 ifp->if_ipackets++; 3042 em_receive_checksum(sc, current_desc, 3043 sc->fmp); 3044#ifndef __NO_STRICT_ALIGNMENT 3045 if (ifp->if_mtu > ETHERMTU && 3046 em_fixup_rx(sc) != 0) 3047 goto skip; 3048#endif 3049 if (current_desc->status & E1000_RXD_STAT_VP) 3050 VLAN_INPUT_TAG(ifp, sc->fmp, 3051 (le16toh(current_desc->special) & 3052 E1000_RXD_SPC_VLAN_MASK)); 3053#ifndef __NO_STRICT_ALIGNMENT 3054skip: 3055#endif 3056 m = sc->fmp; 3057 sc->fmp = NULL; 3058 sc->lmp = NULL; 3059 } 3060 } else { 3061 sc->dropped_pkts++; 3062 em_get_buf(i, sc, mp); 3063 if (sc->fmp != NULL) 3064 m_freem(sc->fmp); 3065 sc->fmp = NULL; 3066 sc->lmp = NULL; 3067 } 3068 3069 /* Zero out the receive descriptors status. */ 3070 current_desc->status = 0; 3071 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3073 3074 /* Advance our pointers to the next descriptor. */ 3075 if (++i == sc->num_rx_desc) 3076 i = 0; 3077 if (m != NULL) { 3078 sc->next_rx_desc_to_check = i; 3079 (*ifp->if_input)(ifp, m); 3080 i = sc->next_rx_desc_to_check; 3081 } 3082 current_desc = &sc->rx_desc_base[i]; 3083 } 3084 sc->next_rx_desc_to_check = i; 3085 3086 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3087 if (--i < 0) 3088 i = sc->num_rx_desc - 1; 3089 E1000_WRITE_REG(&sc->hw, RDT, i); 3090 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3091 return (0); 3092 3093 return (1); 3094} 3095 3096#ifndef __NO_STRICT_ALIGNMENT 3097/* 3098 * When jumbo frames are enabled we should realign entire payload on 3099 * architecures with strict alignment. This is serious design mistake of 8254x 3100 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3101 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3102 * payload. On architecures without strict alignment restrictions 8254x still 3103 * performs unaligned memory access which would reduce the performance too. 3104 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3105 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3106 * existing mbuf chain. 3107 * 3108 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3109 * not used at all on architectures with strict alignment. 3110 */ 3111static int 3112em_fixup_rx(struct em_softc *sc) 3113{ 3114 struct mbuf *m, *n; 3115 int error; 3116 3117 error = 0; 3118 m = sc->fmp; 3119 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3120 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3121 m->m_data += ETHER_HDR_LEN; 3122 } else { 3123 MGETHDR(n, M_DONTWAIT, MT_DATA); 3124 if (n != NULL) { 3125 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3126 m->m_data += ETHER_HDR_LEN; 3127 m->m_len -= ETHER_HDR_LEN; 3128 n->m_len = ETHER_HDR_LEN; 3129 M_MOVE_PKTHDR(n, m); 3130 n->m_next = m; 3131 sc->fmp = n; 3132 } else { 3133 sc->dropped_pkts++; 3134 m_freem(sc->fmp); 3135 sc->fmp = NULL; 3136 error = ENOMEM; 3137 } 3138 } 3139 3140 return (error); 3141} 3142#endif 3143 3144/********************************************************************* 3145 * 3146 * Verify that the hardware indicated that the checksum is valid. 3147 * Inform the stack about the status of checksum so that stack 3148 * doesn't spend time verifying the checksum. 3149 * 3150 *********************************************************************/ 3151static void 3152em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3153 struct mbuf *mp) 3154{ 3155 /* 82543 or newer only */ 3156 if ((sc->hw.mac_type < em_82543) || 3157 /* Ignore Checksum bit is set */ 3158 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3159 mp->m_pkthdr.csum_flags = 0; 3160 return; 3161 } 3162 3163 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3164 /* Did it pass? */ 3165 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3166 /* IP Checksum Good */ 3167 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3168 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3169 3170 } else { 3171 mp->m_pkthdr.csum_flags = 0; 3172 } 3173 } 3174 3175 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3176 /* Did it pass? */ 3177 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3178 mp->m_pkthdr.csum_flags |= 3179 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3180 mp->m_pkthdr.csum_data = htons(0xffff); 3181 } 3182 } 3183} 3184 3185 3186static void 3187em_enable_vlans(struct em_softc *sc) 3188{ 3189 uint32_t ctrl; 3190 3191 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3192 3193 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3194 ctrl |= E1000_CTRL_VME; 3195 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3196} 3197 3198static void 3199em_disable_vlans(struct em_softc *sc) 3200{ 3201 uint32_t ctrl; 3202 3203 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3204 ctrl &= ~E1000_CTRL_VME; 3205 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3206} 3207 3208static void 3209em_enable_intr(struct em_softc *sc) 3210{ 3211 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3212} 3213 3214static void 3215em_disable_intr(struct em_softc *sc) 3216{ 3217 /* 3218 * The first version of 82542 had an errata where when link was forced 3219 * it would stay up even up even if the cable was disconnected. 3220 * Sequence errors were used to detect the disconnect and then the 3221 * driver would unforce the link. This code in the in the ISR. For this 3222 * to work correctly the Sequence error interrupt had to be enabled 3223 * all the time. 3224 */ 3225 3226 if (sc->hw.mac_type == em_82542_rev2_0) 3227 E1000_WRITE_REG(&sc->hw, IMC, 3228 (0xffffffff & ~E1000_IMC_RXSEQ)); 3229 else 3230 E1000_WRITE_REG(&sc->hw, IMC, 3231 0xffffffff); 3232} 3233 3234static int 3235em_is_valid_ether_addr(uint8_t *addr) 3236{ 3237 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3238 3239 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3240 return (FALSE); 3241 } 3242 3243 return (TRUE); 3244} 3245 3246void 3247em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3248{ 3249 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3250} 3251 3252void 3253em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3254{ 3255 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3256} 3257 3258void 3259em_pci_set_mwi(struct em_hw *hw) 3260{ 3261 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3262 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3263} 3264 3265void 3266em_pci_clear_mwi(struct em_hw *hw) 3267{ 3268 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3269 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3270} 3271 3272/********************************************************************* 3273* 82544 Coexistence issue workaround. 3274* There are 2 issues. 3275* 1. Transmit Hang issue. 3276* To detect this issue, following equation can be used... 3277* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3278* If SUM[3:0] is in between 1 to 4, we will have this issue. 3279* 3280* 2. DAC issue. 3281* To detect this issue, following equation can be used... 3282* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3283* If SUM[3:0] is in between 9 to c, we will have this issue. 3284* 3285* 3286* WORKAROUND: 3287* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3288* 3289*** *********************************************************************/ 3290static uint32_t 3291em_fill_descriptors (bus_addr_t address, uint32_t length, 3292 PDESC_ARRAY desc_array) 3293{ 3294 /* Since issue is sensitive to length and address.*/ 3295 /* Let us first check the address...*/ 3296 uint32_t safe_terminator; 3297 if (length <= 4) { 3298 desc_array->descriptor[0].address = address; 3299 desc_array->descriptor[0].length = length; 3300 desc_array->elements = 1; 3301 return (desc_array->elements); 3302 } 3303 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3304 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3305 if (safe_terminator == 0 || 3306 (safe_terminator > 4 && 3307 safe_terminator < 9) || 3308 (safe_terminator > 0xC && 3309 safe_terminator <= 0xF)) { 3310 desc_array->descriptor[0].address = address; 3311 desc_array->descriptor[0].length = length; 3312 desc_array->elements = 1; 3313 return (desc_array->elements); 3314 } 3315 3316 desc_array->descriptor[0].address = address; 3317 desc_array->descriptor[0].length = length - 4; 3318 desc_array->descriptor[1].address = address + (length - 4); 3319 desc_array->descriptor[1].length = 4; 3320 desc_array->elements = 2; 3321 return (desc_array->elements); 3322} 3323 3324/********************************************************************** 3325 * 3326 * Update the board statistics counters. 3327 * 3328 **********************************************************************/ 3329static void 3330em_update_stats_counters(struct em_softc *sc) 3331{ 3332 struct ifnet *ifp; 3333 3334 if(sc->hw.media_type == em_media_type_copper || 3335 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3336 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3337 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3338 } 3339 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3340 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3341 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3342 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3343 3344 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3345 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3346 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3347 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3348 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3349 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3350 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3351 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3352 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3353 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3354 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3355 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3356 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3357 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3358 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3359 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3360 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3361 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3362 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3363 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3364 3365 /* For the 64-bit byte counters the low dword must be read first. */ 3366 /* Both registers clear on the read of the high dword */ 3367 3368 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3369 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3370 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3371 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3372 3373 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3374 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3375 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3376 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3377 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3378 3379 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3380 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3381 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3382 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3383 3384 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3385 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3386 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3387 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3388 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3389 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3390 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3391 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3392 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3393 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3394 3395 if (sc->hw.mac_type >= em_82543) { 3396 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3397 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3398 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3399 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3400 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3401 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3402 } 3403 ifp = sc->ifp; 3404 3405 ifp->if_collisions = sc->stats.colc; 3406 3407 /* Rx Errors */ 3408 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3409 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3410 sc->stats.mpc + sc->stats.cexterr; 3411 3412 /* Tx Errors */ 3413 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3414 sc->watchdog_events; 3415} 3416 3417 3418/********************************************************************** 3419 * 3420 * This routine is called only when em_display_debug_stats is enabled. 3421 * This routine provides a way to take a look at important statistics 3422 * maintained by the driver and hardware. 3423 * 3424 **********************************************************************/ 3425static void 3426em_print_debug_info(struct em_softc *sc) 3427{ 3428 device_t dev = sc->dev; 3429 uint8_t *hw_addr = sc->hw.hw_addr; 3430 3431 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3432 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3433 E1000_READ_REG(&sc->hw, CTRL), 3434 E1000_READ_REG(&sc->hw, RCTL)); 3435 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3436 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3437 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3438 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3439 sc->hw.fc_high_water, 3440 sc->hw.fc_low_water); 3441 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3442 E1000_READ_REG(&sc->hw, TIDV), 3443 E1000_READ_REG(&sc->hw, TADV)); 3444 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3445 E1000_READ_REG(&sc->hw, RDTR), 3446 E1000_READ_REG(&sc->hw, RADV)); 3447 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3448 (long long)sc->tx_fifo_wrk_cnt, 3449 (long long)sc->tx_fifo_reset_cnt); 3450 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3451 E1000_READ_REG(&sc->hw, TDH), 3452 E1000_READ_REG(&sc->hw, TDT)); 3453 device_printf(dev, "Num Tx descriptors avail = %d\n", 3454 sc->num_tx_desc_avail); 3455 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3456 sc->no_tx_desc_avail1); 3457 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3458 sc->no_tx_desc_avail2); 3459 device_printf(dev, "Std mbuf failed = %ld\n", 3460 sc->mbuf_alloc_failed); 3461 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3462 sc->mbuf_cluster_failed); 3463 device_printf(dev, "Driver dropped packets = %ld\n", 3464 sc->dropped_pkts); 3465} 3466 3467static void 3468em_print_hw_stats(struct em_softc *sc) 3469{ 3470 device_t dev = sc->dev; 3471 3472 device_printf(dev, "Excessive collisions = %lld\n", 3473 (long long)sc->stats.ecol); 3474 device_printf(dev, "Symbol errors = %lld\n", 3475 (long long)sc->stats.symerrs); 3476 device_printf(dev, "Sequence errors = %lld\n", 3477 (long long)sc->stats.sec); 3478 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3479 3480 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3481 device_printf(dev, "Receive No Buffers = %lld\n", 3482 (long long)sc->stats.rnbc); 3483 device_printf(dev, "Receive length errors = %lld\n", 3484 (long long)sc->stats.rlec); 3485 device_printf(dev, "Receive errors = %lld\n", 3486 (long long)sc->stats.rxerrc); 3487 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3488 device_printf(dev, "Alignment errors = %lld\n", 3489 (long long)sc->stats.algnerrc); 3490 device_printf(dev, "Carrier extension errors = %lld\n", 3491 (long long)sc->stats.cexterr); 3492 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3493 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3494 3495 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3496 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3497 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3498 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3499 3500 device_printf(dev, "Good Packets Rcvd = %lld\n", 3501 (long long)sc->stats.gprc); 3502 device_printf(dev, "Good Packets Xmtd = %lld\n", 3503 (long long)sc->stats.gptc); 3504} 3505 3506static int 3507em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3508{ 3509 struct em_softc *sc; 3510 int error; 3511 int result; 3512 3513 result = -1; 3514 error = sysctl_handle_int(oidp, &result, 0, req); 3515 3516 if (error || !req->newptr) 3517 return (error); 3518 3519 if (result == 1) { 3520 sc = (struct em_softc *)arg1; 3521 em_print_debug_info(sc); 3522 } 3523 3524 return (error); 3525} 3526 3527 3528static int 3529em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3530{ 3531 struct em_softc *sc; 3532 int error; 3533 int result; 3534 3535 result = -1; 3536 error = sysctl_handle_int(oidp, &result, 0, req); 3537 3538 if (error || !req->newptr) 3539 return (error); 3540 3541 if (result == 1) { 3542 sc = (struct em_softc *)arg1; 3543 em_print_hw_stats(sc); 3544 } 3545 3546 return (error); 3547} 3548 3549static int 3550em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3551{ 3552 struct em_int_delay_info *info; 3553 struct em_softc *sc; 3554 uint32_t regval; 3555 int error; 3556 int usecs; 3557 int ticks; 3558 3559 info = (struct em_int_delay_info *)arg1; 3560 usecs = info->value; 3561 error = sysctl_handle_int(oidp, &usecs, 0, req); 3562 if (error != 0 || req->newptr == NULL) 3563 return (error); 3564 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3565 return (EINVAL); 3566 info->value = usecs; 3567 ticks = E1000_USECS_TO_TICKS(usecs); 3568 3569 sc = info->sc; 3570 3571 EM_LOCK(sc); 3572 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3573 regval = (regval & ~0xffff) | (ticks & 0xffff); 3574 /* Handle a few special cases. */ 3575 switch (info->offset) { 3576 case E1000_RDTR: 3577 case E1000_82542_RDTR: 3578 regval |= E1000_RDT_FPDB; 3579 break; 3580 case E1000_TIDV: 3581 case E1000_82542_TIDV: 3582 if (ticks == 0) { 3583 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3584 /* Don't write 0 into the TIDV register. */ 3585 regval++; 3586 } else 3587 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3588 break; 3589 } 3590 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3591 EM_UNLOCK(sc); 3592 return (0); 3593} 3594 3595static void 3596em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3597 const char *description, struct em_int_delay_info *info, 3598 int offset, int value) 3599{ 3600 info->sc = sc; 3601 info->offset = offset; 3602 info->value = value; 3603 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3604 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3605 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3606 info, 0, em_sysctl_int_delay, "I", description); 3607} 3608 3609#ifndef NO_EM_FASTINTR 3610static void 3611em_add_int_process_limit(struct em_softc *sc, const char *name, 3612 const char *description, int *limit, int value) 3613{ 3614 *limit = value; 3615 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3616 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3617 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3618} 3619#endif 3620