if_em.c revision 155715
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 155715 2006-02-15 13:45:02Z glebius $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 3.2.18"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 143 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 147 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 151 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 155 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 /* required last entry */ 160 { 0, 0, 0, 0, 0} 161}; 162 163/********************************************************************* 164 * Table of branding strings for all supported NICs. 165 *********************************************************************/ 166 167static char *em_strings[] = { 168 "Intel(R) PRO/1000 Network Connection" 169}; 170 171/********************************************************************* 172 * Function prototypes 173 *********************************************************************/ 174static int em_probe(device_t); 175static int em_attach(device_t); 176static int em_detach(device_t); 177static int em_shutdown(device_t); 178static int em_suspend(device_t); 179static int em_resume(device_t); 180static void em_intr(void *); 181#ifndef NO_EM_FASTINTR 182static void em_intr_fast(void *); 183#endif 184static void em_start(struct ifnet *); 185static void em_start_locked(struct ifnet *ifp); 186static int em_ioctl(struct ifnet *, u_long, caddr_t); 187static void em_watchdog(struct ifnet *); 188static void em_init(void *); 189static void em_init_locked(struct em_softc *); 190static void em_stop(void *); 191static void em_media_status(struct ifnet *, struct ifmediareq *); 192static int em_media_change(struct ifnet *); 193static void em_identify_hardware(struct em_softc *); 194static int em_allocate_pci_resources(struct em_softc *); 195static int em_allocate_intr(struct em_softc *); 196static void em_free_intr(struct em_softc *); 197static void em_free_pci_resources(struct em_softc *); 198static void em_local_timer(void *); 199static int em_hardware_init(struct em_softc *); 200static void em_setup_interface(device_t, struct em_softc *); 201static int em_setup_transmit_structures(struct em_softc *); 202static void em_initialize_transmit_unit(struct em_softc *); 203static int em_setup_receive_structures(struct em_softc *); 204static void em_initialize_receive_unit(struct em_softc *); 205static void em_enable_intr(struct em_softc *); 206static void em_disable_intr(struct em_softc *); 207static void em_free_transmit_structures(struct em_softc *); 208static void em_free_receive_structures(struct em_softc *); 209static void em_update_stats_counters(struct em_softc *); 210static void em_txeof(struct em_softc *); 211static int em_allocate_receive_structures(struct em_softc *); 212static int em_allocate_transmit_structures(struct em_softc *); 213static int em_rxeof(struct em_softc *, int); 214#ifndef __NO_STRICT_ALIGNMENT 215static int em_fixup_rx(struct em_softc *); 216#endif 217static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 218 struct mbuf *); 219static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 220 uint32_t *, uint32_t *); 221static void em_set_promisc(struct em_softc *); 222static void em_disable_promisc(struct em_softc *); 223static void em_set_multi(struct em_softc *); 224static void em_print_hw_stats(struct em_softc *); 225static void em_update_link_status(struct em_softc *); 226static int em_get_buf(int i, struct em_softc *, struct mbuf *); 227static void em_enable_vlans(struct em_softc *); 228static void em_disable_vlans(struct em_softc *); 229static int em_encap(struct em_softc *, struct mbuf **); 230static void em_smartspeed(struct em_softc *); 231static int em_82547_fifo_workaround(struct em_softc *, int); 232static void em_82547_update_fifo_head(struct em_softc *, int); 233static int em_82547_tx_fifo_reset(struct em_softc *); 234static void em_82547_move_tail(void *arg); 235static void em_82547_move_tail_locked(struct em_softc *); 236static int em_dma_malloc(struct em_softc *, bus_size_t, 237 struct em_dma_alloc *, int); 238static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 239static void em_print_debug_info(struct em_softc *); 240static int em_is_valid_ether_addr(uint8_t *); 241static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 242static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 243static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 244 PDESC_ARRAY desc_array); 245static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 246static void em_add_int_delay_sysctl(struct em_softc *, const char *, 247 const char *, struct em_int_delay_info *, int, int); 248#ifndef NO_EM_FASTINTR 249static void em_add_int_process_limit(struct em_softc *, const char *, 250 const char *, int *, int); 251static void em_handle_rxtx(void *context, int pending); 252static void em_handle_link(void *context, int pending); 253#endif 254#ifdef DEVICE_POLLING 255static poll_handler_t em_poll; 256#endif 257 258/********************************************************************* 259 * FreeBSD Device Interface Entry Points 260 *********************************************************************/ 261 262static device_method_t em_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, em_probe), 265 DEVMETHOD(device_attach, em_attach), 266 DEVMETHOD(device_detach, em_detach), 267 DEVMETHOD(device_shutdown, em_shutdown), 268 DEVMETHOD(device_suspend, em_suspend), 269 DEVMETHOD(device_resume, em_resume), 270 {0, 0} 271}; 272 273static driver_t em_driver = { 274 "em", em_methods, sizeof(struct em_softc), 275}; 276 277static devclass_t em_devclass; 278DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 279MODULE_DEPEND(em, pci, 1, 1, 1); 280MODULE_DEPEND(em, ether, 1, 1, 1); 281 282/********************************************************************* 283 * Tunable default values. 284 *********************************************************************/ 285 286#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 287#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 288 289static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 290static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 291static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 292static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 293static int em_rxd = EM_DEFAULT_RXD; 294static int em_txd = EM_DEFAULT_TXD; 295 296TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 297TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 298TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 299TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 300TUNABLE_INT("hw.em.rxd", &em_rxd); 301TUNABLE_INT("hw.em.txd", &em_txd); 302#ifndef NO_EM_FASTINTR 303static int em_rx_process_limit = 100; 304TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 305#endif 306 307/********************************************************************* 308 * Device identification routine 309 * 310 * em_probe determines if the driver should be loaded on 311 * adapter based on PCI vendor/device id of the adapter. 312 * 313 * return BUS_PROBE_DEFAULT on success, positive on failure 314 *********************************************************************/ 315 316static int 317em_probe(device_t dev) 318{ 319 char adapter_name[60]; 320 uint16_t pci_vendor_id = 0; 321 uint16_t pci_device_id = 0; 322 uint16_t pci_subvendor_id = 0; 323 uint16_t pci_subdevice_id = 0; 324 em_vendor_info_t *ent; 325 326 INIT_DEBUGOUT("em_probe: begin"); 327 328 pci_vendor_id = pci_get_vendor(dev); 329 if (pci_vendor_id != EM_VENDOR_ID) 330 return (ENXIO); 331 332 pci_device_id = pci_get_device(dev); 333 pci_subvendor_id = pci_get_subvendor(dev); 334 pci_subdevice_id = pci_get_subdevice(dev); 335 336 ent = em_vendor_info_array; 337 while (ent->vendor_id != 0) { 338 if ((pci_vendor_id == ent->vendor_id) && 339 (pci_device_id == ent->device_id) && 340 341 ((pci_subvendor_id == ent->subvendor_id) || 342 (ent->subvendor_id == PCI_ANY_ID)) && 343 344 ((pci_subdevice_id == ent->subdevice_id) || 345 (ent->subdevice_id == PCI_ANY_ID))) { 346 sprintf(adapter_name, "%s %s", 347 em_strings[ent->index], 348 em_driver_version); 349 device_set_desc_copy(dev, adapter_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 ent++; 353 } 354 355 return (ENXIO); 356} 357 358/********************************************************************* 359 * Device initialization routine 360 * 361 * The attach entry point is called when the driver is being loaded. 362 * This routine identifies the type of hardware, allocates all resources 363 * and initializes the hardware. 364 * 365 * return 0 on success, positive on failure 366 *********************************************************************/ 367 368static int 369em_attach(device_t dev) 370{ 371 struct em_softc *sc; 372 int tsize, rsize; 373 int error = 0; 374 375 INIT_DEBUGOUT("em_attach: begin"); 376 377 sc = device_get_softc(dev); 378 sc->dev = sc->osdep.dev = dev; 379 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 380 381 /* SYSCTL stuff */ 382 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 383 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 384 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 385 em_sysctl_debug_info, "I", "Debug Information"); 386 387 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 388 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 389 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 390 em_sysctl_stats, "I", "Statistics"); 391 392 callout_init(&sc->timer, CALLOUT_MPSAFE); 393 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 394 395 /* Determine hardware revision */ 396 em_identify_hardware(sc); 397 398 /* Set up some sysctls for the tunable interrupt delays */ 399 em_add_int_delay_sysctl(sc, "rx_int_delay", 400 "receive interrupt delay in usecs", &sc->rx_int_delay, 401 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 402 em_add_int_delay_sysctl(sc, "tx_int_delay", 403 "transmit interrupt delay in usecs", &sc->tx_int_delay, 404 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 405 if (sc->hw.mac_type >= em_82540) { 406 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 407 "receive interrupt delay limit in usecs", 408 &sc->rx_abs_int_delay, 409 E1000_REG_OFFSET(&sc->hw, RADV), 410 em_rx_abs_int_delay_dflt); 411 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 412 "transmit interrupt delay limit in usecs", 413 &sc->tx_abs_int_delay, 414 E1000_REG_OFFSET(&sc->hw, TADV), 415 em_tx_abs_int_delay_dflt); 416 } 417 418 /* Sysctls for limiting the amount of work done in the taskqueue */ 419#ifndef NO_EM_FASTINTR 420 em_add_int_process_limit(sc, "rx_processing_limit", 421 "max number of rx packets to process", &sc->rx_process_limit, 422 em_rx_process_limit); 423#endif 424 425 /* 426 * Validate number of transmit and receive descriptors. It 427 * must not exceed hardware maximum, and must be multiple 428 * of E1000_DBA_ALIGN. 429 */ 430 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 431 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 432 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 433 (em_txd < EM_MIN_TXD)) { 434 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 435 EM_DEFAULT_TXD, em_txd); 436 sc->num_tx_desc = EM_DEFAULT_TXD; 437 } else 438 sc->num_tx_desc = em_txd; 439 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 440 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 441 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 442 (em_rxd < EM_MIN_RXD)) { 443 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 444 EM_DEFAULT_RXD, em_rxd); 445 sc->num_rx_desc = EM_DEFAULT_RXD; 446 } else 447 sc->num_rx_desc = em_rxd; 448 449 sc->hw.autoneg = DO_AUTO_NEG; 450 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 451 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 452 sc->hw.tbi_compatibility_en = TRUE; 453 sc->rx_buffer_len = EM_RXBUFFER_2048; 454 455 sc->hw.phy_init_script = 1; 456 sc->hw.phy_reset_disable = FALSE; 457 458#ifndef EM_MASTER_SLAVE 459 sc->hw.master_slave = em_ms_hw_default; 460#else 461 sc->hw.master_slave = EM_MASTER_SLAVE; 462#endif 463 /* 464 * Set the max frame size assuming standard ethernet 465 * sized frames. 466 */ 467 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 468 469 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 470 471 /* 472 * This controls when hardware reports transmit completion 473 * status. 474 */ 475 sc->hw.report_tx_early = 1; 476 if (em_allocate_pci_resources(sc)) { 477 device_printf(dev, "Allocation of PCI resources failed\n"); 478 error = ENXIO; 479 goto err_pci; 480 } 481 482 /* Initialize eeprom parameters */ 483 em_init_eeprom_params(&sc->hw); 484 485 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 486 E1000_DBA_ALIGN); 487 488 /* Allocate Transmit Descriptor ring */ 489 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 490 device_printf(dev, "Unable to allocate tx_desc memory\n"); 491 error = ENOMEM; 492 goto err_tx_desc; 493 } 494 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 495 496 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 497 E1000_DBA_ALIGN); 498 499 /* Allocate Receive Descriptor ring */ 500 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 501 device_printf(dev, "Unable to allocate rx_desc memory\n"); 502 error = ENOMEM; 503 goto err_rx_desc; 504 } 505 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 506 507 /* Initialize the hardware */ 508 if (em_hardware_init(sc)) { 509 device_printf(dev, "Unable to initialize the hardware\n"); 510 error = EIO; 511 goto err_hw_init; 512 } 513 514 /* Copy the permanent MAC address out of the EEPROM */ 515 if (em_read_mac_addr(&sc->hw) < 0) { 516 device_printf(dev, "EEPROM read error while reading MAC" 517 " address\n"); 518 error = EIO; 519 goto err_hw_init; 520 } 521 522 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 523 device_printf(dev, "Invalid MAC address\n"); 524 error = EIO; 525 goto err_hw_init; 526 } 527 528 /* Setup OS specific network interface */ 529 em_setup_interface(dev, sc); 530 531 em_allocate_intr(sc); 532 533 /* Initialize statistics */ 534 em_clear_hw_cntrs(&sc->hw); 535 em_update_stats_counters(sc); 536 sc->hw.get_link_status = 1; 537 em_update_link_status(sc); 538 539 /* Identify 82544 on PCIX */ 540 em_get_bus_info(&sc->hw); 541 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 542 sc->pcix_82544 = TRUE; 543 else 544 sc->pcix_82544 = FALSE; 545 546 INIT_DEBUGOUT("em_attach: end"); 547 548 return (0); 549 550err_hw_init: 551 em_dma_free(sc, &sc->rxdma); 552err_rx_desc: 553 em_dma_free(sc, &sc->txdma); 554err_tx_desc: 555err_pci: 556 em_free_intr(sc); 557 em_free_pci_resources(sc); 558 EM_LOCK_DESTROY(sc); 559 560 return (error); 561} 562 563/********************************************************************* 564 * Device removal routine 565 * 566 * The detach entry point is called when the driver is being removed. 567 * This routine stops the adapter and deallocates all the resources 568 * that were allocated for driver operation. 569 * 570 * return 0 on success, positive on failure 571 *********************************************************************/ 572 573static int 574em_detach(device_t dev) 575{ 576 struct em_softc *sc = device_get_softc(dev); 577 struct ifnet *ifp = sc->ifp; 578 579 INIT_DEBUGOUT("em_detach: begin"); 580 581#ifdef DEVICE_POLLING 582 if (ifp->if_capenable & IFCAP_POLLING) 583 ether_poll_deregister(ifp); 584#endif 585 586 em_free_intr(sc); 587 EM_LOCK(sc); 588 sc->in_detach = 1; 589 em_stop(sc); 590 em_phy_hw_reset(&sc->hw); 591 EM_UNLOCK(sc); 592 ether_ifdetach(sc->ifp); 593 594 em_free_pci_resources(sc); 595 bus_generic_detach(dev); 596 if_free(ifp); 597 598 /* Free Transmit Descriptor ring */ 599 if (sc->tx_desc_base) { 600 em_dma_free(sc, &sc->txdma); 601 sc->tx_desc_base = NULL; 602 } 603 604 /* Free Receive Descriptor ring */ 605 if (sc->rx_desc_base) { 606 em_dma_free(sc, &sc->rxdma); 607 sc->rx_desc_base = NULL; 608 } 609 610 EM_LOCK_DESTROY(sc); 611 612 return (0); 613} 614 615/********************************************************************* 616 * 617 * Shutdown entry point 618 * 619 **********************************************************************/ 620 621static int 622em_shutdown(device_t dev) 623{ 624 struct em_softc *sc = device_get_softc(dev); 625 EM_LOCK(sc); 626 em_stop(sc); 627 EM_UNLOCK(sc); 628 return (0); 629} 630 631/* 632 * Suspend/resume device methods. 633 */ 634static int 635em_suspend(device_t dev) 636{ 637 struct em_softc *sc = device_get_softc(dev); 638 639 EM_LOCK(sc); 640 em_stop(sc); 641 EM_UNLOCK(sc); 642 643 return bus_generic_suspend(dev); 644} 645 646static int 647em_resume(device_t dev) 648{ 649 struct em_softc *sc = device_get_softc(dev); 650 struct ifnet *ifp = sc->ifp; 651 652 EM_LOCK(sc); 653 em_init_locked(sc); 654 if ((ifp->if_flags & IFF_UP) && 655 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 656 em_start_locked(ifp); 657 EM_UNLOCK(sc); 658 659 return bus_generic_resume(dev); 660} 661 662 663/********************************************************************* 664 * Transmit entry point 665 * 666 * em_start is called by the stack to initiate a transmit. 667 * The driver will remain in this routine as long as there are 668 * packets to transmit and transmit resources are available. 669 * In case resources are not available stack is notified and 670 * the packet is requeued. 671 **********************************************************************/ 672 673static void 674em_start_locked(struct ifnet *ifp) 675{ 676 struct em_softc *sc = ifp->if_softc; 677 struct mbuf *m_head; 678 679 EM_LOCK_ASSERT(sc); 680 681 if (!sc->link_active) 682 return; 683 684 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 685 686 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 687 if (m_head == NULL) 688 break; 689 /* 690 * em_encap() can modify our pointer, and or make it NULL on 691 * failure. In that event, we can't requeue. 692 */ 693 if (em_encap(sc, &m_head)) { 694 if (m_head == NULL) 695 break; 696 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 697 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 698 break; 699 } 700 701 /* Send a copy of the frame to the BPF listener */ 702 BPF_MTAP(ifp, m_head); 703 704 /* Set timeout in case hardware has problems transmitting. */ 705 ifp->if_timer = EM_TX_TIMEOUT; 706 } 707} 708 709static void 710em_start(struct ifnet *ifp) 711{ 712 struct em_softc *sc = ifp->if_softc; 713 714 EM_LOCK(sc); 715 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 716 em_start_locked(ifp); 717 EM_UNLOCK(sc); 718} 719 720/********************************************************************* 721 * Ioctl entry point 722 * 723 * em_ioctl is called when the user wants to configure the 724 * interface. 725 * 726 * return 0 on success, positive on failure 727 **********************************************************************/ 728 729static int 730em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 731{ 732 struct em_softc *sc = ifp->if_softc; 733 struct ifreq *ifr = (struct ifreq *)data; 734 int error = 0; 735 736 if (sc->in_detach) 737 return (error); 738 739 switch (command) { 740 case SIOCSIFADDR: 741 case SIOCGIFADDR: 742 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 743 ether_ioctl(ifp, command, data); 744 break; 745 case SIOCSIFMTU: 746 { 747 int max_frame_size; 748 749 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 750 751 switch (sc->hw.mac_type) { 752 case em_82571: 753 case em_82572: 754 max_frame_size = 10500; 755 break; 756 case em_82573: 757 /* 82573 does not support jumbo frames. */ 758 max_frame_size = ETHER_MAX_LEN; 759 break; 760 default: 761 max_frame_size = MAX_JUMBO_FRAME_SIZE; 762 } 763 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 764 ETHER_CRC_LEN) { 765 error = EINVAL; 766 break; 767 } 768 769 EM_LOCK(sc); 770 ifp->if_mtu = ifr->ifr_mtu; 771 sc->hw.max_frame_size = 772 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 773 em_init_locked(sc); 774 EM_UNLOCK(sc); 775 break; 776 } 777 case SIOCSIFFLAGS: 778 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 779 EM_LOCK(sc); 780 if (ifp->if_flags & IFF_UP) { 781 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 782 em_init_locked(sc); 783 } 784 785 em_disable_promisc(sc); 786 em_set_promisc(sc); 787 } else { 788 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 789 em_stop(sc); 790 } 791 } 792 EM_UNLOCK(sc); 793 break; 794 case SIOCADDMULTI: 795 case SIOCDELMULTI: 796 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 797 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 798 EM_LOCK(sc); 799 em_disable_intr(sc); 800 em_set_multi(sc); 801 if (sc->hw.mac_type == em_82542_rev2_0) { 802 em_initialize_receive_unit(sc); 803 } 804#ifdef DEVICE_POLLING 805 if (!(ifp->if_capenable & IFCAP_POLLING)) 806#endif 807 em_enable_intr(sc); 808 EM_UNLOCK(sc); 809 } 810 break; 811 case SIOCSIFMEDIA: 812 case SIOCGIFMEDIA: 813 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 814 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 815 break; 816 case SIOCSIFCAP: 817 { 818 int mask, reinit; 819 820 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 821 reinit = 0; 822 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 823#ifdef DEVICE_POLLING 824 if (mask & IFCAP_POLLING) { 825 if (ifr->ifr_reqcap & IFCAP_POLLING) { 826 error = ether_poll_register(em_poll, ifp); 827 if (error) 828 return (error); 829 EM_LOCK(sc); 830 em_disable_intr(sc); 831 ifp->if_capenable |= IFCAP_POLLING; 832 EM_UNLOCK(sc); 833 } else { 834 error = ether_poll_deregister(ifp); 835 /* Enable interrupt even in error case */ 836 EM_LOCK(sc); 837 em_enable_intr(sc); 838 ifp->if_capenable &= ~IFCAP_POLLING; 839 EM_UNLOCK(sc); 840 } 841 } 842#endif 843 if (mask & IFCAP_HWCSUM) { 844 ifp->if_capenable ^= IFCAP_HWCSUM; 845 reinit = 1; 846 } 847 if (mask & IFCAP_VLAN_HWTAGGING) { 848 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 849 reinit = 1; 850 } 851 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 852 em_init(sc); 853 VLAN_CAPABILITIES(ifp); 854 break; 855 } 856 default: 857 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 858 error = EINVAL; 859 } 860 861 return (error); 862} 863 864/********************************************************************* 865 * Watchdog entry point 866 * 867 * This routine is called whenever hardware quits transmitting. 868 * 869 **********************************************************************/ 870 871static void 872em_watchdog(struct ifnet *ifp) 873{ 874 struct em_softc *sc = ifp->if_softc; 875 876 EM_LOCK(sc); 877 /* If we are in this routine because of pause frames, then 878 * don't reset the hardware. 879 */ 880 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 881 ifp->if_timer = EM_TX_TIMEOUT; 882 EM_UNLOCK(sc); 883 return; 884 } 885 886 if (em_check_for_link(&sc->hw) == 0) 887 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 888 889 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 890 sc->watchdog_events++; 891 892 em_init_locked(sc); 893 EM_UNLOCK(sc); 894} 895 896/********************************************************************* 897 * Init entry point 898 * 899 * This routine is used in two ways. It is used by the stack as 900 * init entry point in network interface structure. It is also used 901 * by the driver as a hw/sw initialization routine to get to a 902 * consistent state. 903 * 904 * return 0 on success, positive on failure 905 **********************************************************************/ 906 907static void 908em_init_locked(struct em_softc *sc) 909{ 910 struct ifnet *ifp = sc->ifp; 911 device_t dev = sc->dev; 912 uint32_t pba; 913 914 INIT_DEBUGOUT("em_init: begin"); 915 916 EM_LOCK_ASSERT(sc); 917 918 em_stop(sc); 919 920 /* 921 * Packet Buffer Allocation (PBA) 922 * Writing PBA sets the receive portion of the buffer 923 * the remainder is used for the transmit buffer. 924 */ 925 switch (sc->hw.mac_type) { 926 case em_82547: 927 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 928 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 929 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 930 else 931 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 932 sc->tx_fifo_head = 0; 933 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 934 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 935 break; 936 case em_82571: /* 82571: Total Packet Buffer is 48K */ 937 case em_82572: /* 82572: Total Packet Buffer is 48K */ 938 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 939 break; 940 case em_82573: /* 82573: Total Packet Buffer is 32K */ 941 /* Jumbo frames not supported */ 942 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 943 break; 944 default: 945 /* Devices before 82547 had a Packet Buffer of 64K. */ 946 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 947 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 948 else 949 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 950 } 951 952 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 953 E1000_WRITE_REG(&sc->hw, PBA, pba); 954 955 /* Get the latest mac address, User can use a LAA */ 956 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 957 958 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 959 em_enable_vlans(sc); 960 961 /* Prepare transmit descriptors and buffers */ 962 if (em_setup_transmit_structures(sc)) { 963 device_printf(dev, "Could not setup transmit structures\n"); 964 em_stop(sc); 965 return; 966 } 967 em_initialize_transmit_unit(sc); 968 969 /* Setup Multicast table */ 970 em_set_multi(sc); 971 972 /* Prepare receive descriptors and buffers */ 973 if (em_setup_receive_structures(sc)) { 974 device_printf(dev, "Could not setup receive structures\n"); 975 em_stop(sc); 976 return; 977 } 978 em_initialize_receive_unit(sc); 979 980 /* Don't loose promiscuous settings */ 981 em_set_promisc(sc); 982 983 ifp->if_drv_flags |= IFF_DRV_RUNNING; 984 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 985 986 if (sc->hw.mac_type >= em_82543) { 987 if (ifp->if_capenable & IFCAP_TXCSUM) 988 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 989 else 990 ifp->if_hwassist = 0; 991 } 992 993 callout_reset(&sc->timer, hz, em_local_timer, sc); 994 em_clear_hw_cntrs(&sc->hw); 995#ifdef DEVICE_POLLING 996 /* 997 * Only enable interrupts if we are not polling, make sure 998 * they are off otherwise. 999 */ 1000 if (ifp->if_capenable & IFCAP_POLLING) 1001 em_disable_intr(sc); 1002 else 1003#endif /* DEVICE_POLLING */ 1004 em_enable_intr(sc); 1005 1006 /* Don't reset the phy next time init gets called */ 1007 sc->hw.phy_reset_disable = TRUE; 1008} 1009 1010static void 1011em_init(void *arg) 1012{ 1013 struct em_softc *sc = arg; 1014 1015 EM_LOCK(sc); 1016 em_init_locked(sc); 1017 EM_UNLOCK(sc); 1018} 1019 1020 1021#ifdef DEVICE_POLLING 1022static void 1023em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1024{ 1025 struct em_softc *sc = ifp->if_softc; 1026 uint32_t reg_icr; 1027 1028 EM_LOCK_ASSERT(sc); 1029 1030 if (cmd == POLL_AND_CHECK_STATUS) { 1031 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1032 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1033 callout_stop(&sc->timer); 1034 sc->hw.get_link_status = 1; 1035 em_check_for_link(&sc->hw); 1036 em_update_link_status(sc); 1037 callout_reset(&sc->timer, hz, em_local_timer, sc); 1038 } 1039 } 1040 em_rxeof(sc, count); 1041 em_txeof(sc); 1042 1043 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1044 em_start_locked(ifp); 1045} 1046 1047static void 1048em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1049{ 1050 struct em_softc *sc = ifp->if_softc; 1051 1052 EM_LOCK(sc); 1053 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1054 em_poll_locked(ifp, cmd, count); 1055 EM_UNLOCK(sc); 1056} 1057#endif /* DEVICE_POLLING */ 1058 1059#ifndef NO_EM_FASTINTR 1060static void 1061em_handle_link(void *context, int pending) 1062{ 1063 struct em_softc *sc = context; 1064 struct ifnet *ifp; 1065 1066 ifp = sc->ifp; 1067 1068 EM_LOCK(sc); 1069 1070 callout_stop(&sc->timer); 1071 sc->hw.get_link_status = 1; 1072 em_check_for_link(&sc->hw); 1073 em_update_link_status(sc); 1074 callout_reset(&sc->timer, hz, em_local_timer, sc); 1075 EM_UNLOCK(sc); 1076} 1077 1078static void 1079em_handle_rxtx(void *context, int pending) 1080{ 1081 struct em_softc *sc = context; 1082 struct ifnet *ifp; 1083 1084 NET_LOCK_GIANT(); 1085 ifp = sc->ifp; 1086 1087 /* 1088 * TODO: 1089 * It should be possible to run the tx clean loop without the lock. 1090 */ 1091 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1092 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1093 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1094 EM_LOCK(sc); 1095 em_txeof(sc); 1096 1097 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1098 em_start_locked(ifp); 1099 EM_UNLOCK(sc); 1100 } 1101 1102 em_enable_intr(sc); 1103 NET_UNLOCK_GIANT(); 1104} 1105#endif 1106 1107/********************************************************************* 1108 * 1109 * Interrupt Service routine 1110 * 1111 **********************************************************************/ 1112#ifndef NO_EM_FASTINTR 1113static void 1114em_intr_fast(void *arg) 1115{ 1116 struct em_softc *sc = arg; 1117 struct ifnet *ifp; 1118 uint32_t reg_icr; 1119 1120 ifp = sc->ifp; 1121 1122#ifdef DEVICE_POLLING 1123 if (ifp->if_capenable & IFCAP_POLLING) 1124 return; 1125#endif /* DEVICE_POLLING */ 1126 1127 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1128 1129 /* Hot eject? */ 1130 if (reg_icr == 0xffffffff) 1131 return; 1132 1133 /* Definitely not our interrupt. */ 1134 if (reg_icr == 0x0) 1135 return; 1136 1137 /* 1138 * Starting with the 82571 chip, bit 31 should be used to 1139 * determine whether the interrupt belongs to us. 1140 */ 1141 if (sc->hw.mac_type >= em_82571 && 1142 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1143 return; 1144 1145 /* 1146 * Mask interrupts until the taskqueue is finished running. This is 1147 * cheap, just assume that it is needed. This also works around the 1148 * MSI message reordering errata on certain systems. 1149 */ 1150 em_disable_intr(sc); 1151 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1152 1153 /* Link status change */ 1154 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1155 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1156 1157 if (reg_icr & E1000_ICR_RXO) 1158 sc->rx_overruns++; 1159} 1160#endif 1161 1162static void 1163em_intr(void *arg) 1164{ 1165 struct em_softc *sc = arg; 1166 struct ifnet *ifp; 1167 uint32_t reg_icr; 1168 int wantinit = 0; 1169 1170 EM_LOCK(sc); 1171 1172 ifp = sc->ifp; 1173 1174#ifdef DEVICE_POLLING 1175 if (ifp->if_capenable & IFCAP_POLLING) { 1176 EM_UNLOCK(sc); 1177 return; 1178 } 1179#endif 1180 1181 for (;;) { 1182 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1183 if (sc->hw.mac_type >= em_82571 && 1184 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1185 break; 1186 else if (reg_icr == 0) 1187 break; 1188 1189 /* 1190 * XXX: some laptops trigger several spurious interrupts 1191 * on em(4) when in the resume cycle. The ICR register 1192 * reports all-ones value in this case. Processing such 1193 * interrupts would lead to a freeze. I don't know why. 1194 */ 1195 if (reg_icr == 0xffffffff) 1196 break; 1197 1198 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1199 em_rxeof(sc, -1); 1200 em_txeof(sc); 1201 } 1202 1203 /* Link status change */ 1204 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1205 callout_stop(&sc->timer); 1206 sc->hw.get_link_status = 1; 1207 em_check_for_link(&sc->hw); 1208 em_update_link_status(sc); 1209 callout_reset(&sc->timer, hz, em_local_timer, sc); 1210 } 1211 1212 if (reg_icr & E1000_ICR_RXO) { 1213 sc->rx_overruns++; 1214 wantinit = 1; 1215 } 1216 } 1217#if 0 1218 if (wantinit) 1219 em_init_locked(sc); 1220#endif 1221 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1222 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1223 em_start_locked(ifp); 1224 1225 EM_UNLOCK(sc); 1226} 1227 1228/********************************************************************* 1229 * 1230 * Media Ioctl callback 1231 * 1232 * This routine is called whenever the user queries the status of 1233 * the interface using ifconfig. 1234 * 1235 **********************************************************************/ 1236static void 1237em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1238{ 1239 struct em_softc *sc = ifp->if_softc; 1240 1241 INIT_DEBUGOUT("em_media_status: begin"); 1242 1243 em_check_for_link(&sc->hw); 1244 em_update_link_status(sc); 1245 1246 ifmr->ifm_status = IFM_AVALID; 1247 ifmr->ifm_active = IFM_ETHER; 1248 1249 if (!sc->link_active) 1250 return; 1251 1252 ifmr->ifm_status |= IFM_ACTIVE; 1253 1254 if (sc->hw.media_type == em_media_type_fiber) { 1255 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1256 } else { 1257 switch (sc->link_speed) { 1258 case 10: 1259 ifmr->ifm_active |= IFM_10_T; 1260 break; 1261 case 100: 1262 ifmr->ifm_active |= IFM_100_TX; 1263 break; 1264 case 1000: 1265 ifmr->ifm_active |= IFM_1000_T; 1266 break; 1267 } 1268 if (sc->link_duplex == FULL_DUPLEX) 1269 ifmr->ifm_active |= IFM_FDX; 1270 else 1271 ifmr->ifm_active |= IFM_HDX; 1272 } 1273} 1274 1275/********************************************************************* 1276 * 1277 * Media Ioctl callback 1278 * 1279 * This routine is called when the user changes speed/duplex using 1280 * media/mediopt option with ifconfig. 1281 * 1282 **********************************************************************/ 1283static int 1284em_media_change(struct ifnet *ifp) 1285{ 1286 struct em_softc *sc = ifp->if_softc; 1287 struct ifmedia *ifm = &sc->media; 1288 1289 INIT_DEBUGOUT("em_media_change: begin"); 1290 1291 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1292 return (EINVAL); 1293 1294 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1295 case IFM_AUTO: 1296 sc->hw.autoneg = DO_AUTO_NEG; 1297 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1298 break; 1299 case IFM_1000_SX: 1300 case IFM_1000_T: 1301 sc->hw.autoneg = DO_AUTO_NEG; 1302 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1303 break; 1304 case IFM_100_TX: 1305 sc->hw.autoneg = FALSE; 1306 sc->hw.autoneg_advertised = 0; 1307 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1308 sc->hw.forced_speed_duplex = em_100_full; 1309 else 1310 sc->hw.forced_speed_duplex = em_100_half; 1311 break; 1312 case IFM_10_T: 1313 sc->hw.autoneg = FALSE; 1314 sc->hw.autoneg_advertised = 0; 1315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1316 sc->hw.forced_speed_duplex = em_10_full; 1317 else 1318 sc->hw.forced_speed_duplex = em_10_half; 1319 break; 1320 default: 1321 device_printf(sc->dev, "Unsupported media type\n"); 1322 } 1323 1324 /* As the speed/duplex settings my have changed we need to 1325 * reset the PHY. 1326 */ 1327 sc->hw.phy_reset_disable = FALSE; 1328 1329 em_init(sc); 1330 1331 return (0); 1332} 1333 1334/********************************************************************* 1335 * 1336 * This routine maps the mbufs to tx descriptors. 1337 * 1338 * return 0 on success, positive on failure 1339 **********************************************************************/ 1340static int 1341em_encap(struct em_softc *sc, struct mbuf **m_headp) 1342{ 1343 struct ifnet *ifp = sc->ifp; 1344 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1345 bus_dmamap_t map; 1346 struct em_buffer *tx_buffer; 1347 struct em_tx_desc *current_tx_desc; 1348 struct mbuf *m_head; 1349 struct m_tag *mtag; 1350 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1351 int nsegs, i, j; 1352 int error = 0; 1353 1354 m_head = *m_headp; 1355 current_tx_desc = NULL; 1356 txd_used = txd_saved = 0; 1357 1358 /* 1359 * Force a cleanup if number of TX descriptors 1360 * available hits the threshold. 1361 */ 1362 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1363 em_txeof(sc); 1364 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1365 sc->no_tx_desc_avail1++; 1366 return (ENOBUFS); 1367 } 1368 } 1369 1370 /* 1371 * Map the packet for DMA. 1372 */ 1373 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1374 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1375 segs, &nsegs, BUS_DMA_NOWAIT); 1376 map = tx_buffer->map; 1377 if (error != 0) { 1378 sc->no_tx_dma_setup++; 1379 return (error); 1380 } 1381 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1382 1383 if (nsegs > sc->num_tx_desc_avail) { 1384 sc->no_tx_desc_avail2++; 1385 error = ENOBUFS; 1386 goto encap_fail; 1387 } 1388 1389 if (ifp->if_hwassist > 0) 1390 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1391 else 1392 txd_upper = txd_lower = 0; 1393 1394 /* Find out if we are in vlan mode. */ 1395 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1396 1397 /* 1398 * When operating in promiscuous mode, hardware encapsulation for 1399 * packets is disabled. This means we have to add the vlan 1400 * encapsulation in the driver, since it will have come down from the 1401 * VLAN layer with a tag instead of a VLAN header. 1402 */ 1403 if (mtag != NULL && sc->em_insert_vlan_header) { 1404 struct ether_vlan_header *evl; 1405 struct ether_header eh; 1406 1407 m_head = m_pullup(m_head, sizeof(eh)); 1408 if (m_head == NULL) { 1409 *m_headp = NULL; 1410 error = ENOBUFS; 1411 goto encap_fail; 1412 } 1413 eh = *mtod(m_head, struct ether_header *); 1414 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1415 if (m_head == NULL) { 1416 *m_headp = NULL; 1417 error = ENOBUFS; 1418 goto encap_fail; 1419 } 1420 m_head = m_pullup(m_head, sizeof(*evl)); 1421 if (m_head == NULL) { 1422 *m_headp = NULL; 1423 error = ENOBUFS; 1424 goto encap_fail; 1425 } 1426 evl = mtod(m_head, struct ether_vlan_header *); 1427 bcopy(&eh, evl, sizeof(*evl)); 1428 evl->evl_proto = evl->evl_encap_proto; 1429 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1430 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1431 m_tag_delete(m_head, mtag); 1432 mtag = NULL; 1433 *m_headp = m_head; 1434 } 1435 1436 i = sc->next_avail_tx_desc; 1437 if (sc->pcix_82544) { 1438 txd_saved = i; 1439 txd_used = 0; 1440 } 1441 for (j = 0; j < nsegs; j++) { 1442 /* If adapter is 82544 and on PCIX bus. */ 1443 if(sc->pcix_82544) { 1444 DESC_ARRAY desc_array; 1445 uint32_t array_elements, counter; 1446 1447 /* 1448 * Check the Address and Length combination and 1449 * split the data accordingly 1450 */ 1451 array_elements = em_fill_descriptors(segs[j].ds_addr, 1452 segs[j].ds_len, &desc_array); 1453 for (counter = 0; counter < array_elements; counter++) { 1454 if (txd_used == sc->num_tx_desc_avail) { 1455 sc->next_avail_tx_desc = txd_saved; 1456 sc->no_tx_desc_avail2++; 1457 error = ENOBUFS; 1458 goto encap_fail; 1459 } 1460 tx_buffer = &sc->tx_buffer_area[i]; 1461 current_tx_desc = &sc->tx_desc_base[i]; 1462 current_tx_desc->buffer_addr = htole64( 1463 desc_array.descriptor[counter].address); 1464 current_tx_desc->lower.data = htole32( 1465 (sc->txd_cmd | txd_lower | 1466 (uint16_t)desc_array.descriptor[counter].length)); 1467 current_tx_desc->upper.data = htole32((txd_upper)); 1468 if (++i == sc->num_tx_desc) 1469 i = 0; 1470 1471 tx_buffer->m_head = NULL; 1472 txd_used++; 1473 } 1474 } else { 1475 tx_buffer = &sc->tx_buffer_area[i]; 1476 current_tx_desc = &sc->tx_desc_base[i]; 1477 1478 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1479 current_tx_desc->lower.data = htole32( 1480 sc->txd_cmd | txd_lower | segs[j].ds_len); 1481 current_tx_desc->upper.data = htole32(txd_upper); 1482 1483 if (++i == sc->num_tx_desc) 1484 i = 0; 1485 1486 tx_buffer->m_head = NULL; 1487 } 1488 } 1489 1490 sc->next_avail_tx_desc = i; 1491 if (sc->pcix_82544) 1492 sc->num_tx_desc_avail -= txd_used; 1493 else 1494 sc->num_tx_desc_avail -= nsegs; 1495 1496 if (mtag != NULL) { 1497 /* Set the vlan id. */ 1498 current_tx_desc->upper.fields.special = 1499 htole16(VLAN_TAG_VALUE(mtag)); 1500 1501 /* Tell hardware to add tag. */ 1502 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1503 } 1504 1505 tx_buffer->m_head = m_head; 1506 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1507 1508 /* 1509 * Last Descriptor of Packet needs End Of Packet (EOP). 1510 */ 1511 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1512 1513 /* 1514 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1515 * that this frame is available to transmit. 1516 */ 1517 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1520 em_82547_move_tail_locked(sc); 1521 else { 1522 E1000_WRITE_REG(&sc->hw, TDT, i); 1523 if (sc->hw.mac_type == em_82547) 1524 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1525 } 1526 1527 return (0); 1528 1529encap_fail: 1530 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1531 return (error); 1532} 1533 1534/********************************************************************* 1535 * 1536 * 82547 workaround to avoid controller hang in half-duplex environment. 1537 * The workaround is to avoid queuing a large packet that would span 1538 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1539 * in this case. We do that only when FIFO is quiescent. 1540 * 1541 **********************************************************************/ 1542static void 1543em_82547_move_tail_locked(struct em_softc *sc) 1544{ 1545 uint16_t hw_tdt; 1546 uint16_t sw_tdt; 1547 struct em_tx_desc *tx_desc; 1548 uint16_t length = 0; 1549 boolean_t eop = 0; 1550 1551 EM_LOCK_ASSERT(sc); 1552 1553 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1554 sw_tdt = sc->next_avail_tx_desc; 1555 1556 while (hw_tdt != sw_tdt) { 1557 tx_desc = &sc->tx_desc_base[hw_tdt]; 1558 length += tx_desc->lower.flags.length; 1559 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1560 if(++hw_tdt == sc->num_tx_desc) 1561 hw_tdt = 0; 1562 1563 if (eop) { 1564 if (em_82547_fifo_workaround(sc, length)) { 1565 sc->tx_fifo_wrk_cnt++; 1566 callout_reset(&sc->tx_fifo_timer, 1, 1567 em_82547_move_tail, sc); 1568 break; 1569 } 1570 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1571 em_82547_update_fifo_head(sc, length); 1572 length = 0; 1573 } 1574 } 1575} 1576 1577static void 1578em_82547_move_tail(void *arg) 1579{ 1580 struct em_softc *sc = arg; 1581 1582 EM_LOCK(sc); 1583 em_82547_move_tail_locked(sc); 1584 EM_UNLOCK(sc); 1585} 1586 1587static int 1588em_82547_fifo_workaround(struct em_softc *sc, int len) 1589{ 1590 int fifo_space, fifo_pkt_len; 1591 1592 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1593 1594 if (sc->link_duplex == HALF_DUPLEX) { 1595 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1596 1597 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1598 if (em_82547_tx_fifo_reset(sc)) 1599 return (0); 1600 else 1601 return (1); 1602 } 1603 } 1604 1605 return (0); 1606} 1607 1608static void 1609em_82547_update_fifo_head(struct em_softc *sc, int len) 1610{ 1611 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1612 1613 /* tx_fifo_head is always 16 byte aligned */ 1614 sc->tx_fifo_head += fifo_pkt_len; 1615 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1616 sc->tx_fifo_head -= sc->tx_fifo_size; 1617 } 1618} 1619 1620 1621static int 1622em_82547_tx_fifo_reset(struct em_softc *sc) 1623{ 1624 uint32_t tctl; 1625 1626 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1627 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1628 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1629 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1630 1631 /* Disable TX unit */ 1632 tctl = E1000_READ_REG(&sc->hw, TCTL); 1633 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1634 1635 /* Reset FIFO pointers */ 1636 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1637 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1638 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1639 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1640 1641 /* Re-enable TX unit */ 1642 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1643 E1000_WRITE_FLUSH(&sc->hw); 1644 1645 sc->tx_fifo_head = 0; 1646 sc->tx_fifo_reset_cnt++; 1647 1648 return (TRUE); 1649 } 1650 else { 1651 return (FALSE); 1652 } 1653} 1654 1655static void 1656em_set_promisc(struct em_softc *sc) 1657{ 1658 struct ifnet *ifp = sc->ifp; 1659 uint32_t reg_rctl; 1660 1661 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1662 1663 if (ifp->if_flags & IFF_PROMISC) { 1664 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1665 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1666 /* Disable VLAN stripping in promiscous mode 1667 * This enables bridging of vlan tagged frames to occur 1668 * and also allows vlan tags to be seen in tcpdump 1669 */ 1670 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1671 em_disable_vlans(sc); 1672 sc->em_insert_vlan_header = 1; 1673 } else if (ifp->if_flags & IFF_ALLMULTI) { 1674 reg_rctl |= E1000_RCTL_MPE; 1675 reg_rctl &= ~E1000_RCTL_UPE; 1676 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1677 sc->em_insert_vlan_header = 0; 1678 } else 1679 sc->em_insert_vlan_header = 0; 1680} 1681 1682static void 1683em_disable_promisc(struct em_softc *sc) 1684{ 1685 struct ifnet *ifp = sc->ifp; 1686 uint32_t reg_rctl; 1687 1688 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1689 1690 reg_rctl &= (~E1000_RCTL_UPE); 1691 reg_rctl &= (~E1000_RCTL_MPE); 1692 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1693 1694 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1695 em_enable_vlans(sc); 1696 sc->em_insert_vlan_header = 0; 1697} 1698 1699 1700/********************************************************************* 1701 * Multicast Update 1702 * 1703 * This routine is called whenever multicast address list is updated. 1704 * 1705 **********************************************************************/ 1706 1707static void 1708em_set_multi(struct em_softc *sc) 1709{ 1710 struct ifnet *ifp = sc->ifp; 1711 struct ifmultiaddr *ifma; 1712 uint32_t reg_rctl = 0; 1713 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1714 int mcnt = 0; 1715 1716 IOCTL_DEBUGOUT("em_set_multi: begin"); 1717 1718 if (sc->hw.mac_type == em_82542_rev2_0) { 1719 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1720 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1721 em_pci_clear_mwi(&sc->hw); 1722 reg_rctl |= E1000_RCTL_RST; 1723 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1724 msec_delay(5); 1725 } 1726 1727 IF_ADDR_LOCK(ifp); 1728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1729 if (ifma->ifma_addr->sa_family != AF_LINK) 1730 continue; 1731 1732 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1733 break; 1734 1735 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1736 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1737 mcnt++; 1738 } 1739 IF_ADDR_UNLOCK(ifp); 1740 1741 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1742 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1743 reg_rctl |= E1000_RCTL_MPE; 1744 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1745 } else 1746 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1747 1748 if (sc->hw.mac_type == em_82542_rev2_0) { 1749 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1750 reg_rctl &= ~E1000_RCTL_RST; 1751 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1752 msec_delay(5); 1753 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1754 em_pci_set_mwi(&sc->hw); 1755 } 1756} 1757 1758 1759/********************************************************************* 1760 * Timer routine 1761 * 1762 * This routine checks for link status and updates statistics. 1763 * 1764 **********************************************************************/ 1765 1766static void 1767em_local_timer(void *arg) 1768{ 1769 struct em_softc *sc = arg; 1770 struct ifnet *ifp = sc->ifp; 1771 1772 EM_LOCK(sc); 1773 1774 em_check_for_link(&sc->hw); 1775 em_update_link_status(sc); 1776 em_update_stats_counters(sc); 1777 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1778 em_print_hw_stats(sc); 1779 em_smartspeed(sc); 1780 1781 callout_reset(&sc->timer, hz, em_local_timer, sc); 1782 1783 EM_UNLOCK(sc); 1784} 1785 1786static void 1787em_update_link_status(struct em_softc *sc) 1788{ 1789 struct ifnet *ifp = sc->ifp; 1790 device_t dev = sc->dev; 1791 1792 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1793 if (sc->link_active == 0) { 1794 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1795 &sc->link_duplex); 1796 if (bootverbose) 1797 device_printf(dev, "Link is up %d Mbps %s\n", 1798 sc->link_speed, 1799 ((sc->link_duplex == FULL_DUPLEX) ? 1800 "Full Duplex" : "Half Duplex")); 1801 sc->link_active = 1; 1802 sc->smartspeed = 0; 1803 ifp->if_baudrate = sc->link_speed * 1000000; 1804 if_link_state_change(ifp, LINK_STATE_UP); 1805 } 1806 } else { 1807 if (sc->link_active == 1) { 1808 ifp->if_baudrate = sc->link_speed = 0; 1809 sc->link_duplex = 0; 1810 if (bootverbose) 1811 device_printf(dev, "Link is Down\n"); 1812 sc->link_active = 0; 1813 if_link_state_change(ifp, LINK_STATE_DOWN); 1814 } 1815 } 1816} 1817 1818/********************************************************************* 1819 * 1820 * This routine disables all traffic on the adapter by issuing a 1821 * global reset on the MAC and deallocates TX/RX buffers. 1822 * 1823 **********************************************************************/ 1824 1825static void 1826em_stop(void *arg) 1827{ 1828 struct em_softc *sc = arg; 1829 struct ifnet *ifp = sc->ifp; 1830 1831 EM_LOCK_ASSERT(sc); 1832 1833 INIT_DEBUGOUT("em_stop: begin"); 1834 1835 em_disable_intr(sc); 1836 em_reset_hw(&sc->hw); 1837 callout_stop(&sc->timer); 1838 callout_stop(&sc->tx_fifo_timer); 1839 em_free_transmit_structures(sc); 1840 em_free_receive_structures(sc); 1841 1842 /* Tell the stack that the interface is no longer active */ 1843 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1844} 1845 1846 1847/********************************************************************* 1848 * 1849 * Determine hardware revision. 1850 * 1851 **********************************************************************/ 1852static void 1853em_identify_hardware(struct em_softc *sc) 1854{ 1855 device_t dev = sc->dev; 1856 1857 /* Make sure our PCI config space has the necessary stuff set */ 1858 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1859 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1860 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1861 device_printf(dev, "Memory Access and/or Bus Master bits " 1862 "were not set!\n"); 1863 sc->hw.pci_cmd_word |= 1864 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1865 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1866 } 1867 1868 /* Save off the information about this board */ 1869 sc->hw.vendor_id = pci_get_vendor(dev); 1870 sc->hw.device_id = pci_get_device(dev); 1871 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1872 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1873 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1874 1875 /* Identify the MAC */ 1876 if (em_set_mac_type(&sc->hw)) 1877 device_printf(dev, "Unknown MAC Type\n"); 1878 1879 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1880 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1881 sc->hw.phy_init_script = TRUE; 1882} 1883 1884static int 1885em_allocate_pci_resources(struct em_softc *sc) 1886{ 1887 device_t dev = sc->dev; 1888 int val, rid; 1889 1890 rid = PCIR_BAR(0); 1891 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1892 &rid, RF_ACTIVE); 1893 if (sc->res_memory == NULL) { 1894 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1895 return (ENXIO); 1896 } 1897 sc->osdep.mem_bus_space_tag = 1898 rman_get_bustag(sc->res_memory); 1899 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1900 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1901 1902 if (sc->hw.mac_type > em_82543) { 1903 /* Figure our where our IO BAR is ? */ 1904 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1905 val = pci_read_config(dev, rid, 4); 1906 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1907 sc->io_rid = rid; 1908 break; 1909 } 1910 rid += 4; 1911 /* check for 64bit BAR */ 1912 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1913 rid += 4; 1914 } 1915 if (rid >= PCIR_CIS) { 1916 device_printf(dev, "Unable to locate IO BAR\n"); 1917 return (ENXIO); 1918 } 1919 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1920 &sc->io_rid, RF_ACTIVE); 1921 if (sc->res_ioport == NULL) { 1922 device_printf(dev, "Unable to allocate bus resource: " 1923 "ioport\n"); 1924 return (ENXIO); 1925 } 1926 sc->hw.io_base = 0; 1927 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1928 sc->osdep.io_bus_space_handle = 1929 rman_get_bushandle(sc->res_ioport); 1930 } 1931 1932 rid = 0x0; 1933 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1934 RF_SHAREABLE | RF_ACTIVE); 1935 if (sc->res_interrupt == NULL) { 1936 device_printf(dev, "Unable to allocate bus resource: " 1937 "interrupt\n"); 1938 return (ENXIO); 1939 } 1940 1941 sc->hw.back = &sc->osdep; 1942 1943 return (0); 1944} 1945 1946int 1947em_allocate_intr(struct em_softc *sc) 1948{ 1949 device_t dev = sc->dev; 1950 int error; 1951 1952 /* Manually turn off all interrupts */ 1953 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1954 1955 /* 1956 * Try allocating a fast interrupt and the associated deferred 1957 * processing contexts. If that doesn't work, try just using an 1958 * ithread. 1959 */ 1960#ifndef NO_EM_FASTINTR 1961 /* Init the deferred processing contexts. */ 1962 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1963 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1964 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1965 taskqueue_thread_enqueue, &sc->tq); 1966 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1967 device_get_nameunit(sc->dev)); 1968 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1969 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 1970 &sc->int_handler_tag)) != 0) { 1971 device_printf(dev, "Failed to register fast interrupt " 1972 "handler: %d\n", error); 1973 taskqueue_free(sc->tq); 1974 sc->tq = NULL; 1975 } 1976#endif 1977 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 1978 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 1979 &sc->int_handler_tag)) != 0) { 1980 device_printf(dev, "Failed to register interrupt handler"); 1981 return (error); 1982 } 1983 1984 em_enable_intr(sc); 1985 return (0); 1986} 1987 1988static void 1989em_free_intr(struct em_softc *sc) 1990{ 1991 device_t dev = sc->dev; 1992 1993 if (sc->res_interrupt != NULL) { 1994 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 1995 sc->int_handler_tag = NULL; 1996 } 1997 if (sc->tq != NULL) { 1998 taskqueue_drain(sc->tq, &sc->rxtx_task); 1999 taskqueue_drain(taskqueue_fast, &sc->link_task); 2000 taskqueue_free(sc->tq); 2001 sc->tq = NULL; 2002 } 2003} 2004 2005static void 2006em_free_pci_resources(struct em_softc *sc) 2007{ 2008 device_t dev = sc->dev; 2009 2010 if (sc->res_interrupt != NULL) 2011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2012 2013 if (sc->res_memory != NULL) 2014 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2015 sc->res_memory); 2016 2017 if (sc->res_ioport != NULL) 2018 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2019 sc->res_ioport); 2020} 2021 2022/********************************************************************* 2023 * 2024 * Initialize the hardware to a configuration as specified by the 2025 * adapter structure. The controller is reset, the EEPROM is 2026 * verified, the MAC address is set, then the shared initialization 2027 * routines are called. 2028 * 2029 **********************************************************************/ 2030static int 2031em_hardware_init(struct em_softc *sc) 2032{ 2033 device_t dev = sc->dev; 2034 uint16_t rx_buffer_size; 2035 2036 INIT_DEBUGOUT("em_hardware_init: begin"); 2037 /* Issue a global reset */ 2038 em_reset_hw(&sc->hw); 2039 2040 /* When hardware is reset, fifo_head is also reset */ 2041 sc->tx_fifo_head = 0; 2042 2043 /* Make sure we have a good EEPROM before we read from it */ 2044 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2045 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2046 return (EIO); 2047 } 2048 2049 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2050 device_printf(dev, "EEPROM read error while reading part " 2051 "number\n"); 2052 return (EIO); 2053 } 2054 2055 /* 2056 * These parameters control the automatic generation (Tx) and 2057 * response (Rx) to Ethernet PAUSE frames. 2058 * - High water mark should allow for at least two frames to be 2059 * received after sending an XOFF. 2060 * - Low water mark works best when it is very near the high water mark. 2061 * This allows the receiver to restart by sending XON when it has 2062 * drained a bit. Here we use an arbitary value of 1500 which will 2063 * restart after one full frame is pulled from the buffer. There 2064 * could be several smaller frames in the buffer and if so they will 2065 * not trigger the XON until their total number reduces the buffer 2066 * by 1500. 2067 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2068 */ 2069 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2070 2071 sc->hw.fc_high_water = rx_buffer_size - 2072 roundup2(sc->hw.max_frame_size, 1024); 2073 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2074 sc->hw.fc_pause_time = 0x1000; 2075 sc->hw.fc_send_xon = TRUE; 2076 sc->hw.fc = em_fc_full; 2077 2078 if (em_init_hw(&sc->hw) < 0) { 2079 device_printf(dev, "Hardware Initialization Failed"); 2080 return (EIO); 2081 } 2082 2083 em_check_for_link(&sc->hw); 2084 2085 return (0); 2086} 2087 2088/********************************************************************* 2089 * 2090 * Setup networking device structure and register an interface. 2091 * 2092 **********************************************************************/ 2093static void 2094em_setup_interface(device_t dev, struct em_softc *sc) 2095{ 2096 struct ifnet *ifp; 2097 INIT_DEBUGOUT("em_setup_interface: begin"); 2098 2099 ifp = sc->ifp = if_alloc(IFT_ETHER); 2100 if (ifp == NULL) 2101 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2102 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2103 ifp->if_mtu = ETHERMTU; 2104 ifp->if_init = em_init; 2105 ifp->if_softc = sc; 2106 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2107 ifp->if_ioctl = em_ioctl; 2108 ifp->if_start = em_start; 2109 ifp->if_watchdog = em_watchdog; 2110 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2111 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2112 IFQ_SET_READY(&ifp->if_snd); 2113 2114 ether_ifattach(ifp, sc->hw.mac_addr); 2115 2116 ifp->if_capabilities = ifp->if_capenable = 0; 2117 2118 if (sc->hw.mac_type >= em_82543) { 2119 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2120 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2121 } 2122 2123 /* 2124 * Tell the upper layer(s) we support long frames. 2125 */ 2126 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2127 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2128 ifp->if_capenable |= IFCAP_VLAN_MTU; 2129 2130#ifdef DEVICE_POLLING 2131 ifp->if_capabilities |= IFCAP_POLLING; 2132#endif 2133 2134 /* 2135 * Specify the media types supported by this adapter and register 2136 * callbacks to update media and link information 2137 */ 2138 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2139 if (sc->hw.media_type == em_media_type_fiber) { 2140 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2141 0, NULL); 2142 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2143 0, NULL); 2144 } else { 2145 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2146 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2147 0, NULL); 2148 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2149 0, NULL); 2150 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2151 0, NULL); 2152 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2153 0, NULL); 2154 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2155 } 2156 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2157 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2158} 2159 2160 2161/********************************************************************* 2162 * 2163 * Workaround for SmartSpeed on 82541 and 82547 controllers 2164 * 2165 **********************************************************************/ 2166static void 2167em_smartspeed(struct em_softc *sc) 2168{ 2169 uint16_t phy_tmp; 2170 2171 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2172 sc->hw.autoneg == 0 || 2173 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2174 return; 2175 2176 if (sc->smartspeed == 0) { 2177 /* If Master/Slave config fault is asserted twice, 2178 * we assume back-to-back */ 2179 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2180 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2181 return; 2182 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2183 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2184 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2185 if(phy_tmp & CR_1000T_MS_ENABLE) { 2186 phy_tmp &= ~CR_1000T_MS_ENABLE; 2187 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2188 phy_tmp); 2189 sc->smartspeed++; 2190 if(sc->hw.autoneg && 2191 !em_phy_setup_autoneg(&sc->hw) && 2192 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2193 &phy_tmp)) { 2194 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2195 MII_CR_RESTART_AUTO_NEG); 2196 em_write_phy_reg(&sc->hw, PHY_CTRL, 2197 phy_tmp); 2198 } 2199 } 2200 } 2201 return; 2202 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2203 /* If still no link, perhaps using 2/3 pair cable */ 2204 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2205 phy_tmp |= CR_1000T_MS_ENABLE; 2206 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2207 if(sc->hw.autoneg && 2208 !em_phy_setup_autoneg(&sc->hw) && 2209 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2210 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2211 MII_CR_RESTART_AUTO_NEG); 2212 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2213 } 2214 } 2215 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2216 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2217 sc->smartspeed = 0; 2218} 2219 2220 2221/* 2222 * Manage DMA'able memory. 2223 */ 2224static void 2225em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2226{ 2227 if (error) 2228 return; 2229 *(bus_addr_t *) arg = segs[0].ds_addr; 2230} 2231 2232static int 2233em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2234 int mapflags) 2235{ 2236 int error; 2237 2238 error = bus_dma_tag_create(NULL, /* parent */ 2239 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2240 BUS_SPACE_MAXADDR, /* lowaddr */ 2241 BUS_SPACE_MAXADDR, /* highaddr */ 2242 NULL, NULL, /* filter, filterarg */ 2243 size, /* maxsize */ 2244 1, /* nsegments */ 2245 size, /* maxsegsize */ 2246 0, /* flags */ 2247 NULL, /* lockfunc */ 2248 NULL, /* lockarg */ 2249 &dma->dma_tag); 2250 if (error) { 2251 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2252 __func__, error); 2253 goto fail_0; 2254 } 2255 2256 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2257 BUS_DMA_NOWAIT, &dma->dma_map); 2258 if (error) { 2259 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2260 __func__, (uintmax_t)size, error); 2261 goto fail_2; 2262 } 2263 2264 dma->dma_paddr = 0; 2265 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2266 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2267 if (error || dma->dma_paddr == 0) { 2268 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2269 __func__, error); 2270 goto fail_3; 2271 } 2272 2273 return (0); 2274 2275fail_3: 2276 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2277fail_2: 2278 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2279 bus_dma_tag_destroy(dma->dma_tag); 2280fail_0: 2281 dma->dma_map = NULL; 2282 dma->dma_tag = NULL; 2283 2284 return (error); 2285} 2286 2287static void 2288em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2289{ 2290 if (dma->dma_tag == NULL) 2291 return; 2292 if (dma->dma_map != NULL) { 2293 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2295 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2296 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2297 dma->dma_map = NULL; 2298 } 2299 bus_dma_tag_destroy(dma->dma_tag); 2300 dma->dma_tag = NULL; 2301} 2302 2303 2304/********************************************************************* 2305 * 2306 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2307 * the information needed to transmit a packet on the wire. 2308 * 2309 **********************************************************************/ 2310static int 2311em_allocate_transmit_structures(struct em_softc *sc) 2312{ 2313 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2314 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2315 if (sc->tx_buffer_area == NULL) { 2316 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2317 return (ENOMEM); 2318 } 2319 2320 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2321 2322 return (0); 2323} 2324 2325/********************************************************************* 2326 * 2327 * Allocate and initialize transmit structures. 2328 * 2329 **********************************************************************/ 2330static int 2331em_setup_transmit_structures(struct em_softc *sc) 2332{ 2333 device_t dev = sc->dev; 2334 struct em_buffer *tx_buffer; 2335 bus_size_t size; 2336 int error, i; 2337 2338 /* 2339 * Setup DMA descriptor areas. 2340 */ 2341 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2342 if ((error = bus_dma_tag_create(NULL, /* parent */ 2343 1, 0, /* alignment, bounds */ 2344 BUS_SPACE_MAXADDR, /* lowaddr */ 2345 BUS_SPACE_MAXADDR, /* highaddr */ 2346 NULL, NULL, /* filter, filterarg */ 2347 size, /* maxsize */ 2348 EM_MAX_SCATTER, /* nsegments */ 2349 size, /* maxsegsize */ 2350 0, /* flags */ 2351 NULL, /* lockfunc */ 2352 NULL, /* lockarg */ 2353 &sc->txtag)) != 0) { 2354 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2355 goto fail; 2356 } 2357 2358 if ((error = em_allocate_transmit_structures(sc)) != 0) 2359 goto fail; 2360 2361 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2362 tx_buffer = sc->tx_buffer_area; 2363 for (i = 0; i < sc->num_tx_desc; i++) { 2364 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2365 if (error != 0) { 2366 device_printf(dev, "Unable to create TX DMA map\n"); 2367 goto fail; 2368 } 2369 tx_buffer++; 2370 } 2371 2372 sc->next_avail_tx_desc = 0; 2373 sc->oldest_used_tx_desc = 0; 2374 2375 /* Set number of descriptors available */ 2376 sc->num_tx_desc_avail = sc->num_tx_desc; 2377 2378 /* Set checksum context */ 2379 sc->active_checksum_context = OFFLOAD_NONE; 2380 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2381 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2382 2383 return (0); 2384 2385fail: 2386 em_free_transmit_structures(sc); 2387 return (error); 2388} 2389 2390/********************************************************************* 2391 * 2392 * Enable transmit unit. 2393 * 2394 **********************************************************************/ 2395static void 2396em_initialize_transmit_unit(struct em_softc *sc) 2397{ 2398 uint32_t reg_tctl; 2399 uint32_t reg_tipg = 0; 2400 uint64_t bus_addr; 2401 2402 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2403 /* Setup the Base and Length of the Tx Descriptor Ring */ 2404 bus_addr = sc->txdma.dma_paddr; 2405 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2406 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2407 E1000_WRITE_REG(&sc->hw, TDLEN, 2408 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2409 2410 /* Setup the HW Tx Head and Tail descriptor pointers */ 2411 E1000_WRITE_REG(&sc->hw, TDH, 0); 2412 E1000_WRITE_REG(&sc->hw, TDT, 0); 2413 2414 2415 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2416 E1000_READ_REG(&sc->hw, TDLEN)); 2417 2418 /* Set the default values for the Tx Inter Packet Gap timer */ 2419 switch (sc->hw.mac_type) { 2420 case em_82542_rev2_0: 2421 case em_82542_rev2_1: 2422 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2423 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2424 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2425 break; 2426 default: 2427 if (sc->hw.media_type == em_media_type_fiber) 2428 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2429 else 2430 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2431 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2432 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2433 } 2434 2435 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2436 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2437 if(sc->hw.mac_type >= em_82540) 2438 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2439 2440 /* Program the Transmit Control Register */ 2441 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2442 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2443 if (sc->hw.mac_type >= em_82571) 2444 reg_tctl |= E1000_TCTL_MULR; 2445 if (sc->link_duplex == 1) { 2446 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2447 } else { 2448 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2449 } 2450 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2451 2452 /* Setup Transmit Descriptor Settings for this adapter */ 2453 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2454 2455 if (sc->tx_int_delay.value > 0) 2456 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2457} 2458 2459/********************************************************************* 2460 * 2461 * Free all transmit related data structures. 2462 * 2463 **********************************************************************/ 2464static void 2465em_free_transmit_structures(struct em_softc *sc) 2466{ 2467 struct em_buffer *tx_buffer; 2468 int i; 2469 2470 INIT_DEBUGOUT("free_transmit_structures: begin"); 2471 2472 if (sc->tx_buffer_area != NULL) { 2473 tx_buffer = sc->tx_buffer_area; 2474 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2475 if (tx_buffer->m_head != NULL) { 2476 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2477 BUS_DMASYNC_POSTWRITE); 2478 bus_dmamap_unload(sc->txtag, 2479 tx_buffer->map); 2480 m_freem(tx_buffer->m_head); 2481 tx_buffer->m_head = NULL; 2482 } else if (tx_buffer->map != NULL) 2483 bus_dmamap_unload(sc->txtag, 2484 tx_buffer->map); 2485 if (tx_buffer->map != NULL) { 2486 bus_dmamap_destroy(sc->txtag, 2487 tx_buffer->map); 2488 tx_buffer->map = NULL; 2489 } 2490 } 2491 } 2492 if (sc->tx_buffer_area != NULL) { 2493 free(sc->tx_buffer_area, M_DEVBUF); 2494 sc->tx_buffer_area = NULL; 2495 } 2496 if (sc->txtag != NULL) { 2497 bus_dma_tag_destroy(sc->txtag); 2498 sc->txtag = NULL; 2499 } 2500} 2501 2502/********************************************************************* 2503 * 2504 * The offload context needs to be set when we transfer the first 2505 * packet of a particular protocol (TCP/UDP). We change the 2506 * context only if the protocol type changes. 2507 * 2508 **********************************************************************/ 2509static void 2510em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2511 uint32_t *txd_upper, uint32_t *txd_lower) 2512{ 2513 struct em_context_desc *TXD; 2514 struct em_buffer *tx_buffer; 2515 int curr_txd; 2516 2517 if (mp->m_pkthdr.csum_flags) { 2518 2519 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2520 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2521 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2522 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2523 return; 2524 else 2525 sc->active_checksum_context = OFFLOAD_TCP_IP; 2526 2527 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2528 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2529 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2530 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2531 return; 2532 else 2533 sc->active_checksum_context = OFFLOAD_UDP_IP; 2534 } else { 2535 *txd_upper = 0; 2536 *txd_lower = 0; 2537 return; 2538 } 2539 } else { 2540 *txd_upper = 0; 2541 *txd_lower = 0; 2542 return; 2543 } 2544 2545 /* If we reach this point, the checksum offload context 2546 * needs to be reset. 2547 */ 2548 curr_txd = sc->next_avail_tx_desc; 2549 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2550 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2551 2552 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2553 TXD->lower_setup.ip_fields.ipcso = 2554 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2555 TXD->lower_setup.ip_fields.ipcse = 2556 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2557 2558 TXD->upper_setup.tcp_fields.tucss = 2559 ETHER_HDR_LEN + sizeof(struct ip); 2560 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2561 2562 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2563 TXD->upper_setup.tcp_fields.tucso = 2564 ETHER_HDR_LEN + sizeof(struct ip) + 2565 offsetof(struct tcphdr, th_sum); 2566 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2567 TXD->upper_setup.tcp_fields.tucso = 2568 ETHER_HDR_LEN + sizeof(struct ip) + 2569 offsetof(struct udphdr, uh_sum); 2570 } 2571 2572 TXD->tcp_seg_setup.data = htole32(0); 2573 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2574 2575 tx_buffer->m_head = NULL; 2576 2577 if (++curr_txd == sc->num_tx_desc) 2578 curr_txd = 0; 2579 2580 sc->num_tx_desc_avail--; 2581 sc->next_avail_tx_desc = curr_txd; 2582} 2583 2584/********************************************************************** 2585 * 2586 * Examine each tx_buffer in the used queue. If the hardware is done 2587 * processing the packet then free associated resources. The 2588 * tx_buffer is put back on the free queue. 2589 * 2590 **********************************************************************/ 2591static void 2592em_txeof(struct em_softc *sc) 2593{ 2594 int i, num_avail; 2595 struct em_buffer *tx_buffer; 2596 struct em_tx_desc *tx_desc; 2597 struct ifnet *ifp = sc->ifp; 2598 2599 EM_LOCK_ASSERT(sc); 2600 2601 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2602 return; 2603 2604 num_avail = sc->num_tx_desc_avail; 2605 i = sc->oldest_used_tx_desc; 2606 2607 tx_buffer = &sc->tx_buffer_area[i]; 2608 tx_desc = &sc->tx_desc_base[i]; 2609 2610 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2611 BUS_DMASYNC_POSTREAD); 2612 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2613 2614 tx_desc->upper.data = 0; 2615 num_avail++; 2616 2617 if (tx_buffer->m_head) { 2618 ifp->if_opackets++; 2619 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2620 BUS_DMASYNC_POSTWRITE); 2621 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2622 2623 m_freem(tx_buffer->m_head); 2624 tx_buffer->m_head = NULL; 2625 } 2626 2627 if (++i == sc->num_tx_desc) 2628 i = 0; 2629 2630 tx_buffer = &sc->tx_buffer_area[i]; 2631 tx_desc = &sc->tx_desc_base[i]; 2632 } 2633 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2634 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2635 2636 sc->oldest_used_tx_desc = i; 2637 2638 /* 2639 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2640 * that it is OK to send packets. 2641 * If there are no pending descriptors, clear the timeout. Otherwise, 2642 * if some descriptors have been freed, restart the timeout. 2643 */ 2644 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2645 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2646 if (num_avail == sc->num_tx_desc) 2647 ifp->if_timer = 0; 2648 else if (num_avail != sc->num_tx_desc_avail) 2649 ifp->if_timer = EM_TX_TIMEOUT; 2650 } 2651 sc->num_tx_desc_avail = num_avail; 2652} 2653 2654/********************************************************************* 2655 * 2656 * Get a buffer from system mbuf buffer pool. 2657 * 2658 **********************************************************************/ 2659static int 2660em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2661{ 2662 struct ifnet *ifp = sc->ifp; 2663 bus_dma_segment_t segs[1]; 2664 struct em_buffer *rx_buffer; 2665 int error, nsegs; 2666 2667 if (mp == NULL) { 2668 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2669 if (mp == NULL) { 2670 sc->mbuf_cluster_failed++; 2671 return (ENOBUFS); 2672 } 2673 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2674 } else { 2675 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2676 mp->m_data = mp->m_ext.ext_buf; 2677 mp->m_next = NULL; 2678 } 2679 2680 if (ifp->if_mtu <= ETHERMTU) 2681 m_adj(mp, ETHER_ALIGN); 2682 2683 rx_buffer = &sc->rx_buffer_area[i]; 2684 2685 /* 2686 * Using memory from the mbuf cluster pool, invoke the 2687 * bus_dma machinery to arrange the memory mapping. 2688 */ 2689 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2690 mp, segs, &nsegs, 0); 2691 if (error != 0) { 2692 m_free(mp); 2693 return (error); 2694 } 2695 /* If nsegs is wrong then the stack is corrupt. */ 2696 KASSERT(nsegs == 1, ("Too many segments returned!")); 2697 rx_buffer->m_head = mp; 2698 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2699 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2700 2701 return (0); 2702} 2703 2704/********************************************************************* 2705 * 2706 * Allocate memory for rx_buffer structures. Since we use one 2707 * rx_buffer per received packet, the maximum number of rx_buffer's 2708 * that we'll need is equal to the number of receive descriptors 2709 * that we've allocated. 2710 * 2711 **********************************************************************/ 2712static int 2713em_allocate_receive_structures(struct em_softc *sc) 2714{ 2715 device_t dev = sc->dev; 2716 struct em_buffer *rx_buffer; 2717 int i, error; 2718 2719 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2720 M_DEVBUF, M_NOWAIT); 2721 if (sc->rx_buffer_area == NULL) { 2722 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2723 return (ENOMEM); 2724 } 2725 2726 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2727 2728 error = bus_dma_tag_create(NULL, /* parent */ 2729 1, 0, /* alignment, bounds */ 2730 BUS_SPACE_MAXADDR, /* lowaddr */ 2731 BUS_SPACE_MAXADDR, /* highaddr */ 2732 NULL, NULL, /* filter, filterarg */ 2733 MCLBYTES, /* maxsize */ 2734 1, /* nsegments */ 2735 MCLBYTES, /* maxsegsize */ 2736 BUS_DMA_ALLOCNOW, /* flags */ 2737 NULL, /* lockfunc */ 2738 NULL, /* lockarg */ 2739 &sc->rxtag); 2740 if (error) { 2741 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2742 __func__, error); 2743 goto fail; 2744 } 2745 2746 rx_buffer = sc->rx_buffer_area; 2747 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2748 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2749 &rx_buffer->map); 2750 if (error) { 2751 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2752 __func__, error); 2753 goto fail; 2754 } 2755 } 2756 2757 for (i = 0; i < sc->num_rx_desc; i++) { 2758 error = em_get_buf(i, sc, NULL); 2759 if (error) 2760 goto fail; 2761 } 2762 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2764 2765 return (0); 2766 2767fail: 2768 em_free_receive_structures(sc); 2769 return (error); 2770} 2771 2772/********************************************************************* 2773 * 2774 * Allocate and initialize receive structures. 2775 * 2776 **********************************************************************/ 2777static int 2778em_setup_receive_structures(struct em_softc *sc) 2779{ 2780 int error; 2781 2782 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2783 2784 if ((error = em_allocate_receive_structures(sc)) != 0) 2785 return (error); 2786 2787 /* Setup our descriptor pointers */ 2788 sc->next_rx_desc_to_check = 0; 2789 2790 return (0); 2791} 2792 2793/********************************************************************* 2794 * 2795 * Enable receive unit. 2796 * 2797 **********************************************************************/ 2798static void 2799em_initialize_receive_unit(struct em_softc *sc) 2800{ 2801 struct ifnet *ifp = sc->ifp; 2802 uint64_t bus_addr; 2803 uint32_t reg_rctl; 2804 uint32_t reg_rxcsum; 2805 2806 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2807 2808 /* 2809 * Make sure receives are disabled while setting 2810 * up the descriptor ring 2811 */ 2812 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2813 2814 /* Set the Receive Delay Timer Register */ 2815 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2816 2817 if(sc->hw.mac_type >= em_82540) { 2818 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2819 2820 /* 2821 * Set the interrupt throttling rate. Value is calculated 2822 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2823 */ 2824#define MAX_INTS_PER_SEC 8000 2825#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2826 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2827 } 2828 2829 /* Setup the Base and Length of the Rx Descriptor Ring */ 2830 bus_addr = sc->rxdma.dma_paddr; 2831 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2832 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2833 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2834 sizeof(struct em_rx_desc)); 2835 2836 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2837 E1000_WRITE_REG(&sc->hw, RDH, 0); 2838 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2839 2840 /* Setup the Receive Control Register */ 2841 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2842 E1000_RCTL_RDMTS_HALF | 2843 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2844 2845 if (sc->hw.tbi_compatibility_on == TRUE) 2846 reg_rctl |= E1000_RCTL_SBP; 2847 2848 2849 switch (sc->rx_buffer_len) { 2850 default: 2851 case EM_RXBUFFER_2048: 2852 reg_rctl |= E1000_RCTL_SZ_2048; 2853 break; 2854 case EM_RXBUFFER_4096: 2855 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2856 break; 2857 case EM_RXBUFFER_8192: 2858 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2859 break; 2860 case EM_RXBUFFER_16384: 2861 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2862 break; 2863 } 2864 2865 if (ifp->if_mtu > ETHERMTU) 2866 reg_rctl |= E1000_RCTL_LPE; 2867 2868 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2869 if ((sc->hw.mac_type >= em_82543) && 2870 (ifp->if_capenable & IFCAP_RXCSUM)) { 2871 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2872 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2873 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2874 } 2875 2876 /* Enable Receives */ 2877 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2878} 2879 2880/********************************************************************* 2881 * 2882 * Free receive related data structures. 2883 * 2884 **********************************************************************/ 2885static void 2886em_free_receive_structures(struct em_softc *sc) 2887{ 2888 struct em_buffer *rx_buffer; 2889 int i; 2890 2891 INIT_DEBUGOUT("free_receive_structures: begin"); 2892 2893 if (sc->rx_buffer_area != NULL) { 2894 rx_buffer = sc->rx_buffer_area; 2895 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2896 if (rx_buffer->m_head != NULL) { 2897 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2898 BUS_DMASYNC_POSTREAD); 2899 bus_dmamap_unload(sc->rxtag, 2900 rx_buffer->map); 2901 m_freem(rx_buffer->m_head); 2902 rx_buffer->m_head = NULL; 2903 } else if (rx_buffer->map != NULL) 2904 bus_dmamap_unload(sc->rxtag, 2905 rx_buffer->map); 2906 if (rx_buffer->map != NULL) { 2907 bus_dmamap_destroy(sc->rxtag, 2908 rx_buffer->map); 2909 rx_buffer->map = NULL; 2910 } 2911 } 2912 } 2913 if (sc->rx_buffer_area != NULL) { 2914 free(sc->rx_buffer_area, M_DEVBUF); 2915 sc->rx_buffer_area = NULL; 2916 } 2917 if (sc->rxtag != NULL) { 2918 bus_dma_tag_destroy(sc->rxtag); 2919 sc->rxtag = NULL; 2920 } 2921} 2922 2923/********************************************************************* 2924 * 2925 * This routine executes in interrupt context. It replenishes 2926 * the mbufs in the descriptor and sends data which has been 2927 * dma'ed into host memory to upper layer. 2928 * 2929 * We loop at most count times if count is > 0, or until done if 2930 * count < 0. 2931 * 2932 *********************************************************************/ 2933static int 2934em_rxeof(struct em_softc *sc, int count) 2935{ 2936 struct ifnet *ifp; 2937 struct mbuf *mp; 2938 uint8_t accept_frame = 0; 2939 uint8_t eop = 0; 2940 uint16_t len, desc_len, prev_len_adj; 2941 int i; 2942 2943 /* Pointer to the receive descriptor being examined. */ 2944 struct em_rx_desc *current_desc; 2945 2946 ifp = sc->ifp; 2947 i = sc->next_rx_desc_to_check; 2948 current_desc = &sc->rx_desc_base[i]; 2949 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2950 BUS_DMASYNC_POSTREAD); 2951 2952 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 2953 return (0); 2954 2955 while ((current_desc->status & E1000_RXD_STAT_DD) && 2956 (count != 0) && 2957 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2958 struct mbuf *m = NULL; 2959 2960 mp = sc->rx_buffer_area[i].m_head; 2961 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 2962 BUS_DMASYNC_POSTREAD); 2963 bus_dmamap_unload(sc->rxtag, 2964 sc->rx_buffer_area[i].map); 2965 2966 accept_frame = 1; 2967 prev_len_adj = 0; 2968 desc_len = le16toh(current_desc->length); 2969 if (current_desc->status & E1000_RXD_STAT_EOP) { 2970 count--; 2971 eop = 1; 2972 if (desc_len < ETHER_CRC_LEN) { 2973 len = 0; 2974 prev_len_adj = ETHER_CRC_LEN - desc_len; 2975 } else 2976 len = desc_len - ETHER_CRC_LEN; 2977 } else { 2978 eop = 0; 2979 len = desc_len; 2980 } 2981 2982 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2983 uint8_t last_byte; 2984 uint32_t pkt_len = desc_len; 2985 2986 if (sc->fmp != NULL) 2987 pkt_len += sc->fmp->m_pkthdr.len; 2988 2989 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 2990 if (TBI_ACCEPT(&sc->hw, current_desc->status, 2991 current_desc->errors, 2992 pkt_len, last_byte)) { 2993 em_tbi_adjust_stats(&sc->hw, 2994 &sc->stats, pkt_len, 2995 sc->hw.mac_addr); 2996 if (len > 0) 2997 len--; 2998 } else 2999 accept_frame = 0; 3000 } 3001 3002 if (accept_frame) { 3003 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3004 sc->dropped_pkts++; 3005 em_get_buf(i, sc, mp); 3006 if (sc->fmp != NULL) 3007 m_freem(sc->fmp); 3008 sc->fmp = NULL; 3009 sc->lmp = NULL; 3010 break; 3011 } 3012 3013 /* Assign correct length to the current fragment */ 3014 mp->m_len = len; 3015 3016 if (sc->fmp == NULL) { 3017 mp->m_pkthdr.len = len; 3018 sc->fmp = mp; /* Store the first mbuf */ 3019 sc->lmp = mp; 3020 } else { 3021 /* Chain mbuf's together */ 3022 mp->m_flags &= ~M_PKTHDR; 3023 /* 3024 * Adjust length of previous mbuf in chain if 3025 * we received less than 4 bytes in the last 3026 * descriptor. 3027 */ 3028 if (prev_len_adj > 0) { 3029 sc->lmp->m_len -= prev_len_adj; 3030 sc->fmp->m_pkthdr.len -= 3031 prev_len_adj; 3032 } 3033 sc->lmp->m_next = mp; 3034 sc->lmp = sc->lmp->m_next; 3035 sc->fmp->m_pkthdr.len += len; 3036 } 3037 3038 if (eop) { 3039 sc->fmp->m_pkthdr.rcvif = ifp; 3040 ifp->if_ipackets++; 3041 em_receive_checksum(sc, current_desc, 3042 sc->fmp); 3043#ifndef __NO_STRICT_ALIGNMENT 3044 if (ifp->if_mtu > ETHERMTU && 3045 em_fixup_rx(sc) != 0) 3046 goto skip; 3047#endif 3048 if (current_desc->status & E1000_RXD_STAT_VP) 3049 VLAN_INPUT_TAG(ifp, sc->fmp, 3050 (le16toh(current_desc->special) & 3051 E1000_RXD_SPC_VLAN_MASK)); 3052#ifndef __NO_STRICT_ALIGNMENT 3053skip: 3054#endif 3055 m = sc->fmp; 3056 sc->fmp = NULL; 3057 sc->lmp = NULL; 3058 } 3059 } else { 3060 sc->dropped_pkts++; 3061 em_get_buf(i, sc, mp); 3062 if (sc->fmp != NULL) 3063 m_freem(sc->fmp); 3064 sc->fmp = NULL; 3065 sc->lmp = NULL; 3066 } 3067 3068 /* Zero out the receive descriptors status. */ 3069 current_desc->status = 0; 3070 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3072 3073 /* Advance our pointers to the next descriptor. */ 3074 if (++i == sc->num_rx_desc) 3075 i = 0; 3076 if (m != NULL) { 3077 sc->next_rx_desc_to_check = i; 3078 (*ifp->if_input)(ifp, m); 3079 i = sc->next_rx_desc_to_check; 3080 } 3081 current_desc = &sc->rx_desc_base[i]; 3082 } 3083 sc->next_rx_desc_to_check = i; 3084 3085 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3086 if (--i < 0) 3087 i = sc->num_rx_desc - 1; 3088 E1000_WRITE_REG(&sc->hw, RDT, i); 3089 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3090 return (0); 3091 3092 return (1); 3093} 3094 3095#ifndef __NO_STRICT_ALIGNMENT 3096/* 3097 * When jumbo frames are enabled we should realign entire payload on 3098 * architecures with strict alignment. This is serious design mistake of 8254x 3099 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3100 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3101 * payload. On architecures without strict alignment restrictions 8254x still 3102 * performs unaligned memory access which would reduce the performance too. 3103 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3104 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3105 * existing mbuf chain. 3106 * 3107 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3108 * not used at all on architectures with strict alignment. 3109 */ 3110static int 3111em_fixup_rx(struct em_softc *sc) 3112{ 3113 struct mbuf *m, *n; 3114 int error; 3115 3116 error = 0; 3117 m = sc->fmp; 3118 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3119 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3120 m->m_data += ETHER_HDR_LEN; 3121 } else { 3122 MGETHDR(n, M_DONTWAIT, MT_DATA); 3123 if (n != NULL) { 3124 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3125 m->m_data += ETHER_HDR_LEN; 3126 m->m_len -= ETHER_HDR_LEN; 3127 n->m_len = ETHER_HDR_LEN; 3128 M_MOVE_PKTHDR(n, m); 3129 n->m_next = m; 3130 sc->fmp = n; 3131 } else { 3132 sc->dropped_pkts++; 3133 m_freem(sc->fmp); 3134 sc->fmp = NULL; 3135 error = ENOMEM; 3136 } 3137 } 3138 3139 return (error); 3140} 3141#endif 3142 3143/********************************************************************* 3144 * 3145 * Verify that the hardware indicated that the checksum is valid. 3146 * Inform the stack about the status of checksum so that stack 3147 * doesn't spend time verifying the checksum. 3148 * 3149 *********************************************************************/ 3150static void 3151em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3152 struct mbuf *mp) 3153{ 3154 /* 82543 or newer only */ 3155 if ((sc->hw.mac_type < em_82543) || 3156 /* Ignore Checksum bit is set */ 3157 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3158 mp->m_pkthdr.csum_flags = 0; 3159 return; 3160 } 3161 3162 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3163 /* Did it pass? */ 3164 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3165 /* IP Checksum Good */ 3166 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3167 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3168 3169 } else { 3170 mp->m_pkthdr.csum_flags = 0; 3171 } 3172 } 3173 3174 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3175 /* Did it pass? */ 3176 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3177 mp->m_pkthdr.csum_flags |= 3178 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3179 mp->m_pkthdr.csum_data = htons(0xffff); 3180 } 3181 } 3182} 3183 3184 3185static void 3186em_enable_vlans(struct em_softc *sc) 3187{ 3188 uint32_t ctrl; 3189 3190 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3191 3192 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3193 ctrl |= E1000_CTRL_VME; 3194 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3195} 3196 3197static void 3198em_disable_vlans(struct em_softc *sc) 3199{ 3200 uint32_t ctrl; 3201 3202 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3203 ctrl &= ~E1000_CTRL_VME; 3204 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3205} 3206 3207static void 3208em_enable_intr(struct em_softc *sc) 3209{ 3210 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3211} 3212 3213static void 3214em_disable_intr(struct em_softc *sc) 3215{ 3216 /* 3217 * The first version of 82542 had an errata where when link was forced 3218 * it would stay up even up even if the cable was disconnected. 3219 * Sequence errors were used to detect the disconnect and then the 3220 * driver would unforce the link. This code in the in the ISR. For this 3221 * to work correctly the Sequence error interrupt had to be enabled 3222 * all the time. 3223 */ 3224 3225 if (sc->hw.mac_type == em_82542_rev2_0) 3226 E1000_WRITE_REG(&sc->hw, IMC, 3227 (0xffffffff & ~E1000_IMC_RXSEQ)); 3228 else 3229 E1000_WRITE_REG(&sc->hw, IMC, 3230 0xffffffff); 3231} 3232 3233static int 3234em_is_valid_ether_addr(uint8_t *addr) 3235{ 3236 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3237 3238 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3239 return (FALSE); 3240 } 3241 3242 return (TRUE); 3243} 3244 3245void 3246em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3247{ 3248 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3249} 3250 3251void 3252em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3253{ 3254 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3255} 3256 3257void 3258em_pci_set_mwi(struct em_hw *hw) 3259{ 3260 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3261 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3262} 3263 3264void 3265em_pci_clear_mwi(struct em_hw *hw) 3266{ 3267 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3268 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3269} 3270 3271/********************************************************************* 3272* 82544 Coexistence issue workaround. 3273* There are 2 issues. 3274* 1. Transmit Hang issue. 3275* To detect this issue, following equation can be used... 3276* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3277* If SUM[3:0] is in between 1 to 4, we will have this issue. 3278* 3279* 2. DAC issue. 3280* To detect this issue, following equation can be used... 3281* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3282* If SUM[3:0] is in between 9 to c, we will have this issue. 3283* 3284* 3285* WORKAROUND: 3286* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3287* 3288*** *********************************************************************/ 3289static uint32_t 3290em_fill_descriptors (bus_addr_t address, uint32_t length, 3291 PDESC_ARRAY desc_array) 3292{ 3293 /* Since issue is sensitive to length and address.*/ 3294 /* Let us first check the address...*/ 3295 uint32_t safe_terminator; 3296 if (length <= 4) { 3297 desc_array->descriptor[0].address = address; 3298 desc_array->descriptor[0].length = length; 3299 desc_array->elements = 1; 3300 return (desc_array->elements); 3301 } 3302 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3303 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3304 if (safe_terminator == 0 || 3305 (safe_terminator > 4 && 3306 safe_terminator < 9) || 3307 (safe_terminator > 0xC && 3308 safe_terminator <= 0xF)) { 3309 desc_array->descriptor[0].address = address; 3310 desc_array->descriptor[0].length = length; 3311 desc_array->elements = 1; 3312 return (desc_array->elements); 3313 } 3314 3315 desc_array->descriptor[0].address = address; 3316 desc_array->descriptor[0].length = length - 4; 3317 desc_array->descriptor[1].address = address + (length - 4); 3318 desc_array->descriptor[1].length = 4; 3319 desc_array->elements = 2; 3320 return (desc_array->elements); 3321} 3322 3323/********************************************************************** 3324 * 3325 * Update the board statistics counters. 3326 * 3327 **********************************************************************/ 3328static void 3329em_update_stats_counters(struct em_softc *sc) 3330{ 3331 struct ifnet *ifp; 3332 3333 if(sc->hw.media_type == em_media_type_copper || 3334 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3335 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3336 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3337 } 3338 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3339 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3340 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3341 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3342 3343 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3344 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3345 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3346 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3347 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3348 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3349 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3350 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3351 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3352 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3353 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3354 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3355 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3356 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3357 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3358 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3359 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3360 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3361 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3362 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3363 3364 /* For the 64-bit byte counters the low dword must be read first. */ 3365 /* Both registers clear on the read of the high dword */ 3366 3367 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3368 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3369 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3370 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3371 3372 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3373 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3374 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3375 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3376 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3377 3378 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3379 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3380 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3381 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3382 3383 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3384 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3385 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3386 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3387 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3388 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3389 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3390 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3391 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3392 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3393 3394 if (sc->hw.mac_type >= em_82543) { 3395 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3396 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3397 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3398 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3399 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3400 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3401 } 3402 ifp = sc->ifp; 3403 3404 ifp->if_collisions = sc->stats.colc; 3405 3406 /* Rx Errors */ 3407 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3408 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3409 sc->stats.mpc + sc->stats.cexterr; 3410 3411 /* Tx Errors */ 3412 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3413 sc->watchdog_events; 3414} 3415 3416 3417/********************************************************************** 3418 * 3419 * This routine is called only when em_display_debug_stats is enabled. 3420 * This routine provides a way to take a look at important statistics 3421 * maintained by the driver and hardware. 3422 * 3423 **********************************************************************/ 3424static void 3425em_print_debug_info(struct em_softc *sc) 3426{ 3427 device_t dev = sc->dev; 3428 uint8_t *hw_addr = sc->hw.hw_addr; 3429 3430 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3431 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3432 E1000_READ_REG(&sc->hw, CTRL), 3433 E1000_READ_REG(&sc->hw, RCTL)); 3434 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3435 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3436 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3437 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3438 sc->hw.fc_high_water, 3439 sc->hw.fc_low_water); 3440 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3441 E1000_READ_REG(&sc->hw, TIDV), 3442 E1000_READ_REG(&sc->hw, TADV)); 3443 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3444 E1000_READ_REG(&sc->hw, RDTR), 3445 E1000_READ_REG(&sc->hw, RADV)); 3446 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3447 (long long)sc->tx_fifo_wrk_cnt, 3448 (long long)sc->tx_fifo_reset_cnt); 3449 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3450 E1000_READ_REG(&sc->hw, TDH), 3451 E1000_READ_REG(&sc->hw, TDT)); 3452 device_printf(dev, "Num Tx descriptors avail = %d\n", 3453 sc->num_tx_desc_avail); 3454 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3455 sc->no_tx_desc_avail1); 3456 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3457 sc->no_tx_desc_avail2); 3458 device_printf(dev, "Std mbuf failed = %ld\n", 3459 sc->mbuf_alloc_failed); 3460 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3461 sc->mbuf_cluster_failed); 3462 device_printf(dev, "Driver dropped packets = %ld\n", 3463 sc->dropped_pkts); 3464} 3465 3466static void 3467em_print_hw_stats(struct em_softc *sc) 3468{ 3469 device_t dev = sc->dev; 3470 3471 device_printf(dev, "Excessive collisions = %lld\n", 3472 (long long)sc->stats.ecol); 3473 device_printf(dev, "Symbol errors = %lld\n", 3474 (long long)sc->stats.symerrs); 3475 device_printf(dev, "Sequence errors = %lld\n", 3476 (long long)sc->stats.sec); 3477 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3478 3479 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3480 device_printf(dev, "Receive No Buffers = %lld\n", 3481 (long long)sc->stats.rnbc); 3482 device_printf(dev, "Receive length errors = %lld\n", 3483 (long long)sc->stats.rlec); 3484 device_printf(dev, "Receive errors = %lld\n", 3485 (long long)sc->stats.rxerrc); 3486 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3487 device_printf(dev, "Alignment errors = %lld\n", 3488 (long long)sc->stats.algnerrc); 3489 device_printf(dev, "Carrier extension errors = %lld\n", 3490 (long long)sc->stats.cexterr); 3491 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3492 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3493 3494 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3495 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3496 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3497 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3498 3499 device_printf(dev, "Good Packets Rcvd = %lld\n", 3500 (long long)sc->stats.gprc); 3501 device_printf(dev, "Good Packets Xmtd = %lld\n", 3502 (long long)sc->stats.gptc); 3503} 3504 3505static int 3506em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3507{ 3508 struct em_softc *sc; 3509 int error; 3510 int result; 3511 3512 result = -1; 3513 error = sysctl_handle_int(oidp, &result, 0, req); 3514 3515 if (error || !req->newptr) 3516 return (error); 3517 3518 if (result == 1) { 3519 sc = (struct em_softc *)arg1; 3520 em_print_debug_info(sc); 3521 } 3522 3523 return (error); 3524} 3525 3526 3527static int 3528em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3529{ 3530 struct em_softc *sc; 3531 int error; 3532 int result; 3533 3534 result = -1; 3535 error = sysctl_handle_int(oidp, &result, 0, req); 3536 3537 if (error || !req->newptr) 3538 return (error); 3539 3540 if (result == 1) { 3541 sc = (struct em_softc *)arg1; 3542 em_print_hw_stats(sc); 3543 } 3544 3545 return (error); 3546} 3547 3548static int 3549em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3550{ 3551 struct em_int_delay_info *info; 3552 struct em_softc *sc; 3553 uint32_t regval; 3554 int error; 3555 int usecs; 3556 int ticks; 3557 3558 info = (struct em_int_delay_info *)arg1; 3559 usecs = info->value; 3560 error = sysctl_handle_int(oidp, &usecs, 0, req); 3561 if (error != 0 || req->newptr == NULL) 3562 return (error); 3563 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3564 return (EINVAL); 3565 info->value = usecs; 3566 ticks = E1000_USECS_TO_TICKS(usecs); 3567 3568 sc = info->sc; 3569 3570 EM_LOCK(sc); 3571 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3572 regval = (regval & ~0xffff) | (ticks & 0xffff); 3573 /* Handle a few special cases. */ 3574 switch (info->offset) { 3575 case E1000_RDTR: 3576 case E1000_82542_RDTR: 3577 regval |= E1000_RDT_FPDB; 3578 break; 3579 case E1000_TIDV: 3580 case E1000_82542_TIDV: 3581 if (ticks == 0) { 3582 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3583 /* Don't write 0 into the TIDV register. */ 3584 regval++; 3585 } else 3586 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3587 break; 3588 } 3589 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3590 EM_UNLOCK(sc); 3591 return (0); 3592} 3593 3594static void 3595em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3596 const char *description, struct em_int_delay_info *info, 3597 int offset, int value) 3598{ 3599 info->sc = sc; 3600 info->offset = offset; 3601 info->value = value; 3602 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3603 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3604 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3605 info, 0, em_sysctl_int_delay, "I", description); 3606} 3607 3608#ifndef NO_EM_FASTINTR 3609static void 3610em_add_int_process_limit(struct em_softc *sc, const char *name, 3611 const char *description, int *limit, int value) 3612{ 3613 *limit = value; 3614 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3615 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3616 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3617} 3618#endif 3619