if_em.c revision 155709
1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.c 155709 2006-02-15 08:39:50Z glebius $*/ 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/kthread.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/taskqueue.h> 54 55#include <machine/bus.h> 56#include <machine/resource.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64 65#include <net/if_types.h> 66#include <net/if_vlan_var.h> 67 68#include <netinet/in_systm.h> 69#include <netinet/in.h> 70#include <netinet/ip.h> 71#include <netinet/tcp.h> 72#include <netinet/udp.h> 73 74#include <dev/pci/pcivar.h> 75#include <dev/pci/pcireg.h> 76#include <dev/em/if_em_hw.h> 77#include <dev/em/if_em.h> 78 79/********************************************************************* 80 * Set this to one to display debug statistics 81 *********************************************************************/ 82int em_display_debug_stats = 0; 83 84/********************************************************************* 85 * Driver version 86 *********************************************************************/ 87 88char em_driver_version[] = "Version - 3.2.18"; 89 90 91/********************************************************************* 92 * PCI Device ID Table 93 * 94 * Used by probe to select devices to load on 95 * Last field stores an index into em_strings 96 * Last entry must be all 0s 97 * 98 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 99 *********************************************************************/ 100 101static em_vendor_info_t em_vendor_info_array[] = 102{ 103 /* Intel(R) PRO/1000 Network Connection */ 104 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 105 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 106 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 110 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 123 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 143 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 147 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 151 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 155 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 /* required last entry */ 160 { 0, 0, 0, 0, 0} 161}; 162 163/********************************************************************* 164 * Table of branding strings for all supported NICs. 165 *********************************************************************/ 166 167static char *em_strings[] = { 168 "Intel(R) PRO/1000 Network Connection" 169}; 170 171/********************************************************************* 172 * Function prototypes 173 *********************************************************************/ 174static int em_probe(device_t); 175static int em_attach(device_t); 176static int em_detach(device_t); 177static int em_shutdown(device_t); 178static int em_suspend(device_t); 179static int em_resume(device_t); 180static void em_intr(void *); 181#ifndef NO_EM_FASTINTR 182static void em_intr_fast(void *); 183#endif 184static void em_start(struct ifnet *); 185static void em_start_locked(struct ifnet *ifp); 186static int em_ioctl(struct ifnet *, u_long, caddr_t); 187static void em_watchdog(struct ifnet *); 188static void em_init(void *); 189static void em_init_locked(struct em_softc *); 190static void em_stop(void *); 191static void em_media_status(struct ifnet *, struct ifmediareq *); 192static int em_media_change(struct ifnet *); 193static void em_identify_hardware(struct em_softc *); 194static int em_allocate_pci_resources(struct em_softc *); 195static int em_allocate_intr(struct em_softc *); 196static void em_free_intr(struct em_softc *); 197static void em_free_pci_resources(struct em_softc *); 198static void em_local_timer(void *); 199static int em_hardware_init(struct em_softc *); 200static void em_setup_interface(device_t, struct em_softc *); 201static int em_setup_transmit_structures(struct em_softc *); 202static void em_initialize_transmit_unit(struct em_softc *); 203static int em_setup_receive_structures(struct em_softc *); 204static void em_initialize_receive_unit(struct em_softc *); 205static void em_enable_intr(struct em_softc *); 206static void em_disable_intr(struct em_softc *); 207static void em_free_transmit_structures(struct em_softc *); 208static void em_free_receive_structures(struct em_softc *); 209static void em_update_stats_counters(struct em_softc *); 210static void em_txeof(struct em_softc *); 211static int em_allocate_receive_structures(struct em_softc *); 212static int em_allocate_transmit_structures(struct em_softc *); 213static int em_rxeof(struct em_softc *, int); 214#ifndef __NO_STRICT_ALIGNMENT 215static int em_fixup_rx(struct em_softc *); 216#endif 217static void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 218 struct mbuf *); 219static void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 220 uint32_t *, uint32_t *); 221static void em_set_promisc(struct em_softc *); 222static void em_disable_promisc(struct em_softc *); 223static void em_set_multi(struct em_softc *); 224static void em_print_hw_stats(struct em_softc *); 225static void em_print_link_status(struct em_softc *); 226static int em_get_buf(int i, struct em_softc *, struct mbuf *); 227static void em_enable_vlans(struct em_softc *); 228static void em_disable_vlans(struct em_softc *); 229static int em_encap(struct em_softc *, struct mbuf **); 230static void em_smartspeed(struct em_softc *); 231static int em_82547_fifo_workaround(struct em_softc *, int); 232static void em_82547_update_fifo_head(struct em_softc *, int); 233static int em_82547_tx_fifo_reset(struct em_softc *); 234static void em_82547_move_tail(void *arg); 235static void em_82547_move_tail_locked(struct em_softc *); 236static int em_dma_malloc(struct em_softc *, bus_size_t, 237 struct em_dma_alloc *, int); 238static void em_dma_free(struct em_softc *, struct em_dma_alloc *); 239static void em_print_debug_info(struct em_softc *); 240static int em_is_valid_ether_addr(uint8_t *); 241static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 242static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 243static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 244 PDESC_ARRAY desc_array); 245static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 246static void em_add_int_delay_sysctl(struct em_softc *, const char *, 247 const char *, struct em_int_delay_info *, int, int); 248#ifndef NO_EM_FASTINTR 249static void em_add_int_process_limit(struct em_softc *, const char *, 250 const char *, int *, int); 251static void em_handle_rxtx(void *context, int pending); 252static void em_handle_link(void *context, int pending); 253#endif 254#ifdef DEVICE_POLLING 255static poll_handler_t em_poll; 256#endif 257 258/********************************************************************* 259 * FreeBSD Device Interface Entry Points 260 *********************************************************************/ 261 262static device_method_t em_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, em_probe), 265 DEVMETHOD(device_attach, em_attach), 266 DEVMETHOD(device_detach, em_detach), 267 DEVMETHOD(device_shutdown, em_shutdown), 268 DEVMETHOD(device_suspend, em_suspend), 269 DEVMETHOD(device_resume, em_resume), 270 {0, 0} 271}; 272 273static driver_t em_driver = { 274 "em", em_methods, sizeof(struct em_softc), 275}; 276 277static devclass_t em_devclass; 278DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 279MODULE_DEPEND(em, pci, 1, 1, 1); 280MODULE_DEPEND(em, ether, 1, 1, 1); 281 282/********************************************************************* 283 * Tunable default values. 284 *********************************************************************/ 285 286#define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 287#define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 288 289static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 290static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 291static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 292static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 293static int em_rxd = EM_DEFAULT_RXD; 294static int em_txd = EM_DEFAULT_TXD; 295 296TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 297TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 298TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 299TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 300TUNABLE_INT("hw.em.rxd", &em_rxd); 301TUNABLE_INT("hw.em.txd", &em_txd); 302#ifndef NO_EM_FASTINTR 303static int em_rx_process_limit = 100; 304TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 305#endif 306 307/********************************************************************* 308 * Device identification routine 309 * 310 * em_probe determines if the driver should be loaded on 311 * adapter based on PCI vendor/device id of the adapter. 312 * 313 * return BUS_PROBE_DEFAULT on success, positive on failure 314 *********************************************************************/ 315 316static int 317em_probe(device_t dev) 318{ 319 char adapter_name[60]; 320 uint16_t pci_vendor_id = 0; 321 uint16_t pci_device_id = 0; 322 uint16_t pci_subvendor_id = 0; 323 uint16_t pci_subdevice_id = 0; 324 em_vendor_info_t *ent; 325 326 INIT_DEBUGOUT("em_probe: begin"); 327 328 pci_vendor_id = pci_get_vendor(dev); 329 if (pci_vendor_id != EM_VENDOR_ID) 330 return (ENXIO); 331 332 pci_device_id = pci_get_device(dev); 333 pci_subvendor_id = pci_get_subvendor(dev); 334 pci_subdevice_id = pci_get_subdevice(dev); 335 336 ent = em_vendor_info_array; 337 while (ent->vendor_id != 0) { 338 if ((pci_vendor_id == ent->vendor_id) && 339 (pci_device_id == ent->device_id) && 340 341 ((pci_subvendor_id == ent->subvendor_id) || 342 (ent->subvendor_id == PCI_ANY_ID)) && 343 344 ((pci_subdevice_id == ent->subdevice_id) || 345 (ent->subdevice_id == PCI_ANY_ID))) { 346 sprintf(adapter_name, "%s %s", 347 em_strings[ent->index], 348 em_driver_version); 349 device_set_desc_copy(dev, adapter_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 ent++; 353 } 354 355 return (ENXIO); 356} 357 358/********************************************************************* 359 * Device initialization routine 360 * 361 * The attach entry point is called when the driver is being loaded. 362 * This routine identifies the type of hardware, allocates all resources 363 * and initializes the hardware. 364 * 365 * return 0 on success, positive on failure 366 *********************************************************************/ 367 368static int 369em_attach(device_t dev) 370{ 371 struct em_softc *sc; 372 int tsize, rsize; 373 int error = 0; 374 375 INIT_DEBUGOUT("em_attach: begin"); 376 377 sc = device_get_softc(dev); 378 sc->dev = sc->osdep.dev = dev; 379 EM_LOCK_INIT(sc, device_get_nameunit(dev)); 380 381 /* SYSCTL stuff */ 382 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 383 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 384 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 385 em_sysctl_debug_info, "I", "Debug Information"); 386 387 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 388 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 389 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 390 em_sysctl_stats, "I", "Statistics"); 391 392 callout_init(&sc->timer, CALLOUT_MPSAFE); 393 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE); 394 395 /* Determine hardware revision */ 396 em_identify_hardware(sc); 397 398 /* Set up some sysctls for the tunable interrupt delays */ 399 em_add_int_delay_sysctl(sc, "rx_int_delay", 400 "receive interrupt delay in usecs", &sc->rx_int_delay, 401 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt); 402 em_add_int_delay_sysctl(sc, "tx_int_delay", 403 "transmit interrupt delay in usecs", &sc->tx_int_delay, 404 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt); 405 if (sc->hw.mac_type >= em_82540) { 406 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 407 "receive interrupt delay limit in usecs", 408 &sc->rx_abs_int_delay, 409 E1000_REG_OFFSET(&sc->hw, RADV), 410 em_rx_abs_int_delay_dflt); 411 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 412 "transmit interrupt delay limit in usecs", 413 &sc->tx_abs_int_delay, 414 E1000_REG_OFFSET(&sc->hw, TADV), 415 em_tx_abs_int_delay_dflt); 416 } 417 418 /* Sysctls for limiting the amount of work done in the taskqueue */ 419#ifndef NO_EM_FASTINTR 420 em_add_int_process_limit(sc, "rx_processing_limit", 421 "max number of rx packets to process", &sc->rx_process_limit, 422 em_rx_process_limit); 423#endif 424 425 /* 426 * Validate number of transmit and receive descriptors. It 427 * must not exceed hardware maximum, and must be multiple 428 * of E1000_DBA_ALIGN. 429 */ 430 if (((em_txd * sizeof(struct em_tx_desc)) % E1000_DBA_ALIGN) != 0 || 431 (sc->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 432 (sc->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 433 (em_txd < EM_MIN_TXD)) { 434 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 435 EM_DEFAULT_TXD, em_txd); 436 sc->num_tx_desc = EM_DEFAULT_TXD; 437 } else 438 sc->num_tx_desc = em_txd; 439 if (((em_rxd * sizeof(struct em_rx_desc)) % E1000_DBA_ALIGN) != 0 || 440 (sc->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 441 (sc->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 442 (em_rxd < EM_MIN_RXD)) { 443 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 444 EM_DEFAULT_RXD, em_rxd); 445 sc->num_rx_desc = EM_DEFAULT_RXD; 446 } else 447 sc->num_rx_desc = em_rxd; 448 449 sc->hw.autoneg = DO_AUTO_NEG; 450 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 451 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 452 sc->hw.tbi_compatibility_en = TRUE; 453 sc->rx_buffer_len = EM_RXBUFFER_2048; 454 455 sc->hw.phy_init_script = 1; 456 sc->hw.phy_reset_disable = FALSE; 457 458#ifndef EM_MASTER_SLAVE 459 sc->hw.master_slave = em_ms_hw_default; 460#else 461 sc->hw.master_slave = EM_MASTER_SLAVE; 462#endif 463 /* 464 * Set the max frame size assuming standard ethernet 465 * sized frames. 466 */ 467 sc->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 468 469 sc->hw.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 470 471 /* 472 * This controls when hardware reports transmit completion 473 * status. 474 */ 475 sc->hw.report_tx_early = 1; 476 if (em_allocate_pci_resources(sc)) { 477 device_printf(dev, "Allocation of PCI resources failed\n"); 478 error = ENXIO; 479 goto err_pci; 480 } 481 482 /* Initialize eeprom parameters */ 483 em_init_eeprom_params(&sc->hw); 484 485 tsize = roundup2(sc->num_tx_desc * sizeof(struct em_tx_desc), 486 E1000_DBA_ALIGN); 487 488 /* Allocate Transmit Descriptor ring */ 489 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 490 device_printf(dev, "Unable to allocate tx_desc memory\n"); 491 error = ENOMEM; 492 goto err_tx_desc; 493 } 494 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 495 496 rsize = roundup2(sc->num_rx_desc * sizeof(struct em_rx_desc), 497 E1000_DBA_ALIGN); 498 499 /* Allocate Receive Descriptor ring */ 500 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 501 device_printf(dev, "Unable to allocate rx_desc memory\n"); 502 error = ENOMEM; 503 goto err_rx_desc; 504 } 505 sc->rx_desc_base = (struct em_rx_desc *)sc->rxdma.dma_vaddr; 506 507 /* Initialize the hardware */ 508 if (em_hardware_init(sc)) { 509 device_printf(dev, "Unable to initialize the hardware\n"); 510 error = EIO; 511 goto err_hw_init; 512 } 513 514 /* Copy the permanent MAC address out of the EEPROM */ 515 if (em_read_mac_addr(&sc->hw) < 0) { 516 device_printf(dev, "EEPROM read error while reading MAC" 517 " address\n"); 518 error = EIO; 519 goto err_hw_init; 520 } 521 522 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 523 device_printf(dev, "Invalid MAC address\n"); 524 error = EIO; 525 goto err_hw_init; 526 } 527 528 /* Setup OS specific network interface */ 529 em_setup_interface(dev, sc); 530 531 em_allocate_intr(sc); 532 533 /* Initialize statistics */ 534 em_clear_hw_cntrs(&sc->hw); 535 em_update_stats_counters(sc); 536 sc->hw.get_link_status = 1; 537 em_check_for_link(&sc->hw); 538 539 if (bootverbose) { 540 /* Print the link status */ 541 if (sc->link_active == 1) { 542 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 543 &sc->link_duplex); 544 device_printf(dev, "Speed:%d Mbps Duplex:%s\n", 545 sc->link_speed, sc->link_duplex == FULL_DUPLEX ? 546 "Full" : "Half"); 547 } else 548 device_printf(dev, "Speed:N/A Duplex:N/A\n"); 549 } 550 551 /* Identify 82544 on PCIX */ 552 em_get_bus_info(&sc->hw); 553 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544) 554 sc->pcix_82544 = TRUE; 555 else 556 sc->pcix_82544 = FALSE; 557 558 INIT_DEBUGOUT("em_attach: end"); 559 560 return (0); 561 562err_hw_init: 563 em_dma_free(sc, &sc->rxdma); 564err_rx_desc: 565 em_dma_free(sc, &sc->txdma); 566err_tx_desc: 567err_pci: 568 em_free_intr(sc); 569 em_free_pci_resources(sc); 570 EM_LOCK_DESTROY(sc); 571 572 return (error); 573} 574 575/********************************************************************* 576 * Device removal routine 577 * 578 * The detach entry point is called when the driver is being removed. 579 * This routine stops the adapter and deallocates all the resources 580 * that were allocated for driver operation. 581 * 582 * return 0 on success, positive on failure 583 *********************************************************************/ 584 585static int 586em_detach(device_t dev) 587{ 588 struct em_softc *sc = device_get_softc(dev); 589 struct ifnet *ifp = sc->ifp; 590 591 INIT_DEBUGOUT("em_detach: begin"); 592 593#ifdef DEVICE_POLLING 594 if (ifp->if_capenable & IFCAP_POLLING) 595 ether_poll_deregister(ifp); 596#endif 597 598 em_free_intr(sc); 599 EM_LOCK(sc); 600 sc->in_detach = 1; 601 em_stop(sc); 602 em_phy_hw_reset(&sc->hw); 603 EM_UNLOCK(sc); 604 ether_ifdetach(sc->ifp); 605 606 em_free_pci_resources(sc); 607 bus_generic_detach(dev); 608 if_free(ifp); 609 610 /* Free Transmit Descriptor ring */ 611 if (sc->tx_desc_base) { 612 em_dma_free(sc, &sc->txdma); 613 sc->tx_desc_base = NULL; 614 } 615 616 /* Free Receive Descriptor ring */ 617 if (sc->rx_desc_base) { 618 em_dma_free(sc, &sc->rxdma); 619 sc->rx_desc_base = NULL; 620 } 621 622 EM_LOCK_DESTROY(sc); 623 624 return (0); 625} 626 627/********************************************************************* 628 * 629 * Shutdown entry point 630 * 631 **********************************************************************/ 632 633static int 634em_shutdown(device_t dev) 635{ 636 struct em_softc *sc = device_get_softc(dev); 637 EM_LOCK(sc); 638 em_stop(sc); 639 EM_UNLOCK(sc); 640 return (0); 641} 642 643/* 644 * Suspend/resume device methods. 645 */ 646static int 647em_suspend(device_t dev) 648{ 649 struct em_softc *sc = device_get_softc(dev); 650 651 EM_LOCK(sc); 652 em_stop(sc); 653 EM_UNLOCK(sc); 654 655 return bus_generic_suspend(dev); 656} 657 658static int 659em_resume(device_t dev) 660{ 661 struct em_softc *sc = device_get_softc(dev); 662 struct ifnet *ifp = sc->ifp; 663 664 EM_LOCK(sc); 665 em_init_locked(sc); 666 if ((ifp->if_flags & IFF_UP) && 667 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 668 em_start_locked(ifp); 669 EM_UNLOCK(sc); 670 671 return bus_generic_resume(dev); 672} 673 674 675/********************************************************************* 676 * Transmit entry point 677 * 678 * em_start is called by the stack to initiate a transmit. 679 * The driver will remain in this routine as long as there are 680 * packets to transmit and transmit resources are available. 681 * In case resources are not available stack is notified and 682 * the packet is requeued. 683 **********************************************************************/ 684 685static void 686em_start_locked(struct ifnet *ifp) 687{ 688 struct em_softc *sc = ifp->if_softc; 689 struct mbuf *m_head; 690 691 EM_LOCK_ASSERT(sc); 692 693 if (!sc->link_active) 694 return; 695 696 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 697 698 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 699 if (m_head == NULL) 700 break; 701 /* 702 * em_encap() can modify our pointer, and or make it NULL on 703 * failure. In that event, we can't requeue. 704 */ 705 if (em_encap(sc, &m_head)) { 706 if (m_head == NULL) 707 break; 708 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 709 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 710 break; 711 } 712 713 /* Send a copy of the frame to the BPF listener */ 714 BPF_MTAP(ifp, m_head); 715 716 /* Set timeout in case hardware has problems transmitting. */ 717 ifp->if_timer = EM_TX_TIMEOUT; 718 } 719} 720 721static void 722em_start(struct ifnet *ifp) 723{ 724 struct em_softc *sc = ifp->if_softc; 725 726 EM_LOCK(sc); 727 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 728 em_start_locked(ifp); 729 EM_UNLOCK(sc); 730} 731 732/********************************************************************* 733 * Ioctl entry point 734 * 735 * em_ioctl is called when the user wants to configure the 736 * interface. 737 * 738 * return 0 on success, positive on failure 739 **********************************************************************/ 740 741static int 742em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 743{ 744 struct em_softc *sc = ifp->if_softc; 745 struct ifreq *ifr = (struct ifreq *)data; 746 int error = 0; 747 748 if (sc->in_detach) 749 return (error); 750 751 switch (command) { 752 case SIOCSIFADDR: 753 case SIOCGIFADDR: 754 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)"); 755 ether_ioctl(ifp, command, data); 756 break; 757 case SIOCSIFMTU: 758 { 759 int max_frame_size; 760 761 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 762 763 switch (sc->hw.mac_type) { 764 case em_82571: 765 case em_82572: 766 max_frame_size = 10500; 767 break; 768 case em_82573: 769 /* 82573 does not support jumbo frames. */ 770 max_frame_size = ETHER_MAX_LEN; 771 break; 772 default: 773 max_frame_size = MAX_JUMBO_FRAME_SIZE; 774 } 775 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 776 ETHER_CRC_LEN) { 777 error = EINVAL; 778 break; 779 } 780 781 EM_LOCK(sc); 782 ifp->if_mtu = ifr->ifr_mtu; 783 sc->hw.max_frame_size = 784 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 785 em_init_locked(sc); 786 EM_UNLOCK(sc); 787 break; 788 } 789 case SIOCSIFFLAGS: 790 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 791 EM_LOCK(sc); 792 if (ifp->if_flags & IFF_UP) { 793 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 794 em_init_locked(sc); 795 } 796 797 em_disable_promisc(sc); 798 em_set_promisc(sc); 799 } else { 800 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 801 em_stop(sc); 802 } 803 } 804 EM_UNLOCK(sc); 805 break; 806 case SIOCADDMULTI: 807 case SIOCDELMULTI: 808 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 809 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 810 EM_LOCK(sc); 811 em_disable_intr(sc); 812 em_set_multi(sc); 813 if (sc->hw.mac_type == em_82542_rev2_0) { 814 em_initialize_receive_unit(sc); 815 } 816#ifdef DEVICE_POLLING 817 if (!(ifp->if_capenable & IFCAP_POLLING)) 818#endif 819 em_enable_intr(sc); 820 EM_UNLOCK(sc); 821 } 822 break; 823 case SIOCSIFMEDIA: 824 case SIOCGIFMEDIA: 825 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 826 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 827 break; 828 case SIOCSIFCAP: 829 { 830 int mask, reinit; 831 832 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 833 reinit = 0; 834 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 835#ifdef DEVICE_POLLING 836 if (mask & IFCAP_POLLING) { 837 if (ifr->ifr_reqcap & IFCAP_POLLING) { 838 error = ether_poll_register(em_poll, ifp); 839 if (error) 840 return (error); 841 EM_LOCK(sc); 842 em_disable_intr(sc); 843 ifp->if_capenable |= IFCAP_POLLING; 844 EM_UNLOCK(sc); 845 } else { 846 error = ether_poll_deregister(ifp); 847 /* Enable interrupt even in error case */ 848 EM_LOCK(sc); 849 em_enable_intr(sc); 850 ifp->if_capenable &= ~IFCAP_POLLING; 851 EM_UNLOCK(sc); 852 } 853 } 854#endif 855 if (mask & IFCAP_HWCSUM) { 856 ifp->if_capenable ^= IFCAP_HWCSUM; 857 reinit = 1; 858 } 859 if (mask & IFCAP_VLAN_HWTAGGING) { 860 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 861 reinit = 1; 862 } 863 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 864 em_init(sc); 865 VLAN_CAPABILITIES(ifp); 866 break; 867 } 868 default: 869 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command); 870 error = EINVAL; 871 } 872 873 return (error); 874} 875 876/********************************************************************* 877 * Watchdog entry point 878 * 879 * This routine is called whenever hardware quits transmitting. 880 * 881 **********************************************************************/ 882 883static void 884em_watchdog(struct ifnet *ifp) 885{ 886 struct em_softc *sc = ifp->if_softc; 887 888 EM_LOCK(sc); 889 /* If we are in this routine because of pause frames, then 890 * don't reset the hardware. 891 */ 892 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 893 ifp->if_timer = EM_TX_TIMEOUT; 894 EM_UNLOCK(sc); 895 return; 896 } 897 898 if (em_check_for_link(&sc->hw) == 0) 899 device_printf(sc->dev, "watchdog timeout -- resetting\n"); 900 901 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 902 sc->watchdog_events++; 903 904 em_init_locked(sc); 905 EM_UNLOCK(sc); 906} 907 908/********************************************************************* 909 * Init entry point 910 * 911 * This routine is used in two ways. It is used by the stack as 912 * init entry point in network interface structure. It is also used 913 * by the driver as a hw/sw initialization routine to get to a 914 * consistent state. 915 * 916 * return 0 on success, positive on failure 917 **********************************************************************/ 918 919static void 920em_init_locked(struct em_softc *sc) 921{ 922 struct ifnet *ifp = sc->ifp; 923 device_t dev = sc->dev; 924 uint32_t pba; 925 926 INIT_DEBUGOUT("em_init: begin"); 927 928 EM_LOCK_ASSERT(sc); 929 930 em_stop(sc); 931 932 /* 933 * Packet Buffer Allocation (PBA) 934 * Writing PBA sets the receive portion of the buffer 935 * the remainder is used for the transmit buffer. 936 */ 937 switch (sc->hw.mac_type) { 938 case em_82547: 939 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 940 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 941 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 942 else 943 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 944 sc->tx_fifo_head = 0; 945 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 946 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 947 break; 948 case em_82571: /* 82571: Total Packet Buffer is 48K */ 949 case em_82572: /* 82572: Total Packet Buffer is 48K */ 950 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 951 break; 952 case em_82573: /* 82573: Total Packet Buffer is 32K */ 953 /* Jumbo frames not supported */ 954 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 955 break; 956 default: 957 /* Devices before 82547 had a Packet Buffer of 64K. */ 958 if(sc->hw.max_frame_size > EM_RXBUFFER_8192) 959 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 960 else 961 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 962 } 963 964 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 965 E1000_WRITE_REG(&sc->hw, PBA, pba); 966 967 /* Get the latest mac address, User can use a LAA */ 968 bcopy(IF_LLADDR(sc->ifp), sc->hw.mac_addr, ETHER_ADDR_LEN); 969 970 /* Initialize the hardware */ 971 if (em_hardware_init(sc)) { 972 device_printf(dev, "Unable to initialize the hardware\n"); 973 return; 974 } 975 976 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 977 em_enable_vlans(sc); 978 979 /* Prepare transmit descriptors and buffers */ 980 if (em_setup_transmit_structures(sc)) { 981 device_printf(dev, "Could not setup transmit structures\n"); 982 em_stop(sc); 983 return; 984 } 985 em_initialize_transmit_unit(sc); 986 987 /* Setup Multicast table */ 988 em_set_multi(sc); 989 990 /* Prepare receive descriptors and buffers */ 991 if (em_setup_receive_structures(sc)) { 992 device_printf(dev, "Could not setup receive structures\n"); 993 em_stop(sc); 994 return; 995 } 996 em_initialize_receive_unit(sc); 997 998 /* Don't loose promiscuous settings */ 999 em_set_promisc(sc); 1000 1001 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1002 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1003 1004 if (sc->hw.mac_type >= em_82543) { 1005 if (ifp->if_capenable & IFCAP_TXCSUM) 1006 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1007 else 1008 ifp->if_hwassist = 0; 1009 } 1010 1011 callout_reset(&sc->timer, hz, em_local_timer, sc); 1012 em_clear_hw_cntrs(&sc->hw); 1013#ifdef DEVICE_POLLING 1014 /* 1015 * Only enable interrupts if we are not polling, make sure 1016 * they are off otherwise. 1017 */ 1018 if (ifp->if_capenable & IFCAP_POLLING) 1019 em_disable_intr(sc); 1020 else 1021#endif /* DEVICE_POLLING */ 1022 em_enable_intr(sc); 1023 1024 /* Don't reset the phy next time init gets called */ 1025 sc->hw.phy_reset_disable = TRUE; 1026} 1027 1028static void 1029em_init(void *arg) 1030{ 1031 struct em_softc *sc = arg; 1032 1033 EM_LOCK(sc); 1034 em_init_locked(sc); 1035 EM_UNLOCK(sc); 1036} 1037 1038 1039#ifdef DEVICE_POLLING 1040static void 1041em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1042{ 1043 struct em_softc *sc = ifp->if_softc; 1044 uint32_t reg_icr; 1045 1046 EM_LOCK_ASSERT(sc); 1047 1048 if (cmd == POLL_AND_CHECK_STATUS) { 1049 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1050 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1051 callout_stop(&sc->timer); 1052 sc->hw.get_link_status = 1; 1053 em_check_for_link(&sc->hw); 1054 em_print_link_status(sc); 1055 callout_reset(&sc->timer, hz, em_local_timer, sc); 1056 } 1057 } 1058 em_rxeof(sc, count); 1059 em_txeof(sc); 1060 1061 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1062 em_start_locked(ifp); 1063} 1064 1065static void 1066em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1067{ 1068 struct em_softc *sc = ifp->if_softc; 1069 1070 EM_LOCK(sc); 1071 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1072 em_poll_locked(ifp, cmd, count); 1073 EM_UNLOCK(sc); 1074} 1075#endif /* DEVICE_POLLING */ 1076 1077#ifndef NO_EM_FASTINTR 1078static void 1079em_handle_link(void *context, int pending) 1080{ 1081 struct em_softc *sc = context; 1082 struct ifnet *ifp; 1083 1084 ifp = sc->ifp; 1085 1086 EM_LOCK(sc); 1087 1088 callout_stop(&sc->timer); 1089 sc->hw.get_link_status = 1; 1090 em_check_for_link(&sc->hw); 1091 em_print_link_status(sc); 1092 callout_reset(&sc->timer, hz, em_local_timer, sc); 1093 EM_UNLOCK(sc); 1094} 1095 1096static void 1097em_handle_rxtx(void *context, int pending) 1098{ 1099 struct em_softc *sc = context; 1100 struct ifnet *ifp; 1101 1102 NET_LOCK_GIANT(); 1103 ifp = sc->ifp; 1104 1105 /* 1106 * TODO: 1107 * It should be possible to run the tx clean loop without the lock. 1108 */ 1109 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1110 if (em_rxeof(sc, sc->rx_process_limit) != 0) 1111 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1112 EM_LOCK(sc); 1113 em_txeof(sc); 1114 1115 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1116 em_start_locked(ifp); 1117 EM_UNLOCK(sc); 1118 } 1119 1120 em_enable_intr(sc); 1121 NET_UNLOCK_GIANT(); 1122} 1123#endif 1124 1125/********************************************************************* 1126 * 1127 * Interrupt Service routine 1128 * 1129 **********************************************************************/ 1130#ifndef NO_EM_FASTINTR 1131static void 1132em_intr_fast(void *arg) 1133{ 1134 struct em_softc *sc = arg; 1135 struct ifnet *ifp; 1136 uint32_t reg_icr; 1137 1138 ifp = sc->ifp; 1139 1140#ifdef DEVICE_POLLING 1141 if (ifp->if_capenable & IFCAP_POLLING) 1142 return; 1143#endif /* DEVICE_POLLING */ 1144 1145 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1146 1147 /* Hot eject? */ 1148 if (reg_icr == 0xffffffff) 1149 return; 1150 1151 /* Definitely not our interrupt. */ 1152 if (reg_icr == 0x0) 1153 return; 1154 1155 /* 1156 * Starting with the 82571 chip, bit 31 should be used to 1157 * determine whether the interrupt belongs to us. 1158 */ 1159 if (sc->hw.mac_type >= em_82571 && 1160 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1161 return; 1162 1163 /* 1164 * Mask interrupts until the taskqueue is finished running. This is 1165 * cheap, just assume that it is needed. This also works around the 1166 * MSI message reordering errata on certain systems. 1167 */ 1168 em_disable_intr(sc); 1169 taskqueue_enqueue(sc->tq, &sc->rxtx_task); 1170 1171 /* Link status change */ 1172 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1173 taskqueue_enqueue(taskqueue_fast, &sc->link_task); 1174 1175 if (reg_icr & E1000_ICR_RXO) 1176 sc->rx_overruns++; 1177} 1178#endif 1179 1180static void 1181em_intr(void *arg) 1182{ 1183 struct em_softc *sc = arg; 1184 struct ifnet *ifp; 1185 uint32_t reg_icr; 1186 int wantinit = 0; 1187 1188 EM_LOCK(sc); 1189 1190 ifp = sc->ifp; 1191 1192#ifdef DEVICE_POLLING 1193 if (ifp->if_capenable & IFCAP_POLLING) { 1194 EM_UNLOCK(sc); 1195 return; 1196 } 1197#endif 1198 1199 for (;;) { 1200 reg_icr = E1000_READ_REG(&sc->hw, ICR); 1201 if (sc->hw.mac_type >= em_82571 && 1202 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1203 break; 1204 else if (reg_icr == 0) 1205 break; 1206 1207 /* 1208 * XXX: some laptops trigger several spurious interrupts 1209 * on em(4) when in the resume cycle. The ICR register 1210 * reports all-ones value in this case. Processing such 1211 * interrupts would lead to a freeze. I don't know why. 1212 */ 1213 if (reg_icr == 0xffffffff) 1214 break; 1215 1216 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1217 em_rxeof(sc, -1); 1218 em_txeof(sc); 1219 } 1220 1221 /* Link status change */ 1222 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1223 callout_stop(&sc->timer); 1224 sc->hw.get_link_status = 1; 1225 em_check_for_link(&sc->hw); 1226 em_print_link_status(sc); 1227 callout_reset(&sc->timer, hz, em_local_timer, sc); 1228 } 1229 1230 if (reg_icr & E1000_ICR_RXO) { 1231 sc->rx_overruns++; 1232 wantinit = 1; 1233 } 1234 } 1235#if 0 1236 if (wantinit) 1237 em_init_locked(sc); 1238#endif 1239 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1240 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1241 em_start_locked(ifp); 1242 1243 EM_UNLOCK(sc); 1244} 1245 1246/********************************************************************* 1247 * 1248 * Media Ioctl callback 1249 * 1250 * This routine is called whenever the user queries the status of 1251 * the interface using ifconfig. 1252 * 1253 **********************************************************************/ 1254static void 1255em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1256{ 1257 struct em_softc *sc = ifp->if_softc; 1258 1259 INIT_DEBUGOUT("em_media_status: begin"); 1260 1261 em_check_for_link(&sc->hw); 1262 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1263 if (sc->link_active == 0) { 1264 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1265 &sc->link_duplex); 1266 sc->link_active = 1; 1267 } 1268 } else { 1269 if (sc->link_active == 1) { 1270 sc->link_speed = 0; 1271 sc->link_duplex = 0; 1272 sc->link_active = 0; 1273 } 1274 } 1275 1276 ifmr->ifm_status = IFM_AVALID; 1277 ifmr->ifm_active = IFM_ETHER; 1278 1279 if (!sc->link_active) 1280 return; 1281 1282 ifmr->ifm_status |= IFM_ACTIVE; 1283 1284 if (sc->hw.media_type == em_media_type_fiber) { 1285 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1286 } else { 1287 switch (sc->link_speed) { 1288 case 10: 1289 ifmr->ifm_active |= IFM_10_T; 1290 break; 1291 case 100: 1292 ifmr->ifm_active |= IFM_100_TX; 1293 break; 1294 case 1000: 1295 ifmr->ifm_active |= IFM_1000_T; 1296 break; 1297 } 1298 if (sc->link_duplex == FULL_DUPLEX) 1299 ifmr->ifm_active |= IFM_FDX; 1300 else 1301 ifmr->ifm_active |= IFM_HDX; 1302 } 1303} 1304 1305/********************************************************************* 1306 * 1307 * Media Ioctl callback 1308 * 1309 * This routine is called when the user changes speed/duplex using 1310 * media/mediopt option with ifconfig. 1311 * 1312 **********************************************************************/ 1313static int 1314em_media_change(struct ifnet *ifp) 1315{ 1316 struct em_softc *sc = ifp->if_softc; 1317 struct ifmedia *ifm = &sc->media; 1318 1319 INIT_DEBUGOUT("em_media_change: begin"); 1320 1321 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1322 return (EINVAL); 1323 1324 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1325 case IFM_AUTO: 1326 sc->hw.autoneg = DO_AUTO_NEG; 1327 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1328 break; 1329 case IFM_1000_SX: 1330 case IFM_1000_T: 1331 sc->hw.autoneg = DO_AUTO_NEG; 1332 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1333 break; 1334 case IFM_100_TX: 1335 sc->hw.autoneg = FALSE; 1336 sc->hw.autoneg_advertised = 0; 1337 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1338 sc->hw.forced_speed_duplex = em_100_full; 1339 else 1340 sc->hw.forced_speed_duplex = em_100_half; 1341 break; 1342 case IFM_10_T: 1343 sc->hw.autoneg = FALSE; 1344 sc->hw.autoneg_advertised = 0; 1345 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1346 sc->hw.forced_speed_duplex = em_10_full; 1347 else 1348 sc->hw.forced_speed_duplex = em_10_half; 1349 break; 1350 default: 1351 device_printf(sc->dev, "Unsupported media type\n"); 1352 } 1353 1354 /* As the speed/duplex settings my have changed we need to 1355 * reset the PHY. 1356 */ 1357 sc->hw.phy_reset_disable = FALSE; 1358 1359 em_init(sc); 1360 1361 return (0); 1362} 1363 1364/********************************************************************* 1365 * 1366 * This routine maps the mbufs to tx descriptors. 1367 * 1368 * return 0 on success, positive on failure 1369 **********************************************************************/ 1370static int 1371em_encap(struct em_softc *sc, struct mbuf **m_headp) 1372{ 1373 struct ifnet *ifp = sc->ifp; 1374 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1375 bus_dmamap_t map; 1376 struct em_buffer *tx_buffer; 1377 struct em_tx_desc *current_tx_desc; 1378 struct mbuf *m_head; 1379 struct m_tag *mtag; 1380 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1381 int nsegs, i, j; 1382 int error = 0; 1383 1384 m_head = *m_headp; 1385 current_tx_desc = NULL; 1386 txd_used = txd_saved = 0; 1387 1388 /* 1389 * Force a cleanup if number of TX descriptors 1390 * available hits the threshold. 1391 */ 1392 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1393 em_txeof(sc); 1394 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1395 sc->no_tx_desc_avail1++; 1396 return (ENOBUFS); 1397 } 1398 } 1399 1400 /* 1401 * Map the packet for DMA. 1402 */ 1403 tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc]; 1404 error = bus_dmamap_load_mbuf_sg(sc->txtag, tx_buffer->map, m_head, 1405 segs, &nsegs, BUS_DMA_NOWAIT); 1406 map = tx_buffer->map; 1407 if (error != 0) { 1408 sc->no_tx_dma_setup++; 1409 return (error); 1410 } 1411 KASSERT(nsegs != 0, ("em_encap: empty packet")); 1412 1413 if (nsegs > sc->num_tx_desc_avail) { 1414 sc->no_tx_desc_avail2++; 1415 error = ENOBUFS; 1416 goto encap_fail; 1417 } 1418 1419 if (ifp->if_hwassist > 0) 1420 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1421 else 1422 txd_upper = txd_lower = 0; 1423 1424 /* Find out if we are in vlan mode. */ 1425 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1426 1427 /* 1428 * When operating in promiscuous mode, hardware encapsulation for 1429 * packets is disabled. This means we have to add the vlan 1430 * encapsulation in the driver, since it will have come down from the 1431 * VLAN layer with a tag instead of a VLAN header. 1432 */ 1433 if (mtag != NULL && sc->em_insert_vlan_header) { 1434 struct ether_vlan_header *evl; 1435 struct ether_header eh; 1436 1437 m_head = m_pullup(m_head, sizeof(eh)); 1438 if (m_head == NULL) { 1439 *m_headp = NULL; 1440 error = ENOBUFS; 1441 goto encap_fail; 1442 } 1443 eh = *mtod(m_head, struct ether_header *); 1444 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1445 if (m_head == NULL) { 1446 *m_headp = NULL; 1447 error = ENOBUFS; 1448 goto encap_fail; 1449 } 1450 m_head = m_pullup(m_head, sizeof(*evl)); 1451 if (m_head == NULL) { 1452 *m_headp = NULL; 1453 error = ENOBUFS; 1454 goto encap_fail; 1455 } 1456 evl = mtod(m_head, struct ether_vlan_header *); 1457 bcopy(&eh, evl, sizeof(*evl)); 1458 evl->evl_proto = evl->evl_encap_proto; 1459 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1460 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1461 m_tag_delete(m_head, mtag); 1462 mtag = NULL; 1463 *m_headp = m_head; 1464 } 1465 1466 i = sc->next_avail_tx_desc; 1467 if (sc->pcix_82544) { 1468 txd_saved = i; 1469 txd_used = 0; 1470 } 1471 for (j = 0; j < nsegs; j++) { 1472 /* If adapter is 82544 and on PCIX bus. */ 1473 if(sc->pcix_82544) { 1474 DESC_ARRAY desc_array; 1475 uint32_t array_elements, counter; 1476 1477 /* 1478 * Check the Address and Length combination and 1479 * split the data accordingly 1480 */ 1481 array_elements = em_fill_descriptors(segs[j].ds_addr, 1482 segs[j].ds_len, &desc_array); 1483 for (counter = 0; counter < array_elements; counter++) { 1484 if (txd_used == sc->num_tx_desc_avail) { 1485 sc->next_avail_tx_desc = txd_saved; 1486 sc->no_tx_desc_avail2++; 1487 error = ENOBUFS; 1488 goto encap_fail; 1489 } 1490 tx_buffer = &sc->tx_buffer_area[i]; 1491 current_tx_desc = &sc->tx_desc_base[i]; 1492 current_tx_desc->buffer_addr = htole64( 1493 desc_array.descriptor[counter].address); 1494 current_tx_desc->lower.data = htole32( 1495 (sc->txd_cmd | txd_lower | 1496 (uint16_t)desc_array.descriptor[counter].length)); 1497 current_tx_desc->upper.data = htole32((txd_upper)); 1498 if (++i == sc->num_tx_desc) 1499 i = 0; 1500 1501 tx_buffer->m_head = NULL; 1502 txd_used++; 1503 } 1504 } else { 1505 tx_buffer = &sc->tx_buffer_area[i]; 1506 current_tx_desc = &sc->tx_desc_base[i]; 1507 1508 current_tx_desc->buffer_addr = htole64(segs[j].ds_addr); 1509 current_tx_desc->lower.data = htole32( 1510 sc->txd_cmd | txd_lower | segs[j].ds_len); 1511 current_tx_desc->upper.data = htole32(txd_upper); 1512 1513 if (++i == sc->num_tx_desc) 1514 i = 0; 1515 1516 tx_buffer->m_head = NULL; 1517 } 1518 } 1519 1520 sc->next_avail_tx_desc = i; 1521 if (sc->pcix_82544) 1522 sc->num_tx_desc_avail -= txd_used; 1523 else 1524 sc->num_tx_desc_avail -= nsegs; 1525 1526 if (mtag != NULL) { 1527 /* Set the vlan id. */ 1528 current_tx_desc->upper.fields.special = 1529 htole16(VLAN_TAG_VALUE(mtag)); 1530 1531 /* Tell hardware to add tag. */ 1532 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1533 } 1534 1535 tx_buffer->m_head = m_head; 1536 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1537 1538 /* 1539 * Last Descriptor of Packet needs End Of Packet (EOP). 1540 */ 1541 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP); 1542 1543 /* 1544 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1545 * that this frame is available to transmit. 1546 */ 1547 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 1548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1549 if (sc->hw.mac_type == em_82547 && sc->link_duplex == HALF_DUPLEX) 1550 em_82547_move_tail_locked(sc); 1551 else { 1552 E1000_WRITE_REG(&sc->hw, TDT, i); 1553 if (sc->hw.mac_type == em_82547) 1554 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1555 } 1556 1557 return (0); 1558 1559encap_fail: 1560 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1561 return (error); 1562} 1563 1564/********************************************************************* 1565 * 1566 * 82547 workaround to avoid controller hang in half-duplex environment. 1567 * The workaround is to avoid queuing a large packet that would span 1568 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1569 * in this case. We do that only when FIFO is quiescent. 1570 * 1571 **********************************************************************/ 1572static void 1573em_82547_move_tail_locked(struct em_softc *sc) 1574{ 1575 uint16_t hw_tdt; 1576 uint16_t sw_tdt; 1577 struct em_tx_desc *tx_desc; 1578 uint16_t length = 0; 1579 boolean_t eop = 0; 1580 1581 EM_LOCK_ASSERT(sc); 1582 1583 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1584 sw_tdt = sc->next_avail_tx_desc; 1585 1586 while (hw_tdt != sw_tdt) { 1587 tx_desc = &sc->tx_desc_base[hw_tdt]; 1588 length += tx_desc->lower.flags.length; 1589 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1590 if(++hw_tdt == sc->num_tx_desc) 1591 hw_tdt = 0; 1592 1593 if (eop) { 1594 if (em_82547_fifo_workaround(sc, length)) { 1595 sc->tx_fifo_wrk_cnt++; 1596 callout_reset(&sc->tx_fifo_timer, 1, 1597 em_82547_move_tail, sc); 1598 break; 1599 } 1600 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1601 em_82547_update_fifo_head(sc, length); 1602 length = 0; 1603 } 1604 } 1605} 1606 1607static void 1608em_82547_move_tail(void *arg) 1609{ 1610 struct em_softc *sc = arg; 1611 1612 EM_LOCK(sc); 1613 em_82547_move_tail_locked(sc); 1614 EM_UNLOCK(sc); 1615} 1616 1617static int 1618em_82547_fifo_workaround(struct em_softc *sc, int len) 1619{ 1620 int fifo_space, fifo_pkt_len; 1621 1622 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1623 1624 if (sc->link_duplex == HALF_DUPLEX) { 1625 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1626 1627 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1628 if (em_82547_tx_fifo_reset(sc)) 1629 return (0); 1630 else 1631 return (1); 1632 } 1633 } 1634 1635 return (0); 1636} 1637 1638static void 1639em_82547_update_fifo_head(struct em_softc *sc, int len) 1640{ 1641 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1642 1643 /* tx_fifo_head is always 16 byte aligned */ 1644 sc->tx_fifo_head += fifo_pkt_len; 1645 if (sc->tx_fifo_head >= sc->tx_fifo_size) { 1646 sc->tx_fifo_head -= sc->tx_fifo_size; 1647 } 1648} 1649 1650 1651static int 1652em_82547_tx_fifo_reset(struct em_softc *sc) 1653{ 1654 uint32_t tctl; 1655 1656 if ((E1000_READ_REG(&sc->hw, TDT) == E1000_READ_REG(&sc->hw, TDH)) && 1657 (E1000_READ_REG(&sc->hw, TDFT) == E1000_READ_REG(&sc->hw, TDFH)) && 1658 (E1000_READ_REG(&sc->hw, TDFTS) == E1000_READ_REG(&sc->hw, TDFHS))&& 1659 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1660 1661 /* Disable TX unit */ 1662 tctl = E1000_READ_REG(&sc->hw, TCTL); 1663 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1664 1665 /* Reset FIFO pointers */ 1666 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1667 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1668 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1669 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1670 1671 /* Re-enable TX unit */ 1672 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1673 E1000_WRITE_FLUSH(&sc->hw); 1674 1675 sc->tx_fifo_head = 0; 1676 sc->tx_fifo_reset_cnt++; 1677 1678 return (TRUE); 1679 } 1680 else { 1681 return (FALSE); 1682 } 1683} 1684 1685static void 1686em_set_promisc(struct em_softc *sc) 1687{ 1688 struct ifnet *ifp = sc->ifp; 1689 uint32_t reg_rctl; 1690 1691 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1692 1693 if (ifp->if_flags & IFF_PROMISC) { 1694 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1695 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1696 /* Disable VLAN stripping in promiscous mode 1697 * This enables bridging of vlan tagged frames to occur 1698 * and also allows vlan tags to be seen in tcpdump 1699 */ 1700 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1701 em_disable_vlans(sc); 1702 sc->em_insert_vlan_header = 1; 1703 } else if (ifp->if_flags & IFF_ALLMULTI) { 1704 reg_rctl |= E1000_RCTL_MPE; 1705 reg_rctl &= ~E1000_RCTL_UPE; 1706 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1707 sc->em_insert_vlan_header = 0; 1708 } else 1709 sc->em_insert_vlan_header = 0; 1710} 1711 1712static void 1713em_disable_promisc(struct em_softc *sc) 1714{ 1715 struct ifnet *ifp = sc->ifp; 1716 uint32_t reg_rctl; 1717 1718 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1719 1720 reg_rctl &= (~E1000_RCTL_UPE); 1721 reg_rctl &= (~E1000_RCTL_MPE); 1722 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1723 1724 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1725 em_enable_vlans(sc); 1726 sc->em_insert_vlan_header = 0; 1727} 1728 1729 1730/********************************************************************* 1731 * Multicast Update 1732 * 1733 * This routine is called whenever multicast address list is updated. 1734 * 1735 **********************************************************************/ 1736 1737static void 1738em_set_multi(struct em_softc *sc) 1739{ 1740 struct ifnet *ifp = sc->ifp; 1741 struct ifmultiaddr *ifma; 1742 uint32_t reg_rctl = 0; 1743 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1744 int mcnt = 0; 1745 1746 IOCTL_DEBUGOUT("em_set_multi: begin"); 1747 1748 if (sc->hw.mac_type == em_82542_rev2_0) { 1749 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1750 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1751 em_pci_clear_mwi(&sc->hw); 1752 reg_rctl |= E1000_RCTL_RST; 1753 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1754 msec_delay(5); 1755 } 1756 1757 IF_ADDR_LOCK(ifp); 1758 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1759 if (ifma->ifma_addr->sa_family != AF_LINK) 1760 continue; 1761 1762 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1763 break; 1764 1765 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1766 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1767 mcnt++; 1768 } 1769 IF_ADDR_UNLOCK(ifp); 1770 1771 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1772 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1773 reg_rctl |= E1000_RCTL_MPE; 1774 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1775 } else 1776 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1); 1777 1778 if (sc->hw.mac_type == em_82542_rev2_0) { 1779 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1780 reg_rctl &= ~E1000_RCTL_RST; 1781 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1782 msec_delay(5); 1783 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1784 em_pci_set_mwi(&sc->hw); 1785 } 1786} 1787 1788 1789/********************************************************************* 1790 * Timer routine 1791 * 1792 * This routine checks for link status and updates statistics. 1793 * 1794 **********************************************************************/ 1795 1796static void 1797em_local_timer(void *arg) 1798{ 1799 struct em_softc *sc = arg; 1800 struct ifnet *ifp = sc->ifp; 1801 1802 EM_LOCK(sc); 1803 1804 em_check_for_link(&sc->hw); 1805 em_print_link_status(sc); 1806 em_update_stats_counters(sc); 1807 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 1808 em_print_hw_stats(sc); 1809 em_smartspeed(sc); 1810 1811 callout_reset(&sc->timer, hz, em_local_timer, sc); 1812 1813 EM_UNLOCK(sc); 1814} 1815 1816static void 1817em_print_link_status(struct em_softc *sc) 1818{ 1819 struct ifnet *ifp = sc->ifp; 1820 device_t dev = sc->dev; 1821 1822 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1823 if (sc->link_active == 0) { 1824 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 1825 &sc->link_duplex); 1826 if (bootverbose) 1827 device_printf(dev, "Link is up %d Mbps %s\n", 1828 sc->link_speed, 1829 ((sc->link_duplex == FULL_DUPLEX) ? 1830 "Full Duplex" : "Half Duplex")); 1831 sc->link_active = 1; 1832 sc->smartspeed = 0; 1833 if_link_state_change(ifp, LINK_STATE_UP); 1834 } 1835 } else { 1836 if (sc->link_active == 1) { 1837 sc->link_speed = 0; 1838 sc->link_duplex = 0; 1839 if (bootverbose) 1840 device_printf(dev, "Link is Down\n"); 1841 sc->link_active = 0; 1842 if_link_state_change(ifp, LINK_STATE_DOWN); 1843 } 1844 } 1845} 1846 1847/********************************************************************* 1848 * 1849 * This routine disables all traffic on the adapter by issuing a 1850 * global reset on the MAC and deallocates TX/RX buffers. 1851 * 1852 **********************************************************************/ 1853 1854static void 1855em_stop(void *arg) 1856{ 1857 struct em_softc *sc = arg; 1858 struct ifnet *ifp = sc->ifp; 1859 1860 EM_LOCK_ASSERT(sc); 1861 1862 INIT_DEBUGOUT("em_stop: begin"); 1863 1864 em_disable_intr(sc); 1865 em_reset_hw(&sc->hw); 1866 callout_stop(&sc->timer); 1867 callout_stop(&sc->tx_fifo_timer); 1868 em_free_transmit_structures(sc); 1869 em_free_receive_structures(sc); 1870 1871 /* Tell the stack that the interface is no longer active */ 1872 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1873} 1874 1875 1876/********************************************************************* 1877 * 1878 * Determine hardware revision. 1879 * 1880 **********************************************************************/ 1881static void 1882em_identify_hardware(struct em_softc *sc) 1883{ 1884 device_t dev = sc->dev; 1885 1886 /* Make sure our PCI config space has the necessary stuff set */ 1887 sc->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1888 if ((sc->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 1889 (sc->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 1890 device_printf(dev, "Memory Access and/or Bus Master bits " 1891 "were not set!\n"); 1892 sc->hw.pci_cmd_word |= 1893 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1894 pci_write_config(dev, PCIR_COMMAND, sc->hw.pci_cmd_word, 2); 1895 } 1896 1897 /* Save off the information about this board */ 1898 sc->hw.vendor_id = pci_get_vendor(dev); 1899 sc->hw.device_id = pci_get_device(dev); 1900 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1901 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1902 sc->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1903 1904 /* Identify the MAC */ 1905 if (em_set_mac_type(&sc->hw)) 1906 device_printf(dev, "Unknown MAC Type\n"); 1907 1908 if(sc->hw.mac_type == em_82541 || sc->hw.mac_type == em_82541_rev_2 || 1909 sc->hw.mac_type == em_82547 || sc->hw.mac_type == em_82547_rev_2) 1910 sc->hw.phy_init_script = TRUE; 1911} 1912 1913static int 1914em_allocate_pci_resources(struct em_softc *sc) 1915{ 1916 device_t dev = sc->dev; 1917 int val, rid; 1918 1919 rid = PCIR_BAR(0); 1920 sc->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1921 &rid, RF_ACTIVE); 1922 if (sc->res_memory == NULL) { 1923 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1924 return (ENXIO); 1925 } 1926 sc->osdep.mem_bus_space_tag = 1927 rman_get_bustag(sc->res_memory); 1928 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->res_memory); 1929 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 1930 1931 if (sc->hw.mac_type > em_82543) { 1932 /* Figure our where our IO BAR is ? */ 1933 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1934 val = pci_read_config(dev, rid, 4); 1935 if (E1000_BAR_TYPE(val) == E1000_BAR_TYPE_IO) { 1936 sc->io_rid = rid; 1937 break; 1938 } 1939 rid += 4; 1940 /* check for 64bit BAR */ 1941 if (E1000_BAR_MEM_TYPE(val) == E1000_BAR_MEM_TYPE_64BIT) 1942 rid += 4; 1943 } 1944 if (rid >= PCIR_CIS) { 1945 device_printf(dev, "Unable to locate IO BAR\n"); 1946 return (ENXIO); 1947 } 1948 sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1949 &sc->io_rid, RF_ACTIVE); 1950 if (sc->res_ioport == NULL) { 1951 device_printf(dev, "Unable to allocate bus resource: " 1952 "ioport\n"); 1953 return (ENXIO); 1954 } 1955 sc->hw.io_base = 0; 1956 sc->osdep.io_bus_space_tag = rman_get_bustag(sc->res_ioport); 1957 sc->osdep.io_bus_space_handle = 1958 rman_get_bushandle(sc->res_ioport); 1959 } 1960 1961 rid = 0x0; 1962 sc->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1963 RF_SHAREABLE | RF_ACTIVE); 1964 if (sc->res_interrupt == NULL) { 1965 device_printf(dev, "Unable to allocate bus resource: " 1966 "interrupt\n"); 1967 return (ENXIO); 1968 } 1969 1970 sc->hw.back = &sc->osdep; 1971 1972 return (0); 1973} 1974 1975int 1976em_allocate_intr(struct em_softc *sc) 1977{ 1978 device_t dev = sc->dev; 1979 int error; 1980 1981 /* Manually turn off all interrupts */ 1982 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 1983 1984 /* 1985 * Try allocating a fast interrupt and the associated deferred 1986 * processing contexts. If that doesn't work, try just using an 1987 * ithread. 1988 */ 1989#ifndef NO_EM_FASTINTR 1990 /* Init the deferred processing contexts. */ 1991 TASK_INIT(&sc->rxtx_task, 0, em_handle_rxtx, sc); 1992 TASK_INIT(&sc->link_task, 0, em_handle_link, sc); 1993 sc->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 1994 taskqueue_thread_enqueue, &sc->tq); 1995 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 1996 device_get_nameunit(sc->dev)); 1997 if ((error = bus_setup_intr(dev, sc->res_interrupt, 1998 INTR_TYPE_NET | INTR_FAST, em_intr_fast, sc, 1999 &sc->int_handler_tag)) != 0) { 2000 device_printf(dev, "Failed to register fast interrupt " 2001 "handler: %d\n", error); 2002 taskqueue_free(sc->tq); 2003 sc->tq = NULL; 2004 } 2005#endif 2006 if (sc->int_handler_tag == NULL && (error = bus_setup_intr(dev, 2007 sc->res_interrupt, INTR_TYPE_NET | INTR_MPSAFE, em_intr, sc, 2008 &sc->int_handler_tag)) != 0) { 2009 device_printf(dev, "Failed to register interrupt handler"); 2010 return (error); 2011 } 2012 2013 em_enable_intr(sc); 2014 return (0); 2015} 2016 2017static void 2018em_free_intr(struct em_softc *sc) 2019{ 2020 device_t dev = sc->dev; 2021 2022 if (sc->res_interrupt != NULL) { 2023 bus_teardown_intr(dev, sc->res_interrupt, sc->int_handler_tag); 2024 sc->int_handler_tag = NULL; 2025 } 2026 if (sc->tq != NULL) { 2027 taskqueue_drain(sc->tq, &sc->rxtx_task); 2028 taskqueue_drain(taskqueue_fast, &sc->link_task); 2029 taskqueue_free(sc->tq); 2030 sc->tq = NULL; 2031 } 2032} 2033 2034static void 2035em_free_pci_resources(struct em_softc *sc) 2036{ 2037 device_t dev = sc->dev; 2038 2039 if (sc->res_interrupt != NULL) 2040 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_interrupt); 2041 2042 if (sc->res_memory != NULL) 2043 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2044 sc->res_memory); 2045 2046 if (sc->res_ioport != NULL) 2047 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 2048 sc->res_ioport); 2049} 2050 2051/********************************************************************* 2052 * 2053 * Initialize the hardware to a configuration as specified by the 2054 * adapter structure. The controller is reset, the EEPROM is 2055 * verified, the MAC address is set, then the shared initialization 2056 * routines are called. 2057 * 2058 **********************************************************************/ 2059static int 2060em_hardware_init(struct em_softc *sc) 2061{ 2062 device_t dev = sc->dev; 2063 uint16_t rx_buffer_size; 2064 2065 INIT_DEBUGOUT("em_hardware_init: begin"); 2066 /* Issue a global reset */ 2067 em_reset_hw(&sc->hw); 2068 2069 /* When hardware is reset, fifo_head is also reset */ 2070 sc->tx_fifo_head = 0; 2071 2072 /* Make sure we have a good EEPROM before we read from it */ 2073 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 2074 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2075 return (EIO); 2076 } 2077 2078 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 2079 device_printf(dev, "EEPROM read error while reading part " 2080 "number\n"); 2081 return (EIO); 2082 } 2083 2084 /* 2085 * These parameters control the automatic generation (Tx) and 2086 * response (Rx) to Ethernet PAUSE frames. 2087 * - High water mark should allow for at least two frames to be 2088 * received after sending an XOFF. 2089 * - Low water mark works best when it is very near the high water mark. 2090 * This allows the receiver to restart by sending XON when it has 2091 * drained a bit. Here we use an arbitary value of 1500 which will 2092 * restart after one full frame is pulled from the buffer. There 2093 * could be several smaller frames in the buffer and if so they will 2094 * not trigger the XON until their total number reduces the buffer 2095 * by 1500. 2096 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2097 */ 2098 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 2099 2100 sc->hw.fc_high_water = rx_buffer_size - 2101 roundup2(sc->hw.max_frame_size, 1024); 2102 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 2103 sc->hw.fc_pause_time = 0x1000; 2104 sc->hw.fc_send_xon = TRUE; 2105 sc->hw.fc = em_fc_full; 2106 2107 if (em_init_hw(&sc->hw) < 0) { 2108 device_printf(dev, "Hardware Initialization Failed"); 2109 return (EIO); 2110 } 2111 2112 em_check_for_link(&sc->hw); 2113 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) 2114 sc->link_active = 1; 2115 else 2116 sc->link_active = 0; 2117 2118 if (sc->link_active) 2119 em_get_speed_and_duplex(&sc->hw, &sc->link_speed, 2120 &sc->link_duplex); 2121 else 2122 sc->link_speed = sc->link_duplex = 0; 2123 2124 return (0); 2125} 2126 2127/********************************************************************* 2128 * 2129 * Setup networking device structure and register an interface. 2130 * 2131 **********************************************************************/ 2132static void 2133em_setup_interface(device_t dev, struct em_softc *sc) 2134{ 2135 struct ifnet *ifp; 2136 INIT_DEBUGOUT("em_setup_interface: begin"); 2137 2138 ifp = sc->ifp = if_alloc(IFT_ETHER); 2139 if (ifp == NULL) 2140 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2141 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2142 ifp->if_mtu = ETHERMTU; 2143 ifp->if_baudrate = 1000000000; 2144 ifp->if_init = em_init; 2145 ifp->if_softc = sc; 2146 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2147 ifp->if_ioctl = em_ioctl; 2148 ifp->if_start = em_start; 2149 ifp->if_watchdog = em_watchdog; 2150 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 2151 ifp->if_snd.ifq_drv_maxlen = sc->num_tx_desc - 1; 2152 IFQ_SET_READY(&ifp->if_snd); 2153 2154 ether_ifattach(ifp, sc->hw.mac_addr); 2155 2156 ifp->if_capabilities = ifp->if_capenable = 0; 2157 2158 if (sc->hw.mac_type >= em_82543) { 2159 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2160 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2161 } 2162 2163 /* 2164 * Tell the upper layer(s) we support long frames. 2165 */ 2166 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2167 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2168 ifp->if_capenable |= IFCAP_VLAN_MTU; 2169 2170#ifdef DEVICE_POLLING 2171 ifp->if_capabilities |= IFCAP_POLLING; 2172#endif 2173 2174 /* 2175 * Specify the media types supported by this adapter and register 2176 * callbacks to update media and link information 2177 */ 2178 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, em_media_status); 2179 if (sc->hw.media_type == em_media_type_fiber) { 2180 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2181 0, NULL); 2182 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 2183 0, NULL); 2184 } else { 2185 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2186 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2187 0, NULL); 2188 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 2189 0, NULL); 2190 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2191 0, NULL); 2192 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2193 0, NULL); 2194 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2195 } 2196 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2197 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2198} 2199 2200 2201/********************************************************************* 2202 * 2203 * Workaround for SmartSpeed on 82541 and 82547 controllers 2204 * 2205 **********************************************************************/ 2206static void 2207em_smartspeed(struct em_softc *sc) 2208{ 2209 uint16_t phy_tmp; 2210 2211 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2212 sc->hw.autoneg == 0 || 2213 (sc->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2214 return; 2215 2216 if (sc->smartspeed == 0) { 2217 /* If Master/Slave config fault is asserted twice, 2218 * we assume back-to-back */ 2219 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2220 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2221 return; 2222 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2223 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2224 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2225 if(phy_tmp & CR_1000T_MS_ENABLE) { 2226 phy_tmp &= ~CR_1000T_MS_ENABLE; 2227 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, 2228 phy_tmp); 2229 sc->smartspeed++; 2230 if(sc->hw.autoneg && 2231 !em_phy_setup_autoneg(&sc->hw) && 2232 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2233 &phy_tmp)) { 2234 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2235 MII_CR_RESTART_AUTO_NEG); 2236 em_write_phy_reg(&sc->hw, PHY_CTRL, 2237 phy_tmp); 2238 } 2239 } 2240 } 2241 return; 2242 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2243 /* If still no link, perhaps using 2/3 pair cable */ 2244 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2245 phy_tmp |= CR_1000T_MS_ENABLE; 2246 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2247 if(sc->hw.autoneg && 2248 !em_phy_setup_autoneg(&sc->hw) && 2249 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2250 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2251 MII_CR_RESTART_AUTO_NEG); 2252 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2253 } 2254 } 2255 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2256 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2257 sc->smartspeed = 0; 2258} 2259 2260 2261/* 2262 * Manage DMA'able memory. 2263 */ 2264static void 2265em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2266{ 2267 if (error) 2268 return; 2269 *(bus_addr_t *) arg = segs[0].ds_addr; 2270} 2271 2272static int 2273em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma, 2274 int mapflags) 2275{ 2276 int error; 2277 2278 error = bus_dma_tag_create(NULL, /* parent */ 2279 E1000_DBA_ALIGN, 0, /* alignment, bounds */ 2280 BUS_SPACE_MAXADDR, /* lowaddr */ 2281 BUS_SPACE_MAXADDR, /* highaddr */ 2282 NULL, NULL, /* filter, filterarg */ 2283 size, /* maxsize */ 2284 1, /* nsegments */ 2285 size, /* maxsegsize */ 2286 0, /* flags */ 2287 NULL, /* lockfunc */ 2288 NULL, /* lockarg */ 2289 &dma->dma_tag); 2290 if (error) { 2291 device_printf(sc->dev, "%s: bus_dma_tag_create failed: %d\n", 2292 __func__, error); 2293 goto fail_0; 2294 } 2295 2296 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2297 BUS_DMA_NOWAIT, &dma->dma_map); 2298 if (error) { 2299 device_printf(sc->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2300 __func__, (uintmax_t)size, error); 2301 goto fail_2; 2302 } 2303 2304 dma->dma_paddr = 0; 2305 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2306 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2307 if (error || dma->dma_paddr == 0) { 2308 device_printf(sc->dev, "%s: bus_dmamap_load failed: %d\n", 2309 __func__, error); 2310 goto fail_3; 2311 } 2312 2313 return (0); 2314 2315fail_3: 2316 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2317fail_2: 2318 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2319 bus_dma_tag_destroy(dma->dma_tag); 2320fail_0: 2321 dma->dma_map = NULL; 2322 dma->dma_tag = NULL; 2323 2324 return (error); 2325} 2326 2327static void 2328em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2329{ 2330 if (dma->dma_tag == NULL) 2331 return; 2332 if (dma->dma_map != NULL) { 2333 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2335 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2336 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2337 dma->dma_map = NULL; 2338 } 2339 bus_dma_tag_destroy(dma->dma_tag); 2340 dma->dma_tag = NULL; 2341} 2342 2343 2344/********************************************************************* 2345 * 2346 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2347 * the information needed to transmit a packet on the wire. 2348 * 2349 **********************************************************************/ 2350static int 2351em_allocate_transmit_structures(struct em_softc *sc) 2352{ 2353 sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2354 sc->num_tx_desc, M_DEVBUF, M_NOWAIT); 2355 if (sc->tx_buffer_area == NULL) { 2356 device_printf(sc->dev, "Unable to allocate tx_buffer memory\n"); 2357 return (ENOMEM); 2358 } 2359 2360 bzero(sc->tx_buffer_area, sizeof(struct em_buffer) * sc->num_tx_desc); 2361 2362 return (0); 2363} 2364 2365/********************************************************************* 2366 * 2367 * Allocate and initialize transmit structures. 2368 * 2369 **********************************************************************/ 2370static int 2371em_setup_transmit_structures(struct em_softc *sc) 2372{ 2373 device_t dev = sc->dev; 2374 struct em_buffer *tx_buffer; 2375 bus_size_t size; 2376 int error, i; 2377 2378 /* 2379 * Setup DMA descriptor areas. 2380 */ 2381 size = roundup2(sc->hw.max_frame_size, MCLBYTES); 2382 if ((error = bus_dma_tag_create(NULL, /* parent */ 2383 1, 0, /* alignment, bounds */ 2384 BUS_SPACE_MAXADDR, /* lowaddr */ 2385 BUS_SPACE_MAXADDR, /* highaddr */ 2386 NULL, NULL, /* filter, filterarg */ 2387 size, /* maxsize */ 2388 EM_MAX_SCATTER, /* nsegments */ 2389 size, /* maxsegsize */ 2390 0, /* flags */ 2391 NULL, /* lockfunc */ 2392 NULL, /* lockarg */ 2393 &sc->txtag)) != 0) { 2394 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2395 goto fail; 2396 } 2397 2398 if ((error = em_allocate_transmit_structures(sc)) != 0) 2399 goto fail; 2400 2401 bzero(sc->tx_desc_base, (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 2402 tx_buffer = sc->tx_buffer_area; 2403 for (i = 0; i < sc->num_tx_desc; i++) { 2404 error = bus_dmamap_create(sc->txtag, 0, &tx_buffer->map); 2405 if (error != 0) { 2406 device_printf(dev, "Unable to create TX DMA map\n"); 2407 goto fail; 2408 } 2409 tx_buffer++; 2410 } 2411 2412 sc->next_avail_tx_desc = 0; 2413 sc->oldest_used_tx_desc = 0; 2414 2415 /* Set number of descriptors available */ 2416 sc->num_tx_desc_avail = sc->num_tx_desc; 2417 2418 /* Set checksum context */ 2419 sc->active_checksum_context = OFFLOAD_NONE; 2420 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2421 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2422 2423 return (0); 2424 2425fail: 2426 em_free_transmit_structures(sc); 2427 return (error); 2428} 2429 2430/********************************************************************* 2431 * 2432 * Enable transmit unit. 2433 * 2434 **********************************************************************/ 2435static void 2436em_initialize_transmit_unit(struct em_softc *sc) 2437{ 2438 uint32_t reg_tctl; 2439 uint32_t reg_tipg = 0; 2440 uint64_t bus_addr; 2441 2442 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2443 /* Setup the Base and Length of the Tx Descriptor Ring */ 2444 bus_addr = sc->txdma.dma_paddr; 2445 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr); 2446 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2447 E1000_WRITE_REG(&sc->hw, TDLEN, 2448 sc->num_tx_desc * sizeof(struct em_tx_desc)); 2449 2450 /* Setup the HW Tx Head and Tail descriptor pointers */ 2451 E1000_WRITE_REG(&sc->hw, TDH, 0); 2452 E1000_WRITE_REG(&sc->hw, TDT, 0); 2453 2454 2455 HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&sc->hw, TDBAL), 2456 E1000_READ_REG(&sc->hw, TDLEN)); 2457 2458 /* Set the default values for the Tx Inter Packet Gap timer */ 2459 switch (sc->hw.mac_type) { 2460 case em_82542_rev2_0: 2461 case em_82542_rev2_1: 2462 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2463 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2464 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2465 break; 2466 default: 2467 if (sc->hw.media_type == em_media_type_fiber) 2468 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2469 else 2470 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2471 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2472 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2473 } 2474 2475 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2476 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value); 2477 if(sc->hw.mac_type >= em_82540) 2478 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay.value); 2479 2480 /* Program the Transmit Control Register */ 2481 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2482 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2483 if (sc->hw.mac_type >= em_82571) 2484 reg_tctl |= E1000_TCTL_MULR; 2485 if (sc->link_duplex == 1) { 2486 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2487 } else { 2488 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2489 } 2490 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2491 2492 /* Setup Transmit Descriptor Settings for this adapter */ 2493 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS; 2494 2495 if (sc->tx_int_delay.value > 0) 2496 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2497} 2498 2499/********************************************************************* 2500 * 2501 * Free all transmit related data structures. 2502 * 2503 **********************************************************************/ 2504static void 2505em_free_transmit_structures(struct em_softc *sc) 2506{ 2507 struct em_buffer *tx_buffer; 2508 int i; 2509 2510 INIT_DEBUGOUT("free_transmit_structures: begin"); 2511 2512 if (sc->tx_buffer_area != NULL) { 2513 tx_buffer = sc->tx_buffer_area; 2514 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2515 if (tx_buffer->m_head != NULL) { 2516 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2517 BUS_DMASYNC_POSTWRITE); 2518 bus_dmamap_unload(sc->txtag, 2519 tx_buffer->map); 2520 m_freem(tx_buffer->m_head); 2521 tx_buffer->m_head = NULL; 2522 } else if (tx_buffer->map != NULL) 2523 bus_dmamap_unload(sc->txtag, 2524 tx_buffer->map); 2525 if (tx_buffer->map != NULL) { 2526 bus_dmamap_destroy(sc->txtag, 2527 tx_buffer->map); 2528 tx_buffer->map = NULL; 2529 } 2530 } 2531 } 2532 if (sc->tx_buffer_area != NULL) { 2533 free(sc->tx_buffer_area, M_DEVBUF); 2534 sc->tx_buffer_area = NULL; 2535 } 2536 if (sc->txtag != NULL) { 2537 bus_dma_tag_destroy(sc->txtag); 2538 sc->txtag = NULL; 2539 } 2540} 2541 2542/********************************************************************* 2543 * 2544 * The offload context needs to be set when we transfer the first 2545 * packet of a particular protocol (TCP/UDP). We change the 2546 * context only if the protocol type changes. 2547 * 2548 **********************************************************************/ 2549static void 2550em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2551 uint32_t *txd_upper, uint32_t *txd_lower) 2552{ 2553 struct em_context_desc *TXD; 2554 struct em_buffer *tx_buffer; 2555 int curr_txd; 2556 2557 if (mp->m_pkthdr.csum_flags) { 2558 2559 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2560 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2561 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2562 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2563 return; 2564 else 2565 sc->active_checksum_context = OFFLOAD_TCP_IP; 2566 2567 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2568 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2569 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2570 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2571 return; 2572 else 2573 sc->active_checksum_context = OFFLOAD_UDP_IP; 2574 } else { 2575 *txd_upper = 0; 2576 *txd_lower = 0; 2577 return; 2578 } 2579 } else { 2580 *txd_upper = 0; 2581 *txd_lower = 0; 2582 return; 2583 } 2584 2585 /* If we reach this point, the checksum offload context 2586 * needs to be reset. 2587 */ 2588 curr_txd = sc->next_avail_tx_desc; 2589 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2590 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2591 2592 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2593 TXD->lower_setup.ip_fields.ipcso = 2594 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2595 TXD->lower_setup.ip_fields.ipcse = 2596 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2597 2598 TXD->upper_setup.tcp_fields.tucss = 2599 ETHER_HDR_LEN + sizeof(struct ip); 2600 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2601 2602 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2603 TXD->upper_setup.tcp_fields.tucso = 2604 ETHER_HDR_LEN + sizeof(struct ip) + 2605 offsetof(struct tcphdr, th_sum); 2606 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2607 TXD->upper_setup.tcp_fields.tucso = 2608 ETHER_HDR_LEN + sizeof(struct ip) + 2609 offsetof(struct udphdr, uh_sum); 2610 } 2611 2612 TXD->tcp_seg_setup.data = htole32(0); 2613 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2614 2615 tx_buffer->m_head = NULL; 2616 2617 if (++curr_txd == sc->num_tx_desc) 2618 curr_txd = 0; 2619 2620 sc->num_tx_desc_avail--; 2621 sc->next_avail_tx_desc = curr_txd; 2622} 2623 2624/********************************************************************** 2625 * 2626 * Examine each tx_buffer in the used queue. If the hardware is done 2627 * processing the packet then free associated resources. The 2628 * tx_buffer is put back on the free queue. 2629 * 2630 **********************************************************************/ 2631static void 2632em_txeof(struct em_softc *sc) 2633{ 2634 int i, num_avail; 2635 struct em_buffer *tx_buffer; 2636 struct em_tx_desc *tx_desc; 2637 struct ifnet *ifp = sc->ifp; 2638 2639 EM_LOCK_ASSERT(sc); 2640 2641 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2642 return; 2643 2644 num_avail = sc->num_tx_desc_avail; 2645 i = sc->oldest_used_tx_desc; 2646 2647 tx_buffer = &sc->tx_buffer_area[i]; 2648 tx_desc = &sc->tx_desc_base[i]; 2649 2650 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2651 BUS_DMASYNC_POSTREAD); 2652 while (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2653 2654 tx_desc->upper.data = 0; 2655 num_avail++; 2656 2657 if (tx_buffer->m_head) { 2658 ifp->if_opackets++; 2659 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2660 BUS_DMASYNC_POSTWRITE); 2661 bus_dmamap_unload(sc->txtag, tx_buffer->map); 2662 2663 m_freem(tx_buffer->m_head); 2664 tx_buffer->m_head = NULL; 2665 } 2666 2667 if (++i == sc->num_tx_desc) 2668 i = 0; 2669 2670 tx_buffer = &sc->tx_buffer_area[i]; 2671 tx_desc = &sc->tx_desc_base[i]; 2672 } 2673 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 2674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2675 2676 sc->oldest_used_tx_desc = i; 2677 2678 /* 2679 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 2680 * that it is OK to send packets. 2681 * If there are no pending descriptors, clear the timeout. Otherwise, 2682 * if some descriptors have been freed, restart the timeout. 2683 */ 2684 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2685 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2686 if (num_avail == sc->num_tx_desc) 2687 ifp->if_timer = 0; 2688 else if (num_avail != sc->num_tx_desc_avail) 2689 ifp->if_timer = EM_TX_TIMEOUT; 2690 } 2691 sc->num_tx_desc_avail = num_avail; 2692} 2693 2694/********************************************************************* 2695 * 2696 * Get a buffer from system mbuf buffer pool. 2697 * 2698 **********************************************************************/ 2699static int 2700em_get_buf(int i, struct em_softc *sc, struct mbuf *mp) 2701{ 2702 struct ifnet *ifp = sc->ifp; 2703 bus_dma_segment_t segs[1]; 2704 struct em_buffer *rx_buffer; 2705 int error, nsegs; 2706 2707 if (mp == NULL) { 2708 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2709 if (mp == NULL) { 2710 sc->mbuf_cluster_failed++; 2711 return (ENOBUFS); 2712 } 2713 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2714 } else { 2715 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2716 mp->m_data = mp->m_ext.ext_buf; 2717 mp->m_next = NULL; 2718 } 2719 2720 if (ifp->if_mtu <= ETHERMTU) 2721 m_adj(mp, ETHER_ALIGN); 2722 2723 rx_buffer = &sc->rx_buffer_area[i]; 2724 2725 /* 2726 * Using memory from the mbuf cluster pool, invoke the 2727 * bus_dma machinery to arrange the memory mapping. 2728 */ 2729 error = bus_dmamap_load_mbuf_sg(sc->rxtag, rx_buffer->map, 2730 mp, segs, &nsegs, 0); 2731 if (error != 0) { 2732 m_free(mp); 2733 return (error); 2734 } 2735 /* If nsegs is wrong then the stack is corrupt. */ 2736 KASSERT(nsegs == 1, ("Too many segments returned!")); 2737 rx_buffer->m_head = mp; 2738 sc->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 2739 bus_dmamap_sync(sc->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2740 2741 return (0); 2742} 2743 2744/********************************************************************* 2745 * 2746 * Allocate memory for rx_buffer structures. Since we use one 2747 * rx_buffer per received packet, the maximum number of rx_buffer's 2748 * that we'll need is equal to the number of receive descriptors 2749 * that we've allocated. 2750 * 2751 **********************************************************************/ 2752static int 2753em_allocate_receive_structures(struct em_softc *sc) 2754{ 2755 device_t dev = sc->dev; 2756 struct em_buffer *rx_buffer; 2757 int i, error; 2758 2759 sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * sc->num_rx_desc, 2760 M_DEVBUF, M_NOWAIT); 2761 if (sc->rx_buffer_area == NULL) { 2762 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 2763 return (ENOMEM); 2764 } 2765 2766 bzero(sc->rx_buffer_area, sizeof(struct em_buffer) * sc->num_rx_desc); 2767 2768 error = bus_dma_tag_create(NULL, /* parent */ 2769 1, 0, /* alignment, bounds */ 2770 BUS_SPACE_MAXADDR, /* lowaddr */ 2771 BUS_SPACE_MAXADDR, /* highaddr */ 2772 NULL, NULL, /* filter, filterarg */ 2773 MCLBYTES, /* maxsize */ 2774 1, /* nsegments */ 2775 MCLBYTES, /* maxsegsize */ 2776 BUS_DMA_ALLOCNOW, /* flags */ 2777 NULL, /* lockfunc */ 2778 NULL, /* lockarg */ 2779 &sc->rxtag); 2780 if (error) { 2781 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 2782 __func__, error); 2783 goto fail; 2784 } 2785 2786 rx_buffer = sc->rx_buffer_area; 2787 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2788 error = bus_dmamap_create(sc->rxtag, BUS_DMA_NOWAIT, 2789 &rx_buffer->map); 2790 if (error) { 2791 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 2792 __func__, error); 2793 goto fail; 2794 } 2795 } 2796 2797 for (i = 0; i < sc->num_rx_desc; i++) { 2798 error = em_get_buf(i, sc, NULL); 2799 if (error) 2800 goto fail; 2801 } 2802 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2804 2805 return (0); 2806 2807fail: 2808 em_free_receive_structures(sc); 2809 return (error); 2810} 2811 2812/********************************************************************* 2813 * 2814 * Allocate and initialize receive structures. 2815 * 2816 **********************************************************************/ 2817static int 2818em_setup_receive_structures(struct em_softc *sc) 2819{ 2820 int error; 2821 2822 bzero(sc->rx_desc_base, (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2823 2824 if ((error = em_allocate_receive_structures(sc)) != 0) 2825 return (error); 2826 2827 /* Setup our descriptor pointers */ 2828 sc->next_rx_desc_to_check = 0; 2829 2830 return (0); 2831} 2832 2833/********************************************************************* 2834 * 2835 * Enable receive unit. 2836 * 2837 **********************************************************************/ 2838static void 2839em_initialize_receive_unit(struct em_softc *sc) 2840{ 2841 struct ifnet *ifp = sc->ifp; 2842 uint64_t bus_addr; 2843 uint32_t reg_rctl; 2844 uint32_t reg_rxcsum; 2845 2846 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2847 2848 /* 2849 * Make sure receives are disabled while setting 2850 * up the descriptor ring 2851 */ 2852 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2853 2854 /* Set the Receive Delay Timer Register */ 2855 E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay.value | E1000_RDT_FPDB); 2856 2857 if(sc->hw.mac_type >= em_82540) { 2858 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay.value); 2859 2860 /* 2861 * Set the interrupt throttling rate. Value is calculated 2862 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2863 */ 2864#define MAX_INTS_PER_SEC 8000 2865#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2866 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2867 } 2868 2869 /* Setup the Base and Length of the Rx Descriptor Ring */ 2870 bus_addr = sc->rxdma.dma_paddr; 2871 E1000_WRITE_REG(&sc->hw, RDBAL, (uint32_t)bus_addr); 2872 E1000_WRITE_REG(&sc->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2873 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2874 sizeof(struct em_rx_desc)); 2875 2876 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2877 E1000_WRITE_REG(&sc->hw, RDH, 0); 2878 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1); 2879 2880 /* Setup the Receive Control Register */ 2881 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2882 E1000_RCTL_RDMTS_HALF | 2883 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2884 2885 if (sc->hw.tbi_compatibility_on == TRUE) 2886 reg_rctl |= E1000_RCTL_SBP; 2887 2888 2889 switch (sc->rx_buffer_len) { 2890 default: 2891 case EM_RXBUFFER_2048: 2892 reg_rctl |= E1000_RCTL_SZ_2048; 2893 break; 2894 case EM_RXBUFFER_4096: 2895 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2896 break; 2897 case EM_RXBUFFER_8192: 2898 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2899 break; 2900 case EM_RXBUFFER_16384: 2901 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2902 break; 2903 } 2904 2905 if (ifp->if_mtu > ETHERMTU) 2906 reg_rctl |= E1000_RCTL_LPE; 2907 2908 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2909 if ((sc->hw.mac_type >= em_82543) && 2910 (ifp->if_capenable & IFCAP_RXCSUM)) { 2911 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2912 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2913 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2914 } 2915 2916 /* Enable Receives */ 2917 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2918} 2919 2920/********************************************************************* 2921 * 2922 * Free receive related data structures. 2923 * 2924 **********************************************************************/ 2925static void 2926em_free_receive_structures(struct em_softc *sc) 2927{ 2928 struct em_buffer *rx_buffer; 2929 int i; 2930 2931 INIT_DEBUGOUT("free_receive_structures: begin"); 2932 2933 if (sc->rx_buffer_area != NULL) { 2934 rx_buffer = sc->rx_buffer_area; 2935 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2936 if (rx_buffer->m_head != NULL) { 2937 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2938 BUS_DMASYNC_POSTREAD); 2939 bus_dmamap_unload(sc->rxtag, 2940 rx_buffer->map); 2941 m_freem(rx_buffer->m_head); 2942 rx_buffer->m_head = NULL; 2943 } else if (rx_buffer->map != NULL) 2944 bus_dmamap_unload(sc->rxtag, 2945 rx_buffer->map); 2946 if (rx_buffer->map != NULL) { 2947 bus_dmamap_destroy(sc->rxtag, 2948 rx_buffer->map); 2949 rx_buffer->map = NULL; 2950 } 2951 } 2952 } 2953 if (sc->rx_buffer_area != NULL) { 2954 free(sc->rx_buffer_area, M_DEVBUF); 2955 sc->rx_buffer_area = NULL; 2956 } 2957 if (sc->rxtag != NULL) { 2958 bus_dma_tag_destroy(sc->rxtag); 2959 sc->rxtag = NULL; 2960 } 2961} 2962 2963/********************************************************************* 2964 * 2965 * This routine executes in interrupt context. It replenishes 2966 * the mbufs in the descriptor and sends data which has been 2967 * dma'ed into host memory to upper layer. 2968 * 2969 * We loop at most count times if count is > 0, or until done if 2970 * count < 0. 2971 * 2972 *********************************************************************/ 2973static int 2974em_rxeof(struct em_softc *sc, int count) 2975{ 2976 struct ifnet *ifp; 2977 struct mbuf *mp; 2978 uint8_t accept_frame = 0; 2979 uint8_t eop = 0; 2980 uint16_t len, desc_len, prev_len_adj; 2981 int i; 2982 2983 /* Pointer to the receive descriptor being examined. */ 2984 struct em_rx_desc *current_desc; 2985 2986 ifp = sc->ifp; 2987 i = sc->next_rx_desc_to_check; 2988 current_desc = &sc->rx_desc_base[i]; 2989 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2990 BUS_DMASYNC_POSTREAD); 2991 2992 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 2993 return (0); 2994 2995 while ((current_desc->status & E1000_RXD_STAT_DD) && 2996 (count != 0) && 2997 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2998 struct mbuf *m = NULL; 2999 3000 mp = sc->rx_buffer_area[i].m_head; 3001 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map, 3002 BUS_DMASYNC_POSTREAD); 3003 bus_dmamap_unload(sc->rxtag, 3004 sc->rx_buffer_area[i].map); 3005 3006 accept_frame = 1; 3007 prev_len_adj = 0; 3008 desc_len = le16toh(current_desc->length); 3009 if (current_desc->status & E1000_RXD_STAT_EOP) { 3010 count--; 3011 eop = 1; 3012 if (desc_len < ETHER_CRC_LEN) { 3013 len = 0; 3014 prev_len_adj = ETHER_CRC_LEN - desc_len; 3015 } else 3016 len = desc_len - ETHER_CRC_LEN; 3017 } else { 3018 eop = 0; 3019 len = desc_len; 3020 } 3021 3022 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3023 uint8_t last_byte; 3024 uint32_t pkt_len = desc_len; 3025 3026 if (sc->fmp != NULL) 3027 pkt_len += sc->fmp->m_pkthdr.len; 3028 3029 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3030 if (TBI_ACCEPT(&sc->hw, current_desc->status, 3031 current_desc->errors, 3032 pkt_len, last_byte)) { 3033 em_tbi_adjust_stats(&sc->hw, 3034 &sc->stats, pkt_len, 3035 sc->hw.mac_addr); 3036 if (len > 0) 3037 len--; 3038 } else 3039 accept_frame = 0; 3040 } 3041 3042 if (accept_frame) { 3043 if (em_get_buf(i, sc, NULL) == ENOBUFS) { 3044 sc->dropped_pkts++; 3045 em_get_buf(i, sc, mp); 3046 if (sc->fmp != NULL) 3047 m_freem(sc->fmp); 3048 sc->fmp = NULL; 3049 sc->lmp = NULL; 3050 break; 3051 } 3052 3053 /* Assign correct length to the current fragment */ 3054 mp->m_len = len; 3055 3056 if (sc->fmp == NULL) { 3057 mp->m_pkthdr.len = len; 3058 sc->fmp = mp; /* Store the first mbuf */ 3059 sc->lmp = mp; 3060 } else { 3061 /* Chain mbuf's together */ 3062 mp->m_flags &= ~M_PKTHDR; 3063 /* 3064 * Adjust length of previous mbuf in chain if 3065 * we received less than 4 bytes in the last 3066 * descriptor. 3067 */ 3068 if (prev_len_adj > 0) { 3069 sc->lmp->m_len -= prev_len_adj; 3070 sc->fmp->m_pkthdr.len -= 3071 prev_len_adj; 3072 } 3073 sc->lmp->m_next = mp; 3074 sc->lmp = sc->lmp->m_next; 3075 sc->fmp->m_pkthdr.len += len; 3076 } 3077 3078 if (eop) { 3079 sc->fmp->m_pkthdr.rcvif = ifp; 3080 ifp->if_ipackets++; 3081 em_receive_checksum(sc, current_desc, 3082 sc->fmp); 3083#ifndef __NO_STRICT_ALIGNMENT 3084 if (ifp->if_mtu > ETHERMTU && 3085 em_fixup_rx(sc) != 0) 3086 goto skip; 3087#endif 3088 if (current_desc->status & E1000_RXD_STAT_VP) 3089 VLAN_INPUT_TAG(ifp, sc->fmp, 3090 (le16toh(current_desc->special) & 3091 E1000_RXD_SPC_VLAN_MASK)); 3092#ifndef __NO_STRICT_ALIGNMENT 3093skip: 3094#endif 3095 m = sc->fmp; 3096 sc->fmp = NULL; 3097 sc->lmp = NULL; 3098 } 3099 } else { 3100 sc->dropped_pkts++; 3101 em_get_buf(i, sc, mp); 3102 if (sc->fmp != NULL) 3103 m_freem(sc->fmp); 3104 sc->fmp = NULL; 3105 sc->lmp = NULL; 3106 } 3107 3108 /* Zero out the receive descriptors status. */ 3109 current_desc->status = 0; 3110 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 3111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3112 3113 /* Advance our pointers to the next descriptor. */ 3114 if (++i == sc->num_rx_desc) 3115 i = 0; 3116 if (m != NULL) { 3117 sc->next_rx_desc_to_check = i; 3118 (*ifp->if_input)(ifp, m); 3119 i = sc->next_rx_desc_to_check; 3120 } 3121 current_desc = &sc->rx_desc_base[i]; 3122 } 3123 sc->next_rx_desc_to_check = i; 3124 3125 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3126 if (--i < 0) 3127 i = sc->num_rx_desc - 1; 3128 E1000_WRITE_REG(&sc->hw, RDT, i); 3129 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3130 return (0); 3131 3132 return (1); 3133} 3134 3135#ifndef __NO_STRICT_ALIGNMENT 3136/* 3137 * When jumbo frames are enabled we should realign entire payload on 3138 * architecures with strict alignment. This is serious design mistake of 8254x 3139 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3140 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3141 * payload. On architecures without strict alignment restrictions 8254x still 3142 * performs unaligned memory access which would reduce the performance too. 3143 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3144 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3145 * existing mbuf chain. 3146 * 3147 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3148 * not used at all on architectures with strict alignment. 3149 */ 3150static int 3151em_fixup_rx(struct em_softc *sc) 3152{ 3153 struct mbuf *m, *n; 3154 int error; 3155 3156 error = 0; 3157 m = sc->fmp; 3158 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3159 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3160 m->m_data += ETHER_HDR_LEN; 3161 } else { 3162 MGETHDR(n, M_DONTWAIT, MT_DATA); 3163 if (n != NULL) { 3164 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3165 m->m_data += ETHER_HDR_LEN; 3166 m->m_len -= ETHER_HDR_LEN; 3167 n->m_len = ETHER_HDR_LEN; 3168 M_MOVE_PKTHDR(n, m); 3169 n->m_next = m; 3170 sc->fmp = n; 3171 } else { 3172 sc->dropped_pkts++; 3173 m_freem(sc->fmp); 3174 sc->fmp = NULL; 3175 error = ENOMEM; 3176 } 3177 } 3178 3179 return (error); 3180} 3181#endif 3182 3183/********************************************************************* 3184 * 3185 * Verify that the hardware indicated that the checksum is valid. 3186 * Inform the stack about the status of checksum so that stack 3187 * doesn't spend time verifying the checksum. 3188 * 3189 *********************************************************************/ 3190static void 3191em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 3192 struct mbuf *mp) 3193{ 3194 /* 82543 or newer only */ 3195 if ((sc->hw.mac_type < em_82543) || 3196 /* Ignore Checksum bit is set */ 3197 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3198 mp->m_pkthdr.csum_flags = 0; 3199 return; 3200 } 3201 3202 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3203 /* Did it pass? */ 3204 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3205 /* IP Checksum Good */ 3206 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3207 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3208 3209 } else { 3210 mp->m_pkthdr.csum_flags = 0; 3211 } 3212 } 3213 3214 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3215 /* Did it pass? */ 3216 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3217 mp->m_pkthdr.csum_flags |= 3218 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3219 mp->m_pkthdr.csum_data = htons(0xffff); 3220 } 3221 } 3222} 3223 3224 3225static void 3226em_enable_vlans(struct em_softc *sc) 3227{ 3228 uint32_t ctrl; 3229 3230 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 3231 3232 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3233 ctrl |= E1000_CTRL_VME; 3234 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3235} 3236 3237static void 3238em_disable_vlans(struct em_softc *sc) 3239{ 3240 uint32_t ctrl; 3241 3242 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3243 ctrl &= ~E1000_CTRL_VME; 3244 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3245} 3246 3247static void 3248em_enable_intr(struct em_softc *sc) 3249{ 3250 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3251} 3252 3253static void 3254em_disable_intr(struct em_softc *sc) 3255{ 3256 /* 3257 * The first version of 82542 had an errata where when link was forced 3258 * it would stay up even up even if the cable was disconnected. 3259 * Sequence errors were used to detect the disconnect and then the 3260 * driver would unforce the link. This code in the in the ISR. For this 3261 * to work correctly the Sequence error interrupt had to be enabled 3262 * all the time. 3263 */ 3264 3265 if (sc->hw.mac_type == em_82542_rev2_0) 3266 E1000_WRITE_REG(&sc->hw, IMC, 3267 (0xffffffff & ~E1000_IMC_RXSEQ)); 3268 else 3269 E1000_WRITE_REG(&sc->hw, IMC, 3270 0xffffffff); 3271} 3272 3273static int 3274em_is_valid_ether_addr(uint8_t *addr) 3275{ 3276 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3277 3278 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3279 return (FALSE); 3280 } 3281 3282 return (TRUE); 3283} 3284 3285void 3286em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3287{ 3288 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3289} 3290 3291void 3292em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3293{ 3294 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3295} 3296 3297void 3298em_pci_set_mwi(struct em_hw *hw) 3299{ 3300 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3301 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3302} 3303 3304void 3305em_pci_clear_mwi(struct em_hw *hw) 3306{ 3307 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3308 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3309} 3310 3311/********************************************************************* 3312* 82544 Coexistence issue workaround. 3313* There are 2 issues. 3314* 1. Transmit Hang issue. 3315* To detect this issue, following equation can be used... 3316* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3317* If SUM[3:0] is in between 1 to 4, we will have this issue. 3318* 3319* 2. DAC issue. 3320* To detect this issue, following equation can be used... 3321* SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3322* If SUM[3:0] is in between 9 to c, we will have this issue. 3323* 3324* 3325* WORKAROUND: 3326* Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3327* 3328*** *********************************************************************/ 3329static uint32_t 3330em_fill_descriptors (bus_addr_t address, uint32_t length, 3331 PDESC_ARRAY desc_array) 3332{ 3333 /* Since issue is sensitive to length and address.*/ 3334 /* Let us first check the address...*/ 3335 uint32_t safe_terminator; 3336 if (length <= 4) { 3337 desc_array->descriptor[0].address = address; 3338 desc_array->descriptor[0].length = length; 3339 desc_array->elements = 1; 3340 return (desc_array->elements); 3341 } 3342 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3343 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3344 if (safe_terminator == 0 || 3345 (safe_terminator > 4 && 3346 safe_terminator < 9) || 3347 (safe_terminator > 0xC && 3348 safe_terminator <= 0xF)) { 3349 desc_array->descriptor[0].address = address; 3350 desc_array->descriptor[0].length = length; 3351 desc_array->elements = 1; 3352 return (desc_array->elements); 3353 } 3354 3355 desc_array->descriptor[0].address = address; 3356 desc_array->descriptor[0].length = length - 4; 3357 desc_array->descriptor[1].address = address + (length - 4); 3358 desc_array->descriptor[1].length = 4; 3359 desc_array->elements = 2; 3360 return (desc_array->elements); 3361} 3362 3363/********************************************************************** 3364 * 3365 * Update the board statistics counters. 3366 * 3367 **********************************************************************/ 3368static void 3369em_update_stats_counters(struct em_softc *sc) 3370{ 3371 struct ifnet *ifp; 3372 3373 if(sc->hw.media_type == em_media_type_copper || 3374 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3375 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3376 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3377 } 3378 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3379 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3380 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3381 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3382 3383 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3384 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3385 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3386 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3387 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3388 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3389 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3390 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3391 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3392 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3393 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3394 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3395 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3396 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3397 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3398 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3399 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3400 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3401 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3402 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3403 3404 /* For the 64-bit byte counters the low dword must be read first. */ 3405 /* Both registers clear on the read of the high dword */ 3406 3407 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3408 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3409 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3410 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3411 3412 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3413 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3414 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3415 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3416 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3417 3418 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3419 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3420 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3421 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3422 3423 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3424 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3425 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3426 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3427 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3428 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3429 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3430 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3431 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3432 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3433 3434 if (sc->hw.mac_type >= em_82543) { 3435 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, ALGNERRC); 3436 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, RXERRC); 3437 sc->stats.tncrs += E1000_READ_REG(&sc->hw, TNCRS); 3438 sc->stats.cexterr += E1000_READ_REG(&sc->hw, CEXTERR); 3439 sc->stats.tsctc += E1000_READ_REG(&sc->hw, TSCTC); 3440 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, TSCTFC); 3441 } 3442 ifp = sc->ifp; 3443 3444 ifp->if_collisions = sc->stats.colc; 3445 3446 /* Rx Errors */ 3447 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3448 sc->stats.crcerrs + sc->stats.algnerrc + sc->stats.rlec + 3449 sc->stats.mpc + sc->stats.cexterr; 3450 3451 /* Tx Errors */ 3452 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3453 sc->watchdog_events; 3454} 3455 3456 3457/********************************************************************** 3458 * 3459 * This routine is called only when em_display_debug_stats is enabled. 3460 * This routine provides a way to take a look at important statistics 3461 * maintained by the driver and hardware. 3462 * 3463 **********************************************************************/ 3464static void 3465em_print_debug_info(struct em_softc *sc) 3466{ 3467 device_t dev = sc->dev; 3468 uint8_t *hw_addr = sc->hw.hw_addr; 3469 3470 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3471 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3472 E1000_READ_REG(&sc->hw, CTRL), 3473 E1000_READ_REG(&sc->hw, RCTL)); 3474 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3475 ((E1000_READ_REG(&sc->hw, PBA) & 0xffff0000) >> 16),\ 3476 (E1000_READ_REG(&sc->hw, PBA) & 0xffff) ); 3477 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3478 sc->hw.fc_high_water, 3479 sc->hw.fc_low_water); 3480 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3481 E1000_READ_REG(&sc->hw, TIDV), 3482 E1000_READ_REG(&sc->hw, TADV)); 3483 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3484 E1000_READ_REG(&sc->hw, RDTR), 3485 E1000_READ_REG(&sc->hw, RADV)); 3486 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3487 (long long)sc->tx_fifo_wrk_cnt, 3488 (long long)sc->tx_fifo_reset_cnt); 3489 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3490 E1000_READ_REG(&sc->hw, TDH), 3491 E1000_READ_REG(&sc->hw, TDT)); 3492 device_printf(dev, "Num Tx descriptors avail = %d\n", 3493 sc->num_tx_desc_avail); 3494 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3495 sc->no_tx_desc_avail1); 3496 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3497 sc->no_tx_desc_avail2); 3498 device_printf(dev, "Std mbuf failed = %ld\n", 3499 sc->mbuf_alloc_failed); 3500 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3501 sc->mbuf_cluster_failed); 3502 device_printf(dev, "Driver dropped packets = %ld\n", 3503 sc->dropped_pkts); 3504} 3505 3506static void 3507em_print_hw_stats(struct em_softc *sc) 3508{ 3509 device_t dev = sc->dev; 3510 3511 device_printf(dev, "Excessive collisions = %lld\n", 3512 (long long)sc->stats.ecol); 3513 device_printf(dev, "Symbol errors = %lld\n", 3514 (long long)sc->stats.symerrs); 3515 device_printf(dev, "Sequence errors = %lld\n", 3516 (long long)sc->stats.sec); 3517 device_printf(dev, "Defer count = %lld\n", (long long)sc->stats.dc); 3518 3519 device_printf(dev, "Missed Packets = %lld\n", (long long)sc->stats.mpc); 3520 device_printf(dev, "Receive No Buffers = %lld\n", 3521 (long long)sc->stats.rnbc); 3522 device_printf(dev, "Receive length errors = %lld\n", 3523 (long long)sc->stats.rlec); 3524 device_printf(dev, "Receive errors = %lld\n", 3525 (long long)sc->stats.rxerrc); 3526 device_printf(dev, "Crc errors = %lld\n", (long long)sc->stats.crcerrs); 3527 device_printf(dev, "Alignment errors = %lld\n", 3528 (long long)sc->stats.algnerrc); 3529 device_printf(dev, "Carrier extension errors = %lld\n", 3530 (long long)sc->stats.cexterr); 3531 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3532 device_printf(dev, "watchdog timeouts = %ld\n", sc->watchdog_events); 3533 3534 device_printf(dev, "XON Rcvd = %lld\n", (long long)sc->stats.xonrxc); 3535 device_printf(dev, "XON Xmtd = %lld\n", (long long)sc->stats.xontxc); 3536 device_printf(dev, "XOFF Rcvd = %lld\n", (long long)sc->stats.xoffrxc); 3537 device_printf(dev, "XOFF Xmtd = %lld\n", (long long)sc->stats.xofftxc); 3538 3539 device_printf(dev, "Good Packets Rcvd = %lld\n", 3540 (long long)sc->stats.gprc); 3541 device_printf(dev, "Good Packets Xmtd = %lld\n", 3542 (long long)sc->stats.gptc); 3543} 3544 3545static int 3546em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3547{ 3548 struct em_softc *sc; 3549 int error; 3550 int result; 3551 3552 result = -1; 3553 error = sysctl_handle_int(oidp, &result, 0, req); 3554 3555 if (error || !req->newptr) 3556 return (error); 3557 3558 if (result == 1) { 3559 sc = (struct em_softc *)arg1; 3560 em_print_debug_info(sc); 3561 } 3562 3563 return (error); 3564} 3565 3566 3567static int 3568em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3569{ 3570 struct em_softc *sc; 3571 int error; 3572 int result; 3573 3574 result = -1; 3575 error = sysctl_handle_int(oidp, &result, 0, req); 3576 3577 if (error || !req->newptr) 3578 return (error); 3579 3580 if (result == 1) { 3581 sc = (struct em_softc *)arg1; 3582 em_print_hw_stats(sc); 3583 } 3584 3585 return (error); 3586} 3587 3588static int 3589em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3590{ 3591 struct em_int_delay_info *info; 3592 struct em_softc *sc; 3593 uint32_t regval; 3594 int error; 3595 int usecs; 3596 int ticks; 3597 3598 info = (struct em_int_delay_info *)arg1; 3599 usecs = info->value; 3600 error = sysctl_handle_int(oidp, &usecs, 0, req); 3601 if (error != 0 || req->newptr == NULL) 3602 return (error); 3603 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3604 return (EINVAL); 3605 info->value = usecs; 3606 ticks = E1000_USECS_TO_TICKS(usecs); 3607 3608 sc = info->sc; 3609 3610 EM_LOCK(sc); 3611 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 3612 regval = (regval & ~0xffff) | (ticks & 0xffff); 3613 /* Handle a few special cases. */ 3614 switch (info->offset) { 3615 case E1000_RDTR: 3616 case E1000_82542_RDTR: 3617 regval |= E1000_RDT_FPDB; 3618 break; 3619 case E1000_TIDV: 3620 case E1000_82542_TIDV: 3621 if (ticks == 0) { 3622 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 3623 /* Don't write 0 into the TIDV register. */ 3624 regval++; 3625 } else 3626 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3627 break; 3628 } 3629 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 3630 EM_UNLOCK(sc); 3631 return (0); 3632} 3633 3634static void 3635em_add_int_delay_sysctl(struct em_softc *sc, const char *name, 3636 const char *description, struct em_int_delay_info *info, 3637 int offset, int value) 3638{ 3639 info->sc = sc; 3640 info->offset = offset; 3641 info->value = value; 3642 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 3643 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3644 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3645 info, 0, em_sysctl_int_delay, "I", description); 3646} 3647 3648#ifndef NO_EM_FASTINTR 3649static void 3650em_add_int_process_limit(struct em_softc *sc, const char *name, 3651 const char *description, int *limit, int value) 3652{ 3653 *limit = value; 3654 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 3655 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 3656 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 3657} 3658#endif 3659