1209616Sjfv/******************************************************************************
2209616Sjfv
3235527Sjfv  Copyright (c) 2001-2011, Intel Corporation
4209616Sjfv  All rights reserved.
5209616Sjfv
6209616Sjfv  Redistribution and use in source and binary forms, with or without
7209616Sjfv  modification, are permitted provided that the following conditions are met:
8209616Sjfv
9209616Sjfv   1. Redistributions of source code must retain the above copyright notice,
10209616Sjfv      this list of conditions and the following disclaimer.
11209616Sjfv
12209616Sjfv   2. Redistributions in binary form must reproduce the above copyright
13209616Sjfv      notice, this list of conditions and the following disclaimer in the
14209616Sjfv      documentation and/or other materials provided with the distribution.
15209616Sjfv
16209616Sjfv   3. Neither the name of the Intel Corporation nor the names of its
17209616Sjfv      contributors may be used to endorse or promote products derived from
18209616Sjfv      this software without specific prior written permission.
19209616Sjfv
20209616Sjfv  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21209616Sjfv  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22209616Sjfv  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23209616Sjfv  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24209616Sjfv  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25209616Sjfv  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26209616Sjfv  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27209616Sjfv  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28209616Sjfv  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29209616Sjfv  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30209616Sjfv  POSSIBILITY OF SUCH DAMAGE.
31209616Sjfv
32209616Sjfv******************************************************************************/
33209616Sjfv/*$FreeBSD$*/
34209616Sjfv
35209616Sjfv
36209616Sjfv#include "e1000_api.h"
37209616Sjfv
38209616Sjfv
39235527Sjfvstatic s32 e1000_init_phy_params_vf(struct e1000_hw *hw);
40235527Sjfvstatic s32 e1000_init_nvm_params_vf(struct e1000_hw *hw);
41235527Sjfvstatic void e1000_release_vf(struct e1000_hw *hw);
42235527Sjfvstatic s32 e1000_acquire_vf(struct e1000_hw *hw);
43235527Sjfvstatic s32 e1000_setup_link_vf(struct e1000_hw *hw);
44235527Sjfvstatic s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);
45235527Sjfvstatic s32 e1000_init_mac_params_vf(struct e1000_hw *hw);
46235527Sjfvstatic s32 e1000_check_for_link_vf(struct e1000_hw *hw);
47235527Sjfvstatic s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
48235527Sjfv				     u16 *duplex);
49235527Sjfvstatic s32 e1000_init_hw_vf(struct e1000_hw *hw);
50235527Sjfvstatic s32 e1000_reset_hw_vf(struct e1000_hw *hw);
51235527Sjfvstatic void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);
52235527Sjfvstatic void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);
53235527Sjfvstatic s32 e1000_read_mac_addr_vf(struct e1000_hw *);
54209616Sjfv
55209616Sjfv/**
56209616Sjfv *  e1000_init_phy_params_vf - Inits PHY params
57209616Sjfv *  @hw: pointer to the HW structure
58209616Sjfv *
59209616Sjfv *  Doesn't do much - there's no PHY available to the VF.
60209616Sjfv **/
61209616Sjfvstatic s32 e1000_init_phy_params_vf(struct e1000_hw *hw)
62209616Sjfv{
63209616Sjfv	DEBUGFUNC("e1000_init_phy_params_vf");
64209616Sjfv	hw->phy.type = e1000_phy_vf;
65209616Sjfv	hw->phy.ops.acquire = e1000_acquire_vf;
66209616Sjfv	hw->phy.ops.release = e1000_release_vf;
67209616Sjfv
68209616Sjfv	return E1000_SUCCESS;
69209616Sjfv}
70209616Sjfv
71209616Sjfv/**
72209616Sjfv *  e1000_init_nvm_params_vf - Inits NVM params
73209616Sjfv *  @hw: pointer to the HW structure
74209616Sjfv *
75209616Sjfv *  Doesn't do much - there's no NVM available to the VF.
76209616Sjfv **/
77209616Sjfvstatic s32 e1000_init_nvm_params_vf(struct e1000_hw *hw)
78209616Sjfv{
79209616Sjfv	DEBUGFUNC("e1000_init_nvm_params_vf");
80209616Sjfv	hw->nvm.type = e1000_nvm_none;
81209616Sjfv	hw->nvm.ops.acquire = e1000_acquire_vf;
82209616Sjfv	hw->nvm.ops.release = e1000_release_vf;
83209616Sjfv
84209616Sjfv	return E1000_SUCCESS;
85209616Sjfv}
86209616Sjfv
87209616Sjfv/**
88209616Sjfv *  e1000_init_mac_params_vf - Inits MAC params
89209616Sjfv *  @hw: pointer to the HW structure
90209616Sjfv **/
91209616Sjfvstatic s32 e1000_init_mac_params_vf(struct e1000_hw *hw)
92209616Sjfv{
93209616Sjfv	struct e1000_mac_info *mac = &hw->mac;
94209616Sjfv
95209616Sjfv	DEBUGFUNC("e1000_init_mac_params_vf");
96209616Sjfv
97209616Sjfv	/* Set media type */
98209616Sjfv	/*
99209616Sjfv	 * Virtual functions don't care what they're media type is as they
100209616Sjfv	 * have no direct access to the PHY, or the media.  That is handled
101209616Sjfv	 * by the physical function driver.
102209616Sjfv	 */
103209616Sjfv	hw->phy.media_type = e1000_media_type_unknown;
104209616Sjfv
105209616Sjfv	/* No ASF features for the VF driver */
106209616Sjfv	mac->asf_firmware_present = FALSE;
107209616Sjfv	/* ARC subsystem not supported */
108209616Sjfv	mac->arc_subsystem_valid = FALSE;
109209616Sjfv	/* Disable adaptive IFS mode so the generic funcs don't do anything */
110209616Sjfv	mac->adaptive_ifs = FALSE;
111209616Sjfv	/* VF's have no MTA Registers - PF feature only */
112209616Sjfv	mac->mta_reg_count = 128;
113209616Sjfv	/* VF's have no access to RAR entries  */
114209616Sjfv	mac->rar_entry_count = 1;
115209616Sjfv
116209616Sjfv	/* Function pointers */
117209616Sjfv	/* link setup */
118209616Sjfv	mac->ops.setup_link = e1000_setup_link_vf;
119209616Sjfv	/* bus type/speed/width */
120209616Sjfv	mac->ops.get_bus_info = e1000_get_bus_info_pcie_vf;
121209616Sjfv	/* reset */
122209616Sjfv	mac->ops.reset_hw = e1000_reset_hw_vf;
123209616Sjfv	/* hw initialization */
124209616Sjfv	mac->ops.init_hw = e1000_init_hw_vf;
125209616Sjfv	/* check for link */
126209616Sjfv	mac->ops.check_for_link = e1000_check_for_link_vf;
127209616Sjfv	/* link info */
128209616Sjfv	mac->ops.get_link_up_info = e1000_get_link_up_info_vf;
129209616Sjfv	/* multicast address update */
130209616Sjfv	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_vf;
131209616Sjfv	/* set mac address */
132209616Sjfv	mac->ops.rar_set = e1000_rar_set_vf;
133209616Sjfv	/* read mac address */
134209616Sjfv	mac->ops.read_mac_addr = e1000_read_mac_addr_vf;
135209616Sjfv
136209616Sjfv
137209616Sjfv	return E1000_SUCCESS;
138209616Sjfv}
139209616Sjfv
140209616Sjfv/**
141209616Sjfv *  e1000_init_function_pointers_vf - Inits function pointers
142209616Sjfv *  @hw: pointer to the HW structure
143209616Sjfv **/
144209616Sjfvvoid e1000_init_function_pointers_vf(struct e1000_hw *hw)
145209616Sjfv{
146209616Sjfv	DEBUGFUNC("e1000_init_function_pointers_vf");
147209616Sjfv
148209616Sjfv	hw->mac.ops.init_params = e1000_init_mac_params_vf;
149209616Sjfv	hw->nvm.ops.init_params = e1000_init_nvm_params_vf;
150209616Sjfv	hw->phy.ops.init_params = e1000_init_phy_params_vf;
151209616Sjfv	hw->mbx.ops.init_params = e1000_init_mbx_params_vf;
152209616Sjfv}
153209616Sjfv
154209616Sjfv/**
155209616Sjfv *  e1000_acquire_vf - Acquire rights to access PHY or NVM.
156209616Sjfv *  @hw: pointer to the HW structure
157209616Sjfv *
158209616Sjfv *  There is no PHY or NVM so we want all attempts to acquire these to fail.
159209616Sjfv *  In addition, the MAC registers to access PHY/NVM don't exist so we don't
160209616Sjfv *  even want any SW to attempt to use them.
161209616Sjfv **/
162209616Sjfvstatic s32 e1000_acquire_vf(struct e1000_hw *hw)
163209616Sjfv{
164209616Sjfv	return -E1000_ERR_PHY;
165209616Sjfv}
166209616Sjfv
167209616Sjfv/**
168209616Sjfv *  e1000_release_vf - Release PHY or NVM
169209616Sjfv *  @hw: pointer to the HW structure
170209616Sjfv *
171209616Sjfv *  There is no PHY or NVM so we want all attempts to acquire these to fail.
172209616Sjfv *  In addition, the MAC registers to access PHY/NVM don't exist so we don't
173209616Sjfv *  even want any SW to attempt to use them.
174209616Sjfv **/
175209616Sjfvstatic void e1000_release_vf(struct e1000_hw *hw)
176209616Sjfv{
177209616Sjfv	return;
178209616Sjfv}
179209616Sjfv
180209616Sjfv/**
181209616Sjfv *  e1000_setup_link_vf - Sets up link.
182209616Sjfv *  @hw: pointer to the HW structure
183209616Sjfv *
184209616Sjfv *  Virtual functions cannot change link.
185209616Sjfv **/
186209616Sjfvstatic s32 e1000_setup_link_vf(struct e1000_hw *hw)
187209616Sjfv{
188209616Sjfv	DEBUGFUNC("e1000_setup_link_vf");
189209616Sjfv
190209616Sjfv	return E1000_SUCCESS;
191209616Sjfv}
192209616Sjfv
193209616Sjfv/**
194209616Sjfv *  e1000_get_bus_info_pcie_vf - Gets the bus info.
195209616Sjfv *  @hw: pointer to the HW structure
196209616Sjfv *
197209616Sjfv *  Virtual functions are not really on their own bus.
198209616Sjfv **/
199209616Sjfvstatic s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw)
200209616Sjfv{
201209616Sjfv	struct e1000_bus_info *bus = &hw->bus;
202209616Sjfv
203209616Sjfv	DEBUGFUNC("e1000_get_bus_info_pcie_vf");
204209616Sjfv
205209616Sjfv	/* Do not set type PCI-E because we don't want disable master to run */
206209616Sjfv	bus->type = e1000_bus_type_reserved;
207209616Sjfv	bus->speed = e1000_bus_speed_2500;
208209616Sjfv
209209616Sjfv	return 0;
210209616Sjfv}
211209616Sjfv
212209616Sjfv/**
213209616Sjfv *  e1000_get_link_up_info_vf - Gets link info.
214209616Sjfv *  @hw: pointer to the HW structure
215209616Sjfv *  @speed: pointer to 16 bit value to store link speed.
216209616Sjfv *  @duplex: pointer to 16 bit value to store duplex.
217209616Sjfv *
218209616Sjfv *  Since we cannot read the PHY and get accurate link info, we must rely upon
219209616Sjfv *  the status register's data which is often stale and inaccurate.
220209616Sjfv **/
221209616Sjfvstatic s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
222235527Sjfv				     u16 *duplex)
223209616Sjfv{
224209616Sjfv	s32 status;
225209616Sjfv
226209616Sjfv	DEBUGFUNC("e1000_get_link_up_info_vf");
227209616Sjfv
228209616Sjfv	status = E1000_READ_REG(hw, E1000_STATUS);
229209616Sjfv	if (status & E1000_STATUS_SPEED_1000) {
230209616Sjfv		*speed = SPEED_1000;
231209616Sjfv		DEBUGOUT("1000 Mbs, ");
232209616Sjfv	} else if (status & E1000_STATUS_SPEED_100) {
233209616Sjfv		*speed = SPEED_100;
234209616Sjfv		DEBUGOUT("100 Mbs, ");
235209616Sjfv	} else {
236209616Sjfv		*speed = SPEED_10;
237209616Sjfv		DEBUGOUT("10 Mbs, ");
238209616Sjfv	}
239209616Sjfv
240209616Sjfv	if (status & E1000_STATUS_FD) {
241209616Sjfv		*duplex = FULL_DUPLEX;
242209616Sjfv		DEBUGOUT("Full Duplex\n");
243209616Sjfv	} else {
244209616Sjfv		*duplex = HALF_DUPLEX;
245209616Sjfv		DEBUGOUT("Half Duplex\n");
246209616Sjfv	}
247209616Sjfv
248209616Sjfv	return E1000_SUCCESS;
249209616Sjfv}
250209616Sjfv
251209616Sjfv/**
252209616Sjfv *  e1000_reset_hw_vf - Resets the HW
253209616Sjfv *  @hw: pointer to the HW structure
254209616Sjfv *
255209616Sjfv *  VF's provide a function level reset. This is done using bit 26 of ctrl_reg.
256209616Sjfv *  This is all the reset we can perform on a VF.
257209616Sjfv **/
258209616Sjfvstatic s32 e1000_reset_hw_vf(struct e1000_hw *hw)
259209616Sjfv{
260209616Sjfv	struct e1000_mbx_info *mbx = &hw->mbx;
261209616Sjfv	u32 timeout = E1000_VF_INIT_TIMEOUT;
262209616Sjfv	s32 ret_val = -E1000_ERR_MAC_INIT;
263209616Sjfv	u32 ctrl, msgbuf[3];
264209616Sjfv	u8 *addr = (u8 *)(&msgbuf[1]);
265209616Sjfv
266209616Sjfv	DEBUGFUNC("e1000_reset_hw_vf");
267209616Sjfv
268209616Sjfv	DEBUGOUT("Issuing a function level reset to MAC\n");
269209616Sjfv	ctrl = E1000_READ_REG(hw, E1000_CTRL);
270209616Sjfv	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
271209616Sjfv
272209616Sjfv	/* we cannot reset while the RSTI / RSTD bits are asserted */
273209616Sjfv	while (!mbx->ops.check_for_rst(hw, 0) && timeout) {
274209616Sjfv		timeout--;
275209616Sjfv		usec_delay(5);
276209616Sjfv	}
277209616Sjfv
278209616Sjfv	if (timeout) {
279209616Sjfv		/* mailbox timeout can now become active */
280209616Sjfv		mbx->timeout = E1000_VF_MBX_INIT_TIMEOUT;
281209616Sjfv
282209616Sjfv		msgbuf[0] = E1000_VF_RESET;
283209616Sjfv		mbx->ops.write_posted(hw, msgbuf, 1, 0);
284209616Sjfv
285209616Sjfv		msec_delay(10);
286209616Sjfv
287209616Sjfv		/* set our "perm_addr" based on info provided by PF */
288209616Sjfv		ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);
289209616Sjfv		if (!ret_val) {
290209616Sjfv			if (msgbuf[0] == (E1000_VF_RESET |
291235527Sjfv			    E1000_VT_MSGTYPE_ACK))
292209616Sjfv				memcpy(hw->mac.perm_addr, addr, 6);
293209616Sjfv			else
294209616Sjfv				ret_val = -E1000_ERR_MAC_INIT;
295209616Sjfv		}
296209616Sjfv	}
297209616Sjfv
298209616Sjfv	return ret_val;
299209616Sjfv}
300209616Sjfv
301209616Sjfv/**
302209616Sjfv *  e1000_init_hw_vf - Inits the HW
303209616Sjfv *  @hw: pointer to the HW structure
304209616Sjfv *
305209616Sjfv *  Not much to do here except clear the PF Reset indication if there is one.
306209616Sjfv **/
307209616Sjfvstatic s32 e1000_init_hw_vf(struct e1000_hw *hw)
308209616Sjfv{
309209616Sjfv	DEBUGFUNC("e1000_init_hw_vf");
310209616Sjfv
311209616Sjfv	/* attempt to set and restore our mac address */
312209616Sjfv	e1000_rar_set_vf(hw, hw->mac.addr, 0);
313209616Sjfv
314209616Sjfv	return E1000_SUCCESS;
315209616Sjfv}
316209616Sjfv
317209616Sjfv/**
318209616Sjfv *  e1000_rar_set_vf - set device MAC address
319209616Sjfv *  @hw: pointer to the HW structure
320209616Sjfv *  @addr: pointer to the receive address
321209616Sjfv *  @index receive address array register
322209616Sjfv **/
323209616Sjfvstatic void e1000_rar_set_vf(struct e1000_hw *hw, u8 * addr, u32 index)
324209616Sjfv{
325209616Sjfv	struct e1000_mbx_info *mbx = &hw->mbx;
326209616Sjfv	u32 msgbuf[3];
327209616Sjfv	u8 *msg_addr = (u8 *)(&msgbuf[1]);
328209616Sjfv	s32 ret_val;
329209616Sjfv
330209616Sjfv	memset(msgbuf, 0, 12);
331209616Sjfv	msgbuf[0] = E1000_VF_SET_MAC_ADDR;
332209616Sjfv	memcpy(msg_addr, addr, 6);
333209616Sjfv	ret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0);
334209616Sjfv
335209616Sjfv	if (!ret_val)
336209616Sjfv		ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);
337209616Sjfv
338209616Sjfv	msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
339209616Sjfv
340209616Sjfv	/* if nacked the address was rejected, use "perm_addr" */
341209616Sjfv	if (!ret_val &&
342209616Sjfv	    (msgbuf[0] == (E1000_VF_SET_MAC_ADDR | E1000_VT_MSGTYPE_NACK)))
343209616Sjfv		e1000_read_mac_addr_vf(hw);
344209616Sjfv}
345209616Sjfv
346209616Sjfv/**
347209616Sjfv *  e1000_hash_mc_addr_vf - Generate a multicast hash value
348209616Sjfv *  @hw: pointer to the HW structure
349209616Sjfv *  @mc_addr: pointer to a multicast address
350209616Sjfv *
351209616Sjfv *  Generates a multicast address hash value which is used to determine
352209616Sjfv *  the multicast filter table array address and new table value.
353209616Sjfv **/
354209616Sjfvstatic u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)
355209616Sjfv{
356209616Sjfv	u32 hash_value, hash_mask;
357209616Sjfv	u8 bit_shift = 0;
358209616Sjfv
359209616Sjfv	DEBUGFUNC("e1000_hash_mc_addr_generic");
360209616Sjfv
361209616Sjfv	/* Register count multiplied by bits per register */
362209616Sjfv	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
363209616Sjfv
364209616Sjfv	/*
365209616Sjfv	 * The bit_shift is the number of left-shifts
366209616Sjfv	 * where 0xFF would still fall within the hash mask.
367209616Sjfv	 */
368209616Sjfv	while (hash_mask >> bit_shift != 0xFF)
369209616Sjfv		bit_shift++;
370209616Sjfv
371209616Sjfv	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
372235527Sjfv				  (((u16) mc_addr[5]) << bit_shift)));
373209616Sjfv
374209616Sjfv	return hash_value;
375209616Sjfv}
376209616Sjfv
377235527Sjfvstatic void e1000_write_msg_read_ack(struct e1000_hw *hw,
378235527Sjfv				     u32 *msg, u16 size)
379235527Sjfv{
380235527Sjfv	struct e1000_mbx_info *mbx = &hw->mbx;
381235527Sjfv	u32 retmsg[E1000_VFMAILBOX_SIZE];
382235527Sjfv	s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
383235527Sjfv
384235527Sjfv	if (!retval)
385235527Sjfv		mbx->ops.read_posted(hw, retmsg, E1000_VFMAILBOX_SIZE, 0);
386235527Sjfv}
387235527Sjfv
388209616Sjfv/**
389209616Sjfv *  e1000_update_mc_addr_list_vf - Update Multicast addresses
390209616Sjfv *  @hw: pointer to the HW structure
391209616Sjfv *  @mc_addr_list: array of multicast addresses to program
392209616Sjfv *  @mc_addr_count: number of multicast addresses to program
393209616Sjfv *
394209616Sjfv *  Updates the Multicast Table Array.
395209616Sjfv *  The caller must have a packed mc_addr_list of multicast addresses.
396209616Sjfv **/
397209616Sjfvvoid e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
398235527Sjfv				  u8 *mc_addr_list, u32 mc_addr_count)
399209616Sjfv{
400209616Sjfv	u32 msgbuf[E1000_VFMAILBOX_SIZE];
401209616Sjfv	u16 *hash_list = (u16 *)&msgbuf[1];
402209616Sjfv	u32 hash_value;
403209616Sjfv	u32 i;
404209616Sjfv
405209616Sjfv	DEBUGFUNC("e1000_update_mc_addr_list_vf");
406209616Sjfv
407209616Sjfv	/* Each entry in the list uses 1 16 bit word.  We have 30
408209616Sjfv	 * 16 bit words available in our HW msg buffer (minus 1 for the
409209616Sjfv	 * msg type).  That's 30 hash values if we pack 'em right.  If
410209616Sjfv	 * there are more than 30 MC addresses to add then punt the
411209616Sjfv	 * extras for now and then add code to handle more than 30 later.
412209616Sjfv	 * It would be unusual for a server to request that many multi-cast
413209616Sjfv	 * addresses except for in large enterprise network environments.
414209616Sjfv	 */
415209616Sjfv
416209616Sjfv	DEBUGOUT1("MC Addr Count = %d\n", mc_addr_count);
417209616Sjfv
418209616Sjfv	if (mc_addr_count > 30) {
419209616Sjfv		msgbuf[0] |= E1000_VF_SET_MULTICAST_OVERFLOW;
420209616Sjfv		mc_addr_count = 30;
421209616Sjfv	}
422209616Sjfv
423209616Sjfv	msgbuf[0] = E1000_VF_SET_MULTICAST;
424209616Sjfv	msgbuf[0] |= mc_addr_count << E1000_VT_MSGINFO_SHIFT;
425209616Sjfv
426209616Sjfv	for (i = 0; i < mc_addr_count; i++) {
427209616Sjfv		hash_value = e1000_hash_mc_addr_vf(hw, mc_addr_list);
428209616Sjfv		DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
429209616Sjfv		hash_list[i] = hash_value & 0x0FFF;
430209616Sjfv		mc_addr_list += ETH_ADDR_LEN;
431209616Sjfv	}
432209616Sjfv
433235527Sjfv	e1000_write_msg_read_ack(hw, msgbuf, E1000_VFMAILBOX_SIZE);
434209616Sjfv}
435209616Sjfv
436209616Sjfv/**
437209616Sjfv *  e1000_vfta_set_vf - Set/Unset vlan filter table address
438209616Sjfv *  @hw: pointer to the HW structure
439209616Sjfv *  @vid: determines the vfta register and bit to set/unset
440209616Sjfv *  @set: if TRUE then set bit, else clear bit
441209616Sjfv **/
442209616Sjfvvoid e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)
443209616Sjfv{
444209616Sjfv	u32 msgbuf[2];
445209616Sjfv
446209616Sjfv	msgbuf[0] = E1000_VF_SET_VLAN;
447209616Sjfv	msgbuf[1] = vid;
448209616Sjfv	/* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
449209616Sjfv	if (set)
450209616Sjfv		msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
451209616Sjfv
452235527Sjfv	e1000_write_msg_read_ack(hw, msgbuf, 2);
453209616Sjfv}
454209616Sjfv
455209616Sjfv/** e1000_rlpml_set_vf - Set the maximum receive packet length
456209616Sjfv *  @hw: pointer to the HW structure
457209616Sjfv *  @max_size: value to assign to max frame size
458209616Sjfv **/
459209616Sjfvvoid e1000_rlpml_set_vf(struct e1000_hw *hw, u16 max_size)
460209616Sjfv{
461209616Sjfv	u32 msgbuf[2];
462209616Sjfv
463209616Sjfv	msgbuf[0] = E1000_VF_SET_LPE;
464209616Sjfv	msgbuf[1] = max_size;
465209616Sjfv
466235527Sjfv	e1000_write_msg_read_ack(hw, msgbuf, 2);
467209616Sjfv}
468209616Sjfv
469209616Sjfv/**
470209616Sjfv *  e1000_promisc_set_vf - Set flags for Unicast or Multicast promisc
471209616Sjfv *  @hw: pointer to the HW structure
472209616Sjfv *  @uni: boolean indicating unicast promisc status
473209616Sjfv *  @multi: boolean indicating multicast promisc status
474209616Sjfv **/
475209616Sjfvs32 e1000_promisc_set_vf(struct e1000_hw *hw, enum e1000_promisc_type type)
476209616Sjfv{
477209616Sjfv	struct e1000_mbx_info *mbx = &hw->mbx;
478209616Sjfv	u32 msgbuf = E1000_VF_SET_PROMISC;
479209616Sjfv	s32 ret_val;
480209616Sjfv
481209616Sjfv	switch (type) {
482209616Sjfv	case e1000_promisc_multicast:
483209616Sjfv		msgbuf |= E1000_VF_SET_PROMISC_MULTICAST;
484209616Sjfv		break;
485209616Sjfv	case e1000_promisc_enabled:
486209616Sjfv		msgbuf |= E1000_VF_SET_PROMISC_MULTICAST;
487209616Sjfv	case e1000_promisc_unicast:
488209616Sjfv		msgbuf |= E1000_VF_SET_PROMISC_UNICAST;
489209616Sjfv	case e1000_promisc_disabled:
490209616Sjfv		break;
491209616Sjfv	default:
492209616Sjfv		return -E1000_ERR_MAC_INIT;
493209616Sjfv	}
494209616Sjfv
495209616Sjfv	 ret_val = mbx->ops.write_posted(hw, &msgbuf, 1, 0);
496209616Sjfv
497209616Sjfv	if (!ret_val)
498209616Sjfv		ret_val = mbx->ops.read_posted(hw, &msgbuf, 1, 0);
499209616Sjfv
500209616Sjfv	if (!ret_val && !(msgbuf & E1000_VT_MSGTYPE_ACK))
501209616Sjfv		ret_val = -E1000_ERR_MAC_INIT;
502209616Sjfv
503209616Sjfv	return ret_val;
504209616Sjfv}
505209616Sjfv
506209616Sjfv/**
507209616Sjfv *  e1000_read_mac_addr_vf - Read device MAC address
508209616Sjfv *  @hw: pointer to the HW structure
509209616Sjfv **/
510209616Sjfvstatic s32 e1000_read_mac_addr_vf(struct e1000_hw *hw)
511209616Sjfv{
512209616Sjfv	int i;
513209616Sjfv
514209616Sjfv	for (i = 0; i < ETH_ADDR_LEN; i++)
515209616Sjfv		hw->mac.addr[i] = hw->mac.perm_addr[i];
516209616Sjfv
517209616Sjfv	return E1000_SUCCESS;
518209616Sjfv}
519209616Sjfv
520209616Sjfv/**
521209616Sjfv *  e1000_check_for_link_vf - Check for link for a virtual interface
522209616Sjfv *  @hw: pointer to the HW structure
523209616Sjfv *
524209616Sjfv *  Checks to see if the underlying PF is still talking to the VF and
525209616Sjfv *  if it is then it reports the link state to the hardware, otherwise
526209616Sjfv *  it reports link down and returns an error.
527209616Sjfv **/
528209616Sjfvstatic s32 e1000_check_for_link_vf(struct e1000_hw *hw)
529209616Sjfv{
530209616Sjfv	struct e1000_mbx_info *mbx = &hw->mbx;
531209616Sjfv	struct e1000_mac_info *mac = &hw->mac;
532209616Sjfv	s32 ret_val = E1000_SUCCESS;
533209616Sjfv	u32 in_msg = 0;
534209616Sjfv
535209616Sjfv	DEBUGFUNC("e1000_check_for_link_vf");
536209616Sjfv
537209616Sjfv	/*
538209616Sjfv	 * We only want to run this if there has been a rst asserted.
539209616Sjfv	 * in this case that could mean a link change, device reset,
540209616Sjfv	 * or a virtual function reset
541209616Sjfv	 */
542209616Sjfv
543218530Sjfv	/* If we were hit with a reset or timeout drop the link */
544218530Sjfv	if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
545209616Sjfv		mac->get_link_status = TRUE;
546209616Sjfv
547209616Sjfv	if (!mac->get_link_status)
548209616Sjfv		goto out;
549209616Sjfv
550209616Sjfv	/* if link status is down no point in checking to see if pf is up */
551209616Sjfv	if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
552209616Sjfv		goto out;
553209616Sjfv
554209616Sjfv	/* if the read failed it could just be a mailbox collision, best wait
555209616Sjfv	 * until we are called again and don't report an error */
556209616Sjfv	if (mbx->ops.read(hw, &in_msg, 1, 0))
557209616Sjfv		goto out;
558209616Sjfv
559209616Sjfv	/* if incoming message isn't clear to send we are waiting on response */
560209616Sjfv	if (!(in_msg & E1000_VT_MSGTYPE_CTS)) {
561209616Sjfv		/* message is not CTS and is NACK we have lost CTS status */
562209616Sjfv		if (in_msg & E1000_VT_MSGTYPE_NACK)
563209616Sjfv			ret_val = -E1000_ERR_MAC_INIT;
564209616Sjfv		goto out;
565209616Sjfv	}
566209616Sjfv
567209616Sjfv	/* at this point we know the PF is talking to us, check and see if
568209616Sjfv	 * we are still accepting timeout or if we had a timeout failure.
569209616Sjfv	 * if we failed then we will need to reinit */
570209616Sjfv	if (!mbx->timeout) {
571209616Sjfv		ret_val = -E1000_ERR_MAC_INIT;
572209616Sjfv		goto out;
573209616Sjfv	}
574209616Sjfv
575209616Sjfv	/* if we passed all the tests above then the link is up and we no
576209616Sjfv	 * longer need to check for link */
577209616Sjfv	mac->get_link_status = FALSE;
578209616Sjfv
579209616Sjfvout:
580209616Sjfv	return ret_val;
581209616Sjfv}
582209616Sjfv
583