e1000_mac.c revision 235527
1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_mac.c 235527 2012-05-16 22:22:52Z jfv $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.rar_set = e1000_rar_set_generic; 82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83} 84 85/** 86 * e1000_null_ops_generic - No-op function, returns 0 87 * @hw: pointer to the HW structure 88 **/ 89s32 e1000_null_ops_generic(struct e1000_hw *hw) 90{ 91 DEBUGFUNC("e1000_null_ops_generic"); 92 return E1000_SUCCESS; 93} 94 95/** 96 * e1000_null_mac_generic - No-op function, return void 97 * @hw: pointer to the HW structure 98 **/ 99void e1000_null_mac_generic(struct e1000_hw *hw) 100{ 101 DEBUGFUNC("e1000_null_mac_generic"); 102 return; 103} 104 105/** 106 * e1000_null_link_info - No-op function, return 0 107 * @hw: pointer to the HW structure 108 **/ 109s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110{ 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113} 114 115/** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119bool e1000_null_mng_mode(struct e1000_hw *hw) 120{ 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123} 124 125/** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130{ 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133} 134 135/** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140{ 141 DEBUGFUNC("e1000_null_write_vfta"); 142 return; 143} 144 145/** 146 * e1000_null_rar_set - No-op function, return void 147 * @hw: pointer to the HW structure 148 **/ 149void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150{ 151 DEBUGFUNC("e1000_null_rar_set"); 152 return; 153} 154 155/** 156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157 * @hw: pointer to the HW structure 158 * 159 * Determines and stores the system bus information for a particular 160 * network interface. The following bus information is determined and stored: 161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162 **/ 163s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164{ 165 struct e1000_mac_info *mac = &hw->mac; 166 struct e1000_bus_info *bus = &hw->bus; 167 u32 status = E1000_READ_REG(hw, E1000_STATUS); 168 s32 ret_val = E1000_SUCCESS; 169 170 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171 172 /* PCI or PCI-X? */ 173 bus->type = (status & E1000_STATUS_PCIX_MODE) 174 ? e1000_bus_type_pcix 175 : e1000_bus_type_pci; 176 177 /* Bus speed */ 178 if (bus->type == e1000_bus_type_pci) { 179 bus->speed = (status & E1000_STATUS_PCI66) 180 ? e1000_bus_speed_66 181 : e1000_bus_speed_33; 182 } else { 183 switch (status & E1000_STATUS_PCIX_SPEED) { 184 case E1000_STATUS_PCIX_SPEED_66: 185 bus->speed = e1000_bus_speed_66; 186 break; 187 case E1000_STATUS_PCIX_SPEED_100: 188 bus->speed = e1000_bus_speed_100; 189 break; 190 case E1000_STATUS_PCIX_SPEED_133: 191 bus->speed = e1000_bus_speed_133; 192 break; 193 default: 194 bus->speed = e1000_bus_speed_reserved; 195 break; 196 } 197 } 198 199 /* Bus width */ 200 bus->width = (status & E1000_STATUS_BUS64) 201 ? e1000_bus_width_64 202 : e1000_bus_width_32; 203 204 /* Which PCI(-X) function? */ 205 mac->ops.set_lan_id(hw); 206 207 return ret_val; 208} 209 210/** 211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212 * @hw: pointer to the HW structure 213 * 214 * Determines and stores the system bus information for a particular 215 * network interface. The following bus information is determined and stored: 216 * bus speed, bus width, type (PCIe), and PCIe function. 217 **/ 218s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219{ 220 struct e1000_mac_info *mac = &hw->mac; 221 struct e1000_bus_info *bus = &hw->bus; 222 s32 ret_val; 223 u16 pcie_link_status; 224 225 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226 227 bus->type = e1000_bus_type_pci_express; 228 229 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 230 &pcie_link_status); 231 if (ret_val) { 232 bus->width = e1000_bus_width_unknown; 233 bus->speed = e1000_bus_speed_unknown; 234 } else { 235 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 236 case PCIE_LINK_SPEED_2500: 237 bus->speed = e1000_bus_speed_2500; 238 break; 239 case PCIE_LINK_SPEED_5000: 240 bus->speed = e1000_bus_speed_5000; 241 break; 242 default: 243 bus->speed = e1000_bus_speed_unknown; 244 break; 245 } 246 247 bus->width = (enum e1000_bus_width)((pcie_link_status & 248 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 249 } 250 251 mac->ops.set_lan_id(hw); 252 253 return E1000_SUCCESS; 254} 255 256/** 257 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 258 * 259 * @hw: pointer to the HW structure 260 * 261 * Determines the LAN function id by reading memory-mapped registers 262 * and swaps the port value if requested. 263 **/ 264static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 265{ 266 struct e1000_bus_info *bus = &hw->bus; 267 u32 reg; 268 269 /* 270 * The status register reports the correct function number 271 * for the device regardless of function swap state. 272 */ 273 reg = E1000_READ_REG(hw, E1000_STATUS); 274 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 275} 276 277/** 278 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 279 * @hw: pointer to the HW structure 280 * 281 * Determines the LAN function id by reading PCI config space. 282 **/ 283void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 284{ 285 struct e1000_bus_info *bus = &hw->bus; 286 u16 pci_header_type; 287 u32 status; 288 289 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 290 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 291 status = E1000_READ_REG(hw, E1000_STATUS); 292 bus->func = (status & E1000_STATUS_FUNC_MASK) 293 >> E1000_STATUS_FUNC_SHIFT; 294 } else { 295 bus->func = 0; 296 } 297} 298 299/** 300 * e1000_set_lan_id_single_port - Set LAN id for a single port device 301 * @hw: pointer to the HW structure 302 * 303 * Sets the LAN function id to zero for a single port device. 304 **/ 305void e1000_set_lan_id_single_port(struct e1000_hw *hw) 306{ 307 struct e1000_bus_info *bus = &hw->bus; 308 309 bus->func = 0; 310} 311 312/** 313 * e1000_clear_vfta_generic - Clear VLAN filter table 314 * @hw: pointer to the HW structure 315 * 316 * Clears the register array which contains the VLAN filter table by 317 * setting all the values to 0. 318 **/ 319void e1000_clear_vfta_generic(struct e1000_hw *hw) 320{ 321 u32 offset; 322 323 DEBUGFUNC("e1000_clear_vfta_generic"); 324 325 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 326 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 327 E1000_WRITE_FLUSH(hw); 328 } 329} 330 331/** 332 * e1000_write_vfta_generic - Write value to VLAN filter table 333 * @hw: pointer to the HW structure 334 * @offset: register offset in VLAN filter table 335 * @value: register value written to VLAN filter table 336 * 337 * Writes value at the given offset in the register array which stores 338 * the VLAN filter table. 339 **/ 340void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 341{ 342 DEBUGFUNC("e1000_write_vfta_generic"); 343 344 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 345 E1000_WRITE_FLUSH(hw); 346} 347 348/** 349 * e1000_init_rx_addrs_generic - Initialize receive address's 350 * @hw: pointer to the HW structure 351 * @rar_count: receive address registers 352 * 353 * Setup the receive address registers by setting the base receive address 354 * register to the devices MAC address and clearing all the other receive 355 * address registers to 0. 356 **/ 357void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 358{ 359 u32 i; 360 u8 mac_addr[ETH_ADDR_LEN] = {0}; 361 362 DEBUGFUNC("e1000_init_rx_addrs_generic"); 363 364 /* Setup the receive address */ 365 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 366 367 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 368 369 /* Zero out the other (rar_entry_count - 1) receive addresses */ 370 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 371 for (i = 1; i < rar_count; i++) 372 hw->mac.ops.rar_set(hw, mac_addr, i); 373} 374 375/** 376 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 377 * @hw: pointer to the HW structure 378 * 379 * Checks the nvm for an alternate MAC address. An alternate MAC address 380 * can be setup by pre-boot software and must be treated like a permanent 381 * address and must override the actual permanent MAC address. If an 382 * alternate MAC address is found it is programmed into RAR0, replacing 383 * the permanent address that was installed into RAR0 by the Si on reset. 384 * This function will return SUCCESS unless it encounters an error while 385 * reading the EEPROM. 386 **/ 387s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 388{ 389 u32 i; 390 s32 ret_val = E1000_SUCCESS; 391 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 392 u8 alt_mac_addr[ETH_ADDR_LEN]; 393 394 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 395 396 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 397 if (ret_val) 398 goto out; 399 400 /* not supported on older hardware or 82573 */ 401 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 402 goto out; 403 404 /* 405 * Alternate MAC address is handled by the option ROM for 82580 406 * and newer. SW support not required. 407 */ 408 if (hw->mac.type >= e1000_82580) 409 goto out; 410 411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 412 &nvm_alt_mac_addr_offset); 413 if (ret_val) { 414 DEBUGOUT("NVM Read Error\n"); 415 goto out; 416 } 417 418 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 419 (nvm_alt_mac_addr_offset == 0x0000)) 420 /* There is no Alternate MAC Address */ 421 goto out; 422 423 if (hw->bus.func == E1000_FUNC_1) 424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 425 if (hw->bus.func == E1000_FUNC_2) 426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 427 428 if (hw->bus.func == E1000_FUNC_3) 429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 430 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 431 offset = nvm_alt_mac_addr_offset + (i >> 1); 432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 433 if (ret_val) { 434 DEBUGOUT("NVM Read Error\n"); 435 goto out; 436 } 437 438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 440 } 441 442 /* if multicast bit is set, the alternate address will not be used */ 443 if (alt_mac_addr[0] & 0x01) { 444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 445 goto out; 446 } 447 448 /* 449 * We have a valid alternate MAC address, and we want to treat it the 450 * same as the normal permanent MAC address stored by the HW into the 451 * RAR. Do this by mapping this address into RAR0. 452 */ 453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 454 455out: 456 return ret_val; 457} 458 459/** 460 * e1000_rar_set_generic - Set receive address register 461 * @hw: pointer to the HW structure 462 * @addr: pointer to the receive address 463 * @index: receive address array register 464 * 465 * Sets the receive address array register at index to the address passed 466 * in by addr. 467 **/ 468void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 469{ 470 u32 rar_low, rar_high; 471 472 DEBUGFUNC("e1000_rar_set_generic"); 473 474 /* 475 * HW expects these in little endian so we reverse the byte order 476 * from network order (big endian) to little endian 477 */ 478 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 479 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 480 481 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 482 483 /* If MAC address zero, no need to set the AV bit */ 484 if (rar_low || rar_high) 485 rar_high |= E1000_RAH_AV; 486 487 /* 488 * Some bridges will combine consecutive 32-bit writes into 489 * a single burst write, which will malfunction on some parts. 490 * The flushes avoid this. 491 */ 492 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 493 E1000_WRITE_FLUSH(hw); 494 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 495 E1000_WRITE_FLUSH(hw); 496} 497 498/** 499 * e1000_update_mc_addr_list_generic - Update Multicast addresses 500 * @hw: pointer to the HW structure 501 * @mc_addr_list: array of multicast addresses to program 502 * @mc_addr_count: number of multicast addresses to program 503 * 504 * Updates entire Multicast Table Array. 505 * The caller must have a packed mc_addr_list of multicast addresses. 506 **/ 507void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 508 u8 *mc_addr_list, u32 mc_addr_count) 509{ 510 u32 hash_value, hash_bit, hash_reg; 511 int i; 512 513 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 514 515 /* clear mta_shadow */ 516 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 517 518 /* update mta_shadow from mc_addr_list */ 519 for (i = 0; (u32) i < mc_addr_count; i++) { 520 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 521 522 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 523 hash_bit = hash_value & 0x1F; 524 525 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 526 mc_addr_list += (ETH_ADDR_LEN); 527 } 528 529 /* replace the entire MTA table */ 530 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 531 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 532 E1000_WRITE_FLUSH(hw); 533} 534 535/** 536 * e1000_hash_mc_addr_generic - Generate a multicast hash value 537 * @hw: pointer to the HW structure 538 * @mc_addr: pointer to a multicast address 539 * 540 * Generates a multicast address hash value which is used to determine 541 * the multicast filter table array address and new table value. 542 **/ 543u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 544{ 545 u32 hash_value, hash_mask; 546 u8 bit_shift = 0; 547 548 DEBUGFUNC("e1000_hash_mc_addr_generic"); 549 550 /* Register count multiplied by bits per register */ 551 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 552 553 /* 554 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 555 * where 0xFF would still fall within the hash mask. 556 */ 557 while (hash_mask >> bit_shift != 0xFF) 558 bit_shift++; 559 560 /* 561 * The portion of the address that is used for the hash table 562 * is determined by the mc_filter_type setting. 563 * The algorithm is such that there is a total of 8 bits of shifting. 564 * The bit_shift for a mc_filter_type of 0 represents the number of 565 * left-shifts where the MSB of mc_addr[5] would still fall within 566 * the hash_mask. Case 0 does this exactly. Since there are a total 567 * of 8 bits of shifting, then mc_addr[4] will shift right the 568 * remaining number of bits. Thus 8 - bit_shift. The rest of the 569 * cases are a variation of this algorithm...essentially raising the 570 * number of bits to shift mc_addr[5] left, while still keeping the 571 * 8-bit shifting total. 572 * 573 * For example, given the following Destination MAC Address and an 574 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 575 * we can see that the bit_shift for case 0 is 4. These are the hash 576 * values resulting from each mc_filter_type... 577 * [0] [1] [2] [3] [4] [5] 578 * 01 AA 00 12 34 56 579 * LSB MSB 580 * 581 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 582 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 583 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 584 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 585 */ 586 switch (hw->mac.mc_filter_type) { 587 default: 588 case 0: 589 break; 590 case 1: 591 bit_shift += 1; 592 break; 593 case 2: 594 bit_shift += 2; 595 break; 596 case 3: 597 bit_shift += 4; 598 break; 599 } 600 601 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 602 (((u16) mc_addr[5]) << bit_shift))); 603 604 return hash_value; 605} 606 607/** 608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 609 * @hw: pointer to the HW structure 610 * 611 * In certain situations, a system BIOS may report that the PCIx maximum 612 * memory read byte count (MMRBC) value is higher than than the actual 613 * value. We check the PCIx command register with the current PCIx status 614 * register. 615 **/ 616void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 617{ 618 u16 cmd_mmrbc; 619 u16 pcix_cmd; 620 u16 pcix_stat_hi_word; 621 u16 stat_mmrbc; 622 623 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 624 625 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 626 if (hw->bus.type != e1000_bus_type_pcix) 627 return; 628 629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 631 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 632 PCIX_COMMAND_MMRBC_SHIFT; 633 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 634 PCIX_STATUS_HI_MMRBC_SHIFT; 635 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 636 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 637 if (cmd_mmrbc > stat_mmrbc) { 638 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 639 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 641 } 642} 643 644/** 645 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 646 * @hw: pointer to the HW structure 647 * 648 * Clears the base hardware counters by reading the counter registers. 649 **/ 650void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 651{ 652 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 653 654 E1000_READ_REG(hw, E1000_CRCERRS); 655 E1000_READ_REG(hw, E1000_SYMERRS); 656 E1000_READ_REG(hw, E1000_MPC); 657 E1000_READ_REG(hw, E1000_SCC); 658 E1000_READ_REG(hw, E1000_ECOL); 659 E1000_READ_REG(hw, E1000_MCC); 660 E1000_READ_REG(hw, E1000_LATECOL); 661 E1000_READ_REG(hw, E1000_COLC); 662 E1000_READ_REG(hw, E1000_DC); 663 E1000_READ_REG(hw, E1000_SEC); 664 E1000_READ_REG(hw, E1000_RLEC); 665 E1000_READ_REG(hw, E1000_XONRXC); 666 E1000_READ_REG(hw, E1000_XONTXC); 667 E1000_READ_REG(hw, E1000_XOFFRXC); 668 E1000_READ_REG(hw, E1000_XOFFTXC); 669 E1000_READ_REG(hw, E1000_FCRUC); 670 E1000_READ_REG(hw, E1000_GPRC); 671 E1000_READ_REG(hw, E1000_BPRC); 672 E1000_READ_REG(hw, E1000_MPRC); 673 E1000_READ_REG(hw, E1000_GPTC); 674 E1000_READ_REG(hw, E1000_GORCL); 675 E1000_READ_REG(hw, E1000_GORCH); 676 E1000_READ_REG(hw, E1000_GOTCL); 677 E1000_READ_REG(hw, E1000_GOTCH); 678 E1000_READ_REG(hw, E1000_RNBC); 679 E1000_READ_REG(hw, E1000_RUC); 680 E1000_READ_REG(hw, E1000_RFC); 681 E1000_READ_REG(hw, E1000_ROC); 682 E1000_READ_REG(hw, E1000_RJC); 683 E1000_READ_REG(hw, E1000_TORL); 684 E1000_READ_REG(hw, E1000_TORH); 685 E1000_READ_REG(hw, E1000_TOTL); 686 E1000_READ_REG(hw, E1000_TOTH); 687 E1000_READ_REG(hw, E1000_TPR); 688 E1000_READ_REG(hw, E1000_TPT); 689 E1000_READ_REG(hw, E1000_MPTC); 690 E1000_READ_REG(hw, E1000_BPTC); 691} 692 693/** 694 * e1000_check_for_copper_link_generic - Check for link (Copper) 695 * @hw: pointer to the HW structure 696 * 697 * Checks to see of the link status of the hardware has changed. If a 698 * change in link status has been detected, then we read the PHY registers 699 * to get the current speed/duplex if link exists. 700 **/ 701s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 702{ 703 struct e1000_mac_info *mac = &hw->mac; 704 s32 ret_val; 705 bool link; 706 707 DEBUGFUNC("e1000_check_for_copper_link"); 708 709 /* 710 * We only want to go out to the PHY registers to see if Auto-Neg 711 * has completed and/or if our link status has changed. The 712 * get_link_status flag is set upon receiving a Link Status 713 * Change or Rx Sequence Error interrupt. 714 */ 715 if (!mac->get_link_status) { 716 ret_val = E1000_SUCCESS; 717 goto out; 718 } 719 720 /* 721 * First we want to see if the MII Status Register reports 722 * link. If so, then we want to get the current speed/duplex 723 * of the PHY. 724 */ 725 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 726 if (ret_val) 727 goto out; 728 729 if (!link) 730 goto out; /* No link detected */ 731 732 mac->get_link_status = FALSE; 733 734 /* 735 * Check if there was DownShift, must be checked 736 * immediately after link-up 737 */ 738 e1000_check_downshift_generic(hw); 739 740 /* 741 * If we are forcing speed/duplex, then we simply return since 742 * we have already determined whether we have link or not. 743 */ 744 if (!mac->autoneg) { 745 ret_val = -E1000_ERR_CONFIG; 746 goto out; 747 } 748 749 /* 750 * Auto-Neg is enabled. Auto Speed Detection takes care 751 * of MAC speed/duplex configuration. So we only need to 752 * configure Collision Distance in the MAC. 753 */ 754 mac->ops.config_collision_dist(hw); 755 756 /* 757 * Configure Flow Control now that Auto-Neg has completed. 758 * First, we need to restore the desired flow control 759 * settings because we may have had to re-autoneg with a 760 * different link partner. 761 */ 762 ret_val = e1000_config_fc_after_link_up_generic(hw); 763 if (ret_val) 764 DEBUGOUT("Error configuring flow control\n"); 765 766out: 767 return ret_val; 768} 769 770/** 771 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 772 * @hw: pointer to the HW structure 773 * 774 * Checks for link up on the hardware. If link is not up and we have 775 * a signal, then we need to force link up. 776 **/ 777s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 778{ 779 struct e1000_mac_info *mac = &hw->mac; 780 u32 rxcw; 781 u32 ctrl; 782 u32 status; 783 s32 ret_val = E1000_SUCCESS; 784 785 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 786 787 ctrl = E1000_READ_REG(hw, E1000_CTRL); 788 status = E1000_READ_REG(hw, E1000_STATUS); 789 rxcw = E1000_READ_REG(hw, E1000_RXCW); 790 791 /* 792 * If we don't have link (auto-negotiation failed or link partner 793 * cannot auto-negotiate), the cable is plugged in (we have signal), 794 * and our link partner is not trying to auto-negotiate with us (we 795 * are receiving idles or data), we need to force link up. We also 796 * need to give auto-negotiation time to complete, in case the cable 797 * was just plugged in. The autoneg_failed flag does this. 798 */ 799 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 800 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 801 (!(rxcw & E1000_RXCW_C))) { 802 if (mac->autoneg_failed == 0) { 803 mac->autoneg_failed = 1; 804 goto out; 805 } 806 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 807 808 /* Disable auto-negotiation in the TXCW register */ 809 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 810 811 /* Force link-up and also force full-duplex. */ 812 ctrl = E1000_READ_REG(hw, E1000_CTRL); 813 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 815 816 /* Configure Flow Control after forcing link up. */ 817 ret_val = e1000_config_fc_after_link_up_generic(hw); 818 if (ret_val) { 819 DEBUGOUT("Error configuring flow control\n"); 820 goto out; 821 } 822 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 823 /* 824 * If we are forcing link and we are receiving /C/ ordered 825 * sets, re-enable auto-negotiation in the TXCW register 826 * and disable forced link in the Device Control register 827 * in an attempt to auto-negotiate with our link partner. 828 */ 829 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 830 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 831 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 832 833 mac->serdes_has_link = TRUE; 834 } 835 836out: 837 return ret_val; 838} 839 840/** 841 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 842 * @hw: pointer to the HW structure 843 * 844 * Checks for link up on the hardware. If link is not up and we have 845 * a signal, then we need to force link up. 846 **/ 847s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 848{ 849 struct e1000_mac_info *mac = &hw->mac; 850 u32 rxcw; 851 u32 ctrl; 852 u32 status; 853 s32 ret_val = E1000_SUCCESS; 854 855 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 856 857 ctrl = E1000_READ_REG(hw, E1000_CTRL); 858 status = E1000_READ_REG(hw, E1000_STATUS); 859 rxcw = E1000_READ_REG(hw, E1000_RXCW); 860 861 /* 862 * If we don't have link (auto-negotiation failed or link partner 863 * cannot auto-negotiate), and our link partner is not trying to 864 * auto-negotiate with us (we are receiving idles or data), 865 * we need to force link up. We also need to give auto-negotiation 866 * time to complete. 867 */ 868 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 869 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 870 if (mac->autoneg_failed == 0) { 871 mac->autoneg_failed = 1; 872 goto out; 873 } 874 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 875 876 /* Disable auto-negotiation in the TXCW register */ 877 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 878 879 /* Force link-up and also force full-duplex. */ 880 ctrl = E1000_READ_REG(hw, E1000_CTRL); 881 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 882 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 883 884 /* Configure Flow Control after forcing link up. */ 885 ret_val = e1000_config_fc_after_link_up_generic(hw); 886 if (ret_val) { 887 DEBUGOUT("Error configuring flow control\n"); 888 goto out; 889 } 890 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 891 /* 892 * If we are forcing link and we are receiving /C/ ordered 893 * sets, re-enable auto-negotiation in the TXCW register 894 * and disable forced link in the Device Control register 895 * in an attempt to auto-negotiate with our link partner. 896 */ 897 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 898 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 899 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 900 901 mac->serdes_has_link = TRUE; 902 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 903 /* 904 * If we force link for non-auto-negotiation switch, check 905 * link status based on MAC synchronization for internal 906 * serdes media type. 907 */ 908 /* SYNCH bit and IV bit are sticky. */ 909 usec_delay(10); 910 rxcw = E1000_READ_REG(hw, E1000_RXCW); 911 if (rxcw & E1000_RXCW_SYNCH) { 912 if (!(rxcw & E1000_RXCW_IV)) { 913 mac->serdes_has_link = TRUE; 914 DEBUGOUT("SERDES: Link up - forced.\n"); 915 } 916 } else { 917 mac->serdes_has_link = FALSE; 918 DEBUGOUT("SERDES: Link down - force failed.\n"); 919 } 920 } 921 922 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 923 status = E1000_READ_REG(hw, E1000_STATUS); 924 if (status & E1000_STATUS_LU) { 925 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 926 usec_delay(10); 927 rxcw = E1000_READ_REG(hw, E1000_RXCW); 928 if (rxcw & E1000_RXCW_SYNCH) { 929 if (!(rxcw & E1000_RXCW_IV)) { 930 mac->serdes_has_link = TRUE; 931 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 932 } else { 933 mac->serdes_has_link = FALSE; 934 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 935 } 936 } else { 937 mac->serdes_has_link = FALSE; 938 DEBUGOUT("SERDES: Link down - no sync.\n"); 939 } 940 } else { 941 mac->serdes_has_link = FALSE; 942 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 943 } 944 } 945 946out: 947 return ret_val; 948} 949 950/** 951 * e1000_setup_link_generic - Setup flow control and link settings 952 * @hw: pointer to the HW structure 953 * 954 * Determines which flow control settings to use, then configures flow 955 * control. Calls the appropriate media-specific link configuration 956 * function. Assuming the adapter has a valid link partner, a valid link 957 * should be established. Assumes the hardware has previously been reset 958 * and the transmitter and receiver are not enabled. 959 **/ 960s32 e1000_setup_link_generic(struct e1000_hw *hw) 961{ 962 s32 ret_val = E1000_SUCCESS; 963 964 DEBUGFUNC("e1000_setup_link_generic"); 965 966 /* 967 * In the case of the phy reset being blocked, we already have a link. 968 * We do not need to set it up again. 969 */ 970 if (e1000_check_reset_block(hw)) 971 goto out; 972 973 /* 974 * If requested flow control is set to default, set flow control 975 * based on the EEPROM flow control settings. 976 */ 977 if (hw->fc.requested_mode == e1000_fc_default) { 978 ret_val = e1000_set_default_fc_generic(hw); 979 if (ret_val) 980 goto out; 981 } 982 983 /* 984 * Save off the requested flow control mode for use later. Depending 985 * on the link partner's capabilities, we may or may not use this mode. 986 */ 987 hw->fc.current_mode = hw->fc.requested_mode; 988 989 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 990 hw->fc.current_mode); 991 992 /* Call the necessary media_type subroutine to configure the link. */ 993 ret_val = hw->mac.ops.setup_physical_interface(hw); 994 if (ret_val) 995 goto out; 996 997 /* 998 * Initialize the flow control address, type, and PAUSE timer 999 * registers to their default values. This is done even if flow 1000 * control is disabled, because it does not hurt anything to 1001 * initialize these registers. 1002 */ 1003 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1004 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1005 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1006 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1007 1008 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1009 1010 ret_val = e1000_set_fc_watermarks_generic(hw); 1011 1012out: 1013 return ret_val; 1014} 1015 1016/** 1017 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1018 * @hw: pointer to the HW structure 1019 * 1020 * Configures collision distance and flow control for fiber and serdes 1021 * links. Upon successful setup, poll for link. 1022 **/ 1023s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1024{ 1025 struct e1000_mac_info *mac = &hw->mac; 1026 u32 ctrl; 1027 s32 ret_val = E1000_SUCCESS; 1028 1029 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1030 1031 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1032 1033 /* Take the link out of reset */ 1034 ctrl &= ~E1000_CTRL_LRST; 1035 1036 mac->ops.config_collision_dist(hw); 1037 1038 ret_val = e1000_commit_fc_settings_generic(hw); 1039 if (ret_val) 1040 goto out; 1041 1042 /* 1043 * Since auto-negotiation is enabled, take the link out of reset (the 1044 * link will be in reset, because we previously reset the chip). This 1045 * will restart auto-negotiation. If auto-negotiation is successful 1046 * then the link-up status bit will be set and the flow control enable 1047 * bits (RFCE and TFCE) will be set according to their negotiated value. 1048 */ 1049 DEBUGOUT("Auto-negotiation enabled\n"); 1050 1051 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1052 E1000_WRITE_FLUSH(hw); 1053 msec_delay(1); 1054 1055 /* 1056 * For these adapters, the SW definable pin 1 is set when the optics 1057 * detect a signal. If we have a signal, then poll for a "Link-Up" 1058 * indication. 1059 */ 1060 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1063 } else { 1064 DEBUGOUT("No signal detected\n"); 1065 } 1066 1067out: 1068 return ret_val; 1069} 1070 1071/** 1072 * e1000_config_collision_dist_generic - Configure collision distance 1073 * @hw: pointer to the HW structure 1074 * 1075 * Configures the collision distance to the default value and is used 1076 * during link setup. 1077 **/ 1078void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1079{ 1080 u32 tctl; 1081 1082 DEBUGFUNC("e1000_config_collision_dist_generic"); 1083 1084 tctl = E1000_READ_REG(hw, E1000_TCTL); 1085 1086 tctl &= ~E1000_TCTL_COLD; 1087 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1088 1089 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1090 E1000_WRITE_FLUSH(hw); 1091} 1092 1093/** 1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1095 * @hw: pointer to the HW structure 1096 * 1097 * Polls for link up by reading the status register, if link fails to come 1098 * up with auto-negotiation, then the link is forced if a signal is detected. 1099 **/ 1100s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1101{ 1102 struct e1000_mac_info *mac = &hw->mac; 1103 u32 i, status; 1104 s32 ret_val = E1000_SUCCESS; 1105 1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1107 1108 /* 1109 * If we have a signal (the cable is plugged in, or assumed TRUE for 1110 * serdes media) then poll for a "Link-Up" indication in the Device 1111 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1112 * seconds (Auto-negotiation should complete in less than 500 1113 * milliseconds even if the other end is doing it in SW). 1114 */ 1115 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1116 msec_delay(10); 1117 status = E1000_READ_REG(hw, E1000_STATUS); 1118 if (status & E1000_STATUS_LU) 1119 break; 1120 } 1121 if (i == FIBER_LINK_UP_LIMIT) { 1122 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1123 mac->autoneg_failed = 1; 1124 /* 1125 * AutoNeg failed to achieve a link, so we'll call 1126 * mac->check_for_link. This routine will force the 1127 * link up if we detect a signal. This will allow us to 1128 * communicate with non-autonegotiating link partners. 1129 */ 1130 ret_val = mac->ops.check_for_link(hw); 1131 if (ret_val) { 1132 DEBUGOUT("Error while checking for link\n"); 1133 goto out; 1134 } 1135 mac->autoneg_failed = 0; 1136 } else { 1137 mac->autoneg_failed = 0; 1138 DEBUGOUT("Valid Link Found\n"); 1139 } 1140 1141out: 1142 return ret_val; 1143} 1144 1145/** 1146 * e1000_commit_fc_settings_generic - Configure flow control 1147 * @hw: pointer to the HW structure 1148 * 1149 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1150 * base on the flow control settings in e1000_mac_info. 1151 **/ 1152s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1153{ 1154 struct e1000_mac_info *mac = &hw->mac; 1155 u32 txcw; 1156 s32 ret_val = E1000_SUCCESS; 1157 1158 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1159 1160 /* 1161 * Check for a software override of the flow control settings, and 1162 * setup the device accordingly. If auto-negotiation is enabled, then 1163 * software will have to set the "PAUSE" bits to the correct value in 1164 * the Transmit Config Word Register (TXCW) and re-start auto- 1165 * negotiation. However, if auto-negotiation is disabled, then 1166 * software will have to manually configure the two flow control enable 1167 * bits in the CTRL register. 1168 * 1169 * The possible values of the "fc" parameter are: 1170 * 0: Flow control is completely disabled 1171 * 1: Rx flow control is enabled (we can receive pause frames, 1172 * but not send pause frames). 1173 * 2: Tx flow control is enabled (we can send pause frames but we 1174 * do not support receiving pause frames). 1175 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1176 */ 1177 switch (hw->fc.current_mode) { 1178 case e1000_fc_none: 1179 /* Flow control completely disabled by a software over-ride. */ 1180 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1181 break; 1182 case e1000_fc_rx_pause: 1183 /* 1184 * Rx Flow control is enabled and Tx Flow control is disabled 1185 * by a software over-ride. Since there really isn't a way to 1186 * advertise that we are capable of Rx Pause ONLY, we will 1187 * advertise that we support both symmetric and asymmetric Rx 1188 * PAUSE. Later, we will disable the adapter's ability to send 1189 * PAUSE frames. 1190 */ 1191 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1192 break; 1193 case e1000_fc_tx_pause: 1194 /* 1195 * Tx Flow control is enabled, and Rx Flow control is disabled, 1196 * by a software over-ride. 1197 */ 1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1199 break; 1200 case e1000_fc_full: 1201 /* 1202 * Flow control (both Rx and Tx) is enabled by a software 1203 * over-ride. 1204 */ 1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1206 break; 1207 default: 1208 DEBUGOUT("Flow control param set incorrectly\n"); 1209 ret_val = -E1000_ERR_CONFIG; 1210 goto out; 1211 break; 1212 } 1213 1214 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1215 mac->txcw = txcw; 1216 1217out: 1218 return ret_val; 1219} 1220 1221/** 1222 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1223 * @hw: pointer to the HW structure 1224 * 1225 * Sets the flow control high/low threshold (watermark) registers. If 1226 * flow control XON frame transmission is enabled, then set XON frame 1227 * transmission as well. 1228 **/ 1229s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1230{ 1231 u32 fcrtl = 0, fcrth = 0; 1232 1233 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1234 1235 /* 1236 * Set the flow control receive threshold registers. Normally, 1237 * these registers will be set to a default threshold that may be 1238 * adjusted later by the driver's runtime code. However, if the 1239 * ability to transmit pause frames is not enabled, then these 1240 * registers will be set to 0. 1241 */ 1242 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1243 /* 1244 * We need to set up the Receive Threshold high and low water 1245 * marks as well as (optionally) enabling the transmission of 1246 * XON frames. 1247 */ 1248 fcrtl = hw->fc.low_water; 1249 if (hw->fc.send_xon) 1250 fcrtl |= E1000_FCRTL_XONE; 1251 1252 fcrth = hw->fc.high_water; 1253 } 1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1256 1257 return E1000_SUCCESS; 1258} 1259 1260/** 1261 * e1000_set_default_fc_generic - Set flow control default values 1262 * @hw: pointer to the HW structure 1263 * 1264 * Read the EEPROM for the default values for flow control and store the 1265 * values. 1266 **/ 1267s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1268{ 1269 s32 ret_val = E1000_SUCCESS; 1270 u16 nvm_data; 1271 1272 DEBUGFUNC("e1000_set_default_fc_generic"); 1273 1274 /* 1275 * Read and store word 0x0F of the EEPROM. This word contains bits 1276 * that determine the hardware's default PAUSE (flow control) mode, 1277 * a bit that determines whether the HW defaults to enabling or 1278 * disabling auto-negotiation, and the direction of the 1279 * SW defined pins. If there is no SW over-ride of the flow 1280 * control setting, then the variable hw->fc will 1281 * be initialized based on a value in the EEPROM. 1282 */ 1283 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1284 1285 if (ret_val) { 1286 DEBUGOUT("NVM Read Error\n"); 1287 goto out; 1288 } 1289 1290 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1291 hw->fc.requested_mode = e1000_fc_none; 1292 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1293 NVM_WORD0F_ASM_DIR) 1294 hw->fc.requested_mode = e1000_fc_tx_pause; 1295 else 1296 hw->fc.requested_mode = e1000_fc_full; 1297 1298out: 1299 return ret_val; 1300} 1301 1302/** 1303 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1304 * @hw: pointer to the HW structure 1305 * 1306 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1307 * device control register to reflect the adapter settings. TFCE and RFCE 1308 * need to be explicitly set by software when a copper PHY is used because 1309 * autonegotiation is managed by the PHY rather than the MAC. Software must 1310 * also configure these bits when link is forced on a fiber connection. 1311 **/ 1312s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1313{ 1314 u32 ctrl; 1315 s32 ret_val = E1000_SUCCESS; 1316 1317 DEBUGFUNC("e1000_force_mac_fc_generic"); 1318 1319 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1320 1321 /* 1322 * Because we didn't get link via the internal auto-negotiation 1323 * mechanism (we either forced link or we got link via PHY 1324 * auto-neg), we have to manually enable/disable transmit an 1325 * receive flow control. 1326 * 1327 * The "Case" statement below enables/disable flow control 1328 * according to the "hw->fc.current_mode" parameter. 1329 * 1330 * The possible values of the "fc" parameter are: 1331 * 0: Flow control is completely disabled 1332 * 1: Rx flow control is enabled (we can receive pause 1333 * frames but not send pause frames). 1334 * 2: Tx flow control is enabled (we can send pause frames 1335 * frames but we do not receive pause frames). 1336 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1337 * other: No other values should be possible at this point. 1338 */ 1339 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1340 1341 switch (hw->fc.current_mode) { 1342 case e1000_fc_none: 1343 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1344 break; 1345 case e1000_fc_rx_pause: 1346 ctrl &= (~E1000_CTRL_TFCE); 1347 ctrl |= E1000_CTRL_RFCE; 1348 break; 1349 case e1000_fc_tx_pause: 1350 ctrl &= (~E1000_CTRL_RFCE); 1351 ctrl |= E1000_CTRL_TFCE; 1352 break; 1353 case e1000_fc_full: 1354 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1355 break; 1356 default: 1357 DEBUGOUT("Flow control param set incorrectly\n"); 1358 ret_val = -E1000_ERR_CONFIG; 1359 goto out; 1360 } 1361 1362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1363 1364out: 1365 return ret_val; 1366} 1367 1368/** 1369 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1370 * @hw: pointer to the HW structure 1371 * 1372 * Checks the status of auto-negotiation after link up to ensure that the 1373 * speed and duplex were not forced. If the link needed to be forced, then 1374 * flow control needs to be forced also. If auto-negotiation is enabled 1375 * and did not fail, then we configure flow control based on our link 1376 * partner. 1377 **/ 1378s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1379{ 1380 struct e1000_mac_info *mac = &hw->mac; 1381 s32 ret_val = E1000_SUCCESS; 1382 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1383 u16 speed, duplex; 1384 1385 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1386 1387 /* 1388 * Check for the case where we have fiber media and auto-neg failed 1389 * so we had to force link. In this case, we need to force the 1390 * configuration of the MAC to match the "fc" parameter. 1391 */ 1392 if (mac->autoneg_failed) { 1393 if (hw->phy.media_type == e1000_media_type_fiber || 1394 hw->phy.media_type == e1000_media_type_internal_serdes) 1395 ret_val = e1000_force_mac_fc_generic(hw); 1396 } else { 1397 if (hw->phy.media_type == e1000_media_type_copper) 1398 ret_val = e1000_force_mac_fc_generic(hw); 1399 } 1400 1401 if (ret_val) { 1402 DEBUGOUT("Error forcing flow control settings\n"); 1403 goto out; 1404 } 1405 1406 /* 1407 * Check for the case where we have copper media and auto-neg is 1408 * enabled. In this case, we need to check and see if Auto-Neg 1409 * has completed, and if so, how the PHY and link partner has 1410 * flow control configured. 1411 */ 1412 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1413 /* 1414 * Read the MII Status Register and check to see if AutoNeg 1415 * has completed. We read this twice because this reg has 1416 * some "sticky" (latched) bits. 1417 */ 1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1419 if (ret_val) 1420 goto out; 1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1422 if (ret_val) 1423 goto out; 1424 1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1426 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1427 goto out; 1428 } 1429 1430 /* 1431 * The AutoNeg process has completed, so we now need to 1432 * read both the Auto Negotiation Advertisement 1433 * Register (Address 4) and the Auto_Negotiation Base 1434 * Page Ability Register (Address 5) to determine how 1435 * flow control was negotiated. 1436 */ 1437 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1438 &mii_nway_adv_reg); 1439 if (ret_val) 1440 goto out; 1441 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1442 &mii_nway_lp_ability_reg); 1443 if (ret_val) 1444 goto out; 1445 1446 /* 1447 * Two bits in the Auto Negotiation Advertisement Register 1448 * (Address 4) and two bits in the Auto Negotiation Base 1449 * Page Ability Register (Address 5) determine flow control 1450 * for both the PHY and the link partner. The following 1451 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1452 * 1999, describes these PAUSE resolution bits and how flow 1453 * control is determined based upon these settings. 1454 * NOTE: DC = Don't Care 1455 * 1456 * LOCAL DEVICE | LINK PARTNER 1457 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1458 *-------|---------|-------|---------|-------------------- 1459 * 0 | 0 | DC | DC | e1000_fc_none 1460 * 0 | 1 | 0 | DC | e1000_fc_none 1461 * 0 | 1 | 1 | 0 | e1000_fc_none 1462 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1463 * 1 | 0 | 0 | DC | e1000_fc_none 1464 * 1 | DC | 1 | DC | e1000_fc_full 1465 * 1 | 1 | 0 | 0 | e1000_fc_none 1466 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1467 * 1468 * Are both PAUSE bits set to 1? If so, this implies 1469 * Symmetric Flow Control is enabled at both ends. The 1470 * ASM_DIR bits are irrelevant per the spec. 1471 * 1472 * For Symmetric Flow Control: 1473 * 1474 * LOCAL DEVICE | LINK PARTNER 1475 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1476 *-------|---------|-------|---------|-------------------- 1477 * 1 | DC | 1 | DC | E1000_fc_full 1478 * 1479 */ 1480 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1481 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1482 /* 1483 * Now we need to check if the user selected Rx ONLY 1484 * of pause frames. In this case, we had to advertise 1485 * FULL flow control because we could not advertise Rx 1486 * ONLY. Hence, we must now check to see if we need to 1487 * turn OFF the TRANSMISSION of PAUSE frames. 1488 */ 1489 if (hw->fc.requested_mode == e1000_fc_full) { 1490 hw->fc.current_mode = e1000_fc_full; 1491 DEBUGOUT("Flow Control = FULL.\n"); 1492 } else { 1493 hw->fc.current_mode = e1000_fc_rx_pause; 1494 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1495 } 1496 } 1497 /* 1498 * For receiving PAUSE frames ONLY. 1499 * 1500 * LOCAL DEVICE | LINK PARTNER 1501 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1502 *-------|---------|-------|---------|-------------------- 1503 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1504 */ 1505 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1506 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1507 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1508 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1509 hw->fc.current_mode = e1000_fc_tx_pause; 1510 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1511 } 1512 /* 1513 * For transmitting PAUSE frames ONLY. 1514 * 1515 * LOCAL DEVICE | LINK PARTNER 1516 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1517 *-------|---------|-------|---------|-------------------- 1518 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1519 */ 1520 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1521 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1522 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1523 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1524 hw->fc.current_mode = e1000_fc_rx_pause; 1525 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1526 } else { 1527 /* 1528 * Per the IEEE spec, at this point flow control 1529 * should be disabled. 1530 */ 1531 hw->fc.current_mode = e1000_fc_none; 1532 DEBUGOUT("Flow Control = NONE.\n"); 1533 } 1534 1535 /* 1536 * Now we need to do one last check... If we auto- 1537 * negotiated to HALF DUPLEX, flow control should not be 1538 * enabled per IEEE 802.3 spec. 1539 */ 1540 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1541 if (ret_val) { 1542 DEBUGOUT("Error getting link speed and duplex\n"); 1543 goto out; 1544 } 1545 1546 if (duplex == HALF_DUPLEX) 1547 hw->fc.current_mode = e1000_fc_none; 1548 1549 /* 1550 * Now we call a subroutine to actually force the MAC 1551 * controller to use the correct flow control settings. 1552 */ 1553 ret_val = e1000_force_mac_fc_generic(hw); 1554 if (ret_val) { 1555 DEBUGOUT("Error forcing flow control settings\n"); 1556 goto out; 1557 } 1558 } 1559 1560out: 1561 return ret_val; 1562} 1563 1564/** 1565 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1566 * @hw: pointer to the HW structure 1567 * @speed: stores the current speed 1568 * @duplex: stores the current duplex 1569 * 1570 * Read the status register for the current speed/duplex and store the current 1571 * speed and duplex for copper connections. 1572 **/ 1573s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1574 u16 *duplex) 1575{ 1576 u32 status; 1577 1578 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1579 1580 status = E1000_READ_REG(hw, E1000_STATUS); 1581 if (status & E1000_STATUS_SPEED_1000) { 1582 *speed = SPEED_1000; 1583 DEBUGOUT("1000 Mbs, "); 1584 } else if (status & E1000_STATUS_SPEED_100) { 1585 *speed = SPEED_100; 1586 DEBUGOUT("100 Mbs, "); 1587 } else { 1588 *speed = SPEED_10; 1589 DEBUGOUT("10 Mbs, "); 1590 } 1591 1592 if (status & E1000_STATUS_FD) { 1593 *duplex = FULL_DUPLEX; 1594 DEBUGOUT("Full Duplex\n"); 1595 } else { 1596 *duplex = HALF_DUPLEX; 1597 DEBUGOUT("Half Duplex\n"); 1598 } 1599 1600 return E1000_SUCCESS; 1601} 1602 1603/** 1604 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1605 * @hw: pointer to the HW structure 1606 * @speed: stores the current speed 1607 * @duplex: stores the current duplex 1608 * 1609 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1610 * for fiber/serdes links. 1611 **/ 1612s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1613 u16 *speed, u16 *duplex) 1614{ 1615 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1616 1617 *speed = SPEED_1000; 1618 *duplex = FULL_DUPLEX; 1619 1620 return E1000_SUCCESS; 1621} 1622 1623/** 1624 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1625 * @hw: pointer to the HW structure 1626 * 1627 * Acquire the HW semaphore to access the PHY or NVM 1628 **/ 1629s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1630{ 1631 u32 swsm; 1632 s32 ret_val = E1000_SUCCESS; 1633 s32 timeout = hw->nvm.word_size + 1; 1634 s32 i = 0; 1635 1636 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1637 1638 /* Get the SW semaphore */ 1639 while (i < timeout) { 1640 swsm = E1000_READ_REG(hw, E1000_SWSM); 1641 if (!(swsm & E1000_SWSM_SMBI)) 1642 break; 1643 1644 usec_delay(50); 1645 i++; 1646 } 1647 1648 if (i == timeout) { 1649 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1650 ret_val = -E1000_ERR_NVM; 1651 goto out; 1652 } 1653 1654 /* Get the FW semaphore. */ 1655 for (i = 0; i < timeout; i++) { 1656 swsm = E1000_READ_REG(hw, E1000_SWSM); 1657 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1658 1659 /* Semaphore acquired if bit latched */ 1660 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1661 break; 1662 1663 usec_delay(50); 1664 } 1665 1666 if (i == timeout) { 1667 /* Release semaphores */ 1668 e1000_put_hw_semaphore_generic(hw); 1669 DEBUGOUT("Driver can't access the NVM\n"); 1670 ret_val = -E1000_ERR_NVM; 1671 goto out; 1672 } 1673 1674out: 1675 return ret_val; 1676} 1677 1678/** 1679 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1680 * @hw: pointer to the HW structure 1681 * 1682 * Release hardware semaphore used to access the PHY or NVM 1683 **/ 1684void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1685{ 1686 u32 swsm; 1687 1688 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1689 1690 swsm = E1000_READ_REG(hw, E1000_SWSM); 1691 1692 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1693 1694 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1695} 1696 1697/** 1698 * e1000_get_auto_rd_done_generic - Check for auto read completion 1699 * @hw: pointer to the HW structure 1700 * 1701 * Check EEPROM for Auto Read done bit. 1702 **/ 1703s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1704{ 1705 s32 i = 0; 1706 s32 ret_val = E1000_SUCCESS; 1707 1708 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1709 1710 while (i < AUTO_READ_DONE_TIMEOUT) { 1711 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1712 break; 1713 msec_delay(1); 1714 i++; 1715 } 1716 1717 if (i == AUTO_READ_DONE_TIMEOUT) { 1718 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1719 ret_val = -E1000_ERR_RESET; 1720 goto out; 1721 } 1722 1723out: 1724 return ret_val; 1725} 1726 1727/** 1728 * e1000_valid_led_default_generic - Verify a valid default LED config 1729 * @hw: pointer to the HW structure 1730 * @data: pointer to the NVM (EEPROM) 1731 * 1732 * Read the EEPROM for the current default LED configuration. If the 1733 * LED configuration is not valid, set to a valid LED configuration. 1734 **/ 1735s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1736{ 1737 s32 ret_val; 1738 1739 DEBUGFUNC("e1000_valid_led_default_generic"); 1740 1741 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1742 if (ret_val) { 1743 DEBUGOUT("NVM Read Error\n"); 1744 goto out; 1745 } 1746 1747 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1748 *data = ID_LED_DEFAULT; 1749 1750out: 1751 return ret_val; 1752} 1753 1754/** 1755 * e1000_id_led_init_generic - 1756 * @hw: pointer to the HW structure 1757 * 1758 **/ 1759s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1760{ 1761 struct e1000_mac_info *mac = &hw->mac; 1762 s32 ret_val; 1763 const u32 ledctl_mask = 0x000000FF; 1764 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1765 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1766 u16 data, i, temp; 1767 const u16 led_mask = 0x0F; 1768 1769 DEBUGFUNC("e1000_id_led_init_generic"); 1770 1771 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1772 if (ret_val) 1773 goto out; 1774 1775 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1776 mac->ledctl_mode1 = mac->ledctl_default; 1777 mac->ledctl_mode2 = mac->ledctl_default; 1778 1779 for (i = 0; i < 4; i++) { 1780 temp = (data >> (i << 2)) & led_mask; 1781 switch (temp) { 1782 case ID_LED_ON1_DEF2: 1783 case ID_LED_ON1_ON2: 1784 case ID_LED_ON1_OFF2: 1785 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1786 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1787 break; 1788 case ID_LED_OFF1_DEF2: 1789 case ID_LED_OFF1_ON2: 1790 case ID_LED_OFF1_OFF2: 1791 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1792 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1793 break; 1794 default: 1795 /* Do nothing */ 1796 break; 1797 } 1798 switch (temp) { 1799 case ID_LED_DEF1_ON2: 1800 case ID_LED_ON1_ON2: 1801 case ID_LED_OFF1_ON2: 1802 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1803 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1804 break; 1805 case ID_LED_DEF1_OFF2: 1806 case ID_LED_ON1_OFF2: 1807 case ID_LED_OFF1_OFF2: 1808 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1809 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1810 break; 1811 default: 1812 /* Do nothing */ 1813 break; 1814 } 1815 } 1816 1817out: 1818 return ret_val; 1819} 1820 1821/** 1822 * e1000_setup_led_generic - Configures SW controllable LED 1823 * @hw: pointer to the HW structure 1824 * 1825 * This prepares the SW controllable LED for use and saves the current state 1826 * of the LED so it can be later restored. 1827 **/ 1828s32 e1000_setup_led_generic(struct e1000_hw *hw) 1829{ 1830 u32 ledctl; 1831 s32 ret_val = E1000_SUCCESS; 1832 1833 DEBUGFUNC("e1000_setup_led_generic"); 1834 1835 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1836 ret_val = -E1000_ERR_CONFIG; 1837 goto out; 1838 } 1839 1840 if (hw->phy.media_type == e1000_media_type_fiber) { 1841 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1842 hw->mac.ledctl_default = ledctl; 1843 /* Turn off LED0 */ 1844 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1845 E1000_LEDCTL_LED0_MODE_MASK); 1846 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1847 E1000_LEDCTL_LED0_MODE_SHIFT); 1848 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1849 } else if (hw->phy.media_type == e1000_media_type_copper) { 1850 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1851 } 1852 1853out: 1854 return ret_val; 1855} 1856 1857/** 1858 * e1000_cleanup_led_generic - Set LED config to default operation 1859 * @hw: pointer to the HW structure 1860 * 1861 * Remove the current LED configuration and set the LED configuration 1862 * to the default value, saved from the EEPROM. 1863 **/ 1864s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1865{ 1866 DEBUGFUNC("e1000_cleanup_led_generic"); 1867 1868 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1869 return E1000_SUCCESS; 1870} 1871 1872/** 1873 * e1000_blink_led_generic - Blink LED 1874 * @hw: pointer to the HW structure 1875 * 1876 * Blink the LEDs which are set to be on. 1877 **/ 1878s32 e1000_blink_led_generic(struct e1000_hw *hw) 1879{ 1880 u32 ledctl_blink = 0; 1881 u32 i; 1882 1883 DEBUGFUNC("e1000_blink_led_generic"); 1884 1885 if (hw->phy.media_type == e1000_media_type_fiber) { 1886 /* always blink LED0 for PCI-E fiber */ 1887 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1888 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1889 } else { 1890 /* 1891 * set the blink bit for each LED that's "on" (0x0E) 1892 * in ledctl_mode2 1893 */ 1894 ledctl_blink = hw->mac.ledctl_mode2; 1895 for (i = 0; i < 4; i++) 1896 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1897 E1000_LEDCTL_MODE_LED_ON) 1898 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1899 (i * 8)); 1900 } 1901 1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1903 1904 return E1000_SUCCESS; 1905} 1906 1907/** 1908 * e1000_led_on_generic - Turn LED on 1909 * @hw: pointer to the HW structure 1910 * 1911 * Turn LED on. 1912 **/ 1913s32 e1000_led_on_generic(struct e1000_hw *hw) 1914{ 1915 u32 ctrl; 1916 1917 DEBUGFUNC("e1000_led_on_generic"); 1918 1919 switch (hw->phy.media_type) { 1920 case e1000_media_type_fiber: 1921 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1922 ctrl &= ~E1000_CTRL_SWDPIN0; 1923 ctrl |= E1000_CTRL_SWDPIO0; 1924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1925 break; 1926 case e1000_media_type_copper: 1927 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1928 break; 1929 default: 1930 break; 1931 } 1932 1933 return E1000_SUCCESS; 1934} 1935 1936/** 1937 * e1000_led_off_generic - Turn LED off 1938 * @hw: pointer to the HW structure 1939 * 1940 * Turn LED off. 1941 **/ 1942s32 e1000_led_off_generic(struct e1000_hw *hw) 1943{ 1944 u32 ctrl; 1945 1946 DEBUGFUNC("e1000_led_off_generic"); 1947 1948 switch (hw->phy.media_type) { 1949 case e1000_media_type_fiber: 1950 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1951 ctrl |= E1000_CTRL_SWDPIN0; 1952 ctrl |= E1000_CTRL_SWDPIO0; 1953 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1954 break; 1955 case e1000_media_type_copper: 1956 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1957 break; 1958 default: 1959 break; 1960 } 1961 1962 return E1000_SUCCESS; 1963} 1964 1965/** 1966 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1967 * @hw: pointer to the HW structure 1968 * @no_snoop: bitmap of snoop events 1969 * 1970 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1971 **/ 1972void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1973{ 1974 u32 gcr; 1975 1976 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1977 1978 if (hw->bus.type != e1000_bus_type_pci_express) 1979 goto out; 1980 1981 if (no_snoop) { 1982 gcr = E1000_READ_REG(hw, E1000_GCR); 1983 gcr &= ~(PCIE_NO_SNOOP_ALL); 1984 gcr |= no_snoop; 1985 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1986 } 1987out: 1988 return; 1989} 1990 1991/** 1992 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1993 * @hw: pointer to the HW structure 1994 * 1995 * Returns E1000_SUCCESS if successful, else returns -10 1996 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1997 * the master requests to be disabled. 1998 * 1999 * Disables PCI-Express master access and verifies there are no pending 2000 * requests. 2001 **/ 2002s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2003{ 2004 u32 ctrl; 2005 s32 timeout = MASTER_DISABLE_TIMEOUT; 2006 s32 ret_val = E1000_SUCCESS; 2007 2008 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2009 2010 if (hw->bus.type != e1000_bus_type_pci_express) 2011 goto out; 2012 2013 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2014 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2015 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2016 2017 while (timeout) { 2018 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2019 E1000_STATUS_GIO_MASTER_ENABLE)) 2020 break; 2021 usec_delay(100); 2022 timeout--; 2023 } 2024 2025 if (!timeout) { 2026 DEBUGOUT("Master requests are pending.\n"); 2027 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2028 } 2029 2030out: 2031 return ret_val; 2032} 2033 2034/** 2035 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2036 * @hw: pointer to the HW structure 2037 * 2038 * Reset the Adaptive Interframe Spacing throttle to default values. 2039 **/ 2040void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2041{ 2042 struct e1000_mac_info *mac = &hw->mac; 2043 2044 DEBUGFUNC("e1000_reset_adaptive_generic"); 2045 2046 if (!mac->adaptive_ifs) { 2047 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2048 goto out; 2049 } 2050 2051 mac->current_ifs_val = 0; 2052 mac->ifs_min_val = IFS_MIN; 2053 mac->ifs_max_val = IFS_MAX; 2054 mac->ifs_step_size = IFS_STEP; 2055 mac->ifs_ratio = IFS_RATIO; 2056 2057 mac->in_ifs_mode = FALSE; 2058 E1000_WRITE_REG(hw, E1000_AIT, 0); 2059out: 2060 return; 2061} 2062 2063/** 2064 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2065 * @hw: pointer to the HW structure 2066 * 2067 * Update the Adaptive Interframe Spacing Throttle value based on the 2068 * time between transmitted packets and time between collisions. 2069 **/ 2070void e1000_update_adaptive_generic(struct e1000_hw *hw) 2071{ 2072 struct e1000_mac_info *mac = &hw->mac; 2073 2074 DEBUGFUNC("e1000_update_adaptive_generic"); 2075 2076 if (!mac->adaptive_ifs) { 2077 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2078 goto out; 2079 } 2080 2081 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2082 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2083 mac->in_ifs_mode = TRUE; 2084 if (mac->current_ifs_val < mac->ifs_max_val) { 2085 if (!mac->current_ifs_val) 2086 mac->current_ifs_val = mac->ifs_min_val; 2087 else 2088 mac->current_ifs_val += 2089 mac->ifs_step_size; 2090 E1000_WRITE_REG(hw, E1000_AIT, 2091 mac->current_ifs_val); 2092 } 2093 } 2094 } else { 2095 if (mac->in_ifs_mode && 2096 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2097 mac->current_ifs_val = 0; 2098 mac->in_ifs_mode = FALSE; 2099 E1000_WRITE_REG(hw, E1000_AIT, 0); 2100 } 2101 } 2102out: 2103 return; 2104} 2105 2106/** 2107 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2108 * @hw: pointer to the HW structure 2109 * 2110 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2111 * set, which is forced to MDI mode only. 2112 **/ 2113static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2114{ 2115 s32 ret_val = E1000_SUCCESS; 2116 2117 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2118 2119 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2120 DEBUGOUT("Invalid MDI setting detected\n"); 2121 hw->phy.mdix = 1; 2122 ret_val = -E1000_ERR_CONFIG; 2123 goto out; 2124 } 2125 2126out: 2127 return ret_val; 2128} 2129 2130/** 2131 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2132 * @hw: pointer to the HW structure 2133 * @reg: 32bit register offset such as E1000_SCTL 2134 * @offset: register offset to write to 2135 * @data: data to write at register offset 2136 * 2137 * Writes an address/data control type register. There are several of these 2138 * and they all have the format address << 8 | data and bit 31 is polled for 2139 * completion. 2140 **/ 2141s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2142 u32 offset, u8 data) 2143{ 2144 u32 i, regvalue = 0; 2145 s32 ret_val = E1000_SUCCESS; 2146 2147 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2148 2149 /* Set up the address and data */ 2150 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2151 E1000_WRITE_REG(hw, reg, regvalue); 2152 2153 /* Poll the ready bit to see if the MDI read completed */ 2154 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2155 usec_delay(5); 2156 regvalue = E1000_READ_REG(hw, reg); 2157 if (regvalue & E1000_GEN_CTL_READY) 2158 break; 2159 } 2160 if (!(regvalue & E1000_GEN_CTL_READY)) { 2161 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2162 ret_val = -E1000_ERR_PHY; 2163 goto out; 2164 } 2165 2166out: 2167 return ret_val; 2168} 2169