e1000_mac.c revision 218548
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 218548 2011-02-11 09:58:38Z bz $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.rar_set = e1000_rar_set_generic; 82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83} 84 85/** 86 * e1000_null_ops_generic - No-op function, returns 0 87 * @hw: pointer to the HW structure 88 **/ 89s32 e1000_null_ops_generic(struct e1000_hw *hw) 90{ 91 DEBUGFUNC("e1000_null_ops_generic"); 92 return E1000_SUCCESS; 93} 94 95/** 96 * e1000_null_mac_generic - No-op function, return void 97 * @hw: pointer to the HW structure 98 **/ 99void e1000_null_mac_generic(struct e1000_hw *hw) 100{ 101 DEBUGFUNC("e1000_null_mac_generic"); 102 return; 103} 104 105/** 106 * e1000_null_link_info - No-op function, return 0 107 * @hw: pointer to the HW structure 108 **/ 109s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110{ 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113} 114 115/** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119bool e1000_null_mng_mode(struct e1000_hw *hw) 120{ 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123} 124 125/** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130{ 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133} 134 135/** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140{ 141 DEBUGFUNC("e1000_null_write_vfta"); 142 return; 143} 144 145/** 146 * e1000_null_rar_set - No-op function, return void 147 * @hw: pointer to the HW structure 148 **/ 149void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150{ 151 DEBUGFUNC("e1000_null_rar_set"); 152 return; 153} 154 155/** 156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157 * @hw: pointer to the HW structure 158 * 159 * Determines and stores the system bus information for a particular 160 * network interface. The following bus information is determined and stored: 161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162 **/ 163s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164{ 165 struct e1000_mac_info *mac = &hw->mac; 166 struct e1000_bus_info *bus = &hw->bus; 167 u32 status = E1000_READ_REG(hw, E1000_STATUS); 168 s32 ret_val = E1000_SUCCESS; 169 170 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171 172 /* PCI or PCI-X? */ 173 bus->type = (status & E1000_STATUS_PCIX_MODE) 174 ? e1000_bus_type_pcix 175 : e1000_bus_type_pci; 176 177 /* Bus speed */ 178 if (bus->type == e1000_bus_type_pci) { 179 bus->speed = (status & E1000_STATUS_PCI66) 180 ? e1000_bus_speed_66 181 : e1000_bus_speed_33; 182 } else { 183 switch (status & E1000_STATUS_PCIX_SPEED) { 184 case E1000_STATUS_PCIX_SPEED_66: 185 bus->speed = e1000_bus_speed_66; 186 break; 187 case E1000_STATUS_PCIX_SPEED_100: 188 bus->speed = e1000_bus_speed_100; 189 break; 190 case E1000_STATUS_PCIX_SPEED_133: 191 bus->speed = e1000_bus_speed_133; 192 break; 193 default: 194 bus->speed = e1000_bus_speed_reserved; 195 break; 196 } 197 } 198 199 /* Bus width */ 200 bus->width = (status & E1000_STATUS_BUS64) 201 ? e1000_bus_width_64 202 : e1000_bus_width_32; 203 204 /* Which PCI(-X) function? */ 205 mac->ops.set_lan_id(hw); 206 207 return ret_val; 208} 209 210/** 211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212 * @hw: pointer to the HW structure 213 * 214 * Determines and stores the system bus information for a particular 215 * network interface. The following bus information is determined and stored: 216 * bus speed, bus width, type (PCIe), and PCIe function. 217 **/ 218s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219{ 220 struct e1000_mac_info *mac = &hw->mac; 221 struct e1000_bus_info *bus = &hw->bus; 222 s32 ret_val; 223 u16 pcie_link_status; 224 225 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226 227 bus->type = e1000_bus_type_pci_express; 228 229 ret_val = e1000_read_pcie_cap_reg(hw, 230 PCIE_LINK_STATUS, 231 &pcie_link_status); 232 if (ret_val) { 233 bus->width = e1000_bus_width_unknown; 234 bus->speed = e1000_bus_speed_unknown; 235 } else { 236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 237 case PCIE_LINK_SPEED_2500: 238 bus->speed = e1000_bus_speed_2500; 239 break; 240 case PCIE_LINK_SPEED_5000: 241 bus->speed = e1000_bus_speed_5000; 242 break; 243 default: 244 bus->speed = e1000_bus_speed_unknown; 245 break; 246 } 247 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> 250 PCIE_LINK_WIDTH_SHIFT); 251 } 252 253 mac->ops.set_lan_id(hw); 254 255 return E1000_SUCCESS; 256} 257 258/** 259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260 * 261 * @hw: pointer to the HW structure 262 * 263 * Determines the LAN function id by reading memory-mapped registers 264 * and swaps the port value if requested. 265 **/ 266static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267{ 268 struct e1000_bus_info *bus = &hw->bus; 269 u32 reg; 270 271 /* 272 * The status register reports the correct function number 273 * for the device regardless of function swap state. 274 */ 275 reg = E1000_READ_REG(hw, E1000_STATUS); 276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 277} 278 279/** 280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 281 * @hw: pointer to the HW structure 282 * 283 * Determines the LAN function id by reading PCI config space. 284 **/ 285void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 286{ 287 struct e1000_bus_info *bus = &hw->bus; 288 u16 pci_header_type; 289 u32 status; 290 291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 293 status = E1000_READ_REG(hw, E1000_STATUS); 294 bus->func = (status & E1000_STATUS_FUNC_MASK) 295 >> E1000_STATUS_FUNC_SHIFT; 296 } else { 297 bus->func = 0; 298 } 299} 300 301/** 302 * e1000_set_lan_id_single_port - Set LAN id for a single port device 303 * @hw: pointer to the HW structure 304 * 305 * Sets the LAN function id to zero for a single port device. 306 **/ 307void e1000_set_lan_id_single_port(struct e1000_hw *hw) 308{ 309 struct e1000_bus_info *bus = &hw->bus; 310 311 bus->func = 0; 312} 313 314/** 315 * e1000_clear_vfta_generic - Clear VLAN filter table 316 * @hw: pointer to the HW structure 317 * 318 * Clears the register array which contains the VLAN filter table by 319 * setting all the values to 0. 320 **/ 321void e1000_clear_vfta_generic(struct e1000_hw *hw) 322{ 323 u32 offset; 324 325 DEBUGFUNC("e1000_clear_vfta_generic"); 326 327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 329 E1000_WRITE_FLUSH(hw); 330 } 331} 332 333/** 334 * e1000_write_vfta_generic - Write value to VLAN filter table 335 * @hw: pointer to the HW structure 336 * @offset: register offset in VLAN filter table 337 * @value: register value written to VLAN filter table 338 * 339 * Writes value at the given offset in the register array which stores 340 * the VLAN filter table. 341 **/ 342void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 343{ 344 DEBUGFUNC("e1000_write_vfta_generic"); 345 346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 347 E1000_WRITE_FLUSH(hw); 348} 349 350/** 351 * e1000_init_rx_addrs_generic - Initialize receive address's 352 * @hw: pointer to the HW structure 353 * @rar_count: receive address registers 354 * 355 * Setups the receive address registers by setting the base receive address 356 * register to the devices MAC address and clearing all the other receive 357 * address registers to 0. 358 **/ 359void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 360{ 361 u32 i; 362 u8 mac_addr[ETH_ADDR_LEN] = {0}; 363 364 DEBUGFUNC("e1000_init_rx_addrs_generic"); 365 366 /* Setup the receive address */ 367 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 368 369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 370 371 /* Zero out the other (rar_entry_count - 1) receive addresses */ 372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 373 for (i = 1; i < rar_count; i++) 374 hw->mac.ops.rar_set(hw, mac_addr, i); 375} 376 377/** 378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 379 * @hw: pointer to the HW structure 380 * 381 * Checks the nvm for an alternate MAC address. An alternate MAC address 382 * can be setup by pre-boot software and must be treated like a permanent 383 * address and must override the actual permanent MAC address. If an 384 * alternate MAC address is found it is programmed into RAR0, replacing 385 * the permanent address that was installed into RAR0 by the Si on reset. 386 * This function will return SUCCESS unless it encounters an error while 387 * reading the EEPROM. 388 **/ 389s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 390{ 391 u32 i; 392 s32 ret_val = E1000_SUCCESS; 393 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 394 u8 alt_mac_addr[ETH_ADDR_LEN]; 395 396 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 397 398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 399 if (ret_val) 400 goto out; 401 402 if (!(nvm_data & NVM_COMPAT_LOM)) 403 goto out; 404 405 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 406 &nvm_alt_mac_addr_offset); 407 if (ret_val) { 408 DEBUGOUT("NVM Read Error\n"); 409 goto out; 410 } 411 412 if (nvm_alt_mac_addr_offset == 0xFFFF) { 413 /* There is no Alternate MAC Address */ 414 goto out; 415 } 416 417 if (hw->bus.func == E1000_FUNC_1) 418 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 419 if (hw->bus.func == E1000_FUNC_2) 420 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 421 422 if (hw->bus.func == E1000_FUNC_3) 423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 424 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 425 offset = nvm_alt_mac_addr_offset + (i >> 1); 426 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 427 if (ret_val) { 428 DEBUGOUT("NVM Read Error\n"); 429 goto out; 430 } 431 432 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 433 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 434 } 435 436 /* if multicast bit is set, the alternate address will not be used */ 437 if (alt_mac_addr[0] & 0x01) { 438 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 439 goto out; 440 } 441 442 /* 443 * We have a valid alternate MAC address, and we want to treat it the 444 * same as the normal permanent MAC address stored by the HW into the 445 * RAR. Do this by mapping this address into RAR0. 446 */ 447 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 448 449out: 450 return ret_val; 451} 452 453/** 454 * e1000_rar_set_generic - Set receive address register 455 * @hw: pointer to the HW structure 456 * @addr: pointer to the receive address 457 * @index: receive address array register 458 * 459 * Sets the receive address array register at index to the address passed 460 * in by addr. 461 **/ 462void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 463{ 464 u32 rar_low, rar_high; 465 466 DEBUGFUNC("e1000_rar_set_generic"); 467 468 /* 469 * HW expects these in little endian so we reverse the byte order 470 * from network order (big endian) to little endian 471 */ 472 rar_low = ((u32) addr[0] | 473 ((u32) addr[1] << 8) | 474 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 475 476 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 477 478 /* If MAC address zero, no need to set the AV bit */ 479 if (rar_low || rar_high) 480 rar_high |= E1000_RAH_AV; 481 482 /* 483 * Some bridges will combine consecutive 32-bit writes into 484 * a single burst write, which will malfunction on some parts. 485 * The flushes avoid this. 486 */ 487 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 488 E1000_WRITE_FLUSH(hw); 489 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 490 E1000_WRITE_FLUSH(hw); 491} 492 493/** 494 * e1000_update_mc_addr_list_generic - Update Multicast addresses 495 * @hw: pointer to the HW structure 496 * @mc_addr_list: array of multicast addresses to program 497 * @mc_addr_count: number of multicast addresses to program 498 * 499 * Updates entire Multicast Table Array. 500 * The caller must have a packed mc_addr_list of multicast addresses. 501 **/ 502void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 503 u8 *mc_addr_list, u32 mc_addr_count) 504{ 505 u32 hash_value, hash_bit, hash_reg; 506 int i; 507 508 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 509 510 /* clear mta_shadow */ 511 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 512 513 /* update mta_shadow from mc_addr_list */ 514 for (i = 0; (u32) i < mc_addr_count; i++) { 515 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 516 517 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 518 hash_bit = hash_value & 0x1F; 519 520 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 521 mc_addr_list += (ETH_ADDR_LEN); 522 } 523 524 /* replace the entire MTA table */ 525 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 526 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 527 E1000_WRITE_FLUSH(hw); 528} 529 530/** 531 * e1000_hash_mc_addr_generic - Generate a multicast hash value 532 * @hw: pointer to the HW structure 533 * @mc_addr: pointer to a multicast address 534 * 535 * Generates a multicast address hash value which is used to determine 536 * the multicast filter table array address and new table value. 537 **/ 538u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 539{ 540 u32 hash_value, hash_mask; 541 u8 bit_shift = 0; 542 543 DEBUGFUNC("e1000_hash_mc_addr_generic"); 544 545 /* Register count multiplied by bits per register */ 546 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 547 548 /* 549 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 550 * where 0xFF would still fall within the hash mask. 551 */ 552 while (hash_mask >> bit_shift != 0xFF) 553 bit_shift++; 554 555 /* 556 * The portion of the address that is used for the hash table 557 * is determined by the mc_filter_type setting. 558 * The algorithm is such that there is a total of 8 bits of shifting. 559 * The bit_shift for a mc_filter_type of 0 represents the number of 560 * left-shifts where the MSB of mc_addr[5] would still fall within 561 * the hash_mask. Case 0 does this exactly. Since there are a total 562 * of 8 bits of shifting, then mc_addr[4] will shift right the 563 * remaining number of bits. Thus 8 - bit_shift. The rest of the 564 * cases are a variation of this algorithm...essentially raising the 565 * number of bits to shift mc_addr[5] left, while still keeping the 566 * 8-bit shifting total. 567 * 568 * For example, given the following Destination MAC Address and an 569 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 570 * we can see that the bit_shift for case 0 is 4. These are the hash 571 * values resulting from each mc_filter_type... 572 * [0] [1] [2] [3] [4] [5] 573 * 01 AA 00 12 34 56 574 * LSB MSB 575 * 576 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 577 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 578 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 579 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 580 */ 581 switch (hw->mac.mc_filter_type) { 582 default: 583 case 0: 584 break; 585 case 1: 586 bit_shift += 1; 587 break; 588 case 2: 589 bit_shift += 2; 590 break; 591 case 3: 592 bit_shift += 4; 593 break; 594 } 595 596 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 597 (((u16) mc_addr[5]) << bit_shift))); 598 599 return hash_value; 600} 601 602/** 603 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 604 * @hw: pointer to the HW structure 605 * 606 * In certain situations, a system BIOS may report that the PCIx maximum 607 * memory read byte count (MMRBC) value is higher than than the actual 608 * value. We check the PCIx command register with the current PCIx status 609 * register. 610 **/ 611void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 612{ 613 u16 cmd_mmrbc; 614 u16 pcix_cmd; 615 u16 pcix_stat_hi_word; 616 u16 stat_mmrbc; 617 618 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 619 620 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 621 if (hw->bus.type != e1000_bus_type_pcix) 622 return; 623 624 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 625 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 626 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 627 PCIX_COMMAND_MMRBC_SHIFT; 628 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 629 PCIX_STATUS_HI_MMRBC_SHIFT; 630 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 631 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 632 if (cmd_mmrbc > stat_mmrbc) { 633 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 634 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 635 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 636 } 637} 638 639/** 640 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 641 * @hw: pointer to the HW structure 642 * 643 * Clears the base hardware counters by reading the counter registers. 644 **/ 645void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 646{ 647 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 648 649 E1000_READ_REG(hw, E1000_CRCERRS); 650 E1000_READ_REG(hw, E1000_SYMERRS); 651 E1000_READ_REG(hw, E1000_MPC); 652 E1000_READ_REG(hw, E1000_SCC); 653 E1000_READ_REG(hw, E1000_ECOL); 654 E1000_READ_REG(hw, E1000_MCC); 655 E1000_READ_REG(hw, E1000_LATECOL); 656 E1000_READ_REG(hw, E1000_COLC); 657 E1000_READ_REG(hw, E1000_DC); 658 E1000_READ_REG(hw, E1000_SEC); 659 E1000_READ_REG(hw, E1000_RLEC); 660 E1000_READ_REG(hw, E1000_XONRXC); 661 E1000_READ_REG(hw, E1000_XONTXC); 662 E1000_READ_REG(hw, E1000_XOFFRXC); 663 E1000_READ_REG(hw, E1000_XOFFTXC); 664 E1000_READ_REG(hw, E1000_FCRUC); 665 E1000_READ_REG(hw, E1000_GPRC); 666 E1000_READ_REG(hw, E1000_BPRC); 667 E1000_READ_REG(hw, E1000_MPRC); 668 E1000_READ_REG(hw, E1000_GPTC); 669 E1000_READ_REG(hw, E1000_GORCL); 670 E1000_READ_REG(hw, E1000_GORCH); 671 E1000_READ_REG(hw, E1000_GOTCL); 672 E1000_READ_REG(hw, E1000_GOTCH); 673 E1000_READ_REG(hw, E1000_RNBC); 674 E1000_READ_REG(hw, E1000_RUC); 675 E1000_READ_REG(hw, E1000_RFC); 676 E1000_READ_REG(hw, E1000_ROC); 677 E1000_READ_REG(hw, E1000_RJC); 678 E1000_READ_REG(hw, E1000_TORL); 679 E1000_READ_REG(hw, E1000_TORH); 680 E1000_READ_REG(hw, E1000_TOTL); 681 E1000_READ_REG(hw, E1000_TOTH); 682 E1000_READ_REG(hw, E1000_TPR); 683 E1000_READ_REG(hw, E1000_TPT); 684 E1000_READ_REG(hw, E1000_MPTC); 685 E1000_READ_REG(hw, E1000_BPTC); 686} 687 688/** 689 * e1000_check_for_copper_link_generic - Check for link (Copper) 690 * @hw: pointer to the HW structure 691 * 692 * Checks to see of the link status of the hardware has changed. If a 693 * change in link status has been detected, then we read the PHY registers 694 * to get the current speed/duplex if link exists. 695 **/ 696s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 697{ 698 struct e1000_mac_info *mac = &hw->mac; 699 s32 ret_val; 700 bool link; 701 702 DEBUGFUNC("e1000_check_for_copper_link"); 703 704 /* 705 * We only want to go out to the PHY registers to see if Auto-Neg 706 * has completed and/or if our link status has changed. The 707 * get_link_status flag is set upon receiving a Link Status 708 * Change or Rx Sequence Error interrupt. 709 */ 710 if (!mac->get_link_status) { 711 ret_val = E1000_SUCCESS; 712 goto out; 713 } 714 715 /* 716 * First we want to see if the MII Status Register reports 717 * link. If so, then we want to get the current speed/duplex 718 * of the PHY. 719 */ 720 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 721 if (ret_val) 722 goto out; 723 724 if (!link) 725 goto out; /* No link detected */ 726 727 mac->get_link_status = FALSE; 728 729 /* 730 * Check if there was DownShift, must be checked 731 * immediately after link-up 732 */ 733 e1000_check_downshift_generic(hw); 734 735 /* 736 * If we are forcing speed/duplex, then we simply return since 737 * we have already determined whether we have link or not. 738 */ 739 if (!mac->autoneg) { 740 ret_val = -E1000_ERR_CONFIG; 741 goto out; 742 } 743 744 /* 745 * Auto-Neg is enabled. Auto Speed Detection takes care 746 * of MAC speed/duplex configuration. So we only need to 747 * configure Collision Distance in the MAC. 748 */ 749 mac->ops.config_collision_dist(hw); 750 751 /* 752 * Configure Flow Control now that Auto-Neg has completed. 753 * First, we need to restore the desired flow control 754 * settings because we may have had to re-autoneg with a 755 * different link partner. 756 */ 757 ret_val = e1000_config_fc_after_link_up_generic(hw); 758 if (ret_val) 759 DEBUGOUT("Error configuring flow control\n"); 760 761out: 762 return ret_val; 763} 764 765/** 766 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 767 * @hw: pointer to the HW structure 768 * 769 * Checks for link up on the hardware. If link is not up and we have 770 * a signal, then we need to force link up. 771 **/ 772s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 773{ 774 struct e1000_mac_info *mac = &hw->mac; 775 u32 rxcw; 776 u32 ctrl; 777 u32 status; 778 s32 ret_val = E1000_SUCCESS; 779 780 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 781 782 ctrl = E1000_READ_REG(hw, E1000_CTRL); 783 status = E1000_READ_REG(hw, E1000_STATUS); 784 rxcw = E1000_READ_REG(hw, E1000_RXCW); 785 786 /* 787 * If we don't have link (auto-negotiation failed or link partner 788 * cannot auto-negotiate), the cable is plugged in (we have signal), 789 * and our link partner is not trying to auto-negotiate with us (we 790 * are receiving idles or data), we need to force link up. We also 791 * need to give auto-negotiation time to complete, in case the cable 792 * was just plugged in. The autoneg_failed flag does this. 793 */ 794 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 795 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 796 (!(rxcw & E1000_RXCW_C))) { 797 if (mac->autoneg_failed == 0) { 798 mac->autoneg_failed = 1; 799 goto out; 800 } 801 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 802 803 /* Disable auto-negotiation in the TXCW register */ 804 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 805 806 /* Force link-up and also force full-duplex. */ 807 ctrl = E1000_READ_REG(hw, E1000_CTRL); 808 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 809 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 810 811 /* Configure Flow Control after forcing link up. */ 812 ret_val = e1000_config_fc_after_link_up_generic(hw); 813 if (ret_val) { 814 DEBUGOUT("Error configuring flow control\n"); 815 goto out; 816 } 817 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 818 /* 819 * If we are forcing link and we are receiving /C/ ordered 820 * sets, re-enable auto-negotiation in the TXCW register 821 * and disable forced link in the Device Control register 822 * in an attempt to auto-negotiate with our link partner. 823 */ 824 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 827 828 mac->serdes_has_link = TRUE; 829 } 830 831out: 832 return ret_val; 833} 834 835/** 836 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 837 * @hw: pointer to the HW structure 838 * 839 * Checks for link up on the hardware. If link is not up and we have 840 * a signal, then we need to force link up. 841 **/ 842s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 843{ 844 struct e1000_mac_info *mac = &hw->mac; 845 u32 rxcw; 846 u32 ctrl; 847 u32 status; 848 s32 ret_val = E1000_SUCCESS; 849 850 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 851 852 ctrl = E1000_READ_REG(hw, E1000_CTRL); 853 status = E1000_READ_REG(hw, E1000_STATUS); 854 rxcw = E1000_READ_REG(hw, E1000_RXCW); 855 856 /* 857 * If we don't have link (auto-negotiation failed or link partner 858 * cannot auto-negotiate), and our link partner is not trying to 859 * auto-negotiate with us (we are receiving idles or data), 860 * we need to force link up. We also need to give auto-negotiation 861 * time to complete. 862 */ 863 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 864 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 865 if (mac->autoneg_failed == 0) { 866 mac->autoneg_failed = 1; 867 goto out; 868 } 869 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 870 871 /* Disable auto-negotiation in the TXCW register */ 872 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 873 874 /* Force link-up and also force full-duplex. */ 875 ctrl = E1000_READ_REG(hw, E1000_CTRL); 876 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 877 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 878 879 /* Configure Flow Control after forcing link up. */ 880 ret_val = e1000_config_fc_after_link_up_generic(hw); 881 if (ret_val) { 882 DEBUGOUT("Error configuring flow control\n"); 883 goto out; 884 } 885 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 886 /* 887 * If we are forcing link and we are receiving /C/ ordered 888 * sets, re-enable auto-negotiation in the TXCW register 889 * and disable forced link in the Device Control register 890 * in an attempt to auto-negotiate with our link partner. 891 */ 892 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 893 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 894 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 895 896 mac->serdes_has_link = TRUE; 897 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 898 /* 899 * If we force link for non-auto-negotiation switch, check 900 * link status based on MAC synchronization for internal 901 * serdes media type. 902 */ 903 /* SYNCH bit and IV bit are sticky. */ 904 usec_delay(10); 905 rxcw = E1000_READ_REG(hw, E1000_RXCW); 906 if (rxcw & E1000_RXCW_SYNCH) { 907 if (!(rxcw & E1000_RXCW_IV)) { 908 mac->serdes_has_link = TRUE; 909 DEBUGOUT("SERDES: Link up - forced.\n"); 910 } 911 } else { 912 mac->serdes_has_link = FALSE; 913 DEBUGOUT("SERDES: Link down - force failed.\n"); 914 } 915 } 916 917 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 918 status = E1000_READ_REG(hw, E1000_STATUS); 919 if (status & E1000_STATUS_LU) { 920 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 921 usec_delay(10); 922 rxcw = E1000_READ_REG(hw, E1000_RXCW); 923 if (rxcw & E1000_RXCW_SYNCH) { 924 if (!(rxcw & E1000_RXCW_IV)) { 925 mac->serdes_has_link = TRUE; 926 DEBUGOUT("SERDES: Link up - autoneg " 927 "completed sucessfully.\n"); 928 } else { 929 mac->serdes_has_link = FALSE; 930 DEBUGOUT("SERDES: Link down - invalid" 931 "codewords detected in autoneg.\n"); 932 } 933 } else { 934 mac->serdes_has_link = FALSE; 935 DEBUGOUT("SERDES: Link down - no sync.\n"); 936 } 937 } else { 938 mac->serdes_has_link = FALSE; 939 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 940 } 941 } 942 943out: 944 return ret_val; 945} 946 947/** 948 * e1000_setup_link_generic - Setup flow control and link settings 949 * @hw: pointer to the HW structure 950 * 951 * Determines which flow control settings to use, then configures flow 952 * control. Calls the appropriate media-specific link configuration 953 * function. Assuming the adapter has a valid link partner, a valid link 954 * should be established. Assumes the hardware has previously been reset 955 * and the transmitter and receiver are not enabled. 956 **/ 957s32 e1000_setup_link_generic(struct e1000_hw *hw) 958{ 959 s32 ret_val = E1000_SUCCESS; 960 961 DEBUGFUNC("e1000_setup_link_generic"); 962 963 /* 964 * In the case of the phy reset being blocked, we already have a link. 965 * We do not need to set it up again. 966 */ 967 if (e1000_check_reset_block(hw)) 968 goto out; 969 970 /* 971 * If requested flow control is set to default, set flow control 972 * based on the EEPROM flow control settings. 973 */ 974 if (hw->fc.requested_mode == e1000_fc_default) { 975 ret_val = e1000_set_default_fc_generic(hw); 976 if (ret_val) 977 goto out; 978 } 979 980 /* 981 * Save off the requested flow control mode for use later. Depending 982 * on the link partner's capabilities, we may or may not use this mode. 983 */ 984 hw->fc.current_mode = hw->fc.requested_mode; 985 986 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 987 hw->fc.current_mode); 988 989 /* Call the necessary media_type subroutine to configure the link. */ 990 ret_val = hw->mac.ops.setup_physical_interface(hw); 991 if (ret_val) 992 goto out; 993 994 /* 995 * Initialize the flow control address, type, and PAUSE timer 996 * registers to their default values. This is done even if flow 997 * control is disabled, because it does not hurt anything to 998 * initialize these registers. 999 */ 1000 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1001 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1002 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1003 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1004 1005 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1006 1007 ret_val = e1000_set_fc_watermarks_generic(hw); 1008 1009out: 1010 return ret_val; 1011} 1012 1013/** 1014 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1015 * @hw: pointer to the HW structure 1016 * 1017 * Configures collision distance and flow control for fiber and serdes 1018 * links. Upon successful setup, poll for link. 1019 **/ 1020s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1021{ 1022 struct e1000_mac_info *mac = &hw->mac; 1023 u32 ctrl; 1024 s32 ret_val = E1000_SUCCESS; 1025 1026 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1027 1028 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1029 1030 /* Take the link out of reset */ 1031 ctrl &= ~E1000_CTRL_LRST; 1032 1033 mac->ops.config_collision_dist(hw); 1034 1035 ret_val = e1000_commit_fc_settings_generic(hw); 1036 if (ret_val) 1037 goto out; 1038 1039 /* 1040 * Since auto-negotiation is enabled, take the link out of reset (the 1041 * link will be in reset, because we previously reset the chip). This 1042 * will restart auto-negotiation. If auto-negotiation is successful 1043 * then the link-up status bit will be set and the flow control enable 1044 * bits (RFCE and TFCE) will be set according to their negotiated value. 1045 */ 1046 DEBUGOUT("Auto-negotiation enabled\n"); 1047 1048 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1049 E1000_WRITE_FLUSH(hw); 1050 msec_delay(1); 1051 1052 /* 1053 * For these adapters, the SW definable pin 1 is set when the optics 1054 * detect a signal. If we have a signal, then poll for a "Link-Up" 1055 * indication. 1056 */ 1057 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1058 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1059 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1060 } else { 1061 DEBUGOUT("No signal detected\n"); 1062 } 1063 1064out: 1065 return ret_val; 1066} 1067 1068/** 1069 * e1000_config_collision_dist_generic - Configure collision distance 1070 * @hw: pointer to the HW structure 1071 * 1072 * Configures the collision distance to the default value and is used 1073 * during link setup. 1074 **/ 1075void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1076{ 1077 u32 tctl; 1078 1079 DEBUGFUNC("e1000_config_collision_dist_generic"); 1080 1081 tctl = E1000_READ_REG(hw, E1000_TCTL); 1082 1083 tctl &= ~E1000_TCTL_COLD; 1084 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1085 1086 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1087 E1000_WRITE_FLUSH(hw); 1088} 1089 1090/** 1091 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1092 * @hw: pointer to the HW structure 1093 * 1094 * Polls for link up by reading the status register, if link fails to come 1095 * up with auto-negotiation, then the link is forced if a signal is detected. 1096 **/ 1097s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1098{ 1099 struct e1000_mac_info *mac = &hw->mac; 1100 u32 i, status; 1101 s32 ret_val = E1000_SUCCESS; 1102 1103 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1104 1105 /* 1106 * If we have a signal (the cable is plugged in, or assumed TRUE for 1107 * serdes media) then poll for a "Link-Up" indication in the Device 1108 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1109 * seconds (Auto-negotiation should complete in less than 500 1110 * milliseconds even if the other end is doing it in SW). 1111 */ 1112 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1113 msec_delay(10); 1114 status = E1000_READ_REG(hw, E1000_STATUS); 1115 if (status & E1000_STATUS_LU) 1116 break; 1117 } 1118 if (i == FIBER_LINK_UP_LIMIT) { 1119 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1120 mac->autoneg_failed = 1; 1121 /* 1122 * AutoNeg failed to achieve a link, so we'll call 1123 * mac->check_for_link. This routine will force the 1124 * link up if we detect a signal. This will allow us to 1125 * communicate with non-autonegotiating link partners. 1126 */ 1127 ret_val = mac->ops.check_for_link(hw); 1128 if (ret_val) { 1129 DEBUGOUT("Error while checking for link\n"); 1130 goto out; 1131 } 1132 mac->autoneg_failed = 0; 1133 } else { 1134 mac->autoneg_failed = 0; 1135 DEBUGOUT("Valid Link Found\n"); 1136 } 1137 1138out: 1139 return ret_val; 1140} 1141 1142/** 1143 * e1000_commit_fc_settings_generic - Configure flow control 1144 * @hw: pointer to the HW structure 1145 * 1146 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1147 * base on the flow control settings in e1000_mac_info. 1148 **/ 1149s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1150{ 1151 struct e1000_mac_info *mac = &hw->mac; 1152 u32 txcw; 1153 s32 ret_val = E1000_SUCCESS; 1154 1155 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1156 1157 /* 1158 * Check for a software override of the flow control settings, and 1159 * setup the device accordingly. If auto-negotiation is enabled, then 1160 * software will have to set the "PAUSE" bits to the correct value in 1161 * the Transmit Config Word Register (TXCW) and re-start auto- 1162 * negotiation. However, if auto-negotiation is disabled, then 1163 * software will have to manually configure the two flow control enable 1164 * bits in the CTRL register. 1165 * 1166 * The possible values of the "fc" parameter are: 1167 * 0: Flow control is completely disabled 1168 * 1: Rx flow control is enabled (we can receive pause frames, 1169 * but not send pause frames). 1170 * 2: Tx flow control is enabled (we can send pause frames but we 1171 * do not support receiving pause frames). 1172 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1173 */ 1174 switch (hw->fc.current_mode) { 1175 case e1000_fc_none: 1176 /* Flow control completely disabled by a software over-ride. */ 1177 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1178 break; 1179 case e1000_fc_rx_pause: 1180 /* 1181 * Rx Flow control is enabled and Tx Flow control is disabled 1182 * by a software over-ride. Since there really isn't a way to 1183 * advertise that we are capable of Rx Pause ONLY, we will 1184 * advertise that we support both symmetric and asymmetric Rx 1185 * PAUSE. Later, we will disable the adapter's ability to send 1186 * PAUSE frames. 1187 */ 1188 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1189 break; 1190 case e1000_fc_tx_pause: 1191 /* 1192 * Tx Flow control is enabled, and Rx Flow control is disabled, 1193 * by a software over-ride. 1194 */ 1195 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1196 break; 1197 case e1000_fc_full: 1198 /* 1199 * Flow control (both Rx and Tx) is enabled by a software 1200 * over-ride. 1201 */ 1202 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1203 break; 1204 default: 1205 DEBUGOUT("Flow control param set incorrectly\n"); 1206 ret_val = -E1000_ERR_CONFIG; 1207 goto out; 1208 break; 1209 } 1210 1211 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1212 mac->txcw = txcw; 1213 1214out: 1215 return ret_val; 1216} 1217 1218/** 1219 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1220 * @hw: pointer to the HW structure 1221 * 1222 * Sets the flow control high/low threshold (watermark) registers. If 1223 * flow control XON frame transmission is enabled, then set XON frame 1224 * transmission as well. 1225 **/ 1226s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1227{ 1228 u32 fcrtl = 0, fcrth = 0; 1229 1230 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1231 1232 /* 1233 * Set the flow control receive threshold registers. Normally, 1234 * these registers will be set to a default threshold that may be 1235 * adjusted later by the driver's runtime code. However, if the 1236 * ability to transmit pause frames is not enabled, then these 1237 * registers will be set to 0. 1238 */ 1239 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1240 /* 1241 * We need to set up the Receive Threshold high and low water 1242 * marks as well as (optionally) enabling the transmission of 1243 * XON frames. 1244 */ 1245 fcrtl = hw->fc.low_water; 1246 if (hw->fc.send_xon) 1247 fcrtl |= E1000_FCRTL_XONE; 1248 1249 fcrth = hw->fc.high_water; 1250 } 1251 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1252 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1253 1254 return E1000_SUCCESS; 1255} 1256 1257/** 1258 * e1000_set_default_fc_generic - Set flow control default values 1259 * @hw: pointer to the HW structure 1260 * 1261 * Read the EEPROM for the default values for flow control and store the 1262 * values. 1263 **/ 1264s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1265{ 1266 s32 ret_val = E1000_SUCCESS; 1267 u16 nvm_data; 1268 1269 DEBUGFUNC("e1000_set_default_fc_generic"); 1270 1271 /* 1272 * Read and store word 0x0F of the EEPROM. This word contains bits 1273 * that determine the hardware's default PAUSE (flow control) mode, 1274 * a bit that determines whether the HW defaults to enabling or 1275 * disabling auto-negotiation, and the direction of the 1276 * SW defined pins. If there is no SW over-ride of the flow 1277 * control setting, then the variable hw->fc will 1278 * be initialized based on a value in the EEPROM. 1279 */ 1280 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1281 1282 if (ret_val) { 1283 DEBUGOUT("NVM Read Error\n"); 1284 goto out; 1285 } 1286 1287 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1288 hw->fc.requested_mode = e1000_fc_none; 1289 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1290 NVM_WORD0F_ASM_DIR) 1291 hw->fc.requested_mode = e1000_fc_tx_pause; 1292 else 1293 hw->fc.requested_mode = e1000_fc_full; 1294 1295out: 1296 return ret_val; 1297} 1298 1299/** 1300 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1301 * @hw: pointer to the HW structure 1302 * 1303 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1304 * device control register to reflect the adapter settings. TFCE and RFCE 1305 * need to be explicitly set by software when a copper PHY is used because 1306 * autonegotiation is managed by the PHY rather than the MAC. Software must 1307 * also configure these bits when link is forced on a fiber connection. 1308 **/ 1309s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1310{ 1311 u32 ctrl; 1312 s32 ret_val = E1000_SUCCESS; 1313 1314 DEBUGFUNC("e1000_force_mac_fc_generic"); 1315 1316 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1317 1318 /* 1319 * Because we didn't get link via the internal auto-negotiation 1320 * mechanism (we either forced link or we got link via PHY 1321 * auto-neg), we have to manually enable/disable transmit an 1322 * receive flow control. 1323 * 1324 * The "Case" statement below enables/disable flow control 1325 * according to the "hw->fc.current_mode" parameter. 1326 * 1327 * The possible values of the "fc" parameter are: 1328 * 0: Flow control is completely disabled 1329 * 1: Rx flow control is enabled (we can receive pause 1330 * frames but not send pause frames). 1331 * 2: Tx flow control is enabled (we can send pause frames 1332 * frames but we do not receive pause frames). 1333 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1334 * other: No other values should be possible at this point. 1335 */ 1336 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1337 1338 switch (hw->fc.current_mode) { 1339 case e1000_fc_none: 1340 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1341 break; 1342 case e1000_fc_rx_pause: 1343 ctrl &= (~E1000_CTRL_TFCE); 1344 ctrl |= E1000_CTRL_RFCE; 1345 break; 1346 case e1000_fc_tx_pause: 1347 ctrl &= (~E1000_CTRL_RFCE); 1348 ctrl |= E1000_CTRL_TFCE; 1349 break; 1350 case e1000_fc_full: 1351 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1352 break; 1353 default: 1354 DEBUGOUT("Flow control param set incorrectly\n"); 1355 ret_val = -E1000_ERR_CONFIG; 1356 goto out; 1357 } 1358 1359 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1360 1361out: 1362 return ret_val; 1363} 1364 1365/** 1366 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1367 * @hw: pointer to the HW structure 1368 * 1369 * Checks the status of auto-negotiation after link up to ensure that the 1370 * speed and duplex were not forced. If the link needed to be forced, then 1371 * flow control needs to be forced also. If auto-negotiation is enabled 1372 * and did not fail, then we configure flow control based on our link 1373 * partner. 1374 **/ 1375s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1376{ 1377 struct e1000_mac_info *mac = &hw->mac; 1378 s32 ret_val = E1000_SUCCESS; 1379 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1380 u16 speed, duplex; 1381 1382 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1383 1384 /* 1385 * Check for the case where we have fiber media and auto-neg failed 1386 * so we had to force link. In this case, we need to force the 1387 * configuration of the MAC to match the "fc" parameter. 1388 */ 1389 if (mac->autoneg_failed) { 1390 if (hw->phy.media_type == e1000_media_type_fiber || 1391 hw->phy.media_type == e1000_media_type_internal_serdes) 1392 ret_val = e1000_force_mac_fc_generic(hw); 1393 } else { 1394 if (hw->phy.media_type == e1000_media_type_copper) 1395 ret_val = e1000_force_mac_fc_generic(hw); 1396 } 1397 1398 if (ret_val) { 1399 DEBUGOUT("Error forcing flow control settings\n"); 1400 goto out; 1401 } 1402 1403 /* 1404 * Check for the case where we have copper media and auto-neg is 1405 * enabled. In this case, we need to check and see if Auto-Neg 1406 * has completed, and if so, how the PHY and link partner has 1407 * flow control configured. 1408 */ 1409 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1410 /* 1411 * Read the MII Status Register and check to see if AutoNeg 1412 * has completed. We read this twice because this reg has 1413 * some "sticky" (latched) bits. 1414 */ 1415 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1416 if (ret_val) 1417 goto out; 1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1419 if (ret_val) 1420 goto out; 1421 1422 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1423 DEBUGOUT("Copper PHY and Auto Neg " 1424 "has not completed.\n"); 1425 goto out; 1426 } 1427 1428 /* 1429 * The AutoNeg process has completed, so we now need to 1430 * read both the Auto Negotiation Advertisement 1431 * Register (Address 4) and the Auto_Negotiation Base 1432 * Page Ability Register (Address 5) to determine how 1433 * flow control was negotiated. 1434 */ 1435 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1436 &mii_nway_adv_reg); 1437 if (ret_val) 1438 goto out; 1439 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1440 &mii_nway_lp_ability_reg); 1441 if (ret_val) 1442 goto out; 1443 1444 /* 1445 * Two bits in the Auto Negotiation Advertisement Register 1446 * (Address 4) and two bits in the Auto Negotiation Base 1447 * Page Ability Register (Address 5) determine flow control 1448 * for both the PHY and the link partner. The following 1449 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1450 * 1999, describes these PAUSE resolution bits and how flow 1451 * control is determined based upon these settings. 1452 * NOTE: DC = Don't Care 1453 * 1454 * LOCAL DEVICE | LINK PARTNER 1455 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1456 *-------|---------|-------|---------|-------------------- 1457 * 0 | 0 | DC | DC | e1000_fc_none 1458 * 0 | 1 | 0 | DC | e1000_fc_none 1459 * 0 | 1 | 1 | 0 | e1000_fc_none 1460 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1461 * 1 | 0 | 0 | DC | e1000_fc_none 1462 * 1 | DC | 1 | DC | e1000_fc_full 1463 * 1 | 1 | 0 | 0 | e1000_fc_none 1464 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1465 * 1466 * Are both PAUSE bits set to 1? If so, this implies 1467 * Symmetric Flow Control is enabled at both ends. The 1468 * ASM_DIR bits are irrelevant per the spec. 1469 * 1470 * For Symmetric Flow Control: 1471 * 1472 * LOCAL DEVICE | LINK PARTNER 1473 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1474 *-------|---------|-------|---------|-------------------- 1475 * 1 | DC | 1 | DC | E1000_fc_full 1476 * 1477 */ 1478 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1479 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1480 /* 1481 * Now we need to check if the user selected Rx ONLY 1482 * of pause frames. In this case, we had to advertise 1483 * FULL flow control because we could not advertise Rx 1484 * ONLY. Hence, we must now check to see if we need to 1485 * turn OFF the TRANSMISSION of PAUSE frames. 1486 */ 1487 if (hw->fc.requested_mode == e1000_fc_full) { 1488 hw->fc.current_mode = e1000_fc_full; 1489 DEBUGOUT("Flow Control = FULL.\r\n"); 1490 } else { 1491 hw->fc.current_mode = e1000_fc_rx_pause; 1492 DEBUGOUT("Flow Control = " 1493 "Rx PAUSE frames only.\r\n"); 1494 } 1495 } 1496 /* 1497 * For receiving PAUSE frames ONLY. 1498 * 1499 * LOCAL DEVICE | LINK PARTNER 1500 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1501 *-------|---------|-------|---------|-------------------- 1502 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1503 */ 1504 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1505 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1506 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1507 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1508 hw->fc.current_mode = e1000_fc_tx_pause; 1509 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1510 } 1511 /* 1512 * For transmitting PAUSE frames ONLY. 1513 * 1514 * LOCAL DEVICE | LINK PARTNER 1515 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1516 *-------|---------|-------|---------|-------------------- 1517 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1518 */ 1519 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1520 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1521 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1522 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1523 hw->fc.current_mode = e1000_fc_rx_pause; 1524 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1525 } else { 1526 /* 1527 * Per the IEEE spec, at this point flow control 1528 * should be disabled. 1529 */ 1530 hw->fc.current_mode = e1000_fc_none; 1531 DEBUGOUT("Flow Control = NONE.\r\n"); 1532 } 1533 1534 /* 1535 * Now we need to do one last check... If we auto- 1536 * negotiated to HALF DUPLEX, flow control should not be 1537 * enabled per IEEE 802.3 spec. 1538 */ 1539 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1540 if (ret_val) { 1541 DEBUGOUT("Error getting link speed and duplex\n"); 1542 goto out; 1543 } 1544 1545 if (duplex == HALF_DUPLEX) 1546 hw->fc.current_mode = e1000_fc_none; 1547 1548 /* 1549 * Now we call a subroutine to actually force the MAC 1550 * controller to use the correct flow control settings. 1551 */ 1552 ret_val = e1000_force_mac_fc_generic(hw); 1553 if (ret_val) { 1554 DEBUGOUT("Error forcing flow control settings\n"); 1555 goto out; 1556 } 1557 } 1558 1559out: 1560 return ret_val; 1561} 1562 1563/** 1564 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1565 * @hw: pointer to the HW structure 1566 * @speed: stores the current speed 1567 * @duplex: stores the current duplex 1568 * 1569 * Read the status register for the current speed/duplex and store the current 1570 * speed and duplex for copper connections. 1571 **/ 1572s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1573 u16 *duplex) 1574{ 1575 u32 status; 1576 1577 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1578 1579 status = E1000_READ_REG(hw, E1000_STATUS); 1580 if (status & E1000_STATUS_SPEED_1000) { 1581 *speed = SPEED_1000; 1582 DEBUGOUT("1000 Mbs, "); 1583 } else if (status & E1000_STATUS_SPEED_100) { 1584 *speed = SPEED_100; 1585 DEBUGOUT("100 Mbs, "); 1586 } else { 1587 *speed = SPEED_10; 1588 DEBUGOUT("10 Mbs, "); 1589 } 1590 1591 if (status & E1000_STATUS_FD) { 1592 *duplex = FULL_DUPLEX; 1593 DEBUGOUT("Full Duplex\n"); 1594 } else { 1595 *duplex = HALF_DUPLEX; 1596 DEBUGOUT("Half Duplex\n"); 1597 } 1598 1599 return E1000_SUCCESS; 1600} 1601 1602/** 1603 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1604 * @hw: pointer to the HW structure 1605 * @speed: stores the current speed 1606 * @duplex: stores the current duplex 1607 * 1608 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1609 * for fiber/serdes links. 1610 **/ 1611s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1612 u16 *speed, u16 *duplex) 1613{ 1614 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1615 1616 *speed = SPEED_1000; 1617 *duplex = FULL_DUPLEX; 1618 1619 return E1000_SUCCESS; 1620} 1621 1622/** 1623 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1624 * @hw: pointer to the HW structure 1625 * 1626 * Acquire the HW semaphore to access the PHY or NVM 1627 **/ 1628s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1629{ 1630 u32 swsm; 1631 s32 ret_val = E1000_SUCCESS; 1632 s32 timeout = hw->nvm.word_size + 1; 1633 s32 i = 0; 1634 1635 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1636 1637 /* Get the SW semaphore */ 1638 while (i < timeout) { 1639 swsm = E1000_READ_REG(hw, E1000_SWSM); 1640 if (!(swsm & E1000_SWSM_SMBI)) 1641 break; 1642 1643 usec_delay(50); 1644 i++; 1645 } 1646 1647 if (i == timeout) { 1648 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1649 ret_val = -E1000_ERR_NVM; 1650 goto out; 1651 } 1652 1653 /* Get the FW semaphore. */ 1654 for (i = 0; i < timeout; i++) { 1655 swsm = E1000_READ_REG(hw, E1000_SWSM); 1656 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1657 1658 /* Semaphore acquired if bit latched */ 1659 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1660 break; 1661 1662 usec_delay(50); 1663 } 1664 1665 if (i == timeout) { 1666 /* Release semaphores */ 1667 e1000_put_hw_semaphore_generic(hw); 1668 DEBUGOUT("Driver can't access the NVM\n"); 1669 ret_val = -E1000_ERR_NVM; 1670 goto out; 1671 } 1672 1673out: 1674 return ret_val; 1675} 1676 1677/** 1678 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1679 * @hw: pointer to the HW structure 1680 * 1681 * Release hardware semaphore used to access the PHY or NVM 1682 **/ 1683void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1684{ 1685 u32 swsm; 1686 1687 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1688 1689 swsm = E1000_READ_REG(hw, E1000_SWSM); 1690 1691 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1692 1693 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1694} 1695 1696/** 1697 * e1000_get_auto_rd_done_generic - Check for auto read completion 1698 * @hw: pointer to the HW structure 1699 * 1700 * Check EEPROM for Auto Read done bit. 1701 **/ 1702s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1703{ 1704 s32 i = 0; 1705 s32 ret_val = E1000_SUCCESS; 1706 1707 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1708 1709 while (i < AUTO_READ_DONE_TIMEOUT) { 1710 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1711 break; 1712 msec_delay(1); 1713 i++; 1714 } 1715 1716 if (i == AUTO_READ_DONE_TIMEOUT) { 1717 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1718 ret_val = -E1000_ERR_RESET; 1719 goto out; 1720 } 1721 1722out: 1723 return ret_val; 1724} 1725 1726/** 1727 * e1000_valid_led_default_generic - Verify a valid default LED config 1728 * @hw: pointer to the HW structure 1729 * @data: pointer to the NVM (EEPROM) 1730 * 1731 * Read the EEPROM for the current default LED configuration. If the 1732 * LED configuration is not valid, set to a valid LED configuration. 1733 **/ 1734s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1735{ 1736 s32 ret_val; 1737 1738 DEBUGFUNC("e1000_valid_led_default_generic"); 1739 1740 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1741 if (ret_val) { 1742 DEBUGOUT("NVM Read Error\n"); 1743 goto out; 1744 } 1745 1746 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1747 *data = ID_LED_DEFAULT; 1748 1749out: 1750 return ret_val; 1751} 1752 1753/** 1754 * e1000_id_led_init_generic - 1755 * @hw: pointer to the HW structure 1756 * 1757 **/ 1758s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1759{ 1760 struct e1000_mac_info *mac = &hw->mac; 1761 s32 ret_val; 1762 const u32 ledctl_mask = 0x000000FF; 1763 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1764 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1765 u16 data, i, temp; 1766 const u16 led_mask = 0x0F; 1767 1768 DEBUGFUNC("e1000_id_led_init_generic"); 1769 1770 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1771 if (ret_val) 1772 goto out; 1773 1774 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1775 mac->ledctl_mode1 = mac->ledctl_default; 1776 mac->ledctl_mode2 = mac->ledctl_default; 1777 1778 for (i = 0; i < 4; i++) { 1779 temp = (data >> (i << 2)) & led_mask; 1780 switch (temp) { 1781 case ID_LED_ON1_DEF2: 1782 case ID_LED_ON1_ON2: 1783 case ID_LED_ON1_OFF2: 1784 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1785 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1786 break; 1787 case ID_LED_OFF1_DEF2: 1788 case ID_LED_OFF1_ON2: 1789 case ID_LED_OFF1_OFF2: 1790 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1791 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1792 break; 1793 default: 1794 /* Do nothing */ 1795 break; 1796 } 1797 switch (temp) { 1798 case ID_LED_DEF1_ON2: 1799 case ID_LED_ON1_ON2: 1800 case ID_LED_OFF1_ON2: 1801 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1802 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1803 break; 1804 case ID_LED_DEF1_OFF2: 1805 case ID_LED_ON1_OFF2: 1806 case ID_LED_OFF1_OFF2: 1807 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1808 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1809 break; 1810 default: 1811 /* Do nothing */ 1812 break; 1813 } 1814 } 1815 1816out: 1817 return ret_val; 1818} 1819 1820/** 1821 * e1000_setup_led_generic - Configures SW controllable LED 1822 * @hw: pointer to the HW structure 1823 * 1824 * This prepares the SW controllable LED for use and saves the current state 1825 * of the LED so it can be later restored. 1826 **/ 1827s32 e1000_setup_led_generic(struct e1000_hw *hw) 1828{ 1829 u32 ledctl; 1830 s32 ret_val = E1000_SUCCESS; 1831 1832 DEBUGFUNC("e1000_setup_led_generic"); 1833 1834 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1835 ret_val = -E1000_ERR_CONFIG; 1836 goto out; 1837 } 1838 1839 if (hw->phy.media_type == e1000_media_type_fiber) { 1840 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1841 hw->mac.ledctl_default = ledctl; 1842 /* Turn off LED0 */ 1843 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1844 E1000_LEDCTL_LED0_BLINK | 1845 E1000_LEDCTL_LED0_MODE_MASK); 1846 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1847 E1000_LEDCTL_LED0_MODE_SHIFT); 1848 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1849 } else if (hw->phy.media_type == e1000_media_type_copper) { 1850 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1851 } 1852 1853out: 1854 return ret_val; 1855} 1856 1857/** 1858 * e1000_cleanup_led_generic - Set LED config to default operation 1859 * @hw: pointer to the HW structure 1860 * 1861 * Remove the current LED configuration and set the LED configuration 1862 * to the default value, saved from the EEPROM. 1863 **/ 1864s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1865{ 1866 DEBUGFUNC("e1000_cleanup_led_generic"); 1867 1868 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1869 return E1000_SUCCESS; 1870} 1871 1872/** 1873 * e1000_blink_led_generic - Blink LED 1874 * @hw: pointer to the HW structure 1875 * 1876 * Blink the LEDs which are set to be on. 1877 **/ 1878s32 e1000_blink_led_generic(struct e1000_hw *hw) 1879{ 1880 u32 ledctl_blink = 0; 1881 u32 i; 1882 1883 DEBUGFUNC("e1000_blink_led_generic"); 1884 1885 if (hw->phy.media_type == e1000_media_type_fiber) { 1886 /* always blink LED0 for PCI-E fiber */ 1887 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1888 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1889 } else { 1890 /* 1891 * set the blink bit for each LED that's "on" (0x0E) 1892 * in ledctl_mode2 1893 */ 1894 ledctl_blink = hw->mac.ledctl_mode2; 1895 for (i = 0; i < 4; i++) 1896 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1897 E1000_LEDCTL_MODE_LED_ON) 1898 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1899 (i * 8)); 1900 } 1901 1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1903 1904 return E1000_SUCCESS; 1905} 1906 1907/** 1908 * e1000_led_on_generic - Turn LED on 1909 * @hw: pointer to the HW structure 1910 * 1911 * Turn LED on. 1912 **/ 1913s32 e1000_led_on_generic(struct e1000_hw *hw) 1914{ 1915 u32 ctrl; 1916 1917 DEBUGFUNC("e1000_led_on_generic"); 1918 1919 switch (hw->phy.media_type) { 1920 case e1000_media_type_fiber: 1921 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1922 ctrl &= ~E1000_CTRL_SWDPIN0; 1923 ctrl |= E1000_CTRL_SWDPIO0; 1924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1925 break; 1926 case e1000_media_type_copper: 1927 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1928 break; 1929 default: 1930 break; 1931 } 1932 1933 return E1000_SUCCESS; 1934} 1935 1936/** 1937 * e1000_led_off_generic - Turn LED off 1938 * @hw: pointer to the HW structure 1939 * 1940 * Turn LED off. 1941 **/ 1942s32 e1000_led_off_generic(struct e1000_hw *hw) 1943{ 1944 u32 ctrl; 1945 1946 DEBUGFUNC("e1000_led_off_generic"); 1947 1948 switch (hw->phy.media_type) { 1949 case e1000_media_type_fiber: 1950 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1951 ctrl |= E1000_CTRL_SWDPIN0; 1952 ctrl |= E1000_CTRL_SWDPIO0; 1953 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1954 break; 1955 case e1000_media_type_copper: 1956 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1957 break; 1958 default: 1959 break; 1960 } 1961 1962 return E1000_SUCCESS; 1963} 1964 1965/** 1966 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1967 * @hw: pointer to the HW structure 1968 * @no_snoop: bitmap of snoop events 1969 * 1970 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1971 **/ 1972void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1973{ 1974 u32 gcr; 1975 1976 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1977 1978 if (hw->bus.type != e1000_bus_type_pci_express) 1979 goto out; 1980 1981 if (no_snoop) { 1982 gcr = E1000_READ_REG(hw, E1000_GCR); 1983 gcr &= ~(PCIE_NO_SNOOP_ALL); 1984 gcr |= no_snoop; 1985 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1986 } 1987out: 1988 return; 1989} 1990 1991/** 1992 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1993 * @hw: pointer to the HW structure 1994 * 1995 * Returns E1000_SUCCESS if successful, else returns -10 1996 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1997 * the master requests to be disabled. 1998 * 1999 * Disables PCI-Express master access and verifies there are no pending 2000 * requests. 2001 **/ 2002s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2003{ 2004 u32 ctrl; 2005 s32 timeout = MASTER_DISABLE_TIMEOUT; 2006 s32 ret_val = E1000_SUCCESS; 2007 2008 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2009 2010 if (hw->bus.type != e1000_bus_type_pci_express) 2011 goto out; 2012 2013 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2014 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2015 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2016 2017 while (timeout) { 2018 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2019 E1000_STATUS_GIO_MASTER_ENABLE)) 2020 break; 2021 usec_delay(100); 2022 timeout--; 2023 } 2024 2025 if (!timeout) { 2026 DEBUGOUT("Master requests are pending.\n"); 2027 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2028 } 2029 2030out: 2031 return ret_val; 2032} 2033 2034/** 2035 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2036 * @hw: pointer to the HW structure 2037 * 2038 * Reset the Adaptive Interframe Spacing throttle to default values. 2039 **/ 2040void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2041{ 2042 struct e1000_mac_info *mac = &hw->mac; 2043 2044 DEBUGFUNC("e1000_reset_adaptive_generic"); 2045 2046 if (!mac->adaptive_ifs) { 2047 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2048 goto out; 2049 } 2050 2051 mac->current_ifs_val = 0; 2052 mac->ifs_min_val = IFS_MIN; 2053 mac->ifs_max_val = IFS_MAX; 2054 mac->ifs_step_size = IFS_STEP; 2055 mac->ifs_ratio = IFS_RATIO; 2056 2057 mac->in_ifs_mode = FALSE; 2058 E1000_WRITE_REG(hw, E1000_AIT, 0); 2059out: 2060 return; 2061} 2062 2063/** 2064 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2065 * @hw: pointer to the HW structure 2066 * 2067 * Update the Adaptive Interframe Spacing Throttle value based on the 2068 * time between transmitted packets and time between collisions. 2069 **/ 2070void e1000_update_adaptive_generic(struct e1000_hw *hw) 2071{ 2072 struct e1000_mac_info *mac = &hw->mac; 2073 2074 DEBUGFUNC("e1000_update_adaptive_generic"); 2075 2076 if (!mac->adaptive_ifs) { 2077 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2078 goto out; 2079 } 2080 2081 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2082 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2083 mac->in_ifs_mode = TRUE; 2084 if (mac->current_ifs_val < mac->ifs_max_val) { 2085 if (!mac->current_ifs_val) 2086 mac->current_ifs_val = mac->ifs_min_val; 2087 else 2088 mac->current_ifs_val += 2089 mac->ifs_step_size; 2090 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2091 } 2092 } 2093 } else { 2094 if (mac->in_ifs_mode && 2095 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2096 mac->current_ifs_val = 0; 2097 mac->in_ifs_mode = FALSE; 2098 E1000_WRITE_REG(hw, E1000_AIT, 0); 2099 } 2100 } 2101out: 2102 return; 2103} 2104 2105/** 2106 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2107 * @hw: pointer to the HW structure 2108 * 2109 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2110 * set, which is forced to MDI mode only. 2111 **/ 2112static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2113{ 2114 s32 ret_val = E1000_SUCCESS; 2115 2116 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2117 2118 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2119 DEBUGOUT("Invalid MDI setting detected\n"); 2120 hw->phy.mdix = 1; 2121 ret_val = -E1000_ERR_CONFIG; 2122 goto out; 2123 } 2124 2125out: 2126 return ret_val; 2127} 2128 2129/** 2130 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2131 * @hw: pointer to the HW structure 2132 * @reg: 32bit register offset such as E1000_SCTL 2133 * @offset: register offset to write to 2134 * @data: data to write at register offset 2135 * 2136 * Writes an address/data control type register. There are several of these 2137 * and they all have the format address << 8 | data and bit 31 is polled for 2138 * completion. 2139 **/ 2140s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2141 u32 offset, u8 data) 2142{ 2143 u32 i, regvalue = 0; 2144 s32 ret_val = E1000_SUCCESS; 2145 2146 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2147 2148 /* Set up the address and data */ 2149 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2150 E1000_WRITE_REG(hw, reg, regvalue); 2151 2152 /* Poll the ready bit to see if the MDI read completed */ 2153 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2154 usec_delay(5); 2155 regvalue = E1000_READ_REG(hw, reg); 2156 if (regvalue & E1000_GEN_CTL_READY) 2157 break; 2158 } 2159 if (!(regvalue & E1000_GEN_CTL_READY)) { 2160 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2161 ret_val = -E1000_ERR_PHY; 2162 goto out; 2163 } 2164 2165out: 2166 return ret_val; 2167} 2168