e1000_mac.c revision 200243
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 200243 2009-12-08 01:07:44Z jfv $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.mta_set = e1000_null_mta_set; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84} 85 86/** 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 **/ 90s32 e1000_null_ops_generic(struct e1000_hw *hw) 91{ 92 DEBUGFUNC("e1000_null_ops_generic"); 93 return E1000_SUCCESS; 94} 95 96/** 97 * e1000_null_mac_generic - No-op function, return void 98 * @hw: pointer to the HW structure 99 **/ 100void e1000_null_mac_generic(struct e1000_hw *hw) 101{ 102 DEBUGFUNC("e1000_null_mac_generic"); 103 return; 104} 105 106/** 107 * e1000_null_link_info - No-op function, return 0 108 * @hw: pointer to the HW structure 109 **/ 110s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 111{ 112 DEBUGFUNC("e1000_null_link_info"); 113 return E1000_SUCCESS; 114} 115 116/** 117 * e1000_null_mng_mode - No-op function, return FALSE 118 * @hw: pointer to the HW structure 119 **/ 120bool e1000_null_mng_mode(struct e1000_hw *hw) 121{ 122 DEBUGFUNC("e1000_null_mng_mode"); 123 return FALSE; 124} 125 126/** 127 * e1000_null_update_mc - No-op function, return void 128 * @hw: pointer to the HW structure 129 **/ 130void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 131{ 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134} 135 136/** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 141{ 142 DEBUGFUNC("e1000_null_write_vfta"); 143 return; 144} 145 146/** 147 * e1000_null_set_mta - No-op function, return void 148 * @hw: pointer to the HW structure 149 **/ 150void e1000_null_mta_set(struct e1000_hw *hw, u32 a) 151{ 152 DEBUGFUNC("e1000_null_mta_set"); 153 return; 154} 155 156/** 157 * e1000_null_rar_set - No-op function, return void 158 * @hw: pointer to the HW structure 159 **/ 160void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 161{ 162 DEBUGFUNC("e1000_null_rar_set"); 163 return; 164} 165 166/** 167 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 168 * @hw: pointer to the HW structure 169 * 170 * Determines and stores the system bus information for a particular 171 * network interface. The following bus information is determined and stored: 172 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 173 **/ 174s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 175{ 176 struct e1000_mac_info *mac = &hw->mac; 177 struct e1000_bus_info *bus = &hw->bus; 178 u32 status = E1000_READ_REG(hw, E1000_STATUS); 179 s32 ret_val = E1000_SUCCESS; 180 181 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 182 183 /* PCI or PCI-X? */ 184 bus->type = (status & E1000_STATUS_PCIX_MODE) 185 ? e1000_bus_type_pcix 186 : e1000_bus_type_pci; 187 188 /* Bus speed */ 189 if (bus->type == e1000_bus_type_pci) { 190 bus->speed = (status & E1000_STATUS_PCI66) 191 ? e1000_bus_speed_66 192 : e1000_bus_speed_33; 193 } else { 194 switch (status & E1000_STATUS_PCIX_SPEED) { 195 case E1000_STATUS_PCIX_SPEED_66: 196 bus->speed = e1000_bus_speed_66; 197 break; 198 case E1000_STATUS_PCIX_SPEED_100: 199 bus->speed = e1000_bus_speed_100; 200 break; 201 case E1000_STATUS_PCIX_SPEED_133: 202 bus->speed = e1000_bus_speed_133; 203 break; 204 default: 205 bus->speed = e1000_bus_speed_reserved; 206 break; 207 } 208 } 209 210 /* Bus width */ 211 bus->width = (status & E1000_STATUS_BUS64) 212 ? e1000_bus_width_64 213 : e1000_bus_width_32; 214 215 /* Which PCI(-X) function? */ 216 mac->ops.set_lan_id(hw); 217 218 return ret_val; 219} 220 221/** 222 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 223 * @hw: pointer to the HW structure 224 * 225 * Determines and stores the system bus information for a particular 226 * network interface. The following bus information is determined and stored: 227 * bus speed, bus width, type (PCIe), and PCIe function. 228 **/ 229s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 230{ 231 struct e1000_mac_info *mac = &hw->mac; 232 struct e1000_bus_info *bus = &hw->bus; 233 s32 ret_val; 234 u16 pcie_link_status; 235 236 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 237 238 bus->type = e1000_bus_type_pci_express; 239 bus->speed = e1000_bus_speed_2500; 240 241 ret_val = e1000_read_pcie_cap_reg(hw, 242 PCIE_LINK_STATUS, 243 &pcie_link_status); 244 if (ret_val) 245 bus->width = e1000_bus_width_unknown; 246 else 247 bus->width = (enum e1000_bus_width)((pcie_link_status & 248 PCIE_LINK_WIDTH_MASK) >> 249 PCIE_LINK_WIDTH_SHIFT); 250 251 mac->ops.set_lan_id(hw); 252 253 return E1000_SUCCESS; 254} 255 256/** 257 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 258 * 259 * @hw: pointer to the HW structure 260 * 261 * Determines the LAN function id by reading memory-mapped registers 262 * and swaps the port value if requested. 263 **/ 264static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 265{ 266 struct e1000_bus_info *bus = &hw->bus; 267 u32 reg; 268 269 /* 270 * The status register reports the correct function number 271 * for the device regardless of function swap state. 272 */ 273 reg = E1000_READ_REG(hw, E1000_STATUS); 274 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 275} 276 277/** 278 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 279 * @hw: pointer to the HW structure 280 * 281 * Determines the LAN function id by reading PCI config space. 282 **/ 283void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 284{ 285 struct e1000_bus_info *bus = &hw->bus; 286 u16 pci_header_type; 287 u32 status; 288 289 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 290 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 291 status = E1000_READ_REG(hw, E1000_STATUS); 292 bus->func = (status & E1000_STATUS_FUNC_MASK) 293 >> E1000_STATUS_FUNC_SHIFT; 294 } else { 295 bus->func = 0; 296 } 297} 298 299/** 300 * e1000_set_lan_id_single_port - Set LAN id for a single port device 301 * @hw: pointer to the HW structure 302 * 303 * Sets the LAN function id to zero for a single port device. 304 **/ 305void e1000_set_lan_id_single_port(struct e1000_hw *hw) 306{ 307 struct e1000_bus_info *bus = &hw->bus; 308 309 bus->func = 0; 310} 311 312/** 313 * e1000_clear_vfta_generic - Clear VLAN filter table 314 * @hw: pointer to the HW structure 315 * 316 * Clears the register array which contains the VLAN filter table by 317 * setting all the values to 0. 318 **/ 319void e1000_clear_vfta_generic(struct e1000_hw *hw) 320{ 321 u32 offset; 322 323 DEBUGFUNC("e1000_clear_vfta_generic"); 324 325 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 326 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 327 E1000_WRITE_FLUSH(hw); 328 } 329} 330 331/** 332 * e1000_write_vfta_generic - Write value to VLAN filter table 333 * @hw: pointer to the HW structure 334 * @offset: register offset in VLAN filter table 335 * @value: register value written to VLAN filter table 336 * 337 * Writes value at the given offset in the register array which stores 338 * the VLAN filter table. 339 **/ 340void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 341{ 342 DEBUGFUNC("e1000_write_vfta_generic"); 343 344 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 345 E1000_WRITE_FLUSH(hw); 346} 347 348/** 349 * e1000_init_rx_addrs_generic - Initialize receive address's 350 * @hw: pointer to the HW structure 351 * @rar_count: receive address registers 352 * 353 * Setups the receive address registers by setting the base receive address 354 * register to the devices MAC address and clearing all the other receive 355 * address registers to 0. 356 **/ 357void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 358{ 359 u32 i; 360 u8 mac_addr[ETH_ADDR_LEN] = {0}; 361 362 DEBUGFUNC("e1000_init_rx_addrs_generic"); 363 364 /* Setup the receive address */ 365 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 366 367 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 368 369 /* Zero out the other (rar_entry_count - 1) receive addresses */ 370 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 371 for (i = 1; i < rar_count; i++) 372 hw->mac.ops.rar_set(hw, mac_addr, i); 373} 374 375/** 376 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 377 * @hw: pointer to the HW structure 378 * 379 * Checks the nvm for an alternate MAC address. An alternate MAC address 380 * can be setup by pre-boot software and must be treated like a permanent 381 * address and must override the actual permanent MAC address. If an 382 * alternate MAC address is found it is programmed into RAR0, replacing 383 * the permanent address that was installed into RAR0 by the Si on reset. 384 * This function will return SUCCESS unless it encounters an error while 385 * reading the EEPROM. 386 **/ 387s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 388{ 389 u32 i; 390 s32 ret_val = E1000_SUCCESS; 391 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 392 u8 alt_mac_addr[ETH_ADDR_LEN]; 393 394 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 395 396 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 397 &nvm_alt_mac_addr_offset); 398 if (ret_val) { 399 DEBUGOUT("NVM Read Error\n"); 400 goto out; 401 } 402 403 if (nvm_alt_mac_addr_offset == 0xFFFF) { 404 /* There is no Alternate MAC Address */ 405 goto out; 406 } 407 408 if (hw->bus.func == E1000_FUNC_1) 409 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 410 if (hw->bus.func == E1000_FUNC_2) 411 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 412 413 if (hw->bus.func == E1000_FUNC_3) 414 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 415 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 416 offset = nvm_alt_mac_addr_offset + (i >> 1); 417 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 418 if (ret_val) { 419 DEBUGOUT("NVM Read Error\n"); 420 goto out; 421 } 422 423 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 424 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 425 } 426 427 /* if multicast bit is set, the alternate address will not be used */ 428 if (alt_mac_addr[0] & 0x01) { 429 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 430 goto out; 431 } 432 433 /* 434 * We have a valid alternate MAC address, and we want to treat it the 435 * same as the normal permanent MAC address stored by the HW into the 436 * RAR. Do this by mapping this address into RAR0. 437 */ 438 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 439 440out: 441 return ret_val; 442} 443 444/** 445 * e1000_rar_set_generic - Set receive address register 446 * @hw: pointer to the HW structure 447 * @addr: pointer to the receive address 448 * @index: receive address array register 449 * 450 * Sets the receive address array register at index to the address passed 451 * in by addr. 452 **/ 453void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 454{ 455 u32 rar_low, rar_high; 456 457 DEBUGFUNC("e1000_rar_set_generic"); 458 459 /* 460 * HW expects these in little endian so we reverse the byte order 461 * from network order (big endian) to little endian 462 */ 463 rar_low = ((u32) addr[0] | 464 ((u32) addr[1] << 8) | 465 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 466 467 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 468 469 /* If MAC address zero, no need to set the AV bit */ 470 if (rar_low || rar_high) 471 rar_high |= E1000_RAH_AV; 472 473 /* 474 * Some bridges will combine consecutive 32-bit writes into 475 * a single burst write, which will malfunction on some parts. 476 * The flushes avoid this. 477 */ 478 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 479 E1000_WRITE_FLUSH(hw); 480 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 481 E1000_WRITE_FLUSH(hw); 482} 483 484/** 485 * e1000_mta_set_generic - Set multicast filter table address 486 * @hw: pointer to the HW structure 487 * @hash_value: determines the MTA register and bit to set 488 * 489 * The multicast table address is a register array of 32-bit registers. 490 * The hash_value is used to determine what register the bit is in, the 491 * current value is read, the new bit is OR'd in and the new value is 492 * written back into the register. 493 **/ 494void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 495{ 496 u32 hash_bit, hash_reg, mta; 497 498 DEBUGFUNC("e1000_mta_set_generic"); 499 /* 500 * The MTA is a register array of 32-bit registers. It is 501 * treated like an array of (32*mta_reg_count) bits. We want to 502 * set bit BitArray[hash_value]. So we figure out what register 503 * the bit is in, read it, OR in the new bit, then write 504 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 505 * mask to bits 31:5 of the hash value which gives us the 506 * register we're modifying. The hash bit within that register 507 * is determined by the lower 5 bits of the hash value. 508 */ 509 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 510 hash_bit = hash_value & 0x1F; 511 512 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 513 514 mta |= (1 << hash_bit); 515 516 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 517 E1000_WRITE_FLUSH(hw); 518} 519 520/** 521 * e1000_update_mc_addr_list_generic - Update Multicast addresses 522 * @hw: pointer to the HW structure 523 * @mc_addr_list: array of multicast addresses to program 524 * @mc_addr_count: number of multicast addresses to program 525 * 526 * Updates entire Multicast Table Array. 527 * The caller must have a packed mc_addr_list of multicast addresses. 528 **/ 529void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 530 u8 *mc_addr_list, u32 mc_addr_count) 531{ 532 u32 hash_value, hash_bit, hash_reg; 533 int i; 534 535 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 536 537 /* clear mta_shadow */ 538 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 539 540 /* update mta_shadow from mc_addr_list */ 541 for (i = 0; (u32) i < mc_addr_count; i++) { 542 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 543 544 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 545 hash_bit = hash_value & 0x1F; 546 547 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 548 mc_addr_list += (ETH_ADDR_LEN); 549 } 550 551 /* replace the entire MTA table */ 552 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 553 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 554 E1000_WRITE_FLUSH(hw); 555} 556 557/** 558 * e1000_hash_mc_addr_generic - Generate a multicast hash value 559 * @hw: pointer to the HW structure 560 * @mc_addr: pointer to a multicast address 561 * 562 * Generates a multicast address hash value which is used to determine 563 * the multicast filter table array address and new table value. See 564 * e1000_mta_set_generic() 565 **/ 566u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 567{ 568 u32 hash_value, hash_mask; 569 u8 bit_shift = 0; 570 571 DEBUGFUNC("e1000_hash_mc_addr_generic"); 572 573 /* Register count multiplied by bits per register */ 574 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 575 576 /* 577 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 578 * where 0xFF would still fall within the hash mask. 579 */ 580 while (hash_mask >> bit_shift != 0xFF) 581 bit_shift++; 582 583 /* 584 * The portion of the address that is used for the hash table 585 * is determined by the mc_filter_type setting. 586 * The algorithm is such that there is a total of 8 bits of shifting. 587 * The bit_shift for a mc_filter_type of 0 represents the number of 588 * left-shifts where the MSB of mc_addr[5] would still fall within 589 * the hash_mask. Case 0 does this exactly. Since there are a total 590 * of 8 bits of shifting, then mc_addr[4] will shift right the 591 * remaining number of bits. Thus 8 - bit_shift. The rest of the 592 * cases are a variation of this algorithm...essentially raising the 593 * number of bits to shift mc_addr[5] left, while still keeping the 594 * 8-bit shifting total. 595 * 596 * For example, given the following Destination MAC Address and an 597 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 598 * we can see that the bit_shift for case 0 is 4. These are the hash 599 * values resulting from each mc_filter_type... 600 * [0] [1] [2] [3] [4] [5] 601 * 01 AA 00 12 34 56 602 * LSB MSB 603 * 604 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 605 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 606 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 607 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 608 */ 609 switch (hw->mac.mc_filter_type) { 610 default: 611 case 0: 612 break; 613 case 1: 614 bit_shift += 1; 615 break; 616 case 2: 617 bit_shift += 2; 618 break; 619 case 3: 620 bit_shift += 4; 621 break; 622 } 623 624 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 625 (((u16) mc_addr[5]) << bit_shift))); 626 627 return hash_value; 628} 629 630/** 631 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 632 * @hw: pointer to the HW structure 633 * 634 * In certain situations, a system BIOS may report that the PCIx maximum 635 * memory read byte count (MMRBC) value is higher than than the actual 636 * value. We check the PCIx command register with the current PCIx status 637 * register. 638 **/ 639void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 640{ 641 u16 cmd_mmrbc; 642 u16 pcix_cmd; 643 u16 pcix_stat_hi_word; 644 u16 stat_mmrbc; 645 646 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 647 648 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 649 if (hw->bus.type != e1000_bus_type_pcix) 650 return; 651 652 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 653 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 654 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 655 PCIX_COMMAND_MMRBC_SHIFT; 656 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 657 PCIX_STATUS_HI_MMRBC_SHIFT; 658 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 659 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 660 if (cmd_mmrbc > stat_mmrbc) { 661 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 662 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 663 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 664 } 665} 666 667/** 668 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 669 * @hw: pointer to the HW structure 670 * 671 * Clears the base hardware counters by reading the counter registers. 672 **/ 673void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 674{ 675 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 676 677 E1000_READ_REG(hw, E1000_CRCERRS); 678 E1000_READ_REG(hw, E1000_SYMERRS); 679 E1000_READ_REG(hw, E1000_MPC); 680 E1000_READ_REG(hw, E1000_SCC); 681 E1000_READ_REG(hw, E1000_ECOL); 682 E1000_READ_REG(hw, E1000_MCC); 683 E1000_READ_REG(hw, E1000_LATECOL); 684 E1000_READ_REG(hw, E1000_COLC); 685 E1000_READ_REG(hw, E1000_DC); 686 E1000_READ_REG(hw, E1000_SEC); 687 E1000_READ_REG(hw, E1000_RLEC); 688 E1000_READ_REG(hw, E1000_XONRXC); 689 E1000_READ_REG(hw, E1000_XONTXC); 690 E1000_READ_REG(hw, E1000_XOFFRXC); 691 E1000_READ_REG(hw, E1000_XOFFTXC); 692 E1000_READ_REG(hw, E1000_FCRUC); 693 E1000_READ_REG(hw, E1000_GPRC); 694 E1000_READ_REG(hw, E1000_BPRC); 695 E1000_READ_REG(hw, E1000_MPRC); 696 E1000_READ_REG(hw, E1000_GPTC); 697 E1000_READ_REG(hw, E1000_GORCL); 698 E1000_READ_REG(hw, E1000_GORCH); 699 E1000_READ_REG(hw, E1000_GOTCL); 700 E1000_READ_REG(hw, E1000_GOTCH); 701 E1000_READ_REG(hw, E1000_RNBC); 702 E1000_READ_REG(hw, E1000_RUC); 703 E1000_READ_REG(hw, E1000_RFC); 704 E1000_READ_REG(hw, E1000_ROC); 705 E1000_READ_REG(hw, E1000_RJC); 706 E1000_READ_REG(hw, E1000_TORL); 707 E1000_READ_REG(hw, E1000_TORH); 708 E1000_READ_REG(hw, E1000_TOTL); 709 E1000_READ_REG(hw, E1000_TOTH); 710 E1000_READ_REG(hw, E1000_TPR); 711 E1000_READ_REG(hw, E1000_TPT); 712 E1000_READ_REG(hw, E1000_MPTC); 713 E1000_READ_REG(hw, E1000_BPTC); 714} 715 716/** 717 * e1000_check_for_copper_link_generic - Check for link (Copper) 718 * @hw: pointer to the HW structure 719 * 720 * Checks to see of the link status of the hardware has changed. If a 721 * change in link status has been detected, then we read the PHY registers 722 * to get the current speed/duplex if link exists. 723 **/ 724s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 725{ 726 struct e1000_mac_info *mac = &hw->mac; 727 s32 ret_val; 728 bool link; 729 730 DEBUGFUNC("e1000_check_for_copper_link"); 731 732 /* 733 * We only want to go out to the PHY registers to see if Auto-Neg 734 * has completed and/or if our link status has changed. The 735 * get_link_status flag is set upon receiving a Link Status 736 * Change or Rx Sequence Error interrupt. 737 */ 738 if (!mac->get_link_status) { 739 ret_val = E1000_SUCCESS; 740 goto out; 741 } 742 743 /* 744 * First we want to see if the MII Status Register reports 745 * link. If so, then we want to get the current speed/duplex 746 * of the PHY. 747 */ 748 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 749 if (ret_val) 750 goto out; 751 752 if (!link) 753 goto out; /* No link detected */ 754 755 mac->get_link_status = FALSE; 756 757 /* 758 * Check if there was DownShift, must be checked 759 * immediately after link-up 760 */ 761 e1000_check_downshift_generic(hw); 762 763 /* 764 * If we are forcing speed/duplex, then we simply return since 765 * we have already determined whether we have link or not. 766 */ 767 if (!mac->autoneg) { 768 ret_val = -E1000_ERR_CONFIG; 769 goto out; 770 } 771 772 /* 773 * Auto-Neg is enabled. Auto Speed Detection takes care 774 * of MAC speed/duplex configuration. So we only need to 775 * configure Collision Distance in the MAC. 776 */ 777 e1000_config_collision_dist_generic(hw); 778 779 /* 780 * Configure Flow Control now that Auto-Neg has completed. 781 * First, we need to restore the desired flow control 782 * settings because we may have had to re-autoneg with a 783 * different link partner. 784 */ 785 ret_val = e1000_config_fc_after_link_up_generic(hw); 786 if (ret_val) 787 DEBUGOUT("Error configuring flow control\n"); 788 789out: 790 return ret_val; 791} 792 793/** 794 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 795 * @hw: pointer to the HW structure 796 * 797 * Checks for link up on the hardware. If link is not up and we have 798 * a signal, then we need to force link up. 799 **/ 800s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 801{ 802 struct e1000_mac_info *mac = &hw->mac; 803 u32 rxcw; 804 u32 ctrl; 805 u32 status; 806 s32 ret_val = E1000_SUCCESS; 807 808 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 809 810 ctrl = E1000_READ_REG(hw, E1000_CTRL); 811 status = E1000_READ_REG(hw, E1000_STATUS); 812 rxcw = E1000_READ_REG(hw, E1000_RXCW); 813 814 /* 815 * If we don't have link (auto-negotiation failed or link partner 816 * cannot auto-negotiate), the cable is plugged in (we have signal), 817 * and our link partner is not trying to auto-negotiate with us (we 818 * are receiving idles or data), we need to force link up. We also 819 * need to give auto-negotiation time to complete, in case the cable 820 * was just plugged in. The autoneg_failed flag does this. 821 */ 822 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 823 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 824 (!(rxcw & E1000_RXCW_C))) { 825 if (mac->autoneg_failed == 0) { 826 mac->autoneg_failed = 1; 827 goto out; 828 } 829 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 830 831 /* Disable auto-negotiation in the TXCW register */ 832 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 833 834 /* Force link-up and also force full-duplex. */ 835 ctrl = E1000_READ_REG(hw, E1000_CTRL); 836 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 837 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 838 839 /* Configure Flow Control after forcing link up. */ 840 ret_val = e1000_config_fc_after_link_up_generic(hw); 841 if (ret_val) { 842 DEBUGOUT("Error configuring flow control\n"); 843 goto out; 844 } 845 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 846 /* 847 * If we are forcing link and we are receiving /C/ ordered 848 * sets, re-enable auto-negotiation in the TXCW register 849 * and disable forced link in the Device Control register 850 * in an attempt to auto-negotiate with our link partner. 851 */ 852 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 853 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 854 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 855 856 mac->serdes_has_link = TRUE; 857 } 858 859out: 860 return ret_val; 861} 862 863/** 864 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 865 * @hw: pointer to the HW structure 866 * 867 * Checks for link up on the hardware. If link is not up and we have 868 * a signal, then we need to force link up. 869 **/ 870s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 871{ 872 struct e1000_mac_info *mac = &hw->mac; 873 u32 rxcw; 874 u32 ctrl; 875 u32 status; 876 s32 ret_val = E1000_SUCCESS; 877 878 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 879 880 ctrl = E1000_READ_REG(hw, E1000_CTRL); 881 status = E1000_READ_REG(hw, E1000_STATUS); 882 rxcw = E1000_READ_REG(hw, E1000_RXCW); 883 884 /* 885 * If we don't have link (auto-negotiation failed or link partner 886 * cannot auto-negotiate), and our link partner is not trying to 887 * auto-negotiate with us (we are receiving idles or data), 888 * we need to force link up. We also need to give auto-negotiation 889 * time to complete. 890 */ 891 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 892 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 893 if (mac->autoneg_failed == 0) { 894 mac->autoneg_failed = 1; 895 goto out; 896 } 897 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 898 899 /* Disable auto-negotiation in the TXCW register */ 900 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 901 902 /* Force link-up and also force full-duplex. */ 903 ctrl = E1000_READ_REG(hw, E1000_CTRL); 904 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 905 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 906 907 /* Configure Flow Control after forcing link up. */ 908 ret_val = e1000_config_fc_after_link_up_generic(hw); 909 if (ret_val) { 910 DEBUGOUT("Error configuring flow control\n"); 911 goto out; 912 } 913 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 914 /* 915 * If we are forcing link and we are receiving /C/ ordered 916 * sets, re-enable auto-negotiation in the TXCW register 917 * and disable forced link in the Device Control register 918 * in an attempt to auto-negotiate with our link partner. 919 */ 920 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 921 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 922 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 923 924 mac->serdes_has_link = TRUE; 925 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 926 /* 927 * If we force link for non-auto-negotiation switch, check 928 * link status based on MAC synchronization for internal 929 * serdes media type. 930 */ 931 /* SYNCH bit and IV bit are sticky. */ 932 usec_delay(10); 933 rxcw = E1000_READ_REG(hw, E1000_RXCW); 934 if (rxcw & E1000_RXCW_SYNCH) { 935 if (!(rxcw & E1000_RXCW_IV)) { 936 mac->serdes_has_link = TRUE; 937 DEBUGOUT("SERDES: Link up - forced.\n"); 938 } 939 } else { 940 mac->serdes_has_link = FALSE; 941 DEBUGOUT("SERDES: Link down - force failed.\n"); 942 } 943 } 944 945 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 946 status = E1000_READ_REG(hw, E1000_STATUS); 947 if (status & E1000_STATUS_LU) { 948 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 949 usec_delay(10); 950 rxcw = E1000_READ_REG(hw, E1000_RXCW); 951 if (rxcw & E1000_RXCW_SYNCH) { 952 if (!(rxcw & E1000_RXCW_IV)) { 953 mac->serdes_has_link = TRUE; 954 DEBUGOUT("SERDES: Link up - autoneg " 955 "completed sucessfully.\n"); 956 } else { 957 mac->serdes_has_link = FALSE; 958 DEBUGOUT("SERDES: Link down - invalid" 959 "codewords detected in autoneg.\n"); 960 } 961 } else { 962 mac->serdes_has_link = FALSE; 963 DEBUGOUT("SERDES: Link down - no sync.\n"); 964 } 965 } else { 966 mac->serdes_has_link = FALSE; 967 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 968 } 969 } 970 971out: 972 return ret_val; 973} 974 975/** 976 * e1000_setup_link_generic - Setup flow control and link settings 977 * @hw: pointer to the HW structure 978 * 979 * Determines which flow control settings to use, then configures flow 980 * control. Calls the appropriate media-specific link configuration 981 * function. Assuming the adapter has a valid link partner, a valid link 982 * should be established. Assumes the hardware has previously been reset 983 * and the transmitter and receiver are not enabled. 984 **/ 985s32 e1000_setup_link_generic(struct e1000_hw *hw) 986{ 987 s32 ret_val = E1000_SUCCESS; 988 989 DEBUGFUNC("e1000_setup_link_generic"); 990 991 /* 992 * In the case of the phy reset being blocked, we already have a link. 993 * We do not need to set it up again. 994 */ 995 if (e1000_check_reset_block(hw)) 996 goto out; 997 998 /* 999 * If requested flow control is set to default, set flow control 1000 * based on the EEPROM flow control settings. 1001 */ 1002 if (hw->fc.requested_mode == e1000_fc_default) { 1003 ret_val = e1000_set_default_fc_generic(hw); 1004 if (ret_val) 1005 goto out; 1006 } 1007 1008 /* 1009 * Save off the requested flow control mode for use later. Depending 1010 * on the link partner's capabilities, we may or may not use this mode. 1011 */ 1012 hw->fc.current_mode = hw->fc.requested_mode; 1013 1014 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1015 hw->fc.current_mode); 1016 1017 /* Call the necessary media_type subroutine to configure the link. */ 1018 ret_val = hw->mac.ops.setup_physical_interface(hw); 1019 if (ret_val) 1020 goto out; 1021 1022 /* 1023 * Initialize the flow control address, type, and PAUSE timer 1024 * registers to their default values. This is done even if flow 1025 * control is disabled, because it does not hurt anything to 1026 * initialize these registers. 1027 */ 1028 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1029 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1030 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1031 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1032 1033 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1034 1035 ret_val = e1000_set_fc_watermarks_generic(hw); 1036 1037out: 1038 return ret_val; 1039} 1040 1041/** 1042 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1043 * @hw: pointer to the HW structure 1044 * 1045 * Configures collision distance and flow control for fiber and serdes 1046 * links. Upon successful setup, poll for link. 1047 **/ 1048s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1049{ 1050 u32 ctrl; 1051 s32 ret_val = E1000_SUCCESS; 1052 1053 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1054 1055 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1056 1057 /* Take the link out of reset */ 1058 ctrl &= ~E1000_CTRL_LRST; 1059 1060 e1000_config_collision_dist_generic(hw); 1061 1062 ret_val = e1000_commit_fc_settings_generic(hw); 1063 if (ret_val) 1064 goto out; 1065 1066 /* 1067 * Since auto-negotiation is enabled, take the link out of reset (the 1068 * link will be in reset, because we previously reset the chip). This 1069 * will restart auto-negotiation. If auto-negotiation is successful 1070 * then the link-up status bit will be set and the flow control enable 1071 * bits (RFCE and TFCE) will be set according to their negotiated value. 1072 */ 1073 DEBUGOUT("Auto-negotiation enabled\n"); 1074 1075 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1076 E1000_WRITE_FLUSH(hw); 1077 msec_delay(1); 1078 1079 /* 1080 * For these adapters, the SW definable pin 1 is set when the optics 1081 * detect a signal. If we have a signal, then poll for a "Link-Up" 1082 * indication. 1083 */ 1084 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1085 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1086 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1087 } else { 1088 DEBUGOUT("No signal detected\n"); 1089 } 1090 1091out: 1092 return ret_val; 1093} 1094 1095/** 1096 * e1000_config_collision_dist_generic - Configure collision distance 1097 * @hw: pointer to the HW structure 1098 * 1099 * Configures the collision distance to the default value and is used 1100 * during link setup. Currently no func pointer exists and all 1101 * implementations are handled in the generic version of this function. 1102 **/ 1103void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1104{ 1105 u32 tctl; 1106 1107 DEBUGFUNC("e1000_config_collision_dist_generic"); 1108 1109 tctl = E1000_READ_REG(hw, E1000_TCTL); 1110 1111 tctl &= ~E1000_TCTL_COLD; 1112 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1113 1114 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1115 E1000_WRITE_FLUSH(hw); 1116} 1117 1118/** 1119 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1120 * @hw: pointer to the HW structure 1121 * 1122 * Polls for link up by reading the status register, if link fails to come 1123 * up with auto-negotiation, then the link is forced if a signal is detected. 1124 **/ 1125s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1126{ 1127 struct e1000_mac_info *mac = &hw->mac; 1128 u32 i, status; 1129 s32 ret_val = E1000_SUCCESS; 1130 1131 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1132 1133 /* 1134 * If we have a signal (the cable is plugged in, or assumed TRUE for 1135 * serdes media) then poll for a "Link-Up" indication in the Device 1136 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1137 * seconds (Auto-negotiation should complete in less than 500 1138 * milliseconds even if the other end is doing it in SW). 1139 */ 1140 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1141 msec_delay(10); 1142 status = E1000_READ_REG(hw, E1000_STATUS); 1143 if (status & E1000_STATUS_LU) 1144 break; 1145 } 1146 if (i == FIBER_LINK_UP_LIMIT) { 1147 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1148 mac->autoneg_failed = 1; 1149 /* 1150 * AutoNeg failed to achieve a link, so we'll call 1151 * mac->check_for_link. This routine will force the 1152 * link up if we detect a signal. This will allow us to 1153 * communicate with non-autonegotiating link partners. 1154 */ 1155 ret_val = hw->mac.ops.check_for_link(hw); 1156 if (ret_val) { 1157 DEBUGOUT("Error while checking for link\n"); 1158 goto out; 1159 } 1160 mac->autoneg_failed = 0; 1161 } else { 1162 mac->autoneg_failed = 0; 1163 DEBUGOUT("Valid Link Found\n"); 1164 } 1165 1166out: 1167 return ret_val; 1168} 1169 1170/** 1171 * e1000_commit_fc_settings_generic - Configure flow control 1172 * @hw: pointer to the HW structure 1173 * 1174 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1175 * base on the flow control settings in e1000_mac_info. 1176 **/ 1177s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1178{ 1179 struct e1000_mac_info *mac = &hw->mac; 1180 u32 txcw; 1181 s32 ret_val = E1000_SUCCESS; 1182 1183 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1184 1185 /* 1186 * Check for a software override of the flow control settings, and 1187 * setup the device accordingly. If auto-negotiation is enabled, then 1188 * software will have to set the "PAUSE" bits to the correct value in 1189 * the Transmit Config Word Register (TXCW) and re-start auto- 1190 * negotiation. However, if auto-negotiation is disabled, then 1191 * software will have to manually configure the two flow control enable 1192 * bits in the CTRL register. 1193 * 1194 * The possible values of the "fc" parameter are: 1195 * 0: Flow control is completely disabled 1196 * 1: Rx flow control is enabled (we can receive pause frames, 1197 * but not send pause frames). 1198 * 2: Tx flow control is enabled (we can send pause frames but we 1199 * do not support receiving pause frames). 1200 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1201 */ 1202 switch (hw->fc.current_mode) { 1203 case e1000_fc_none: 1204 /* Flow control completely disabled by a software over-ride. */ 1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1206 break; 1207 case e1000_fc_rx_pause: 1208 /* 1209 * Rx Flow control is enabled and Tx Flow control is disabled 1210 * by a software over-ride. Since there really isn't a way to 1211 * advertise that we are capable of Rx Pause ONLY, we will 1212 * advertise that we support both symmetric and asymmetric RX 1213 * PAUSE. Later, we will disable the adapter's ability to send 1214 * PAUSE frames. 1215 */ 1216 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1217 break; 1218 case e1000_fc_tx_pause: 1219 /* 1220 * Tx Flow control is enabled, and Rx Flow control is disabled, 1221 * by a software over-ride. 1222 */ 1223 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1224 break; 1225 case e1000_fc_full: 1226 /* 1227 * Flow control (both Rx and Tx) is enabled by a software 1228 * over-ride. 1229 */ 1230 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1231 break; 1232 default: 1233 DEBUGOUT("Flow control param set incorrectly\n"); 1234 ret_val = -E1000_ERR_CONFIG; 1235 goto out; 1236 break; 1237 } 1238 1239 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1240 mac->txcw = txcw; 1241 1242out: 1243 return ret_val; 1244} 1245 1246/** 1247 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1248 * @hw: pointer to the HW structure 1249 * 1250 * Sets the flow control high/low threshold (watermark) registers. If 1251 * flow control XON frame transmission is enabled, then set XON frame 1252 * transmission as well. 1253 **/ 1254s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1255{ 1256 s32 ret_val = E1000_SUCCESS; 1257 u32 fcrtl = 0, fcrth = 0; 1258 1259 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1260 1261 /* 1262 * Set the flow control receive threshold registers. Normally, 1263 * these registers will be set to a default threshold that may be 1264 * adjusted later by the driver's runtime code. However, if the 1265 * ability to transmit pause frames is not enabled, then these 1266 * registers will be set to 0. 1267 */ 1268 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1269 /* 1270 * We need to set up the Receive Threshold high and low water 1271 * marks as well as (optionally) enabling the transmission of 1272 * XON frames. 1273 */ 1274 fcrtl = hw->fc.low_water; 1275 if (hw->fc.send_xon) 1276 fcrtl |= E1000_FCRTL_XONE; 1277 1278 fcrth = hw->fc.high_water; 1279 } 1280 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1281 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1282 1283 return ret_val; 1284} 1285 1286/** 1287 * e1000_set_default_fc_generic - Set flow control default values 1288 * @hw: pointer to the HW structure 1289 * 1290 * Read the EEPROM for the default values for flow control and store the 1291 * values. 1292 **/ 1293s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1294{ 1295 s32 ret_val = E1000_SUCCESS; 1296 u16 nvm_data; 1297 1298 DEBUGFUNC("e1000_set_default_fc_generic"); 1299 1300 /* 1301 * Read and store word 0x0F of the EEPROM. This word contains bits 1302 * that determine the hardware's default PAUSE (flow control) mode, 1303 * a bit that determines whether the HW defaults to enabling or 1304 * disabling auto-negotiation, and the direction of the 1305 * SW defined pins. If there is no SW over-ride of the flow 1306 * control setting, then the variable hw->fc will 1307 * be initialized based on a value in the EEPROM. 1308 */ 1309 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1310 1311 if (ret_val) { 1312 DEBUGOUT("NVM Read Error\n"); 1313 goto out; 1314 } 1315 1316 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1317 hw->fc.requested_mode = e1000_fc_none; 1318 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1319 NVM_WORD0F_ASM_DIR) 1320 hw->fc.requested_mode = e1000_fc_tx_pause; 1321 else 1322 hw->fc.requested_mode = e1000_fc_full; 1323 1324out: 1325 return ret_val; 1326} 1327 1328/** 1329 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1330 * @hw: pointer to the HW structure 1331 * 1332 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1333 * device control register to reflect the adapter settings. TFCE and RFCE 1334 * need to be explicitly set by software when a copper PHY is used because 1335 * autonegotiation is managed by the PHY rather than the MAC. Software must 1336 * also configure these bits when link is forced on a fiber connection. 1337 **/ 1338s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1339{ 1340 u32 ctrl; 1341 s32 ret_val = E1000_SUCCESS; 1342 1343 DEBUGFUNC("e1000_force_mac_fc_generic"); 1344 1345 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1346 1347 /* 1348 * Because we didn't get link via the internal auto-negotiation 1349 * mechanism (we either forced link or we got link via PHY 1350 * auto-neg), we have to manually enable/disable transmit an 1351 * receive flow control. 1352 * 1353 * The "Case" statement below enables/disable flow control 1354 * according to the "hw->fc.current_mode" parameter. 1355 * 1356 * The possible values of the "fc" parameter are: 1357 * 0: Flow control is completely disabled 1358 * 1: Rx flow control is enabled (we can receive pause 1359 * frames but not send pause frames). 1360 * 2: Tx flow control is enabled (we can send pause frames 1361 * frames but we do not receive pause frames). 1362 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1363 * other: No other values should be possible at this point. 1364 */ 1365 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1366 1367 switch (hw->fc.current_mode) { 1368 case e1000_fc_none: 1369 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1370 break; 1371 case e1000_fc_rx_pause: 1372 ctrl &= (~E1000_CTRL_TFCE); 1373 ctrl |= E1000_CTRL_RFCE; 1374 break; 1375 case e1000_fc_tx_pause: 1376 ctrl &= (~E1000_CTRL_RFCE); 1377 ctrl |= E1000_CTRL_TFCE; 1378 break; 1379 case e1000_fc_full: 1380 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1381 break; 1382 default: 1383 DEBUGOUT("Flow control param set incorrectly\n"); 1384 ret_val = -E1000_ERR_CONFIG; 1385 goto out; 1386 } 1387 1388 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1389 1390out: 1391 return ret_val; 1392} 1393 1394/** 1395 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1396 * @hw: pointer to the HW structure 1397 * 1398 * Checks the status of auto-negotiation after link up to ensure that the 1399 * speed and duplex were not forced. If the link needed to be forced, then 1400 * flow control needs to be forced also. If auto-negotiation is enabled 1401 * and did not fail, then we configure flow control based on our link 1402 * partner. 1403 **/ 1404s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1405{ 1406 struct e1000_mac_info *mac = &hw->mac; 1407 s32 ret_val = E1000_SUCCESS; 1408 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1409 u16 speed, duplex; 1410 1411 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1412 1413 /* 1414 * Check for the case where we have fiber media and auto-neg failed 1415 * so we had to force link. In this case, we need to force the 1416 * configuration of the MAC to match the "fc" parameter. 1417 */ 1418 if (mac->autoneg_failed) { 1419 if (hw->phy.media_type == e1000_media_type_fiber || 1420 hw->phy.media_type == e1000_media_type_internal_serdes) 1421 ret_val = e1000_force_mac_fc_generic(hw); 1422 } else { 1423 if (hw->phy.media_type == e1000_media_type_copper) 1424 ret_val = e1000_force_mac_fc_generic(hw); 1425 } 1426 1427 if (ret_val) { 1428 DEBUGOUT("Error forcing flow control settings\n"); 1429 goto out; 1430 } 1431 1432 /* 1433 * Check for the case where we have copper media and auto-neg is 1434 * enabled. In this case, we need to check and see if Auto-Neg 1435 * has completed, and if so, how the PHY and link partner has 1436 * flow control configured. 1437 */ 1438 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1439 /* 1440 * Read the MII Status Register and check to see if AutoNeg 1441 * has completed. We read this twice because this reg has 1442 * some "sticky" (latched) bits. 1443 */ 1444 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1445 if (ret_val) 1446 goto out; 1447 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1448 if (ret_val) 1449 goto out; 1450 1451 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1452 DEBUGOUT("Copper PHY and Auto Neg " 1453 "has not completed.\n"); 1454 goto out; 1455 } 1456 1457 /* 1458 * The AutoNeg process has completed, so we now need to 1459 * read both the Auto Negotiation Advertisement 1460 * Register (Address 4) and the Auto_Negotiation Base 1461 * Page Ability Register (Address 5) to determine how 1462 * flow control was negotiated. 1463 */ 1464 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1465 &mii_nway_adv_reg); 1466 if (ret_val) 1467 goto out; 1468 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1469 &mii_nway_lp_ability_reg); 1470 if (ret_val) 1471 goto out; 1472 1473 /* 1474 * Two bits in the Auto Negotiation Advertisement Register 1475 * (Address 4) and two bits in the Auto Negotiation Base 1476 * Page Ability Register (Address 5) determine flow control 1477 * for both the PHY and the link partner. The following 1478 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1479 * 1999, describes these PAUSE resolution bits and how flow 1480 * control is determined based upon these settings. 1481 * NOTE: DC = Don't Care 1482 * 1483 * LOCAL DEVICE | LINK PARTNER 1484 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1485 *-------|---------|-------|---------|-------------------- 1486 * 0 | 0 | DC | DC | e1000_fc_none 1487 * 0 | 1 | 0 | DC | e1000_fc_none 1488 * 0 | 1 | 1 | 0 | e1000_fc_none 1489 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1490 * 1 | 0 | 0 | DC | e1000_fc_none 1491 * 1 | DC | 1 | DC | e1000_fc_full 1492 * 1 | 1 | 0 | 0 | e1000_fc_none 1493 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1494 * 1495 * Are both PAUSE bits set to 1? If so, this implies 1496 * Symmetric Flow Control is enabled at both ends. The 1497 * ASM_DIR bits are irrelevant per the spec. 1498 * 1499 * For Symmetric Flow Control: 1500 * 1501 * LOCAL DEVICE | LINK PARTNER 1502 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1503 *-------|---------|-------|---------|-------------------- 1504 * 1 | DC | 1 | DC | E1000_fc_full 1505 * 1506 */ 1507 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1508 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1509 /* 1510 * Now we need to check if the user selected Rx ONLY 1511 * of pause frames. In this case, we had to advertise 1512 * FULL flow control because we could not advertise Rx 1513 * ONLY. Hence, we must now check to see if we need to 1514 * turn OFF the TRANSMISSION of PAUSE frames. 1515 */ 1516 if (hw->fc.requested_mode == e1000_fc_full) { 1517 hw->fc.current_mode = e1000_fc_full; 1518 DEBUGOUT("Flow Control = FULL.\r\n"); 1519 } else { 1520 hw->fc.current_mode = e1000_fc_rx_pause; 1521 DEBUGOUT("Flow Control = " 1522 "RX PAUSE frames only.\r\n"); 1523 } 1524 } 1525 /* 1526 * For receiving PAUSE frames ONLY. 1527 * 1528 * LOCAL DEVICE | LINK PARTNER 1529 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1530 *-------|---------|-------|---------|-------------------- 1531 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1532 */ 1533 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1534 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1535 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1536 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1537 hw->fc.current_mode = e1000_fc_tx_pause; 1538 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1539 } 1540 /* 1541 * For transmitting PAUSE frames ONLY. 1542 * 1543 * LOCAL DEVICE | LINK PARTNER 1544 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1545 *-------|---------|-------|---------|-------------------- 1546 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1547 */ 1548 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1549 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1550 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1551 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1552 hw->fc.current_mode = e1000_fc_rx_pause; 1553 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1554 } else { 1555 /* 1556 * Per the IEEE spec, at this point flow control 1557 * should be disabled. 1558 */ 1559 hw->fc.current_mode = e1000_fc_none; 1560 DEBUGOUT("Flow Control = NONE.\r\n"); 1561 } 1562 1563 /* 1564 * Now we need to do one last check... If we auto- 1565 * negotiated to HALF DUPLEX, flow control should not be 1566 * enabled per IEEE 802.3 spec. 1567 */ 1568 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1569 if (ret_val) { 1570 DEBUGOUT("Error getting link speed and duplex\n"); 1571 goto out; 1572 } 1573 1574 if (duplex == HALF_DUPLEX) 1575 hw->fc.current_mode = e1000_fc_none; 1576 1577 /* 1578 * Now we call a subroutine to actually force the MAC 1579 * controller to use the correct flow control settings. 1580 */ 1581 ret_val = e1000_force_mac_fc_generic(hw); 1582 if (ret_val) { 1583 DEBUGOUT("Error forcing flow control settings\n"); 1584 goto out; 1585 } 1586 } 1587 1588out: 1589 return ret_val; 1590} 1591 1592/** 1593 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1594 * @hw: pointer to the HW structure 1595 * @speed: stores the current speed 1596 * @duplex: stores the current duplex 1597 * 1598 * Read the status register for the current speed/duplex and store the current 1599 * speed and duplex for copper connections. 1600 **/ 1601s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1602 u16 *duplex) 1603{ 1604 u32 status; 1605 1606 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1607 1608 status = E1000_READ_REG(hw, E1000_STATUS); 1609 if (status & E1000_STATUS_SPEED_1000) { 1610 *speed = SPEED_1000; 1611 DEBUGOUT("1000 Mbs, "); 1612 } else if (status & E1000_STATUS_SPEED_100) { 1613 *speed = SPEED_100; 1614 DEBUGOUT("100 Mbs, "); 1615 } else { 1616 *speed = SPEED_10; 1617 DEBUGOUT("10 Mbs, "); 1618 } 1619 1620 if (status & E1000_STATUS_FD) { 1621 *duplex = FULL_DUPLEX; 1622 DEBUGOUT("Full Duplex\n"); 1623 } else { 1624 *duplex = HALF_DUPLEX; 1625 DEBUGOUT("Half Duplex\n"); 1626 } 1627 1628 return E1000_SUCCESS; 1629} 1630 1631/** 1632 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1633 * @hw: pointer to the HW structure 1634 * @speed: stores the current speed 1635 * @duplex: stores the current duplex 1636 * 1637 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1638 * for fiber/serdes links. 1639 **/ 1640s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1641 u16 *speed, u16 *duplex) 1642{ 1643 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1644 1645 *speed = SPEED_1000; 1646 *duplex = FULL_DUPLEX; 1647 1648 return E1000_SUCCESS; 1649} 1650 1651/** 1652 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1653 * @hw: pointer to the HW structure 1654 * 1655 * Acquire the HW semaphore to access the PHY or NVM 1656 **/ 1657s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1658{ 1659 u32 swsm; 1660 s32 ret_val = E1000_SUCCESS; 1661 s32 timeout = hw->nvm.word_size + 1; 1662 s32 i = 0; 1663 1664 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1665 1666 /* Get the SW semaphore */ 1667 while (i < timeout) { 1668 swsm = E1000_READ_REG(hw, E1000_SWSM); 1669 if (!(swsm & E1000_SWSM_SMBI)) 1670 break; 1671 1672 usec_delay(50); 1673 i++; 1674 } 1675 1676 if (i == timeout) { 1677 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1678 ret_val = -E1000_ERR_NVM; 1679 goto out; 1680 } 1681 1682 /* Get the FW semaphore. */ 1683 for (i = 0; i < timeout; i++) { 1684 swsm = E1000_READ_REG(hw, E1000_SWSM); 1685 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1686 1687 /* Semaphore acquired if bit latched */ 1688 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1689 break; 1690 1691 usec_delay(50); 1692 } 1693 1694 if (i == timeout) { 1695 /* Release semaphores */ 1696 e1000_put_hw_semaphore_generic(hw); 1697 DEBUGOUT("Driver can't access the NVM\n"); 1698 ret_val = -E1000_ERR_NVM; 1699 goto out; 1700 } 1701 1702out: 1703 return ret_val; 1704} 1705 1706/** 1707 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1708 * @hw: pointer to the HW structure 1709 * 1710 * Release hardware semaphore used to access the PHY or NVM 1711 **/ 1712void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1713{ 1714 u32 swsm; 1715 1716 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1717 1718 swsm = E1000_READ_REG(hw, E1000_SWSM); 1719 1720 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1721 1722 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1723} 1724 1725/** 1726 * e1000_get_auto_rd_done_generic - Check for auto read completion 1727 * @hw: pointer to the HW structure 1728 * 1729 * Check EEPROM for Auto Read done bit. 1730 **/ 1731s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1732{ 1733 s32 i = 0; 1734 s32 ret_val = E1000_SUCCESS; 1735 1736 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1737 1738 while (i < AUTO_READ_DONE_TIMEOUT) { 1739 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1740 break; 1741 msec_delay(1); 1742 i++; 1743 } 1744 1745 if (i == AUTO_READ_DONE_TIMEOUT) { 1746 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1747 ret_val = -E1000_ERR_RESET; 1748 goto out; 1749 } 1750 1751out: 1752 return ret_val; 1753} 1754 1755/** 1756 * e1000_valid_led_default_generic - Verify a valid default LED config 1757 * @hw: pointer to the HW structure 1758 * @data: pointer to the NVM (EEPROM) 1759 * 1760 * Read the EEPROM for the current default LED configuration. If the 1761 * LED configuration is not valid, set to a valid LED configuration. 1762 **/ 1763s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1764{ 1765 s32 ret_val; 1766 1767 DEBUGFUNC("e1000_valid_led_default_generic"); 1768 1769 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1770 if (ret_val) { 1771 DEBUGOUT("NVM Read Error\n"); 1772 goto out; 1773 } 1774 1775 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1776 *data = ID_LED_DEFAULT; 1777 1778out: 1779 return ret_val; 1780} 1781 1782/** 1783 * e1000_id_led_init_generic - 1784 * @hw: pointer to the HW structure 1785 * 1786 **/ 1787s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1788{ 1789 struct e1000_mac_info *mac = &hw->mac; 1790 s32 ret_val; 1791 const u32 ledctl_mask = 0x000000FF; 1792 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1793 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1794 u16 data, i, temp; 1795 const u16 led_mask = 0x0F; 1796 1797 DEBUGFUNC("e1000_id_led_init_generic"); 1798 1799 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1800 if (ret_val) 1801 goto out; 1802 1803 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1804 mac->ledctl_mode1 = mac->ledctl_default; 1805 mac->ledctl_mode2 = mac->ledctl_default; 1806 1807 for (i = 0; i < 4; i++) { 1808 temp = (data >> (i << 2)) & led_mask; 1809 switch (temp) { 1810 case ID_LED_ON1_DEF2: 1811 case ID_LED_ON1_ON2: 1812 case ID_LED_ON1_OFF2: 1813 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1814 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1815 break; 1816 case ID_LED_OFF1_DEF2: 1817 case ID_LED_OFF1_ON2: 1818 case ID_LED_OFF1_OFF2: 1819 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1820 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1821 break; 1822 default: 1823 /* Do nothing */ 1824 break; 1825 } 1826 switch (temp) { 1827 case ID_LED_DEF1_ON2: 1828 case ID_LED_ON1_ON2: 1829 case ID_LED_OFF1_ON2: 1830 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1831 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1832 break; 1833 case ID_LED_DEF1_OFF2: 1834 case ID_LED_ON1_OFF2: 1835 case ID_LED_OFF1_OFF2: 1836 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1837 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1838 break; 1839 default: 1840 /* Do nothing */ 1841 break; 1842 } 1843 } 1844 1845out: 1846 return ret_val; 1847} 1848 1849/** 1850 * e1000_setup_led_generic - Configures SW controllable LED 1851 * @hw: pointer to the HW structure 1852 * 1853 * This prepares the SW controllable LED for use and saves the current state 1854 * of the LED so it can be later restored. 1855 **/ 1856s32 e1000_setup_led_generic(struct e1000_hw *hw) 1857{ 1858 u32 ledctl; 1859 s32 ret_val = E1000_SUCCESS; 1860 1861 DEBUGFUNC("e1000_setup_led_generic"); 1862 1863 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1864 ret_val = -E1000_ERR_CONFIG; 1865 goto out; 1866 } 1867 1868 if (hw->phy.media_type == e1000_media_type_fiber) { 1869 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1870 hw->mac.ledctl_default = ledctl; 1871 /* Turn off LED0 */ 1872 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1873 E1000_LEDCTL_LED0_BLINK | 1874 E1000_LEDCTL_LED0_MODE_MASK); 1875 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1876 E1000_LEDCTL_LED0_MODE_SHIFT); 1877 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1878 } else if (hw->phy.media_type == e1000_media_type_copper) { 1879 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1880 } 1881 1882out: 1883 return ret_val; 1884} 1885 1886/** 1887 * e1000_cleanup_led_generic - Set LED config to default operation 1888 * @hw: pointer to the HW structure 1889 * 1890 * Remove the current LED configuration and set the LED configuration 1891 * to the default value, saved from the EEPROM. 1892 **/ 1893s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1894{ 1895 s32 ret_val = E1000_SUCCESS; 1896 1897 DEBUGFUNC("e1000_cleanup_led_generic"); 1898 1899 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1900 ret_val = -E1000_ERR_CONFIG; 1901 goto out; 1902 } 1903 1904 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1905 1906out: 1907 return ret_val; 1908} 1909 1910/** 1911 * e1000_blink_led_generic - Blink LED 1912 * @hw: pointer to the HW structure 1913 * 1914 * Blink the LEDs which are set to be on. 1915 **/ 1916s32 e1000_blink_led_generic(struct e1000_hw *hw) 1917{ 1918 u32 ledctl_blink = 0; 1919 u32 i; 1920 1921 DEBUGFUNC("e1000_blink_led_generic"); 1922 1923 if (hw->phy.media_type == e1000_media_type_fiber) { 1924 /* always blink LED0 for PCI-E fiber */ 1925 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1926 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1927 } else { 1928 /* 1929 * set the blink bit for each LED that's "on" (0x0E) 1930 * in ledctl_mode2 1931 */ 1932 ledctl_blink = hw->mac.ledctl_mode2; 1933 for (i = 0; i < 4; i++) 1934 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1935 E1000_LEDCTL_MODE_LED_ON) 1936 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1937 (i * 8)); 1938 } 1939 1940 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1941 1942 return E1000_SUCCESS; 1943} 1944 1945/** 1946 * e1000_led_on_generic - Turn LED on 1947 * @hw: pointer to the HW structure 1948 * 1949 * Turn LED on. 1950 **/ 1951s32 e1000_led_on_generic(struct e1000_hw *hw) 1952{ 1953 u32 ctrl; 1954 1955 DEBUGFUNC("e1000_led_on_generic"); 1956 1957 switch (hw->phy.media_type) { 1958 case e1000_media_type_fiber: 1959 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1960 ctrl &= ~E1000_CTRL_SWDPIN0; 1961 ctrl |= E1000_CTRL_SWDPIO0; 1962 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1963 break; 1964 case e1000_media_type_copper: 1965 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1966 break; 1967 default: 1968 break; 1969 } 1970 1971 return E1000_SUCCESS; 1972} 1973 1974/** 1975 * e1000_led_off_generic - Turn LED off 1976 * @hw: pointer to the HW structure 1977 * 1978 * Turn LED off. 1979 **/ 1980s32 e1000_led_off_generic(struct e1000_hw *hw) 1981{ 1982 u32 ctrl; 1983 1984 DEBUGFUNC("e1000_led_off_generic"); 1985 1986 switch (hw->phy.media_type) { 1987 case e1000_media_type_fiber: 1988 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1989 ctrl |= E1000_CTRL_SWDPIN0; 1990 ctrl |= E1000_CTRL_SWDPIO0; 1991 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1992 break; 1993 case e1000_media_type_copper: 1994 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1995 break; 1996 default: 1997 break; 1998 } 1999 2000 return E1000_SUCCESS; 2001} 2002 2003/** 2004 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2005 * @hw: pointer to the HW structure 2006 * @no_snoop: bitmap of snoop events 2007 * 2008 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2009 **/ 2010void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2011{ 2012 u32 gcr; 2013 2014 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2015 2016 if (hw->bus.type != e1000_bus_type_pci_express) 2017 goto out; 2018 2019 if (no_snoop) { 2020 gcr = E1000_READ_REG(hw, E1000_GCR); 2021 gcr &= ~(PCIE_NO_SNOOP_ALL); 2022 gcr |= no_snoop; 2023 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2024 } 2025out: 2026 return; 2027} 2028 2029/** 2030 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2031 * @hw: pointer to the HW structure 2032 * 2033 * Returns E1000_SUCCESS if successful, else returns -10 2034 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2035 * the master requests to be disabled. 2036 * 2037 * Disables PCI-Express master access and verifies there are no pending 2038 * requests. 2039 **/ 2040s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2041{ 2042 u32 ctrl; 2043 s32 timeout = MASTER_DISABLE_TIMEOUT; 2044 s32 ret_val = E1000_SUCCESS; 2045 2046 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2047 2048 if (hw->bus.type != e1000_bus_type_pci_express) 2049 goto out; 2050 2051 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2052 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2053 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2054 2055 while (timeout) { 2056 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2057 E1000_STATUS_GIO_MASTER_ENABLE)) 2058 break; 2059 usec_delay(100); 2060 timeout--; 2061 } 2062 2063 if (!timeout) { 2064 DEBUGOUT("Master requests are pending.\n"); 2065 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2066 goto out; 2067 } 2068 2069out: 2070 return ret_val; 2071} 2072 2073/** 2074 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2075 * @hw: pointer to the HW structure 2076 * 2077 * Reset the Adaptive Interframe Spacing throttle to default values. 2078 **/ 2079void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2080{ 2081 struct e1000_mac_info *mac = &hw->mac; 2082 2083 DEBUGFUNC("e1000_reset_adaptive_generic"); 2084 2085 if (!mac->adaptive_ifs) { 2086 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2087 goto out; 2088 } 2089 2090 mac->current_ifs_val = 0; 2091 mac->ifs_min_val = IFS_MIN; 2092 mac->ifs_max_val = IFS_MAX; 2093 mac->ifs_step_size = IFS_STEP; 2094 mac->ifs_ratio = IFS_RATIO; 2095 2096 mac->in_ifs_mode = FALSE; 2097 E1000_WRITE_REG(hw, E1000_AIT, 0); 2098out: 2099 return; 2100} 2101 2102/** 2103 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2104 * @hw: pointer to the HW structure 2105 * 2106 * Update the Adaptive Interframe Spacing Throttle value based on the 2107 * time between transmitted packets and time between collisions. 2108 **/ 2109void e1000_update_adaptive_generic(struct e1000_hw *hw) 2110{ 2111 struct e1000_mac_info *mac = &hw->mac; 2112 2113 DEBUGFUNC("e1000_update_adaptive_generic"); 2114 2115 if (!mac->adaptive_ifs) { 2116 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2117 goto out; 2118 } 2119 2120 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2121 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2122 mac->in_ifs_mode = TRUE; 2123 if (mac->current_ifs_val < mac->ifs_max_val) { 2124 if (!mac->current_ifs_val) 2125 mac->current_ifs_val = mac->ifs_min_val; 2126 else 2127 mac->current_ifs_val += 2128 mac->ifs_step_size; 2129 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2130 } 2131 } 2132 } else { 2133 if (mac->in_ifs_mode && 2134 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2135 mac->current_ifs_val = 0; 2136 mac->in_ifs_mode = FALSE; 2137 E1000_WRITE_REG(hw, E1000_AIT, 0); 2138 } 2139 } 2140out: 2141 return; 2142} 2143 2144/** 2145 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2146 * @hw: pointer to the HW structure 2147 * 2148 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2149 * set, which is forced to MDI mode only. 2150 **/ 2151static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2152{ 2153 s32 ret_val = E1000_SUCCESS; 2154 2155 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2156 2157 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2158 DEBUGOUT("Invalid MDI setting detected\n"); 2159 hw->phy.mdix = 1; 2160 ret_val = -E1000_ERR_CONFIG; 2161 goto out; 2162 } 2163 2164out: 2165 return ret_val; 2166} 2167 2168/** 2169 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2170 * @hw: pointer to the HW structure 2171 * @reg: 32bit register offset such as E1000_SCTL 2172 * @offset: register offset to write to 2173 * @data: data to write at register offset 2174 * 2175 * Writes an address/data control type register. There are several of these 2176 * and they all have the format address << 8 | data and bit 31 is polled for 2177 * completion. 2178 **/ 2179s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2180 u32 offset, u8 data) 2181{ 2182 u32 i, regvalue = 0; 2183 s32 ret_val = E1000_SUCCESS; 2184 2185 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2186 2187 /* Set up the address and data */ 2188 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2189 E1000_WRITE_REG(hw, reg, regvalue); 2190 2191 /* Poll the ready bit to see if the MDI read completed */ 2192 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2193 usec_delay(5); 2194 regvalue = E1000_READ_REG(hw, reg); 2195 if (regvalue & E1000_GEN_CTL_READY) 2196 break; 2197 } 2198 if (!(regvalue & E1000_GEN_CTL_READY)) { 2199 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2200 ret_val = -E1000_ERR_PHY; 2201 goto out; 2202 } 2203 2204out: 2205 return ret_val; 2206} 2207