e1000_mac.c revision 190872
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 190872 2009-04-10 00:05:46Z jfv $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.mta_set = e1000_null_mta_set; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84} 85 86/** 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 **/ 90s32 e1000_null_ops_generic(struct e1000_hw *hw) 91{ 92 DEBUGFUNC("e1000_null_ops_generic"); 93 return E1000_SUCCESS; 94} 95 96/** 97 * e1000_null_mac_generic - No-op function, return void 98 * @hw: pointer to the HW structure 99 **/ 100void e1000_null_mac_generic(struct e1000_hw *hw) 101{ 102 DEBUGFUNC("e1000_null_mac_generic"); 103 return; 104} 105 106/** 107 * e1000_null_link_info - No-op function, return 0 108 * @hw: pointer to the HW structure 109 **/ 110s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 111{ 112 DEBUGFUNC("e1000_null_link_info"); 113 return E1000_SUCCESS; 114} 115 116/** 117 * e1000_null_mng_mode - No-op function, return FALSE 118 * @hw: pointer to the HW structure 119 **/ 120bool e1000_null_mng_mode(struct e1000_hw *hw) 121{ 122 DEBUGFUNC("e1000_null_mng_mode"); 123 return FALSE; 124} 125 126/** 127 * e1000_null_update_mc - No-op function, return void 128 * @hw: pointer to the HW structure 129 **/ 130void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 131{ 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134} 135 136/** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 141{ 142 DEBUGFUNC("e1000_null_write_vfta"); 143 return; 144} 145 146/** 147 * e1000_null_set_mta - No-op function, return void 148 * @hw: pointer to the HW structure 149 **/ 150void e1000_null_mta_set(struct e1000_hw *hw, u32 a) 151{ 152 DEBUGFUNC("e1000_null_mta_set"); 153 return; 154} 155 156/** 157 * e1000_null_rar_set - No-op function, return void 158 * @hw: pointer to the HW structure 159 **/ 160void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 161{ 162 DEBUGFUNC("e1000_null_rar_set"); 163 return; 164} 165 166/** 167 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 168 * @hw: pointer to the HW structure 169 * 170 * Determines and stores the system bus information for a particular 171 * network interface. The following bus information is determined and stored: 172 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 173 **/ 174s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 175{ 176 struct e1000_mac_info *mac = &hw->mac; 177 struct e1000_bus_info *bus = &hw->bus; 178 u32 status = E1000_READ_REG(hw, E1000_STATUS); 179 s32 ret_val = E1000_SUCCESS; 180 181 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 182 183 /* PCI or PCI-X? */ 184 bus->type = (status & E1000_STATUS_PCIX_MODE) 185 ? e1000_bus_type_pcix 186 : e1000_bus_type_pci; 187 188 /* Bus speed */ 189 if (bus->type == e1000_bus_type_pci) { 190 bus->speed = (status & E1000_STATUS_PCI66) 191 ? e1000_bus_speed_66 192 : e1000_bus_speed_33; 193 } else { 194 switch (status & E1000_STATUS_PCIX_SPEED) { 195 case E1000_STATUS_PCIX_SPEED_66: 196 bus->speed = e1000_bus_speed_66; 197 break; 198 case E1000_STATUS_PCIX_SPEED_100: 199 bus->speed = e1000_bus_speed_100; 200 break; 201 case E1000_STATUS_PCIX_SPEED_133: 202 bus->speed = e1000_bus_speed_133; 203 break; 204 default: 205 bus->speed = e1000_bus_speed_reserved; 206 break; 207 } 208 } 209 210 /* Bus width */ 211 bus->width = (status & E1000_STATUS_BUS64) 212 ? e1000_bus_width_64 213 : e1000_bus_width_32; 214 215 /* Which PCI(-X) function? */ 216 mac->ops.set_lan_id(hw); 217 218 return ret_val; 219} 220 221/** 222 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 223 * @hw: pointer to the HW structure 224 * 225 * Determines and stores the system bus information for a particular 226 * network interface. The following bus information is determined and stored: 227 * bus speed, bus width, type (PCIe), and PCIe function. 228 **/ 229s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 230{ 231 struct e1000_mac_info *mac = &hw->mac; 232 struct e1000_bus_info *bus = &hw->bus; 233 234 s32 ret_val; 235 u16 pcie_link_status; 236 237 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 238 239 bus->type = e1000_bus_type_pci_express; 240 bus->speed = e1000_bus_speed_2500; 241 242 ret_val = e1000_read_pcie_cap_reg(hw, 243 PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) 246 bus->width = e1000_bus_width_unknown; 247 else 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> 250 PCIE_LINK_WIDTH_SHIFT); 251 252 mac->ops.set_lan_id(hw); 253 254 return E1000_SUCCESS; 255} 256 257/** 258 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 259 * 260 * @hw: pointer to the HW structure 261 * 262 * Determines the LAN function id by reading memory-mapped registers 263 * and swaps the port value if requested. 264 **/ 265static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 266{ 267 struct e1000_bus_info *bus = &hw->bus; 268 u32 reg; 269 270 /* 271 * The status register reports the correct function number 272 * for the device regardless of function swap state. 273 */ 274 reg = E1000_READ_REG(hw, E1000_STATUS); 275 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 276} 277 278/** 279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 280 * @hw: pointer to the HW structure 281 * 282 * Determines the LAN function id by reading PCI config space. 283 **/ 284void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 285{ 286 struct e1000_bus_info *bus = &hw->bus; 287 u16 pci_header_type; 288 u32 status; 289 290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 292 status = E1000_READ_REG(hw, E1000_STATUS); 293 bus->func = (status & E1000_STATUS_FUNC_MASK) 294 >> E1000_STATUS_FUNC_SHIFT; 295 } else { 296 bus->func = 0; 297 } 298} 299 300/** 301 * e1000_set_lan_id_single_port - Set LAN id for a single port device 302 * @hw: pointer to the HW structure 303 * 304 * Sets the LAN function id to zero for a single port device. 305 **/ 306void e1000_set_lan_id_single_port(struct e1000_hw *hw) 307{ 308 struct e1000_bus_info *bus = &hw->bus; 309 310 bus->func = 0; 311} 312 313/** 314 * e1000_clear_vfta_generic - Clear VLAN filter table 315 * @hw: pointer to the HW structure 316 * 317 * Clears the register array which contains the VLAN filter table by 318 * setting all the values to 0. 319 **/ 320void e1000_clear_vfta_generic(struct e1000_hw *hw) 321{ 322 u32 offset; 323 324 DEBUGFUNC("e1000_clear_vfta_generic"); 325 326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 328 E1000_WRITE_FLUSH(hw); 329 } 330} 331 332/** 333 * e1000_write_vfta_generic - Write value to VLAN filter table 334 * @hw: pointer to the HW structure 335 * @offset: register offset in VLAN filter table 336 * @value: register value written to VLAN filter table 337 * 338 * Writes value at the given offset in the register array which stores 339 * the VLAN filter table. 340 **/ 341void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 342{ 343 DEBUGFUNC("e1000_write_vfta_generic"); 344 345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 346 E1000_WRITE_FLUSH(hw); 347} 348 349/** 350 * e1000_init_rx_addrs_generic - Initialize receive address's 351 * @hw: pointer to the HW structure 352 * @rar_count: receive address registers 353 * 354 * Setups the receive address registers by setting the base receive address 355 * register to the devices MAC address and clearing all the other receive 356 * address registers to 0. 357 **/ 358void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 359{ 360 u32 i; 361 u8 mac_addr[ETH_ADDR_LEN] = {0}; 362 363 DEBUGFUNC("e1000_init_rx_addrs_generic"); 364 365 /* Setup the receive address */ 366 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 367 368 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 369 370 /* Zero out the other (rar_entry_count - 1) receive addresses */ 371 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 372 for (i = 1; i < rar_count; i++) 373 hw->mac.ops.rar_set(hw, mac_addr, i); 374} 375 376/** 377 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 378 * @hw: pointer to the HW structure 379 * 380 * Checks the nvm for an alternate MAC address. An alternate MAC address 381 * can be setup by pre-boot software and must be treated like a permanent 382 * address and must override the actual permanent MAC address. If an 383 * alternate MAC address is found it is programmed into RAR0, replacing 384 * the permanent address that was installed into RAR0 by the Si on reset. 385 * This function will return SUCCESS unless it encounters an error while 386 * reading the EEPROM. 387 **/ 388s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 389{ 390 u32 i; 391 s32 ret_val = E1000_SUCCESS; 392 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 393 u8 alt_mac_addr[ETH_ADDR_LEN]; 394 395 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 396 397 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 398 &nvm_alt_mac_addr_offset); 399 if (ret_val) { 400 DEBUGOUT("NVM Read Error\n"); 401 goto out; 402 } 403 404 if (nvm_alt_mac_addr_offset == 0xFFFF) { 405 /* There is no Alternate MAC Address */ 406 goto out; 407 } 408 409 if (hw->bus.func == E1000_FUNC_1) 410 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 411 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 412 offset = nvm_alt_mac_addr_offset + (i >> 1); 413 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 414 if (ret_val) { 415 DEBUGOUT("NVM Read Error\n"); 416 goto out; 417 } 418 419 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 420 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 421 } 422 423 /* if multicast bit is set, the alternate address will not be used */ 424 if (alt_mac_addr[0] & 0x01) { 425 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 426 goto out; 427 } 428 429 /* 430 * We have a valid alternate MAC address, and we want to treat it the 431 * same as the normal permanent MAC address stored by the HW into the 432 * RAR. Do this by mapping this address into RAR0. 433 */ 434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 435 436out: 437 return ret_val; 438} 439 440/** 441 * e1000_rar_set_generic - Set receive address register 442 * @hw: pointer to the HW structure 443 * @addr: pointer to the receive address 444 * @index: receive address array register 445 * 446 * Sets the receive address array register at index to the address passed 447 * in by addr. 448 **/ 449void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 450{ 451 u32 rar_low, rar_high; 452 453 DEBUGFUNC("e1000_rar_set_generic"); 454 455 /* 456 * HW expects these in little endian so we reverse the byte order 457 * from network order (big endian) to little endian 458 */ 459 rar_low = ((u32) addr[0] | 460 ((u32) addr[1] << 8) | 461 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 462 463 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 464 465 /* If MAC address zero, no need to set the AV bit */ 466 if (rar_low || rar_high) 467 rar_high |= E1000_RAH_AV; 468 469 /* 470 * Some bridges will combine consecutive 32-bit writes into 471 * a single burst write, which will malfunction on some parts. 472 * The flushes avoid this. 473 */ 474 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 475 E1000_WRITE_FLUSH(hw); 476 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 477 E1000_WRITE_FLUSH(hw); 478} 479 480/** 481 * e1000_mta_set_generic - Set multicast filter table address 482 * @hw: pointer to the HW structure 483 * @hash_value: determines the MTA register and bit to set 484 * 485 * The multicast table address is a register array of 32-bit registers. 486 * The hash_value is used to determine what register the bit is in, the 487 * current value is read, the new bit is OR'd in and the new value is 488 * written back into the register. 489 **/ 490void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 491{ 492 u32 hash_bit, hash_reg, mta; 493 494 DEBUGFUNC("e1000_mta_set_generic"); 495 /* 496 * The MTA is a register array of 32-bit registers. It is 497 * treated like an array of (32*mta_reg_count) bits. We want to 498 * set bit BitArray[hash_value]. So we figure out what register 499 * the bit is in, read it, OR in the new bit, then write 500 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 501 * mask to bits 31:5 of the hash value which gives us the 502 * register we're modifying. The hash bit within that register 503 * is determined by the lower 5 bits of the hash value. 504 */ 505 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 506 hash_bit = hash_value & 0x1F; 507 508 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 509 510 mta |= (1 << hash_bit); 511 512 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 513 E1000_WRITE_FLUSH(hw); 514} 515 516/** 517 * e1000_update_mc_addr_list_generic - Update Multicast addresses 518 * @hw: pointer to the HW structure 519 * @mc_addr_list: array of multicast addresses to program 520 * @mc_addr_count: number of multicast addresses to program 521 * 522 * Updates entire Multicast Table Array. 523 * The caller must have a packed mc_addr_list of multicast addresses. 524 **/ 525void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 526 u8 *mc_addr_list, u32 mc_addr_count) 527{ 528 u32 hash_value, hash_bit, hash_reg; 529 int i; 530 531 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 532 533 /* clear mta_shadow */ 534 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 535 536 /* update mta_shadow from mc_addr_list */ 537 for (i = 0; (u32) i < mc_addr_count; i++) { 538 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 539 540 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 541 hash_bit = hash_value & 0x1F; 542 543 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 544 mc_addr_list += (ETH_ADDR_LEN); 545 } 546 547 /* replace the entire MTA table */ 548 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 549 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 550 E1000_WRITE_FLUSH(hw); 551} 552 553/** 554 * e1000_hash_mc_addr_generic - Generate a multicast hash value 555 * @hw: pointer to the HW structure 556 * @mc_addr: pointer to a multicast address 557 * 558 * Generates a multicast address hash value which is used to determine 559 * the multicast filter table array address and new table value. See 560 * e1000_mta_set_generic() 561 **/ 562u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 563{ 564 u32 hash_value, hash_mask; 565 u8 bit_shift = 0; 566 567 DEBUGFUNC("e1000_hash_mc_addr_generic"); 568 569 /* Register count multiplied by bits per register */ 570 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 571 572 /* 573 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 574 * where 0xFF would still fall within the hash mask. 575 */ 576 while (hash_mask >> bit_shift != 0xFF) 577 bit_shift++; 578 579 /* 580 * The portion of the address that is used for the hash table 581 * is determined by the mc_filter_type setting. 582 * The algorithm is such that there is a total of 8 bits of shifting. 583 * The bit_shift for a mc_filter_type of 0 represents the number of 584 * left-shifts where the MSB of mc_addr[5] would still fall within 585 * the hash_mask. Case 0 does this exactly. Since there are a total 586 * of 8 bits of shifting, then mc_addr[4] will shift right the 587 * remaining number of bits. Thus 8 - bit_shift. The rest of the 588 * cases are a variation of this algorithm...essentially raising the 589 * number of bits to shift mc_addr[5] left, while still keeping the 590 * 8-bit shifting total. 591 * 592 * For example, given the following Destination MAC Address and an 593 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 594 * we can see that the bit_shift for case 0 is 4. These are the hash 595 * values resulting from each mc_filter_type... 596 * [0] [1] [2] [3] [4] [5] 597 * 01 AA 00 12 34 56 598 * LSB MSB 599 * 600 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 601 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 602 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 603 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 604 */ 605 switch (hw->mac.mc_filter_type) { 606 default: 607 case 0: 608 break; 609 case 1: 610 bit_shift += 1; 611 break; 612 case 2: 613 bit_shift += 2; 614 break; 615 case 3: 616 bit_shift += 4; 617 break; 618 } 619 620 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 621 (((u16) mc_addr[5]) << bit_shift))); 622 623 return hash_value; 624} 625 626/** 627 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 628 * @hw: pointer to the HW structure 629 * 630 * In certain situations, a system BIOS may report that the PCIx maximum 631 * memory read byte count (MMRBC) value is higher than than the actual 632 * value. We check the PCIx command register with the current PCIx status 633 * register. 634 **/ 635void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 636{ 637 u16 cmd_mmrbc; 638 u16 pcix_cmd; 639 u16 pcix_stat_hi_word; 640 u16 stat_mmrbc; 641 642 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 643 644 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 645 if (hw->bus.type != e1000_bus_type_pcix) 646 return; 647 648 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 650 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 651 PCIX_COMMAND_MMRBC_SHIFT; 652 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 653 PCIX_STATUS_HI_MMRBC_SHIFT; 654 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 655 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 656 if (cmd_mmrbc > stat_mmrbc) { 657 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 658 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 659 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 660 } 661} 662 663/** 664 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 665 * @hw: pointer to the HW structure 666 * 667 * Clears the base hardware counters by reading the counter registers. 668 **/ 669void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 670{ 671 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 672 673 E1000_READ_REG(hw, E1000_CRCERRS); 674 E1000_READ_REG(hw, E1000_SYMERRS); 675 E1000_READ_REG(hw, E1000_MPC); 676 E1000_READ_REG(hw, E1000_SCC); 677 E1000_READ_REG(hw, E1000_ECOL); 678 E1000_READ_REG(hw, E1000_MCC); 679 E1000_READ_REG(hw, E1000_LATECOL); 680 E1000_READ_REG(hw, E1000_COLC); 681 E1000_READ_REG(hw, E1000_DC); 682 E1000_READ_REG(hw, E1000_SEC); 683 E1000_READ_REG(hw, E1000_RLEC); 684 E1000_READ_REG(hw, E1000_XONRXC); 685 E1000_READ_REG(hw, E1000_XONTXC); 686 E1000_READ_REG(hw, E1000_XOFFRXC); 687 E1000_READ_REG(hw, E1000_XOFFTXC); 688 E1000_READ_REG(hw, E1000_FCRUC); 689 E1000_READ_REG(hw, E1000_GPRC); 690 E1000_READ_REG(hw, E1000_BPRC); 691 E1000_READ_REG(hw, E1000_MPRC); 692 E1000_READ_REG(hw, E1000_GPTC); 693 E1000_READ_REG(hw, E1000_GORCL); 694 E1000_READ_REG(hw, E1000_GORCH); 695 E1000_READ_REG(hw, E1000_GOTCL); 696 E1000_READ_REG(hw, E1000_GOTCH); 697 E1000_READ_REG(hw, E1000_RNBC); 698 E1000_READ_REG(hw, E1000_RUC); 699 E1000_READ_REG(hw, E1000_RFC); 700 E1000_READ_REG(hw, E1000_ROC); 701 E1000_READ_REG(hw, E1000_RJC); 702 E1000_READ_REG(hw, E1000_TORL); 703 E1000_READ_REG(hw, E1000_TORH); 704 E1000_READ_REG(hw, E1000_TOTL); 705 E1000_READ_REG(hw, E1000_TOTH); 706 E1000_READ_REG(hw, E1000_TPR); 707 E1000_READ_REG(hw, E1000_TPT); 708 E1000_READ_REG(hw, E1000_MPTC); 709 E1000_READ_REG(hw, E1000_BPTC); 710} 711 712/** 713 * e1000_check_for_copper_link_generic - Check for link (Copper) 714 * @hw: pointer to the HW structure 715 * 716 * Checks to see of the link status of the hardware has changed. If a 717 * change in link status has been detected, then we read the PHY registers 718 * to get the current speed/duplex if link exists. 719 **/ 720s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 721{ 722 struct e1000_mac_info *mac = &hw->mac; 723 s32 ret_val; 724 bool link; 725 726 DEBUGFUNC("e1000_check_for_copper_link"); 727 728 /* 729 * We only want to go out to the PHY registers to see if Auto-Neg 730 * has completed and/or if our link status has changed. The 731 * get_link_status flag is set upon receiving a Link Status 732 * Change or Rx Sequence Error interrupt. 733 */ 734 if (!mac->get_link_status) { 735 ret_val = E1000_SUCCESS; 736 goto out; 737 } 738 739 /* 740 * First we want to see if the MII Status Register reports 741 * link. If so, then we want to get the current speed/duplex 742 * of the PHY. 743 */ 744 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 745 if (ret_val) 746 goto out; 747 748 if (!link) 749 goto out; /* No link detected */ 750 751 mac->get_link_status = FALSE; 752 753 /* 754 * Check if there was DownShift, must be checked 755 * immediately after link-up 756 */ 757 e1000_check_downshift_generic(hw); 758 759 /* 760 * If we are forcing speed/duplex, then we simply return since 761 * we have already determined whether we have link or not. 762 */ 763 if (!mac->autoneg) { 764 ret_val = -E1000_ERR_CONFIG; 765 goto out; 766 } 767 768 /* 769 * Auto-Neg is enabled. Auto Speed Detection takes care 770 * of MAC speed/duplex configuration. So we only need to 771 * configure Collision Distance in the MAC. 772 */ 773 e1000_config_collision_dist_generic(hw); 774 775 /* 776 * Configure Flow Control now that Auto-Neg has completed. 777 * First, we need to restore the desired flow control 778 * settings because we may have had to re-autoneg with a 779 * different link partner. 780 */ 781 ret_val = e1000_config_fc_after_link_up_generic(hw); 782 if (ret_val) 783 DEBUGOUT("Error configuring flow control\n"); 784 785out: 786 return ret_val; 787} 788 789/** 790 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 791 * @hw: pointer to the HW structure 792 * 793 * Checks for link up on the hardware. If link is not up and we have 794 * a signal, then we need to force link up. 795 **/ 796s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 797{ 798 struct e1000_mac_info *mac = &hw->mac; 799 u32 rxcw; 800 u32 ctrl; 801 u32 status; 802 s32 ret_val = E1000_SUCCESS; 803 804 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 805 806 ctrl = E1000_READ_REG(hw, E1000_CTRL); 807 status = E1000_READ_REG(hw, E1000_STATUS); 808 rxcw = E1000_READ_REG(hw, E1000_RXCW); 809 810 /* 811 * If we don't have link (auto-negotiation failed or link partner 812 * cannot auto-negotiate), the cable is plugged in (we have signal), 813 * and our link partner is not trying to auto-negotiate with us (we 814 * are receiving idles or data), we need to force link up. We also 815 * need to give auto-negotiation time to complete, in case the cable 816 * was just plugged in. The autoneg_failed flag does this. 817 */ 818 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 819 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 820 (!(rxcw & E1000_RXCW_C))) { 821 if (mac->autoneg_failed == 0) { 822 mac->autoneg_failed = 1; 823 goto out; 824 } 825 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 826 827 /* Disable auto-negotiation in the TXCW register */ 828 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 829 830 /* Force link-up and also force full-duplex. */ 831 ctrl = E1000_READ_REG(hw, E1000_CTRL); 832 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 833 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 834 835 /* Configure Flow Control after forcing link up. */ 836 ret_val = e1000_config_fc_after_link_up_generic(hw); 837 if (ret_val) { 838 DEBUGOUT("Error configuring flow control\n"); 839 goto out; 840 } 841 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 842 /* 843 * If we are forcing link and we are receiving /C/ ordered 844 * sets, re-enable auto-negotiation in the TXCW register 845 * and disable forced link in the Device Control register 846 * in an attempt to auto-negotiate with our link partner. 847 */ 848 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 849 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 850 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 851 852 mac->serdes_has_link = TRUE; 853 } 854 855out: 856 return ret_val; 857} 858 859/** 860 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 861 * @hw: pointer to the HW structure 862 * 863 * Checks for link up on the hardware. If link is not up and we have 864 * a signal, then we need to force link up. 865 **/ 866s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 867{ 868 struct e1000_mac_info *mac = &hw->mac; 869 u32 rxcw; 870 u32 ctrl; 871 u32 status; 872 s32 ret_val = E1000_SUCCESS; 873 874 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 875 876 ctrl = E1000_READ_REG(hw, E1000_CTRL); 877 status = E1000_READ_REG(hw, E1000_STATUS); 878 rxcw = E1000_READ_REG(hw, E1000_RXCW); 879 880 /* 881 * If we don't have link (auto-negotiation failed or link partner 882 * cannot auto-negotiate), and our link partner is not trying to 883 * auto-negotiate with us (we are receiving idles or data), 884 * we need to force link up. We also need to give auto-negotiation 885 * time to complete. 886 */ 887 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 888 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 889 if (mac->autoneg_failed == 0) { 890 mac->autoneg_failed = 1; 891 goto out; 892 } 893 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 894 895 /* Disable auto-negotiation in the TXCW register */ 896 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 897 898 /* Force link-up and also force full-duplex. */ 899 ctrl = E1000_READ_REG(hw, E1000_CTRL); 900 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 901 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 902 903 /* Configure Flow Control after forcing link up. */ 904 ret_val = e1000_config_fc_after_link_up_generic(hw); 905 if (ret_val) { 906 DEBUGOUT("Error configuring flow control\n"); 907 goto out; 908 } 909 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 910 /* 911 * If we are forcing link and we are receiving /C/ ordered 912 * sets, re-enable auto-negotiation in the TXCW register 913 * and disable forced link in the Device Control register 914 * in an attempt to auto-negotiate with our link partner. 915 */ 916 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 917 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 918 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 919 920 mac->serdes_has_link = TRUE; 921 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 922 /* 923 * If we force link for non-auto-negotiation switch, check 924 * link status based on MAC synchronization for internal 925 * serdes media type. 926 */ 927 /* SYNCH bit and IV bit are sticky. */ 928 usec_delay(10); 929 rxcw = E1000_READ_REG(hw, E1000_RXCW); 930 if (rxcw & E1000_RXCW_SYNCH) { 931 if (!(rxcw & E1000_RXCW_IV)) { 932 mac->serdes_has_link = TRUE; 933 DEBUGOUT("SERDES: Link up - forced.\n"); 934 } 935 } else { 936 mac->serdes_has_link = FALSE; 937 DEBUGOUT("SERDES: Link down - force failed.\n"); 938 } 939 } 940 941 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 942 status = E1000_READ_REG(hw, E1000_STATUS); 943 if (status & E1000_STATUS_LU) { 944 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 945 usec_delay(10); 946 rxcw = E1000_READ_REG(hw, E1000_RXCW); 947 if (rxcw & E1000_RXCW_SYNCH) { 948 if (!(rxcw & E1000_RXCW_IV)) { 949 mac->serdes_has_link = TRUE; 950 DEBUGOUT("SERDES: Link up - autoneg " 951 "completed sucessfully.\n"); 952 } else { 953 mac->serdes_has_link = FALSE; 954 DEBUGOUT("SERDES: Link down - invalid" 955 "codewords detected in autoneg.\n"); 956 } 957 } else { 958 mac->serdes_has_link = FALSE; 959 DEBUGOUT("SERDES: Link down - no sync.\n"); 960 } 961 } else { 962 mac->serdes_has_link = FALSE; 963 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 964 } 965 } 966 967out: 968 return ret_val; 969} 970 971/** 972 * e1000_setup_link_generic - Setup flow control and link settings 973 * @hw: pointer to the HW structure 974 * 975 * Determines which flow control settings to use, then configures flow 976 * control. Calls the appropriate media-specific link configuration 977 * function. Assuming the adapter has a valid link partner, a valid link 978 * should be established. Assumes the hardware has previously been reset 979 * and the transmitter and receiver are not enabled. 980 **/ 981s32 e1000_setup_link_generic(struct e1000_hw *hw) 982{ 983 s32 ret_val = E1000_SUCCESS; 984 985 DEBUGFUNC("e1000_setup_link_generic"); 986 987 /* 988 * In the case of the phy reset being blocked, we already have a link. 989 * We do not need to set it up again. 990 */ 991 if (hw->phy.ops.check_reset_block) 992 if (hw->phy.ops.check_reset_block(hw)) 993 goto out; 994 995 /* 996 * If requested flow control is set to default, set flow control 997 * based on the EEPROM flow control settings. 998 */ 999 if (hw->fc.requested_mode == e1000_fc_default) { 1000 ret_val = e1000_set_default_fc_generic(hw); 1001 if (ret_val) 1002 goto out; 1003 } 1004 1005 /* 1006 * Save off the requested flow control mode for use later. Depending 1007 * on the link partner's capabilities, we may or may not use this mode. 1008 */ 1009 hw->fc.current_mode = hw->fc.requested_mode; 1010 1011 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1012 hw->fc.current_mode); 1013 1014 /* Call the necessary media_type subroutine to configure the link. */ 1015 ret_val = hw->mac.ops.setup_physical_interface(hw); 1016 if (ret_val) 1017 goto out; 1018 1019 /* 1020 * Initialize the flow control address, type, and PAUSE timer 1021 * registers to their default values. This is done even if flow 1022 * control is disabled, because it does not hurt anything to 1023 * initialize these registers. 1024 */ 1025 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1026 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1027 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1028 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1029 1030 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1031 1032 ret_val = e1000_set_fc_watermarks_generic(hw); 1033 1034out: 1035 return ret_val; 1036} 1037 1038/** 1039 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1040 * @hw: pointer to the HW structure 1041 * 1042 * Configures collision distance and flow control for fiber and serdes 1043 * links. Upon successful setup, poll for link. 1044 **/ 1045s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1046{ 1047 u32 ctrl; 1048 s32 ret_val = E1000_SUCCESS; 1049 1050 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1051 1052 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1053 1054 /* Take the link out of reset */ 1055 ctrl &= ~E1000_CTRL_LRST; 1056 1057 e1000_config_collision_dist_generic(hw); 1058 1059 ret_val = e1000_commit_fc_settings_generic(hw); 1060 if (ret_val) 1061 goto out; 1062 1063 /* 1064 * Since auto-negotiation is enabled, take the link out of reset (the 1065 * link will be in reset, because we previously reset the chip). This 1066 * will restart auto-negotiation. If auto-negotiation is successful 1067 * then the link-up status bit will be set and the flow control enable 1068 * bits (RFCE and TFCE) will be set according to their negotiated value. 1069 */ 1070 DEBUGOUT("Auto-negotiation enabled\n"); 1071 1072 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1073 E1000_WRITE_FLUSH(hw); 1074 msec_delay(1); 1075 1076 /* 1077 * For these adapters, the SW definable pin 1 is set when the optics 1078 * detect a signal. If we have a signal, then poll for a "Link-Up" 1079 * indication. 1080 */ 1081 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1082 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1083 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1084 } else { 1085 DEBUGOUT("No signal detected\n"); 1086 } 1087 1088out: 1089 return ret_val; 1090} 1091 1092/** 1093 * e1000_config_collision_dist_generic - Configure collision distance 1094 * @hw: pointer to the HW structure 1095 * 1096 * Configures the collision distance to the default value and is used 1097 * during link setup. Currently no func pointer exists and all 1098 * implementations are handled in the generic version of this function. 1099 **/ 1100void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1101{ 1102 u32 tctl; 1103 1104 DEBUGFUNC("e1000_config_collision_dist_generic"); 1105 1106 tctl = E1000_READ_REG(hw, E1000_TCTL); 1107 1108 tctl &= ~E1000_TCTL_COLD; 1109 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1110 1111 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1112 E1000_WRITE_FLUSH(hw); 1113} 1114 1115/** 1116 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1117 * @hw: pointer to the HW structure 1118 * 1119 * Polls for link up by reading the status register, if link fails to come 1120 * up with auto-negotiation, then the link is forced if a signal is detected. 1121 **/ 1122s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1123{ 1124 struct e1000_mac_info *mac = &hw->mac; 1125 u32 i, status; 1126 s32 ret_val = E1000_SUCCESS; 1127 1128 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1129 1130 /* 1131 * If we have a signal (the cable is plugged in, or assumed TRUE for 1132 * serdes media) then poll for a "Link-Up" indication in the Device 1133 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1134 * seconds (Auto-negotiation should complete in less than 500 1135 * milliseconds even if the other end is doing it in SW). 1136 */ 1137 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1138 msec_delay(10); 1139 status = E1000_READ_REG(hw, E1000_STATUS); 1140 if (status & E1000_STATUS_LU) 1141 break; 1142 } 1143 if (i == FIBER_LINK_UP_LIMIT) { 1144 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1145 mac->autoneg_failed = 1; 1146 /* 1147 * AutoNeg failed to achieve a link, so we'll call 1148 * mac->check_for_link. This routine will force the 1149 * link up if we detect a signal. This will allow us to 1150 * communicate with non-autonegotiating link partners. 1151 */ 1152 ret_val = hw->mac.ops.check_for_link(hw); 1153 if (ret_val) { 1154 DEBUGOUT("Error while checking for link\n"); 1155 goto out; 1156 } 1157 mac->autoneg_failed = 0; 1158 } else { 1159 mac->autoneg_failed = 0; 1160 DEBUGOUT("Valid Link Found\n"); 1161 } 1162 1163out: 1164 return ret_val; 1165} 1166 1167/** 1168 * e1000_commit_fc_settings_generic - Configure flow control 1169 * @hw: pointer to the HW structure 1170 * 1171 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1172 * base on the flow control settings in e1000_mac_info. 1173 **/ 1174s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1175{ 1176 struct e1000_mac_info *mac = &hw->mac; 1177 u32 txcw; 1178 s32 ret_val = E1000_SUCCESS; 1179 1180 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1181 1182 /* 1183 * Check for a software override of the flow control settings, and 1184 * setup the device accordingly. If auto-negotiation is enabled, then 1185 * software will have to set the "PAUSE" bits to the correct value in 1186 * the Transmit Config Word Register (TXCW) and re-start auto- 1187 * negotiation. However, if auto-negotiation is disabled, then 1188 * software will have to manually configure the two flow control enable 1189 * bits in the CTRL register. 1190 * 1191 * The possible values of the "fc" parameter are: 1192 * 0: Flow control is completely disabled 1193 * 1: Rx flow control is enabled (we can receive pause frames, 1194 * but not send pause frames). 1195 * 2: Tx flow control is enabled (we can send pause frames but we 1196 * do not support receiving pause frames). 1197 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1198 */ 1199 switch (hw->fc.current_mode) { 1200 case e1000_fc_none: 1201 /* Flow control completely disabled by a software over-ride. */ 1202 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1203 break; 1204 case e1000_fc_rx_pause: 1205 /* 1206 * Rx Flow control is enabled and Tx Flow control is disabled 1207 * by a software over-ride. Since there really isn't a way to 1208 * advertise that we are capable of Rx Pause ONLY, we will 1209 * advertise that we support both symmetric and asymmetric RX 1210 * PAUSE. Later, we will disable the adapter's ability to send 1211 * PAUSE frames. 1212 */ 1213 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1214 break; 1215 case e1000_fc_tx_pause: 1216 /* 1217 * Tx Flow control is enabled, and Rx Flow control is disabled, 1218 * by a software over-ride. 1219 */ 1220 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1221 break; 1222 case e1000_fc_full: 1223 /* 1224 * Flow control (both Rx and Tx) is enabled by a software 1225 * over-ride. 1226 */ 1227 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1228 break; 1229 default: 1230 DEBUGOUT("Flow control param set incorrectly\n"); 1231 ret_val = -E1000_ERR_CONFIG; 1232 goto out; 1233 break; 1234 } 1235 1236 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1237 mac->txcw = txcw; 1238 1239out: 1240 return ret_val; 1241} 1242 1243/** 1244 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1245 * @hw: pointer to the HW structure 1246 * 1247 * Sets the flow control high/low threshold (watermark) registers. If 1248 * flow control XON frame transmission is enabled, then set XON frame 1249 * transmission as well. 1250 **/ 1251s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1252{ 1253 s32 ret_val = E1000_SUCCESS; 1254 u32 fcrtl = 0, fcrth = 0; 1255 1256 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1257 1258 /* 1259 * Set the flow control receive threshold registers. Normally, 1260 * these registers will be set to a default threshold that may be 1261 * adjusted later by the driver's runtime code. However, if the 1262 * ability to transmit pause frames is not enabled, then these 1263 * registers will be set to 0. 1264 */ 1265 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1266 /* 1267 * We need to set up the Receive Threshold high and low water 1268 * marks as well as (optionally) enabling the transmission of 1269 * XON frames. 1270 */ 1271 fcrtl = hw->fc.low_water; 1272 if (hw->fc.send_xon) 1273 fcrtl |= E1000_FCRTL_XONE; 1274 1275 fcrth = hw->fc.high_water; 1276 } 1277 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1278 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1279 1280 return ret_val; 1281} 1282 1283/** 1284 * e1000_set_default_fc_generic - Set flow control default values 1285 * @hw: pointer to the HW structure 1286 * 1287 * Read the EEPROM for the default values for flow control and store the 1288 * values. 1289 **/ 1290s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1291{ 1292 s32 ret_val = E1000_SUCCESS; 1293 u16 nvm_data; 1294 1295 DEBUGFUNC("e1000_set_default_fc_generic"); 1296 1297 /* 1298 * Read and store word 0x0F of the EEPROM. This word contains bits 1299 * that determine the hardware's default PAUSE (flow control) mode, 1300 * a bit that determines whether the HW defaults to enabling or 1301 * disabling auto-negotiation, and the direction of the 1302 * SW defined pins. If there is no SW over-ride of the flow 1303 * control setting, then the variable hw->fc will 1304 * be initialized based on a value in the EEPROM. 1305 */ 1306 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1307 1308 if (ret_val) { 1309 DEBUGOUT("NVM Read Error\n"); 1310 goto out; 1311 } 1312 1313 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1314 hw->fc.requested_mode = e1000_fc_none; 1315 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1316 NVM_WORD0F_ASM_DIR) 1317 hw->fc.requested_mode = e1000_fc_tx_pause; 1318 else 1319 hw->fc.requested_mode = e1000_fc_full; 1320 1321out: 1322 return ret_val; 1323} 1324 1325/** 1326 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1327 * @hw: pointer to the HW structure 1328 * 1329 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1330 * device control register to reflect the adapter settings. TFCE and RFCE 1331 * need to be explicitly set by software when a copper PHY is used because 1332 * autonegotiation is managed by the PHY rather than the MAC. Software must 1333 * also configure these bits when link is forced on a fiber connection. 1334 **/ 1335s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1336{ 1337 u32 ctrl; 1338 s32 ret_val = E1000_SUCCESS; 1339 1340 DEBUGFUNC("e1000_force_mac_fc_generic"); 1341 1342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1343 1344 /* 1345 * Because we didn't get link via the internal auto-negotiation 1346 * mechanism (we either forced link or we got link via PHY 1347 * auto-neg), we have to manually enable/disable transmit an 1348 * receive flow control. 1349 * 1350 * The "Case" statement below enables/disable flow control 1351 * according to the "hw->fc.current_mode" parameter. 1352 * 1353 * The possible values of the "fc" parameter are: 1354 * 0: Flow control is completely disabled 1355 * 1: Rx flow control is enabled (we can receive pause 1356 * frames but not send pause frames). 1357 * 2: Tx flow control is enabled (we can send pause frames 1358 * frames but we do not receive pause frames). 1359 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1360 * other: No other values should be possible at this point. 1361 */ 1362 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1363 1364 switch (hw->fc.current_mode) { 1365 case e1000_fc_none: 1366 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1367 break; 1368 case e1000_fc_rx_pause: 1369 ctrl &= (~E1000_CTRL_TFCE); 1370 ctrl |= E1000_CTRL_RFCE; 1371 break; 1372 case e1000_fc_tx_pause: 1373 ctrl &= (~E1000_CTRL_RFCE); 1374 ctrl |= E1000_CTRL_TFCE; 1375 break; 1376 case e1000_fc_full: 1377 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1378 break; 1379 default: 1380 DEBUGOUT("Flow control param set incorrectly\n"); 1381 ret_val = -E1000_ERR_CONFIG; 1382 goto out; 1383 } 1384 1385 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1386 1387out: 1388 return ret_val; 1389} 1390 1391/** 1392 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1393 * @hw: pointer to the HW structure 1394 * 1395 * Checks the status of auto-negotiation after link up to ensure that the 1396 * speed and duplex were not forced. If the link needed to be forced, then 1397 * flow control needs to be forced also. If auto-negotiation is enabled 1398 * and did not fail, then we configure flow control based on our link 1399 * partner. 1400 **/ 1401s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1402{ 1403 struct e1000_mac_info *mac = &hw->mac; 1404 s32 ret_val = E1000_SUCCESS; 1405 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1406 u16 speed, duplex; 1407 1408 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1409 1410 /* 1411 * Check for the case where we have fiber media and auto-neg failed 1412 * so we had to force link. In this case, we need to force the 1413 * configuration of the MAC to match the "fc" parameter. 1414 */ 1415 if (mac->autoneg_failed) { 1416 if (hw->phy.media_type == e1000_media_type_fiber || 1417 hw->phy.media_type == e1000_media_type_internal_serdes) 1418 ret_val = e1000_force_mac_fc_generic(hw); 1419 } else { 1420 if (hw->phy.media_type == e1000_media_type_copper) 1421 ret_val = e1000_force_mac_fc_generic(hw); 1422 } 1423 1424 if (ret_val) { 1425 DEBUGOUT("Error forcing flow control settings\n"); 1426 goto out; 1427 } 1428 1429 /* 1430 * Check for the case where we have copper media and auto-neg is 1431 * enabled. In this case, we need to check and see if Auto-Neg 1432 * has completed, and if so, how the PHY and link partner has 1433 * flow control configured. 1434 */ 1435 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1436 /* 1437 * Read the MII Status Register and check to see if AutoNeg 1438 * has completed. We read this twice because this reg has 1439 * some "sticky" (latched) bits. 1440 */ 1441 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1442 if (ret_val) 1443 goto out; 1444 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1445 if (ret_val) 1446 goto out; 1447 1448 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1449 DEBUGOUT("Copper PHY and Auto Neg " 1450 "has not completed.\n"); 1451 goto out; 1452 } 1453 1454 /* 1455 * The AutoNeg process has completed, so we now need to 1456 * read both the Auto Negotiation Advertisement 1457 * Register (Address 4) and the Auto_Negotiation Base 1458 * Page Ability Register (Address 5) to determine how 1459 * flow control was negotiated. 1460 */ 1461 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1462 &mii_nway_adv_reg); 1463 if (ret_val) 1464 goto out; 1465 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1466 &mii_nway_lp_ability_reg); 1467 if (ret_val) 1468 goto out; 1469 1470 /* 1471 * Two bits in the Auto Negotiation Advertisement Register 1472 * (Address 4) and two bits in the Auto Negotiation Base 1473 * Page Ability Register (Address 5) determine flow control 1474 * for both the PHY and the link partner. The following 1475 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1476 * 1999, describes these PAUSE resolution bits and how flow 1477 * control is determined based upon these settings. 1478 * NOTE: DC = Don't Care 1479 * 1480 * LOCAL DEVICE | LINK PARTNER 1481 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1482 *-------|---------|-------|---------|-------------------- 1483 * 0 | 0 | DC | DC | e1000_fc_none 1484 * 0 | 1 | 0 | DC | e1000_fc_none 1485 * 0 | 1 | 1 | 0 | e1000_fc_none 1486 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1487 * 1 | 0 | 0 | DC | e1000_fc_none 1488 * 1 | DC | 1 | DC | e1000_fc_full 1489 * 1 | 1 | 0 | 0 | e1000_fc_none 1490 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1491 * 1492 * Are both PAUSE bits set to 1? If so, this implies 1493 * Symmetric Flow Control is enabled at both ends. The 1494 * ASM_DIR bits are irrelevant per the spec. 1495 * 1496 * For Symmetric Flow Control: 1497 * 1498 * LOCAL DEVICE | LINK PARTNER 1499 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1500 *-------|---------|-------|---------|-------------------- 1501 * 1 | DC | 1 | DC | E1000_fc_full 1502 * 1503 */ 1504 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1505 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1506 /* 1507 * Now we need to check if the user selected Rx ONLY 1508 * of pause frames. In this case, we had to advertise 1509 * FULL flow control because we could not advertise RX 1510 * ONLY. Hence, we must now check to see if we need to 1511 * turn OFF the TRANSMISSION of PAUSE frames. 1512 */ 1513 if (hw->fc.requested_mode == e1000_fc_full) { 1514 hw->fc.current_mode = e1000_fc_full; 1515 DEBUGOUT("Flow Control = FULL.\r\n"); 1516 } else { 1517 hw->fc.current_mode = e1000_fc_rx_pause; 1518 DEBUGOUT("Flow Control = " 1519 "RX PAUSE frames only.\r\n"); 1520 } 1521 } 1522 /* 1523 * For receiving PAUSE frames ONLY. 1524 * 1525 * LOCAL DEVICE | LINK PARTNER 1526 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1527 *-------|---------|-------|---------|-------------------- 1528 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1529 */ 1530 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1531 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1532 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1533 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1534 hw->fc.current_mode = e1000_fc_tx_pause; 1535 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1536 } 1537 /* 1538 * For transmitting PAUSE frames ONLY. 1539 * 1540 * LOCAL DEVICE | LINK PARTNER 1541 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1542 *-------|---------|-------|---------|-------------------- 1543 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1544 */ 1545 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1546 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1547 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1548 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1549 hw->fc.current_mode = e1000_fc_rx_pause; 1550 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1551 } else { 1552 /* 1553 * Per the IEEE spec, at this point flow control 1554 * should be disabled. 1555 */ 1556 hw->fc.current_mode = e1000_fc_none; 1557 DEBUGOUT("Flow Control = NONE.\r\n"); 1558 } 1559 1560 /* 1561 * Now we need to do one last check... If we auto- 1562 * negotiated to HALF DUPLEX, flow control should not be 1563 * enabled per IEEE 802.3 spec. 1564 */ 1565 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1566 if (ret_val) { 1567 DEBUGOUT("Error getting link speed and duplex\n"); 1568 goto out; 1569 } 1570 1571 if (duplex == HALF_DUPLEX) 1572 hw->fc.current_mode = e1000_fc_none; 1573 1574 /* 1575 * Now we call a subroutine to actually force the MAC 1576 * controller to use the correct flow control settings. 1577 */ 1578 ret_val = e1000_force_mac_fc_generic(hw); 1579 if (ret_val) { 1580 DEBUGOUT("Error forcing flow control settings\n"); 1581 goto out; 1582 } 1583 } 1584 1585out: 1586 return ret_val; 1587} 1588 1589/** 1590 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1591 * @hw: pointer to the HW structure 1592 * @speed: stores the current speed 1593 * @duplex: stores the current duplex 1594 * 1595 * Read the status register for the current speed/duplex and store the current 1596 * speed and duplex for copper connections. 1597 **/ 1598s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1599 u16 *duplex) 1600{ 1601 u32 status; 1602 1603 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1604 1605 status = E1000_READ_REG(hw, E1000_STATUS); 1606 if (status & E1000_STATUS_SPEED_1000) { 1607 *speed = SPEED_1000; 1608 DEBUGOUT("1000 Mbs, "); 1609 } else if (status & E1000_STATUS_SPEED_100) { 1610 *speed = SPEED_100; 1611 DEBUGOUT("100 Mbs, "); 1612 } else { 1613 *speed = SPEED_10; 1614 DEBUGOUT("10 Mbs, "); 1615 } 1616 1617 if (status & E1000_STATUS_FD) { 1618 *duplex = FULL_DUPLEX; 1619 DEBUGOUT("Full Duplex\n"); 1620 } else { 1621 *duplex = HALF_DUPLEX; 1622 DEBUGOUT("Half Duplex\n"); 1623 } 1624 1625 return E1000_SUCCESS; 1626} 1627 1628/** 1629 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1630 * @hw: pointer to the HW structure 1631 * @speed: stores the current speed 1632 * @duplex: stores the current duplex 1633 * 1634 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1635 * for fiber/serdes links. 1636 **/ 1637s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1638 u16 *speed, u16 *duplex) 1639{ 1640 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1641 1642 *speed = SPEED_1000; 1643 *duplex = FULL_DUPLEX; 1644 1645 return E1000_SUCCESS; 1646} 1647 1648/** 1649 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1650 * @hw: pointer to the HW structure 1651 * 1652 * Acquire the HW semaphore to access the PHY or NVM 1653 **/ 1654s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1655{ 1656 u32 swsm; 1657 s32 ret_val = E1000_SUCCESS; 1658 s32 timeout = hw->nvm.word_size + 1; 1659 s32 i = 0; 1660 1661 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1662 1663 /* Get the SW semaphore */ 1664 while (i < timeout) { 1665 swsm = E1000_READ_REG(hw, E1000_SWSM); 1666 if (!(swsm & E1000_SWSM_SMBI)) 1667 break; 1668 1669 usec_delay(50); 1670 i++; 1671 } 1672 1673 if (i == timeout) { 1674 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1675 ret_val = -E1000_ERR_NVM; 1676 goto out; 1677 } 1678 1679 /* Get the FW semaphore. */ 1680 for (i = 0; i < timeout; i++) { 1681 swsm = E1000_READ_REG(hw, E1000_SWSM); 1682 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1683 1684 /* Semaphore acquired if bit latched */ 1685 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1686 break; 1687 1688 usec_delay(50); 1689 } 1690 1691 if (i == timeout) { 1692 /* Release semaphores */ 1693 e1000_put_hw_semaphore_generic(hw); 1694 DEBUGOUT("Driver can't access the NVM\n"); 1695 ret_val = -E1000_ERR_NVM; 1696 goto out; 1697 } 1698 1699out: 1700 return ret_val; 1701} 1702 1703/** 1704 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1705 * @hw: pointer to the HW structure 1706 * 1707 * Release hardware semaphore used to access the PHY or NVM 1708 **/ 1709void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1710{ 1711 u32 swsm; 1712 1713 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1714 1715 swsm = E1000_READ_REG(hw, E1000_SWSM); 1716 1717 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1718 1719 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1720} 1721 1722/** 1723 * e1000_get_auto_rd_done_generic - Check for auto read completion 1724 * @hw: pointer to the HW structure 1725 * 1726 * Check EEPROM for Auto Read done bit. 1727 **/ 1728s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1729{ 1730 s32 i = 0; 1731 s32 ret_val = E1000_SUCCESS; 1732 1733 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1734 1735 while (i < AUTO_READ_DONE_TIMEOUT) { 1736 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1737 break; 1738 msec_delay(1); 1739 i++; 1740 } 1741 1742 if (i == AUTO_READ_DONE_TIMEOUT) { 1743 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1744 ret_val = -E1000_ERR_RESET; 1745 goto out; 1746 } 1747 1748out: 1749 return ret_val; 1750} 1751 1752/** 1753 * e1000_valid_led_default_generic - Verify a valid default LED config 1754 * @hw: pointer to the HW structure 1755 * @data: pointer to the NVM (EEPROM) 1756 * 1757 * Read the EEPROM for the current default LED configuration. If the 1758 * LED configuration is not valid, set to a valid LED configuration. 1759 **/ 1760s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1761{ 1762 s32 ret_val; 1763 1764 DEBUGFUNC("e1000_valid_led_default_generic"); 1765 1766 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1767 if (ret_val) { 1768 DEBUGOUT("NVM Read Error\n"); 1769 goto out; 1770 } 1771 1772 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1773 *data = ID_LED_DEFAULT; 1774 1775out: 1776 return ret_val; 1777} 1778 1779/** 1780 * e1000_id_led_init_generic - 1781 * @hw: pointer to the HW structure 1782 * 1783 **/ 1784s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1785{ 1786 struct e1000_mac_info *mac = &hw->mac; 1787 s32 ret_val; 1788 const u32 ledctl_mask = 0x000000FF; 1789 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1790 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1791 u16 data, i, temp; 1792 const u16 led_mask = 0x0F; 1793 1794 DEBUGFUNC("e1000_id_led_init_generic"); 1795 1796 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1797 if (ret_val) 1798 goto out; 1799 1800 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1801 mac->ledctl_mode1 = mac->ledctl_default; 1802 mac->ledctl_mode2 = mac->ledctl_default; 1803 1804 for (i = 0; i < 4; i++) { 1805 temp = (data >> (i << 2)) & led_mask; 1806 switch (temp) { 1807 case ID_LED_ON1_DEF2: 1808 case ID_LED_ON1_ON2: 1809 case ID_LED_ON1_OFF2: 1810 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1811 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1812 break; 1813 case ID_LED_OFF1_DEF2: 1814 case ID_LED_OFF1_ON2: 1815 case ID_LED_OFF1_OFF2: 1816 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1817 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1818 break; 1819 default: 1820 /* Do nothing */ 1821 break; 1822 } 1823 switch (temp) { 1824 case ID_LED_DEF1_ON2: 1825 case ID_LED_ON1_ON2: 1826 case ID_LED_OFF1_ON2: 1827 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1828 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1829 break; 1830 case ID_LED_DEF1_OFF2: 1831 case ID_LED_ON1_OFF2: 1832 case ID_LED_OFF1_OFF2: 1833 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1834 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1835 break; 1836 default: 1837 /* Do nothing */ 1838 break; 1839 } 1840 } 1841 1842out: 1843 return ret_val; 1844} 1845 1846/** 1847 * e1000_setup_led_generic - Configures SW controllable LED 1848 * @hw: pointer to the HW structure 1849 * 1850 * This prepares the SW controllable LED for use and saves the current state 1851 * of the LED so it can be later restored. 1852 **/ 1853s32 e1000_setup_led_generic(struct e1000_hw *hw) 1854{ 1855 u32 ledctl; 1856 s32 ret_val = E1000_SUCCESS; 1857 1858 DEBUGFUNC("e1000_setup_led_generic"); 1859 1860 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1861 ret_val = -E1000_ERR_CONFIG; 1862 goto out; 1863 } 1864 1865 if (hw->phy.media_type == e1000_media_type_fiber) { 1866 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1867 hw->mac.ledctl_default = ledctl; 1868 /* Turn off LED0 */ 1869 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1870 E1000_LEDCTL_LED0_BLINK | 1871 E1000_LEDCTL_LED0_MODE_MASK); 1872 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1873 E1000_LEDCTL_LED0_MODE_SHIFT); 1874 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1875 } else if (hw->phy.media_type == e1000_media_type_copper) { 1876 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1877 } 1878 1879out: 1880 return ret_val; 1881} 1882 1883/** 1884 * e1000_cleanup_led_generic - Set LED config to default operation 1885 * @hw: pointer to the HW structure 1886 * 1887 * Remove the current LED configuration and set the LED configuration 1888 * to the default value, saved from the EEPROM. 1889 **/ 1890s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1891{ 1892 s32 ret_val = E1000_SUCCESS; 1893 1894 DEBUGFUNC("e1000_cleanup_led_generic"); 1895 1896 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1897 ret_val = -E1000_ERR_CONFIG; 1898 goto out; 1899 } 1900 1901 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1902 1903out: 1904 return ret_val; 1905} 1906 1907/** 1908 * e1000_blink_led_generic - Blink LED 1909 * @hw: pointer to the HW structure 1910 * 1911 * Blink the LEDs which are set to be on. 1912 **/ 1913s32 e1000_blink_led_generic(struct e1000_hw *hw) 1914{ 1915 u32 ledctl_blink = 0; 1916 u32 i; 1917 1918 DEBUGFUNC("e1000_blink_led_generic"); 1919 1920 if (hw->phy.media_type == e1000_media_type_fiber) { 1921 /* always blink LED0 for PCI-E fiber */ 1922 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1923 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1924 } else { 1925 /* 1926 * set the blink bit for each LED that's "on" (0x0E) 1927 * in ledctl_mode2 1928 */ 1929 ledctl_blink = hw->mac.ledctl_mode2; 1930 for (i = 0; i < 4; i++) 1931 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1932 E1000_LEDCTL_MODE_LED_ON) 1933 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1934 (i * 8)); 1935 } 1936 1937 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1938 1939 return E1000_SUCCESS; 1940} 1941 1942/** 1943 * e1000_led_on_generic - Turn LED on 1944 * @hw: pointer to the HW structure 1945 * 1946 * Turn LED on. 1947 **/ 1948s32 e1000_led_on_generic(struct e1000_hw *hw) 1949{ 1950 u32 ctrl; 1951 1952 DEBUGFUNC("e1000_led_on_generic"); 1953 1954 switch (hw->phy.media_type) { 1955 case e1000_media_type_fiber: 1956 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1957 ctrl &= ~E1000_CTRL_SWDPIN0; 1958 ctrl |= E1000_CTRL_SWDPIO0; 1959 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1960 break; 1961 case e1000_media_type_copper: 1962 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1963 break; 1964 default: 1965 break; 1966 } 1967 1968 return E1000_SUCCESS; 1969} 1970 1971/** 1972 * e1000_led_off_generic - Turn LED off 1973 * @hw: pointer to the HW structure 1974 * 1975 * Turn LED off. 1976 **/ 1977s32 e1000_led_off_generic(struct e1000_hw *hw) 1978{ 1979 u32 ctrl; 1980 1981 DEBUGFUNC("e1000_led_off_generic"); 1982 1983 switch (hw->phy.media_type) { 1984 case e1000_media_type_fiber: 1985 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1986 ctrl |= E1000_CTRL_SWDPIN0; 1987 ctrl |= E1000_CTRL_SWDPIO0; 1988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1989 break; 1990 case e1000_media_type_copper: 1991 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1992 break; 1993 default: 1994 break; 1995 } 1996 1997 return E1000_SUCCESS; 1998} 1999 2000/** 2001 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2002 * @hw: pointer to the HW structure 2003 * @no_snoop: bitmap of snoop events 2004 * 2005 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2006 **/ 2007void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2008{ 2009 u32 gcr; 2010 2011 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2012 2013 if (hw->bus.type != e1000_bus_type_pci_express) 2014 goto out; 2015 2016 if (no_snoop) { 2017 gcr = E1000_READ_REG(hw, E1000_GCR); 2018 gcr &= ~(PCIE_NO_SNOOP_ALL); 2019 gcr |= no_snoop; 2020 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2021 } 2022out: 2023 return; 2024} 2025 2026/** 2027 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2028 * @hw: pointer to the HW structure 2029 * 2030 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 2031 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2032 * the master requests to be disabled. 2033 * 2034 * Disables PCI-Express master access and verifies there are no pending 2035 * requests. 2036 **/ 2037s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2038{ 2039 u32 ctrl; 2040 s32 timeout = MASTER_DISABLE_TIMEOUT; 2041 s32 ret_val = E1000_SUCCESS; 2042 2043 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2044 2045 if (hw->bus.type != e1000_bus_type_pci_express) 2046 goto out; 2047 2048 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2049 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2050 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2051 2052 while (timeout) { 2053 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2054 E1000_STATUS_GIO_MASTER_ENABLE)) 2055 break; 2056 usec_delay(100); 2057 timeout--; 2058 } 2059 2060 if (!timeout) { 2061 DEBUGOUT("Master requests are pending.\n"); 2062 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2063 goto out; 2064 } 2065 2066out: 2067 return ret_val; 2068} 2069 2070/** 2071 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2072 * @hw: pointer to the HW structure 2073 * 2074 * Reset the Adaptive Interframe Spacing throttle to default values. 2075 **/ 2076void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2077{ 2078 struct e1000_mac_info *mac = &hw->mac; 2079 2080 DEBUGFUNC("e1000_reset_adaptive_generic"); 2081 2082 if (!mac->adaptive_ifs) { 2083 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2084 goto out; 2085 } 2086 2087 mac->current_ifs_val = 0; 2088 mac->ifs_min_val = IFS_MIN; 2089 mac->ifs_max_val = IFS_MAX; 2090 mac->ifs_step_size = IFS_STEP; 2091 mac->ifs_ratio = IFS_RATIO; 2092 2093 mac->in_ifs_mode = FALSE; 2094 E1000_WRITE_REG(hw, E1000_AIT, 0); 2095out: 2096 return; 2097} 2098 2099/** 2100 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2101 * @hw: pointer to the HW structure 2102 * 2103 * Update the Adaptive Interframe Spacing Throttle value based on the 2104 * time between transmitted packets and time between collisions. 2105 **/ 2106void e1000_update_adaptive_generic(struct e1000_hw *hw) 2107{ 2108 struct e1000_mac_info *mac = &hw->mac; 2109 2110 DEBUGFUNC("e1000_update_adaptive_generic"); 2111 2112 if (!mac->adaptive_ifs) { 2113 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2114 goto out; 2115 } 2116 2117 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2118 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2119 mac->in_ifs_mode = TRUE; 2120 if (mac->current_ifs_val < mac->ifs_max_val) { 2121 if (!mac->current_ifs_val) 2122 mac->current_ifs_val = mac->ifs_min_val; 2123 else 2124 mac->current_ifs_val += 2125 mac->ifs_step_size; 2126 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2127 } 2128 } 2129 } else { 2130 if (mac->in_ifs_mode && 2131 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2132 mac->current_ifs_val = 0; 2133 mac->in_ifs_mode = FALSE; 2134 E1000_WRITE_REG(hw, E1000_AIT, 0); 2135 } 2136 } 2137out: 2138 return; 2139} 2140 2141/** 2142 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2143 * @hw: pointer to the HW structure 2144 * 2145 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2146 * set, which is forced to MDI mode only. 2147 **/ 2148s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2149{ 2150 s32 ret_val = E1000_SUCCESS; 2151 2152 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2153 2154 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2155 DEBUGOUT("Invalid MDI setting detected\n"); 2156 hw->phy.mdix = 1; 2157 ret_val = -E1000_ERR_CONFIG; 2158 goto out; 2159 } 2160 2161out: 2162 return ret_val; 2163} 2164 2165/** 2166 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2167 * @hw: pointer to the HW structure 2168 * @reg: 32bit register offset such as E1000_SCTL 2169 * @offset: register offset to write to 2170 * @data: data to write at register offset 2171 * 2172 * Writes an address/data control type register. There are several of these 2173 * and they all have the format address << 8 | data and bit 31 is polled for 2174 * completion. 2175 **/ 2176s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2177 u32 offset, u8 data) 2178{ 2179 u32 i, regvalue = 0; 2180 s32 ret_val = E1000_SUCCESS; 2181 2182 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2183 2184 /* Set up the address and data */ 2185 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2186 E1000_WRITE_REG(hw, reg, regvalue); 2187 2188 /* Poll the ready bit to see if the MDI read completed */ 2189 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2190 usec_delay(5); 2191 regvalue = E1000_READ_REG(hw, reg); 2192 if (regvalue & E1000_GEN_CTL_READY) 2193 break; 2194 } 2195 if (!(regvalue & E1000_GEN_CTL_READY)) { 2196 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2197 ret_val = -E1000_ERR_PHY; 2198 goto out; 2199 } 2200 2201out: 2202 return ret_val; 2203} 2204