e1000_mac.c revision 177867
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_mac.c 177867 2008-04-02 22:00:36Z jfv $*/ 34 35#include "e1000_api.h" 36#include "e1000_mac.h" 37 38/** 39 * e1000_init_mac_ops_generic - Initialize MAC function pointers 40 * @hw: pointer to the HW structure 41 * 42 * Setups up the function pointers to no-op functions 43 **/ 44void e1000_init_mac_ops_generic(struct e1000_hw *hw) 45{ 46 struct e1000_mac_info *mac = &hw->mac; 47 DEBUGFUNC("e1000_init_mac_ops_generic"); 48 49 /* General Setup */ 50 mac->ops.init_params = e1000_null_ops_generic; 51 mac->ops.init_hw = e1000_null_ops_generic; 52 mac->ops.reset_hw = e1000_null_ops_generic; 53 mac->ops.setup_physical_interface = e1000_null_ops_generic; 54 mac->ops.get_bus_info = e1000_null_ops_generic; 55 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 56 mac->ops.remove_device = e1000_remove_device_generic; 57 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 58 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 59 /* LED */ 60 mac->ops.cleanup_led = e1000_null_ops_generic; 61 mac->ops.setup_led = e1000_null_ops_generic; 62 mac->ops.blink_led = e1000_null_ops_generic; 63 mac->ops.led_on = e1000_null_ops_generic; 64 mac->ops.led_off = e1000_null_ops_generic; 65 /* LINK */ 66 mac->ops.setup_link = e1000_null_ops_generic; 67 mac->ops.get_link_up_info = e1000_null_link_info; 68 mac->ops.check_for_link = e1000_null_ops_generic; 69 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 70 /* Management */ 71 mac->ops.check_mng_mode = e1000_null_mng_mode; 72 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 73 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 74 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 75 /* VLAN, MC, etc. */ 76 mac->ops.update_mc_addr_list = e1000_null_update_mc; 77 mac->ops.clear_vfta = e1000_null_mac_generic; 78 mac->ops.write_vfta = e1000_null_write_vfta; 79 mac->ops.mta_set = e1000_null_mta_set; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82} 83 84/** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88s32 e1000_null_ops_generic(struct e1000_hw *hw) 89{ 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92} 93 94/** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98void e1000_null_mac_generic(struct e1000_hw *hw) 99{ 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102} 103 104/** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 109{ 110 DEBUGFUNC("e1000_null_link_info"); 111 return E1000_SUCCESS; 112} 113 114/** 115 * e1000_null_mng_mode - No-op function, return FALSE 116 * @hw: pointer to the HW structure 117 **/ 118bool e1000_null_mng_mode(struct e1000_hw *hw) 119{ 120 DEBUGFUNC("e1000_null_mng_mode"); 121 return FALSE; 122} 123 124/** 125 * e1000_null_update_mc - No-op function, return void 126 * @hw: pointer to the HW structure 127 **/ 128void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a, u32 b, u32 c) 129{ 130 DEBUGFUNC("e1000_null_update_mc"); 131 return; 132} 133 134/** 135 * e1000_null_write_vfta - No-op function, return void 136 * @hw: pointer to the HW structure 137 **/ 138void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 139{ 140 DEBUGFUNC("e1000_null_write_vfta"); 141 return; 142} 143 144/** 145 * e1000_null_set_mta - No-op function, return void 146 * @hw: pointer to the HW structure 147 **/ 148void e1000_null_mta_set(struct e1000_hw *hw, u32 a) 149{ 150 DEBUGFUNC("e1000_null_mta_set"); 151 return; 152} 153 154/** 155 * e1000_null_rar_set - No-op function, return void 156 * @hw: pointer to the HW structure 157 **/ 158void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 159{ 160 DEBUGFUNC("e1000_null_rar_set"); 161 return; 162} 163 164/** 165 * e1000_remove_device_generic - Free device specific structure 166 * @hw: pointer to the HW structure 167 * 168 * If a device specific structure was allocated, this function will 169 * free it. 170 **/ 171void e1000_remove_device_generic(struct e1000_hw *hw) 172{ 173 DEBUGFUNC("e1000_remove_device_generic"); 174 175 /* Freeing the dev_spec member of e1000_hw structure */ 176 e1000_free_dev_spec_struct(hw); 177} 178 179/** 180 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 181 * @hw: pointer to the HW structure 182 * 183 * Determines and stores the system bus information for a particular 184 * network interface. The following bus information is determined and stored: 185 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 186 **/ 187s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 188{ 189 struct e1000_bus_info *bus = &hw->bus; 190 u32 status = E1000_READ_REG(hw, E1000_STATUS); 191 s32 ret_val = E1000_SUCCESS; 192 u16 pci_header_type; 193 194 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 195 196 /* PCI or PCI-X? */ 197 bus->type = (status & E1000_STATUS_PCIX_MODE) 198 ? e1000_bus_type_pcix 199 : e1000_bus_type_pci; 200 201 /* Bus speed */ 202 if (bus->type == e1000_bus_type_pci) { 203 bus->speed = (status & E1000_STATUS_PCI66) 204 ? e1000_bus_speed_66 205 : e1000_bus_speed_33; 206 } else { 207 switch (status & E1000_STATUS_PCIX_SPEED) { 208 case E1000_STATUS_PCIX_SPEED_66: 209 bus->speed = e1000_bus_speed_66; 210 break; 211 case E1000_STATUS_PCIX_SPEED_100: 212 bus->speed = e1000_bus_speed_100; 213 break; 214 case E1000_STATUS_PCIX_SPEED_133: 215 bus->speed = e1000_bus_speed_133; 216 break; 217 default: 218 bus->speed = e1000_bus_speed_reserved; 219 break; 220 } 221 } 222 223 /* Bus width */ 224 bus->width = (status & E1000_STATUS_BUS64) 225 ? e1000_bus_width_64 226 : e1000_bus_width_32; 227 228 /* Which PCI(-X) function? */ 229 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 230 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 231 bus->func = (status & E1000_STATUS_FUNC_MASK) 232 >> E1000_STATUS_FUNC_SHIFT; 233 else 234 bus->func = 0; 235 236 return ret_val; 237} 238 239/** 240 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 241 * @hw: pointer to the HW structure 242 * 243 * Determines and stores the system bus information for a particular 244 * network interface. The following bus information is determined and stored: 245 * bus speed, bus width, type (PCIe), and PCIe function. 246 **/ 247s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 248{ 249 struct e1000_bus_info *bus = &hw->bus; 250 s32 ret_val; 251 u32 status; 252 u16 pcie_link_status, pci_header_type; 253 254 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 255 256 bus->type = e1000_bus_type_pci_express; 257 bus->speed = e1000_bus_speed_2500; 258 259 ret_val = e1000_read_pcie_cap_reg(hw, 260 PCIE_LINK_STATUS, 261 &pcie_link_status); 262 if (ret_val) 263 bus->width = e1000_bus_width_unknown; 264 else 265 bus->width = (e1000_bus_width)((pcie_link_status & 266 PCIE_LINK_WIDTH_MASK) >> 267 PCIE_LINK_WIDTH_SHIFT); 268 269 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 270 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 271 status = E1000_READ_REG(hw, E1000_STATUS); 272 bus->func = (status & E1000_STATUS_FUNC_MASK) 273 >> E1000_STATUS_FUNC_SHIFT; 274 } else { 275 bus->func = 0; 276 } 277 278 return E1000_SUCCESS; 279} 280 281/** 282 * e1000_clear_vfta_generic - Clear VLAN filter table 283 * @hw: pointer to the HW structure 284 * 285 * Clears the register array which contains the VLAN filter table by 286 * setting all the values to 0. 287 **/ 288void e1000_clear_vfta_generic(struct e1000_hw *hw) 289{ 290 u32 offset; 291 292 DEBUGFUNC("e1000_clear_vfta_generic"); 293 294 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 295 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 296 E1000_WRITE_FLUSH(hw); 297 } 298} 299 300/** 301 * e1000_write_vfta_generic - Write value to VLAN filter table 302 * @hw: pointer to the HW structure 303 * @offset: register offset in VLAN filter table 304 * @value: register value written to VLAN filter table 305 * 306 * Writes value at the given offset in the register array which stores 307 * the VLAN filter table. 308 **/ 309void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 310{ 311 DEBUGFUNC("e1000_write_vfta_generic"); 312 313 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 314 E1000_WRITE_FLUSH(hw); 315} 316 317/** 318 * e1000_init_rx_addrs_generic - Initialize receive address's 319 * @hw: pointer to the HW structure 320 * @rar_count: receive address registers 321 * 322 * Setups the receive address registers by setting the base receive address 323 * register to the devices MAC address and clearing all the other receive 324 * address registers to 0. 325 **/ 326void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 327{ 328 u32 i; 329 330 DEBUGFUNC("e1000_init_rx_addrs_generic"); 331 332 /* Setup the receive address */ 333 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 334 335 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 336 337 /* Zero out the other (rar_entry_count - 1) receive addresses */ 338 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 339 for (i = 1; i < rar_count; i++) { 340 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 341 E1000_WRITE_FLUSH(hw); 342 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 343 E1000_WRITE_FLUSH(hw); 344 } 345} 346 347/** 348 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 349 * @hw: pointer to the HW structure 350 * 351 * Checks the nvm for an alternate MAC address. An alternate MAC address 352 * can be setup by pre-boot software and must be treated like a permanent 353 * address and must override the actual permanent MAC address. If an 354 * alternate MAC address is found it is saved in the hw struct and 355 * programmed into RAR0 and the function returns success, otherwise the 356 * function returns an error. 357 **/ 358s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 359{ 360 u32 i; 361 s32 ret_val = E1000_SUCCESS; 362 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 363 u8 alt_mac_addr[ETH_ADDR_LEN]; 364 365 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 366 367 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 368 &nvm_alt_mac_addr_offset); 369 if (ret_val) { 370 DEBUGOUT("NVM Read Error\n"); 371 goto out; 372 } 373 374 if (nvm_alt_mac_addr_offset == 0xFFFF) { 375 ret_val = -(E1000_NOT_IMPLEMENTED); 376 goto out; 377 } 378 379 if (hw->bus.func == E1000_FUNC_1) 380 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16); 381 382 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 383 offset = nvm_alt_mac_addr_offset + (i >> 1); 384 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 385 if (ret_val) { 386 DEBUGOUT("NVM Read Error\n"); 387 goto out; 388 } 389 390 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 391 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 392 } 393 394 /* if multicast bit is set, the alternate address will not be used */ 395 if (alt_mac_addr[0] & 0x01) { 396 ret_val = -(E1000_NOT_IMPLEMENTED); 397 goto out; 398 } 399 400 for (i = 0; i < ETH_ADDR_LEN; i++) 401 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 402 403 hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); 404 405out: 406 return ret_val; 407} 408 409/** 410 * e1000_rar_set_generic - Set receive address register 411 * @hw: pointer to the HW structure 412 * @addr: pointer to the receive address 413 * @index: receive address array register 414 * 415 * Sets the receive address array register at index to the address passed 416 * in by addr. 417 **/ 418void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 419{ 420 u32 rar_low, rar_high; 421 422 DEBUGFUNC("e1000_rar_set_generic"); 423 424 /* 425 * HW expects these in little endian so we reverse the byte order 426 * from network order (big endian) to little endian 427 */ 428 rar_low = ((u32) addr[0] | 429 ((u32) addr[1] << 8) | 430 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 431 432 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 433 434 /* If MAC address zero, no need to set the AV bit */ 435 if (rar_low || rar_high) { 436 if (!hw->mac.disable_av) 437 rar_high |= E1000_RAH_AV; 438 } 439 440 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 441 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 442} 443 444/** 445 * e1000_mta_set_generic - Set multicast filter table address 446 * @hw: pointer to the HW structure 447 * @hash_value: determines the MTA register and bit to set 448 * 449 * The multicast table address is a register array of 32-bit registers. 450 * The hash_value is used to determine what register the bit is in, the 451 * current value is read, the new bit is OR'd in and the new value is 452 * written back into the register. 453 **/ 454void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 455{ 456 u32 hash_bit, hash_reg, mta; 457 458 DEBUGFUNC("e1000_mta_set_generic"); 459 /* 460 * The MTA is a register array of 32-bit registers. It is 461 * treated like an array of (32*mta_reg_count) bits. We want to 462 * set bit BitArray[hash_value]. So we figure out what register 463 * the bit is in, read it, OR in the new bit, then write 464 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 465 * mask to bits 31:5 of the hash value which gives us the 466 * register we're modifying. The hash bit within that register 467 * is determined by the lower 5 bits of the hash value. 468 */ 469 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 470 hash_bit = hash_value & 0x1F; 471 472 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 473 474 mta |= (1 << hash_bit); 475 476 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 477 E1000_WRITE_FLUSH(hw); 478} 479 480/** 481 * e1000_update_mc_addr_list_generic - Update Multicast addresses 482 * @hw: pointer to the HW structure 483 * @mc_addr_list: array of multicast addresses to program 484 * @mc_addr_count: number of multicast addresses to program 485 * @rar_used_count: the first RAR register free to program 486 * @rar_count: total number of supported Receive Address Registers 487 * 488 * Updates the Receive Address Registers and Multicast Table Array. 489 * The caller must have a packed mc_addr_list of multicast addresses. 490 * The parameter rar_count will usually be hw->mac.rar_entry_count 491 * unless there are workarounds that change this. 492 **/ 493void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 494 u8 *mc_addr_list, u32 mc_addr_count, 495 u32 rar_used_count, u32 rar_count) 496{ 497 u32 hash_value; 498 u32 i; 499 500 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 501 502 /* 503 * Load the first set of multicast addresses into the exact 504 * filters (RAR). If there are not enough to fill the RAR 505 * array, clear the filters. 506 */ 507 for (i = rar_used_count; i < rar_count; i++) { 508 if (mc_addr_count) { 509 hw->mac.ops.rar_set(hw, mc_addr_list, i); 510 mc_addr_count--; 511 mc_addr_list += ETH_ADDR_LEN; 512 } else { 513 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 514 E1000_WRITE_FLUSH(hw); 515 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 516 E1000_WRITE_FLUSH(hw); 517 } 518 } 519 520 /* Clear the old settings from the MTA */ 521 DEBUGOUT("Clearing MTA\n"); 522 for (i = 0; i < hw->mac.mta_reg_count; i++) { 523 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 524 E1000_WRITE_FLUSH(hw); 525 } 526 527 /* Load any remaining multicast addresses into the hash table. */ 528 for (; mc_addr_count > 0; mc_addr_count--) { 529 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 530 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 531 hw->mac.ops.mta_set(hw, hash_value); 532 mc_addr_list += ETH_ADDR_LEN; 533 } 534} 535 536/** 537 * e1000_hash_mc_addr_generic - Generate a multicast hash value 538 * @hw: pointer to the HW structure 539 * @mc_addr: pointer to a multicast address 540 * 541 * Generates a multicast address hash value which is used to determine 542 * the multicast filter table array address and new table value. See 543 * e1000_mta_set_generic() 544 **/ 545u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 546{ 547 u32 hash_value, hash_mask; 548 u8 bit_shift = 0; 549 550 DEBUGFUNC("e1000_hash_mc_addr_generic"); 551 552 /* Register count multiplied by bits per register */ 553 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 554 555 /* 556 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 557 * where 0xFF would still fall within the hash mask. 558 */ 559 while (hash_mask >> bit_shift != 0xFF) 560 bit_shift++; 561 562 /* 563 * The portion of the address that is used for the hash table 564 * is determined by the mc_filter_type setting. 565 * The algorithm is such that there is a total of 8 bits of shifting. 566 * The bit_shift for a mc_filter_type of 0 represents the number of 567 * left-shifts where the MSB of mc_addr[5] would still fall within 568 * the hash_mask. Case 0 does this exactly. Since there are a total 569 * of 8 bits of shifting, then mc_addr[4] will shift right the 570 * remaining number of bits. Thus 8 - bit_shift. The rest of the 571 * cases are a variation of this algorithm...essentially raising the 572 * number of bits to shift mc_addr[5] left, while still keeping the 573 * 8-bit shifting total. 574 * 575 * For example, given the following Destination MAC Address and an 576 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 577 * we can see that the bit_shift for case 0 is 4. These are the hash 578 * values resulting from each mc_filter_type... 579 * [0] [1] [2] [3] [4] [5] 580 * 01 AA 00 12 34 56 581 * LSB MSB 582 * 583 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 584 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 585 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 586 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 587 */ 588 switch (hw->mac.mc_filter_type) { 589 default: 590 case 0: 591 break; 592 case 1: 593 bit_shift += 1; 594 break; 595 case 2: 596 bit_shift += 2; 597 break; 598 case 3: 599 bit_shift += 4; 600 break; 601 } 602 603 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 604 (((u16) mc_addr[5]) << bit_shift))); 605 606 return hash_value; 607} 608 609/** 610 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 611 * @hw: pointer to the HW structure 612 * 613 * In certain situations, a system BIOS may report that the PCIx maximum 614 * memory read byte count (MMRBC) value is higher than than the actual 615 * value. We check the PCIx command register with the current PCIx status 616 * register. 617 **/ 618void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 619{ 620 u16 cmd_mmrbc; 621 u16 pcix_cmd; 622 u16 pcix_stat_hi_word; 623 u16 stat_mmrbc; 624 625 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 626 627 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 628 if (hw->bus.type != e1000_bus_type_pcix) 629 return; 630 631 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 632 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 633 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 634 PCIX_COMMAND_MMRBC_SHIFT; 635 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 636 PCIX_STATUS_HI_MMRBC_SHIFT; 637 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 638 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 639 if (cmd_mmrbc > stat_mmrbc) { 640 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 641 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 642 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 643 } 644} 645 646/** 647 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 648 * @hw: pointer to the HW structure 649 * 650 * Clears the base hardware counters by reading the counter registers. 651 **/ 652void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 653{ 654 volatile u32 temp; 655 656 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 657 658 temp = E1000_READ_REG(hw, E1000_CRCERRS); 659 temp = E1000_READ_REG(hw, E1000_SYMERRS); 660 temp = E1000_READ_REG(hw, E1000_MPC); 661 temp = E1000_READ_REG(hw, E1000_SCC); 662 temp = E1000_READ_REG(hw, E1000_ECOL); 663 temp = E1000_READ_REG(hw, E1000_MCC); 664 temp = E1000_READ_REG(hw, E1000_LATECOL); 665 temp = E1000_READ_REG(hw, E1000_COLC); 666 temp = E1000_READ_REG(hw, E1000_DC); 667 temp = E1000_READ_REG(hw, E1000_SEC); 668 temp = E1000_READ_REG(hw, E1000_RLEC); 669 temp = E1000_READ_REG(hw, E1000_XONRXC); 670 temp = E1000_READ_REG(hw, E1000_XONTXC); 671 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 672 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 673 temp = E1000_READ_REG(hw, E1000_FCRUC); 674 temp = E1000_READ_REG(hw, E1000_GPRC); 675 temp = E1000_READ_REG(hw, E1000_BPRC); 676 temp = E1000_READ_REG(hw, E1000_MPRC); 677 temp = E1000_READ_REG(hw, E1000_GPTC); 678 temp = E1000_READ_REG(hw, E1000_GORCL); 679 temp = E1000_READ_REG(hw, E1000_GORCH); 680 temp = E1000_READ_REG(hw, E1000_GOTCL); 681 temp = E1000_READ_REG(hw, E1000_GOTCH); 682 temp = E1000_READ_REG(hw, E1000_RNBC); 683 temp = E1000_READ_REG(hw, E1000_RUC); 684 temp = E1000_READ_REG(hw, E1000_RFC); 685 temp = E1000_READ_REG(hw, E1000_ROC); 686 temp = E1000_READ_REG(hw, E1000_RJC); 687 temp = E1000_READ_REG(hw, E1000_TORL); 688 temp = E1000_READ_REG(hw, E1000_TORH); 689 temp = E1000_READ_REG(hw, E1000_TOTL); 690 temp = E1000_READ_REG(hw, E1000_TOTH); 691 temp = E1000_READ_REG(hw, E1000_TPR); 692 temp = E1000_READ_REG(hw, E1000_TPT); 693 temp = E1000_READ_REG(hw, E1000_MPTC); 694 temp = E1000_READ_REG(hw, E1000_BPTC); 695} 696 697/** 698 * e1000_check_for_copper_link_generic - Check for link (Copper) 699 * @hw: pointer to the HW structure 700 * 701 * Checks to see of the link status of the hardware has changed. If a 702 * change in link status has been detected, then we read the PHY registers 703 * to get the current speed/duplex if link exists. 704 **/ 705s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 706{ 707 struct e1000_mac_info *mac = &hw->mac; 708 s32 ret_val; 709 bool link; 710 711 DEBUGFUNC("e1000_check_for_copper_link"); 712 713 /* 714 * We only want to go out to the PHY registers to see if Auto-Neg 715 * has completed and/or if our link status has changed. The 716 * get_link_status flag is set upon receiving a Link Status 717 * Change or Rx Sequence Error interrupt. 718 */ 719 if (!mac->get_link_status) { 720 ret_val = E1000_SUCCESS; 721 goto out; 722 } 723 724 /* 725 * First we want to see if the MII Status Register reports 726 * link. If so, then we want to get the current speed/duplex 727 * of the PHY. 728 */ 729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730 if (ret_val) 731 goto out; 732 733 if (!link) 734 goto out; /* No link detected */ 735 736 mac->get_link_status = FALSE; 737 738 /* 739 * Check if there was DownShift, must be checked 740 * immediately after link-up 741 */ 742 e1000_check_downshift_generic(hw); 743 744 /* 745 * If we are forcing speed/duplex, then we simply return since 746 * we have already determined whether we have link or not. 747 */ 748 if (!mac->autoneg) { 749 ret_val = -E1000_ERR_CONFIG; 750 goto out; 751 } 752 753 /* 754 * Auto-Neg is enabled. Auto Speed Detection takes care 755 * of MAC speed/duplex configuration. So we only need to 756 * configure Collision Distance in the MAC. 757 */ 758 e1000_config_collision_dist_generic(hw); 759 760 /* 761 * Configure Flow Control now that Auto-Neg has completed. 762 * First, we need to restore the desired flow control 763 * settings because we may have had to re-autoneg with a 764 * different link partner. 765 */ 766 ret_val = e1000_config_fc_after_link_up_generic(hw); 767 if (ret_val) { 768 DEBUGOUT("Error configuring flow control\n"); 769 } 770 771out: 772 return ret_val; 773} 774 775/** 776 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 777 * @hw: pointer to the HW structure 778 * 779 * Checks for link up on the hardware. If link is not up and we have 780 * a signal, then we need to force link up. 781 **/ 782s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 783{ 784 struct e1000_mac_info *mac = &hw->mac; 785 u32 rxcw; 786 u32 ctrl; 787 u32 status; 788 s32 ret_val = E1000_SUCCESS; 789 790 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 791 792 ctrl = E1000_READ_REG(hw, E1000_CTRL); 793 status = E1000_READ_REG(hw, E1000_STATUS); 794 rxcw = E1000_READ_REG(hw, E1000_RXCW); 795 796 /* 797 * If we don't have link (auto-negotiation failed or link partner 798 * cannot auto-negotiate), the cable is plugged in (we have signal), 799 * and our link partner is not trying to auto-negotiate with us (we 800 * are receiving idles or data), we need to force link up. We also 801 * need to give auto-negotiation time to complete, in case the cable 802 * was just plugged in. The autoneg_failed flag does this. 803 */ 804 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 805 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 806 (!(rxcw & E1000_RXCW_C))) { 807 if (mac->autoneg_failed == 0) { 808 mac->autoneg_failed = 1; 809 goto out; 810 } 811 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 812 813 /* Disable auto-negotiation in the TXCW register */ 814 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 815 816 /* Force link-up and also force full-duplex. */ 817 ctrl = E1000_READ_REG(hw, E1000_CTRL); 818 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 819 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 820 821 /* Configure Flow Control after forcing link up. */ 822 ret_val = e1000_config_fc_after_link_up_generic(hw); 823 if (ret_val) { 824 DEBUGOUT("Error configuring flow control\n"); 825 goto out; 826 } 827 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 828 /* 829 * If we are forcing link and we are receiving /C/ ordered 830 * sets, re-enable auto-negotiation in the TXCW register 831 * and disable forced link in the Device Control register 832 * in an attempt to auto-negotiate with our link partner. 833 */ 834 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 835 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 836 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 837 838 mac->serdes_has_link = TRUE; 839 } 840 841out: 842 return ret_val; 843} 844 845/** 846 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 847 * @hw: pointer to the HW structure 848 * 849 * Checks for link up on the hardware. If link is not up and we have 850 * a signal, then we need to force link up. 851 **/ 852s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 853{ 854 struct e1000_mac_info *mac = &hw->mac; 855 u32 rxcw; 856 u32 ctrl; 857 u32 status; 858 s32 ret_val = E1000_SUCCESS; 859 860 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 861 862 ctrl = E1000_READ_REG(hw, E1000_CTRL); 863 status = E1000_READ_REG(hw, E1000_STATUS); 864 rxcw = E1000_READ_REG(hw, E1000_RXCW); 865 866 /* 867 * If we don't have link (auto-negotiation failed or link partner 868 * cannot auto-negotiate), and our link partner is not trying to 869 * auto-negotiate with us (we are receiving idles or data), 870 * we need to force link up. We also need to give auto-negotiation 871 * time to complete. 872 */ 873 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 874 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 875 if (mac->autoneg_failed == 0) { 876 mac->autoneg_failed = 1; 877 goto out; 878 } 879 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 880 881 /* Disable auto-negotiation in the TXCW register */ 882 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 883 884 /* Force link-up and also force full-duplex. */ 885 ctrl = E1000_READ_REG(hw, E1000_CTRL); 886 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 887 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 888 889 /* Configure Flow Control after forcing link up. */ 890 ret_val = e1000_config_fc_after_link_up_generic(hw); 891 if (ret_val) { 892 DEBUGOUT("Error configuring flow control\n"); 893 goto out; 894 } 895 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 896 /* 897 * If we are forcing link and we are receiving /C/ ordered 898 * sets, re-enable auto-negotiation in the TXCW register 899 * and disable forced link in the Device Control register 900 * in an attempt to auto-negotiate with our link partner. 901 */ 902 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 903 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 904 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 905 906 mac->serdes_has_link = TRUE; 907 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 908 /* 909 * If we force link for non-auto-negotiation switch, check 910 * link status based on MAC synchronization for internal 911 * serdes media type. 912 */ 913 /* SYNCH bit and IV bit are sticky. */ 914 usec_delay(10); 915 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 916 if (!(rxcw & E1000_RXCW_IV)) { 917 mac->serdes_has_link = TRUE; 918 DEBUGOUT("SERDES: Link is up.\n"); 919 } 920 } else { 921 mac->serdes_has_link = FALSE; 922 DEBUGOUT("SERDES: Link is down.\n"); 923 } 924 } 925 926 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 927 status = E1000_READ_REG(hw, E1000_STATUS); 928 mac->serdes_has_link = (status & E1000_STATUS_LU) 929 ? TRUE 930 : FALSE; 931 } 932 933out: 934 return ret_val; 935} 936 937/** 938 * e1000_setup_link_generic - Setup flow control and link settings 939 * @hw: pointer to the HW structure 940 * 941 * Determines which flow control settings to use, then configures flow 942 * control. Calls the appropriate media-specific link configuration 943 * function. Assuming the adapter has a valid link partner, a valid link 944 * should be established. Assumes the hardware has previously been reset 945 * and the transmitter and receiver are not enabled. 946 **/ 947s32 e1000_setup_link_generic(struct e1000_hw *hw) 948{ 949 s32 ret_val = E1000_SUCCESS; 950 951 DEBUGFUNC("e1000_setup_link_generic"); 952 953 /* 954 * In the case of the phy reset being blocked, we already have a link. 955 * We do not need to set it up again. 956 */ 957 if (hw->phy.ops.check_reset_block) 958 if (hw->phy.ops.check_reset_block(hw)) 959 goto out; 960 961 /* 962 * If flow control is set to default, set flow control based on 963 * the EEPROM flow control settings. 964 */ 965 if (hw->fc.type == e1000_fc_default) { 966 ret_val = e1000_set_default_fc_generic(hw); 967 if (ret_val) 968 goto out; 969 } 970 971 /* 972 * We want to save off the original Flow Control configuration just 973 * in case we get disconnected and then reconnected into a different 974 * hub or switch with different Flow Control capabilities. 975 */ 976 hw->fc.original_type = hw->fc.type; 977 978 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 979 980 /* Call the necessary media_type subroutine to configure the link. */ 981 ret_val = hw->mac.ops.setup_physical_interface(hw); 982 if (ret_val) 983 goto out; 984 985 /* 986 * Initialize the flow control address, type, and PAUSE timer 987 * registers to their default values. This is done even if flow 988 * control is disabled, because it does not hurt anything to 989 * initialize these registers. 990 */ 991 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 992 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 993 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 994 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 995 996 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 997 998 ret_val = e1000_set_fc_watermarks_generic(hw); 999 1000out: 1001 return ret_val; 1002} 1003 1004/** 1005 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1006 * @hw: pointer to the HW structure 1007 * 1008 * Configures collision distance and flow control for fiber and serdes 1009 * links. Upon successful setup, poll for link. 1010 **/ 1011s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1012{ 1013 u32 ctrl; 1014 s32 ret_val = E1000_SUCCESS; 1015 1016 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1017 1018 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1019 1020 /* Take the link out of reset */ 1021 ctrl &= ~E1000_CTRL_LRST; 1022 1023 e1000_config_collision_dist_generic(hw); 1024 1025 ret_val = e1000_commit_fc_settings_generic(hw); 1026 if (ret_val) 1027 goto out; 1028 1029 /* 1030 * Since auto-negotiation is enabled, take the link out of reset (the 1031 * link will be in reset, because we previously reset the chip). This 1032 * will restart auto-negotiation. If auto-negotiation is successful 1033 * then the link-up status bit will be set and the flow control enable 1034 * bits (RFCE and TFCE) will be set according to their negotiated value. 1035 */ 1036 DEBUGOUT("Auto-negotiation enabled\n"); 1037 1038 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1039 E1000_WRITE_FLUSH(hw); 1040 msec_delay(1); 1041 1042 /* 1043 * For these adapters, the SW definable pin 1 is set when the optics 1044 * detect a signal. If we have a signal, then poll for a "Link-Up" 1045 * indication. 1046 */ 1047 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1048 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1049 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1050 } else { 1051 DEBUGOUT("No signal detected\n"); 1052 } 1053 1054out: 1055 return ret_val; 1056} 1057 1058/** 1059 * e1000_config_collision_dist_generic - Configure collision distance 1060 * @hw: pointer to the HW structure 1061 * 1062 * Configures the collision distance to the default value and is used 1063 * during link setup. Currently no func pointer exists and all 1064 * implementations are handled in the generic version of this function. 1065 **/ 1066void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1067{ 1068 u32 tctl; 1069 1070 DEBUGFUNC("e1000_config_collision_dist_generic"); 1071 1072 tctl = E1000_READ_REG(hw, E1000_TCTL); 1073 1074 tctl &= ~E1000_TCTL_COLD; 1075 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1076 1077 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1078 E1000_WRITE_FLUSH(hw); 1079} 1080 1081/** 1082 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1083 * @hw: pointer to the HW structure 1084 * 1085 * Polls for link up by reading the status register, if link fails to come 1086 * up with auto-negotiation, then the link is forced if a signal is detected. 1087 **/ 1088s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1089{ 1090 struct e1000_mac_info *mac = &hw->mac; 1091 u32 i, status; 1092 s32 ret_val = E1000_SUCCESS; 1093 1094 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1095 1096 /* 1097 * If we have a signal (the cable is plugged in, or assumed TRUE for 1098 * serdes media) then poll for a "Link-Up" indication in the Device 1099 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1100 * seconds (Auto-negotiation should complete in less than 500 1101 * milliseconds even if the other end is doing it in SW). 1102 */ 1103 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1104 msec_delay(10); 1105 status = E1000_READ_REG(hw, E1000_STATUS); 1106 if (status & E1000_STATUS_LU) 1107 break; 1108 } 1109 if (i == FIBER_LINK_UP_LIMIT) { 1110 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1111 mac->autoneg_failed = 1; 1112 /* 1113 * AutoNeg failed to achieve a link, so we'll call 1114 * mac->check_for_link. This routine will force the 1115 * link up if we detect a signal. This will allow us to 1116 * communicate with non-autonegotiating link partners. 1117 */ 1118 ret_val = hw->mac.ops.check_for_link(hw); 1119 if (ret_val) { 1120 DEBUGOUT("Error while checking for link\n"); 1121 goto out; 1122 } 1123 mac->autoneg_failed = 0; 1124 } else { 1125 mac->autoneg_failed = 0; 1126 DEBUGOUT("Valid Link Found\n"); 1127 } 1128 1129out: 1130 return ret_val; 1131} 1132 1133/** 1134 * e1000_commit_fc_settings_generic - Configure flow control 1135 * @hw: pointer to the HW structure 1136 * 1137 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1138 * base on the flow control settings in e1000_mac_info. 1139 **/ 1140s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1141{ 1142 struct e1000_mac_info *mac = &hw->mac; 1143 u32 txcw; 1144 s32 ret_val = E1000_SUCCESS; 1145 1146 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1147 1148 /* 1149 * Check for a software override of the flow control settings, and 1150 * setup the device accordingly. If auto-negotiation is enabled, then 1151 * software will have to set the "PAUSE" bits to the correct value in 1152 * the Transmit Config Word Register (TXCW) and re-start auto- 1153 * negotiation. However, if auto-negotiation is disabled, then 1154 * software will have to manually configure the two flow control enable 1155 * bits in the CTRL register. 1156 * 1157 * The possible values of the "fc" parameter are: 1158 * 0: Flow control is completely disabled 1159 * 1: Rx flow control is enabled (we can receive pause frames, 1160 * but not send pause frames). 1161 * 2: Tx flow control is enabled (we can send pause frames but we 1162 * do not support receiving pause frames). 1163 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1164 */ 1165 switch (hw->fc.type) { 1166 case e1000_fc_none: 1167 /* Flow control completely disabled by a software over-ride. */ 1168 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1169 break; 1170 case e1000_fc_rx_pause: 1171 /* 1172 * Rx Flow control is enabled and Tx Flow control is disabled 1173 * by a software over-ride. Since there really isn't a way to 1174 * advertise that we are capable of Rx Pause ONLY, we will 1175 * advertise that we support both symmetric and asymmetric RX 1176 * PAUSE. Later, we will disable the adapter's ability to send 1177 * PAUSE frames. 1178 */ 1179 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1180 break; 1181 case e1000_fc_tx_pause: 1182 /* 1183 * Tx Flow control is enabled, and Rx Flow control is disabled, 1184 * by a software over-ride. 1185 */ 1186 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1187 break; 1188 case e1000_fc_full: 1189 /* 1190 * Flow control (both Rx and Tx) is enabled by a software 1191 * over-ride. 1192 */ 1193 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1194 break; 1195 default: 1196 DEBUGOUT("Flow control param set incorrectly\n"); 1197 ret_val = -E1000_ERR_CONFIG; 1198 goto out; 1199 break; 1200 } 1201 1202 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1203 mac->txcw = txcw; 1204 1205out: 1206 return ret_val; 1207} 1208 1209/** 1210 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1211 * @hw: pointer to the HW structure 1212 * 1213 * Sets the flow control high/low threshold (watermark) registers. If 1214 * flow control XON frame transmission is enabled, then set XON frame 1215 * transmission as well. 1216 **/ 1217s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1218{ 1219 s32 ret_val = E1000_SUCCESS; 1220 u32 fcrtl = 0, fcrth = 0; 1221 1222 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1223 1224 /* 1225 * Set the flow control receive threshold registers. Normally, 1226 * these registers will be set to a default threshold that may be 1227 * adjusted later by the driver's runtime code. However, if the 1228 * ability to transmit pause frames is not enabled, then these 1229 * registers will be set to 0. 1230 */ 1231 if (hw->fc.type & e1000_fc_tx_pause) { 1232 /* 1233 * We need to set up the Receive Threshold high and low water 1234 * marks as well as (optionally) enabling the transmission of 1235 * XON frames. 1236 */ 1237 fcrtl = hw->fc.low_water; 1238 if (hw->fc.send_xon) 1239 fcrtl |= E1000_FCRTL_XONE; 1240 1241 fcrth = hw->fc.high_water; 1242 } 1243 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1244 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1245 1246 return ret_val; 1247} 1248 1249/** 1250 * e1000_set_default_fc_generic - Set flow control default values 1251 * @hw: pointer to the HW structure 1252 * 1253 * Read the EEPROM for the default values for flow control and store the 1254 * values. 1255 **/ 1256s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1257{ 1258 s32 ret_val = E1000_SUCCESS; 1259 u16 nvm_data; 1260 1261 DEBUGFUNC("e1000_set_default_fc_generic"); 1262 1263 /* 1264 * Read and store word 0x0F of the EEPROM. This word contains bits 1265 * that determine the hardware's default PAUSE (flow control) mode, 1266 * a bit that determines whether the HW defaults to enabling or 1267 * disabling auto-negotiation, and the direction of the 1268 * SW defined pins. If there is no SW over-ride of the flow 1269 * control setting, then the variable hw->fc will 1270 * be initialized based on a value in the EEPROM. 1271 */ 1272 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1273 1274 if (ret_val) { 1275 DEBUGOUT("NVM Read Error\n"); 1276 goto out; 1277 } 1278 1279 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1280 hw->fc.type = e1000_fc_none; 1281 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1282 NVM_WORD0F_ASM_DIR) 1283 hw->fc.type = e1000_fc_tx_pause; 1284 else 1285 hw->fc.type = e1000_fc_full; 1286 1287out: 1288 return ret_val; 1289} 1290 1291/** 1292 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1293 * @hw: pointer to the HW structure 1294 * 1295 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1296 * device control register to reflect the adapter settings. TFCE and RFCE 1297 * need to be explicitly set by software when a copper PHY is used because 1298 * autonegotiation is managed by the PHY rather than the MAC. Software must 1299 * also configure these bits when link is forced on a fiber connection. 1300 **/ 1301s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1302{ 1303 u32 ctrl; 1304 s32 ret_val = E1000_SUCCESS; 1305 1306 DEBUGFUNC("e1000_force_mac_fc_generic"); 1307 1308 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1309 1310 /* 1311 * Because we didn't get link via the internal auto-negotiation 1312 * mechanism (we either forced link or we got link via PHY 1313 * auto-neg), we have to manually enable/disable transmit an 1314 * receive flow control. 1315 * 1316 * The "Case" statement below enables/disable flow control 1317 * according to the "hw->fc.type" parameter. 1318 * 1319 * The possible values of the "fc" parameter are: 1320 * 0: Flow control is completely disabled 1321 * 1: Rx flow control is enabled (we can receive pause 1322 * frames but not send pause frames). 1323 * 2: Tx flow control is enabled (we can send pause frames 1324 * frames but we do not receive pause frames). 1325 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1326 * other: No other values should be possible at this point. 1327 */ 1328 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1329 1330 switch (hw->fc.type) { 1331 case e1000_fc_none: 1332 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1333 break; 1334 case e1000_fc_rx_pause: 1335 ctrl &= (~E1000_CTRL_TFCE); 1336 ctrl |= E1000_CTRL_RFCE; 1337 break; 1338 case e1000_fc_tx_pause: 1339 ctrl &= (~E1000_CTRL_RFCE); 1340 ctrl |= E1000_CTRL_TFCE; 1341 break; 1342 case e1000_fc_full: 1343 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1344 break; 1345 default: 1346 DEBUGOUT("Flow control param set incorrectly\n"); 1347 ret_val = -E1000_ERR_CONFIG; 1348 goto out; 1349 } 1350 1351 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1352 1353out: 1354 return ret_val; 1355} 1356 1357/** 1358 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1359 * @hw: pointer to the HW structure 1360 * 1361 * Checks the status of auto-negotiation after link up to ensure that the 1362 * speed and duplex were not forced. If the link needed to be forced, then 1363 * flow control needs to be forced also. If auto-negotiation is enabled 1364 * and did not fail, then we configure flow control based on our link 1365 * partner. 1366 **/ 1367s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1368{ 1369 struct e1000_mac_info *mac = &hw->mac; 1370 struct e1000_phy_info *phy = &hw->phy; 1371 s32 ret_val = E1000_SUCCESS; 1372 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1373 u16 speed, duplex; 1374 1375 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1376 1377 /* 1378 * Check for the case where we have fiber media and auto-neg failed 1379 * so we had to force link. In this case, we need to force the 1380 * configuration of the MAC to match the "fc" parameter. 1381 */ 1382 if (mac->autoneg_failed) { 1383 if (hw->phy.media_type == e1000_media_type_fiber || 1384 hw->phy.media_type == e1000_media_type_internal_serdes) 1385 ret_val = e1000_force_mac_fc_generic(hw); 1386 } else { 1387 if (hw->phy.media_type == e1000_media_type_copper) 1388 ret_val = e1000_force_mac_fc_generic(hw); 1389 } 1390 1391 if (ret_val) { 1392 DEBUGOUT("Error forcing flow control settings\n"); 1393 goto out; 1394 } 1395 1396 /* 1397 * Check for the case where we have copper media and auto-neg is 1398 * enabled. In this case, we need to check and see if Auto-Neg 1399 * has completed, and if so, how the PHY and link partner has 1400 * flow control configured. 1401 */ 1402 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1403 /* 1404 * Read the MII Status Register and check to see if AutoNeg 1405 * has completed. We read this twice because this reg has 1406 * some "sticky" (latched) bits. 1407 */ 1408 ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1409 if (ret_val) 1410 goto out; 1411 ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1412 if (ret_val) 1413 goto out; 1414 1415 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1416 DEBUGOUT("Copper PHY and Auto Neg " 1417 "has not completed.\n"); 1418 goto out; 1419 } 1420 1421 /* 1422 * The AutoNeg process has completed, so we now need to 1423 * read both the Auto Negotiation Advertisement 1424 * Register (Address 4) and the Auto_Negotiation Base 1425 * Page Ability Register (Address 5) to determine how 1426 * flow control was negotiated. 1427 */ 1428 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, 1429 &mii_nway_adv_reg); 1430 if (ret_val) 1431 goto out; 1432 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, 1433 &mii_nway_lp_ability_reg); 1434 if (ret_val) 1435 goto out; 1436 1437 /* 1438 * Two bits in the Auto Negotiation Advertisement Register 1439 * (Address 4) and two bits in the Auto Negotiation Base 1440 * Page Ability Register (Address 5) determine flow control 1441 * for both the PHY and the link partner. The following 1442 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1443 * 1999, describes these PAUSE resolution bits and how flow 1444 * control is determined based upon these settings. 1445 * NOTE: DC = Don't Care 1446 * 1447 * LOCAL DEVICE | LINK PARTNER 1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1449 *-------|---------|-------|---------|-------------------- 1450 * 0 | 0 | DC | DC | e1000_fc_none 1451 * 0 | 1 | 0 | DC | e1000_fc_none 1452 * 0 | 1 | 1 | 0 | e1000_fc_none 1453 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1454 * 1 | 0 | 0 | DC | e1000_fc_none 1455 * 1 | DC | 1 | DC | e1000_fc_full 1456 * 1 | 1 | 0 | 0 | e1000_fc_none 1457 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1458 * 1459 * Are both PAUSE bits set to 1? If so, this implies 1460 * Symmetric Flow Control is enabled at both ends. The 1461 * ASM_DIR bits are irrelevant per the spec. 1462 * 1463 * For Symmetric Flow Control: 1464 * 1465 * LOCAL DEVICE | LINK PARTNER 1466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467 *-------|---------|-------|---------|-------------------- 1468 * 1 | DC | 1 | DC | E1000_fc_full 1469 * 1470 */ 1471 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1472 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1473 /* 1474 * Now we need to check if the user selected Rx ONLY 1475 * of pause frames. In this case, we had to advertise 1476 * FULL flow control because we could not advertise RX 1477 * ONLY. Hence, we must now check to see if we need to 1478 * turn OFF the TRANSMISSION of PAUSE frames. 1479 */ 1480 if (hw->fc.original_type == e1000_fc_full) { 1481 hw->fc.type = e1000_fc_full; 1482 DEBUGOUT("Flow Control = FULL.\r\n"); 1483 } else { 1484 hw->fc.type = e1000_fc_rx_pause; 1485 DEBUGOUT("Flow Control = " 1486 "RX PAUSE frames only.\r\n"); 1487 } 1488 } 1489 /* 1490 * For receiving PAUSE frames ONLY. 1491 * 1492 * LOCAL DEVICE | LINK PARTNER 1493 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1494 *-------|---------|-------|---------|-------------------- 1495 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1496 */ 1497 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1498 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1499 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1500 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1501 hw->fc.type = e1000_fc_tx_pause; 1502 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1503 } 1504 /* 1505 * For transmitting PAUSE frames ONLY. 1506 * 1507 * LOCAL DEVICE | LINK PARTNER 1508 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1509 *-------|---------|-------|---------|-------------------- 1510 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1511 */ 1512 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1513 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1514 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1515 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1516 hw->fc.type = e1000_fc_rx_pause; 1517 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1518 } else { 1519 /* 1520 * Per the IEEE spec, at this point flow control 1521 * should be disabled. 1522 */ 1523 hw->fc.type = e1000_fc_none; 1524 DEBUGOUT("Flow Control = NONE.\r\n"); 1525 } 1526 1527 /* 1528 * Now we need to do one last check... If we auto- 1529 * negotiated to HALF DUPLEX, flow control should not be 1530 * enabled per IEEE 802.3 spec. 1531 */ 1532 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1533 if (ret_val) { 1534 DEBUGOUT("Error getting link speed and duplex\n"); 1535 goto out; 1536 } 1537 1538 if (duplex == HALF_DUPLEX) 1539 hw->fc.type = e1000_fc_none; 1540 1541 /* 1542 * Now we call a subroutine to actually force the MAC 1543 * controller to use the correct flow control settings. 1544 */ 1545 ret_val = e1000_force_mac_fc_generic(hw); 1546 if (ret_val) { 1547 DEBUGOUT("Error forcing flow control settings\n"); 1548 goto out; 1549 } 1550 } 1551 1552out: 1553 return ret_val; 1554} 1555 1556/** 1557 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1558 * @hw: pointer to the HW structure 1559 * @speed: stores the current speed 1560 * @duplex: stores the current duplex 1561 * 1562 * Read the status register for the current speed/duplex and store the current 1563 * speed and duplex for copper connections. 1564 **/ 1565s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1566 u16 *duplex) 1567{ 1568 u32 status; 1569 1570 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1571 1572 status = E1000_READ_REG(hw, E1000_STATUS); 1573 if (status & E1000_STATUS_SPEED_1000) { 1574 *speed = SPEED_1000; 1575 DEBUGOUT("1000 Mbs, "); 1576 } else if (status & E1000_STATUS_SPEED_100) { 1577 *speed = SPEED_100; 1578 DEBUGOUT("100 Mbs, "); 1579 } else { 1580 *speed = SPEED_10; 1581 DEBUGOUT("10 Mbs, "); 1582 } 1583 1584 if (status & E1000_STATUS_FD) { 1585 *duplex = FULL_DUPLEX; 1586 DEBUGOUT("Full Duplex\n"); 1587 } else { 1588 *duplex = HALF_DUPLEX; 1589 DEBUGOUT("Half Duplex\n"); 1590 } 1591 1592 return E1000_SUCCESS; 1593} 1594 1595/** 1596 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1597 * @hw: pointer to the HW structure 1598 * @speed: stores the current speed 1599 * @duplex: stores the current duplex 1600 * 1601 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1602 * for fiber/serdes links. 1603 **/ 1604s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1605 u16 *speed, u16 *duplex) 1606{ 1607 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1608 1609 *speed = SPEED_1000; 1610 *duplex = FULL_DUPLEX; 1611 1612 return E1000_SUCCESS; 1613} 1614 1615/** 1616 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1617 * @hw: pointer to the HW structure 1618 * 1619 * Acquire the HW semaphore to access the PHY or NVM 1620 **/ 1621s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1622{ 1623 u32 swsm; 1624 s32 ret_val = E1000_SUCCESS; 1625 s32 timeout = hw->nvm.word_size + 1; 1626 s32 i = 0; 1627 1628 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1629 1630 /* Get the SW semaphore */ 1631 while (i < timeout) { 1632 swsm = E1000_READ_REG(hw, E1000_SWSM); 1633 if (!(swsm & E1000_SWSM_SMBI)) 1634 break; 1635 1636 usec_delay(50); 1637 i++; 1638 } 1639 1640 if (i == timeout) { 1641 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1642 ret_val = -E1000_ERR_NVM; 1643 goto out; 1644 } 1645 1646 /* Get the FW semaphore. */ 1647 for (i = 0; i < timeout; i++) { 1648 swsm = E1000_READ_REG(hw, E1000_SWSM); 1649 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1650 1651 /* Semaphore acquired if bit latched */ 1652 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1653 break; 1654 1655 usec_delay(50); 1656 } 1657 1658 if (i == timeout) { 1659 /* Release semaphores */ 1660 e1000_put_hw_semaphore_generic(hw); 1661 DEBUGOUT("Driver can't access the NVM\n"); 1662 ret_val = -E1000_ERR_NVM; 1663 goto out; 1664 } 1665 1666out: 1667 return ret_val; 1668} 1669 1670/** 1671 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1672 * @hw: pointer to the HW structure 1673 * 1674 * Release hardware semaphore used to access the PHY or NVM 1675 **/ 1676void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1677{ 1678 u32 swsm; 1679 1680 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1681 1682 swsm = E1000_READ_REG(hw, E1000_SWSM); 1683 1684 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1685 1686 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1687} 1688 1689/** 1690 * e1000_get_auto_rd_done_generic - Check for auto read completion 1691 * @hw: pointer to the HW structure 1692 * 1693 * Check EEPROM for Auto Read done bit. 1694 **/ 1695s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1696{ 1697 s32 i = 0; 1698 s32 ret_val = E1000_SUCCESS; 1699 1700 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1701 1702 while (i < AUTO_READ_DONE_TIMEOUT) { 1703 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1704 break; 1705 msec_delay(1); 1706 i++; 1707 } 1708 1709 if (i == AUTO_READ_DONE_TIMEOUT) { 1710 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1711 ret_val = -E1000_ERR_RESET; 1712 goto out; 1713 } 1714 1715out: 1716 return ret_val; 1717} 1718 1719/** 1720 * e1000_valid_led_default_generic - Verify a valid default LED config 1721 * @hw: pointer to the HW structure 1722 * @data: pointer to the NVM (EEPROM) 1723 * 1724 * Read the EEPROM for the current default LED configuration. If the 1725 * LED configuration is not valid, set to a valid LED configuration. 1726 **/ 1727s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1728{ 1729 s32 ret_val; 1730 1731 DEBUGFUNC("e1000_valid_led_default_generic"); 1732 1733 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1734 if (ret_val) { 1735 DEBUGOUT("NVM Read Error\n"); 1736 goto out; 1737 } 1738 1739 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1740 *data = ID_LED_DEFAULT; 1741 1742out: 1743 return ret_val; 1744} 1745 1746/** 1747 * e1000_id_led_init_generic - 1748 * @hw: pointer to the HW structure 1749 * 1750 **/ 1751s32 e1000_id_led_init_generic(struct e1000_hw * hw) 1752{ 1753 struct e1000_mac_info *mac = &hw->mac; 1754 s32 ret_val; 1755 const u32 ledctl_mask = 0x000000FF; 1756 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1757 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1758 u16 data, i, temp; 1759 const u16 led_mask = 0x0F; 1760 1761 DEBUGFUNC("e1000_id_led_init_generic"); 1762 1763 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1764 if (ret_val) 1765 goto out; 1766 1767 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1768 mac->ledctl_mode1 = mac->ledctl_default; 1769 mac->ledctl_mode2 = mac->ledctl_default; 1770 1771 for (i = 0; i < 4; i++) { 1772 temp = (data >> (i << 2)) & led_mask; 1773 switch (temp) { 1774 case ID_LED_ON1_DEF2: 1775 case ID_LED_ON1_ON2: 1776 case ID_LED_ON1_OFF2: 1777 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1778 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1779 break; 1780 case ID_LED_OFF1_DEF2: 1781 case ID_LED_OFF1_ON2: 1782 case ID_LED_OFF1_OFF2: 1783 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1784 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1785 break; 1786 default: 1787 /* Do nothing */ 1788 break; 1789 } 1790 switch (temp) { 1791 case ID_LED_DEF1_ON2: 1792 case ID_LED_ON1_ON2: 1793 case ID_LED_OFF1_ON2: 1794 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1795 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1796 break; 1797 case ID_LED_DEF1_OFF2: 1798 case ID_LED_ON1_OFF2: 1799 case ID_LED_OFF1_OFF2: 1800 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1801 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1802 break; 1803 default: 1804 /* Do nothing */ 1805 break; 1806 } 1807 } 1808 1809out: 1810 return ret_val; 1811} 1812 1813/** 1814 * e1000_setup_led_generic - Configures SW controllable LED 1815 * @hw: pointer to the HW structure 1816 * 1817 * This prepares the SW controllable LED for use and saves the current state 1818 * of the LED so it can be later restored. 1819 **/ 1820s32 e1000_setup_led_generic(struct e1000_hw *hw) 1821{ 1822 u32 ledctl; 1823 s32 ret_val = E1000_SUCCESS; 1824 1825 DEBUGFUNC("e1000_setup_led_generic"); 1826 1827 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1828 ret_val = -E1000_ERR_CONFIG; 1829 goto out; 1830 } 1831 1832 if (hw->phy.media_type == e1000_media_type_fiber) { 1833 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1834 hw->mac.ledctl_default = ledctl; 1835 /* Turn off LED0 */ 1836 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1837 E1000_LEDCTL_LED0_BLINK | 1838 E1000_LEDCTL_LED0_MODE_MASK); 1839 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1840 E1000_LEDCTL_LED0_MODE_SHIFT); 1841 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1842 } else if (hw->phy.media_type == e1000_media_type_copper) { 1843 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1844 } 1845 1846out: 1847 return ret_val; 1848} 1849 1850/** 1851 * e1000_cleanup_led_generic - Set LED config to default operation 1852 * @hw: pointer to the HW structure 1853 * 1854 * Remove the current LED configuration and set the LED configuration 1855 * to the default value, saved from the EEPROM. 1856 **/ 1857s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1858{ 1859 s32 ret_val = E1000_SUCCESS; 1860 1861 DEBUGFUNC("e1000_cleanup_led_generic"); 1862 1863 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1864 ret_val = -E1000_ERR_CONFIG; 1865 goto out; 1866 } 1867 1868 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1869 1870out: 1871 return ret_val; 1872} 1873 1874/** 1875 * e1000_blink_led_generic - Blink LED 1876 * @hw: pointer to the HW structure 1877 * 1878 * Blink the LEDs which are set to be on. 1879 **/ 1880s32 e1000_blink_led_generic(struct e1000_hw *hw) 1881{ 1882 u32 ledctl_blink = 0; 1883 u32 i; 1884 1885 DEBUGFUNC("e1000_blink_led_generic"); 1886 1887 if (hw->phy.media_type == e1000_media_type_fiber) { 1888 /* always blink LED0 for PCI-E fiber */ 1889 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1890 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1891 } else { 1892 /* 1893 * set the blink bit for each LED that's "on" (0x0E) 1894 * in ledctl_mode2 1895 */ 1896 ledctl_blink = hw->mac.ledctl_mode2; 1897 for (i = 0; i < 4; i++) 1898 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1899 E1000_LEDCTL_MODE_LED_ON) 1900 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1901 (i * 8)); 1902 } 1903 1904 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1905 1906 return E1000_SUCCESS; 1907} 1908 1909/** 1910 * e1000_led_on_generic - Turn LED on 1911 * @hw: pointer to the HW structure 1912 * 1913 * Turn LED on. 1914 **/ 1915s32 e1000_led_on_generic(struct e1000_hw *hw) 1916{ 1917 u32 ctrl; 1918 1919 DEBUGFUNC("e1000_led_on_generic"); 1920 1921 switch (hw->phy.media_type) { 1922 case e1000_media_type_fiber: 1923 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1924 ctrl &= ~E1000_CTRL_SWDPIN0; 1925 ctrl |= E1000_CTRL_SWDPIO0; 1926 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1927 break; 1928 case e1000_media_type_copper: 1929 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1930 break; 1931 default: 1932 break; 1933 } 1934 1935 return E1000_SUCCESS; 1936} 1937 1938/** 1939 * e1000_led_off_generic - Turn LED off 1940 * @hw: pointer to the HW structure 1941 * 1942 * Turn LED off. 1943 **/ 1944s32 e1000_led_off_generic(struct e1000_hw *hw) 1945{ 1946 u32 ctrl; 1947 1948 DEBUGFUNC("e1000_led_off_generic"); 1949 1950 switch (hw->phy.media_type) { 1951 case e1000_media_type_fiber: 1952 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1953 ctrl |= E1000_CTRL_SWDPIN0; 1954 ctrl |= E1000_CTRL_SWDPIO0; 1955 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1956 break; 1957 case e1000_media_type_copper: 1958 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1959 break; 1960 default: 1961 break; 1962 } 1963 1964 return E1000_SUCCESS; 1965} 1966 1967/** 1968 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1969 * @hw: pointer to the HW structure 1970 * @no_snoop: bitmap of snoop events 1971 * 1972 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1973 **/ 1974void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1975{ 1976 u32 gcr; 1977 1978 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1979 1980 if (hw->bus.type != e1000_bus_type_pci_express) 1981 goto out; 1982 1983 if (no_snoop) { 1984 gcr = E1000_READ_REG(hw, E1000_GCR); 1985 gcr &= ~(PCIE_NO_SNOOP_ALL); 1986 gcr |= no_snoop; 1987 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1988 } 1989out: 1990 return; 1991} 1992 1993/** 1994 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1995 * @hw: pointer to the HW structure 1996 * 1997 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1998 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1999 * the master requests to be disabled. 2000 * 2001 * Disables PCI-Express master access and verifies there are no pending 2002 * requests. 2003 **/ 2004s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2005{ 2006 u32 ctrl; 2007 s32 timeout = MASTER_DISABLE_TIMEOUT; 2008 s32 ret_val = E1000_SUCCESS; 2009 2010 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2011 2012 if (hw->bus.type != e1000_bus_type_pci_express) 2013 goto out; 2014 2015 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2016 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2017 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2018 2019 while (timeout) { 2020 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2021 E1000_STATUS_GIO_MASTER_ENABLE)) 2022 break; 2023 usec_delay(100); 2024 timeout--; 2025 } 2026 2027 if (!timeout) { 2028 DEBUGOUT("Master requests are pending.\n"); 2029 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2030 goto out; 2031 } 2032 2033out: 2034 return ret_val; 2035} 2036 2037/** 2038 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2039 * @hw: pointer to the HW structure 2040 * 2041 * Reset the Adaptive Interframe Spacing throttle to default values. 2042 **/ 2043void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2044{ 2045 struct e1000_mac_info *mac = &hw->mac; 2046 2047 DEBUGFUNC("e1000_reset_adaptive_generic"); 2048 2049 if (!mac->adaptive_ifs) { 2050 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2051 goto out; 2052 } 2053 2054 if (!mac->ifs_params_forced) { 2055 mac->current_ifs_val = 0; 2056 mac->ifs_min_val = IFS_MIN; 2057 mac->ifs_max_val = IFS_MAX; 2058 mac->ifs_step_size = IFS_STEP; 2059 mac->ifs_ratio = IFS_RATIO; 2060 } 2061 2062 mac->in_ifs_mode = FALSE; 2063 E1000_WRITE_REG(hw, E1000_AIT, 0); 2064out: 2065 return; 2066} 2067 2068/** 2069 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2070 * @hw: pointer to the HW structure 2071 * 2072 * Update the Adaptive Interframe Spacing Throttle value based on the 2073 * time between transmitted packets and time between collisions. 2074 **/ 2075void e1000_update_adaptive_generic(struct e1000_hw *hw) 2076{ 2077 struct e1000_mac_info *mac = &hw->mac; 2078 2079 DEBUGFUNC("e1000_update_adaptive_generic"); 2080 2081 if (!mac->adaptive_ifs) { 2082 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2083 goto out; 2084 } 2085 2086 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2087 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2088 mac->in_ifs_mode = TRUE; 2089 if (mac->current_ifs_val < mac->ifs_max_val) { 2090 if (!mac->current_ifs_val) 2091 mac->current_ifs_val = mac->ifs_min_val; 2092 else 2093 mac->current_ifs_val += 2094 mac->ifs_step_size; 2095 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2096 } 2097 } 2098 } else { 2099 if (mac->in_ifs_mode && 2100 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2101 mac->current_ifs_val = 0; 2102 mac->in_ifs_mode = FALSE; 2103 E1000_WRITE_REG(hw, E1000_AIT, 0); 2104 } 2105 } 2106out: 2107 return; 2108} 2109 2110/** 2111 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2112 * @hw: pointer to the HW structure 2113 * 2114 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2115 * set, which is forced to MDI mode only. 2116 **/ 2117s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2118{ 2119 s32 ret_val = E1000_SUCCESS; 2120 2121 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2122 2123 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2124 DEBUGOUT("Invalid MDI setting detected\n"); 2125 hw->phy.mdix = 1; 2126 ret_val = -E1000_ERR_CONFIG; 2127 goto out; 2128 } 2129 2130out: 2131 return ret_val; 2132} 2133 2134/** 2135 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2136 * @hw: pointer to the HW structure 2137 * @reg: 32bit register offset such as E1000_SCTL 2138 * @offset: register offset to write to 2139 * @data: data to write at register offset 2140 * 2141 * Writes an address/data control type register. There are several of these 2142 * and they all have the format address << 8 | data and bit 31 is polled for 2143 * completion. 2144 **/ 2145s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2146 u32 offset, u8 data) 2147{ 2148 u32 i, regvalue = 0; 2149 s32 ret_val = E1000_SUCCESS; 2150 2151 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2152 2153 /* Set up the address and data */ 2154 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2155 E1000_WRITE_REG(hw, reg, regvalue); 2156 2157 /* Poll the ready bit to see if the MDI read completed */ 2158 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2159 usec_delay(5); 2160 regvalue = E1000_READ_REG(hw, reg); 2161 if (regvalue & E1000_GEN_CTL_READY) 2162 break; 2163 } 2164 if (!(regvalue & E1000_GEN_CTL_READY)) { 2165 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2166 ret_val = -E1000_ERR_PHY; 2167 goto out; 2168 } 2169 2170out: 2171 return ret_val; 2172} 2173