e1000_mac.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_mac.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36#include "e1000_api.h" 37#include "e1000_mac.h" 38 39/** 40 * e1000_remove_device_generic - Free device specific structure 41 * @hw: pointer to the HW structure 42 * 43 * If a device specific structure was allocated, this function will 44 * free it. 45 **/ 46void e1000_remove_device_generic(struct e1000_hw *hw) 47{ 48 DEBUGFUNC("e1000_remove_device_generic"); 49 50 /* Freeing the dev_spec member of e1000_hw structure */ 51 e1000_free_dev_spec_struct(hw); 52} 53 54/** 55 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 56 * @hw: pointer to the HW structure 57 * 58 * Determines and stores the system bus information for a particular 59 * network interface. The following bus information is determined and stored: 60 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 61 **/ 62s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 63{ 64 struct e1000_bus_info *bus = &hw->bus; 65 u32 status = E1000_READ_REG(hw, E1000_STATUS); 66 s32 ret_val = E1000_SUCCESS; 67 u16 pci_header_type; 68 69 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 70 71 /* PCI or PCI-X? */ 72 bus->type = (status & E1000_STATUS_PCIX_MODE) 73 ? e1000_bus_type_pcix 74 : e1000_bus_type_pci; 75 76 /* Bus speed */ 77 if (bus->type == e1000_bus_type_pci) { 78 bus->speed = (status & E1000_STATUS_PCI66) 79 ? e1000_bus_speed_66 80 : e1000_bus_speed_33; 81 } else { 82 switch (status & E1000_STATUS_PCIX_SPEED) { 83 case E1000_STATUS_PCIX_SPEED_66: 84 bus->speed = e1000_bus_speed_66; 85 break; 86 case E1000_STATUS_PCIX_SPEED_100: 87 bus->speed = e1000_bus_speed_100; 88 break; 89 case E1000_STATUS_PCIX_SPEED_133: 90 bus->speed = e1000_bus_speed_133; 91 break; 92 default: 93 bus->speed = e1000_bus_speed_reserved; 94 break; 95 } 96 } 97 98 /* Bus width */ 99 bus->width = (status & E1000_STATUS_BUS64) 100 ? e1000_bus_width_64 101 : e1000_bus_width_32; 102 103 /* Which PCI(-X) function? */ 104 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 105 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 106 bus->func = (status & E1000_STATUS_FUNC_MASK) 107 >> E1000_STATUS_FUNC_SHIFT; 108 else 109 bus->func = 0; 110 111 return ret_val; 112} 113 114/** 115 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 116 * @hw: pointer to the HW structure 117 * 118 * Determines and stores the system bus information for a particular 119 * network interface. The following bus information is determined and stored: 120 * bus speed, bus width, type (PCIe), and PCIe function. 121 **/ 122s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 123{ 124 struct e1000_bus_info *bus = &hw->bus; 125 s32 ret_val; 126 u32 status; 127 u16 pcie_link_status, pci_header_type; 128 129 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 130 131 bus->type = e1000_bus_type_pci_express; 132 bus->speed = e1000_bus_speed_2500; 133 134 ret_val = e1000_read_pcie_cap_reg(hw, 135 PCIE_LINK_STATUS, 136 &pcie_link_status); 137 if (ret_val) 138 bus->width = e1000_bus_width_unknown; 139 else 140 bus->width = (e1000_bus_width)((pcie_link_status & 141 PCIE_LINK_WIDTH_MASK) >> 142 PCIE_LINK_WIDTH_SHIFT); 143 144 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 145 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 146 status = E1000_READ_REG(hw, E1000_STATUS); 147 bus->func = (status & E1000_STATUS_FUNC_MASK) 148 >> E1000_STATUS_FUNC_SHIFT; 149 } else { 150 bus->func = 0; 151 } 152 153 return E1000_SUCCESS; 154} 155 156/** 157 * e1000_clear_vfta_generic - Clear VLAN filter table 158 * @hw: pointer to the HW structure 159 * 160 * Clears the register array which contains the VLAN filter table by 161 * setting all the values to 0. 162 **/ 163void e1000_clear_vfta_generic(struct e1000_hw *hw) 164{ 165 u32 offset; 166 167 DEBUGFUNC("e1000_clear_vfta_generic"); 168 169 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 170 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 171 E1000_WRITE_FLUSH(hw); 172 } 173} 174 175/** 176 * e1000_write_vfta_generic - Write value to VLAN filter table 177 * @hw: pointer to the HW structure 178 * @offset: register offset in VLAN filter table 179 * @value: register value written to VLAN filter table 180 * 181 * Writes value at the given offset in the register array which stores 182 * the VLAN filter table. 183 **/ 184void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 185{ 186 DEBUGFUNC("e1000_write_vfta_generic"); 187 188 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 189 E1000_WRITE_FLUSH(hw); 190} 191 192/** 193 * e1000_init_rx_addrs_generic - Initialize receive address's 194 * @hw: pointer to the HW structure 195 * @rar_count: receive address registers 196 * 197 * Setups the receive address registers by setting the base receive address 198 * register to the devices MAC address and clearing all the other receive 199 * address registers to 0. 200 **/ 201void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 202{ 203 u32 i; 204 205 DEBUGFUNC("e1000_init_rx_addrs_generic"); 206 207 /* Setup the receive address */ 208 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 209 210 e1000_rar_set_generic(hw, hw->mac.addr, 0); 211 212 /* Zero out the other (rar_entry_count - 1) receive addresses */ 213 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 214 for (i = 1; i < rar_count; i++) { 215 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 216 E1000_WRITE_FLUSH(hw); 217 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 218 E1000_WRITE_FLUSH(hw); 219 } 220} 221 222/** 223 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 224 * @hw: pointer to the HW structure 225 * 226 * Checks the nvm for an alternate MAC address. An alternate MAC address 227 * can be setup by pre-boot software and must be treated like a permanent 228 * address and must override the actual permanent MAC address. If an 229 * alternate MAC address is found it is saved in the hw struct and 230 * programmed into RAR0 and the function returns success, otherwise the 231 * function returns an error. 232 **/ 233s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 234{ 235 u32 i; 236 s32 ret_val = E1000_SUCCESS; 237 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 238 u8 alt_mac_addr[ETH_ADDR_LEN]; 239 240 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 241 242 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 243 &nvm_alt_mac_addr_offset); 244 if (ret_val) { 245 DEBUGOUT("NVM Read Error\n"); 246 goto out; 247 } 248 249 if (nvm_alt_mac_addr_offset == 0xFFFF) { 250 ret_val = -(E1000_NOT_IMPLEMENTED); 251 goto out; 252 } 253 254 if (hw->bus.func == E1000_FUNC_1) 255 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16); 256 257 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 258 offset = nvm_alt_mac_addr_offset + (i >> 1); 259 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 260 if (ret_val) { 261 DEBUGOUT("NVM Read Error\n"); 262 goto out; 263 } 264 265 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 266 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 267 } 268 269 /* if multicast bit is set, the alternate address will not be used */ 270 if (alt_mac_addr[0] & 0x01) { 271 ret_val = -(E1000_NOT_IMPLEMENTED); 272 goto out; 273 } 274 275 for (i = 0; i < ETH_ADDR_LEN; i++) 276 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 277 278 e1000_rar_set(hw, hw->mac.perm_addr, 0); 279 280out: 281 return ret_val; 282} 283 284/** 285 * e1000_rar_set_generic - Set receive address register 286 * @hw: pointer to the HW structure 287 * @addr: pointer to the receive address 288 * @index: receive address array register 289 * 290 * Sets the receive address array register at index to the address passed 291 * in by addr. 292 **/ 293void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 294{ 295 u32 rar_low, rar_high; 296 297 DEBUGFUNC("e1000_rar_set_generic"); 298 299 /* 300 * HW expects these in little endian so we reverse the byte order 301 * from network order (big endian) to little endian 302 */ 303 rar_low = ((u32) addr[0] | 304 ((u32) addr[1] << 8) | 305 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 306 307 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 308 309 /* If MAC address zero, no need to set the AV bit */ 310 if (rar_low || rar_high) { 311 if (!hw->mac.disable_av) 312 rar_high |= E1000_RAH_AV; 313 } 314 315 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 316 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 317} 318 319/** 320 * e1000_mta_set_generic - Set multicast filter table address 321 * @hw: pointer to the HW structure 322 * @hash_value: determines the MTA register and bit to set 323 * 324 * The multicast table address is a register array of 32-bit registers. 325 * The hash_value is used to determine what register the bit is in, the 326 * current value is read, the new bit is OR'd in and the new value is 327 * written back into the register. 328 **/ 329void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 330{ 331 u32 hash_bit, hash_reg, mta; 332 333 DEBUGFUNC("e1000_mta_set_generic"); 334 /* 335 * The MTA is a register array of 32-bit registers. It is 336 * treated like an array of (32*mta_reg_count) bits. We want to 337 * set bit BitArray[hash_value]. So we figure out what register 338 * the bit is in, read it, OR in the new bit, then write 339 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 340 * mask to bits 31:5 of the hash value which gives us the 341 * register we're modifying. The hash bit within that register 342 * is determined by the lower 5 bits of the hash value. 343 */ 344 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 345 hash_bit = hash_value & 0x1F; 346 347 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 348 349 mta |= (1 << hash_bit); 350 351 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 352 E1000_WRITE_FLUSH(hw); 353} 354 355/** 356 * e1000_update_mc_addr_list_generic - Update Multicast addresses 357 * @hw: pointer to the HW structure 358 * @mc_addr_list: array of multicast addresses to program 359 * @mc_addr_count: number of multicast addresses to program 360 * @rar_used_count: the first RAR register free to program 361 * @rar_count: total number of supported Receive Address Registers 362 * 363 * Updates the Receive Address Registers and Multicast Table Array. 364 * The caller must have a packed mc_addr_list of multicast addresses. 365 * The parameter rar_count will usually be hw->mac.rar_entry_count 366 * unless there are workarounds that change this. 367 **/ 368void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 369 u8 *mc_addr_list, u32 mc_addr_count, 370 u32 rar_used_count, u32 rar_count) 371{ 372 u32 hash_value; 373 u32 i; 374 375 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 376 377 /* 378 * Load the first set of multicast addresses into the exact 379 * filters (RAR). If there are not enough to fill the RAR 380 * array, clear the filters. 381 */ 382 for (i = rar_used_count; i < rar_count; i++) { 383 if (mc_addr_count) { 384 e1000_rar_set(hw, mc_addr_list, i); 385 mc_addr_count--; 386 mc_addr_list += ETH_ADDR_LEN; 387 } else { 388 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 389 E1000_WRITE_FLUSH(hw); 390 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 391 E1000_WRITE_FLUSH(hw); 392 } 393 } 394 395 /* Clear the old settings from the MTA */ 396 DEBUGOUT("Clearing MTA\n"); 397 for (i = 0; i < hw->mac.mta_reg_count; i++) { 398 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 399 E1000_WRITE_FLUSH(hw); 400 } 401 402 /* Load any remaining multicast addresses into the hash table. */ 403 for (; mc_addr_count > 0; mc_addr_count--) { 404 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 405 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 406 e1000_mta_set(hw, hash_value); 407 mc_addr_list += ETH_ADDR_LEN; 408 } 409} 410 411/** 412 * e1000_hash_mc_addr_generic - Generate a multicast hash value 413 * @hw: pointer to the HW structure 414 * @mc_addr: pointer to a multicast address 415 * 416 * Generates a multicast address hash value which is used to determine 417 * the multicast filter table array address and new table value. See 418 * e1000_mta_set_generic() 419 **/ 420u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 421{ 422 u32 hash_value, hash_mask; 423 u8 bit_shift = 0; 424 425 DEBUGFUNC("e1000_hash_mc_addr_generic"); 426 427 /* Register count multiplied by bits per register */ 428 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 429 430 /* 431 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 432 * where 0xFF would still fall within the hash mask. 433 */ 434 while (hash_mask >> bit_shift != 0xFF) 435 bit_shift++; 436 437 /* 438 * The portion of the address that is used for the hash table 439 * is determined by the mc_filter_type setting. 440 * The algorithm is such that there is a total of 8 bits of shifting. 441 * The bit_shift for a mc_filter_type of 0 represents the number of 442 * left-shifts where the MSB of mc_addr[5] would still fall within 443 * the hash_mask. Case 0 does this exactly. Since there are a total 444 * of 8 bits of shifting, then mc_addr[4] will shift right the 445 * remaining number of bits. Thus 8 - bit_shift. The rest of the 446 * cases are a variation of this algorithm...essentially raising the 447 * number of bits to shift mc_addr[5] left, while still keeping the 448 * 8-bit shifting total. 449 * 450 * For example, given the following Destination MAC Address and an 451 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 452 * we can see that the bit_shift for case 0 is 4. These are the hash 453 * values resulting from each mc_filter_type... 454 * [0] [1] [2] [3] [4] [5] 455 * 01 AA 00 12 34 56 456 * LSB MSB 457 * 458 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 459 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 460 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 461 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 462 */ 463 switch (hw->mac.mc_filter_type) { 464 default: 465 case 0: 466 break; 467 case 1: 468 bit_shift += 1; 469 break; 470 case 2: 471 bit_shift += 2; 472 break; 473 case 3: 474 bit_shift += 4; 475 break; 476 } 477 478 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 479 (((u16) mc_addr[5]) << bit_shift))); 480 481 return hash_value; 482} 483 484/** 485 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 486 * @hw: pointer to the HW structure 487 * 488 * In certain situations, a system BIOS may report that the PCIx maximum 489 * memory read byte count (MMRBC) value is higher than than the actual 490 * value. We check the PCIx command register with the current PCIx status 491 * register. 492 **/ 493void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 494{ 495 u16 cmd_mmrbc; 496 u16 pcix_cmd; 497 u16 pcix_stat_hi_word; 498 u16 stat_mmrbc; 499 500 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 501 502 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 503 if (hw->bus.type != e1000_bus_type_pcix) 504 return; 505 506 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 507 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 508 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 509 PCIX_COMMAND_MMRBC_SHIFT; 510 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 511 PCIX_STATUS_HI_MMRBC_SHIFT; 512 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 513 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 514 if (cmd_mmrbc > stat_mmrbc) { 515 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 516 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 517 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 518 } 519} 520 521/** 522 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 523 * @hw: pointer to the HW structure 524 * 525 * Clears the base hardware counters by reading the counter registers. 526 **/ 527void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 528{ 529 volatile u32 temp; 530 531 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 532 533 temp = E1000_READ_REG(hw, E1000_CRCERRS); 534 temp = E1000_READ_REG(hw, E1000_SYMERRS); 535 temp = E1000_READ_REG(hw, E1000_MPC); 536 temp = E1000_READ_REG(hw, E1000_SCC); 537 temp = E1000_READ_REG(hw, E1000_ECOL); 538 temp = E1000_READ_REG(hw, E1000_MCC); 539 temp = E1000_READ_REG(hw, E1000_LATECOL); 540 temp = E1000_READ_REG(hw, E1000_COLC); 541 temp = E1000_READ_REG(hw, E1000_DC); 542 temp = E1000_READ_REG(hw, E1000_SEC); 543 temp = E1000_READ_REG(hw, E1000_RLEC); 544 temp = E1000_READ_REG(hw, E1000_XONRXC); 545 temp = E1000_READ_REG(hw, E1000_XONTXC); 546 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 547 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 548 temp = E1000_READ_REG(hw, E1000_FCRUC); 549 temp = E1000_READ_REG(hw, E1000_GPRC); 550 temp = E1000_READ_REG(hw, E1000_BPRC); 551 temp = E1000_READ_REG(hw, E1000_MPRC); 552 temp = E1000_READ_REG(hw, E1000_GPTC); 553 temp = E1000_READ_REG(hw, E1000_GORCL); 554 temp = E1000_READ_REG(hw, E1000_GORCH); 555 temp = E1000_READ_REG(hw, E1000_GOTCL); 556 temp = E1000_READ_REG(hw, E1000_GOTCH); 557 temp = E1000_READ_REG(hw, E1000_RNBC); 558 temp = E1000_READ_REG(hw, E1000_RUC); 559 temp = E1000_READ_REG(hw, E1000_RFC); 560 temp = E1000_READ_REG(hw, E1000_ROC); 561 temp = E1000_READ_REG(hw, E1000_RJC); 562 temp = E1000_READ_REG(hw, E1000_TORL); 563 temp = E1000_READ_REG(hw, E1000_TORH); 564 temp = E1000_READ_REG(hw, E1000_TOTL); 565 temp = E1000_READ_REG(hw, E1000_TOTH); 566 temp = E1000_READ_REG(hw, E1000_TPR); 567 temp = E1000_READ_REG(hw, E1000_TPT); 568 temp = E1000_READ_REG(hw, E1000_MPTC); 569 temp = E1000_READ_REG(hw, E1000_BPTC); 570} 571 572/** 573 * e1000_check_for_copper_link_generic - Check for link (Copper) 574 * @hw: pointer to the HW structure 575 * 576 * Checks to see of the link status of the hardware has changed. If a 577 * change in link status has been detected, then we read the PHY registers 578 * to get the current speed/duplex if link exists. 579 **/ 580s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 581{ 582 struct e1000_mac_info *mac = &hw->mac; 583 s32 ret_val; 584 bool link; 585 586 DEBUGFUNC("e1000_check_for_copper_link"); 587 588 /* 589 * We only want to go out to the PHY registers to see if Auto-Neg 590 * has completed and/or if our link status has changed. The 591 * get_link_status flag is set upon receiving a Link Status 592 * Change or Rx Sequence Error interrupt. 593 */ 594 if (!mac->get_link_status) { 595 ret_val = E1000_SUCCESS; 596 goto out; 597 } 598 599 /* 600 * First we want to see if the MII Status Register reports 601 * link. If so, then we want to get the current speed/duplex 602 * of the PHY. 603 */ 604 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 605 if (ret_val) 606 goto out; 607 608 if (!link) 609 goto out; /* No link detected */ 610 611 mac->get_link_status = FALSE; 612 613 /* 614 * Check if there was DownShift, must be checked 615 * immediately after link-up 616 */ 617 e1000_check_downshift_generic(hw); 618 619 /* 620 * If we are forcing speed/duplex, then we simply return since 621 * we have already determined whether we have link or not. 622 */ 623 if (!mac->autoneg) { 624 ret_val = -E1000_ERR_CONFIG; 625 goto out; 626 } 627 628 /* 629 * Auto-Neg is enabled. Auto Speed Detection takes care 630 * of MAC speed/duplex configuration. So we only need to 631 * configure Collision Distance in the MAC. 632 */ 633 e1000_config_collision_dist_generic(hw); 634 635 /* 636 * Configure Flow Control now that Auto-Neg has completed. 637 * First, we need to restore the desired flow control 638 * settings because we may have had to re-autoneg with a 639 * different link partner. 640 */ 641 ret_val = e1000_config_fc_after_link_up_generic(hw); 642 if (ret_val) { 643 DEBUGOUT("Error configuring flow control\n"); 644 } 645 646out: 647 return ret_val; 648} 649 650/** 651 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 652 * @hw: pointer to the HW structure 653 * 654 * Checks for link up on the hardware. If link is not up and we have 655 * a signal, then we need to force link up. 656 **/ 657s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 658{ 659 struct e1000_mac_info *mac = &hw->mac; 660 u32 rxcw; 661 u32 ctrl; 662 u32 status; 663 s32 ret_val = E1000_SUCCESS; 664 665 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 666 667 ctrl = E1000_READ_REG(hw, E1000_CTRL); 668 status = E1000_READ_REG(hw, E1000_STATUS); 669 rxcw = E1000_READ_REG(hw, E1000_RXCW); 670 671 /* 672 * If we don't have link (auto-negotiation failed or link partner 673 * cannot auto-negotiate), the cable is plugged in (we have signal), 674 * and our link partner is not trying to auto-negotiate with us (we 675 * are receiving idles or data), we need to force link up. We also 676 * need to give auto-negotiation time to complete, in case the cable 677 * was just plugged in. The autoneg_failed flag does this. 678 */ 679 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 680 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 681 (!(rxcw & E1000_RXCW_C))) { 682 if (mac->autoneg_failed == 0) { 683 mac->autoneg_failed = 1; 684 goto out; 685 } 686 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 687 688 /* Disable auto-negotiation in the TXCW register */ 689 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 690 691 /* Force link-up and also force full-duplex. */ 692 ctrl = E1000_READ_REG(hw, E1000_CTRL); 693 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 694 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 695 696 /* Configure Flow Control after forcing link up. */ 697 ret_val = e1000_config_fc_after_link_up_generic(hw); 698 if (ret_val) { 699 DEBUGOUT("Error configuring flow control\n"); 700 goto out; 701 } 702 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 703 /* 704 * If we are forcing link and we are receiving /C/ ordered 705 * sets, re-enable auto-negotiation in the TXCW register 706 * and disable forced link in the Device Control register 707 * in an attempt to auto-negotiate with our link partner. 708 */ 709 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 710 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 711 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 712 713 mac->serdes_has_link = TRUE; 714 } 715 716out: 717 return ret_val; 718} 719 720/** 721 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 722 * @hw: pointer to the HW structure 723 * 724 * Checks for link up on the hardware. If link is not up and we have 725 * a signal, then we need to force link up. 726 **/ 727s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 728{ 729 struct e1000_mac_info *mac = &hw->mac; 730 u32 rxcw; 731 u32 ctrl; 732 u32 status; 733 s32 ret_val = E1000_SUCCESS; 734 735 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 736 737 ctrl = E1000_READ_REG(hw, E1000_CTRL); 738 status = E1000_READ_REG(hw, E1000_STATUS); 739 rxcw = E1000_READ_REG(hw, E1000_RXCW); 740 741 /* 742 * If we don't have link (auto-negotiation failed or link partner 743 * cannot auto-negotiate), and our link partner is not trying to 744 * auto-negotiate with us (we are receiving idles or data), 745 * we need to force link up. We also need to give auto-negotiation 746 * time to complete. 747 */ 748 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 749 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 750 if (mac->autoneg_failed == 0) { 751 mac->autoneg_failed = 1; 752 goto out; 753 } 754 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 755 756 /* Disable auto-negotiation in the TXCW register */ 757 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 758 759 /* Force link-up and also force full-duplex. */ 760 ctrl = E1000_READ_REG(hw, E1000_CTRL); 761 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 762 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 763 764 /* Configure Flow Control after forcing link up. */ 765 ret_val = e1000_config_fc_after_link_up_generic(hw); 766 if (ret_val) { 767 DEBUGOUT("Error configuring flow control\n"); 768 goto out; 769 } 770 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 771 /* 772 * If we are forcing link and we are receiving /C/ ordered 773 * sets, re-enable auto-negotiation in the TXCW register 774 * and disable forced link in the Device Control register 775 * in an attempt to auto-negotiate with our link partner. 776 */ 777 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 778 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 779 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 780 781 mac->serdes_has_link = TRUE; 782 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 783 /* 784 * If we force link for non-auto-negotiation switch, check 785 * link status based on MAC synchronization for internal 786 * serdes media type. 787 */ 788 /* SYNCH bit and IV bit are sticky. */ 789 usec_delay(10); 790 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 791 if (!(rxcw & E1000_RXCW_IV)) { 792 mac->serdes_has_link = TRUE; 793 DEBUGOUT("SERDES: Link is up.\n"); 794 } 795 } else { 796 mac->serdes_has_link = FALSE; 797 DEBUGOUT("SERDES: Link is down.\n"); 798 } 799 } 800 801 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 802 status = E1000_READ_REG(hw, E1000_STATUS); 803 mac->serdes_has_link = (status & E1000_STATUS_LU) 804 ? TRUE 805 : FALSE; 806 } 807 808out: 809 return ret_val; 810} 811 812/** 813 * e1000_setup_link_generic - Setup flow control and link settings 814 * @hw: pointer to the HW structure 815 * 816 * Determines which flow control settings to use, then configures flow 817 * control. Calls the appropriate media-specific link configuration 818 * function. Assuming the adapter has a valid link partner, a valid link 819 * should be established. Assumes the hardware has previously been reset 820 * and the transmitter and receiver are not enabled. 821 **/ 822s32 e1000_setup_link_generic(struct e1000_hw *hw) 823{ 824 struct e1000_functions *func = &hw->func; 825 s32 ret_val = E1000_SUCCESS; 826 827 DEBUGFUNC("e1000_setup_link_generic"); 828 829 /* 830 * In the case of the phy reset being blocked, we already have a link. 831 * We do not need to set it up again. 832 */ 833 if (e1000_check_reset_block(hw)) 834 goto out; 835 836 /* 837 * If flow control is set to default, set flow control based on 838 * the EEPROM flow control settings. 839 */ 840 if (hw->fc.type == e1000_fc_default) { 841 ret_val = e1000_set_default_fc_generic(hw); 842 if (ret_val) 843 goto out; 844 } 845 846 /* 847 * We want to save off the original Flow Control configuration just 848 * in case we get disconnected and then reconnected into a different 849 * hub or switch with different Flow Control capabilities. 850 */ 851 hw->fc.original_type = hw->fc.type; 852 853 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 854 855 /* Call the necessary media_type subroutine to configure the link. */ 856 ret_val = func->setup_physical_interface(hw); 857 if (ret_val) 858 goto out; 859 860 /* 861 * Initialize the flow control address, type, and PAUSE timer 862 * registers to their default values. This is done even if flow 863 * control is disabled, because it does not hurt anything to 864 * initialize these registers. 865 */ 866 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 867 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 868 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 869 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 870 871 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 872 873 ret_val = e1000_set_fc_watermarks_generic(hw); 874 875out: 876 return ret_val; 877} 878 879/** 880 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 881 * @hw: pointer to the HW structure 882 * 883 * Configures collision distance and flow control for fiber and serdes 884 * links. Upon successful setup, poll for link. 885 **/ 886s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 887{ 888 u32 ctrl; 889 s32 ret_val = E1000_SUCCESS; 890 891 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 892 893 ctrl = E1000_READ_REG(hw, E1000_CTRL); 894 895 /* Take the link out of reset */ 896 ctrl &= ~E1000_CTRL_LRST; 897 898 e1000_config_collision_dist_generic(hw); 899 900 ret_val = e1000_commit_fc_settings_generic(hw); 901 if (ret_val) 902 goto out; 903 904 /* 905 * Since auto-negotiation is enabled, take the link out of reset (the 906 * link will be in reset, because we previously reset the chip). This 907 * will restart auto-negotiation. If auto-negotiation is successful 908 * then the link-up status bit will be set and the flow control enable 909 * bits (RFCE and TFCE) will be set according to their negotiated value. 910 */ 911 DEBUGOUT("Auto-negotiation enabled\n"); 912 913 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 914 E1000_WRITE_FLUSH(hw); 915 msec_delay(1); 916 917 /* 918 * For these adapters, the SW definable pin 1 is set when the optics 919 * detect a signal. If we have a signal, then poll for a "Link-Up" 920 * indication. 921 */ 922 if (hw->phy.media_type == e1000_media_type_internal_serdes || 923 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 924 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 925 } else { 926 DEBUGOUT("No signal detected\n"); 927 } 928 929out: 930 return ret_val; 931} 932 933/** 934 * e1000_config_collision_dist_generic - Configure collision distance 935 * @hw: pointer to the HW structure 936 * 937 * Configures the collision distance to the default value and is used 938 * during link setup. Currently no func pointer exists and all 939 * implementations are handled in the generic version of this function. 940 **/ 941void e1000_config_collision_dist_generic(struct e1000_hw *hw) 942{ 943 u32 tctl; 944 945 DEBUGFUNC("e1000_config_collision_dist_generic"); 946 947 tctl = E1000_READ_REG(hw, E1000_TCTL); 948 949 tctl &= ~E1000_TCTL_COLD; 950 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 951 952 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 953 E1000_WRITE_FLUSH(hw); 954} 955 956/** 957 * e1000_poll_fiber_serdes_link_generic - Poll for link up 958 * @hw: pointer to the HW structure 959 * 960 * Polls for link up by reading the status register, if link fails to come 961 * up with auto-negotiation, then the link is forced if a signal is detected. 962 **/ 963s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 964{ 965 struct e1000_mac_info *mac = &hw->mac; 966 u32 i, status; 967 s32 ret_val = E1000_SUCCESS; 968 969 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 970 971 /* 972 * If we have a signal (the cable is plugged in, or assumed true for 973 * serdes media) then poll for a "Link-Up" indication in the Device 974 * Status Register. Time-out if a link isn't seen in 500 milliseconds 975 * seconds (Auto-negotiation should complete in less than 500 976 * milliseconds even if the other end is doing it in SW). 977 */ 978 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 979 msec_delay(10); 980 status = E1000_READ_REG(hw, E1000_STATUS); 981 if (status & E1000_STATUS_LU) 982 break; 983 } 984 if (i == FIBER_LINK_UP_LIMIT) { 985 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 986 mac->autoneg_failed = 1; 987 /* 988 * AutoNeg failed to achieve a link, so we'll call 989 * mac->check_for_link. This routine will force the 990 * link up if we detect a signal. This will allow us to 991 * communicate with non-autonegotiating link partners. 992 */ 993 ret_val = e1000_check_for_link(hw); 994 if (ret_val) { 995 DEBUGOUT("Error while checking for link\n"); 996 goto out; 997 } 998 mac->autoneg_failed = 0; 999 } else { 1000 mac->autoneg_failed = 0; 1001 DEBUGOUT("Valid Link Found\n"); 1002 } 1003 1004out: 1005 return ret_val; 1006} 1007 1008/** 1009 * e1000_commit_fc_settings_generic - Configure flow control 1010 * @hw: pointer to the HW structure 1011 * 1012 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1013 * base on the flow control settings in e1000_mac_info. 1014 **/ 1015s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1016{ 1017 struct e1000_mac_info *mac = &hw->mac; 1018 u32 txcw; 1019 s32 ret_val = E1000_SUCCESS; 1020 1021 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1022 1023 /* 1024 * Check for a software override of the flow control settings, and 1025 * setup the device accordingly. If auto-negotiation is enabled, then 1026 * software will have to set the "PAUSE" bits to the correct value in 1027 * the Transmit Config Word Register (TXCW) and re-start auto- 1028 * negotiation. However, if auto-negotiation is disabled, then 1029 * software will have to manually configure the two flow control enable 1030 * bits in the CTRL register. 1031 * 1032 * The possible values of the "fc" parameter are: 1033 * 0: Flow control is completely disabled 1034 * 1: Rx flow control is enabled (we can receive pause frames, 1035 * but not send pause frames). 1036 * 2: Tx flow control is enabled (we can send pause frames but we 1037 * do not support receiving pause frames). 1038 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1039 */ 1040 switch (hw->fc.type) { 1041 case e1000_fc_none: 1042 /* Flow control completely disabled by a software over-ride. */ 1043 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1044 break; 1045 case e1000_fc_rx_pause: 1046 /* 1047 * Rx Flow control is enabled and Tx Flow control is disabled 1048 * by a software over-ride. Since there really isn't a way to 1049 * advertise that we are capable of Rx Pause ONLY, we will 1050 * advertise that we support both symmetric and asymmetric RX 1051 * PAUSE. Later, we will disable the adapter's ability to send 1052 * PAUSE frames. 1053 */ 1054 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1055 break; 1056 case e1000_fc_tx_pause: 1057 /* 1058 * Tx Flow control is enabled, and Rx Flow control is disabled, 1059 * by a software over-ride. 1060 */ 1061 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1062 break; 1063 case e1000_fc_full: 1064 /* 1065 * Flow control (both Rx and Tx) is enabled by a software 1066 * over-ride. 1067 */ 1068 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1069 break; 1070 default: 1071 DEBUGOUT("Flow control param set incorrectly\n"); 1072 ret_val = -E1000_ERR_CONFIG; 1073 goto out; 1074 break; 1075 } 1076 1077 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1078 mac->txcw = txcw; 1079 1080out: 1081 return ret_val; 1082} 1083 1084/** 1085 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1086 * @hw: pointer to the HW structure 1087 * 1088 * Sets the flow control high/low threshold (watermark) registers. If 1089 * flow control XON frame transmission is enabled, then set XON frame 1090 * transmission as well. 1091 **/ 1092s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1093{ 1094 s32 ret_val = E1000_SUCCESS; 1095 u32 fcrtl = 0, fcrth = 0; 1096 1097 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1098 1099 /* 1100 * Set the flow control receive threshold registers. Normally, 1101 * these registers will be set to a default threshold that may be 1102 * adjusted later by the driver's runtime code. However, if the 1103 * ability to transmit pause frames is not enabled, then these 1104 * registers will be set to 0. 1105 */ 1106 if (hw->fc.type & e1000_fc_tx_pause) { 1107 /* 1108 * We need to set up the Receive Threshold high and low water 1109 * marks as well as (optionally) enabling the transmission of 1110 * XON frames. 1111 */ 1112 fcrtl = hw->fc.low_water; 1113 if (hw->fc.send_xon) 1114 fcrtl |= E1000_FCRTL_XONE; 1115 1116 fcrth = hw->fc.high_water; 1117 } 1118 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1119 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1120 1121 return ret_val; 1122} 1123 1124/** 1125 * e1000_set_default_fc_generic - Set flow control default values 1126 * @hw: pointer to the HW structure 1127 * 1128 * Read the EEPROM for the default values for flow control and store the 1129 * values. 1130 **/ 1131s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1132{ 1133 s32 ret_val = E1000_SUCCESS; 1134 u16 nvm_data; 1135 1136 DEBUGFUNC("e1000_set_default_fc_generic"); 1137 1138 /* 1139 * Read and store word 0x0F of the EEPROM. This word contains bits 1140 * that determine the hardware's default PAUSE (flow control) mode, 1141 * a bit that determines whether the HW defaults to enabling or 1142 * disabling auto-negotiation, and the direction of the 1143 * SW defined pins. If there is no SW over-ride of the flow 1144 * control setting, then the variable hw->fc will 1145 * be initialized based on a value in the EEPROM. 1146 */ 1147 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1148 1149 if (ret_val) { 1150 DEBUGOUT("NVM Read Error\n"); 1151 goto out; 1152 } 1153 1154 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1155 hw->fc.type = e1000_fc_none; 1156 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1157 NVM_WORD0F_ASM_DIR) 1158 hw->fc.type = e1000_fc_tx_pause; 1159 else 1160 hw->fc.type = e1000_fc_full; 1161 1162out: 1163 return ret_val; 1164} 1165 1166/** 1167 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1168 * @hw: pointer to the HW structure 1169 * 1170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1171 * device control register to reflect the adapter settings. TFCE and RFCE 1172 * need to be explicitly set by software when a copper PHY is used because 1173 * autonegotiation is managed by the PHY rather than the MAC. Software must 1174 * also configure these bits when link is forced on a fiber connection. 1175 **/ 1176s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1177{ 1178 u32 ctrl; 1179 s32 ret_val = E1000_SUCCESS; 1180 1181 DEBUGFUNC("e1000_force_mac_fc_generic"); 1182 1183 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1184 1185 /* 1186 * Because we didn't get link via the internal auto-negotiation 1187 * mechanism (we either forced link or we got link via PHY 1188 * auto-neg), we have to manually enable/disable transmit an 1189 * receive flow control. 1190 * 1191 * The "Case" statement below enables/disable flow control 1192 * according to the "hw->fc.type" parameter. 1193 * 1194 * The possible values of the "fc" parameter are: 1195 * 0: Flow control is completely disabled 1196 * 1: Rx flow control is enabled (we can receive pause 1197 * frames but not send pause frames). 1198 * 2: Tx flow control is enabled (we can send pause frames 1199 * frames but we do not receive pause frames). 1200 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1201 * other: No other values should be possible at this point. 1202 */ 1203 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1204 1205 switch (hw->fc.type) { 1206 case e1000_fc_none: 1207 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1208 break; 1209 case e1000_fc_rx_pause: 1210 ctrl &= (~E1000_CTRL_TFCE); 1211 ctrl |= E1000_CTRL_RFCE; 1212 break; 1213 case e1000_fc_tx_pause: 1214 ctrl &= (~E1000_CTRL_RFCE); 1215 ctrl |= E1000_CTRL_TFCE; 1216 break; 1217 case e1000_fc_full: 1218 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1219 break; 1220 default: 1221 DEBUGOUT("Flow control param set incorrectly\n"); 1222 ret_val = -E1000_ERR_CONFIG; 1223 goto out; 1224 } 1225 1226 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1227 1228out: 1229 return ret_val; 1230} 1231 1232/** 1233 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1234 * @hw: pointer to the HW structure 1235 * 1236 * Checks the status of auto-negotiation after link up to ensure that the 1237 * speed and duplex were not forced. If the link needed to be forced, then 1238 * flow control needs to be forced also. If auto-negotiation is enabled 1239 * and did not fail, then we configure flow control based on our link 1240 * partner. 1241 **/ 1242s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1243{ 1244 struct e1000_mac_info *mac = &hw->mac; 1245 s32 ret_val = E1000_SUCCESS; 1246 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1247 u16 speed, duplex; 1248 1249 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1250 1251 /* 1252 * Check for the case where we have fiber media and auto-neg failed 1253 * so we had to force link. In this case, we need to force the 1254 * configuration of the MAC to match the "fc" parameter. 1255 */ 1256 if (mac->autoneg_failed) { 1257 if (hw->phy.media_type == e1000_media_type_fiber || 1258 hw->phy.media_type == e1000_media_type_internal_serdes) 1259 ret_val = e1000_force_mac_fc_generic(hw); 1260 } else { 1261 if (hw->phy.media_type == e1000_media_type_copper) 1262 ret_val = e1000_force_mac_fc_generic(hw); 1263 } 1264 1265 if (ret_val) { 1266 DEBUGOUT("Error forcing flow control settings\n"); 1267 goto out; 1268 } 1269 1270 /* 1271 * Check for the case where we have copper media and auto-neg is 1272 * enabled. In this case, we need to check and see if Auto-Neg 1273 * has completed, and if so, how the PHY and link partner has 1274 * flow control configured. 1275 */ 1276 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1277 /* 1278 * Read the MII Status Register and check to see if AutoNeg 1279 * has completed. We read this twice because this reg has 1280 * some "sticky" (latched) bits. 1281 */ 1282 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1283 if (ret_val) 1284 goto out; 1285 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1286 if (ret_val) 1287 goto out; 1288 1289 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1290 DEBUGOUT("Copper PHY and Auto Neg " 1291 "has not completed.\n"); 1292 goto out; 1293 } 1294 1295 /* 1296 * The AutoNeg process has completed, so we now need to 1297 * read both the Auto Negotiation Advertisement 1298 * Register (Address 4) and the Auto_Negotiation Base 1299 * Page Ability Register (Address 5) to determine how 1300 * flow control was negotiated. 1301 */ 1302 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1303 &mii_nway_adv_reg); 1304 if (ret_val) 1305 goto out; 1306 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 1307 &mii_nway_lp_ability_reg); 1308 if (ret_val) 1309 goto out; 1310 1311 /* 1312 * Two bits in the Auto Negotiation Advertisement Register 1313 * (Address 4) and two bits in the Auto Negotiation Base 1314 * Page Ability Register (Address 5) determine flow control 1315 * for both the PHY and the link partner. The following 1316 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1317 * 1999, describes these PAUSE resolution bits and how flow 1318 * control is determined based upon these settings. 1319 * NOTE: DC = Don't Care 1320 * 1321 * LOCAL DEVICE | LINK PARTNER 1322 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1323 *-------|---------|-------|---------|-------------------- 1324 * 0 | 0 | DC | DC | e1000_fc_none 1325 * 0 | 1 | 0 | DC | e1000_fc_none 1326 * 0 | 1 | 1 | 0 | e1000_fc_none 1327 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1328 * 1 | 0 | 0 | DC | e1000_fc_none 1329 * 1 | DC | 1 | DC | e1000_fc_full 1330 * 1 | 1 | 0 | 0 | e1000_fc_none 1331 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1332 * 1333 * Are both PAUSE bits set to 1? If so, this implies 1334 * Symmetric Flow Control is enabled at both ends. The 1335 * ASM_DIR bits are irrelevant per the spec. 1336 * 1337 * For Symmetric Flow Control: 1338 * 1339 * LOCAL DEVICE | LINK PARTNER 1340 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1341 *-------|---------|-------|---------|-------------------- 1342 * 1 | DC | 1 | DC | E1000_fc_full 1343 * 1344 */ 1345 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1346 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1347 /* 1348 * Now we need to check if the user selected Rx ONLY 1349 * of pause frames. In this case, we had to advertise 1350 * FULL flow control because we could not advertise RX 1351 * ONLY. Hence, we must now check to see if we need to 1352 * turn OFF the TRANSMISSION of PAUSE frames. 1353 */ 1354 if (hw->fc.original_type == e1000_fc_full) { 1355 hw->fc.type = e1000_fc_full; 1356 DEBUGOUT("Flow Control = FULL.\r\n"); 1357 } else { 1358 hw->fc.type = e1000_fc_rx_pause; 1359 DEBUGOUT("Flow Control = " 1360 "RX PAUSE frames only.\r\n"); 1361 } 1362 } 1363 /* 1364 * For receiving PAUSE frames ONLY. 1365 * 1366 * LOCAL DEVICE | LINK PARTNER 1367 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1368 *-------|---------|-------|---------|-------------------- 1369 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1370 */ 1371 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1372 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1373 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1374 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1375 hw->fc.type = e1000_fc_tx_pause; 1376 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1377 } 1378 /* 1379 * For transmitting PAUSE frames ONLY. 1380 * 1381 * LOCAL DEVICE | LINK PARTNER 1382 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1383 *-------|---------|-------|---------|-------------------- 1384 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1385 */ 1386 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1387 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1388 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1389 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1390 hw->fc.type = e1000_fc_rx_pause; 1391 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1392 } else { 1393 /* 1394 * Per the IEEE spec, at this point flow control 1395 * should be disabled. 1396 */ 1397 hw->fc.type = e1000_fc_none; 1398 DEBUGOUT("Flow Control = NONE.\r\n"); 1399 } 1400 1401 /* 1402 * Now we need to do one last check... If we auto- 1403 * negotiated to HALF DUPLEX, flow control should not be 1404 * enabled per IEEE 802.3 spec. 1405 */ 1406 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1407 if (ret_val) { 1408 DEBUGOUT("Error getting link speed and duplex\n"); 1409 goto out; 1410 } 1411 1412 if (duplex == HALF_DUPLEX) 1413 hw->fc.type = e1000_fc_none; 1414 1415 /* 1416 * Now we call a subroutine to actually force the MAC 1417 * controller to use the correct flow control settings. 1418 */ 1419 ret_val = e1000_force_mac_fc_generic(hw); 1420 if (ret_val) { 1421 DEBUGOUT("Error forcing flow control settings\n"); 1422 goto out; 1423 } 1424 } 1425 1426out: 1427 return ret_val; 1428} 1429 1430/** 1431 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1432 * @hw: pointer to the HW structure 1433 * @speed: stores the current speed 1434 * @duplex: stores the current duplex 1435 * 1436 * Read the status register for the current speed/duplex and store the current 1437 * speed and duplex for copper connections. 1438 **/ 1439s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1440 u16 *duplex) 1441{ 1442 u32 status; 1443 1444 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1445 1446 status = E1000_READ_REG(hw, E1000_STATUS); 1447 if (status & E1000_STATUS_SPEED_1000) { 1448 *speed = SPEED_1000; 1449 DEBUGOUT("1000 Mbs, "); 1450 } else if (status & E1000_STATUS_SPEED_100) { 1451 *speed = SPEED_100; 1452 DEBUGOUT("100 Mbs, "); 1453 } else { 1454 *speed = SPEED_10; 1455 DEBUGOUT("10 Mbs, "); 1456 } 1457 1458 if (status & E1000_STATUS_FD) { 1459 *duplex = FULL_DUPLEX; 1460 DEBUGOUT("Full Duplex\n"); 1461 } else { 1462 *duplex = HALF_DUPLEX; 1463 DEBUGOUT("Half Duplex\n"); 1464 } 1465 1466 return E1000_SUCCESS; 1467} 1468 1469/** 1470 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1471 * @hw: pointer to the HW structure 1472 * @speed: stores the current speed 1473 * @duplex: stores the current duplex 1474 * 1475 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1476 * for fiber/serdes links. 1477 **/ 1478s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1479 u16 *speed, u16 *duplex) 1480{ 1481 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1482 UNREFERENCED_PARAMETER(hw); 1483 1484 *speed = SPEED_1000; 1485 *duplex = FULL_DUPLEX; 1486 1487 return E1000_SUCCESS; 1488} 1489 1490/** 1491 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1492 * @hw: pointer to the HW structure 1493 * 1494 * Acquire the HW semaphore to access the PHY or NVM 1495 **/ 1496s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1497{ 1498 u32 swsm; 1499 s32 ret_val = E1000_SUCCESS; 1500 s32 timeout = hw->nvm.word_size + 1; 1501 s32 i = 0; 1502 1503 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1504 1505 /* Get the SW semaphore */ 1506 while (i < timeout) { 1507 swsm = E1000_READ_REG(hw, E1000_SWSM); 1508 if (!(swsm & E1000_SWSM_SMBI)) 1509 break; 1510 1511 usec_delay(50); 1512 i++; 1513 } 1514 1515 if (i == timeout) { 1516 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1517 ret_val = -E1000_ERR_NVM; 1518 goto out; 1519 } 1520 1521 /* Get the FW semaphore. */ 1522 for (i = 0; i < timeout; i++) { 1523 swsm = E1000_READ_REG(hw, E1000_SWSM); 1524 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1525 1526 /* Semaphore acquired if bit latched */ 1527 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1528 break; 1529 1530 usec_delay(50); 1531 } 1532 1533 if (i == timeout) { 1534 /* Release semaphores */ 1535 e1000_put_hw_semaphore_generic(hw); 1536 DEBUGOUT("Driver can't access the NVM\n"); 1537 ret_val = -E1000_ERR_NVM; 1538 goto out; 1539 } 1540 1541out: 1542 return ret_val; 1543} 1544 1545/** 1546 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1547 * @hw: pointer to the HW structure 1548 * 1549 * Release hardware semaphore used to access the PHY or NVM 1550 **/ 1551void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1552{ 1553 u32 swsm; 1554 1555 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1556 1557 swsm = E1000_READ_REG(hw, E1000_SWSM); 1558 1559 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1560 1561 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1562} 1563 1564/** 1565 * e1000_get_auto_rd_done_generic - Check for auto read completion 1566 * @hw: pointer to the HW structure 1567 * 1568 * Check EEPROM for Auto Read done bit. 1569 **/ 1570s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1571{ 1572 s32 i = 0; 1573 s32 ret_val = E1000_SUCCESS; 1574 1575 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1576 1577 while (i < AUTO_READ_DONE_TIMEOUT) { 1578 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1579 break; 1580 msec_delay(1); 1581 i++; 1582 } 1583 1584 if (i == AUTO_READ_DONE_TIMEOUT) { 1585 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1586 ret_val = -E1000_ERR_RESET; 1587 goto out; 1588 } 1589 1590out: 1591 return ret_val; 1592} 1593 1594/** 1595 * e1000_valid_led_default_generic - Verify a valid default LED config 1596 * @hw: pointer to the HW structure 1597 * @data: pointer to the NVM (EEPROM) 1598 * 1599 * Read the EEPROM for the current default LED configuration. If the 1600 * LED configuration is not valid, set to a valid LED configuration. 1601 **/ 1602s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1603{ 1604 s32 ret_val; 1605 1606 DEBUGFUNC("e1000_valid_led_default_generic"); 1607 1608 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1609 if (ret_val) { 1610 DEBUGOUT("NVM Read Error\n"); 1611 goto out; 1612 } 1613 1614 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1615 *data = ID_LED_DEFAULT; 1616 1617out: 1618 return ret_val; 1619} 1620 1621/** 1622 * e1000_id_led_init_generic - 1623 * @hw: pointer to the HW structure 1624 * 1625 **/ 1626s32 e1000_id_led_init_generic(struct e1000_hw * hw) 1627{ 1628 struct e1000_mac_info *mac = &hw->mac; 1629 s32 ret_val; 1630 const u32 ledctl_mask = 0x000000FF; 1631 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1632 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1633 u16 data, i, temp; 1634 const u16 led_mask = 0x0F; 1635 1636 DEBUGFUNC("e1000_id_led_init_generic"); 1637 1638 ret_val = hw->func.valid_led_default(hw, &data); 1639 if (ret_val) 1640 goto out; 1641 1642 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1643 mac->ledctl_mode1 = mac->ledctl_default; 1644 mac->ledctl_mode2 = mac->ledctl_default; 1645 1646 for (i = 0; i < 4; i++) { 1647 temp = (data >> (i << 2)) & led_mask; 1648 switch (temp) { 1649 case ID_LED_ON1_DEF2: 1650 case ID_LED_ON1_ON2: 1651 case ID_LED_ON1_OFF2: 1652 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1653 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1654 break; 1655 case ID_LED_OFF1_DEF2: 1656 case ID_LED_OFF1_ON2: 1657 case ID_LED_OFF1_OFF2: 1658 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1659 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1660 break; 1661 default: 1662 /* Do nothing */ 1663 break; 1664 } 1665 switch (temp) { 1666 case ID_LED_DEF1_ON2: 1667 case ID_LED_ON1_ON2: 1668 case ID_LED_OFF1_ON2: 1669 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1670 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1671 break; 1672 case ID_LED_DEF1_OFF2: 1673 case ID_LED_ON1_OFF2: 1674 case ID_LED_OFF1_OFF2: 1675 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1676 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1677 break; 1678 default: 1679 /* Do nothing */ 1680 break; 1681 } 1682 } 1683 1684out: 1685 return ret_val; 1686} 1687 1688/** 1689 * e1000_setup_led_generic - Configures SW controllable LED 1690 * @hw: pointer to the HW structure 1691 * 1692 * This prepares the SW controllable LED for use and saves the current state 1693 * of the LED so it can be later restored. 1694 **/ 1695s32 e1000_setup_led_generic(struct e1000_hw *hw) 1696{ 1697 u32 ledctl; 1698 s32 ret_val = E1000_SUCCESS; 1699 1700 DEBUGFUNC("e1000_setup_led_generic"); 1701 1702 if (hw->func.setup_led != e1000_setup_led_generic) { 1703 ret_val = -E1000_ERR_CONFIG; 1704 goto out; 1705 } 1706 1707 if (hw->phy.media_type == e1000_media_type_fiber) { 1708 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1709 hw->mac.ledctl_default = ledctl; 1710 /* Turn off LED0 */ 1711 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1712 E1000_LEDCTL_LED0_BLINK | 1713 E1000_LEDCTL_LED0_MODE_MASK); 1714 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1715 E1000_LEDCTL_LED0_MODE_SHIFT); 1716 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1717 } else if (hw->phy.media_type == e1000_media_type_copper) { 1718 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1719 } 1720 1721out: 1722 return ret_val; 1723} 1724 1725/** 1726 * e1000_cleanup_led_generic - Set LED config to default operation 1727 * @hw: pointer to the HW structure 1728 * 1729 * Remove the current LED configuration and set the LED configuration 1730 * to the default value, saved from the EEPROM. 1731 **/ 1732s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1733{ 1734 s32 ret_val = E1000_SUCCESS; 1735 1736 DEBUGFUNC("e1000_cleanup_led_generic"); 1737 1738 if (hw->func.cleanup_led != e1000_cleanup_led_generic) { 1739 ret_val = -E1000_ERR_CONFIG; 1740 goto out; 1741 } 1742 1743 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1744 1745out: 1746 return ret_val; 1747} 1748 1749/** 1750 * e1000_blink_led_generic - Blink LED 1751 * @hw: pointer to the HW structure 1752 * 1753 * Blink the LEDs which are set to be on. 1754 **/ 1755s32 e1000_blink_led_generic(struct e1000_hw *hw) 1756{ 1757 u32 ledctl_blink = 0; 1758 u32 i; 1759 1760 DEBUGFUNC("e1000_blink_led_generic"); 1761 1762 if (hw->phy.media_type == e1000_media_type_fiber) { 1763 /* always blink LED0 for PCI-E fiber */ 1764 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1765 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1766 } else { 1767 /* 1768 * set the blink bit for each LED that's "on" (0x0E) 1769 * in ledctl_mode2 1770 */ 1771 ledctl_blink = hw->mac.ledctl_mode2; 1772 for (i = 0; i < 4; i++) 1773 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1774 E1000_LEDCTL_MODE_LED_ON) 1775 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1776 (i * 8)); 1777 } 1778 1779 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1780 1781 return E1000_SUCCESS; 1782} 1783 1784/** 1785 * e1000_led_on_generic - Turn LED on 1786 * @hw: pointer to the HW structure 1787 * 1788 * Turn LED on. 1789 **/ 1790s32 e1000_led_on_generic(struct e1000_hw *hw) 1791{ 1792 u32 ctrl; 1793 1794 DEBUGFUNC("e1000_led_on_generic"); 1795 1796 switch (hw->phy.media_type) { 1797 case e1000_media_type_fiber: 1798 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1799 ctrl &= ~E1000_CTRL_SWDPIN0; 1800 ctrl |= E1000_CTRL_SWDPIO0; 1801 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1802 break; 1803 case e1000_media_type_copper: 1804 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1805 break; 1806 default: 1807 break; 1808 } 1809 1810 return E1000_SUCCESS; 1811} 1812 1813/** 1814 * e1000_led_off_generic - Turn LED off 1815 * @hw: pointer to the HW structure 1816 * 1817 * Turn LED off. 1818 **/ 1819s32 e1000_led_off_generic(struct e1000_hw *hw) 1820{ 1821 u32 ctrl; 1822 1823 DEBUGFUNC("e1000_led_off_generic"); 1824 1825 switch (hw->phy.media_type) { 1826 case e1000_media_type_fiber: 1827 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1828 ctrl |= E1000_CTRL_SWDPIN0; 1829 ctrl |= E1000_CTRL_SWDPIO0; 1830 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1831 break; 1832 case e1000_media_type_copper: 1833 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1834 break; 1835 default: 1836 break; 1837 } 1838 1839 return E1000_SUCCESS; 1840} 1841 1842/** 1843 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1844 * @hw: pointer to the HW structure 1845 * @no_snoop: bitmap of snoop events 1846 * 1847 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1848 **/ 1849void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1850{ 1851 u32 gcr; 1852 1853 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1854 1855 if (hw->bus.type != e1000_bus_type_pci_express) 1856 goto out; 1857 1858 if (no_snoop) { 1859 gcr = E1000_READ_REG(hw, E1000_GCR); 1860 gcr &= ~(PCIE_NO_SNOOP_ALL); 1861 gcr |= no_snoop; 1862 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1863 } 1864out: 1865 return; 1866} 1867 1868/** 1869 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1870 * @hw: pointer to the HW structure 1871 * 1872 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1873 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1874 * the master requests to be disabled. 1875 * 1876 * Disables PCI-Express master access and verifies there are no pending 1877 * requests. 1878 **/ 1879s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1880{ 1881 u32 ctrl; 1882 s32 timeout = MASTER_DISABLE_TIMEOUT; 1883 s32 ret_val = E1000_SUCCESS; 1884 1885 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1886 1887 if (hw->bus.type != e1000_bus_type_pci_express) 1888 goto out; 1889 1890 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1891 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1892 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1893 1894 while (timeout) { 1895 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1896 E1000_STATUS_GIO_MASTER_ENABLE)) 1897 break; 1898 usec_delay(100); 1899 timeout--; 1900 } 1901 1902 if (!timeout) { 1903 DEBUGOUT("Master requests are pending.\n"); 1904 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1905 goto out; 1906 } 1907 1908out: 1909 return ret_val; 1910} 1911 1912/** 1913 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1914 * @hw: pointer to the HW structure 1915 * 1916 * Reset the Adaptive Interframe Spacing throttle to default values. 1917 **/ 1918void e1000_reset_adaptive_generic(struct e1000_hw *hw) 1919{ 1920 struct e1000_mac_info *mac = &hw->mac; 1921 1922 DEBUGFUNC("e1000_reset_adaptive_generic"); 1923 1924 if (!mac->adaptive_ifs) { 1925 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1926 goto out; 1927 } 1928 1929 if (!mac->ifs_params_forced) { 1930 mac->current_ifs_val = 0; 1931 mac->ifs_min_val = IFS_MIN; 1932 mac->ifs_max_val = IFS_MAX; 1933 mac->ifs_step_size = IFS_STEP; 1934 mac->ifs_ratio = IFS_RATIO; 1935 } 1936 1937 mac->in_ifs_mode = FALSE; 1938 E1000_WRITE_REG(hw, E1000_AIT, 0); 1939out: 1940 return; 1941} 1942 1943/** 1944 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 1945 * @hw: pointer to the HW structure 1946 * 1947 * Update the Adaptive Interframe Spacing Throttle value based on the 1948 * time between transmitted packets and time between collisions. 1949 **/ 1950void e1000_update_adaptive_generic(struct e1000_hw *hw) 1951{ 1952 struct e1000_mac_info *mac = &hw->mac; 1953 1954 DEBUGFUNC("e1000_update_adaptive_generic"); 1955 1956 if (!mac->adaptive_ifs) { 1957 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1958 goto out; 1959 } 1960 1961 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1962 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1963 mac->in_ifs_mode = TRUE; 1964 if (mac->current_ifs_val < mac->ifs_max_val) { 1965 if (!mac->current_ifs_val) 1966 mac->current_ifs_val = mac->ifs_min_val; 1967 else 1968 mac->current_ifs_val += 1969 mac->ifs_step_size; 1970 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 1971 } 1972 } 1973 } else { 1974 if (mac->in_ifs_mode && 1975 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1976 mac->current_ifs_val = 0; 1977 mac->in_ifs_mode = FALSE; 1978 E1000_WRITE_REG(hw, E1000_AIT, 0); 1979 } 1980 } 1981out: 1982 return; 1983} 1984 1985/** 1986 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 1987 * @hw: pointer to the HW structure 1988 * 1989 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 1990 * set, which is forced to MDI mode only. 1991 **/ 1992s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 1993{ 1994 s32 ret_val = E1000_SUCCESS; 1995 1996 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 1997 1998 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1999 DEBUGOUT("Invalid MDI setting detected\n"); 2000 hw->phy.mdix = 1; 2001 ret_val = -E1000_ERR_CONFIG; 2002 goto out; 2003 } 2004 2005out: 2006 return ret_val; 2007} 2008 2009/** 2010 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2011 * @hw: pointer to the HW structure 2012 * @reg: 32bit register offset such as E1000_SCTL 2013 * @offset: register offset to write to 2014 * @data: data to write at register offset 2015 * 2016 * Writes an address/data control type register. There are several of these 2017 * and they all have the format address << 8 | data and bit 31 is polled for 2018 * completion. 2019 **/ 2020s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2021 u32 offset, u8 data) 2022{ 2023 u32 i, regvalue = 0; 2024 s32 ret_val = E1000_SUCCESS; 2025 2026 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2027 2028 /* Set up the address and data */ 2029 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2030 E1000_WRITE_REG(hw, reg, regvalue); 2031 2032 /* Poll the ready bit to see if the MDI read completed */ 2033 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2034 usec_delay(5); 2035 regvalue = E1000_READ_REG(hw, reg); 2036 if (regvalue & E1000_GEN_CTL_READY) 2037 break; 2038 } 2039 if (!(regvalue & E1000_GEN_CTL_READY)) { 2040 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2041 ret_val = -E1000_ERR_PHY; 2042 goto out; 2043 } 2044 2045out: 2046 return ret_val; 2047} 2048