e1000_mac.c revision 173788
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_mac.c 173788 2007-11-20 21:41:22Z jfv $ */ 34 35 36#include "e1000_api.h" 37#include "e1000_mac.h" 38 39/** 40 * e1000_remove_device_generic - Free device specific structure 41 * @hw: pointer to the HW structure 42 * 43 * If a device specific structure was allocated, this function will 44 * free it. 45 **/ 46void e1000_remove_device_generic(struct e1000_hw *hw) 47{ 48 DEBUGFUNC("e1000_remove_device_generic"); 49 50 /* Freeing the dev_spec member of e1000_hw structure */ 51 e1000_free_dev_spec_struct(hw); 52} 53 54/** 55 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 56 * @hw: pointer to the HW structure 57 * 58 * Determines and stores the system bus information for a particular 59 * network interface. The following bus information is determined and stored: 60 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 61 **/ 62s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 63{ 64 struct e1000_bus_info *bus = &hw->bus; 65 u32 status = E1000_READ_REG(hw, E1000_STATUS); 66 s32 ret_val = E1000_SUCCESS; 67 u16 pci_header_type; 68 69 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 70 71 /* PCI or PCI-X? */ 72 bus->type = (status & E1000_STATUS_PCIX_MODE) 73 ? e1000_bus_type_pcix 74 : e1000_bus_type_pci; 75 76 /* Bus speed */ 77 if (bus->type == e1000_bus_type_pci) { 78 bus->speed = (status & E1000_STATUS_PCI66) 79 ? e1000_bus_speed_66 80 : e1000_bus_speed_33; 81 } else { 82 switch (status & E1000_STATUS_PCIX_SPEED) { 83 case E1000_STATUS_PCIX_SPEED_66: 84 bus->speed = e1000_bus_speed_66; 85 break; 86 case E1000_STATUS_PCIX_SPEED_100: 87 bus->speed = e1000_bus_speed_100; 88 break; 89 case E1000_STATUS_PCIX_SPEED_133: 90 bus->speed = e1000_bus_speed_133; 91 break; 92 default: 93 bus->speed = e1000_bus_speed_reserved; 94 break; 95 } 96 } 97 98 /* Bus width */ 99 bus->width = (status & E1000_STATUS_BUS64) 100 ? e1000_bus_width_64 101 : e1000_bus_width_32; 102 103 /* Which PCI(-X) function? */ 104 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 105 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 106 bus->func = (status & E1000_STATUS_FUNC_MASK) 107 >> E1000_STATUS_FUNC_SHIFT; 108 else 109 bus->func = 0; 110 111 return ret_val; 112} 113 114/** 115 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 116 * @hw: pointer to the HW structure 117 * 118 * Determines and stores the system bus information for a particular 119 * network interface. The following bus information is determined and stored: 120 * bus speed, bus width, type (PCIe), and PCIe function. 121 **/ 122s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 123{ 124 struct e1000_bus_info *bus = &hw->bus; 125 s32 ret_val; 126 u32 status; 127 u16 pcie_link_status, pci_header_type; 128 129 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 130 131 bus->type = e1000_bus_type_pci_express; 132 bus->speed = e1000_bus_speed_2500; 133 134 ret_val = e1000_read_pcie_cap_reg(hw, 135 PCIE_LINK_STATUS, 136 &pcie_link_status); 137 if (ret_val) 138 bus->width = e1000_bus_width_unknown; 139 else 140 bus->width = (e1000_bus_width)((pcie_link_status & 141 PCIE_LINK_WIDTH_MASK) >> 142 PCIE_LINK_WIDTH_SHIFT); 143 144 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 145 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 146 status = E1000_READ_REG(hw, E1000_STATUS); 147 bus->func = (status & E1000_STATUS_FUNC_MASK) 148 >> E1000_STATUS_FUNC_SHIFT; 149 } else { 150 bus->func = 0; 151 } 152 153 return E1000_SUCCESS; 154} 155 156/** 157 * e1000_clear_vfta_generic - Clear VLAN filter table 158 * @hw: pointer to the HW structure 159 * 160 * Clears the register array which contains the VLAN filter table by 161 * setting all the values to 0. 162 **/ 163void e1000_clear_vfta_generic(struct e1000_hw *hw) 164{ 165 u32 offset; 166 167 DEBUGFUNC("e1000_clear_vfta_generic"); 168 169 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 170 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 171 E1000_WRITE_FLUSH(hw); 172 } 173} 174 175/** 176 * e1000_write_vfta_generic - Write value to VLAN filter table 177 * @hw: pointer to the HW structure 178 * @offset: register offset in VLAN filter table 179 * @value: register value written to VLAN filter table 180 * 181 * Writes value at the given offset in the register array which stores 182 * the VLAN filter table. 183 **/ 184void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 185{ 186 DEBUGFUNC("e1000_write_vfta_generic"); 187 188 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 189 E1000_WRITE_FLUSH(hw); 190} 191 192/** 193 * e1000_init_rx_addrs_generic - Initialize receive address's 194 * @hw: pointer to the HW structure 195 * @rar_count: receive address registers 196 * 197 * Setups the receive address registers by setting the base receive address 198 * register to the devices MAC address and clearing all the other receive 199 * address registers to 0. 200 **/ 201void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 202{ 203 u32 i; 204 205 DEBUGFUNC("e1000_init_rx_addrs_generic"); 206 207 /* Setup the receive address */ 208 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 209 210 e1000_rar_set_generic(hw, hw->mac.addr, 0); 211 212 /* Zero out the other (rar_entry_count - 1) receive addresses */ 213 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 214 for (i = 1; i < rar_count; i++) { 215 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 216 E1000_WRITE_FLUSH(hw); 217 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 218 E1000_WRITE_FLUSH(hw); 219 } 220} 221 222/** 223 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 224 * @hw: pointer to the HW structure 225 * 226 * Checks the nvm for an alternate MAC address. An alternate MAC address 227 * can be setup by pre-boot software and must be treated like a permanent 228 * address and must override the actual permanent MAC address. If an 229 * alternate MAC address is found it is saved in the hw struct and 230 * programmed into RAR0 and the function returns success, otherwise the 231 * function returns an error. 232 **/ 233s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 234{ 235 u32 i; 236 s32 ret_val = E1000_SUCCESS; 237 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 238 u8 alt_mac_addr[ETH_ADDR_LEN]; 239 240 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 241 242 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, &nvm_alt_mac_addr_offset); 243 if (ret_val) { 244 DEBUGOUT("NVM Read Error\n"); 245 goto out; 246 } 247 248 if (nvm_alt_mac_addr_offset == 0xFFFF) { 249 ret_val = -(E1000_NOT_IMPLEMENTED); 250 goto out; 251 } 252 253 if (hw->bus.func == E1000_FUNC_1) 254 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16); 255 256 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 257 offset = nvm_alt_mac_addr_offset + (i >> 1); 258 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 259 if (ret_val) { 260 DEBUGOUT("NVM Read Error\n"); 261 goto out; 262 } 263 264 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 265 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 266 } 267 268 /* if multicast bit is set, the alternate address will not be used */ 269 if (alt_mac_addr[0] & 0x01) { 270 ret_val = -(E1000_NOT_IMPLEMENTED); 271 goto out; 272 } 273 274 for (i = 0; i < ETH_ADDR_LEN; i++) 275 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 276 277 e1000_rar_set(hw, hw->mac.perm_addr, 0); 278 279out: 280 return ret_val; 281} 282 283/** 284 * e1000_rar_set_generic - Set receive address register 285 * @hw: pointer to the HW structure 286 * @addr: pointer to the receive address 287 * @index: receive address array register 288 * 289 * Sets the receive address array register at index to the address passed 290 * in by addr. 291 **/ 292void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 293{ 294 u32 rar_low, rar_high; 295 296 DEBUGFUNC("e1000_rar_set_generic"); 297 298 /* 299 * HW expects these in little endian so we reverse the byte order 300 * from network order (big endian) to little endian 301 */ 302 rar_low = ((u32) addr[0] | 303 ((u32) addr[1] << 8) | 304 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 305 306 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 307 308 /* If MAC address zero, no need to set the AV bit */ 309 if (rar_low || rar_high) { 310 if (!hw->mac.disable_av) 311 rar_high |= E1000_RAH_AV; 312 } 313 314 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 315 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 316} 317 318/** 319 * e1000_mta_set_generic - Set multicast filter table address 320 * @hw: pointer to the HW structure 321 * @hash_value: determines the MTA register and bit to set 322 * 323 * The multicast table address is a register array of 32-bit registers. 324 * The hash_value is used to determine what register the bit is in, the 325 * current value is read, the new bit is OR'd in and the new value is 326 * written back into the register. 327 **/ 328void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 329{ 330 u32 hash_bit, hash_reg, mta; 331 332 DEBUGFUNC("e1000_mta_set_generic"); 333 /* 334 * The MTA is a register array of 32-bit registers. It is 335 * treated like an array of (32*mta_reg_count) bits. We want to 336 * set bit BitArray[hash_value]. So we figure out what register 337 * the bit is in, read it, OR in the new bit, then write 338 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 339 * mask to bits 31:5 of the hash value which gives us the 340 * register we're modifying. The hash bit within that register 341 * is determined by the lower 5 bits of the hash value. 342 */ 343 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 344 hash_bit = hash_value & 0x1F; 345 346 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 347 348 mta |= (1 << hash_bit); 349 350 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 351 E1000_WRITE_FLUSH(hw); 352} 353 354/** 355 * e1000_update_mc_addr_list_generic - Update Multicast addresses 356 * @hw: pointer to the HW structure 357 * @mc_addr_list: array of multicast addresses to program 358 * @mc_addr_count: number of multicast addresses to program 359 * @rar_used_count: the first RAR register free to program 360 * @rar_count: total number of supported Receive Address Registers 361 * 362 * Updates the Receive Address Registers and Multicast Table Array. 363 * The caller must have a packed mc_addr_list of multicast addresses. 364 * The parameter rar_count will usually be hw->mac.rar_entry_count 365 * unless there are workarounds that change this. 366 **/ 367void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 368 u8 *mc_addr_list, u32 mc_addr_count, 369 u32 rar_used_count, u32 rar_count) 370{ 371 u32 hash_value; 372 u32 i; 373 374 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 375 376 /* 377 * Load the first set of multicast addresses into the exact 378 * filters (RAR). If there are not enough to fill the RAR 379 * array, clear the filters. 380 */ 381 for (i = rar_used_count; i < rar_count; i++) { 382 if (mc_addr_count) { 383 e1000_rar_set(hw, mc_addr_list, i); 384 mc_addr_count--; 385 mc_addr_list += ETH_ADDR_LEN; 386 } else { 387 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 388 E1000_WRITE_FLUSH(hw); 389 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 390 E1000_WRITE_FLUSH(hw); 391 } 392 } 393 394 /* Clear the old settings from the MTA */ 395 DEBUGOUT("Clearing MTA\n"); 396 for (i = 0; i < hw->mac.mta_reg_count; i++) { 397 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 398 E1000_WRITE_FLUSH(hw); 399 } 400 401 /* Load any remaining multicast addresses into the hash table. */ 402 for (; mc_addr_count > 0; mc_addr_count--) { 403 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 404 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 405 e1000_mta_set(hw, hash_value); 406 mc_addr_list += ETH_ADDR_LEN; 407 } 408} 409 410/** 411 * e1000_hash_mc_addr_generic - Generate a multicast hash value 412 * @hw: pointer to the HW structure 413 * @mc_addr: pointer to a multicast address 414 * 415 * Generates a multicast address hash value which is used to determine 416 * the multicast filter table array address and new table value. See 417 * e1000_mta_set_generic() 418 **/ 419u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 420{ 421 u32 hash_value, hash_mask; 422 u8 bit_shift = 0; 423 424 DEBUGFUNC("e1000_hash_mc_addr_generic"); 425 426 /* Register count multiplied by bits per register */ 427 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 428 429 /* 430 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 431 * where 0xFF would still fall within the hash mask. 432 */ 433 while (hash_mask >> bit_shift != 0xFF) 434 bit_shift++; 435 436 /* 437 * The portion of the address that is used for the hash table 438 * is determined by the mc_filter_type setting. 439 * The algorithm is such that there is a total of 8 bits of shifting. 440 * The bit_shift for a mc_filter_type of 0 represents the number of 441 * left-shifts where the MSB of mc_addr[5] would still fall within 442 * the hash_mask. Case 0 does this exactly. Since there are a total 443 * of 8 bits of shifting, then mc_addr[4] will shift right the 444 * remaining number of bits. Thus 8 - bit_shift. The rest of the 445 * cases are a variation of this algorithm...essentially raising the 446 * number of bits to shift mc_addr[5] left, while still keeping the 447 * 8-bit shifting total. 448 * 449 * For example, given the following Destination MAC Address and an 450 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 451 * we can see that the bit_shift for case 0 is 4. These are the hash 452 * values resulting from each mc_filter_type... 453 * [0] [1] [2] [3] [4] [5] 454 * 01 AA 00 12 34 56 455 * LSB MSB 456 * 457 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 458 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 459 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 460 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 461 */ 462 switch (hw->mac.mc_filter_type) { 463 default: 464 case 0: 465 break; 466 case 1: 467 bit_shift += 1; 468 break; 469 case 2: 470 bit_shift += 2; 471 break; 472 case 3: 473 bit_shift += 4; 474 break; 475 } 476 477 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 478 (((u16) mc_addr[5]) << bit_shift))); 479 480 return hash_value; 481} 482 483/** 484 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 485 * @hw: pointer to the HW structure 486 * 487 * In certain situations, a system BIOS may report that the PCIx maximum 488 * memory read byte count (MMRBC) value is higher than than the actual 489 * value. We check the PCIx command regsiter with the current PCIx status 490 * regsiter. 491 **/ 492void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 493{ 494 u16 cmd_mmrbc; 495 u16 pcix_cmd; 496 u16 pcix_stat_hi_word; 497 u16 stat_mmrbc; 498 499 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 500 501 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 502 if (hw->bus.type != e1000_bus_type_pcix) 503 return; 504 505 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 506 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 507 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 508 PCIX_COMMAND_MMRBC_SHIFT; 509 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 510 PCIX_STATUS_HI_MMRBC_SHIFT; 511 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 512 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 513 if (cmd_mmrbc > stat_mmrbc) { 514 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 515 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 516 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 517 } 518} 519 520/** 521 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 522 * @hw: pointer to the HW structure 523 * 524 * Clears the base hardware counters by reading the counter registers. 525 **/ 526void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 527{ 528 volatile u32 temp; 529 530 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 531 532 temp = E1000_READ_REG(hw, E1000_CRCERRS); 533 temp = E1000_READ_REG(hw, E1000_SYMERRS); 534 temp = E1000_READ_REG(hw, E1000_MPC); 535 temp = E1000_READ_REG(hw, E1000_SCC); 536 temp = E1000_READ_REG(hw, E1000_ECOL); 537 temp = E1000_READ_REG(hw, E1000_MCC); 538 temp = E1000_READ_REG(hw, E1000_LATECOL); 539 temp = E1000_READ_REG(hw, E1000_COLC); 540 temp = E1000_READ_REG(hw, E1000_DC); 541 temp = E1000_READ_REG(hw, E1000_SEC); 542 temp = E1000_READ_REG(hw, E1000_RLEC); 543 temp = E1000_READ_REG(hw, E1000_XONRXC); 544 temp = E1000_READ_REG(hw, E1000_XONTXC); 545 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 546 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 547 temp = E1000_READ_REG(hw, E1000_FCRUC); 548 temp = E1000_READ_REG(hw, E1000_GPRC); 549 temp = E1000_READ_REG(hw, E1000_BPRC); 550 temp = E1000_READ_REG(hw, E1000_MPRC); 551 temp = E1000_READ_REG(hw, E1000_GPTC); 552 temp = E1000_READ_REG(hw, E1000_GORCL); 553 temp = E1000_READ_REG(hw, E1000_GORCH); 554 temp = E1000_READ_REG(hw, E1000_GOTCL); 555 temp = E1000_READ_REG(hw, E1000_GOTCH); 556 temp = E1000_READ_REG(hw, E1000_RNBC); 557 temp = E1000_READ_REG(hw, E1000_RUC); 558 temp = E1000_READ_REG(hw, E1000_RFC); 559 temp = E1000_READ_REG(hw, E1000_ROC); 560 temp = E1000_READ_REG(hw, E1000_RJC); 561 temp = E1000_READ_REG(hw, E1000_TORL); 562 temp = E1000_READ_REG(hw, E1000_TORH); 563 temp = E1000_READ_REG(hw, E1000_TOTL); 564 temp = E1000_READ_REG(hw, E1000_TOTH); 565 temp = E1000_READ_REG(hw, E1000_TPR); 566 temp = E1000_READ_REG(hw, E1000_TPT); 567 temp = E1000_READ_REG(hw, E1000_MPTC); 568 temp = E1000_READ_REG(hw, E1000_BPTC); 569} 570 571/** 572 * e1000_check_for_copper_link_generic - Check for link (Copper) 573 * @hw: pointer to the HW structure 574 * 575 * Checks to see of the link status of the hardware has changed. If a 576 * change in link status has been detected, then we read the PHY registers 577 * to get the current speed/duplex if link exists. 578 **/ 579s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 580{ 581 struct e1000_mac_info *mac = &hw->mac; 582 s32 ret_val; 583 bool link; 584 585 DEBUGFUNC("e1000_check_for_copper_link"); 586 587 /* 588 * We only want to go out to the PHY registers to see if Auto-Neg 589 * has completed and/or if our link status has changed. The 590 * get_link_status flag is set upon receiving a Link Status 591 * Change or Rx Sequence Error interrupt. 592 */ 593 if (!mac->get_link_status) { 594 ret_val = E1000_SUCCESS; 595 goto out; 596 } 597 598 /* 599 * First we want to see if the MII Status Register reports 600 * link. If so, then we want to get the current speed/duplex 601 * of the PHY. 602 */ 603 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 604 if (ret_val) 605 goto out; 606 607 if (!link) 608 goto out; /* No link detected */ 609 610 mac->get_link_status = FALSE; 611 612 /* 613 * Check if there was DownShift, must be checked 614 * immediately after link-up 615 */ 616 e1000_check_downshift_generic(hw); 617 618 /* 619 * If we are forcing speed/duplex, then we simply return since 620 * we have already determined whether we have link or not. 621 */ 622 if (!mac->autoneg) { 623 ret_val = -E1000_ERR_CONFIG; 624 goto out; 625 } 626 627 /* 628 * Auto-Neg is enabled. Auto Speed Detection takes care 629 * of MAC speed/duplex configuration. So we only need to 630 * configure Collision Distance in the MAC. 631 */ 632 e1000_config_collision_dist_generic(hw); 633 634 /* 635 * Configure Flow Control now that Auto-Neg has completed. 636 * First, we need to restore the desired flow control 637 * settings because we may have had to re-autoneg with a 638 * different link partner. 639 */ 640 ret_val = e1000_config_fc_after_link_up_generic(hw); 641 if (ret_val) { 642 DEBUGOUT("Error configuring flow control\n"); 643 } 644 645out: 646 return ret_val; 647} 648 649/** 650 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 651 * @hw: pointer to the HW structure 652 * 653 * Checks for link up on the hardware. If link is not up and we have 654 * a signal, then we need to force link up. 655 **/ 656s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 657{ 658 struct e1000_mac_info *mac = &hw->mac; 659 u32 rxcw; 660 u32 ctrl; 661 u32 status; 662 s32 ret_val = E1000_SUCCESS; 663 664 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 665 666 ctrl = E1000_READ_REG(hw, E1000_CTRL); 667 status = E1000_READ_REG(hw, E1000_STATUS); 668 rxcw = E1000_READ_REG(hw, E1000_RXCW); 669 670 /* 671 * If we don't have link (auto-negotiation failed or link partner 672 * cannot auto-negotiate), the cable is plugged in (we have signal), 673 * and our link partner is not trying to auto-negotiate with us (we 674 * are receiving idles or data), we need to force link up. We also 675 * need to give auto-negotiation time to complete, in case the cable 676 * was just plugged in. The autoneg_failed flag does this. 677 */ 678 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 679 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 680 (!(rxcw & E1000_RXCW_C))) { 681 if (mac->autoneg_failed == 0) { 682 mac->autoneg_failed = 1; 683 goto out; 684 } 685 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 686 687 /* Disable auto-negotiation in the TXCW register */ 688 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 689 690 /* Force link-up and also force full-duplex. */ 691 ctrl = E1000_READ_REG(hw, E1000_CTRL); 692 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 693 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 694 695 /* Configure Flow Control after forcing link up. */ 696 ret_val = e1000_config_fc_after_link_up_generic(hw); 697 if (ret_val) { 698 DEBUGOUT("Error configuring flow control\n"); 699 goto out; 700 } 701 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 702 /* 703 * If we are forcing link and we are receiving /C/ ordered 704 * sets, re-enable auto-negotiation in the TXCW register 705 * and disable forced link in the Device Control register 706 * in an attempt to auto-negotiate with our link partner. 707 */ 708 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 709 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 710 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 711 712 mac->serdes_has_link = TRUE; 713 } 714 715out: 716 return ret_val; 717} 718 719/** 720 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 721 * @hw: pointer to the HW structure 722 * 723 * Checks for link up on the hardware. If link is not up and we have 724 * a signal, then we need to force link up. 725 **/ 726s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 727{ 728 struct e1000_mac_info *mac = &hw->mac; 729 u32 rxcw; 730 u32 ctrl; 731 u32 status; 732 s32 ret_val = E1000_SUCCESS; 733 734 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 735 736 ctrl = E1000_READ_REG(hw, E1000_CTRL); 737 status = E1000_READ_REG(hw, E1000_STATUS); 738 rxcw = E1000_READ_REG(hw, E1000_RXCW); 739 740 /* 741 * If we don't have link (auto-negotiation failed or link partner 742 * cannot auto-negotiate), and our link partner is not trying to 743 * auto-negotiate with us (we are receiving idles or data), 744 * we need to force link up. We also need to give auto-negotiation 745 * time to complete. 746 */ 747 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 748 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 749 if (mac->autoneg_failed == 0) { 750 mac->autoneg_failed = 1; 751 goto out; 752 } 753 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 754 755 /* Disable auto-negotiation in the TXCW register */ 756 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 757 758 /* Force link-up and also force full-duplex. */ 759 ctrl = E1000_READ_REG(hw, E1000_CTRL); 760 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 761 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 762 763 /* Configure Flow Control after forcing link up. */ 764 ret_val = e1000_config_fc_after_link_up_generic(hw); 765 if (ret_val) { 766 DEBUGOUT("Error configuring flow control\n"); 767 goto out; 768 } 769 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 770 /* 771 * If we are forcing link and we are receiving /C/ ordered 772 * sets, re-enable auto-negotiation in the TXCW register 773 * and disable forced link in the Device Control register 774 * in an attempt to auto-negotiate with our link partner. 775 */ 776 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 777 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 778 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 779 780 mac->serdes_has_link = TRUE; 781 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 782 /* 783 * If we force link for non-auto-negotiation switch, check 784 * link status based on MAC synchronization for internal 785 * serdes media type. 786 */ 787 /* SYNCH bit and IV bit are sticky. */ 788 usec_delay(10); 789 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 790 if (!(rxcw & E1000_RXCW_IV)) { 791 mac->serdes_has_link = TRUE; 792 DEBUGOUT("SERDES: Link is up.\n"); 793 } 794 } else { 795 mac->serdes_has_link = FALSE; 796 DEBUGOUT("SERDES: Link is down.\n"); 797 } 798 } 799 800 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 801 status = E1000_READ_REG(hw, E1000_STATUS); 802 mac->serdes_has_link = (status & E1000_STATUS_LU) 803 ? TRUE 804 : FALSE; 805 } 806 807out: 808 return ret_val; 809} 810 811/** 812 * e1000_setup_link_generic - Setup flow control and link settings 813 * @hw: pointer to the HW structure 814 * 815 * Determines which flow control settings to use, then configures flow 816 * control. Calls the appropriate media-specific link configuration 817 * function. Assuming the adapter has a valid link partner, a valid link 818 * should be established. Assumes the hardware has previously been reset 819 * and the transmitter and receiver are not enabled. 820 **/ 821s32 e1000_setup_link_generic(struct e1000_hw *hw) 822{ 823 struct e1000_functions *func = &hw->func; 824 s32 ret_val = E1000_SUCCESS; 825 826 DEBUGFUNC("e1000_setup_link_generic"); 827 828 /* 829 * In the case of the phy reset being blocked, we already have a link. 830 * We do not need to set it up again. 831 */ 832 if (e1000_check_reset_block(hw)) 833 goto out; 834 835 /* 836 * If flow control is set to default, set flow control based on 837 * the EEPROM flow control settings. 838 */ 839 if (hw->fc.type == e1000_fc_default) { 840 ret_val = e1000_set_default_fc_generic(hw); 841 if (ret_val) 842 goto out; 843 } 844 845 /* 846 * We want to save off the original Flow Control configuration just 847 * in case we get disconnected and then reconnected into a different 848 * hub or switch with different Flow Control capabilities. 849 */ 850 hw->fc.original_type = hw->fc.type; 851 852 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 853 854 /* Call the necessary media_type subroutine to configure the link. */ 855 ret_val = func->setup_physical_interface(hw); 856 if (ret_val) 857 goto out; 858 859 /* 860 * Initialize the flow control address, type, and PAUSE timer 861 * registers to their default values. This is done even if flow 862 * control is disabled, because it does not hurt anything to 863 * initialize these registers. 864 */ 865 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 866 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 867 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 868 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 869 870 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 871 872 ret_val = e1000_set_fc_watermarks_generic(hw); 873 874out: 875 return ret_val; 876} 877 878/** 879 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 880 * @hw: pointer to the HW structure 881 * 882 * Configures collision distance and flow control for fiber and serdes 883 * links. Upon successful setup, poll for link. 884 **/ 885s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 886{ 887 u32 ctrl; 888 s32 ret_val = E1000_SUCCESS; 889 890 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 891 892 ctrl = E1000_READ_REG(hw, E1000_CTRL); 893 894 /* Take the link out of reset */ 895 ctrl &= ~E1000_CTRL_LRST; 896 897 e1000_config_collision_dist_generic(hw); 898 899 ret_val = e1000_commit_fc_settings_generic(hw); 900 if (ret_val) 901 goto out; 902 903 /* 904 * Since auto-negotiation is enabled, take the link out of reset (the 905 * link will be in reset, because we previously reset the chip). This 906 * will restart auto-negotiation. If auto-negotiation is successful 907 * then the link-up status bit will be set and the flow control enable 908 * bits (RFCE and TFCE) will be set according to their negotiated value. 909 */ 910 DEBUGOUT("Auto-negotiation enabled\n"); 911 912 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 913 E1000_WRITE_FLUSH(hw); 914 msec_delay(1); 915 916 /* 917 * For these adapters, the SW defineable pin 1 is set when the optics 918 * detect a signal. If we have a signal, then poll for a "Link-Up" 919 * indication. 920 */ 921 if (hw->phy.media_type == e1000_media_type_internal_serdes || 922 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 923 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 924 } else { 925 DEBUGOUT("No signal detected\n"); 926 } 927 928out: 929 return ret_val; 930} 931 932/** 933 * e1000_config_collision_dist_generic - Configure collision distance 934 * @hw: pointer to the HW structure 935 * 936 * Configures the collision distance to the default value and is used 937 * during link setup. Currently no func pointer exists and all 938 * implementations are handled in the generic version of this function. 939 **/ 940void e1000_config_collision_dist_generic(struct e1000_hw *hw) 941{ 942 u32 tctl; 943 944 DEBUGFUNC("e1000_config_collision_dist_generic"); 945 946 tctl = E1000_READ_REG(hw, E1000_TCTL); 947 948 tctl &= ~E1000_TCTL_COLD; 949 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 950 951 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 952 E1000_WRITE_FLUSH(hw); 953} 954 955/** 956 * e1000_poll_fiber_serdes_link_generic - Poll for link up 957 * @hw: pointer to the HW structure 958 * 959 * Polls for link up by reading the status register, if link fails to come 960 * up with auto-negotiation, then the link is forced if a signal is detected. 961 **/ 962s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 963{ 964 struct e1000_mac_info *mac = &hw->mac; 965 u32 i, status; 966 s32 ret_val = E1000_SUCCESS; 967 968 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 969 970 /* 971 * If we have a signal (the cable is plugged in, or assumed true for 972 * serdes media) then poll for a "Link-Up" indication in the Device 973 * Status Register. Time-out if a link isn't seen in 500 milliseconds 974 * seconds (Auto-negotiation should complete in less than 500 975 * milliseconds even if the other end is doing it in SW). 976 */ 977 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 978 msec_delay(10); 979 status = E1000_READ_REG(hw, E1000_STATUS); 980 if (status & E1000_STATUS_LU) 981 break; 982 } 983 if (i == FIBER_LINK_UP_LIMIT) { 984 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 985 mac->autoneg_failed = 1; 986 /* 987 * AutoNeg failed to achieve a link, so we'll call 988 * mac->check_for_link. This routine will force the 989 * link up if we detect a signal. This will allow us to 990 * communicate with non-autonegotiating link partners. 991 */ 992 ret_val = e1000_check_for_link(hw); 993 if (ret_val) { 994 DEBUGOUT("Error while checking for link\n"); 995 goto out; 996 } 997 mac->autoneg_failed = 0; 998 } else { 999 mac->autoneg_failed = 0; 1000 DEBUGOUT("Valid Link Found\n"); 1001 } 1002 1003out: 1004 return ret_val; 1005} 1006 1007/** 1008 * e1000_commit_fc_settings_generic - Configure flow control 1009 * @hw: pointer to the HW structure 1010 * 1011 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1012 * base on the flow control settings in e1000_mac_info. 1013 **/ 1014s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1015{ 1016 struct e1000_mac_info *mac = &hw->mac; 1017 u32 txcw; 1018 s32 ret_val = E1000_SUCCESS; 1019 1020 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1021 1022 /* 1023 * Check for a software override of the flow control settings, and 1024 * setup the device accordingly. If auto-negotiation is enabled, then 1025 * software will have to set the "PAUSE" bits to the correct value in 1026 * the Transmit Config Word Register (TXCW) and re-start auto- 1027 * negotiation. However, if auto-negotiation is disabled, then 1028 * software will have to manually configure the two flow control enable 1029 * bits in the CTRL register. 1030 * 1031 * The possible values of the "fc" parameter are: 1032 * 0: Flow control is completely disabled 1033 * 1: Rx flow control is enabled (we can receive pause frames, 1034 * but not send pause frames). 1035 * 2: Tx flow control is enabled (we can send pause frames but we 1036 * do not support receiving pause frames). 1037 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1038 */ 1039 switch (hw->fc.type) { 1040 case e1000_fc_none: 1041 /* Flow control completely disabled by a software over-ride. */ 1042 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1043 break; 1044 case e1000_fc_rx_pause: 1045 /* 1046 * Rx Flow control is enabled and Tx Flow control is disabled 1047 * by a software over-ride. Since there really isn't a way to 1048 * advertise that we are capable of Rx Pause ONLY, we will 1049 * advertise that we support both symmetric and asymmetric RX 1050 * PAUSE. Later, we will disable the adapter's ability to send 1051 * PAUSE frames. 1052 */ 1053 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1054 break; 1055 case e1000_fc_tx_pause: 1056 /* 1057 * Tx Flow control is enabled, and Rx Flow control is disabled, 1058 * by a software over-ride. 1059 */ 1060 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1061 break; 1062 case e1000_fc_full: 1063 /* 1064 * Flow control (both Rx and Tx) is enabled by a software 1065 * over-ride. 1066 */ 1067 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1068 break; 1069 default: 1070 DEBUGOUT("Flow control param set incorrectly\n"); 1071 ret_val = -E1000_ERR_CONFIG; 1072 goto out; 1073 break; 1074 } 1075 1076 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1077 mac->txcw = txcw; 1078 1079out: 1080 return ret_val; 1081} 1082 1083/** 1084 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1085 * @hw: pointer to the HW structure 1086 * 1087 * Sets the flow control high/low threshold (watermark) registers. If 1088 * flow control XON frame transmission is enabled, then set XON frame 1089 * tansmission as well. 1090 **/ 1091s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1092{ 1093 s32 ret_val = E1000_SUCCESS; 1094 u32 fcrtl = 0, fcrth = 0; 1095 1096 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1097 1098 /* 1099 * Set the flow control receive threshold registers. Normally, 1100 * these registers will be set to a default threshold that may be 1101 * adjusted later by the driver's runtime code. However, if the 1102 * ability to transmit pause frames is not enabled, then these 1103 * registers will be set to 0. 1104 */ 1105 if (hw->fc.type & e1000_fc_tx_pause) { 1106 /* 1107 * We need to set up the Receive Threshold high and low water 1108 * marks as well as (optionally) enabling the transmission of 1109 * XON frames. 1110 */ 1111 fcrtl = hw->fc.low_water; 1112 if (hw->fc.send_xon) 1113 fcrtl |= E1000_FCRTL_XONE; 1114 1115 fcrth = hw->fc.high_water; 1116 } 1117 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1118 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1119 1120 return ret_val; 1121} 1122 1123/** 1124 * e1000_set_default_fc_generic - Set flow control default values 1125 * @hw: pointer to the HW structure 1126 * 1127 * Read the EEPROM for the default values for flow control and store the 1128 * values. 1129 **/ 1130s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1131{ 1132 s32 ret_val = E1000_SUCCESS; 1133 u16 nvm_data; 1134 1135 DEBUGFUNC("e1000_set_default_fc_generic"); 1136 1137 /* 1138 * Read and store word 0x0F of the EEPROM. This word contains bits 1139 * that determine the hardware's default PAUSE (flow control) mode, 1140 * a bit that determines whether the HW defaults to enabling or 1141 * disabling auto-negotiation, and the direction of the 1142 * SW defined pins. If there is no SW over-ride of the flow 1143 * control setting, then the variable hw->fc will 1144 * be initialized based on a value in the EEPROM. 1145 */ 1146 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1147 1148 if (ret_val) { 1149 DEBUGOUT("NVM Read Error\n"); 1150 goto out; 1151 } 1152 1153 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1154 hw->fc.type = e1000_fc_none; 1155 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1156 NVM_WORD0F_ASM_DIR) 1157 hw->fc.type = e1000_fc_tx_pause; 1158 else 1159 hw->fc.type = e1000_fc_full; 1160 1161out: 1162 return ret_val; 1163} 1164 1165/** 1166 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1167 * @hw: pointer to the HW structure 1168 * 1169 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1170 * device control register to reflect the adapter settings. TFCE and RFCE 1171 * need to be explicitly set by software when a copper PHY is used because 1172 * autonegotiation is managed by the PHY rather than the MAC. Software must 1173 * also configure these bits when link is forced on a fiber connection. 1174 **/ 1175s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1176{ 1177 u32 ctrl; 1178 s32 ret_val = E1000_SUCCESS; 1179 1180 DEBUGFUNC("e1000_force_mac_fc_generic"); 1181 1182 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1183 1184 /* 1185 * Because we didn't get link via the internal auto-negotiation 1186 * mechanism (we either forced link or we got link via PHY 1187 * auto-neg), we have to manually enable/disable transmit an 1188 * receive flow control. 1189 * 1190 * The "Case" statement below enables/disable flow control 1191 * according to the "hw->fc.type" parameter. 1192 * 1193 * The possible values of the "fc" parameter are: 1194 * 0: Flow control is completely disabled 1195 * 1: Rx flow control is enabled (we can receive pause 1196 * frames but not send pause frames). 1197 * 2: Tx flow control is enabled (we can send pause frames 1198 * frames but we do not receive pause frames). 1199 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1200 * other: No other values should be possible at this point. 1201 */ 1202 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1203 1204 switch (hw->fc.type) { 1205 case e1000_fc_none: 1206 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1207 break; 1208 case e1000_fc_rx_pause: 1209 ctrl &= (~E1000_CTRL_TFCE); 1210 ctrl |= E1000_CTRL_RFCE; 1211 break; 1212 case e1000_fc_tx_pause: 1213 ctrl &= (~E1000_CTRL_RFCE); 1214 ctrl |= E1000_CTRL_TFCE; 1215 break; 1216 case e1000_fc_full: 1217 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1218 break; 1219 default: 1220 DEBUGOUT("Flow control param set incorrectly\n"); 1221 ret_val = -E1000_ERR_CONFIG; 1222 goto out; 1223 } 1224 1225 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1226 1227out: 1228 return ret_val; 1229} 1230 1231/** 1232 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1233 * @hw: pointer to the HW structure 1234 * 1235 * Checks the status of auto-negotiation after link up to ensure that the 1236 * speed and duplex were not forced. If the link needed to be forced, then 1237 * flow control needs to be forced also. If auto-negotiation is enabled 1238 * and did not fail, then we configure flow control based on our link 1239 * partner. 1240 **/ 1241s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1242{ 1243 struct e1000_mac_info *mac = &hw->mac; 1244 s32 ret_val = E1000_SUCCESS; 1245 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1246 u16 speed, duplex; 1247 1248 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1249 1250 /* 1251 * Check for the case where we have fiber media and auto-neg failed 1252 * so we had to force link. In this case, we need to force the 1253 * configuration of the MAC to match the "fc" parameter. 1254 */ 1255 if (mac->autoneg_failed) { 1256 if (hw->phy.media_type == e1000_media_type_fiber || 1257 hw->phy.media_type == e1000_media_type_internal_serdes) 1258 ret_val = e1000_force_mac_fc_generic(hw); 1259 } else { 1260 if (hw->phy.media_type == e1000_media_type_copper) 1261 ret_val = e1000_force_mac_fc_generic(hw); 1262 } 1263 1264 if (ret_val) { 1265 DEBUGOUT("Error forcing flow control settings\n"); 1266 goto out; 1267 } 1268 1269 /* 1270 * Check for the case where we have copper media and auto-neg is 1271 * enabled. In this case, we need to check and see if Auto-Neg 1272 * has completed, and if so, how the PHY and link partner has 1273 * flow control configured. 1274 */ 1275 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1276 /* 1277 * Read the MII Status Register and check to see if AutoNeg 1278 * has completed. We read this twice because this reg has 1279 * some "sticky" (latched) bits. 1280 */ 1281 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1282 if (ret_val) 1283 goto out; 1284 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1285 if (ret_val) 1286 goto out; 1287 1288 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1289 DEBUGOUT("Copper PHY and Auto Neg " 1290 "has not completed.\n"); 1291 goto out; 1292 } 1293 1294 /* 1295 * The AutoNeg process has completed, so we now need to 1296 * read both the Auto Negotiation Advertisement 1297 * Register (Address 4) and the Auto_Negotiation Base 1298 * Page Ability Register (Address 5) to determine how 1299 * flow control was negotiated. 1300 */ 1301 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1302 &mii_nway_adv_reg); 1303 if (ret_val) 1304 goto out; 1305 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 1306 &mii_nway_lp_ability_reg); 1307 if (ret_val) 1308 goto out; 1309 1310 /* 1311 * Two bits in the Auto Negotiation Advertisement Register 1312 * (Address 4) and two bits in the Auto Negotiation Base 1313 * Page Ability Register (Address 5) determine flow control 1314 * for both the PHY and the link partner. The following 1315 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1316 * 1999, describes these PAUSE resolution bits and how flow 1317 * control is determined based upon these settings. 1318 * NOTE: DC = Don't Care 1319 * 1320 * LOCAL DEVICE | LINK PARTNER 1321 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1322 *-------|---------|-------|---------|-------------------- 1323 * 0 | 0 | DC | DC | e1000_fc_none 1324 * 0 | 1 | 0 | DC | e1000_fc_none 1325 * 0 | 1 | 1 | 0 | e1000_fc_none 1326 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1327 * 1 | 0 | 0 | DC | e1000_fc_none 1328 * 1 | DC | 1 | DC | e1000_fc_full 1329 * 1 | 1 | 0 | 0 | e1000_fc_none 1330 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1331 * 1332 * Are both PAUSE bits set to 1? If so, this implies 1333 * Symmetric Flow Control is enabled at both ends. The 1334 * ASM_DIR bits are irrelevant per the spec. 1335 * 1336 * For Symmetric Flow Control: 1337 * 1338 * LOCAL DEVICE | LINK PARTNER 1339 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1340 *-------|---------|-------|---------|-------------------- 1341 * 1 | DC | 1 | DC | E1000_fc_full 1342 * 1343 */ 1344 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1345 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1346 /* 1347 * Now we need to check if the user selected Rx ONLY 1348 * of pause frames. In this case, we had to advertise 1349 * FULL flow control because we could not advertise RX 1350 * ONLY. Hence, we must now check to see if we need to 1351 * turn OFF the TRANSMISSION of PAUSE frames. 1352 */ 1353 if (hw->fc.original_type == e1000_fc_full) { 1354 hw->fc.type = e1000_fc_full; 1355 DEBUGOUT("Flow Control = FULL.\r\n"); 1356 } else { 1357 hw->fc.type = e1000_fc_rx_pause; 1358 DEBUGOUT("Flow Control = " 1359 "RX PAUSE frames only.\r\n"); 1360 } 1361 } 1362 /* 1363 * For receiving PAUSE frames ONLY. 1364 * 1365 * LOCAL DEVICE | LINK PARTNER 1366 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1367 *-------|---------|-------|---------|-------------------- 1368 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1369 */ 1370 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1371 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1372 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1373 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1374 hw->fc.type = e1000_fc_tx_pause; 1375 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1376 } 1377 /* 1378 * For transmitting PAUSE frames ONLY. 1379 * 1380 * LOCAL DEVICE | LINK PARTNER 1381 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1382 *-------|---------|-------|---------|-------------------- 1383 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1384 */ 1385 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1386 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1387 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1388 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1389 hw->fc.type = e1000_fc_rx_pause; 1390 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1391 } else { 1392 /* 1393 * Per the IEEE spec, at this point flow control 1394 * should be disabled. 1395 */ 1396 hw->fc.type = e1000_fc_none; 1397 DEBUGOUT("Flow Control = NONE.\r\n"); 1398 } 1399 1400 /* 1401 * Now we need to do one last check... If we auto- 1402 * negotiated to HALF DUPLEX, flow control should not be 1403 * enabled per IEEE 802.3 spec. 1404 */ 1405 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1406 if (ret_val) { 1407 DEBUGOUT("Error getting link speed and duplex\n"); 1408 goto out; 1409 } 1410 1411 if (duplex == HALF_DUPLEX) 1412 hw->fc.type = e1000_fc_none; 1413 1414 /* 1415 * Now we call a subroutine to actually force the MAC 1416 * controller to use the correct flow control settings. 1417 */ 1418 ret_val = e1000_force_mac_fc_generic(hw); 1419 if (ret_val) { 1420 DEBUGOUT("Error forcing flow control settings\n"); 1421 goto out; 1422 } 1423 } 1424 1425out: 1426 return ret_val; 1427} 1428 1429/** 1430 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex 1431 * @hw: pointer to the HW structure 1432 * @speed: stores the current speed 1433 * @duplex: stores the current duplex 1434 * 1435 * Read the status register for the current speed/duplex and store the current 1436 * speed and duplex for copper connections. 1437 **/ 1438s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1439 u16 *duplex) 1440{ 1441 u32 status; 1442 1443 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1444 1445 status = E1000_READ_REG(hw, E1000_STATUS); 1446 if (status & E1000_STATUS_SPEED_1000) { 1447 *speed = SPEED_1000; 1448 DEBUGOUT("1000 Mbs, "); 1449 } else if (status & E1000_STATUS_SPEED_100) { 1450 *speed = SPEED_100; 1451 DEBUGOUT("100 Mbs, "); 1452 } else { 1453 *speed = SPEED_10; 1454 DEBUGOUT("10 Mbs, "); 1455 } 1456 1457 if (status & E1000_STATUS_FD) { 1458 *duplex = FULL_DUPLEX; 1459 DEBUGOUT("Full Duplex\n"); 1460 } else { 1461 *duplex = HALF_DUPLEX; 1462 DEBUGOUT("Half Duplex\n"); 1463 } 1464 1465 return E1000_SUCCESS; 1466} 1467 1468/** 1469 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex 1470 * @hw: pointer to the HW structure 1471 * @speed: stores the current speed 1472 * @duplex: stores the current duplex 1473 * 1474 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1475 * for fiber/serdes links. 1476 **/ 1477s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1478 u16 *speed, u16 *duplex) 1479{ 1480 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1481 UNREFERENCED_PARAMETER(hw); 1482 1483 *speed = SPEED_1000; 1484 *duplex = FULL_DUPLEX; 1485 1486 return E1000_SUCCESS; 1487} 1488 1489/** 1490 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1491 * @hw: pointer to the HW structure 1492 * 1493 * Acquire the HW semaphore to access the PHY or NVM 1494 **/ 1495s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1496{ 1497 u32 swsm; 1498 s32 ret_val = E1000_SUCCESS; 1499 s32 timeout = hw->nvm.word_size + 1; 1500 s32 i = 0; 1501 1502 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1503 1504 /* Get the SW semaphore */ 1505 while (i < timeout) { 1506 swsm = E1000_READ_REG(hw, E1000_SWSM); 1507 if (!(swsm & E1000_SWSM_SMBI)) 1508 break; 1509 1510 usec_delay(50); 1511 i++; 1512 } 1513 1514 if (i == timeout) { 1515 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1516 ret_val = -E1000_ERR_NVM; 1517 goto out; 1518 } 1519 1520 /* Get the FW semaphore. */ 1521 for (i = 0; i < timeout; i++) { 1522 swsm = E1000_READ_REG(hw, E1000_SWSM); 1523 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1524 1525 /* Semaphore acquired if bit latched */ 1526 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1527 break; 1528 1529 usec_delay(50); 1530 } 1531 1532 if (i == timeout) { 1533 /* Release semaphores */ 1534 e1000_put_hw_semaphore_generic(hw); 1535 DEBUGOUT("Driver can't access the NVM\n"); 1536 ret_val = -E1000_ERR_NVM; 1537 goto out; 1538 } 1539 1540out: 1541 return ret_val; 1542} 1543 1544/** 1545 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1546 * @hw: pointer to the HW structure 1547 * 1548 * Release hardware semaphore used to access the PHY or NVM 1549 **/ 1550void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1551{ 1552 u32 swsm; 1553 1554 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1555 1556 swsm = E1000_READ_REG(hw, E1000_SWSM); 1557 1558 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1559 1560 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1561} 1562 1563/** 1564 * e1000_get_auto_rd_done_generic - Check for auto read completion 1565 * @hw: pointer to the HW structure 1566 * 1567 * Check EEPROM for Auto Read done bit. 1568 **/ 1569s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1570{ 1571 s32 i = 0; 1572 s32 ret_val = E1000_SUCCESS; 1573 1574 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1575 1576 while (i < AUTO_READ_DONE_TIMEOUT) { 1577 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1578 break; 1579 msec_delay(1); 1580 i++; 1581 } 1582 1583 if (i == AUTO_READ_DONE_TIMEOUT) { 1584 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1585 ret_val = -E1000_ERR_RESET; 1586 goto out; 1587 } 1588 1589out: 1590 return ret_val; 1591} 1592 1593/** 1594 * e1000_valid_led_default_generic - Verify a valid default LED config 1595 * @hw: pointer to the HW structure 1596 * @data: pointer to the NVM (EEPROM) 1597 * 1598 * Read the EEPROM for the current default LED configuration. If the 1599 * LED configuration is not valid, set to a valid LED configuration. 1600 **/ 1601s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1602{ 1603 s32 ret_val; 1604 1605 DEBUGFUNC("e1000_valid_led_default_generic"); 1606 1607 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1608 if (ret_val) { 1609 DEBUGOUT("NVM Read Error\n"); 1610 goto out; 1611 } 1612 1613 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1614 *data = ID_LED_DEFAULT; 1615 1616out: 1617 return ret_val; 1618} 1619 1620/** 1621 * e1000_id_led_init_generic - 1622 * @hw: pointer to the HW structure 1623 * 1624 **/ 1625s32 e1000_id_led_init_generic(struct e1000_hw * hw) 1626{ 1627 struct e1000_mac_info *mac = &hw->mac; 1628 s32 ret_val; 1629 const u32 ledctl_mask = 0x000000FF; 1630 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1631 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1632 u16 data, i, temp; 1633 const u16 led_mask = 0x0F; 1634 1635 DEBUGFUNC("e1000_id_led_init_generic"); 1636 1637 ret_val = hw->func.valid_led_default(hw, &data); 1638 if (ret_val) 1639 goto out; 1640 1641 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1642 mac->ledctl_mode1 = mac->ledctl_default; 1643 mac->ledctl_mode2 = mac->ledctl_default; 1644 1645 for (i = 0; i < 4; i++) { 1646 temp = (data >> (i << 2)) & led_mask; 1647 switch (temp) { 1648 case ID_LED_ON1_DEF2: 1649 case ID_LED_ON1_ON2: 1650 case ID_LED_ON1_OFF2: 1651 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1652 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1653 break; 1654 case ID_LED_OFF1_DEF2: 1655 case ID_LED_OFF1_ON2: 1656 case ID_LED_OFF1_OFF2: 1657 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1658 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1659 break; 1660 default: 1661 /* Do nothing */ 1662 break; 1663 } 1664 switch (temp) { 1665 case ID_LED_DEF1_ON2: 1666 case ID_LED_ON1_ON2: 1667 case ID_LED_OFF1_ON2: 1668 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1669 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1670 break; 1671 case ID_LED_DEF1_OFF2: 1672 case ID_LED_ON1_OFF2: 1673 case ID_LED_OFF1_OFF2: 1674 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1675 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1676 break; 1677 default: 1678 /* Do nothing */ 1679 break; 1680 } 1681 } 1682 1683out: 1684 return ret_val; 1685} 1686 1687/** 1688 * e1000_setup_led_generic - Configures SW controllable LED 1689 * @hw: pointer to the HW structure 1690 * 1691 * This prepares the SW controllable LED for use and saves the current state 1692 * of the LED so it can be later restored. 1693 **/ 1694s32 e1000_setup_led_generic(struct e1000_hw *hw) 1695{ 1696 u32 ledctl; 1697 s32 ret_val = E1000_SUCCESS; 1698 1699 DEBUGFUNC("e1000_setup_led_generic"); 1700 1701 if (hw->func.setup_led != e1000_setup_led_generic) { 1702 ret_val = -E1000_ERR_CONFIG; 1703 goto out; 1704 } 1705 1706 if (hw->phy.media_type == e1000_media_type_fiber) { 1707 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1708 hw->mac.ledctl_default = ledctl; 1709 /* Turn off LED0 */ 1710 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1711 E1000_LEDCTL_LED0_BLINK | 1712 E1000_LEDCTL_LED0_MODE_MASK); 1713 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1714 E1000_LEDCTL_LED0_MODE_SHIFT); 1715 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1716 } else if (hw->phy.media_type == e1000_media_type_copper) { 1717 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1718 } 1719 1720out: 1721 return ret_val; 1722} 1723 1724/** 1725 * e1000_cleanup_led_generic - Set LED config to default operation 1726 * @hw: pointer to the HW structure 1727 * 1728 * Remove the current LED configuration and set the LED configuration 1729 * to the default value, saved from the EEPROM. 1730 **/ 1731s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1732{ 1733 s32 ret_val = E1000_SUCCESS; 1734 1735 DEBUGFUNC("e1000_cleanup_led_generic"); 1736 1737 if (hw->func.cleanup_led != e1000_cleanup_led_generic) { 1738 ret_val = -E1000_ERR_CONFIG; 1739 goto out; 1740 } 1741 1742 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1743 1744out: 1745 return ret_val; 1746} 1747 1748/** 1749 * e1000_blink_led_generic - Blink LED 1750 * @hw: pointer to the HW structure 1751 * 1752 * Blink the led's which are set to be on. 1753 **/ 1754s32 e1000_blink_led_generic(struct e1000_hw *hw) 1755{ 1756 u32 ledctl_blink = 0; 1757 u32 i; 1758 1759 DEBUGFUNC("e1000_blink_led_generic"); 1760 1761 if (hw->phy.media_type == e1000_media_type_fiber) { 1762 /* always blink LED0 for PCI-E fiber */ 1763 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1764 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1765 } else { 1766 /* 1767 * set the blink bit for each LED that's "on" (0x0E) 1768 * in ledctl_mode2 1769 */ 1770 ledctl_blink = hw->mac.ledctl_mode2; 1771 for (i = 0; i < 4; i++) 1772 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1773 E1000_LEDCTL_MODE_LED_ON) 1774 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1775 (i * 8)); 1776 } 1777 1778 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1779 1780 return E1000_SUCCESS; 1781} 1782 1783/** 1784 * e1000_led_on_generic - Turn LED on 1785 * @hw: pointer to the HW structure 1786 * 1787 * Turn LED on. 1788 **/ 1789s32 e1000_led_on_generic(struct e1000_hw *hw) 1790{ 1791 u32 ctrl; 1792 1793 DEBUGFUNC("e1000_led_on_generic"); 1794 1795 switch (hw->phy.media_type) { 1796 case e1000_media_type_fiber: 1797 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1798 ctrl &= ~E1000_CTRL_SWDPIN0; 1799 ctrl |= E1000_CTRL_SWDPIO0; 1800 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1801 break; 1802 case e1000_media_type_copper: 1803 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1804 break; 1805 default: 1806 break; 1807 } 1808 1809 return E1000_SUCCESS; 1810} 1811 1812/** 1813 * e1000_led_off_generic - Turn LED off 1814 * @hw: pointer to the HW structure 1815 * 1816 * Turn LED off. 1817 **/ 1818s32 e1000_led_off_generic(struct e1000_hw *hw) 1819{ 1820 u32 ctrl; 1821 1822 DEBUGFUNC("e1000_led_off_generic"); 1823 1824 switch (hw->phy.media_type) { 1825 case e1000_media_type_fiber: 1826 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1827 ctrl |= E1000_CTRL_SWDPIN0; 1828 ctrl |= E1000_CTRL_SWDPIO0; 1829 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1830 break; 1831 case e1000_media_type_copper: 1832 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1833 break; 1834 default: 1835 break; 1836 } 1837 1838 return E1000_SUCCESS; 1839} 1840 1841/** 1842 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1843 * @hw: pointer to the HW structure 1844 * @no_snoop: bitmap of snoop events 1845 * 1846 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1847 **/ 1848void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1849{ 1850 u32 gcr; 1851 1852 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1853 1854 if (hw->bus.type != e1000_bus_type_pci_express) 1855 goto out; 1856 1857 if (no_snoop) { 1858 gcr = E1000_READ_REG(hw, E1000_GCR); 1859 gcr &= ~(PCIE_NO_SNOOP_ALL); 1860 gcr |= no_snoop; 1861 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1862 } 1863out: 1864 return; 1865} 1866 1867/** 1868 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1869 * @hw: pointer to the HW structure 1870 * 1871 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1872 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued 1873 * the master requests to be disabled. 1874 * 1875 * Disables PCI-Express master access and verifies there are no pending 1876 * requests. 1877 **/ 1878s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1879{ 1880 u32 ctrl; 1881 s32 timeout = MASTER_DISABLE_TIMEOUT; 1882 s32 ret_val = E1000_SUCCESS; 1883 1884 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1885 1886 if (hw->bus.type != e1000_bus_type_pci_express) 1887 goto out; 1888 1889 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1890 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1891 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1892 1893 while (timeout) { 1894 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1895 E1000_STATUS_GIO_MASTER_ENABLE)) 1896 break; 1897 usec_delay(100); 1898 timeout--; 1899 } 1900 1901 if (!timeout) { 1902 DEBUGOUT("Master requests are pending.\n"); 1903 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1904 goto out; 1905 } 1906 1907out: 1908 return ret_val; 1909} 1910 1911/** 1912 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1913 * @hw: pointer to the HW structure 1914 * 1915 * Reset the Adaptive Interframe Spacing throttle to default values. 1916 **/ 1917void e1000_reset_adaptive_generic(struct e1000_hw *hw) 1918{ 1919 struct e1000_mac_info *mac = &hw->mac; 1920 1921 DEBUGFUNC("e1000_reset_adaptive_generic"); 1922 1923 if (!mac->adaptive_ifs) { 1924 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1925 goto out; 1926 } 1927 1928 if (!mac->ifs_params_forced) { 1929 mac->current_ifs_val = 0; 1930 mac->ifs_min_val = IFS_MIN; 1931 mac->ifs_max_val = IFS_MAX; 1932 mac->ifs_step_size = IFS_STEP; 1933 mac->ifs_ratio = IFS_RATIO; 1934 } 1935 1936 mac->in_ifs_mode = FALSE; 1937 E1000_WRITE_REG(hw, E1000_AIT, 0); 1938out: 1939 return; 1940} 1941 1942/** 1943 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 1944 * @hw: pointer to the HW structure 1945 * 1946 * Update the Adaptive Interframe Spacing Throttle value based on the 1947 * time between transmitted packets and time between collisions. 1948 **/ 1949void e1000_update_adaptive_generic(struct e1000_hw *hw) 1950{ 1951 struct e1000_mac_info *mac = &hw->mac; 1952 1953 DEBUGFUNC("e1000_update_adaptive_generic"); 1954 1955 if (!mac->adaptive_ifs) { 1956 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1957 goto out; 1958 } 1959 1960 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1961 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1962 mac->in_ifs_mode = TRUE; 1963 if (mac->current_ifs_val < mac->ifs_max_val) { 1964 if (!mac->current_ifs_val) 1965 mac->current_ifs_val = mac->ifs_min_val; 1966 else 1967 mac->current_ifs_val += 1968 mac->ifs_step_size; 1969 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 1970 } 1971 } 1972 } else { 1973 if (mac->in_ifs_mode && 1974 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1975 mac->current_ifs_val = 0; 1976 mac->in_ifs_mode = FALSE; 1977 E1000_WRITE_REG(hw, E1000_AIT, 0); 1978 } 1979 } 1980out: 1981 return; 1982} 1983 1984/** 1985 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 1986 * @hw: pointer to the HW structure 1987 * 1988 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1989 * set, which is forced to MDI mode only. 1990 **/ 1991s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 1992{ 1993 s32 ret_val = E1000_SUCCESS; 1994 1995 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 1996 1997 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1998 DEBUGOUT("Invalid MDI setting detected\n"); 1999 hw->phy.mdix = 1; 2000 ret_val = -E1000_ERR_CONFIG; 2001 goto out; 2002 } 2003 2004out: 2005 return ret_val; 2006} 2007 2008/** 2009 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2010 * @hw: pointer to the HW structure 2011 * @reg: 32bit register offset such as E1000_SCTL 2012 * @offset: register offset to write to 2013 * @data: data to write at register offset 2014 * 2015 * Writes an address/data control type register. There are several of these 2016 * and they all have the format address << 8 | data and bit 31 is polled for 2017 * completion. 2018 **/ 2019s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2020 u32 offset, u8 data) 2021{ 2022 u32 i, regvalue = 0; 2023 s32 ret_val = E1000_SUCCESS; 2024 2025 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2026 2027 /* Set up the address and data */ 2028 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2029 E1000_WRITE_REG(hw, reg, regvalue); 2030 2031 /* Poll the ready bit to see if the MDI read completed */ 2032 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2033 usec_delay(5); 2034 regvalue = E1000_READ_REG(hw, reg); 2035 if (regvalue & E1000_GEN_CTL_READY) 2036 break; 2037 } 2038 if (!(regvalue & E1000_GEN_CTL_READY)) { 2039 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2040 ret_val = -E1000_ERR_PHY; 2041 goto out; 2042 } 2043 2044out: 2045 return ret_val; 2046} 2047