e1000_mac.c revision 169589
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_mac.c 169589 2007-05-16 00:14:23Z jfv $*/ 34 35 36#include "e1000_api.h" 37#include "e1000_mac.h" 38 39/** 40 * e1000_remove_device_generic - Free device specific structure 41 * @hw: pointer to the HW structure 42 * 43 * If a device specific structure was allocated, this function will 44 * free it. 45 **/ 46void 47e1000_remove_device_generic(struct e1000_hw *hw) 48{ 49 DEBUGFUNC("e1000_remove_device_generic"); 50 51 /* Freeing the dev_spec member of e1000_hw structure */ 52 e1000_free_dev_spec_struct(hw); 53} 54 55/** 56 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 57 * @hw: pointer to the HW structure 58 * 59 * Determines and stores the system bus information for a particular 60 * network interface. The following bus information is determined and stored: 61 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 62 **/ 63s32 64e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 65{ 66 struct e1000_bus_info *bus = &hw->bus; 67 u32 status = E1000_READ_REG(hw, E1000_STATUS); 68 s32 ret_val = E1000_SUCCESS; 69 u16 pci_header_type; 70 71 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 72 73 /* PCI or PCI-X? */ 74 bus->type = (status & E1000_STATUS_PCIX_MODE) 75 ? e1000_bus_type_pcix 76 : e1000_bus_type_pci; 77 78 /* Bus speed */ 79 if (bus->type == e1000_bus_type_pci) { 80 bus->speed = (status & E1000_STATUS_PCI66) 81 ? e1000_bus_speed_66 82 : e1000_bus_speed_33; 83 } else { 84 switch (status & E1000_STATUS_PCIX_SPEED) { 85 case E1000_STATUS_PCIX_SPEED_66: 86 bus->speed = e1000_bus_speed_66; 87 break; 88 case E1000_STATUS_PCIX_SPEED_100: 89 bus->speed = e1000_bus_speed_100; 90 break; 91 case E1000_STATUS_PCIX_SPEED_133: 92 bus->speed = e1000_bus_speed_133; 93 break; 94 default: 95 bus->speed = e1000_bus_speed_reserved; 96 break; 97 } 98 } 99 100 /* Bus width */ 101 bus->width = (status & E1000_STATUS_BUS64) 102 ? e1000_bus_width_64 103 : e1000_bus_width_32; 104 105 /* Which PCI(-X) function? */ 106 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 107 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 108 bus->func = (status & E1000_STATUS_FUNC_MASK) 109 >> E1000_STATUS_FUNC_SHIFT; 110 else 111 bus->func = 0; 112 113 return ret_val; 114} 115 116/** 117 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 118 * @hw: pointer to the HW structure 119 * 120 * Determines and stores the system bus information for a particular 121 * network interface. The following bus information is determined and stored: 122 * bus speed, bus width, type (PCIe), and PCIe function. 123 **/ 124s32 125e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 126{ 127 struct e1000_bus_info *bus = &hw->bus; 128 s32 ret_val; 129 u32 status; 130 u16 pcie_link_status, pci_header_type; 131 132 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 133 134 bus->type = e1000_bus_type_pci_express; 135 bus->speed = e1000_bus_speed_2500; 136 137 ret_val = e1000_read_pcie_cap_reg(hw, 138 PCIE_LINK_STATUS, 139 &pcie_link_status); 140 if (ret_val) 141 bus->width = e1000_bus_width_unknown; 142 else 143 bus->width = (e1000_bus_width)((pcie_link_status & 144 PCIE_LINK_WIDTH_MASK) >> 145 PCIE_LINK_WIDTH_SHIFT); 146 147 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 148 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 149 status = E1000_READ_REG(hw, E1000_STATUS); 150 bus->func = (status & E1000_STATUS_FUNC_MASK) 151 >> E1000_STATUS_FUNC_SHIFT; 152 } else 153 bus->func = 0; 154 155 return E1000_SUCCESS; 156} 157 158/** 159 * e1000_clear_vfta_generic - Clear VLAN filter table 160 * @hw: pointer to the HW structure 161 * 162 * Clears the register array which contains the VLAN filter table by 163 * setting all the values to 0. 164 **/ 165void 166e1000_clear_vfta_generic(struct e1000_hw *hw) 167{ 168 u32 offset; 169 170 DEBUGFUNC("e1000_clear_vfta_generic"); 171 172 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 173 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 174 E1000_WRITE_FLUSH(hw); 175 } 176} 177 178/** 179 * e1000_write_vfta_generic - Write value to VLAN filter table 180 * @hw: pointer to the HW structure 181 * @offset: register offset in VLAN filter table 182 * @value: register value written to VLAN filter table 183 * 184 * Writes value at the given offset in the register array which stores 185 * the VLAN filter table. 186 **/ 187void 188e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 189{ 190 DEBUGFUNC("e1000_write_vfta_generic"); 191 192 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 193 E1000_WRITE_FLUSH(hw); 194} 195 196/** 197 * e1000_init_rx_addrs_generic - Initialize receive address's 198 * @hw: pointer to the HW structure 199 * @rar_count: receive address registers 200 * 201 * Setups the receive address registers by setting the base receive address 202 * register to the devices MAC address and clearing all the other receive 203 * address registers to 0. 204 **/ 205void 206e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 207{ 208 u32 i; 209 210 DEBUGFUNC("e1000_init_rx_addrs_generic"); 211 212 /* Setup the receive address */ 213 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 214 215 e1000_rar_set_generic(hw, hw->mac.addr, 0); 216 217 /* Zero out the other (rar_entry_count - 1) receive addresses */ 218 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 219 for (i = 1; i < rar_count; i++) { 220 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 221 E1000_WRITE_FLUSH(hw); 222 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 223 E1000_WRITE_FLUSH(hw); 224 } 225} 226 227/** 228 * e1000_rar_set_generic - Set receive address register 229 * @hw: pointer to the HW structure 230 * @addr: pointer to the receive address 231 * @index: receive address array register 232 * 233 * Sets the receive address array register at index to the address passed 234 * in by addr. 235 **/ 236void 237e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 238{ 239 u32 rar_low, rar_high; 240 241 DEBUGFUNC("e1000_rar_set_generic"); 242 243 /* HW expects these in little endian so we reverse the byte order 244 * from network order (big endian) to little endian 245 */ 246 rar_low = ((u32) addr[0] | 247 ((u32) addr[1] << 8) | 248 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 249 250 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 251 252 if (!hw->mac.disable_av) 253 rar_high |= E1000_RAH_AV; 254 255 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 256 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 257} 258 259/** 260 * e1000_mta_set_generic - Set multicast filter table address 261 * @hw: pointer to the HW structure 262 * @hash_value: determines the MTA register and bit to set 263 * 264 * The multicast table address is a register array of 32-bit registers. 265 * The hash_value is used to determine what register the bit is in, the 266 * current value is read, the new bit is OR'd in and the new value is 267 * written back into the register. 268 **/ 269void 270e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 271{ 272 u32 hash_bit, hash_reg, mta; 273 274 DEBUGFUNC("e1000_mta_set_generic"); 275 /* The MTA is a register array of 32-bit registers. It is 276 * treated like an array of (32*mta_reg_count) bits. We want to 277 * set bit BitArray[hash_value]. So we figure out what register 278 * the bit is in, read it, OR in the new bit, then write 279 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 280 * mask to bits 31:5 of the hash value which gives us the 281 * register we're modifying. The hash bit within that register 282 * is determined by the lower 5 bits of the hash value. 283 */ 284 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 285 hash_bit = hash_value & 0x1F; 286 287 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 288 289 mta |= (1 << hash_bit); 290 291 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 292 E1000_WRITE_FLUSH(hw); 293} 294 295/** 296 * e1000_mc_addr_list_update_generic - Update Multicast addresses 297 * @hw: pointer to the HW structure 298 * @mc_addr_list: array of multicast addresses to program 299 * @mc_addr_count: number of multicast addresses to program 300 * @rar_used_count: the first RAR register free to program 301 * @rar_count: total number of supported Receive Address Registers 302 * 303 * Updates the Receive Address Registers and Multicast Table Array. 304 * The caller must have a packed mc_addr_list of multicast addresses. 305 * The parameter rar_count will usually be hw->mac.rar_entry_count 306 * unless there are workarounds that change this. 307 **/ 308void 309e1000_mc_addr_list_update_generic(struct e1000_hw *hw, 310 u8 *mc_addr_list, u32 mc_addr_count, 311 u32 rar_used_count, u32 rar_count) 312{ 313 u32 hash_value; 314 u32 i; 315 316 DEBUGFUNC("e1000_mc_addr_list_update_generic"); 317 318 /* Load the first set of multicast addresses into the exact 319 * filters (RAR). If there are not enough to fill the RAR 320 * array, clear the filters. 321 */ 322 for (i = rar_used_count; i < rar_count; i++) { 323 if (mc_addr_count) { 324 e1000_rar_set(hw, mc_addr_list, i); 325 mc_addr_count--; 326 mc_addr_list += ETH_ADDR_LEN; 327 } else { 328 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 329 E1000_WRITE_FLUSH(hw); 330 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 331 E1000_WRITE_FLUSH(hw); 332 } 333 } 334 335 /* Clear the old settings from the MTA */ 336 DEBUGOUT("Clearing MTA\n"); 337 for (i = 0; i < hw->mac.mta_reg_count; i++) { 338 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 339 E1000_WRITE_FLUSH(hw); 340 } 341 342 /* Load any remaining multicast addresses into the hash table. */ 343 for (; mc_addr_count > 0; mc_addr_count--) { 344 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 345 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 346 e1000_mta_set(hw, hash_value); 347 mc_addr_list += ETH_ADDR_LEN; 348 } 349} 350 351/** 352 * e1000_hash_mc_addr_generic - Generate a multicast hash value 353 * @hw: pointer to the HW structure 354 * @mc_addr: pointer to a multicast address 355 * 356 * Generates a multicast address hash value which is used to determine 357 * the multicast filter table array address and new table value. See 358 * e1000_mta_set_generic() 359 **/ 360u32 361e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 362{ 363 u32 hash_value, hash_mask; 364 u8 bit_shift = 0; 365 366 DEBUGFUNC("e1000_hash_mc_addr_generic"); 367 368 /* Register count multiplied by bits per register */ 369 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 370 371 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 372 * where 0xFF would still fall within the hash mask. */ 373 while (hash_mask >> bit_shift != 0xFF) 374 bit_shift++; 375 376 /* The portion of the address that is used for the hash table 377 * is determined by the mc_filter_type setting. 378 * The algorithm is such that there is a total of 8 bits of shifting. 379 * The bit_shift for a mc_filter_type of 0 represents the number of 380 * left-shifts where the MSB of mc_addr[5] would still fall within 381 * the hash_mask. Case 0 does this exactly. Since there are a total 382 * of 8 bits of shifting, then mc_addr[4] will shift right the 383 * remaining number of bits. Thus 8 - bit_shift. The rest of the 384 * cases are a variation of this algorithm...essentially raising the 385 * number of bits to shift mc_addr[5] left, while still keeping the 386 * 8-bit shifting total. 387 */ 388 /* For example, given the following Destination MAC Address and an 389 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 390 * we can see that the bit_shift for case 0 is 4. These are the hash 391 * values resulting from each mc_filter_type... 392 * [0] [1] [2] [3] [4] [5] 393 * 01 AA 00 12 34 56 394 * LSB MSB 395 * 396 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 397 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 398 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 399 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 400 */ 401 switch (hw->mac.mc_filter_type) { 402 default: 403 case 0: 404 break; 405 case 1: 406 bit_shift += 1; 407 break; 408 case 2: 409 bit_shift += 2; 410 break; 411 case 3: 412 bit_shift += 4; 413 break; 414 } 415 416 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 417 (((u16) mc_addr[5]) << bit_shift))); 418 419 return hash_value; 420} 421 422/** 423 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 424 * @hw: pointer to the HW structure 425 * 426 * In certain situations, a system BIOS may report that the PCIx maximum 427 * memory read byte count (MMRBC) value is higher than than the actual 428 * value. We check the PCIx command regsiter with the current PCIx status 429 * regsiter. 430 **/ 431void 432e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 433{ 434 u16 cmd_mmrbc; 435 u16 pcix_cmd; 436 u16 pcix_stat_hi_word; 437 u16 stat_mmrbc; 438 439 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 440 441 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 442 if (hw->bus.type != e1000_bus_type_pcix) 443 return; 444 445 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 446 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 447 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 448 PCIX_COMMAND_MMRBC_SHIFT; 449 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 450 PCIX_STATUS_HI_MMRBC_SHIFT; 451 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 452 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 453 if (cmd_mmrbc > stat_mmrbc) { 454 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 455 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 456 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 457 } 458} 459 460/** 461 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 462 * @hw: pointer to the HW structure 463 * 464 * Clears the base hardware counters by reading the counter registers. 465 **/ 466void 467e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 468{ 469 volatile u32 temp; 470 471 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 472 473 temp = E1000_READ_REG(hw, E1000_CRCERRS); 474 temp = E1000_READ_REG(hw, E1000_SYMERRS); 475 temp = E1000_READ_REG(hw, E1000_MPC); 476 temp = E1000_READ_REG(hw, E1000_SCC); 477 temp = E1000_READ_REG(hw, E1000_ECOL); 478 temp = E1000_READ_REG(hw, E1000_MCC); 479 temp = E1000_READ_REG(hw, E1000_LATECOL); 480 temp = E1000_READ_REG(hw, E1000_COLC); 481 temp = E1000_READ_REG(hw, E1000_DC); 482 temp = E1000_READ_REG(hw, E1000_SEC); 483 temp = E1000_READ_REG(hw, E1000_RLEC); 484 temp = E1000_READ_REG(hw, E1000_XONRXC); 485 temp = E1000_READ_REG(hw, E1000_XONTXC); 486 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 487 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 488 temp = E1000_READ_REG(hw, E1000_FCRUC); 489 temp = E1000_READ_REG(hw, E1000_GPRC); 490 temp = E1000_READ_REG(hw, E1000_BPRC); 491 temp = E1000_READ_REG(hw, E1000_MPRC); 492 temp = E1000_READ_REG(hw, E1000_GPTC); 493 temp = E1000_READ_REG(hw, E1000_GORCL); 494 temp = E1000_READ_REG(hw, E1000_GORCH); 495 temp = E1000_READ_REG(hw, E1000_GOTCL); 496 temp = E1000_READ_REG(hw, E1000_GOTCH); 497 temp = E1000_READ_REG(hw, E1000_RNBC); 498 temp = E1000_READ_REG(hw, E1000_RUC); 499 temp = E1000_READ_REG(hw, E1000_RFC); 500 temp = E1000_READ_REG(hw, E1000_ROC); 501 temp = E1000_READ_REG(hw, E1000_RJC); 502 temp = E1000_READ_REG(hw, E1000_TORL); 503 temp = E1000_READ_REG(hw, E1000_TORH); 504 temp = E1000_READ_REG(hw, E1000_TOTL); 505 temp = E1000_READ_REG(hw, E1000_TOTH); 506 temp = E1000_READ_REG(hw, E1000_TPR); 507 temp = E1000_READ_REG(hw, E1000_TPT); 508 temp = E1000_READ_REG(hw, E1000_MPTC); 509 temp = E1000_READ_REG(hw, E1000_BPTC); 510} 511 512/** 513 * e1000_check_for_copper_link_generic - Check for link (Copper) 514 * @hw: pointer to the HW structure 515 * 516 * Checks to see of the link status of the hardware has changed. If a 517 * change in link status has been detected, then we read the PHY registers 518 * to get the current speed/duplex if link exists. 519 **/ 520s32 521e1000_check_for_copper_link_generic(struct e1000_hw *hw) 522{ 523 struct e1000_mac_info *mac = &hw->mac; 524 s32 ret_val; 525 boolean_t link; 526 527 DEBUGFUNC("e1000_check_for_copper_link"); 528 529 /* We only want to go out to the PHY registers to see if Auto-Neg 530 * has completed and/or if our link status has changed. The 531 * get_link_status flag is set upon receiving a Link Status 532 * Change or Rx Sequence Error interrupt. 533 */ 534 if (!mac->get_link_status) { 535 ret_val = E1000_SUCCESS; 536 goto out; 537 } 538 539 /* First we want to see if the MII Status Register reports 540 * link. If so, then we want to get the current speed/duplex 541 * of the PHY. 542 */ 543 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 544 if (ret_val) 545 goto out; 546 547 if (!link) 548 goto out; /* No link detected */ 549 550 mac->get_link_status = FALSE; 551 552 /* Check if there was DownShift, must be checked 553 * immediately after link-up */ 554 e1000_check_downshift_generic(hw); 555 556 /* If we are forcing speed/duplex, then we simply return since 557 * we have already determined whether we have link or not. 558 */ 559 if (!mac->autoneg) { 560 ret_val = -E1000_ERR_CONFIG; 561 goto out; 562 } 563 564 /* Auto-Neg is enabled. Auto Speed Detection takes care 565 * of MAC speed/duplex configuration. So we only need to 566 * configure Collision Distance in the MAC. 567 */ 568 e1000_config_collision_dist_generic(hw); 569 570 /* Configure Flow Control now that Auto-Neg has completed. 571 * First, we need to restore the desired flow control 572 * settings because we may have had to re-autoneg with a 573 * different link partner. 574 */ 575 ret_val = e1000_config_fc_after_link_up_generic(hw); 576 if (ret_val) { 577 DEBUGOUT("Error configuring flow control\n"); 578 } 579 580out: 581 return ret_val; 582} 583 584/** 585 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 586 * @hw: pointer to the HW structure 587 * 588 * Checks for link up on the hardware. If link is not up and we have 589 * a signal, then we need to force link up. 590 **/ 591s32 592e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 593{ 594 struct e1000_mac_info *mac = &hw->mac; 595 u32 rxcw; 596 u32 ctrl; 597 u32 status; 598 s32 ret_val = E1000_SUCCESS; 599 600 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 601 602 ctrl = E1000_READ_REG(hw, E1000_CTRL); 603 status = E1000_READ_REG(hw, E1000_STATUS); 604 rxcw = E1000_READ_REG(hw, E1000_RXCW); 605 606 /* If we don't have link (auto-negotiation failed or link partner 607 * cannot auto-negotiate), the cable is plugged in (we have signal), 608 * and our link partner is not trying to auto-negotiate with us (we 609 * are receiving idles or data), we need to force link up. We also 610 * need to give auto-negotiation time to complete, in case the cable 611 * was just plugged in. The autoneg_failed flag does this. 612 */ 613 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 614 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 615 (!(rxcw & E1000_RXCW_C))) { 616 if (mac->autoneg_failed == 0) { 617 mac->autoneg_failed = 1; 618 goto out; 619 } 620 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 621 622 /* Disable auto-negotiation in the TXCW register */ 623 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 624 625 /* Force link-up and also force full-duplex. */ 626 ctrl = E1000_READ_REG(hw, E1000_CTRL); 627 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 628 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 629 630 /* Configure Flow Control after forcing link up. */ 631 ret_val = e1000_config_fc_after_link_up_generic(hw); 632 if (ret_val) { 633 DEBUGOUT("Error configuring flow control\n"); 634 goto out; 635 } 636 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 637 /* If we are forcing link and we are receiving /C/ ordered 638 * sets, re-enable auto-negotiation in the TXCW register 639 * and disable forced link in the Device Control register 640 * in an attempt to auto-negotiate with our link partner. 641 */ 642 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 643 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 644 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 645 646 mac->serdes_has_link = TRUE; 647 } 648 649out: 650 return ret_val; 651} 652 653/** 654 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 655 * @hw: pointer to the HW structure 656 * 657 * Checks for link up on the hardware. If link is not up and we have 658 * a signal, then we need to force link up. 659 **/ 660s32 661e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 662{ 663 struct e1000_mac_info *mac = &hw->mac; 664 u32 rxcw; 665 u32 ctrl; 666 u32 status; 667 s32 ret_val = E1000_SUCCESS; 668 669 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 670 671 ctrl = E1000_READ_REG(hw, E1000_CTRL); 672 status = E1000_READ_REG(hw, E1000_STATUS); 673 rxcw = E1000_READ_REG(hw, E1000_RXCW); 674 675 /* If we don't have link (auto-negotiation failed or link partner 676 * cannot auto-negotiate), and our link partner is not trying to 677 * auto-negotiate with us (we are receiving idles or data), 678 * we need to force link up. We also need to give auto-negotiation 679 * time to complete. 680 */ 681 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 682 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 683 if (mac->autoneg_failed == 0) { 684 mac->autoneg_failed = 1; 685 goto out; 686 } 687 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 688 689 /* Disable auto-negotiation in the TXCW register */ 690 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 691 692 /* Force link-up and also force full-duplex. */ 693 ctrl = E1000_READ_REG(hw, E1000_CTRL); 694 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 695 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 696 697 /* Configure Flow Control after forcing link up. */ 698 ret_val = e1000_config_fc_after_link_up_generic(hw); 699 if (ret_val) { 700 DEBUGOUT("Error configuring flow control\n"); 701 goto out; 702 } 703 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 704 /* If we are forcing link and we are receiving /C/ ordered 705 * sets, re-enable auto-negotiation in the TXCW register 706 * and disable forced link in the Device Control register 707 * in an attempt to auto-negotiate with our link partner. 708 */ 709 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 710 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 711 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 712 713 mac->serdes_has_link = TRUE; 714 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 715 /* If we force link for non-auto-negotiation switch, check 716 * link status based on MAC synchronization for internal 717 * serdes media type. 718 */ 719 /* SYNCH bit and IV bit are sticky. */ 720 usec_delay(10); 721 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 722 if (!(rxcw & E1000_RXCW_IV)) { 723 mac->serdes_has_link = TRUE; 724 DEBUGOUT("SERDES: Link is up.\n"); 725 } 726 } else { 727 mac->serdes_has_link = FALSE; 728 DEBUGOUT("SERDES: Link is down.\n"); 729 } 730 } 731 732 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 733 status = E1000_READ_REG(hw, E1000_STATUS); 734 mac->serdes_has_link = (status & E1000_STATUS_LU) 735 ? TRUE 736 : FALSE; 737 } 738 739out: 740 return ret_val; 741} 742 743/** 744 * e1000_setup_link_generic - Setup flow control and link settings 745 * @hw: pointer to the HW structure 746 * 747 * Determines which flow control settings to use, then configures flow 748 * control. Calls the appropriate media-specific link configuration 749 * function. Assuming the adapter has a valid link partner, a valid link 750 * should be established. Assumes the hardware has previously been reset 751 * and the transmitter and receiver are not enabled. 752 **/ 753s32 754e1000_setup_link_generic(struct e1000_hw *hw) 755{ 756 struct e1000_mac_info *mac = &hw->mac; 757 struct e1000_functions *func = &hw->func; 758 s32 ret_val = E1000_SUCCESS; 759 760 DEBUGFUNC("e1000_setup_link_generic"); 761 762 /* In the case of the phy reset being blocked, we already have a link. 763 * We do not need to set it up again. 764 */ 765 if (e1000_check_reset_block(hw)) 766 goto out; 767 768 ret_val = e1000_set_default_fc_generic(hw); 769 if (ret_val) 770 goto out; 771 772 /* We want to save off the original Flow Control configuration just 773 * in case we get disconnected and then reconnected into a different 774 * hub or switch with different Flow Control capabilities. 775 */ 776 mac->original_fc = mac->fc; 777 778 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); 779 780 /* Call the necessary media_type subroutine to configure the link. */ 781 ret_val = func->setup_physical_interface(hw); 782 if (ret_val) 783 goto out; 784 785 /* Initialize the flow control address, type, and PAUSE timer 786 * registers to their default values. This is done even if flow 787 * control is disabled, because it does not hurt anything to 788 * initialize these registers. 789 */ 790 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 791 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 792 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 793 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 794 795 E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); 796 797 ret_val = e1000_set_fc_watermarks_generic(hw); 798 799out: 800 return ret_val; 801} 802 803/** 804 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 805 * @hw: pointer to the HW structure 806 * 807 * Configures collision distance and flow control for fiber and serdes 808 * links. Upon successful setup, poll for link. 809 **/ 810s32 811e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 812{ 813 u32 ctrl; 814 s32 ret_val = E1000_SUCCESS; 815 816 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 817 818 ctrl = E1000_READ_REG(hw, E1000_CTRL); 819 820 /* Take the link out of reset */ 821 ctrl &= ~E1000_CTRL_LRST; 822 823 e1000_config_collision_dist_generic(hw); 824 825 ret_val = e1000_commit_fc_settings_generic(hw); 826 if (ret_val) 827 goto out; 828 829 /* Since auto-negotiation is enabled, take the link out of reset (the 830 * link will be in reset, because we previously reset the chip). This 831 * will restart auto-negotiation. If auto-negotiation is successful 832 * then the link-up status bit will be set and the flow control enable 833 * bits (RFCE and TFCE) will be set according to their negotiated value. 834 */ 835 DEBUGOUT("Auto-negotiation enabled\n"); 836 837 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 838 E1000_WRITE_FLUSH(hw); 839 msec_delay(1); 840 841 /* For these adapters, the SW defineable pin 1 is set when the optics 842 * detect a signal. If we have a signal, then poll for a "Link-Up" 843 * indication. 844 */ 845 if (hw->media_type == e1000_media_type_internal_serdes || 846 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 847 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 848 } else { 849 DEBUGOUT("No signal detected\n"); 850 } 851 852out: 853 return ret_val; 854} 855 856/** 857 * e1000_config_collision_dist_generic - Configure collision distance 858 * @hw: pointer to the HW structure 859 * 860 * Configures the collision distance to the default value and is used 861 * during link setup. Currently no func pointer exists and all 862 * implementations are handled in the generic version of this function. 863 **/ 864void 865e1000_config_collision_dist_generic(struct e1000_hw *hw) 866{ 867 u32 tctl; 868 869 DEBUGFUNC("e1000_config_collision_dist_generic"); 870 871 tctl = E1000_READ_REG(hw, E1000_TCTL); 872 873 tctl &= ~E1000_TCTL_COLD; 874 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 875 876 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 877 E1000_WRITE_FLUSH(hw); 878} 879 880/** 881 * e1000_poll_fiber_serdes_link_generic - Poll for link up 882 * @hw: pointer to the HW structure 883 * 884 * Polls for link up by reading the status register, if link fails to come 885 * up with auto-negotiation, then the link is forced if a signal is detected. 886 **/ 887s32 888e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 889{ 890 struct e1000_mac_info *mac = &hw->mac; 891 u32 i, status; 892 s32 ret_val = E1000_SUCCESS; 893 894 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 895 896 /* If we have a signal (the cable is plugged in, or assumed true for 897 * serdes media) then poll for a "Link-Up" indication in the Device 898 * Status Register. Time-out if a link isn't seen in 500 milliseconds 899 * seconds (Auto-negotiation should complete in less than 500 900 * milliseconds even if the other end is doing it in SW). 901 */ 902 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 903 msec_delay(10); 904 status = E1000_READ_REG(hw, E1000_STATUS); 905 if (status & E1000_STATUS_LU) 906 break; 907 } 908 if (i == FIBER_LINK_UP_LIMIT) { 909 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 910 mac->autoneg_failed = 1; 911 /* AutoNeg failed to achieve a link, so we'll call 912 * mac->check_for_link. This routine will force the 913 * link up if we detect a signal. This will allow us to 914 * communicate with non-autonegotiating link partners. 915 */ 916 ret_val = e1000_check_for_link(hw); 917 if (ret_val) { 918 DEBUGOUT("Error while checking for link\n"); 919 goto out; 920 } 921 mac->autoneg_failed = 0; 922 } else { 923 mac->autoneg_failed = 0; 924 DEBUGOUT("Valid Link Found\n"); 925 } 926 927out: 928 return ret_val; 929} 930 931/** 932 * e1000_commit_fc_settings_generic - Configure flow control 933 * @hw: pointer to the HW structure 934 * 935 * Write the flow control settings to the Transmit Config Word Register (TXCW) 936 * base on the flow control settings in e1000_mac_info. 937 **/ 938s32 939e1000_commit_fc_settings_generic(struct e1000_hw *hw) 940{ 941 struct e1000_mac_info *mac = &hw->mac; 942 u32 txcw; 943 s32 ret_val = E1000_SUCCESS; 944 945 DEBUGFUNC("e1000_commit_fc_settings_generic"); 946 947 /* Check for a software override of the flow control settings, and 948 * setup the device accordingly. If auto-negotiation is enabled, then 949 * software will have to set the "PAUSE" bits to the correct value in 950 * the Transmit Config Word Register (TXCW) and re-start auto- 951 * negotiation. However, if auto-negotiation is disabled, then 952 * software will have to manually configure the two flow control enable 953 * bits in the CTRL register. 954 * 955 * The possible values of the "fc" parameter are: 956 * 0: Flow control is completely disabled 957 * 1: Rx flow control is enabled (we can receive pause frames, 958 * but not send pause frames). 959 * 2: Tx flow control is enabled (we can send pause frames but we 960 * do not support receiving pause frames). 961 * 3: Both Rx and TX flow control (symmetric) are enabled. 962 */ 963 switch (mac->fc) { 964 case e1000_fc_none: 965 /* Flow control completely disabled by a software over-ride. */ 966 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 967 break; 968 case e1000_fc_rx_pause: 969 /* RX Flow control is enabled and TX Flow control is disabled 970 * by a software over-ride. Since there really isn't a way to 971 * advertise that we are capable of RX Pause ONLY, we will 972 * advertise that we support both symmetric and asymmetric RX 973 * PAUSE. Later, we will disable the adapter's ability to send 974 * PAUSE frames. 975 */ 976 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 977 break; 978 case e1000_fc_tx_pause: 979 /* TX Flow control is enabled, and RX Flow control is disabled, 980 * by a software over-ride. 981 */ 982 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 983 break; 984 case e1000_fc_full: 985 /* Flow control (both RX and TX) is enabled by a software 986 * over-ride. 987 */ 988 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 989 break; 990 default: 991 DEBUGOUT("Flow control param set incorrectly\n"); 992 ret_val = -E1000_ERR_CONFIG; 993 goto out; 994 break; 995 } 996 997 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 998 mac->txcw = txcw; 999 1000out: 1001 return ret_val; 1002} 1003 1004/** 1005 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1006 * @hw: pointer to the HW structure 1007 * 1008 * Sets the flow control high/low threshold (watermark) registers. If 1009 * flow control XON frame transmission is enabled, then set XON frame 1010 * tansmission as well. 1011 **/ 1012s32 1013e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1014{ 1015 struct e1000_mac_info *mac = &hw->mac; 1016 s32 ret_val = E1000_SUCCESS; 1017 u32 fcrtl = 0, fcrth = 0; 1018 1019 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1020 1021 /* Set the flow control receive threshold registers. Normally, 1022 * these registers will be set to a default threshold that may be 1023 * adjusted later by the driver's runtime code. However, if the 1024 * ability to transmit pause frames is not enabled, then these 1025 * registers will be set to 0. 1026 */ 1027 if (mac->fc & e1000_fc_tx_pause) { 1028 /* We need to set up the Receive Threshold high and low water 1029 * marks as well as (optionally) enabling the transmission of 1030 * XON frames. 1031 */ 1032 fcrtl = mac->fc_low_water; 1033 if (mac->fc_send_xon) 1034 fcrtl |= E1000_FCRTL_XONE; 1035 1036 fcrth = mac->fc_high_water; 1037 } 1038 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1039 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1040 1041 return ret_val; 1042} 1043 1044/** 1045 * e1000_set_default_fc_generic - Set flow control default values 1046 * @hw: pointer to the HW structure 1047 * 1048 * Read the EEPROM for the default values for flow control and store the 1049 * values. 1050 **/ 1051s32 1052e1000_set_default_fc_generic(struct e1000_hw *hw) 1053{ 1054 struct e1000_mac_info *mac = &hw->mac; 1055 s32 ret_val = E1000_SUCCESS; 1056 u16 nvm_data; 1057 1058 DEBUGFUNC("e1000_set_default_fc_generic"); 1059 1060 if (mac->fc != e1000_fc_default) 1061 goto out; 1062 1063 /* Read and store word 0x0F of the EEPROM. This word contains bits 1064 * that determine the hardware's default PAUSE (flow control) mode, 1065 * a bit that determines whether the HW defaults to enabling or 1066 * disabling auto-negotiation, and the direction of the 1067 * SW defined pins. If there is no SW over-ride of the flow 1068 * control setting, then the variable hw->fc will 1069 * be initialized based on a value in the EEPROM. 1070 */ 1071 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1072 1073 if (ret_val) { 1074 DEBUGOUT("NVM Read Error\n"); 1075 goto out; 1076 } 1077 1078 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1079 mac->fc = e1000_fc_none; 1080 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1081 NVM_WORD0F_ASM_DIR) 1082 mac->fc = e1000_fc_tx_pause; 1083 else 1084 mac->fc = e1000_fc_full; 1085 1086out: 1087 return ret_val; 1088} 1089 1090/** 1091 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1092 * @hw: pointer to the HW structure 1093 * 1094 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1095 * device control register to reflect the adapter settings. TFCE and RFCE 1096 * need to be explicitly set by software when a copper PHY is used because 1097 * autonegotiation is managed by the PHY rather than the MAC. Software must 1098 * also configure these bits when link is forced on a fiber connection. 1099 **/ 1100s32 1101e1000_force_mac_fc_generic(struct e1000_hw *hw) 1102{ 1103 struct e1000_mac_info *mac = &hw->mac; 1104 u32 ctrl; 1105 s32 ret_val = E1000_SUCCESS; 1106 1107 DEBUGFUNC("e1000_force_mac_fc_generic"); 1108 1109 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1110 1111 /* Because we didn't get link via the internal auto-negotiation 1112 * mechanism (we either forced link or we got link via PHY 1113 * auto-neg), we have to manually enable/disable transmit an 1114 * receive flow control. 1115 * 1116 * The "Case" statement below enables/disable flow control 1117 * according to the "mac->fc" parameter. 1118 * 1119 * The possible values of the "fc" parameter are: 1120 * 0: Flow control is completely disabled 1121 * 1: Rx flow control is enabled (we can receive pause 1122 * frames but not send pause frames). 1123 * 2: Tx flow control is enabled (we can send pause frames 1124 * frames but we do not receive pause frames). 1125 * 3: Both Rx and TX flow control (symmetric) is enabled. 1126 * other: No other values should be possible at this point. 1127 */ 1128 DEBUGOUT1("mac->fc = %u\n", mac->fc); 1129 1130 switch (mac->fc) { 1131 case e1000_fc_none: 1132 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1133 break; 1134 case e1000_fc_rx_pause: 1135 ctrl &= (~E1000_CTRL_TFCE); 1136 ctrl |= E1000_CTRL_RFCE; 1137 break; 1138 case e1000_fc_tx_pause: 1139 ctrl &= (~E1000_CTRL_RFCE); 1140 ctrl |= E1000_CTRL_TFCE; 1141 break; 1142 case e1000_fc_full: 1143 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1144 break; 1145 default: 1146 DEBUGOUT("Flow control param set incorrectly\n"); 1147 ret_val = -E1000_ERR_CONFIG; 1148 goto out; 1149 } 1150 1151 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1152 1153out: 1154 return ret_val; 1155} 1156 1157/** 1158 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1159 * @hw: pointer to the HW structure 1160 * 1161 * Checks the status of auto-negotiation after link up to ensure that the 1162 * speed and duplex were not forced. If the link needed to be forced, then 1163 * flow control needs to be forced also. If auto-negotiation is enabled 1164 * and did not fail, then we configure flow control based on our link 1165 * partner. 1166 **/ 1167s32 1168e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1169{ 1170 struct e1000_mac_info *mac = &hw->mac; 1171 s32 ret_val = E1000_SUCCESS; 1172 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1173 u16 speed, duplex; 1174 1175 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1176 1177 /* Check for the case where we have fiber media and auto-neg failed 1178 * so we had to force link. In this case, we need to force the 1179 * configuration of the MAC to match the "fc" parameter. 1180 */ 1181 if (mac->autoneg_failed) { 1182 if (hw->media_type == e1000_media_type_fiber || 1183 hw->media_type == e1000_media_type_internal_serdes) 1184 ret_val = e1000_force_mac_fc_generic(hw); 1185 } else { 1186 if (hw->media_type == e1000_media_type_copper) 1187 ret_val = e1000_force_mac_fc_generic(hw); 1188 } 1189 1190 if (ret_val) { 1191 DEBUGOUT("Error forcing flow control settings\n"); 1192 goto out; 1193 } 1194 1195 /* Check for the case where we have copper media and auto-neg is 1196 * enabled. In this case, we need to check and see if Auto-Neg 1197 * has completed, and if so, how the PHY and link partner has 1198 * flow control configured. 1199 */ 1200 if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) { 1201 /* Read the MII Status Register and check to see if AutoNeg 1202 * has completed. We read this twice because this reg has 1203 * some "sticky" (latched) bits. 1204 */ 1205 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1206 if (ret_val) 1207 goto out; 1208 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1209 if (ret_val) 1210 goto out; 1211 1212 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1213 DEBUGOUT("Copper PHY and Auto Neg " 1214 "has not completed.\n"); 1215 goto out; 1216 } 1217 1218 /* The AutoNeg process has completed, so we now need to 1219 * read both the Auto Negotiation Advertisement 1220 * Register (Address 4) and the Auto_Negotiation Base 1221 * Page Ability Register (Address 5) to determine how 1222 * flow control was negotiated. 1223 */ 1224 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1225 &mii_nway_adv_reg); 1226 if (ret_val) 1227 goto out; 1228 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 1229 &mii_nway_lp_ability_reg); 1230 if (ret_val) 1231 goto out; 1232 1233 /* Two bits in the Auto Negotiation Advertisement Register 1234 * (Address 4) and two bits in the Auto Negotiation Base 1235 * Page Ability Register (Address 5) determine flow control 1236 * for both the PHY and the link partner. The following 1237 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1238 * 1999, describes these PAUSE resolution bits and how flow 1239 * control is determined based upon these settings. 1240 * NOTE: DC = Don't Care 1241 * 1242 * LOCAL DEVICE | LINK PARTNER 1243 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1244 *-------|---------|-------|---------|-------------------- 1245 * 0 | 0 | DC | DC | e1000_fc_none 1246 * 0 | 1 | 0 | DC | e1000_fc_none 1247 * 0 | 1 | 1 | 0 | e1000_fc_none 1248 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1249 * 1 | 0 | 0 | DC | e1000_fc_none 1250 * 1 | DC | 1 | DC | e1000_fc_full 1251 * 1 | 1 | 0 | 0 | e1000_fc_none 1252 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1253 * 1254 */ 1255 /* Are both PAUSE bits set to 1? If so, this implies 1256 * Symmetric Flow Control is enabled at both ends. The 1257 * ASM_DIR bits are irrelevant per the spec. 1258 * 1259 * For Symmetric Flow Control: 1260 * 1261 * LOCAL DEVICE | LINK PARTNER 1262 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1263 *-------|---------|-------|---------|-------------------- 1264 * 1 | DC | 1 | DC | E1000_fc_full 1265 * 1266 */ 1267 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1268 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1269 /* Now we need to check if the user selected RX ONLY 1270 * of pause frames. In this case, we had to advertise 1271 * FULL flow control because we could not advertise RX 1272 * ONLY. Hence, we must now check to see if we need to 1273 * turn OFF the TRANSMISSION of PAUSE frames. 1274 */ 1275 if (mac->original_fc == e1000_fc_full) { 1276 mac->fc = e1000_fc_full; 1277 DEBUGOUT("Flow Control = FULL.\r\n"); 1278 } else { 1279 mac->fc = e1000_fc_rx_pause; 1280 DEBUGOUT("Flow Control = " 1281 "RX PAUSE frames only.\r\n"); 1282 } 1283 } 1284 /* For receiving PAUSE frames ONLY. 1285 * 1286 * LOCAL DEVICE | LINK PARTNER 1287 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1288 *-------|---------|-------|---------|-------------------- 1289 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1290 * 1291 */ 1292 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1293 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1294 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1295 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1296 mac->fc = e1000_fc_tx_pause; 1297 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1298 } 1299 /* For transmitting PAUSE frames ONLY. 1300 * 1301 * LOCAL DEVICE | LINK PARTNER 1302 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1303 *-------|---------|-------|---------|-------------------- 1304 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1305 * 1306 */ 1307 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1308 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1309 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1310 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1311 mac->fc = e1000_fc_rx_pause; 1312 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1313 } 1314 /* Per the IEEE spec, at this point flow control should be 1315 * disabled. However, we want to consider that we could 1316 * be connected to a legacy switch that doesn't advertise 1317 * desired flow control, but can be forced on the link 1318 * partner. So if we advertised no flow control, that is 1319 * what we will resolve to. If we advertised some kind of 1320 * receive capability (Rx Pause Only or Full Flow Control) 1321 * and the link partner advertised none, we will configure 1322 * ourselves to enable Rx Flow Control only. We can do 1323 * this safely for two reasons: If the link partner really 1324 * didn't want flow control enabled, and we enable Rx, no 1325 * harm done since we won't be receiving any PAUSE frames 1326 * anyway. If the intent on the link partner was to have 1327 * flow control enabled, then by us enabling RX only, we 1328 * can at least receive pause frames and process them. 1329 * This is a good idea because in most cases, since we are 1330 * predominantly a server NIC, more times than not we will 1331 * be asked to delay transmission of packets than asking 1332 * our link partner to pause transmission of frames. 1333 */ 1334 else if ((mac->original_fc == e1000_fc_none || 1335 mac->original_fc == e1000_fc_tx_pause) || 1336 mac->fc_strict_ieee) { 1337 mac->fc = e1000_fc_none; 1338 DEBUGOUT("Flow Control = NONE.\r\n"); 1339 } else { 1340 mac->fc = e1000_fc_rx_pause; 1341 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1342 } 1343 1344 /* Now we need to do one last check... If we auto- 1345 * negotiated to HALF DUPLEX, flow control should not be 1346 * enabled per IEEE 802.3 spec. 1347 */ 1348 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1349 if (ret_val) { 1350 DEBUGOUT("Error getting link speed and duplex\n"); 1351 goto out; 1352 } 1353 1354 if (duplex == HALF_DUPLEX) 1355 mac->fc = e1000_fc_none; 1356 1357 /* Now we call a subroutine to actually force the MAC 1358 * controller to use the correct flow control settings. 1359 */ 1360 ret_val = e1000_force_mac_fc_generic(hw); 1361 if (ret_val) { 1362 DEBUGOUT("Error forcing flow control settings\n"); 1363 goto out; 1364 } 1365 } 1366 1367out: 1368 return ret_val; 1369} 1370 1371/** 1372 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex 1373 * @hw: pointer to the HW structure 1374 * @speed: stores the current speed 1375 * @duplex: stores the current duplex 1376 * 1377 * Read the status register for the current speed/duplex and store the current 1378 * speed and duplex for copper connections. 1379 **/ 1380s32 1381e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1382 u16 *duplex) 1383{ 1384 u32 status; 1385 1386 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1387 1388 status = E1000_READ_REG(hw, E1000_STATUS); 1389 if (status & E1000_STATUS_SPEED_1000) { 1390 *speed = SPEED_1000; 1391 DEBUGOUT("1000 Mbs, "); 1392 } else if (status & E1000_STATUS_SPEED_100) { 1393 *speed = SPEED_100; 1394 DEBUGOUT("100 Mbs, "); 1395 } else { 1396 *speed = SPEED_10; 1397 DEBUGOUT("10 Mbs, "); 1398 } 1399 1400 if (status & E1000_STATUS_FD) { 1401 *duplex = FULL_DUPLEX; 1402 DEBUGOUT("Full Duplex\n"); 1403 } else { 1404 *duplex = HALF_DUPLEX; 1405 DEBUGOUT("Half Duplex\n"); 1406 } 1407 1408 return E1000_SUCCESS; 1409} 1410 1411/** 1412 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex 1413 * @hw: pointer to the HW structure 1414 * @speed: stores the current speed 1415 * @duplex: stores the current duplex 1416 * 1417 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1418 * for fiber/serdes links. 1419 **/ 1420s32 1421e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, u16 *speed, 1422 u16 *duplex) 1423{ 1424 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1425 1426 *speed = SPEED_1000; 1427 *duplex = FULL_DUPLEX; 1428 1429 return E1000_SUCCESS; 1430} 1431 1432/** 1433 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1434 * @hw: pointer to the HW structure 1435 * 1436 * Acquire the HW semaphore to access the PHY or NVM 1437 **/ 1438s32 1439e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1440{ 1441 u32 swsm; 1442 s32 ret_val = E1000_SUCCESS; 1443 s32 timeout = hw->nvm.word_size + 1; 1444 s32 i = 0; 1445 1446 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1447 1448 /* Get the SW semaphore */ 1449 while (i < timeout) { 1450 swsm = E1000_READ_REG(hw, E1000_SWSM); 1451 if (!(swsm & E1000_SWSM_SMBI)) 1452 break; 1453 1454 usec_delay(50); 1455 i++; 1456 } 1457 1458 if (i == timeout) { 1459 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1460 ret_val = -E1000_ERR_NVM; 1461 goto out; 1462 } 1463 1464 /* Get the FW semaphore. */ 1465 for (i = 0; i < timeout; i++) { 1466 swsm = E1000_READ_REG(hw, E1000_SWSM); 1467 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1468 1469 /* Semaphore acquired if bit latched */ 1470 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1471 break; 1472 1473 usec_delay(50); 1474 } 1475 1476 if (i == timeout) { 1477 /* Release semaphores */ 1478 e1000_put_hw_semaphore_generic(hw); 1479 DEBUGOUT("Driver can't access the NVM\n"); 1480 ret_val = -E1000_ERR_NVM; 1481 goto out; 1482 } 1483 1484out: 1485 return ret_val; 1486} 1487 1488/** 1489 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1490 * @hw: pointer to the HW structure 1491 * 1492 * Release hardware semaphore used to access the PHY or NVM 1493 **/ 1494void 1495e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1496{ 1497 u32 swsm; 1498 1499 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1500 1501 swsm = E1000_READ_REG(hw, E1000_SWSM); 1502 1503 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1504 1505 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1506} 1507 1508/** 1509 * e1000_get_auto_rd_done_generic - Check for auto read completion 1510 * @hw: pointer to the HW structure 1511 * 1512 * Check EEPROM for Auto Read done bit. 1513 **/ 1514s32 1515e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1516{ 1517 s32 i = 0; 1518 s32 ret_val = E1000_SUCCESS; 1519 1520 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1521 1522 while (i < AUTO_READ_DONE_TIMEOUT) { 1523 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1524 break; 1525 msec_delay(1); 1526 i++; 1527 } 1528 1529 if (i == AUTO_READ_DONE_TIMEOUT) { 1530 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1531 ret_val = -E1000_ERR_RESET; 1532 goto out; 1533 } 1534 1535out: 1536 return ret_val; 1537} 1538 1539/** 1540 * e1000_valid_led_default_generic - Verify a valid default LED config 1541 * @hw: pointer to the HW structure 1542 * @data: pointer to the NVM (EEPROM) 1543 * 1544 * Read the EEPROM for the current default LED configuration. If the 1545 * LED configuration is not valid, set to a valid LED configuration. 1546 **/ 1547s32 1548e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1549{ 1550 s32 ret_val; 1551 1552 DEBUGFUNC("e1000_valid_led_default_generic"); 1553 1554 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1555 if (ret_val) { 1556 DEBUGOUT("NVM Read Error\n"); 1557 goto out; 1558 } 1559 1560 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1561 *data = ID_LED_DEFAULT; 1562 1563out: 1564 return ret_val; 1565} 1566 1567/** 1568 * e1000_id_led_init_generic - 1569 * @hw: pointer to the HW structure 1570 * 1571 **/ 1572s32 1573e1000_id_led_init_generic(struct e1000_hw * hw) 1574{ 1575 struct e1000_mac_info *mac = &hw->mac; 1576 s32 ret_val; 1577 const u32 ledctl_mask = 0x000000FF; 1578 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1579 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1580 u16 data, i, temp; 1581 const u16 led_mask = 0x0F; 1582 1583 DEBUGFUNC("e1000_id_led_init_generic"); 1584 1585 ret_val = hw->func.valid_led_default(hw, &data); 1586 if (ret_val) 1587 goto out; 1588 1589 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1590 mac->ledctl_mode1 = mac->ledctl_default; 1591 mac->ledctl_mode2 = mac->ledctl_default; 1592 1593 for (i = 0; i < 4; i++) { 1594 temp = (data >> (i << 2)) & led_mask; 1595 switch (temp) { 1596 case ID_LED_ON1_DEF2: 1597 case ID_LED_ON1_ON2: 1598 case ID_LED_ON1_OFF2: 1599 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1600 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1601 break; 1602 case ID_LED_OFF1_DEF2: 1603 case ID_LED_OFF1_ON2: 1604 case ID_LED_OFF1_OFF2: 1605 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1606 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1607 break; 1608 default: 1609 /* Do nothing */ 1610 break; 1611 } 1612 switch (temp) { 1613 case ID_LED_DEF1_ON2: 1614 case ID_LED_ON1_ON2: 1615 case ID_LED_OFF1_ON2: 1616 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1617 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1618 break; 1619 case ID_LED_DEF1_OFF2: 1620 case ID_LED_ON1_OFF2: 1621 case ID_LED_OFF1_OFF2: 1622 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1623 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1624 break; 1625 default: 1626 /* Do nothing */ 1627 break; 1628 } 1629 } 1630 1631out: 1632 return ret_val; 1633} 1634 1635/** 1636 * e1000_setup_led_generic - Configures SW controllable LED 1637 * @hw: pointer to the HW structure 1638 * 1639 * This prepares the SW controllable LED for use and saves the current state 1640 * of the LED so it can be later restored. 1641 **/ 1642s32 1643e1000_setup_led_generic(struct e1000_hw *hw) 1644{ 1645 u32 ledctl; 1646 s32 ret_val = E1000_SUCCESS; 1647 1648 DEBUGFUNC("e1000_setup_led_generic"); 1649 1650 if (hw->func.setup_led != e1000_setup_led_generic) { 1651 ret_val = -E1000_ERR_CONFIG; 1652 goto out; 1653 } 1654 1655 if (hw->media_type == e1000_media_type_fiber) { 1656 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1657 hw->mac.ledctl_default = ledctl; 1658 /* Turn off LED0 */ 1659 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1660 E1000_LEDCTL_LED0_BLINK | 1661 E1000_LEDCTL_LED0_MODE_MASK); 1662 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1663 E1000_LEDCTL_LED0_MODE_SHIFT); 1664 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1665 } else if (hw->media_type == e1000_media_type_copper) { 1666 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1667 } 1668 1669out: 1670 return ret_val; 1671} 1672 1673/** 1674 * e1000_cleanup_led_generic - Set LED config to default operation 1675 * @hw: pointer to the HW structure 1676 * 1677 * Remove the current LED configuration and set the LED configuration 1678 * to the default value, saved from the EEPROM. 1679 **/ 1680s32 1681e1000_cleanup_led_generic(struct e1000_hw *hw) 1682{ 1683 s32 ret_val = E1000_SUCCESS; 1684 1685 DEBUGFUNC("e1000_cleanup_led_generic"); 1686 1687 if (hw->func.cleanup_led != e1000_cleanup_led_generic) { 1688 ret_val = -E1000_ERR_CONFIG; 1689 goto out; 1690 } 1691 1692 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1693 1694out: 1695 return ret_val; 1696} 1697 1698/** 1699 * e1000_blink_led_generic - Blink LED 1700 * @hw: pointer to the HW structure 1701 * 1702 * Blink the led's which are set to be on. 1703 **/ 1704s32 1705e1000_blink_led_generic(struct e1000_hw *hw) 1706{ 1707 u32 ledctl_blink = 0; 1708 u32 i; 1709 1710 DEBUGFUNC("e1000_blink_led_generic"); 1711 1712 if (hw->media_type == e1000_media_type_fiber) { 1713 /* always blink LED0 for PCI-E fiber */ 1714 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1715 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1716 } else { 1717 /* set the blink bit for each LED that's "on" (0x0E) 1718 * in ledctl_mode2 */ 1719 ledctl_blink = hw->mac.ledctl_mode2; 1720 for (i = 0; i < 4; i++) 1721 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1722 E1000_LEDCTL_MODE_LED_ON) 1723 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1724 (i * 8)); 1725 } 1726 1727 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1728 1729 return E1000_SUCCESS; 1730} 1731 1732/** 1733 * e1000_led_on_generic - Turn LED on 1734 * @hw: pointer to the HW structure 1735 * 1736 * Turn LED on. 1737 **/ 1738s32 1739e1000_led_on_generic(struct e1000_hw *hw) 1740{ 1741 u32 ctrl; 1742 1743 DEBUGFUNC("e1000_led_on_generic"); 1744 1745 switch (hw->media_type) { 1746 case e1000_media_type_fiber: 1747 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1748 ctrl &= ~E1000_CTRL_SWDPIN0; 1749 ctrl |= E1000_CTRL_SWDPIO0; 1750 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1751 break; 1752 case e1000_media_type_copper: 1753 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1754 break; 1755 default: 1756 break; 1757 } 1758 1759 return E1000_SUCCESS; 1760} 1761 1762/** 1763 * e1000_led_off_generic - Turn LED off 1764 * @hw: pointer to the HW structure 1765 * 1766 * Turn LED off. 1767 **/ 1768s32 1769e1000_led_off_generic(struct e1000_hw *hw) 1770{ 1771 u32 ctrl; 1772 1773 DEBUGFUNC("e1000_led_off_generic"); 1774 1775 switch (hw->media_type) { 1776 case e1000_media_type_fiber: 1777 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1778 ctrl |= E1000_CTRL_SWDPIN0; 1779 ctrl |= E1000_CTRL_SWDPIO0; 1780 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1781 break; 1782 case e1000_media_type_copper: 1783 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1784 break; 1785 default: 1786 break; 1787 } 1788 1789 return E1000_SUCCESS; 1790} 1791 1792/** 1793 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1794 * @hw: pointer to the HW structure 1795 * @no_snoop: bitmap of snoop events 1796 * 1797 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1798 **/ 1799void 1800e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1801{ 1802 u32 gcr; 1803 1804 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1805 1806 if (hw->bus.type != e1000_bus_type_pci_express) 1807 goto out; 1808 1809 if (no_snoop) { 1810 gcr = E1000_READ_REG(hw, E1000_GCR); 1811 gcr &= ~(PCIE_NO_SNOOP_ALL); 1812 gcr |= no_snoop; 1813 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1814 } 1815out: 1816 return; 1817} 1818 1819/** 1820 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1821 * @hw: pointer to the HW structure 1822 * 1823 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1824 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued 1825 * the master requests to be disabled. 1826 * 1827 * Disables PCI-Express master access and verifies there are no pending 1828 * requests. 1829 **/ 1830s32 1831e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1832{ 1833 u32 ctrl; 1834 s32 timeout = MASTER_DISABLE_TIMEOUT; 1835 s32 ret_val = E1000_SUCCESS; 1836 1837 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1838 1839 if (hw->bus.type != e1000_bus_type_pci_express) 1840 goto out; 1841 1842 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1843 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1844 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1845 1846 while (timeout) { 1847 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1848 E1000_STATUS_GIO_MASTER_ENABLE)) 1849 break; 1850 usec_delay(100); 1851 timeout--; 1852 } 1853 1854 if (!timeout) { 1855 DEBUGOUT("Master requests are pending.\n"); 1856 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1857 goto out; 1858 } 1859 1860out: 1861 return ret_val; 1862} 1863 1864/** 1865 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1866 * @hw: pointer to the HW structure 1867 * 1868 * Reset the Adaptive Interframe Spacing throttle to default values. 1869 **/ 1870void 1871e1000_reset_adaptive_generic(struct e1000_hw *hw) 1872{ 1873 struct e1000_mac_info *mac = &hw->mac; 1874 1875 DEBUGFUNC("e1000_reset_adaptive_generic"); 1876 1877 if (!mac->adaptive_ifs) { 1878 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1879 goto out; 1880 } 1881 1882 if (!mac->ifs_params_forced) { 1883 mac->current_ifs_val = 0; 1884 mac->ifs_min_val = IFS_MIN; 1885 mac->ifs_max_val = IFS_MAX; 1886 mac->ifs_step_size = IFS_STEP; 1887 mac->ifs_ratio = IFS_RATIO; 1888 } 1889 1890 mac->in_ifs_mode = FALSE; 1891 E1000_WRITE_REG(hw, E1000_AIT, 0); 1892out: 1893 return; 1894} 1895 1896/** 1897 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 1898 * @hw: pointer to the HW structure 1899 * 1900 * Update the Adaptive Interframe Spacing Throttle value based on the 1901 * time between transmitted packets and time between collisions. 1902 **/ 1903void 1904e1000_update_adaptive_generic(struct e1000_hw *hw) 1905{ 1906 struct e1000_mac_info *mac = &hw->mac; 1907 1908 DEBUGFUNC("e1000_update_adaptive_generic"); 1909 1910 if (!mac->adaptive_ifs) { 1911 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1912 goto out; 1913 } 1914 1915 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1916 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1917 mac->in_ifs_mode = TRUE; 1918 if (mac->current_ifs_val < mac->ifs_max_val) { 1919 if (!mac->current_ifs_val) 1920 mac->current_ifs_val = mac->ifs_min_val; 1921 else 1922 mac->current_ifs_val += 1923 mac->ifs_step_size; 1924 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 1925 } 1926 } 1927 } else { 1928 if (mac->in_ifs_mode && 1929 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1930 mac->current_ifs_val = 0; 1931 mac->in_ifs_mode = FALSE; 1932 E1000_WRITE_REG(hw, E1000_AIT, 0); 1933 } 1934 } 1935out: 1936 return; 1937} 1938 1939/** 1940 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 1941 * @hw: pointer to the HW structure 1942 * 1943 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1944 * set, which is forced to MDI mode only. 1945 **/ 1946s32 1947e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 1948{ 1949 s32 ret_val = E1000_SUCCESS; 1950 1951 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 1952 1953 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1954 DEBUGOUT("Invalid MDI setting detected\n"); 1955 hw->phy.mdix = 1; 1956 ret_val = -E1000_ERR_CONFIG; 1957 goto out; 1958 } 1959 1960out: 1961 return ret_val; 1962} 1963 1964/** 1965 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 1966 * @hw: pointer to the HW structure 1967 * @reg: 32bit register offset such as E1000_SCTL 1968 * @offset: register offset to write to 1969 * @data: data to write at register offset 1970 * 1971 * Writes an address/data control type register. There are several of these 1972 * and they all have the format address << 8 | data and bit 31 is polled for 1973 * completion. 1974 **/ 1975s32 1976e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 1977 u32 offset, u8 data) 1978{ 1979 u32 i, regvalue = 0; 1980 s32 ret_val = E1000_SUCCESS; 1981 1982 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 1983 1984 /* Set up the address and data */ 1985 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 1986 E1000_WRITE_REG(hw, reg, regvalue); 1987 1988 /* Poll the ready bit to see if the MDI read completed */ 1989 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 1990 usec_delay(5); 1991 regvalue = E1000_READ_REG(hw, reg); 1992 if (regvalue & E1000_GEN_CTL_READY) 1993 break; 1994 } 1995 if (!(regvalue & E1000_GEN_CTL_READY)) { 1996 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 1997 ret_val = -E1000_ERR_PHY; 1998 goto out; 1999 } 2000 2001out: 2002 return ret_val; 2003} 2004