e1000_ich8lan.h revision 173788 
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33/* $FreeBSD: head/sys/dev/em/e1000_ich8lan.h 173788 2007-11-20 21:41:22Z jfv $ */
34
35
36#ifndef _E1000_ICH8LAN_H_
37#define _E1000_ICH8LAN_H_
38
39#define ICH_FLASH_GFPREG                 0x0000
40#define ICH_FLASH_HSFSTS                 0x0004
41#define ICH_FLASH_HSFCTL                 0x0006
42#define ICH_FLASH_FADDR                  0x0008
43#define ICH_FLASH_FDATA0                 0x0010
44
45#define ICH_FLASH_READ_COMMAND_TIMEOUT   500
46#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  500
47#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  3000000
48#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
49#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
50
51#define ICH_CYCLE_READ                   0
52#define ICH_CYCLE_WRITE                  2
53#define ICH_CYCLE_ERASE                  3
54
55#define FLASH_GFPREG_BASE_MASK           0x1FFF
56#define FLASH_SECTOR_ADDR_SHIFT          12
57
58#define E1000_SHADOW_RAM_WORDS           2048
59
60#define ICH_FLASH_SEG_SIZE_256           256
61#define ICH_FLASH_SEG_SIZE_4K            4096
62#define ICH_FLASH_SEG_SIZE_8K            8192
63#define ICH_FLASH_SEG_SIZE_64K           65536
64#define ICH_FLASH_SECTOR_SIZE            4096
65
66#define ICH_FLASH_REG_MAPSIZE            0x00A0
67
68#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
69#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
70/* FW established a valid mode */
71#define E1000_ICH_FWSM_FW_VALID          0x00008000
72
73#define E1000_ICH_MNG_IAMT_MODE          0x2
74
75#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
76                                 (ID_LED_DEF1_OFF2 <<  8) | \
77                                 (ID_LED_DEF1_ON2  <<  4) | \
78                                 (ID_LED_DEF1_DEF2))
79
80#define E1000_ICH_NVM_SIG_WORD           0x13
81#define E1000_ICH_NVM_SIG_MASK           0xC000
82
83#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
84
85#define E1000_FEXTNVM_SW_CONFIG        1
86#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
87
88#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
89
90#define E1000_ICH_RAR_ENTRIES            7
91
92#define PHY_PAGE_SHIFT 5
93#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
94                           ((reg) & MAX_PHY_REG_ADDRESS))
95#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
96#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
97#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
98#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
99
100#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
101#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
102#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
103#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
104
105/*
106 * Additional interrupts need to be handled for ICH family:
107 *  DSW = The FW changed the status of the DISSW bit in FWSM
108 *  PHYINT = The LAN connected device generates an interrupt
109 *  EPRST = Manageability reset event
110 */
111#define IMS_ICH_ENABLE_MASK (\
112    E1000_IMS_DSW   | \
113    E1000_IMS_PHYINT | \
114    E1000_IMS_EPRST)
115
116
117#endif
118