e1000_ich8lan.h revision 169248 
1/*******************************************************************************
2
3  Copyright (c) 2001-2007, Intel Corporation
4  All rights reserved.
5
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8
9   1. Redistributions of source code must retain the above copyright notice,
10      this list of conditions and the following disclaimer.
11
12   2. Redistributions in binary form must reproduce the above copyright
13      notice, this list of conditions and the following disclaimer in the
14      documentation and/or other materials provided with the distribution.
15
16   3. Neither the name of the Intel Corporation nor the names of its
17      contributors may be used to endorse or promote products derived from
18      this software without specific prior written permission.
19
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33
34/*
35 * $FreeBSD: head/sys/dev/em/e1000_ich8lan.h 169248 2007-05-04 13:30:44Z rwatson $
36 */
37
38
39#ifndef _E1000_ICH8LAN_H_
40#define _E1000_ICH8LAN_H_
41
42#include "e1000_api.h"
43
44#define ICH_FLASH_GFPREG                 0x0000
45#define ICH_FLASH_HSFSTS                 0x0004
46#define ICH_FLASH_HSFCTL                 0x0006
47#define ICH_FLASH_FADDR                  0x0008
48#define ICH_FLASH_FDATA0                 0x0010
49
50#define ICH_FLASH_READ_COMMAND_TIMEOUT   500
51#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  500
52#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  3000000
53#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
54#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
55
56#define ICH_CYCLE_READ                   0
57#define ICH_CYCLE_WRITE                  2
58#define ICH_CYCLE_ERASE                  3
59
60#define FLASH_GFPREG_BASE_MASK           0x1FFF
61#define FLASH_SECTOR_ADDR_SHIFT          12
62
63#define E1000_SHADOW_RAM_WORDS           2048
64
65#define ICH_FLASH_SEG_SIZE_256           256
66#define ICH_FLASH_SEG_SIZE_4K            4096
67#define ICH_FLASH_SEG_SIZE_8K            8192
68#define ICH_FLASH_SEG_SIZE_64K           65536
69#define ICH_FLASH_SECTOR_SIZE            4096
70
71#define ICH_FLASH_REG_MAPSIZE            0x00A0
72
73#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
74#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
75#define E1000_ICH_FWSM_FW_VALID          0x00008000 /* FW established a valid
76                                                     * mode.
77                                                     */
78
79#define E1000_ICH_MNG_IAMT_MODE          0x2
80
81#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
82                                 (ID_LED_DEF1_OFF2 <<  8) | \
83                                 (ID_LED_DEF1_ON2  <<  4) | \
84                                 (ID_LED_DEF1_DEF2))
85
86#define E1000_ICH_NVM_SIG_WORD           0x13
87#define E1000_ICH_NVM_SIG_MASK           0xC000
88
89#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
90
91#define E1000_FEXTNVM_SW_CONFIG        1
92#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
93
94#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
95
96#define E1000_ICH_RAR_ENTRIES            7
97
98#define PHY_PAGE_SHIFT 5
99#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
100                           ((reg) & MAX_PHY_REG_ADDRESS))
101#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
102#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
103#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
104#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
105
106#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
107#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
108#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
109#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
110
111/* Additional interrupts need to be handled for ICH family:
112    DSW = The FW changed the status of the DISSW bit in FWSM
113    PHYINT = The LAN connected device generates an interrupt
114    EPRST = Manageability reset event */
115#define IMS_ICH_ENABLE_MASK (\
116    E1000_IMS_DSW   | \
117    E1000_IMS_PHYINT | \
118    E1000_IMS_EPRST)
119
120#endif
121