e1000_ich8lan.h revision 169240 
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33$FreeBSD: head/sys/dev/em/e1000_ich8lan.h 169240 2007-05-04 00:00:12Z jfv $
34
35
36#ifndef _E1000_ICH8LAN_H_
37#define _E1000_ICH8LAN_H_
38
39#include "e1000_api.h"
40
41#define ICH_FLASH_GFPREG                 0x0000
42#define ICH_FLASH_HSFSTS                 0x0004
43#define ICH_FLASH_HSFCTL                 0x0006
44#define ICH_FLASH_FADDR                  0x0008
45#define ICH_FLASH_FDATA0                 0x0010
46
47#define ICH_FLASH_READ_COMMAND_TIMEOUT   500
48#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  500
49#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  3000000
50#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
51#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
52
53#define ICH_CYCLE_READ                   0
54#define ICH_CYCLE_WRITE                  2
55#define ICH_CYCLE_ERASE                  3
56
57#define FLASH_GFPREG_BASE_MASK           0x1FFF
58#define FLASH_SECTOR_ADDR_SHIFT          12
59
60#define E1000_SHADOW_RAM_WORDS           2048
61
62#define ICH_FLASH_SEG_SIZE_256           256
63#define ICH_FLASH_SEG_SIZE_4K            4096
64#define ICH_FLASH_SEG_SIZE_8K            8192
65#define ICH_FLASH_SEG_SIZE_64K           65536
66#define ICH_FLASH_SECTOR_SIZE            4096
67
68#define ICH_FLASH_REG_MAPSIZE            0x00A0
69
70#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
71#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
72#define E1000_ICH_FWSM_FW_VALID          0x00008000 /* FW established a valid
73                                                     * mode.
74                                                     */
75
76#define E1000_ICH_MNG_IAMT_MODE          0x2
77
78#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
79                                 (ID_LED_DEF1_OFF2 <<  8) | \
80                                 (ID_LED_DEF1_ON2  <<  4) | \
81                                 (ID_LED_DEF1_DEF2))
82
83#define E1000_ICH_NVM_SIG_WORD           0x13
84#define E1000_ICH_NVM_SIG_MASK           0xC000
85
86#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
87
88#define E1000_FEXTNVM_SW_CONFIG        1
89#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
90
91#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
92
93#define E1000_ICH_RAR_ENTRIES            7
94
95#define PHY_PAGE_SHIFT 5
96#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
97                           ((reg) & MAX_PHY_REG_ADDRESS))
98#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
99#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
100#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
101#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
102
103#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
104#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
105#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
106#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
107
108/* Additional interrupts need to be handled for ICH family:
109    DSW = The FW changed the status of the DISSW bit in FWSM
110    PHYINT = The LAN connected device generates an interrupt
111    EPRST = Manageability reset event */
112#define IMS_ICH_ENABLE_MASK (\
113    E1000_IMS_DSW   | \
114    E1000_IMS_PHYINT | \
115    E1000_IMS_EPRST)
116
117#endif
118