e1000_ich8lan.c revision 218588
1177867Sjfv/****************************************************************************** 2169240Sjfv 3203049Sjfv Copyright (c) 2001-2010, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 218588 2011-02-12 00:07:40Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82562G 10/100 Network Connection 37185353Sjfv * 82562G-2 10/100 Network Connection 38185353Sjfv * 82562GT 10/100 Network Connection 39185353Sjfv * 82562GT-2 10/100 Network Connection 40185353Sjfv * 82562V 10/100 Network Connection 41185353Sjfv * 82562V-2 10/100 Network Connection 42185353Sjfv * 82566DC-2 Gigabit Network Connection 43185353Sjfv * 82566DC Gigabit Network Connection 44185353Sjfv * 82566DM-2 Gigabit Network Connection 45185353Sjfv * 82566DM Gigabit Network Connection 46185353Sjfv * 82566MC Gigabit Network Connection 47185353Sjfv * 82566MM Gigabit Network Connection 48185353Sjfv * 82567LM Gigabit Network Connection 49185353Sjfv * 82567LF Gigabit Network Connection 50185353Sjfv * 82567V Gigabit Network Connection 51185353Sjfv * 82567LM-2 Gigabit Network Connection 52185353Sjfv * 82567LF-2 Gigabit Network Connection 53185353Sjfv * 82567V-2 Gigabit Network Connection 54185353Sjfv * 82567LF-3 Gigabit Network Connection 55185353Sjfv * 82567LM-3 Gigabit Network Connection 56185353Sjfv * 82567LM-4 Gigabit Network Connection 57194865Sjfv * 82577LM Gigabit Network Connection 58194865Sjfv * 82577LC Gigabit Network Connection 59194865Sjfv * 82578DM Gigabit Network Connection 60194865Sjfv * 82578DC Gigabit Network Connection 61213234Sjfv * 82579LM Gigabit Network Connection 62213234Sjfv * 82579V Gigabit Network Connection 63169240Sjfv */ 64169240Sjfv 65169589Sjfv#include "e1000_api.h" 66169240Sjfv 67177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 68194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); 69177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 71177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 72177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 73200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 74200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 75177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 76213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 77213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 78218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 79218588Sjfv u8 *mc_addr_list, 80218588Sjfv u32 mc_addr_count); 81177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 82177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 83200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 84177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 85173788Sjfv bool active); 86177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 87173788Sjfv bool active); 88177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 89173788Sjfv u16 words, u16 *data); 90177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 91173788Sjfv u16 words, u16 *data); 92177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 93177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 94177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 95173788Sjfv u16 *data); 96194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 97177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 98177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 99177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 100177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 101177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 102177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 103173788Sjfv u16 *speed, u16 *duplex); 104177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 105177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 106177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 107200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 108194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 109194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 110194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 111194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 112177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 113177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 114173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 115173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 116173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 117173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 118178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 119185353Sjfv u32 offset, u8 *data); 120173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 121185353Sjfv u8 size, u16 *data); 122177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 123173788Sjfv u32 offset, u16 *data); 124173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 125173788Sjfv u32 offset, u8 byte); 126177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 127173788Sjfv u32 offset, u8 data); 128173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 129173788Sjfv u8 size, u16 data); 130177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 131177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 132200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 133200243Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 134200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 135203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 136213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 137213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 138169240Sjfv 139169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 140169240Sjfv/* Offset 04h HSFSTS */ 141169240Sjfvunion ich8_hws_flash_status { 142169240Sjfv struct ich8_hsfsts { 143169240Sjfv u16 flcdone :1; /* bit 0 Flash Cycle Done */ 144169240Sjfv u16 flcerr :1; /* bit 1 Flash Cycle Error */ 145169240Sjfv u16 dael :1; /* bit 2 Direct Access error Log */ 146169240Sjfv u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 147169240Sjfv u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 148169240Sjfv u16 reserved1 :2; /* bit 13:6 Reserved */ 149169240Sjfv u16 reserved2 :6; /* bit 13:6 Reserved */ 150169240Sjfv u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 151169240Sjfv u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 152169240Sjfv } hsf_status; 153169240Sjfv u16 regval; 154169240Sjfv}; 155169240Sjfv 156169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 157169240Sjfv/* Offset 06h FLCTL */ 158169240Sjfvunion ich8_hws_flash_ctrl { 159169240Sjfv struct ich8_hsflctl { 160169240Sjfv u16 flcgo :1; /* 0 Flash Cycle Go */ 161169240Sjfv u16 flcycle :2; /* 2:1 Flash Cycle */ 162169240Sjfv u16 reserved :5; /* 7:3 Reserved */ 163169240Sjfv u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 164169240Sjfv u16 flockdn :6; /* 15:10 Reserved */ 165169240Sjfv } hsf_ctrl; 166169240Sjfv u16 regval; 167169240Sjfv}; 168169240Sjfv 169169240Sjfv/* ICH Flash Region Access Permissions */ 170169240Sjfvunion ich8_hws_flash_regacc { 171169240Sjfv struct ich8_flracc { 172169240Sjfv u32 grra :8; /* 0:7 GbE region Read Access */ 173169240Sjfv u32 grwa :8; /* 8:15 GbE region Write Access */ 174169240Sjfv u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 175169240Sjfv u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 176169240Sjfv } hsf_flregacc; 177169240Sjfv u16 regval; 178169240Sjfv}; 179169240Sjfv 180169240Sjfv/** 181194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 182194865Sjfv * @hw: pointer to the HW structure 183194865Sjfv * 184194865Sjfv * Initialize family-specific PHY parameters and function pointers. 185194865Sjfv **/ 186194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 187194865Sjfv{ 188194865Sjfv struct e1000_phy_info *phy = &hw->phy; 189213234Sjfv u32 ctrl, fwsm; 190194865Sjfv s32 ret_val = E1000_SUCCESS; 191194865Sjfv 192194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 193194865Sjfv 194194865Sjfv phy->addr = 1; 195194865Sjfv phy->reset_delay_us = 100; 196194865Sjfv 197194865Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 198194865Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 199194865Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 200194865Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 201200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 202194865Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 203194865Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 204200243Sjfv phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 205200243Sjfv phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 206194865Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 207200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 208194865Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 209194865Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 210194865Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 211194865Sjfv 212213234Sjfv /* 213213234Sjfv * The MAC-PHY interconnect may still be in SMBus mode 214213234Sjfv * after Sx->S0. If the manageability engine (ME) is 215213234Sjfv * disabled, then toggle the LANPHYPC Value bit to force 216213234Sjfv * the interconnect to PCIe mode. 217213234Sjfv */ 218213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 219218588Sjfv if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && 220218588Sjfv !(hw->phy.ops.check_reset_block(hw))) { 221205869Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 222205869Sjfv ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 223205869Sjfv ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 224205869Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 225205869Sjfv usec_delay(10); 226205869Sjfv ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 227205869Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 228205869Sjfv msec_delay(50); 229213234Sjfv 230213234Sjfv /* 231213234Sjfv * Gate automatic PHY configuration by hardware on 232213234Sjfv * non-managed 82579 233213234Sjfv */ 234213234Sjfv if (hw->mac.type == e1000_pch2lan) 235213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 236205869Sjfv } 237205869Sjfv 238205869Sjfv /* 239205869Sjfv * Reset the PHY before any acccess to it. Doing so, ensures that 240205869Sjfv * the PHY is in a known good state before we read/write PHY registers. 241205869Sjfv * The generic reset is sufficient here, because we haven't determined 242205869Sjfv * the PHY type yet. 243205869Sjfv */ 244205869Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 245205869Sjfv if (ret_val) 246205869Sjfv goto out; 247205869Sjfv 248213234Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 249213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 250213234Sjfv !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 251213234Sjfv msec_delay(10); 252213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 253213234Sjfv } 254213234Sjfv 255194865Sjfv phy->id = e1000_phy_unknown; 256213234Sjfv switch (hw->mac.type) { 257213234Sjfv default: 258213234Sjfv ret_val = e1000_get_phy_id(hw); 259213234Sjfv if (ret_val) 260213234Sjfv goto out; 261213234Sjfv if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 262213234Sjfv break; 263213234Sjfv /* fall-through */ 264213234Sjfv case e1000_pch2lan: 265203049Sjfv /* 266213234Sjfv * In case the PHY needs to be in mdio slow mode, 267203049Sjfv * set slow mode and try to get the PHY id again. 268203049Sjfv */ 269203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 270203049Sjfv if (ret_val) 271203049Sjfv goto out; 272203049Sjfv ret_val = e1000_get_phy_id(hw); 273203049Sjfv if (ret_val) 274203049Sjfv goto out; 275213234Sjfv break; 276203049Sjfv } 277194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 278194865Sjfv 279200243Sjfv switch (phy->type) { 280200243Sjfv case e1000_phy_82577: 281213234Sjfv case e1000_phy_82579: 282194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 283194865Sjfv phy->ops.force_speed_duplex = 284194865Sjfv e1000_phy_force_speed_duplex_82577; 285200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 286194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 287194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 288205869Sjfv break; 289200243Sjfv case e1000_phy_82578: 290200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 291200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 292200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 293200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 294200243Sjfv break; 295200243Sjfv default: 296200243Sjfv ret_val = -E1000_ERR_PHY; 297200243Sjfv break; 298194865Sjfv } 299194865Sjfv 300203049Sjfvout: 301194865Sjfv return ret_val; 302194865Sjfv} 303194865Sjfv 304194865Sjfv/** 305169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 306169589Sjfv * @hw: pointer to the HW structure 307169240Sjfv * 308169240Sjfv * Initialize family-specific PHY parameters and function pointers. 309169240Sjfv **/ 310177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 311169240Sjfv{ 312169240Sjfv struct e1000_phy_info *phy = &hw->phy; 313169240Sjfv s32 ret_val = E1000_SUCCESS; 314169589Sjfv u16 i = 0; 315169240Sjfv 316169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 317169240Sjfv 318177867Sjfv phy->addr = 1; 319177867Sjfv phy->reset_delay_us = 100; 320169240Sjfv 321177867Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 322177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 323177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 324177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 325177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 326177867Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 327177867Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 328177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 329177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 330177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 331177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 332177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 333169240Sjfv 334176667Sjfv /* 335176667Sjfv * We may need to do this twice - once for IGP and if that fails, 336176667Sjfv * we'll set BM func pointers and try again 337176667Sjfv */ 338176667Sjfv ret_val = e1000_determine_phy_address(hw); 339176667Sjfv if (ret_val) { 340177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 341177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 342176667Sjfv ret_val = e1000_determine_phy_address(hw); 343176667Sjfv if (ret_val) { 344190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 345176667Sjfv goto out; 346176667Sjfv } 347176667Sjfv } 348169240Sjfv 349169589Sjfv phy->id = 0; 350169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 351169589Sjfv (i++ < 100)) { 352169589Sjfv msec_delay(1); 353169589Sjfv ret_val = e1000_get_phy_id(hw); 354169589Sjfv if (ret_val) 355169589Sjfv goto out; 356169589Sjfv } 357169589Sjfv 358169240Sjfv /* Verify phy id */ 359169240Sjfv switch (phy->id) { 360169240Sjfv case IGP03E1000_E_PHY_ID: 361169240Sjfv phy->type = e1000_phy_igp_3; 362169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 363200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 364200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 365200243Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 366200243Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 367200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 368169240Sjfv break; 369169240Sjfv case IFE_E_PHY_ID: 370169240Sjfv case IFE_PLUS_E_PHY_ID: 371169240Sjfv case IFE_C_E_PHY_ID: 372169240Sjfv phy->type = e1000_phy_ife; 373169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 374200243Sjfv phy->ops.get_info = e1000_get_phy_info_ife; 375200243Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 376200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 377169240Sjfv break; 378176667Sjfv case BME1000_E_PHY_ID: 379176667Sjfv phy->type = e1000_phy_bm; 380176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 381177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 382177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 383177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 384200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 385200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 386200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 387176667Sjfv break; 388169240Sjfv default: 389169240Sjfv ret_val = -E1000_ERR_PHY; 390169240Sjfv goto out; 391169240Sjfv } 392169240Sjfv 393169240Sjfvout: 394169240Sjfv return ret_val; 395169240Sjfv} 396169240Sjfv 397169240Sjfv/** 398169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 399169589Sjfv * @hw: pointer to the HW structure 400169240Sjfv * 401169240Sjfv * Initialize family-specific NVM parameters and function 402169240Sjfv * pointers. 403169240Sjfv **/ 404177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 405169240Sjfv{ 406169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 407185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 408169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 409173788Sjfv s32 ret_val = E1000_SUCCESS; 410169240Sjfv u16 i; 411169240Sjfv 412169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 413169240Sjfv 414173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 415169240Sjfv if (!hw->flash_address) { 416169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 417169240Sjfv ret_val = -E1000_ERR_CONFIG; 418169240Sjfv goto out; 419169240Sjfv } 420169240Sjfv 421185353Sjfv nvm->type = e1000_nvm_flash_sw; 422169240Sjfv 423169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 424169240Sjfv 425173788Sjfv /* 426173788Sjfv * sector_X_addr is a "sector"-aligned address (4096 bytes) 427169240Sjfv * Add 1 to sector_end_addr since this sector is included in 428173788Sjfv * the overall size. 429173788Sjfv */ 430169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 431169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 432169240Sjfv 433169240Sjfv /* flash_base_addr is byte-aligned */ 434185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 435169240Sjfv 436173788Sjfv /* 437173788Sjfv * find total size of the NVM, then cut in half since the total 438173788Sjfv * size represents two separate NVM banks. 439173788Sjfv */ 440185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 441169240Sjfv << FLASH_SECTOR_ADDR_SHIFT; 442185353Sjfv nvm->flash_bank_size /= 2; 443169240Sjfv /* Adjust to word count */ 444185353Sjfv nvm->flash_bank_size /= sizeof(u16); 445169240Sjfv 446185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 447169240Sjfv 448169240Sjfv /* Clear shadow ram */ 449169240Sjfv for (i = 0; i < nvm->word_size; i++) { 450169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 451169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 452169240Sjfv } 453169240Sjfv 454200243Sjfv E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 455200243Sjfv E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 456200243Sjfv 457169240Sjfv /* Function Pointers */ 458200243Sjfv nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 459200243Sjfv nvm->ops.release = e1000_release_nvm_ich8lan; 460177867Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 461177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 462177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 463177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 464177867Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 465169240Sjfv 466169240Sjfvout: 467169240Sjfv return ret_val; 468169240Sjfv} 469169240Sjfv 470169240Sjfv/** 471169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 472169589Sjfv * @hw: pointer to the HW structure 473169240Sjfv * 474169240Sjfv * Initialize family-specific MAC parameters and function 475169240Sjfv * pointers. 476169240Sjfv **/ 477177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 478169240Sjfv{ 479169240Sjfv struct e1000_mac_info *mac = &hw->mac; 480190872Sjfv u16 pci_cfg; 481169240Sjfv 482169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 483169240Sjfv 484169240Sjfv /* Set media type function pointer */ 485173788Sjfv hw->phy.media_type = e1000_media_type_copper; 486169240Sjfv 487169240Sjfv /* Set mta register count */ 488169240Sjfv mac->mta_reg_count = 32; 489169240Sjfv /* Set rar entry count */ 490169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 491169240Sjfv if (mac->type == e1000_ich8lan) 492169240Sjfv mac->rar_entry_count--; 493169240Sjfv /* Set if part includes ASF firmware */ 494169240Sjfv mac->asf_firmware_present = TRUE; 495205869Sjfv /* FWSM register */ 496205869Sjfv mac->has_fwsm = TRUE; 497205869Sjfv /* ARC subsystem not supported */ 498205869Sjfv mac->arc_subsystem_valid = FALSE; 499200243Sjfv /* Adaptive IFS supported */ 500200243Sjfv mac->adaptive_ifs = TRUE; 501169240Sjfv 502169240Sjfv /* Function pointers */ 503169240Sjfv 504169240Sjfv /* bus type/speed/width */ 505177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 506185353Sjfv /* function id */ 507185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 508169240Sjfv /* reset */ 509177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 510169240Sjfv /* hw initialization */ 511177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 512169240Sjfv /* link setup */ 513177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 514169240Sjfv /* physical interface setup */ 515177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 516169240Sjfv /* check for link */ 517200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 518169240Sjfv /* link info */ 519177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 520169240Sjfv /* multicast address update */ 521177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 522169240Sjfv /* clear hardware counters */ 523177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 524169240Sjfv 525190872Sjfv /* LED operations */ 526190872Sjfv switch (mac->type) { 527190872Sjfv case e1000_ich8lan: 528190872Sjfv case e1000_ich9lan: 529190872Sjfv case e1000_ich10lan: 530213234Sjfv /* check management mode */ 531213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 532190872Sjfv /* ID LED init */ 533190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 534190872Sjfv /* blink LED */ 535190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 536190872Sjfv /* setup LED */ 537190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 538190872Sjfv /* cleanup LED */ 539190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 540190872Sjfv /* turn on/off LED */ 541190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 542190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 543190872Sjfv break; 544213234Sjfv case e1000_pch2lan: 545213234Sjfv mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 546213234Sjfv mac->ops.rar_set = e1000_rar_set_pch2lan; 547218588Sjfv /* multicast address update for pch2 */ 548218588Sjfv mac->ops.update_mc_addr_list = 549218588Sjfv e1000_update_mc_addr_list_pch2lan; 550213234Sjfv /* fall-through */ 551194865Sjfv case e1000_pchlan: 552194865Sjfv /* save PCH revision_id */ 553194865Sjfv e1000_read_pci_cfg(hw, 0x2, &pci_cfg); 554194865Sjfv hw->revision_id = (u8)(pci_cfg &= 0x000F); 555213234Sjfv /* check management mode */ 556213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 557194865Sjfv /* ID LED init */ 558194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 559194865Sjfv /* setup LED */ 560194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 561194865Sjfv /* cleanup LED */ 562194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 563194865Sjfv /* turn on/off LED */ 564194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 565194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 566194865Sjfv break; 567190872Sjfv default: 568190872Sjfv break; 569190872Sjfv } 570190872Sjfv 571169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 572169240Sjfv if (mac->type == e1000_ich8lan) 573169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 574169240Sjfv 575213234Sjfv /* Gate automatic PHY configuration by hardware on managed 82579 */ 576213234Sjfv if ((mac->type == e1000_pch2lan) && 577213234Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 578213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 579213234Sjfv 580185353Sjfv return E1000_SUCCESS; 581169240Sjfv} 582169240Sjfv 583169240Sjfv/** 584213234Sjfv * e1000_set_eee_pchlan - Enable/disable EEE support 585213234Sjfv * @hw: pointer to the HW structure 586213234Sjfv * 587213234Sjfv * Enable/disable EEE based on setting in dev_spec structure. The bits in 588213234Sjfv * the LPI Control register will remain set only if/when link is up. 589213234Sjfv **/ 590213234Sjfvstatic s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 591213234Sjfv{ 592213234Sjfv s32 ret_val = E1000_SUCCESS; 593213234Sjfv u16 phy_reg; 594213234Sjfv 595213234Sjfv DEBUGFUNC("e1000_set_eee_pchlan"); 596213234Sjfv 597213234Sjfv if (hw->phy.type != e1000_phy_82579) 598213234Sjfv goto out; 599213234Sjfv 600213234Sjfv ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); 601213234Sjfv if (ret_val) 602213234Sjfv goto out; 603213234Sjfv 604213234Sjfv if (hw->dev_spec.ich8lan.eee_disable) 605213234Sjfv phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 606213234Sjfv else 607213234Sjfv phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 608213234Sjfv 609213234Sjfv ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); 610213234Sjfvout: 611213234Sjfv return ret_val; 612213234Sjfv} 613213234Sjfv 614213234Sjfv/** 615200243Sjfv * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 616200243Sjfv * @hw: pointer to the HW structure 617200243Sjfv * 618200243Sjfv * Checks to see of the link status of the hardware has changed. If a 619200243Sjfv * change in link status has been detected, then we read the PHY registers 620200243Sjfv * to get the current speed/duplex if link exists. 621200243Sjfv **/ 622200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 623200243Sjfv{ 624200243Sjfv struct e1000_mac_info *mac = &hw->mac; 625200243Sjfv s32 ret_val; 626200243Sjfv bool link; 627200243Sjfv 628200243Sjfv DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 629200243Sjfv 630200243Sjfv /* 631200243Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 632200243Sjfv * has completed and/or if our link status has changed. The 633200243Sjfv * get_link_status flag is set upon receiving a Link Status 634200243Sjfv * Change or Rx Sequence Error interrupt. 635200243Sjfv */ 636200243Sjfv if (!mac->get_link_status) { 637200243Sjfv ret_val = E1000_SUCCESS; 638200243Sjfv goto out; 639200243Sjfv } 640200243Sjfv 641200243Sjfv /* 642200243Sjfv * First we want to see if the MII Status Register reports 643200243Sjfv * link. If so, then we want to get the current speed/duplex 644200243Sjfv * of the PHY. 645200243Sjfv */ 646200243Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 647200243Sjfv if (ret_val) 648200243Sjfv goto out; 649200243Sjfv 650200243Sjfv if (hw->mac.type == e1000_pchlan) { 651200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, link); 652200243Sjfv if (ret_val) 653200243Sjfv goto out; 654200243Sjfv } 655200243Sjfv 656200243Sjfv if (!link) 657200243Sjfv goto out; /* No link detected */ 658200243Sjfv 659200243Sjfv mac->get_link_status = FALSE; 660200243Sjfv 661200243Sjfv if (hw->phy.type == e1000_phy_82578) { 662200243Sjfv ret_val = e1000_link_stall_workaround_hv(hw); 663200243Sjfv if (ret_val) 664200243Sjfv goto out; 665200243Sjfv } 666200243Sjfv 667213234Sjfv if (hw->mac.type == e1000_pch2lan) { 668213234Sjfv ret_val = e1000_k1_workaround_lv(hw); 669213234Sjfv if (ret_val) 670213234Sjfv goto out; 671213234Sjfv } 672213234Sjfv 673200243Sjfv /* 674200243Sjfv * Check if there was DownShift, must be checked 675200243Sjfv * immediately after link-up 676200243Sjfv */ 677200243Sjfv e1000_check_downshift_generic(hw); 678200243Sjfv 679213234Sjfv /* Enable/Disable EEE after link up */ 680213234Sjfv ret_val = e1000_set_eee_pchlan(hw); 681213234Sjfv if (ret_val) 682213234Sjfv goto out; 683213234Sjfv 684200243Sjfv /* 685200243Sjfv * If we are forcing speed/duplex, then we simply return since 686200243Sjfv * we have already determined whether we have link or not. 687200243Sjfv */ 688200243Sjfv if (!mac->autoneg) { 689200243Sjfv ret_val = -E1000_ERR_CONFIG; 690200243Sjfv goto out; 691200243Sjfv } 692200243Sjfv 693200243Sjfv /* 694200243Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 695200243Sjfv * of MAC speed/duplex configuration. So we only need to 696200243Sjfv * configure Collision Distance in the MAC. 697200243Sjfv */ 698200243Sjfv e1000_config_collision_dist_generic(hw); 699200243Sjfv 700200243Sjfv /* 701200243Sjfv * Configure Flow Control now that Auto-Neg has completed. 702200243Sjfv * First, we need to restore the desired flow control 703200243Sjfv * settings because we may have had to re-autoneg with a 704200243Sjfv * different link partner. 705200243Sjfv */ 706200243Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 707200243Sjfv if (ret_val) 708200243Sjfv DEBUGOUT("Error configuring flow control\n"); 709200243Sjfv 710200243Sjfvout: 711200243Sjfv return ret_val; 712200243Sjfv} 713200243Sjfv 714200243Sjfv/** 715169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 716169589Sjfv * @hw: pointer to the HW structure 717169240Sjfv * 718169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 719169240Sjfv **/ 720173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 721169240Sjfv{ 722169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 723169240Sjfv 724177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 725177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 726194865Sjfv switch (hw->mac.type) { 727194865Sjfv case e1000_ich8lan: 728194865Sjfv case e1000_ich9lan: 729194865Sjfv case e1000_ich10lan: 730194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 731194865Sjfv break; 732194865Sjfv case e1000_pchlan: 733213234Sjfv case e1000_pch2lan: 734194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 735194865Sjfv break; 736194865Sjfv default: 737194865Sjfv break; 738194865Sjfv } 739169240Sjfv} 740169240Sjfv 741169240Sjfv/** 742200243Sjfv * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 743200243Sjfv * @hw: pointer to the HW structure 744200243Sjfv * 745200243Sjfv * Acquires the mutex for performing NVM operations. 746200243Sjfv **/ 747200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 748200243Sjfv{ 749200243Sjfv DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 750200243Sjfv 751200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 752200243Sjfv 753200243Sjfv return E1000_SUCCESS; 754200243Sjfv} 755200243Sjfv 756200243Sjfv/** 757200243Sjfv * e1000_release_nvm_ich8lan - Release NVM mutex 758200243Sjfv * @hw: pointer to the HW structure 759200243Sjfv * 760200243Sjfv * Releases the mutex used while performing NVM operations. 761200243Sjfv **/ 762200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 763200243Sjfv{ 764200243Sjfv DEBUGFUNC("e1000_release_nvm_ich8lan"); 765200243Sjfv 766200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 767200243Sjfv 768200243Sjfv return; 769200243Sjfv} 770200243Sjfv 771200243Sjfv/** 772169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 773169589Sjfv * @hw: pointer to the HW structure 774169240Sjfv * 775200243Sjfv * Acquires the software control flag for performing PHY and select 776200243Sjfv * MAC CSR accesses. 777169240Sjfv **/ 778177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 779169240Sjfv{ 780169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 781169240Sjfv s32 ret_val = E1000_SUCCESS; 782169240Sjfv 783169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 784169240Sjfv 785200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 786200243Sjfv 787169240Sjfv while (timeout) { 788169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 789200243Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 790200243Sjfv break; 791169240Sjfv 792200243Sjfv msec_delay_irq(1); 793200243Sjfv timeout--; 794200243Sjfv } 795194865Sjfv 796200243Sjfv if (!timeout) { 797200243Sjfv DEBUGOUT("SW/FW/HW has locked the resource for too long.\n"); 798200243Sjfv ret_val = -E1000_ERR_CONFIG; 799200243Sjfv goto out; 800200243Sjfv } 801200243Sjfv 802200243Sjfv timeout = SW_FLAG_TIMEOUT; 803200243Sjfv 804200243Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 805200243Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 806200243Sjfv 807200243Sjfv while (timeout) { 808200243Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 809200243Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 810200243Sjfv break; 811200243Sjfv 812169240Sjfv msec_delay_irq(1); 813169240Sjfv timeout--; 814169240Sjfv } 815169240Sjfv 816169240Sjfv if (!timeout) { 817200243Sjfv DEBUGOUT("Failed to acquire the semaphore.\n"); 818173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 819173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 820169240Sjfv ret_val = -E1000_ERR_CONFIG; 821169240Sjfv goto out; 822169240Sjfv } 823169240Sjfv 824169240Sjfvout: 825200243Sjfv if (ret_val) 826200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 827200243Sjfv 828169240Sjfv return ret_val; 829169240Sjfv} 830169240Sjfv 831169240Sjfv/** 832169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 833169589Sjfv * @hw: pointer to the HW structure 834169240Sjfv * 835200243Sjfv * Releases the software control flag for performing PHY and select 836200243Sjfv * MAC CSR accesses. 837169240Sjfv **/ 838177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 839169240Sjfv{ 840169240Sjfv u32 extcnf_ctrl; 841169240Sjfv 842169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 843169240Sjfv 844169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 845169240Sjfv 846218588Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 847218588Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 848218588Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 849218588Sjfv } else { 850218588Sjfv DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 851218588Sjfv } 852218588Sjfv 853200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 854200243Sjfv 855169240Sjfv return; 856169240Sjfv} 857169240Sjfv 858169240Sjfv/** 859169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 860169589Sjfv * @hw: pointer to the HW structure 861169240Sjfv * 862213234Sjfv * This checks if the adapter has any manageability enabled. 863169240Sjfv * This is a function pointer entry point only called by read/write 864169240Sjfv * routines for the PHY and NVM parts. 865169240Sjfv **/ 866177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 867169240Sjfv{ 868169240Sjfv u32 fwsm; 869169240Sjfv 870169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 871169240Sjfv 872169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 873169240Sjfv 874213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 875213234Sjfv ((fwsm & E1000_FWSM_MODE_MASK) == 876213234Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 877169240Sjfv} 878169240Sjfv 879169240Sjfv/** 880213234Sjfv * e1000_check_mng_mode_pchlan - Checks management mode 881213234Sjfv * @hw: pointer to the HW structure 882213234Sjfv * 883213234Sjfv * This checks if the adapter has iAMT enabled. 884213234Sjfv * This is a function pointer entry point only called by read/write 885213234Sjfv * routines for the PHY and NVM parts. 886213234Sjfv **/ 887213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 888213234Sjfv{ 889213234Sjfv u32 fwsm; 890213234Sjfv 891213234Sjfv DEBUGFUNC("e1000_check_mng_mode_pchlan"); 892213234Sjfv 893213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 894213234Sjfv 895213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 896213234Sjfv (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 897213234Sjfv} 898213234Sjfv 899213234Sjfv/** 900213234Sjfv * e1000_rar_set_pch2lan - Set receive address register 901213234Sjfv * @hw: pointer to the HW structure 902213234Sjfv * @addr: pointer to the receive address 903213234Sjfv * @index: receive address array register 904213234Sjfv * 905213234Sjfv * Sets the receive address array register at index to the address passed 906213234Sjfv * in by addr. For 82579, RAR[0] is the base address register that is to 907213234Sjfv * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 908213234Sjfv * Use SHRA[0-3] in place of those reserved for ME. 909213234Sjfv **/ 910213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 911213234Sjfv{ 912213234Sjfv u32 rar_low, rar_high; 913213234Sjfv 914213234Sjfv DEBUGFUNC("e1000_rar_set_pch2lan"); 915213234Sjfv 916213234Sjfv /* 917213234Sjfv * HW expects these in little endian so we reverse the byte order 918213234Sjfv * from network order (big endian) to little endian 919213234Sjfv */ 920213234Sjfv rar_low = ((u32) addr[0] | 921213234Sjfv ((u32) addr[1] << 8) | 922213234Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 923213234Sjfv 924213234Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 925213234Sjfv 926213234Sjfv /* If MAC address zero, no need to set the AV bit */ 927213234Sjfv if (rar_low || rar_high) 928213234Sjfv rar_high |= E1000_RAH_AV; 929213234Sjfv 930213234Sjfv if (index == 0) { 931213234Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 932213234Sjfv E1000_WRITE_FLUSH(hw); 933213234Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 934213234Sjfv E1000_WRITE_FLUSH(hw); 935213234Sjfv return; 936213234Sjfv } 937213234Sjfv 938213234Sjfv if (index < hw->mac.rar_entry_count) { 939213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 940213234Sjfv E1000_WRITE_FLUSH(hw); 941213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 942213234Sjfv E1000_WRITE_FLUSH(hw); 943213234Sjfv 944213234Sjfv /* verify the register updates */ 945213234Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 946213234Sjfv (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 947213234Sjfv return; 948213234Sjfv 949213234Sjfv DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 950213234Sjfv (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 951213234Sjfv } 952213234Sjfv 953213234Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 954213234Sjfv} 955213234Sjfv 956213234Sjfv/** 957218588Sjfv * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 958218588Sjfv * @hw: pointer to the HW structure 959218588Sjfv * @mc_addr_list: array of multicast addresses to program 960218588Sjfv * @mc_addr_count: number of multicast addresses to program 961218588Sjfv * 962218588Sjfv * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 963218588Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 964218588Sjfv **/ 965218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 966218588Sjfv u8 *mc_addr_list, 967218588Sjfv u32 mc_addr_count) 968218588Sjfv{ 969218588Sjfv int i; 970218588Sjfv 971218588Sjfv DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 972218588Sjfv 973218588Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 974218588Sjfv 975218588Sjfv for (i = 0; i < hw->mac.mta_reg_count; i++) { 976218588Sjfv hw->phy.ops.write_reg(hw, BM_MTA(i), 977218588Sjfv (u16)(hw->mac.mta_shadow[i] & 0xFFFF)); 978218588Sjfv hw->phy.ops.write_reg(hw, (BM_MTA(i) + 1), 979218588Sjfv (u16)((hw->mac.mta_shadow[i] >> 16) & 980218588Sjfv 0xFFFF)); 981218588Sjfv } 982218588Sjfv} 983218588Sjfv 984218588Sjfv/** 985169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 986169589Sjfv * @hw: pointer to the HW structure 987169240Sjfv * 988169240Sjfv * Checks if firmware is blocking the reset of the PHY. 989169240Sjfv * This is a function pointer entry point only called by 990169240Sjfv * reset routines. 991169240Sjfv **/ 992177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 993169240Sjfv{ 994169240Sjfv u32 fwsm; 995169240Sjfv 996169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 997169240Sjfv 998205869Sjfv if (hw->phy.reset_disable) 999205869Sjfv return E1000_BLK_PHY_RESET; 1000205869Sjfv 1001169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1002169240Sjfv 1003169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 1004169240Sjfv : E1000_BLK_PHY_RESET; 1005169240Sjfv} 1006169240Sjfv 1007169240Sjfv/** 1008213234Sjfv * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 1009213234Sjfv * @hw: pointer to the HW structure 1010213234Sjfv * 1011213234Sjfv * Assumes semaphore already acquired. 1012213234Sjfv * 1013213234Sjfv **/ 1014213234Sjfvstatic s32 e1000_write_smbus_addr(struct e1000_hw *hw) 1015213234Sjfv{ 1016213234Sjfv u16 phy_data; 1017213234Sjfv u32 strap = E1000_READ_REG(hw, E1000_STRAP); 1018213234Sjfv s32 ret_val = E1000_SUCCESS; 1019213234Sjfv 1020213234Sjfv strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 1021213234Sjfv 1022213234Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1023213234Sjfv if (ret_val) 1024213234Sjfv goto out; 1025213234Sjfv 1026213234Sjfv phy_data &= ~HV_SMB_ADDR_MASK; 1027213234Sjfv phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1028213234Sjfv phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1029213234Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 1030213234Sjfv 1031213234Sjfvout: 1032213234Sjfv return ret_val; 1033213234Sjfv} 1034213234Sjfv 1035213234Sjfv/** 1036200243Sjfv * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 1037200243Sjfv * @hw: pointer to the HW structure 1038200243Sjfv * 1039200243Sjfv * SW should configure the LCD from the NVM extended configuration region 1040200243Sjfv * as a workaround for certain parts. 1041200243Sjfv **/ 1042200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1043200243Sjfv{ 1044200243Sjfv struct e1000_phy_info *phy = &hw->phy; 1045200243Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1046203049Sjfv s32 ret_val = E1000_SUCCESS; 1047200243Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 1048200243Sjfv 1049213234Sjfv DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 1050203049Sjfv 1051200243Sjfv /* 1052200243Sjfv * Initialize the PHY from the NVM on ICH platforms. This 1053200243Sjfv * is needed due to an issue where the NVM configuration is 1054200243Sjfv * not properly autoloaded after power transitions. 1055200243Sjfv * Therefore, after each PHY reset, we will load the 1056200243Sjfv * configuration data out of the NVM manually. 1057200243Sjfv */ 1058213234Sjfv switch (hw->mac.type) { 1059213234Sjfv case e1000_ich8lan: 1060213234Sjfv if (phy->type != e1000_phy_igp_3) 1061213234Sjfv return ret_val; 1062213234Sjfv 1063213234Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 1064213234Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 1065213234Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1066213234Sjfv break; 1067213234Sjfv } 1068213234Sjfv /* Fall-thru */ 1069213234Sjfv case e1000_pchlan: 1070213234Sjfv case e1000_pch2lan: 1071203049Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1072213234Sjfv break; 1073213234Sjfv default: 1074213234Sjfv return ret_val; 1075213234Sjfv } 1076200243Sjfv 1077213234Sjfv ret_val = hw->phy.ops.acquire(hw); 1078213234Sjfv if (ret_val) 1079213234Sjfv return ret_val; 1080213234Sjfv 1081203049Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 1082203049Sjfv if (!(data & sw_cfg_mask)) 1083203049Sjfv goto out; 1084200243Sjfv 1085203049Sjfv /* 1086203049Sjfv * Make sure HW does not configure LCD from PHY 1087203049Sjfv * extended configuration before SW configuration 1088203049Sjfv */ 1089203049Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1090213234Sjfv if (!(hw->mac.type == e1000_pch2lan)) { 1091213234Sjfv if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 1092213234Sjfv goto out; 1093213234Sjfv } 1094203049Sjfv 1095203049Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 1096203049Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1097203049Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1098203049Sjfv if (!cnf_size) 1099203049Sjfv goto out; 1100203049Sjfv 1101203049Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1102203049Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1103203049Sjfv 1104213234Sjfv if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && 1105213234Sjfv (hw->mac.type == e1000_pchlan)) || 1106213234Sjfv (hw->mac.type == e1000_pch2lan)) { 1107200243Sjfv /* 1108203049Sjfv * HW configures the SMBus address and LEDs when the 1109203049Sjfv * OEM and LCD Write Enable bits are set in the NVM. 1110203049Sjfv * When both NVM bits are cleared, SW will configure 1111203049Sjfv * them instead. 1112200243Sjfv */ 1113213234Sjfv ret_val = e1000_write_smbus_addr(hw); 1114203049Sjfv if (ret_val) 1115200243Sjfv goto out; 1116200243Sjfv 1117203049Sjfv data = E1000_READ_REG(hw, E1000_LEDCTL); 1118203049Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1119203049Sjfv (u16)data); 1120203049Sjfv if (ret_val) 1121200243Sjfv goto out; 1122203049Sjfv } 1123200243Sjfv 1124203049Sjfv /* Configure LCD from extended configuration region. */ 1125200243Sjfv 1126203049Sjfv /* cnf_base_addr is in DWORD */ 1127203049Sjfv word_addr = (u16)(cnf_base_addr << 1); 1128200243Sjfv 1129203049Sjfv for (i = 0; i < cnf_size; i++) { 1130203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 1131203049Sjfv ®_data); 1132203049Sjfv if (ret_val) 1133203049Sjfv goto out; 1134200243Sjfv 1135203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 1136203049Sjfv 1, ®_addr); 1137203049Sjfv if (ret_val) 1138203049Sjfv goto out; 1139200243Sjfv 1140203049Sjfv /* Save off the PHY page for future writes. */ 1141203049Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1142203049Sjfv phy_page = reg_data; 1143203049Sjfv continue; 1144203049Sjfv } 1145200243Sjfv 1146203049Sjfv reg_addr &= PHY_REG_MASK; 1147203049Sjfv reg_addr |= phy_page; 1148200243Sjfv 1149203049Sjfv ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 1150203049Sjfv reg_data); 1151203049Sjfv if (ret_val) 1152203049Sjfv goto out; 1153200243Sjfv } 1154200243Sjfv 1155200243Sjfvout: 1156200243Sjfv hw->phy.ops.release(hw); 1157200243Sjfv return ret_val; 1158200243Sjfv} 1159200243Sjfv 1160200243Sjfv/** 1161200243Sjfv * e1000_k1_gig_workaround_hv - K1 Si workaround 1162200243Sjfv * @hw: pointer to the HW structure 1163200243Sjfv * @link: link up bool flag 1164200243Sjfv * 1165200243Sjfv * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 1166200243Sjfv * from a lower speed. This workaround disables K1 whenever link is at 1Gig 1167200243Sjfv * If link is down, the function will restore the default K1 setting located 1168200243Sjfv * in the NVM. 1169200243Sjfv **/ 1170200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1171200243Sjfv{ 1172200243Sjfv s32 ret_val = E1000_SUCCESS; 1173200243Sjfv u16 status_reg = 0; 1174200243Sjfv bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1175200243Sjfv 1176200243Sjfv DEBUGFUNC("e1000_k1_gig_workaround_hv"); 1177200243Sjfv 1178200243Sjfv if (hw->mac.type != e1000_pchlan) 1179200243Sjfv goto out; 1180200243Sjfv 1181200243Sjfv /* Wrap the whole flow with the sw flag */ 1182200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1183200243Sjfv if (ret_val) 1184200243Sjfv goto out; 1185200243Sjfv 1186200243Sjfv /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1187200243Sjfv if (link) { 1188200243Sjfv if (hw->phy.type == e1000_phy_82578) { 1189200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 1190200243Sjfv &status_reg); 1191200243Sjfv if (ret_val) 1192200243Sjfv goto release; 1193200243Sjfv 1194200243Sjfv status_reg &= BM_CS_STATUS_LINK_UP | 1195200243Sjfv BM_CS_STATUS_RESOLVED | 1196200243Sjfv BM_CS_STATUS_SPEED_MASK; 1197200243Sjfv 1198200243Sjfv if (status_reg == (BM_CS_STATUS_LINK_UP | 1199200243Sjfv BM_CS_STATUS_RESOLVED | 1200200243Sjfv BM_CS_STATUS_SPEED_1000)) 1201200243Sjfv k1_enable = FALSE; 1202200243Sjfv } 1203200243Sjfv 1204200243Sjfv if (hw->phy.type == e1000_phy_82577) { 1205200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 1206200243Sjfv &status_reg); 1207200243Sjfv if (ret_val) 1208200243Sjfv goto release; 1209200243Sjfv 1210200243Sjfv status_reg &= HV_M_STATUS_LINK_UP | 1211200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1212200243Sjfv HV_M_STATUS_SPEED_MASK; 1213200243Sjfv 1214200243Sjfv if (status_reg == (HV_M_STATUS_LINK_UP | 1215200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1216200243Sjfv HV_M_STATUS_SPEED_1000)) 1217200243Sjfv k1_enable = FALSE; 1218200243Sjfv } 1219200243Sjfv 1220200243Sjfv /* Link stall fix for link up */ 1221200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1222200243Sjfv 0x0100); 1223200243Sjfv if (ret_val) 1224200243Sjfv goto release; 1225200243Sjfv 1226200243Sjfv } else { 1227200243Sjfv /* Link stall fix for link down */ 1228200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1229200243Sjfv 0x4100); 1230200243Sjfv if (ret_val) 1231200243Sjfv goto release; 1232200243Sjfv } 1233200243Sjfv 1234200243Sjfv ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1235200243Sjfv 1236200243Sjfvrelease: 1237200243Sjfv hw->phy.ops.release(hw); 1238200243Sjfvout: 1239200243Sjfv return ret_val; 1240200243Sjfv} 1241200243Sjfv 1242200243Sjfv/** 1243200243Sjfv * e1000_configure_k1_ich8lan - Configure K1 power state 1244200243Sjfv * @hw: pointer to the HW structure 1245200243Sjfv * @enable: K1 state to configure 1246200243Sjfv * 1247200243Sjfv * Configure the K1 power state based on the provided parameter. 1248200243Sjfv * Assumes semaphore already acquired. 1249200243Sjfv * 1250200243Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1251200243Sjfv **/ 1252200243Sjfvs32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1253200243Sjfv{ 1254200243Sjfv s32 ret_val = E1000_SUCCESS; 1255200243Sjfv u32 ctrl_reg = 0; 1256200243Sjfv u32 ctrl_ext = 0; 1257200243Sjfv u32 reg = 0; 1258200243Sjfv u16 kmrn_reg = 0; 1259200243Sjfv 1260213234Sjfv DEBUGFUNC("e1000_configure_k1_ich8lan"); 1261213234Sjfv 1262200243Sjfv ret_val = e1000_read_kmrn_reg_locked(hw, 1263200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1264200243Sjfv &kmrn_reg); 1265200243Sjfv if (ret_val) 1266200243Sjfv goto out; 1267200243Sjfv 1268200243Sjfv if (k1_enable) 1269200243Sjfv kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1270200243Sjfv else 1271200243Sjfv kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1272200243Sjfv 1273200243Sjfv ret_val = e1000_write_kmrn_reg_locked(hw, 1274200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1275200243Sjfv kmrn_reg); 1276200243Sjfv if (ret_val) 1277200243Sjfv goto out; 1278200243Sjfv 1279200243Sjfv usec_delay(20); 1280200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1281200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1282200243Sjfv 1283200243Sjfv reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1284200243Sjfv reg |= E1000_CTRL_FRCSPD; 1285200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1286200243Sjfv 1287200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1288200243Sjfv usec_delay(20); 1289200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1290200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1291200243Sjfv usec_delay(20); 1292200243Sjfv 1293200243Sjfvout: 1294200243Sjfv return ret_val; 1295200243Sjfv} 1296200243Sjfv 1297200243Sjfv/** 1298200243Sjfv * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1299200243Sjfv * @hw: pointer to the HW structure 1300200243Sjfv * @d0_state: boolean if entering d0 or d3 device state 1301200243Sjfv * 1302200243Sjfv * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1303200243Sjfv * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1304200243Sjfv * in NVM determines whether HW should configure LPLU and Gbe Disable. 1305200243Sjfv **/ 1306200243Sjfvs32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1307200243Sjfv{ 1308200243Sjfv s32 ret_val = 0; 1309200243Sjfv u32 mac_reg; 1310200243Sjfv u16 oem_reg; 1311200243Sjfv 1312213234Sjfv DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 1313213234Sjfv 1314213234Sjfv if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) 1315200243Sjfv return ret_val; 1316200243Sjfv 1317200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1318200243Sjfv if (ret_val) 1319200243Sjfv return ret_val; 1320200243Sjfv 1321213234Sjfv if (!(hw->mac.type == e1000_pch2lan)) { 1322213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1323213234Sjfv if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1324213234Sjfv goto out; 1325213234Sjfv } 1326200243Sjfv 1327200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 1328200243Sjfv if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1329200243Sjfv goto out; 1330200243Sjfv 1331200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 1332200243Sjfv 1333200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1334200243Sjfv if (ret_val) 1335200243Sjfv goto out; 1336200243Sjfv 1337200243Sjfv oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1338200243Sjfv 1339200243Sjfv if (d0_state) { 1340200243Sjfv if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1341200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1342200243Sjfv 1343200243Sjfv if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1344200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1345200243Sjfv } else { 1346200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 1347200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1348200243Sjfv 1349200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 1350200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1351200243Sjfv } 1352200243Sjfv /* Restart auto-neg to activate the bits */ 1353200243Sjfv if (!hw->phy.ops.check_reset_block(hw)) 1354200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1355200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 1356200243Sjfv 1357200243Sjfvout: 1358200243Sjfv hw->phy.ops.release(hw); 1359200243Sjfv 1360200243Sjfv return ret_val; 1361200243Sjfv} 1362200243Sjfv 1363200243Sjfv 1364200243Sjfv/** 1365194865Sjfv * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx 1366169589Sjfv * @hw: pointer to the HW structure 1367169240Sjfv **/ 1368194865Sjfvs32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 1369169240Sjfv{ 1370213234Sjfv DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan"); 1371213234Sjfv 1372194865Sjfv if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2)) 1373194865Sjfv return E1000_SUCCESS; 1374169240Sjfv 1375194865Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444); 1376194865Sjfv} 1377169240Sjfv 1378194865Sjfv/** 1379203049Sjfv * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 1380203049Sjfv * @hw: pointer to the HW structure 1381203049Sjfv **/ 1382203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 1383203049Sjfv{ 1384203049Sjfv s32 ret_val; 1385203049Sjfv u16 data; 1386203049Sjfv 1387213234Sjfv DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 1388213234Sjfv 1389203049Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 1390203049Sjfv if (ret_val) 1391203049Sjfv return ret_val; 1392203049Sjfv 1393203049Sjfv data |= HV_KMRN_MDIO_SLOW; 1394203049Sjfv 1395203049Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 1396203049Sjfv 1397203049Sjfv return ret_val; 1398203049Sjfv} 1399203049Sjfv 1400203049Sjfv/** 1401194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1402194865Sjfv * done after every PHY reset. 1403194865Sjfv **/ 1404194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1405194865Sjfv{ 1406194865Sjfv s32 ret_val = E1000_SUCCESS; 1407203049Sjfv u16 phy_data; 1408194865Sjfv 1409213234Sjfv DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 1410213234Sjfv 1411194865Sjfv if (hw->mac.type != e1000_pchlan) 1412200243Sjfv goto out; 1413194865Sjfv 1414203049Sjfv /* Set MDIO slow mode before any other MDIO access */ 1415203049Sjfv if (hw->phy.type == e1000_phy_82577) { 1416203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 1417203049Sjfv if (ret_val) 1418203049Sjfv goto out; 1419203049Sjfv } 1420203049Sjfv 1421194865Sjfv /* Hanksville M Phy init for IEEE. */ 1422194865Sjfv if ((hw->revision_id == 2) && 1423194865Sjfv (hw->phy.type == e1000_phy_82577) && 1424194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1425194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8823); 1426194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0018); 1427194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8824); 1428194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0016); 1429194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8825); 1430194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x001A); 1431194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888C); 1432194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1433194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888D); 1434194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1435194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888E); 1436194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1437194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8827); 1438194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1439194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8835); 1440194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1441194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8834); 1442194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1443194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8833); 1444194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0002); 1445169240Sjfv } 1446169240Sjfv 1447194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 1448194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1449194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1450194865Sjfv /* Disable generation of early preamble */ 1451194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1452194865Sjfv if (ret_val) 1453200243Sjfv goto out; 1454169240Sjfv 1455194865Sjfv /* Preamble tuning for SSC */ 1456194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1457194865Sjfv if (ret_val) 1458200243Sjfv goto out; 1459194865Sjfv } 1460169240Sjfv 1461194865Sjfv if (hw->phy.type == e1000_phy_82578) { 1462194865Sjfv if (hw->revision_id < 3) { 1463194865Sjfv /* PHY config */ 1464194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 1465194865Sjfv 0x66C0); 1466194865Sjfv if (ret_val) 1467200243Sjfv goto out; 1468169240Sjfv 1469194865Sjfv /* PHY config */ 1470194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 1471194865Sjfv 0xFFFF); 1472194865Sjfv if (ret_val) 1473200243Sjfv goto out; 1474194865Sjfv } 1475169240Sjfv 1476194865Sjfv /* 1477194865Sjfv * Return registers to default by doing a soft reset then 1478194865Sjfv * writing 0x3140 to the control register. 1479194865Sjfv */ 1480194865Sjfv if (hw->phy.revision < 2) { 1481194865Sjfv e1000_phy_sw_reset_generic(hw); 1482194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 1483194865Sjfv 0x3140); 1484194865Sjfv } 1485194865Sjfv } 1486169240Sjfv 1487194865Sjfv if ((hw->revision_id == 2) && 1488194865Sjfv (hw->phy.type == e1000_phy_82577) && 1489194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1490194865Sjfv /* 1491194865Sjfv * Workaround for OEM (GbE) not operating after reset - 1492194865Sjfv * restart AN (twice) 1493194865Sjfv */ 1494194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1495194865Sjfv if (ret_val) 1496200243Sjfv goto out; 1497194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1498194865Sjfv if (ret_val) 1499200243Sjfv goto out; 1500194865Sjfv } 1501194865Sjfv 1502194865Sjfv /* Select page 0 */ 1503194865Sjfv ret_val = hw->phy.ops.acquire(hw); 1504169240Sjfv if (ret_val) 1505200243Sjfv goto out; 1506200243Sjfv 1507194865Sjfv hw->phy.addr = 1; 1508200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1509203049Sjfv hw->phy.ops.release(hw); 1510200243Sjfv if (ret_val) 1511200243Sjfv goto out; 1512169240Sjfv 1513200243Sjfv /* 1514200243Sjfv * Configure the K1 Si workaround during phy reset assuming there is 1515200243Sjfv * link so that it disables K1 if link is in 1Gbps. 1516200243Sjfv */ 1517200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 1518203049Sjfv if (ret_val) 1519203049Sjfv goto out; 1520200243Sjfv 1521203049Sjfv /* Workaround for link disconnects on a busy hub in half duplex */ 1522203049Sjfv ret_val = hw->phy.ops.acquire(hw); 1523203049Sjfv if (ret_val) 1524203049Sjfv goto out; 1525218588Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG_REG, 1526203049Sjfv &phy_data); 1527203049Sjfv if (ret_val) 1528203049Sjfv goto release; 1529218588Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG_REG, 1530203049Sjfv phy_data & 0x00FF); 1531203049Sjfvrelease: 1532203049Sjfv hw->phy.ops.release(hw); 1533200243Sjfvout: 1534194865Sjfv return ret_val; 1535194865Sjfv} 1536169240Sjfv 1537194865Sjfv/** 1538213234Sjfv * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 1539213234Sjfv * @hw: pointer to the HW structure 1540213234Sjfv **/ 1541213234Sjfvvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 1542213234Sjfv{ 1543213234Sjfv u32 mac_reg; 1544213234Sjfv u16 i; 1545213234Sjfv 1546213234Sjfv DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 1547213234Sjfv 1548213234Sjfv /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 1549213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1550213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 1551213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF)); 1552213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF)); 1553213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 1554213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF)); 1555213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000)); 1556213234Sjfv } 1557213234Sjfv} 1558213234Sjfv 1559213234Sjfvstatic u32 e1000_calc_rx_da_crc(u8 mac[]) 1560213234Sjfv{ 1561213234Sjfv u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 1562213234Sjfv u32 i, j, mask, crc; 1563213234Sjfv 1564213234Sjfv DEBUGFUNC("e1000_calc_rx_da_crc"); 1565213234Sjfv 1566213234Sjfv crc = 0xffffffff; 1567213234Sjfv for (i = 0; i < 6; i++) { 1568213234Sjfv crc = crc ^ mac[i]; 1569213234Sjfv for (j = 8; j > 0; j--) { 1570213234Sjfv mask = (crc & 1) * (-1); 1571213234Sjfv crc = (crc >> 1) ^ (poly & mask); 1572213234Sjfv } 1573213234Sjfv } 1574213234Sjfv return ~crc; 1575213234Sjfv} 1576213234Sjfv 1577213234Sjfv/** 1578213234Sjfv * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 1579213234Sjfv * with 82579 PHY 1580213234Sjfv * @hw: pointer to the HW structure 1581213234Sjfv * @enable: flag to enable/disable workaround when enabling/disabling jumbos 1582213234Sjfv **/ 1583213234Sjfvs32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 1584213234Sjfv{ 1585213234Sjfv s32 ret_val = E1000_SUCCESS; 1586213234Sjfv u16 phy_reg, data; 1587213234Sjfv u32 mac_reg; 1588213234Sjfv u16 i; 1589213234Sjfv 1590213234Sjfv DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 1591213234Sjfv 1592213234Sjfv if (hw->mac.type != e1000_pch2lan) 1593213234Sjfv goto out; 1594213234Sjfv 1595213234Sjfv /* disable Rx path while enabling/disabling workaround */ 1596213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 1597213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 1598213234Sjfv if (ret_val) 1599213234Sjfv goto out; 1600213234Sjfv 1601213234Sjfv if (enable) { 1602213234Sjfv /* 1603213234Sjfv * Write Rx addresses (rar_entry_count for RAL/H, +4 for 1604213234Sjfv * SHRAL/H) and initial CRC values to the MAC 1605213234Sjfv */ 1606213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1607213234Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 1608213234Sjfv u32 addr_high, addr_low; 1609213234Sjfv 1610213234Sjfv addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 1611213234Sjfv if (!(addr_high & E1000_RAH_AV)) 1612213234Sjfv continue; 1613213234Sjfv addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 1614213234Sjfv mac_addr[0] = (addr_low & 0xFF); 1615213234Sjfv mac_addr[1] = ((addr_low >> 8) & 0xFF); 1616213234Sjfv mac_addr[2] = ((addr_low >> 16) & 0xFF); 1617213234Sjfv mac_addr[3] = ((addr_low >> 24) & 0xFF); 1618213234Sjfv mac_addr[4] = (addr_high & 0xFF); 1619213234Sjfv mac_addr[5] = ((addr_high >> 8) & 0xFF); 1620213234Sjfv 1621213234Sjfv E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 1622213234Sjfv e1000_calc_rx_da_crc(mac_addr)); 1623213234Sjfv } 1624213234Sjfv 1625213234Sjfv /* Write Rx addresses to the PHY */ 1626213234Sjfv e1000_copy_rx_addrs_to_phy_ich8lan(hw); 1627213234Sjfv 1628213234Sjfv /* Enable jumbo frame workaround in the MAC */ 1629213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 1630213234Sjfv mac_reg &= ~(1 << 14); 1631213234Sjfv mac_reg |= (7 << 15); 1632213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 1633213234Sjfv 1634213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 1635213234Sjfv mac_reg |= E1000_RCTL_SECRC; 1636213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 1637213234Sjfv 1638213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1639213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1640213234Sjfv &data); 1641213234Sjfv if (ret_val) 1642213234Sjfv goto out; 1643213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1644213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1645213234Sjfv data | (1 << 0)); 1646213234Sjfv if (ret_val) 1647213234Sjfv goto out; 1648213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1649213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1650213234Sjfv &data); 1651213234Sjfv if (ret_val) 1652213234Sjfv goto out; 1653213234Sjfv data &= ~(0xF << 8); 1654213234Sjfv data |= (0xB << 8); 1655213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1656213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1657213234Sjfv data); 1658213234Sjfv if (ret_val) 1659213234Sjfv goto out; 1660213234Sjfv 1661213234Sjfv /* Enable jumbo frame workaround in the PHY */ 1662213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 1663213234Sjfv data &= ~(0x7F << 5); 1664213234Sjfv data |= (0x37 << 5); 1665213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 1666213234Sjfv if (ret_val) 1667213234Sjfv goto out; 1668213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 1669213234Sjfv data &= ~(1 << 13); 1670213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 1671213234Sjfv if (ret_val) 1672213234Sjfv goto out; 1673213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 1674213234Sjfv data &= ~(0x3FF << 2); 1675213234Sjfv data |= (0x1A << 2); 1676213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 1677213234Sjfv if (ret_val) 1678213234Sjfv goto out; 1679213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00); 1680213234Sjfv if (ret_val) 1681213234Sjfv goto out; 1682213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 1683213234Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10)); 1684213234Sjfv if (ret_val) 1685213234Sjfv goto out; 1686213234Sjfv } else { 1687213234Sjfv /* Write MAC register values back to h/w defaults */ 1688213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 1689213234Sjfv mac_reg &= ~(0xF << 14); 1690213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 1691213234Sjfv 1692213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 1693213234Sjfv mac_reg &= ~E1000_RCTL_SECRC; 1694213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 1695213234Sjfv 1696213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1697213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1698213234Sjfv &data); 1699213234Sjfv if (ret_val) 1700213234Sjfv goto out; 1701213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1702213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1703213234Sjfv data & ~(1 << 0)); 1704213234Sjfv if (ret_val) 1705213234Sjfv goto out; 1706213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1707213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1708213234Sjfv &data); 1709213234Sjfv if (ret_val) 1710213234Sjfv goto out; 1711213234Sjfv data &= ~(0xF << 8); 1712213234Sjfv data |= (0xB << 8); 1713213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1714213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1715213234Sjfv data); 1716213234Sjfv if (ret_val) 1717213234Sjfv goto out; 1718213234Sjfv 1719213234Sjfv /* Write PHY register values back to h/w defaults */ 1720213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 1721213234Sjfv data &= ~(0x7F << 5); 1722213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 1723213234Sjfv if (ret_val) 1724213234Sjfv goto out; 1725213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 1726213234Sjfv data |= (1 << 13); 1727213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 1728213234Sjfv if (ret_val) 1729213234Sjfv goto out; 1730213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 1731213234Sjfv data &= ~(0x3FF << 2); 1732213234Sjfv data |= (0x8 << 2); 1733213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 1734213234Sjfv if (ret_val) 1735213234Sjfv goto out; 1736213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 1737213234Sjfv if (ret_val) 1738213234Sjfv goto out; 1739213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 1740213234Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10)); 1741213234Sjfv if (ret_val) 1742213234Sjfv goto out; 1743213234Sjfv } 1744213234Sjfv 1745213234Sjfv /* re-enable Rx path after enabling/disabling workaround */ 1746213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 1747213234Sjfv 1748213234Sjfvout: 1749213234Sjfv return ret_val; 1750213234Sjfv} 1751213234Sjfv 1752213234Sjfv/** 1753213234Sjfv * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1754213234Sjfv * done after every PHY reset. 1755213234Sjfv **/ 1756213234Sjfvstatic s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1757213234Sjfv{ 1758213234Sjfv s32 ret_val = E1000_SUCCESS; 1759213234Sjfv 1760213234Sjfv DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 1761213234Sjfv 1762213234Sjfv if (hw->mac.type != e1000_pch2lan) 1763213234Sjfv goto out; 1764213234Sjfv 1765213234Sjfv /* Set MDIO slow mode before any other MDIO access */ 1766213234Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 1767213234Sjfv 1768213234Sjfvout: 1769213234Sjfv return ret_val; 1770213234Sjfv} 1771213234Sjfv 1772213234Sjfv/** 1773213234Sjfv * e1000_k1_gig_workaround_lv - K1 Si workaround 1774213234Sjfv * @hw: pointer to the HW structure 1775213234Sjfv * 1776213234Sjfv * Workaround to set the K1 beacon duration for 82579 parts 1777213234Sjfv **/ 1778213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 1779213234Sjfv{ 1780213234Sjfv s32 ret_val = E1000_SUCCESS; 1781213234Sjfv u16 status_reg = 0; 1782213234Sjfv u32 mac_reg; 1783213234Sjfv 1784213234Sjfv DEBUGFUNC("e1000_k1_workaround_lv"); 1785213234Sjfv 1786213234Sjfv if (hw->mac.type != e1000_pch2lan) 1787213234Sjfv goto out; 1788213234Sjfv 1789213234Sjfv /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 1790213234Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 1791213234Sjfv if (ret_val) 1792213234Sjfv goto out; 1793213234Sjfv 1794213234Sjfv if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 1795213234Sjfv == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 1796213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1797213234Sjfv mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1798213234Sjfv 1799213234Sjfv if (status_reg & HV_M_STATUS_SPEED_1000) 1800213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1801213234Sjfv else 1802213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 1803213234Sjfv 1804213234Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1805213234Sjfv } 1806213234Sjfv 1807213234Sjfvout: 1808213234Sjfv return ret_val; 1809213234Sjfv} 1810213234Sjfv 1811213234Sjfv/** 1812213234Sjfv * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 1813213234Sjfv * @hw: pointer to the HW structure 1814218588Sjfv * @gate: boolean set to TRUE to gate, FALSE to ungate 1815213234Sjfv * 1816213234Sjfv * Gate/ungate the automatic PHY configuration via hardware; perform 1817213234Sjfv * the configuration via software instead. 1818213234Sjfv **/ 1819213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 1820213234Sjfv{ 1821213234Sjfv u32 extcnf_ctrl; 1822213234Sjfv 1823213234Sjfv DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 1824213234Sjfv 1825213234Sjfv if (hw->mac.type != e1000_pch2lan) 1826213234Sjfv return; 1827213234Sjfv 1828213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1829213234Sjfv 1830213234Sjfv if (gate) 1831213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1832213234Sjfv else 1833213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1834213234Sjfv 1835213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1836213234Sjfv return; 1837213234Sjfv} 1838213234Sjfv 1839213234Sjfv/** 1840213234Sjfv * e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around 1841213234Sjfv * needed for Nahum3 + Hanksville testing, requested by HW team 1842213234Sjfv **/ 1843213234Sjfvstatic s32 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw) 1844213234Sjfv{ 1845213234Sjfv s32 ret_val = E1000_SUCCESS; 1846213234Sjfv 1847213234Sjfv DEBUGFUNC("e1000_hv_phy_tuning_workaround_ich8lan"); 1848213234Sjfv 1849213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1850213234Sjfv if (ret_val) 1851213234Sjfv goto out; 1852213234Sjfv 1853213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1854213234Sjfv if (ret_val) 1855213234Sjfv goto out; 1856213234Sjfv 1857213234Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0); 1858213234Sjfv if (ret_val) 1859213234Sjfv goto out; 1860213234Sjfv 1861213234Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF); 1862213234Sjfv 1863213234Sjfvout: 1864213234Sjfv return ret_val; 1865213234Sjfv} 1866213234Sjfv 1867213234Sjfv/** 1868194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 1869194865Sjfv * @hw: pointer to the HW structure 1870194865Sjfv * 1871194865Sjfv * Check the appropriate indication the MAC has finished configuring the 1872194865Sjfv * PHY after a software reset. 1873194865Sjfv **/ 1874194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 1875194865Sjfv{ 1876194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 1877169240Sjfv 1878194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 1879169240Sjfv 1880194865Sjfv /* Wait for basic configuration completes before proceeding */ 1881194865Sjfv do { 1882194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1883194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 1884194865Sjfv usec_delay(100); 1885194865Sjfv } while ((!data) && --loop); 1886169240Sjfv 1887194865Sjfv /* 1888194865Sjfv * If basic configuration is incomplete before the above loop 1889194865Sjfv * count reaches 0, loading the configuration from NVM will 1890194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 1891194865Sjfv */ 1892194865Sjfv if (loop == 0) 1893194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 1894169240Sjfv 1895194865Sjfv /* Clear the Init Done bit for the next init event */ 1896194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1897194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 1898194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 1899169240Sjfv} 1900169240Sjfv 1901169240Sjfv/** 1902213234Sjfv * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 1903169589Sjfv * @hw: pointer to the HW structure 1904169240Sjfv **/ 1905213234Sjfvstatic s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 1906169240Sjfv{ 1907200243Sjfv s32 ret_val = E1000_SUCCESS; 1908200243Sjfv u16 reg; 1909169240Sjfv 1910213234Sjfv DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 1911169240Sjfv 1912213234Sjfv if (hw->phy.ops.check_reset_block(hw)) 1913169240Sjfv goto out; 1914169240Sjfv 1915213234Sjfv /* Allow time for h/w to get to quiescent state after reset */ 1916194865Sjfv msec_delay(10); 1917194865Sjfv 1918203049Sjfv /* Perform any necessary post-reset workarounds */ 1919203049Sjfv switch (hw->mac.type) { 1920203049Sjfv case e1000_pchlan: 1921194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 1922194865Sjfv if (ret_val) 1923194865Sjfv goto out; 1924203049Sjfv break; 1925213234Sjfv case e1000_pch2lan: 1926213234Sjfv ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 1927213234Sjfv if (ret_val) 1928213234Sjfv goto out; 1929213234Sjfv break; 1930203049Sjfv default: 1931203049Sjfv break; 1932194865Sjfv } 1933194865Sjfv 1934213234Sjfv if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) { 1935213234Sjfv ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw); 1936213234Sjfv if (ret_val) 1937213234Sjfv goto out; 1938213234Sjfv } 1939213234Sjfv 1940200243Sjfv /* Dummy read to clear the phy wakeup bit after lcd reset */ 1941213234Sjfv if (hw->mac.type >= e1000_pchlan) 1942200243Sjfv hw->phy.ops.read_reg(hw, BM_WUC, ®); 1943169240Sjfv 1944200243Sjfv /* Configure the LCD with the extended configuration region in NVM */ 1945200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 1946200243Sjfv if (ret_val) 1947200243Sjfv goto out; 1948169240Sjfv 1949200243Sjfv /* Configure the LCD with the OEM bits in NVM */ 1950203049Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 1951169240Sjfv 1952218588Sjfv if (hw->mac.type == e1000_pch2lan) { 1953218588Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 1954218588Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 1955218588Sjfv E1000_ICH_FWSM_FW_VALID)) { 1956218588Sjfv msec_delay(10); 1957218588Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 1958218588Sjfv } 1959218588Sjfv 1960218588Sjfv /* Set EEE LPI Update Timer to 200usec */ 1961218588Sjfv ret_val = hw->phy.ops.acquire(hw); 1962218588Sjfv if (ret_val) 1963218588Sjfv goto out; 1964218588Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, 1965218588Sjfv I82579_LPI_UPDATE_TIMER); 1966218588Sjfv if (ret_val) 1967218588Sjfv goto release; 1968218588Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 1969218588Sjfv 0x1387); 1970218588Sjfvrelease: 1971218588Sjfv hw->phy.ops.release(hw); 1972213234Sjfv } 1973213234Sjfv 1974169240Sjfvout: 1975169240Sjfv return ret_val; 1976169240Sjfv} 1977169240Sjfv 1978169240Sjfv/** 1979213234Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 1980213234Sjfv * @hw: pointer to the HW structure 1981213234Sjfv * 1982213234Sjfv * Resets the PHY 1983213234Sjfv * This is a function pointer entry point called by drivers 1984213234Sjfv * or other shared routines. 1985213234Sjfv **/ 1986213234Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 1987213234Sjfv{ 1988213234Sjfv s32 ret_val = E1000_SUCCESS; 1989213234Sjfv 1990213234Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 1991213234Sjfv 1992213234Sjfv /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 1993213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 1994213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 1995213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 1996213234Sjfv 1997213234Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 1998213234Sjfv if (ret_val) 1999213234Sjfv goto out; 2000213234Sjfv 2001213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 2002213234Sjfv 2003213234Sjfvout: 2004213234Sjfv return ret_val; 2005213234Sjfv} 2006213234Sjfv 2007213234Sjfv/** 2008200243Sjfv * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2009169589Sjfv * @hw: pointer to the HW structure 2010200243Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2011169240Sjfv * 2012200243Sjfv * Sets the LPLU state according to the active flag. For PCH, if OEM write 2013200243Sjfv * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2014200243Sjfv * the phy speed. This function will manually set the LPLU bit and restart 2015200243Sjfv * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2016200243Sjfv * since it configures the same bit. 2017169240Sjfv **/ 2018200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2019169240Sjfv{ 2020200243Sjfv s32 ret_val = E1000_SUCCESS; 2021200243Sjfv u16 oem_reg; 2022169240Sjfv 2023200243Sjfv DEBUGFUNC("e1000_set_lplu_state_pchlan"); 2024169240Sjfv 2025200243Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 2026169240Sjfv if (ret_val) 2027169240Sjfv goto out; 2028169240Sjfv 2029200243Sjfv if (active) 2030200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 2031200243Sjfv else 2032200243Sjfv oem_reg &= ~HV_OEM_BITS_LPLU; 2033169240Sjfv 2034200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 2035200243Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 2036169240Sjfv 2037169240Sjfvout: 2038169240Sjfv return ret_val; 2039169240Sjfv} 2040169240Sjfv 2041169240Sjfv/** 2042169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2043169589Sjfv * @hw: pointer to the HW structure 2044169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2045169240Sjfv * 2046169240Sjfv * Sets the LPLU D0 state according to the active flag. When 2047169240Sjfv * activating LPLU this function also disables smart speed 2048169240Sjfv * and vice versa. LPLU will not be activated unless the 2049169240Sjfv * device autonegotiation advertisement meets standards of 2050169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 2051169240Sjfv * This is a function pointer entry point only called by 2052169240Sjfv * PHY setup routines. 2053169240Sjfv **/ 2054185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2055169240Sjfv{ 2056169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2057169240Sjfv u32 phy_ctrl; 2058169240Sjfv s32 ret_val = E1000_SUCCESS; 2059169240Sjfv u16 data; 2060169240Sjfv 2061169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 2062169240Sjfv 2063173788Sjfv if (phy->type == e1000_phy_ife) 2064169240Sjfv goto out; 2065169240Sjfv 2066169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2067169240Sjfv 2068169240Sjfv if (active) { 2069169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2070169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2071169240Sjfv 2072194865Sjfv if (phy->type != e1000_phy_igp_3) 2073194865Sjfv goto out; 2074194865Sjfv 2075173788Sjfv /* 2076173788Sjfv * Call gig speed drop workaround on LPLU before accessing 2077173788Sjfv * any PHY registers 2078173788Sjfv */ 2079194865Sjfv if (hw->mac.type == e1000_ich8lan) 2080169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2081169240Sjfv 2082169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2083177867Sjfv ret_val = phy->ops.read_reg(hw, 2084169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2085169240Sjfv &data); 2086169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2087177867Sjfv ret_val = phy->ops.write_reg(hw, 2088169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2089169240Sjfv data); 2090169240Sjfv if (ret_val) 2091169240Sjfv goto out; 2092169240Sjfv } else { 2093169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2094169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2095169240Sjfv 2096194865Sjfv if (phy->type != e1000_phy_igp_3) 2097194865Sjfv goto out; 2098194865Sjfv 2099173788Sjfv /* 2100173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 2101169240Sjfv * during Dx states where the power conservation is most 2102169240Sjfv * important. During driver activity we should enable 2103173788Sjfv * SmartSpeed, so performance is maintained. 2104173788Sjfv */ 2105169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2106177867Sjfv ret_val = phy->ops.read_reg(hw, 2107169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2108169240Sjfv &data); 2109169240Sjfv if (ret_val) 2110169240Sjfv goto out; 2111169240Sjfv 2112169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2113177867Sjfv ret_val = phy->ops.write_reg(hw, 2114169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2115169240Sjfv data); 2116169240Sjfv if (ret_val) 2117169240Sjfv goto out; 2118169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2119177867Sjfv ret_val = phy->ops.read_reg(hw, 2120169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2121169240Sjfv &data); 2122169240Sjfv if (ret_val) 2123169240Sjfv goto out; 2124169240Sjfv 2125169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2126177867Sjfv ret_val = phy->ops.write_reg(hw, 2127169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2128169240Sjfv data); 2129169240Sjfv if (ret_val) 2130169240Sjfv goto out; 2131169240Sjfv } 2132169240Sjfv } 2133169240Sjfv 2134169240Sjfvout: 2135169240Sjfv return ret_val; 2136169240Sjfv} 2137169240Sjfv 2138169240Sjfv/** 2139169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2140169589Sjfv * @hw: pointer to the HW structure 2141169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2142169240Sjfv * 2143169240Sjfv * Sets the LPLU D3 state according to the active flag. When 2144169240Sjfv * activating LPLU this function also disables smart speed 2145169240Sjfv * and vice versa. LPLU will not be activated unless the 2146169240Sjfv * device autonegotiation advertisement meets standards of 2147169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 2148169240Sjfv * This is a function pointer entry point only called by 2149169240Sjfv * PHY setup routines. 2150169240Sjfv **/ 2151185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2152169240Sjfv{ 2153169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2154169240Sjfv u32 phy_ctrl; 2155169240Sjfv s32 ret_val = E1000_SUCCESS; 2156169240Sjfv u16 data; 2157169240Sjfv 2158169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 2159169240Sjfv 2160169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2161169240Sjfv 2162169240Sjfv if (!active) { 2163169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2164169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2165194865Sjfv 2166194865Sjfv if (phy->type != e1000_phy_igp_3) 2167194865Sjfv goto out; 2168194865Sjfv 2169173788Sjfv /* 2170173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 2171169240Sjfv * during Dx states where the power conservation is most 2172169240Sjfv * important. During driver activity we should enable 2173173788Sjfv * SmartSpeed, so performance is maintained. 2174173788Sjfv */ 2175169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2176177867Sjfv ret_val = phy->ops.read_reg(hw, 2177169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2178169240Sjfv &data); 2179169240Sjfv if (ret_val) 2180169240Sjfv goto out; 2181169240Sjfv 2182169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2183177867Sjfv ret_val = phy->ops.write_reg(hw, 2184169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2185169240Sjfv data); 2186169240Sjfv if (ret_val) 2187169240Sjfv goto out; 2188169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2189177867Sjfv ret_val = phy->ops.read_reg(hw, 2190169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2191169240Sjfv &data); 2192169240Sjfv if (ret_val) 2193169240Sjfv goto out; 2194169240Sjfv 2195169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2196177867Sjfv ret_val = phy->ops.write_reg(hw, 2197169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2198169240Sjfv data); 2199169240Sjfv if (ret_val) 2200169240Sjfv goto out; 2201169240Sjfv } 2202169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2203169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2204169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2205169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2206169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2207169240Sjfv 2208194865Sjfv if (phy->type != e1000_phy_igp_3) 2209194865Sjfv goto out; 2210194865Sjfv 2211173788Sjfv /* 2212173788Sjfv * Call gig speed drop workaround on LPLU before accessing 2213173788Sjfv * any PHY registers 2214173788Sjfv */ 2215194865Sjfv if (hw->mac.type == e1000_ich8lan) 2216169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2217169240Sjfv 2218169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2219177867Sjfv ret_val = phy->ops.read_reg(hw, 2220169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2221169240Sjfv &data); 2222169240Sjfv if (ret_val) 2223169240Sjfv goto out; 2224169240Sjfv 2225169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2226177867Sjfv ret_val = phy->ops.write_reg(hw, 2227169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2228169240Sjfv data); 2229169240Sjfv } 2230169240Sjfv 2231169240Sjfvout: 2232169240Sjfv return ret_val; 2233169240Sjfv} 2234169240Sjfv 2235169240Sjfv/** 2236173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 2237173788Sjfv * @hw: pointer to the HW structure 2238173788Sjfv * @bank: pointer to the variable that returns the active bank 2239173788Sjfv * 2240173788Sjfv * Reads signature byte from the NVM using the flash access registers. 2241190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 2242173788Sjfv **/ 2243177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 2244173788Sjfv{ 2245190872Sjfv u32 eecd; 2246178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2247178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 2248178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 2249190872Sjfv u8 sig_byte = 0; 2250190872Sjfv s32 ret_val = E1000_SUCCESS; 2251178523Sjfv 2252213234Sjfv DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 2253213234Sjfv 2254190872Sjfv switch (hw->mac.type) { 2255190872Sjfv case e1000_ich8lan: 2256190872Sjfv case e1000_ich9lan: 2257190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 2258190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 2259190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 2260190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 2261190872Sjfv *bank = 1; 2262190872Sjfv else 2263190872Sjfv *bank = 0; 2264190872Sjfv 2265190872Sjfv goto out; 2266190872Sjfv } 2267190872Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - " 2268190872Sjfv "reading flash signature\n"); 2269190872Sjfv /* fall-thru */ 2270190872Sjfv default: 2271190872Sjfv /* set bank to 0 in case flash read fails */ 2272190872Sjfv *bank = 0; 2273190872Sjfv 2274190872Sjfv /* Check bank 0 */ 2275190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 2276190872Sjfv &sig_byte); 2277190872Sjfv if (ret_val) 2278190872Sjfv goto out; 2279190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2280200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2281178523Sjfv *bank = 0; 2282190872Sjfv goto out; 2283190872Sjfv } 2284185353Sjfv 2285190872Sjfv /* Check bank 1 */ 2286190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 2287190872Sjfv bank1_offset, 2288200243Sjfv &sig_byte); 2289190872Sjfv if (ret_val) 2290190872Sjfv goto out; 2291190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2292200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2293190872Sjfv *bank = 1; 2294190872Sjfv goto out; 2295178523Sjfv } 2296190872Sjfv 2297190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 2298190872Sjfv ret_val = -E1000_ERR_NVM; 2299190872Sjfv break; 2300178523Sjfv } 2301190872Sjfvout: 2302173788Sjfv return ret_val; 2303173788Sjfv} 2304173788Sjfv 2305173788Sjfv/** 2306169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2307169589Sjfv * @hw: pointer to the HW structure 2308169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 2309169589Sjfv * @words: Size of data to read in words 2310169589Sjfv * @data: Pointer to the word(s) to read at offset. 2311169240Sjfv * 2312169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 2313169240Sjfv **/ 2314177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2315173788Sjfv u16 *data) 2316169240Sjfv{ 2317169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2318185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2319169240Sjfv u32 act_offset; 2320169240Sjfv s32 ret_val = E1000_SUCCESS; 2321173788Sjfv u32 bank = 0; 2322169240Sjfv u16 i, word; 2323169240Sjfv 2324169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 2325169240Sjfv 2326169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2327169240Sjfv (words == 0)) { 2328169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 2329169240Sjfv ret_val = -E1000_ERR_NVM; 2330169240Sjfv goto out; 2331169240Sjfv } 2332169240Sjfv 2333200243Sjfv nvm->ops.acquire(hw); 2334169240Sjfv 2335173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2336200243Sjfv if (ret_val != E1000_SUCCESS) { 2337200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 2338200243Sjfv bank = 0; 2339200243Sjfv } 2340173788Sjfv 2341173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 2342169240Sjfv act_offset += offset; 2343169240Sjfv 2344200243Sjfv ret_val = E1000_SUCCESS; 2345169240Sjfv for (i = 0; i < words; i++) { 2346173788Sjfv if ((dev_spec->shadow_ram) && 2347173788Sjfv (dev_spec->shadow_ram[offset+i].modified)) { 2348169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 2349169240Sjfv } else { 2350169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 2351169240Sjfv act_offset + i, 2352169240Sjfv &word); 2353169240Sjfv if (ret_val) 2354169240Sjfv break; 2355169240Sjfv data[i] = word; 2356169240Sjfv } 2357169240Sjfv } 2358169240Sjfv 2359177867Sjfv nvm->ops.release(hw); 2360169240Sjfv 2361169240Sjfvout: 2362190872Sjfv if (ret_val) 2363190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 2364190872Sjfv 2365169240Sjfv return ret_val; 2366169240Sjfv} 2367169240Sjfv 2368169240Sjfv/** 2369169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 2370169589Sjfv * @hw: pointer to the HW structure 2371169240Sjfv * 2372169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 2373169240Sjfv * can be started. 2374169240Sjfv **/ 2375173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2376169240Sjfv{ 2377169240Sjfv union ich8_hws_flash_status hsfsts; 2378169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2379169240Sjfv 2380169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 2381169240Sjfv 2382169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2383169240Sjfv 2384169240Sjfv /* Check if the flash descriptor is valid */ 2385169240Sjfv if (hsfsts.hsf_status.fldesvalid == 0) { 2386169240Sjfv DEBUGOUT("Flash descriptor invalid. " 2387169240Sjfv "SW Sequencing must be used."); 2388169240Sjfv goto out; 2389169240Sjfv } 2390169240Sjfv 2391169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 2392169240Sjfv hsfsts.hsf_status.flcerr = 1; 2393169240Sjfv hsfsts.hsf_status.dael = 1; 2394169240Sjfv 2395169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2396169240Sjfv 2397173788Sjfv /* 2398173788Sjfv * Either we should have a hardware SPI cycle in progress 2399169240Sjfv * bit to check against, in order to start a new cycle or 2400169240Sjfv * FDONE bit should be changed in the hardware so that it 2401176667Sjfv * is 1 after hardware reset, which can then be used as an 2402169240Sjfv * indication whether a cycle is in progress or has been 2403169240Sjfv * completed. 2404169240Sjfv */ 2405169240Sjfv 2406169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 2407173788Sjfv /* 2408173788Sjfv * There is no cycle running at present, 2409173788Sjfv * so we can start a cycle. 2410173788Sjfv * Begin by setting Flash Cycle Done. 2411173788Sjfv */ 2412169240Sjfv hsfsts.hsf_status.flcdone = 1; 2413169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2414169240Sjfv ret_val = E1000_SUCCESS; 2415169240Sjfv } else { 2416218588Sjfv s32 i; 2417218588Sjfv 2418173788Sjfv /* 2419173788Sjfv * Otherwise poll for sometime so the current 2420173788Sjfv * cycle has a chance to end before giving up. 2421173788Sjfv */ 2422169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2423169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2424169240Sjfv ICH_FLASH_HSFSTS); 2425169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 2426169240Sjfv ret_val = E1000_SUCCESS; 2427169240Sjfv break; 2428169240Sjfv } 2429169240Sjfv usec_delay(1); 2430169240Sjfv } 2431169240Sjfv if (ret_val == E1000_SUCCESS) { 2432173788Sjfv /* 2433173788Sjfv * Successful in waiting for previous cycle to timeout, 2434173788Sjfv * now set the Flash Cycle Done. 2435173788Sjfv */ 2436169240Sjfv hsfsts.hsf_status.flcdone = 1; 2437185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 2438169240Sjfv hsfsts.regval); 2439169240Sjfv } else { 2440169240Sjfv DEBUGOUT("Flash controller busy, cannot get access"); 2441169240Sjfv } 2442169240Sjfv } 2443169240Sjfv 2444169240Sjfvout: 2445169240Sjfv return ret_val; 2446169240Sjfv} 2447169240Sjfv 2448169240Sjfv/** 2449169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 2450169589Sjfv * @hw: pointer to the HW structure 2451169589Sjfv * @timeout: maximum time to wait for completion 2452169240Sjfv * 2453169240Sjfv * This function starts a flash cycle and waits for its completion. 2454169240Sjfv **/ 2455173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 2456169240Sjfv{ 2457169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2458169240Sjfv union ich8_hws_flash_status hsfsts; 2459169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2460169240Sjfv u32 i = 0; 2461169240Sjfv 2462169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 2463169240Sjfv 2464169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 2465169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2466169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 2467169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2468169240Sjfv 2469169240Sjfv /* wait till FDONE bit is set to 1 */ 2470169240Sjfv do { 2471169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2472169240Sjfv if (hsfsts.hsf_status.flcdone == 1) 2473169240Sjfv break; 2474169240Sjfv usec_delay(1); 2475169240Sjfv } while (i++ < timeout); 2476169240Sjfv 2477169240Sjfv if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 2478169240Sjfv ret_val = E1000_SUCCESS; 2479169240Sjfv 2480169240Sjfv return ret_val; 2481169240Sjfv} 2482169240Sjfv 2483169240Sjfv/** 2484169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 2485169589Sjfv * @hw: pointer to the HW structure 2486169589Sjfv * @offset: offset to data location 2487169589Sjfv * @data: pointer to the location for storing the data 2488169240Sjfv * 2489169240Sjfv * Reads the flash word at offset into data. Offset is converted 2490169240Sjfv * to bytes before read. 2491169240Sjfv **/ 2492177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 2493173788Sjfv u16 *data) 2494169240Sjfv{ 2495169240Sjfv s32 ret_val; 2496169240Sjfv 2497169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 2498169240Sjfv 2499173788Sjfv if (!data) { 2500169240Sjfv ret_val = -E1000_ERR_NVM; 2501169240Sjfv goto out; 2502169240Sjfv } 2503169240Sjfv 2504169240Sjfv /* Must convert offset into bytes. */ 2505169240Sjfv offset <<= 1; 2506169240Sjfv 2507169240Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 2508169240Sjfv 2509169240Sjfvout: 2510169240Sjfv return ret_val; 2511169240Sjfv} 2512169240Sjfv 2513169240Sjfv/** 2514178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 2515178523Sjfv * @hw: pointer to the HW structure 2516178523Sjfv * @offset: The offset of the byte to read. 2517178523Sjfv * @data: Pointer to a byte to store the value read. 2518178523Sjfv * 2519178523Sjfv * Reads a single byte from the NVM using the flash access registers. 2520178523Sjfv **/ 2521178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2522185353Sjfv u8 *data) 2523178523Sjfv{ 2524178523Sjfv s32 ret_val = E1000_SUCCESS; 2525178523Sjfv u16 word = 0; 2526178523Sjfv 2527178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 2528178523Sjfv if (ret_val) 2529178523Sjfv goto out; 2530178523Sjfv 2531178523Sjfv *data = (u8)word; 2532178523Sjfv 2533178523Sjfvout: 2534178523Sjfv return ret_val; 2535178523Sjfv} 2536178523Sjfv 2537178523Sjfv/** 2538169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 2539169589Sjfv * @hw: pointer to the HW structure 2540169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 2541169589Sjfv * @size: Size of data to read, 1=byte 2=word 2542169589Sjfv * @data: Pointer to the word to store the value read. 2543169240Sjfv * 2544169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 2545169240Sjfv **/ 2546173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2547185353Sjfv u8 size, u16 *data) 2548169240Sjfv{ 2549169240Sjfv union ich8_hws_flash_status hsfsts; 2550169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2551169240Sjfv u32 flash_linear_addr; 2552169240Sjfv u32 flash_data = 0; 2553169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2554169240Sjfv u8 count = 0; 2555169240Sjfv 2556169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 2557169240Sjfv 2558173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 2559169240Sjfv goto out; 2560169240Sjfv 2561169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2562169240Sjfv hw->nvm.flash_base_addr; 2563169240Sjfv 2564169240Sjfv do { 2565169240Sjfv usec_delay(1); 2566169240Sjfv /* Steps */ 2567169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2568169240Sjfv if (ret_val != E1000_SUCCESS) 2569169240Sjfv break; 2570169240Sjfv 2571169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2572169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2573169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 2574169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 2575169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2576169240Sjfv 2577169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 2578169240Sjfv 2579169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2580169240Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 2581169240Sjfv 2582173788Sjfv /* 2583173788Sjfv * Check if FCERR is set to 1, if set to 1, clear it 2584169240Sjfv * and try the whole sequence a few more times, else 2585169240Sjfv * read in (shift in) the Flash Data0, the order is 2586173788Sjfv * least significant byte first msb to lsb 2587173788Sjfv */ 2588169240Sjfv if (ret_val == E1000_SUCCESS) { 2589169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 2590185353Sjfv if (size == 1) 2591169240Sjfv *data = (u8)(flash_data & 0x000000FF); 2592185353Sjfv else if (size == 2) 2593169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 2594169240Sjfv break; 2595169240Sjfv } else { 2596173788Sjfv /* 2597173788Sjfv * If we've gotten here, then things are probably 2598169240Sjfv * completely hosed, but if the error condition is 2599169240Sjfv * detected, it won't hurt to give it another try... 2600169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2601169240Sjfv */ 2602169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2603169240Sjfv ICH_FLASH_HSFSTS); 2604169240Sjfv if (hsfsts.hsf_status.flcerr == 1) { 2605169240Sjfv /* Repeat for some time before giving up. */ 2606169240Sjfv continue; 2607169240Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 2608169240Sjfv DEBUGOUT("Timeout error - flash cycle " 2609169240Sjfv "did not complete."); 2610169240Sjfv break; 2611169240Sjfv } 2612169240Sjfv } 2613169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2614169240Sjfv 2615169240Sjfvout: 2616169240Sjfv return ret_val; 2617169240Sjfv} 2618169240Sjfv 2619169240Sjfv/** 2620169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 2621169589Sjfv * @hw: pointer to the HW structure 2622169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 2623169589Sjfv * @words: Size of data to write in words 2624169589Sjfv * @data: Pointer to the word(s) to write at offset. 2625169240Sjfv * 2626169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 2627169240Sjfv **/ 2628177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2629173788Sjfv u16 *data) 2630169240Sjfv{ 2631169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2632185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2633169240Sjfv s32 ret_val = E1000_SUCCESS; 2634169240Sjfv u16 i; 2635169240Sjfv 2636169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 2637169240Sjfv 2638169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2639169240Sjfv (words == 0)) { 2640169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 2641169240Sjfv ret_val = -E1000_ERR_NVM; 2642169240Sjfv goto out; 2643169240Sjfv } 2644169240Sjfv 2645200243Sjfv nvm->ops.acquire(hw); 2646169240Sjfv 2647169240Sjfv for (i = 0; i < words; i++) { 2648169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 2649169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 2650169240Sjfv } 2651169240Sjfv 2652177867Sjfv nvm->ops.release(hw); 2653169240Sjfv 2654169240Sjfvout: 2655169240Sjfv return ret_val; 2656169240Sjfv} 2657169240Sjfv 2658169240Sjfv/** 2659169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 2660169589Sjfv * @hw: pointer to the HW structure 2661169240Sjfv * 2662169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 2663169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 2664169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 2665169240Sjfv * checking for the modified bit and writing only the pending changes. 2666176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 2667169240Sjfv * future writes. 2668169240Sjfv **/ 2669177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 2670169240Sjfv{ 2671169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2672185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2673173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 2674169240Sjfv s32 ret_val; 2675169240Sjfv u16 data; 2676169240Sjfv 2677169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 2678169240Sjfv 2679169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 2680169240Sjfv if (ret_val) 2681169240Sjfv goto out; 2682169240Sjfv 2683169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 2684169240Sjfv goto out; 2685169240Sjfv 2686200243Sjfv nvm->ops.acquire(hw); 2687169240Sjfv 2688173788Sjfv /* 2689173788Sjfv * We're writing to the opposite bank so if we're on bank 1, 2690169240Sjfv * write to bank 0 etc. We also need to erase the segment that 2691173788Sjfv * is going to be written 2692173788Sjfv */ 2693173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2694190872Sjfv if (ret_val != E1000_SUCCESS) { 2695200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 2696200243Sjfv bank = 0; 2697190872Sjfv } 2698173788Sjfv 2699173788Sjfv if (bank == 0) { 2700169240Sjfv new_bank_offset = nvm->flash_bank_size; 2701169240Sjfv old_bank_offset = 0; 2702190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2703203049Sjfv if (ret_val) 2704203049Sjfv goto release; 2705169240Sjfv } else { 2706169240Sjfv old_bank_offset = nvm->flash_bank_size; 2707169240Sjfv new_bank_offset = 0; 2708190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2709203049Sjfv if (ret_val) 2710203049Sjfv goto release; 2711169240Sjfv } 2712169240Sjfv 2713169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 2714173788Sjfv /* 2715173788Sjfv * Determine whether to write the value stored 2716169240Sjfv * in the other NVM bank or a modified value stored 2717173788Sjfv * in the shadow RAM 2718173788Sjfv */ 2719173788Sjfv if (dev_spec->shadow_ram[i].modified) { 2720169240Sjfv data = dev_spec->shadow_ram[i].value; 2721169240Sjfv } else { 2722190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 2723190872Sjfv old_bank_offset, 2724190872Sjfv &data); 2725190872Sjfv if (ret_val) 2726190872Sjfv break; 2727169240Sjfv } 2728169240Sjfv 2729173788Sjfv /* 2730173788Sjfv * If the word is 0x13, then make sure the signature bits 2731169240Sjfv * (15:14) are 11b until the commit has completed. 2732169240Sjfv * This will allow us to write 10b which indicates the 2733169240Sjfv * signature is valid. We want to do this after the write 2734169240Sjfv * has completed so that we don't mark the segment valid 2735173788Sjfv * while the write is still in progress 2736173788Sjfv */ 2737169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 2738169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 2739169240Sjfv 2740169240Sjfv /* Convert offset to bytes. */ 2741169240Sjfv act_offset = (i + new_bank_offset) << 1; 2742169240Sjfv 2743169240Sjfv usec_delay(100); 2744169240Sjfv /* Write the bytes to the new bank. */ 2745169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2746169240Sjfv act_offset, 2747169240Sjfv (u8)data); 2748169240Sjfv if (ret_val) 2749169240Sjfv break; 2750169240Sjfv 2751169240Sjfv usec_delay(100); 2752169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2753169240Sjfv act_offset + 1, 2754169240Sjfv (u8)(data >> 8)); 2755169240Sjfv if (ret_val) 2756169240Sjfv break; 2757169240Sjfv } 2758169240Sjfv 2759173788Sjfv /* 2760173788Sjfv * Don't bother writing the segment valid bits if sector 2761173788Sjfv * programming failed. 2762173788Sjfv */ 2763169240Sjfv if (ret_val) { 2764169240Sjfv DEBUGOUT("Flash commit failed.\n"); 2765203049Sjfv goto release; 2766169240Sjfv } 2767169240Sjfv 2768173788Sjfv /* 2769173788Sjfv * Finally validate the new segment by setting bit 15:14 2770169240Sjfv * to 10b in word 0x13 , this can be done without an 2771169240Sjfv * erase as well since these bits are 11 to start with 2772173788Sjfv * and we need to change bit 14 to 0b 2773173788Sjfv */ 2774169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2775190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2776203049Sjfv if (ret_val) 2777203049Sjfv goto release; 2778200243Sjfv 2779169240Sjfv data &= 0xBFFF; 2780169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2781169240Sjfv act_offset * 2 + 1, 2782169240Sjfv (u8)(data >> 8)); 2783203049Sjfv if (ret_val) 2784203049Sjfv goto release; 2785169240Sjfv 2786173788Sjfv /* 2787173788Sjfv * And invalidate the previously valid segment by setting 2788169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 2789169240Sjfv * done without an erase because flash erase sets all bits 2790173788Sjfv * to 1's. We can write 1's to 0's without an erase 2791173788Sjfv */ 2792169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2793169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2794203049Sjfv if (ret_val) 2795203049Sjfv goto release; 2796169240Sjfv 2797169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 2798169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 2799169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 2800169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 2801169240Sjfv } 2802169240Sjfv 2803203049Sjfvrelease: 2804177867Sjfv nvm->ops.release(hw); 2805169240Sjfv 2806173788Sjfv /* 2807173788Sjfv * Reload the EEPROM, or else modifications will not appear 2808169240Sjfv * until after the next adapter reset. 2809169240Sjfv */ 2810203049Sjfv if (!ret_val) { 2811203049Sjfv nvm->ops.reload(hw); 2812203049Sjfv msec_delay(10); 2813203049Sjfv } 2814169240Sjfv 2815169240Sjfvout: 2816190872Sjfv if (ret_val) 2817190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 2818190872Sjfv 2819169240Sjfv return ret_val; 2820169240Sjfv} 2821169240Sjfv 2822169240Sjfv/** 2823169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 2824169589Sjfv * @hw: pointer to the HW structure 2825169240Sjfv * 2826169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 2827185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 2828185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 2829169240Sjfv **/ 2830177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 2831169240Sjfv{ 2832169240Sjfv s32 ret_val = E1000_SUCCESS; 2833169240Sjfv u16 data; 2834169240Sjfv 2835169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 2836169240Sjfv 2837173788Sjfv /* 2838173788Sjfv * Read 0x19 and check bit 6. If this bit is 0, the checksum 2839169240Sjfv * needs to be fixed. This bit is an indication that the NVM 2840169240Sjfv * was prepared by OEM software and did not calculate the 2841169240Sjfv * checksum...a likely scenario. 2842169240Sjfv */ 2843177867Sjfv ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 2844169240Sjfv if (ret_val) 2845169240Sjfv goto out; 2846169240Sjfv 2847169240Sjfv if ((data & 0x40) == 0) { 2848169240Sjfv data |= 0x40; 2849177867Sjfv ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 2850169240Sjfv if (ret_val) 2851169240Sjfv goto out; 2852177867Sjfv ret_val = hw->nvm.ops.update(hw); 2853169240Sjfv if (ret_val) 2854169240Sjfv goto out; 2855169240Sjfv } 2856169240Sjfv 2857169240Sjfv ret_val = e1000_validate_nvm_checksum_generic(hw); 2858169240Sjfv 2859169240Sjfvout: 2860169240Sjfv return ret_val; 2861169240Sjfv} 2862169240Sjfv 2863169240Sjfv/** 2864169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 2865169589Sjfv * @hw: pointer to the HW structure 2866169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 2867169589Sjfv * @size: Size of data to read, 1=byte 2=word 2868169589Sjfv * @data: The byte(s) to write to the NVM. 2869169240Sjfv * 2870169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 2871169240Sjfv **/ 2872173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2873173788Sjfv u8 size, u16 data) 2874169240Sjfv{ 2875169240Sjfv union ich8_hws_flash_status hsfsts; 2876169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2877169240Sjfv u32 flash_linear_addr; 2878169240Sjfv u32 flash_data = 0; 2879169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2880169240Sjfv u8 count = 0; 2881169240Sjfv 2882169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 2883169240Sjfv 2884169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 2885169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 2886169240Sjfv goto out; 2887169240Sjfv 2888169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2889169240Sjfv hw->nvm.flash_base_addr; 2890169240Sjfv 2891169240Sjfv do { 2892169240Sjfv usec_delay(1); 2893169240Sjfv /* Steps */ 2894169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2895169240Sjfv if (ret_val != E1000_SUCCESS) 2896169240Sjfv break; 2897169240Sjfv 2898169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2899169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2900185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 2901169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 2902169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2903169240Sjfv 2904169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 2905169240Sjfv 2906169240Sjfv if (size == 1) 2907169240Sjfv flash_data = (u32)data & 0x00FF; 2908169240Sjfv else 2909169240Sjfv flash_data = (u32)data; 2910169240Sjfv 2911169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 2912169240Sjfv 2913173788Sjfv /* 2914173788Sjfv * check if FCERR is set to 1 , if set to 1, clear it 2915173788Sjfv * and try the whole sequence a few more times else done 2916173788Sjfv */ 2917169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2918169240Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 2919185353Sjfv if (ret_val == E1000_SUCCESS) 2920169240Sjfv break; 2921185353Sjfv 2922185353Sjfv /* 2923185353Sjfv * If we're here, then things are most likely 2924185353Sjfv * completely hosed, but if the error condition 2925185353Sjfv * is detected, it won't hurt to give it another 2926185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 2927185353Sjfv */ 2928185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2929200243Sjfv if (hsfsts.hsf_status.flcerr == 1) 2930185353Sjfv /* Repeat for some time before giving up. */ 2931185353Sjfv continue; 2932200243Sjfv if (hsfsts.hsf_status.flcdone == 0) { 2933185353Sjfv DEBUGOUT("Timeout error - flash cycle " 2934185353Sjfv "did not complete."); 2935185353Sjfv break; 2936169240Sjfv } 2937169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2938169240Sjfv 2939169240Sjfvout: 2940169240Sjfv return ret_val; 2941169240Sjfv} 2942169240Sjfv 2943169240Sjfv/** 2944169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 2945169589Sjfv * @hw: pointer to the HW structure 2946169589Sjfv * @offset: The index of the byte to read. 2947169589Sjfv * @data: The byte to write to the NVM. 2948169240Sjfv * 2949169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2950169240Sjfv **/ 2951177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2952173788Sjfv u8 data) 2953169240Sjfv{ 2954169240Sjfv u16 word = (u16)data; 2955169240Sjfv 2956169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 2957169240Sjfv 2958169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 2959169240Sjfv} 2960169240Sjfv 2961169240Sjfv/** 2962169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 2963169589Sjfv * @hw: pointer to the HW structure 2964169589Sjfv * @offset: The offset of the byte to write. 2965169589Sjfv * @byte: The byte to write to the NVM. 2966169240Sjfv * 2967169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2968169240Sjfv * Goes through a retry algorithm before giving up. 2969169240Sjfv **/ 2970176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 2971176667Sjfv u32 offset, u8 byte) 2972169240Sjfv{ 2973169240Sjfv s32 ret_val; 2974169240Sjfv u16 program_retries; 2975169240Sjfv 2976169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 2977169240Sjfv 2978169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2979173788Sjfv if (ret_val == E1000_SUCCESS) 2980169240Sjfv goto out; 2981169240Sjfv 2982169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 2983169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 2984169240Sjfv usec_delay(100); 2985169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2986169240Sjfv if (ret_val == E1000_SUCCESS) 2987169240Sjfv break; 2988169240Sjfv } 2989169240Sjfv if (program_retries == 100) { 2990169240Sjfv ret_val = -E1000_ERR_NVM; 2991169240Sjfv goto out; 2992169240Sjfv } 2993169240Sjfv 2994169240Sjfvout: 2995169240Sjfv return ret_val; 2996169240Sjfv} 2997169240Sjfv 2998169240Sjfv/** 2999169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 3000169589Sjfv * @hw: pointer to the HW structure 3001169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 3002169240Sjfv * 3003169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 3004169240Sjfv * bank N is 4096 * N + flash_reg_addr. 3005169240Sjfv **/ 3006177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 3007169240Sjfv{ 3008169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3009169240Sjfv union ich8_hws_flash_status hsfsts; 3010169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3011169240Sjfv u32 flash_linear_addr; 3012173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 3013173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 3014185353Sjfv s32 ret_val = E1000_SUCCESS; 3015185353Sjfv s32 count = 0; 3016185353Sjfv s32 j, iteration, sector_size; 3017169240Sjfv 3018169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 3019169240Sjfv 3020169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3021169240Sjfv 3022173788Sjfv /* 3023173788Sjfv * Determine HW Sector size: Read BERASE bits of hw flash status 3024173788Sjfv * register 3025173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 3026169240Sjfv * consecutive sectors. The start index for the nth Hw sector 3027169240Sjfv * can be calculated as = bank * 4096 + n * 256 3028169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 3029169240Sjfv * The start index for the nth Hw sector can be calculated 3030169240Sjfv * as = bank * 4096 3031169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 3032169240Sjfv * (ich9 only, otherwise error condition) 3033169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 3034169240Sjfv */ 3035169240Sjfv switch (hsfsts.hsf_status.berasesz) { 3036169240Sjfv case 0: 3037169240Sjfv /* Hw sector size 256 */ 3038169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 3039169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 3040169240Sjfv break; 3041169240Sjfv case 1: 3042169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 3043194865Sjfv iteration = 1; 3044169240Sjfv break; 3045169240Sjfv case 2: 3046195850Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 3047195850Sjfv iteration = 1; 3048169240Sjfv break; 3049169240Sjfv case 3: 3050169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 3051194865Sjfv iteration = 1; 3052169240Sjfv break; 3053169240Sjfv default: 3054169240Sjfv ret_val = -E1000_ERR_NVM; 3055169240Sjfv goto out; 3056169240Sjfv } 3057169240Sjfv 3058169240Sjfv /* Start with the base address, then add the sector offset. */ 3059169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 3060200243Sjfv flash_linear_addr += (bank) ? flash_bank_size : 0; 3061169240Sjfv 3062169240Sjfv for (j = 0; j < iteration ; j++) { 3063169240Sjfv do { 3064169240Sjfv /* Steps */ 3065169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3066169240Sjfv if (ret_val) 3067169240Sjfv goto out; 3068169240Sjfv 3069173788Sjfv /* 3070173788Sjfv * Write a value 11 (block Erase) in Flash 3071173788Sjfv * Cycle field in hw flash control 3072173788Sjfv */ 3073169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 3074169240Sjfv ICH_FLASH_HSFCTL); 3075169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3076185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 3077169240Sjfv hsflctl.regval); 3078169240Sjfv 3079173788Sjfv /* 3080173788Sjfv * Write the last 24 bits of an index within the 3081169240Sjfv * block into Flash Linear address field in Flash 3082169240Sjfv * Address. 3083169240Sjfv */ 3084169240Sjfv flash_linear_addr += (j * sector_size); 3085185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 3086169240Sjfv flash_linear_addr); 3087169240Sjfv 3088169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3089169240Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 3090185353Sjfv if (ret_val == E1000_SUCCESS) 3091169240Sjfv break; 3092185353Sjfv 3093185353Sjfv /* 3094185353Sjfv * Check if FCERR is set to 1. If 1, 3095185353Sjfv * clear it and try the whole sequence 3096185353Sjfv * a few more times else Done 3097185353Sjfv */ 3098185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3099185353Sjfv ICH_FLASH_HSFSTS); 3100185353Sjfv if (hsfsts.hsf_status.flcerr == 1) 3101185353Sjfv /* repeat for some time before giving up */ 3102185353Sjfv continue; 3103185353Sjfv else if (hsfsts.hsf_status.flcdone == 0) 3104185353Sjfv goto out; 3105169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 3106169240Sjfv } 3107169240Sjfv 3108169240Sjfvout: 3109169240Sjfv return ret_val; 3110169240Sjfv} 3111169240Sjfv 3112169240Sjfv/** 3113169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 3114169589Sjfv * @hw: pointer to the HW structure 3115169589Sjfv * @data: Pointer to the LED settings 3116169240Sjfv * 3117169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 3118169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 3119169240Sjfv * setting. 3120169240Sjfv **/ 3121177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 3122169240Sjfv{ 3123169240Sjfv s32 ret_val; 3124169240Sjfv 3125169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 3126169240Sjfv 3127177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 3128169240Sjfv if (ret_val) { 3129169240Sjfv DEBUGOUT("NVM Read Error\n"); 3130169240Sjfv goto out; 3131169240Sjfv } 3132169240Sjfv 3133169240Sjfv if (*data == ID_LED_RESERVED_0000 || 3134169240Sjfv *data == ID_LED_RESERVED_FFFF) 3135169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 3136169240Sjfv 3137169240Sjfvout: 3138169240Sjfv return ret_val; 3139169240Sjfv} 3140169240Sjfv 3141169240Sjfv/** 3142194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 3143194865Sjfv * @hw: pointer to the HW structure 3144194865Sjfv * 3145194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 3146194865Sjfv * the PHY LED configuration register. 3147194865Sjfv * 3148194865Sjfv * PCH also does not have an "always on" or "always off" mode which 3149194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 3150194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 3151194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 3152194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 3153194865Sjfv **/ 3154194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 3155194865Sjfv{ 3156194865Sjfv struct e1000_mac_info *mac = &hw->mac; 3157194865Sjfv s32 ret_val; 3158194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 3159194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 3160194865Sjfv u16 data, i, temp, shift; 3161194865Sjfv 3162194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 3163194865Sjfv 3164194865Sjfv /* Get default ID LED modes */ 3165194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 3166194865Sjfv if (ret_val) 3167194865Sjfv goto out; 3168194865Sjfv 3169194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 3170194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 3171194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 3172194865Sjfv 3173194865Sjfv for (i = 0; i < 4; i++) { 3174194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 3175194865Sjfv shift = (i * 5); 3176194865Sjfv switch (temp) { 3177194865Sjfv case ID_LED_ON1_DEF2: 3178194865Sjfv case ID_LED_ON1_ON2: 3179194865Sjfv case ID_LED_ON1_OFF2: 3180194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3181194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 3182194865Sjfv break; 3183194865Sjfv case ID_LED_OFF1_DEF2: 3184194865Sjfv case ID_LED_OFF1_ON2: 3185194865Sjfv case ID_LED_OFF1_OFF2: 3186194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3187194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 3188194865Sjfv break; 3189194865Sjfv default: 3190194865Sjfv /* Do nothing */ 3191194865Sjfv break; 3192194865Sjfv } 3193194865Sjfv switch (temp) { 3194194865Sjfv case ID_LED_DEF1_ON2: 3195194865Sjfv case ID_LED_ON1_ON2: 3196194865Sjfv case ID_LED_OFF1_ON2: 3197194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3198194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 3199194865Sjfv break; 3200194865Sjfv case ID_LED_DEF1_OFF2: 3201194865Sjfv case ID_LED_ON1_OFF2: 3202194865Sjfv case ID_LED_OFF1_OFF2: 3203194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3204194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 3205194865Sjfv break; 3206194865Sjfv default: 3207194865Sjfv /* Do nothing */ 3208194865Sjfv break; 3209194865Sjfv } 3210194865Sjfv } 3211194865Sjfv 3212194865Sjfvout: 3213194865Sjfv return ret_val; 3214194865Sjfv} 3215194865Sjfv 3216194865Sjfv/** 3217169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 3218169589Sjfv * @hw: pointer to the HW structure 3219169240Sjfv * 3220169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 3221169240Sjfv * register, so the the bus width is hard coded. 3222169240Sjfv **/ 3223177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 3224169240Sjfv{ 3225169240Sjfv struct e1000_bus_info *bus = &hw->bus; 3226169240Sjfv s32 ret_val; 3227169240Sjfv 3228169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 3229169240Sjfv 3230169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 3231169240Sjfv 3232173788Sjfv /* 3233173788Sjfv * ICH devices are "PCI Express"-ish. They have 3234169240Sjfv * a configuration space, but do not contain 3235169240Sjfv * PCI Express Capability registers, so bus width 3236169240Sjfv * must be hardcoded. 3237169240Sjfv */ 3238169240Sjfv if (bus->width == e1000_bus_width_unknown) 3239169240Sjfv bus->width = e1000_bus_width_pcie_x1; 3240169240Sjfv 3241169240Sjfv return ret_val; 3242169240Sjfv} 3243169240Sjfv 3244169240Sjfv/** 3245169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 3246169589Sjfv * @hw: pointer to the HW structure 3247169240Sjfv * 3248169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 3249169240Sjfv * MAC. 3250169240Sjfv **/ 3251177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 3252169240Sjfv{ 3253200243Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3254200243Sjfv u16 reg; 3255218588Sjfv u32 ctrl, kab; 3256169240Sjfv s32 ret_val; 3257169240Sjfv 3258169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 3259169240Sjfv 3260173788Sjfv /* 3261173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 3262169240Sjfv * on the last TLP read/write transaction when MAC is reset. 3263169240Sjfv */ 3264169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 3265185353Sjfv if (ret_val) 3266169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 3267169240Sjfv 3268169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 3269169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3270169240Sjfv 3271173788Sjfv /* 3272173788Sjfv * Disable the Transmit and Receive units. Then delay to allow 3273169240Sjfv * any pending transactions to complete before we hit the MAC 3274169240Sjfv * with the global reset. 3275169240Sjfv */ 3276169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 3277169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 3278169240Sjfv E1000_WRITE_FLUSH(hw); 3279169240Sjfv 3280169240Sjfv msec_delay(10); 3281169240Sjfv 3282169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 3283169240Sjfv if (hw->mac.type == e1000_ich8lan) { 3284169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 3285169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 3286169240Sjfv /* Set Packet Buffer Size to 16k. */ 3287169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 3288169240Sjfv } 3289169240Sjfv 3290200243Sjfv if (hw->mac.type == e1000_pchlan) { 3291200243Sjfv /* Save the NVM K1 bit setting*/ 3292200243Sjfv ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); 3293200243Sjfv if (ret_val) 3294200243Sjfv return ret_val; 3295200243Sjfv 3296200243Sjfv if (reg & E1000_NVM_K1_ENABLE) 3297200243Sjfv dev_spec->nvm_k1_enabled = TRUE; 3298200243Sjfv else 3299200243Sjfv dev_spec->nvm_k1_enabled = FALSE; 3300200243Sjfv } 3301200243Sjfv 3302169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 3303169240Sjfv 3304213234Sjfv if (!hw->phy.ops.check_reset_block(hw)) { 3305173788Sjfv /* 3306213234Sjfv * Full-chip reset requires MAC and PHY reset at the same 3307169240Sjfv * time to make sure the interface between MAC and the 3308169240Sjfv * external PHY is reset. 3309169240Sjfv */ 3310169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 3311213234Sjfv 3312213234Sjfv /* 3313213234Sjfv * Gate automatic PHY configuration by hardware on 3314213234Sjfv * non-managed 82579 3315213234Sjfv */ 3316213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 3317213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3318213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3319169240Sjfv } 3320169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 3321185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 3322169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 3323169240Sjfv msec_delay(20); 3324169240Sjfv 3325194865Sjfv if (!ret_val) 3326194865Sjfv e1000_release_swflag_ich8lan(hw); 3327194865Sjfv 3328213234Sjfv if (ctrl & E1000_CTRL_PHY_RST) { 3329213234Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 3330203049Sjfv if (ret_val) 3331203049Sjfv goto out; 3332203049Sjfv 3333213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 3334213234Sjfv if (ret_val) 3335213234Sjfv goto out; 3336169240Sjfv } 3337169240Sjfv 3338200243Sjfv /* 3339200243Sjfv * For PCH, this write will make sure that any noise 3340200243Sjfv * will be detected as a CRC error and be dropped rather than show up 3341200243Sjfv * as a bad packet to the DMA engine. 3342200243Sjfv */ 3343200243Sjfv if (hw->mac.type == e1000_pchlan) 3344200243Sjfv E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 3345200243Sjfv 3346169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3347218588Sjfv E1000_READ_REG(hw, E1000_ICR); 3348169240Sjfv 3349169240Sjfv kab = E1000_READ_REG(hw, E1000_KABGTXD); 3350169240Sjfv kab |= E1000_KABGTXD_BGSQLBIAS; 3351169240Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 3352169240Sjfv 3353200243Sjfvout: 3354169240Sjfv return ret_val; 3355169240Sjfv} 3356169240Sjfv 3357169240Sjfv/** 3358169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 3359169589Sjfv * @hw: pointer to the HW structure 3360169240Sjfv * 3361169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 3362169240Sjfv * - initialize hardware bits 3363169240Sjfv * - initialize LED identification 3364169240Sjfv * - setup receive address registers 3365169240Sjfv * - setup flow control 3366176667Sjfv * - setup transmit descriptors 3367169240Sjfv * - clear statistics 3368169240Sjfv **/ 3369177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3370169240Sjfv{ 3371169240Sjfv struct e1000_mac_info *mac = &hw->mac; 3372169240Sjfv u32 ctrl_ext, txdctl, snoop; 3373169240Sjfv s32 ret_val; 3374169240Sjfv u16 i; 3375169240Sjfv 3376169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 3377169240Sjfv 3378169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 3379169240Sjfv 3380169240Sjfv /* Initialize identification LED */ 3381190872Sjfv ret_val = mac->ops.id_led_init(hw); 3382190872Sjfv if (ret_val) 3383200243Sjfv DEBUGOUT("Error initializing identification LED\n"); 3384190872Sjfv /* This is not fatal and we should not stop init due to this */ 3385169240Sjfv 3386169240Sjfv /* Setup the receive address. */ 3387169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 3388169240Sjfv 3389169240Sjfv /* Zero out the Multicast HASH table */ 3390169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 3391169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 3392169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3393169240Sjfv 3394194865Sjfv /* 3395194865Sjfv * The 82578 Rx buffer will stall if wakeup is enabled in host and 3396194865Sjfv * the ME. Reading the BM_WUC register will clear the host wakeup bit. 3397194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 3398194865Sjfv */ 3399194865Sjfv if (hw->phy.type == e1000_phy_82578) { 3400194865Sjfv hw->phy.ops.read_reg(hw, BM_WUC, &i); 3401194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 3402194865Sjfv if (ret_val) 3403194865Sjfv return ret_val; 3404194865Sjfv } 3405194865Sjfv 3406169240Sjfv /* Setup link and flow control */ 3407177867Sjfv ret_val = mac->ops.setup_link(hw); 3408169240Sjfv 3409169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 3410173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 3411169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3412169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3413169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3414169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3415173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 3416173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 3417169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3418169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3419169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3420169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3421173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 3422169240Sjfv 3423173788Sjfv /* 3424173788Sjfv * ICH8 has opposite polarity of no_snoop bits. 3425173788Sjfv * By default, we should use snoop behavior. 3426173788Sjfv */ 3427169240Sjfv if (mac->type == e1000_ich8lan) 3428169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 3429169240Sjfv else 3430200243Sjfv snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 3431169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 3432169240Sjfv 3433169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3434169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3435169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3436169240Sjfv 3437173788Sjfv /* 3438173788Sjfv * Clear all of the statistics registers (clear on read). It is 3439169240Sjfv * important that we do this after we have tried to establish link 3440169240Sjfv * because the symbol error count will increment wildly if there 3441169240Sjfv * is no link. 3442169240Sjfv */ 3443169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 3444169240Sjfv 3445169240Sjfv return ret_val; 3446169240Sjfv} 3447169240Sjfv/** 3448169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3449169589Sjfv * @hw: pointer to the HW structure 3450169240Sjfv * 3451169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 3452169240Sjfv * hardware for transmit and receive. 3453169240Sjfv **/ 3454173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3455169240Sjfv{ 3456169240Sjfv u32 reg; 3457169240Sjfv 3458169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 3459169240Sjfv 3460169240Sjfv /* Extended Device Control */ 3461169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3462169240Sjfv reg |= (1 << 22); 3463194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 3464194865Sjfv if (hw->mac.type >= e1000_pchlan) 3465194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 3466169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3467169240Sjfv 3468169240Sjfv /* Transmit Descriptor Control 0 */ 3469173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 3470169240Sjfv reg |= (1 << 22); 3471173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 3472169240Sjfv 3473169240Sjfv /* Transmit Descriptor Control 1 */ 3474173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 3475169240Sjfv reg |= (1 << 22); 3476173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 3477169240Sjfv 3478169240Sjfv /* Transmit Arbitration Control 0 */ 3479173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 3480169240Sjfv if (hw->mac.type == e1000_ich8lan) 3481169240Sjfv reg |= (1 << 28) | (1 << 29); 3482169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 3483173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3484169240Sjfv 3485169240Sjfv /* Transmit Arbitration Control 1 */ 3486173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 3487169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 3488169240Sjfv reg &= ~(1 << 28); 3489169240Sjfv else 3490169240Sjfv reg |= (1 << 28); 3491169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 3492173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 3493169240Sjfv 3494169240Sjfv /* Device Status */ 3495169240Sjfv if (hw->mac.type == e1000_ich8lan) { 3496169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 3497169240Sjfv reg &= ~(1 << 31); 3498169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 3499169240Sjfv } 3500169240Sjfv 3501205869Sjfv /* 3502205869Sjfv * work-around descriptor data corruption issue during nfs v2 udp 3503205869Sjfv * traffic, just disable the nfs filtering capability 3504205869Sjfv */ 3505205869Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 3506205869Sjfv reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3507205869Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 3508205869Sjfv 3509169240Sjfv return; 3510169240Sjfv} 3511169240Sjfv 3512169240Sjfv/** 3513169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 3514169589Sjfv * @hw: pointer to the HW structure 3515169240Sjfv * 3516169240Sjfv * Determines which flow control settings to use, then configures flow 3517169240Sjfv * control. Calls the appropriate media-specific link configuration 3518169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 3519169240Sjfv * should be established. Assumes the hardware has previously been reset 3520169240Sjfv * and the transmitter and receiver are not enabled. 3521169240Sjfv **/ 3522177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 3523169240Sjfv{ 3524169240Sjfv s32 ret_val = E1000_SUCCESS; 3525169240Sjfv 3526169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 3527169240Sjfv 3528177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 3529169240Sjfv goto out; 3530169240Sjfv 3531173788Sjfv /* 3532173788Sjfv * ICH parts do not have a word in the NVM to determine 3533169240Sjfv * the default flow control setting, so we explicitly 3534169240Sjfv * set it to full. 3535169240Sjfv */ 3536185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 3537185353Sjfv hw->fc.requested_mode = e1000_fc_full; 3538169240Sjfv 3539185353Sjfv /* 3540185353Sjfv * Save off the requested flow control mode for use later. Depending 3541185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 3542185353Sjfv */ 3543185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 3544169240Sjfv 3545185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 3546190872Sjfv hw->fc.current_mode); 3547169240Sjfv 3548169240Sjfv /* Continue to configure the copper link. */ 3549177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 3550169240Sjfv if (ret_val) 3551169240Sjfv goto out; 3552169240Sjfv 3553173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 3554194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 3555213234Sjfv (hw->phy.type == e1000_phy_82579) || 3556194865Sjfv (hw->phy.type == e1000_phy_82577)) { 3557213234Sjfv E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 3558213234Sjfv 3559194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 3560194865Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 3561194865Sjfv hw->fc.pause_time); 3562194865Sjfv if (ret_val) 3563194865Sjfv goto out; 3564194865Sjfv } 3565169240Sjfv 3566169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 3567169240Sjfv 3568169240Sjfvout: 3569169240Sjfv return ret_val; 3570169240Sjfv} 3571169240Sjfv 3572169240Sjfv/** 3573169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 3574169589Sjfv * @hw: pointer to the HW structure 3575169240Sjfv * 3576169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 3577169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 3578169240Sjfv * configuring the copper link. 3579169240Sjfv **/ 3580177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 3581169240Sjfv{ 3582169240Sjfv u32 ctrl; 3583169240Sjfv s32 ret_val; 3584169240Sjfv u16 reg_data; 3585169240Sjfv 3586169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 3587169240Sjfv 3588169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 3589169240Sjfv ctrl |= E1000_CTRL_SLU; 3590169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3591169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3592169240Sjfv 3593173788Sjfv /* 3594173788Sjfv * Set the mac to wait the maximum time between each iteration 3595169240Sjfv * and increase the max iterations when polling the phy; 3596173788Sjfv * this fixes erroneous timeouts at 10Mbps. 3597173788Sjfv */ 3598200243Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 3599181027Sjfv 0xFFFF); 3600169240Sjfv if (ret_val) 3601169240Sjfv goto out; 3602194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 3603194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 3604181027Sjfv ®_data); 3605169240Sjfv if (ret_val) 3606169240Sjfv goto out; 3607169240Sjfv reg_data |= 0x3F; 3608194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3609194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 3610181027Sjfv reg_data); 3611169240Sjfv if (ret_val) 3612169240Sjfv goto out; 3613169240Sjfv 3614190872Sjfv switch (hw->phy.type) { 3615190872Sjfv case e1000_phy_igp_3: 3616169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 3617169240Sjfv if (ret_val) 3618169240Sjfv goto out; 3619190872Sjfv break; 3620190872Sjfv case e1000_phy_bm: 3621194865Sjfv case e1000_phy_82578: 3622176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 3623176667Sjfv if (ret_val) 3624176667Sjfv goto out; 3625190872Sjfv break; 3626194865Sjfv case e1000_phy_82577: 3627213234Sjfv case e1000_phy_82579: 3628194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 3629194865Sjfv if (ret_val) 3630194865Sjfv goto out; 3631194865Sjfv break; 3632190872Sjfv case e1000_phy_ife: 3633177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 3634177867Sjfv ®_data); 3635173788Sjfv if (ret_val) 3636173788Sjfv goto out; 3637173788Sjfv 3638173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 3639173788Sjfv 3640173788Sjfv switch (hw->phy.mdix) { 3641173788Sjfv case 1: 3642173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 3643173788Sjfv break; 3644173788Sjfv case 2: 3645173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 3646173788Sjfv break; 3647173788Sjfv case 0: 3648173788Sjfv default: 3649173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 3650173788Sjfv break; 3651173788Sjfv } 3652177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 3653177867Sjfv reg_data); 3654173788Sjfv if (ret_val) 3655173788Sjfv goto out; 3656190872Sjfv break; 3657190872Sjfv default: 3658190872Sjfv break; 3659173788Sjfv } 3660169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 3661169240Sjfv 3662169240Sjfvout: 3663169240Sjfv return ret_val; 3664169240Sjfv} 3665169240Sjfv 3666169240Sjfv/** 3667169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 3668169589Sjfv * @hw: pointer to the HW structure 3669169589Sjfv * @speed: pointer to store current link speed 3670169589Sjfv * @duplex: pointer to store the current link duplex 3671169240Sjfv * 3672176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 3673169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 3674169240Sjfv * gigabit speeds. 3675169240Sjfv **/ 3676177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 3677173788Sjfv u16 *duplex) 3678169240Sjfv{ 3679169240Sjfv s32 ret_val; 3680169240Sjfv 3681169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 3682169240Sjfv 3683169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 3684169240Sjfv if (ret_val) 3685169240Sjfv goto out; 3686169240Sjfv 3687169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 3688169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 3689169240Sjfv (*speed == SPEED_1000)) { 3690169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 3691169240Sjfv } 3692169240Sjfv 3693169240Sjfvout: 3694169240Sjfv return ret_val; 3695169240Sjfv} 3696169240Sjfv 3697169240Sjfv/** 3698169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 3699169589Sjfv * @hw: pointer to the HW structure 3700169240Sjfv * 3701169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 3702169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 3703169240Sjfv * speed is gigabit- 3704169240Sjfv * 0) if workaround is optionally disabled do nothing 3705169240Sjfv * 1) wait 1ms for Kumeran link to come up 3706169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 3707169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 3708169240Sjfv * 4) reset the PHY 3709169240Sjfv * 5) repeat up to 10 times 3710169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 3711169240Sjfv **/ 3712173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3713169240Sjfv{ 3714185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3715169240Sjfv u32 phy_ctrl; 3716169240Sjfv s32 ret_val = E1000_SUCCESS; 3717169240Sjfv u16 i, data; 3718173788Sjfv bool link; 3719169240Sjfv 3720169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 3721169240Sjfv 3722218588Sjfv if (!dev_spec->kmrn_lock_loss_workaround_enabled) 3723169240Sjfv goto out; 3724169240Sjfv 3725173788Sjfv /* 3726173788Sjfv * Make sure link is up before proceeding. If not just return. 3727169240Sjfv * Attempting this while link is negotiating fouled up link 3728173788Sjfv * stability 3729173788Sjfv */ 3730169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3731169240Sjfv if (!link) { 3732169240Sjfv ret_val = E1000_SUCCESS; 3733169240Sjfv goto out; 3734169240Sjfv } 3735169240Sjfv 3736169240Sjfv for (i = 0; i < 10; i++) { 3737169240Sjfv /* read once to clear */ 3738177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3739169240Sjfv if (ret_val) 3740169240Sjfv goto out; 3741169240Sjfv /* and again to get new status */ 3742177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3743169240Sjfv if (ret_val) 3744169240Sjfv goto out; 3745169240Sjfv 3746169240Sjfv /* check for PCS lock */ 3747169240Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 3748169240Sjfv ret_val = E1000_SUCCESS; 3749169240Sjfv goto out; 3750169240Sjfv } 3751169240Sjfv 3752169240Sjfv /* Issue PHY reset */ 3753177867Sjfv hw->phy.ops.reset(hw); 3754169240Sjfv msec_delay_irq(5); 3755169240Sjfv } 3756169240Sjfv /* Disable GigE link negotiation */ 3757169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3758169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 3759169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3760169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3761169240Sjfv 3762173788Sjfv /* 3763176667Sjfv * Call gig speed drop workaround on Gig disable before accessing 3764173788Sjfv * any PHY registers 3765173788Sjfv */ 3766169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3767169240Sjfv 3768169240Sjfv /* unable to acquire PCS lock */ 3769169240Sjfv ret_val = -E1000_ERR_PHY; 3770169240Sjfv 3771169240Sjfvout: 3772169240Sjfv return ret_val; 3773169240Sjfv} 3774169240Sjfv 3775169240Sjfv/** 3776176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 3777169589Sjfv * @hw: pointer to the HW structure 3778176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 3779169240Sjfv * 3780169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 3781169240Sjfv * /disabled - FALSE). 3782169240Sjfv **/ 3783173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3784173788Sjfv bool state) 3785169240Sjfv{ 3786185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3787169240Sjfv 3788169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 3789169240Sjfv 3790169240Sjfv if (hw->mac.type != e1000_ich8lan) { 3791169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 3792185353Sjfv return; 3793169240Sjfv } 3794169240Sjfv 3795169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 3796169240Sjfv 3797169240Sjfv return; 3798169240Sjfv} 3799169240Sjfv 3800169240Sjfv/** 3801169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 3802169589Sjfv * @hw: pointer to the HW structure 3803169240Sjfv * 3804169240Sjfv * Workaround for 82566 power-down on D3 entry: 3805169240Sjfv * 1) disable gigabit link 3806169240Sjfv * 2) write VR power-down enable 3807169240Sjfv * 3) read it back 3808169240Sjfv * Continue if successful, else issue LCD reset and repeat 3809169240Sjfv **/ 3810173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 3811169240Sjfv{ 3812169240Sjfv u32 reg; 3813169240Sjfv u16 data; 3814169240Sjfv u8 retry = 0; 3815169240Sjfv 3816169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 3817169240Sjfv 3818169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 3819169240Sjfv goto out; 3820169240Sjfv 3821169240Sjfv /* Try the workaround twice (if needed) */ 3822169240Sjfv do { 3823169240Sjfv /* Disable link */ 3824169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 3825169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 3826169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3827169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 3828169240Sjfv 3829173788Sjfv /* 3830176667Sjfv * Call gig speed drop workaround on Gig disable before 3831173788Sjfv * accessing any PHY registers 3832173788Sjfv */ 3833169240Sjfv if (hw->mac.type == e1000_ich8lan) 3834169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3835169240Sjfv 3836169240Sjfv /* Write VR power-down enable */ 3837177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3838169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3839185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 3840169240Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 3841169240Sjfv 3842169240Sjfv /* Read it back and test */ 3843177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3844169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3845169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 3846169240Sjfv break; 3847169240Sjfv 3848169240Sjfv /* Issue PHY reset and repeat at most one more time */ 3849169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 3850169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 3851169240Sjfv retry++; 3852169240Sjfv } while (retry); 3853169240Sjfv 3854169240Sjfvout: 3855169240Sjfv return; 3856169240Sjfv} 3857169240Sjfv 3858169240Sjfv/** 3859169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 3860169589Sjfv * @hw: pointer to the HW structure 3861169240Sjfv * 3862169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 3863176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 3864169240Sjfv * 1) Set Kumeran Near-end loopback 3865169240Sjfv * 2) Clear Kumeran Near-end loopback 3866169240Sjfv * Should only be called for ICH8[m] devices with IGP_3 Phy. 3867169240Sjfv **/ 3868173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 3869169240Sjfv{ 3870169240Sjfv s32 ret_val = E1000_SUCCESS; 3871169240Sjfv u16 reg_data; 3872169240Sjfv 3873169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 3874169240Sjfv 3875169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 3876169240Sjfv (hw->phy.type != e1000_phy_igp_3)) 3877169240Sjfv goto out; 3878169240Sjfv 3879181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3880181027Sjfv ®_data); 3881169240Sjfv if (ret_val) 3882169240Sjfv goto out; 3883169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 3884181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3885181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3886181027Sjfv reg_data); 3887169240Sjfv if (ret_val) 3888169240Sjfv goto out; 3889169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 3890181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3891181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3892181027Sjfv reg_data); 3893169240Sjfvout: 3894169240Sjfv return; 3895169240Sjfv} 3896169240Sjfv 3897169240Sjfv/** 3898176667Sjfv * e1000_disable_gig_wol_ich8lan - disable gig during WoL 3899176667Sjfv * @hw: pointer to the HW structure 3900176667Sjfv * 3901176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 3902176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 3903176667Sjfv * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 3904176667Sjfv * to a lower speed. 3905176667Sjfv * 3906190872Sjfv * Should only be called for applicable parts. 3907176667Sjfv **/ 3908176667Sjfvvoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 3909176667Sjfv{ 3910176667Sjfv u32 phy_ctrl; 3911213234Sjfv s32 ret_val; 3912176667Sjfv 3913213234Sjfv DEBUGFUNC("e1000_disable_gig_wol_ich8lan"); 3914194865Sjfv 3915213234Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3916213234Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE; 3917213234Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3918213234Sjfv 3919213234Sjfv if (hw->mac.type >= e1000_pchlan) { 3920213234Sjfv e1000_oem_bits_config_ich8lan(hw, FALSE); 3921213234Sjfv ret_val = hw->phy.ops.acquire(hw); 3922213234Sjfv if (ret_val) 3923213234Sjfv return; 3924213234Sjfv e1000_write_smbus_addr(hw); 3925213234Sjfv hw->phy.ops.release(hw); 3926176667Sjfv } 3927176667Sjfv 3928176667Sjfv return; 3929176667Sjfv} 3930176667Sjfv 3931176667Sjfv/** 3932169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 3933169589Sjfv * @hw: pointer to the HW structure 3934169240Sjfv * 3935169240Sjfv * Return the LED back to the default configuration. 3936169240Sjfv **/ 3937177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 3938169240Sjfv{ 3939169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 3940169240Sjfv 3941169240Sjfv if (hw->phy.type == e1000_phy_ife) 3942203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3943203049Sjfv 0); 3944169240Sjfv 3945203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 3946203049Sjfv return E1000_SUCCESS; 3947169240Sjfv} 3948169240Sjfv 3949169240Sjfv/** 3950176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 3951169589Sjfv * @hw: pointer to the HW structure 3952169240Sjfv * 3953176667Sjfv * Turn on the LEDs. 3954169240Sjfv **/ 3955177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 3956169240Sjfv{ 3957169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 3958169240Sjfv 3959169240Sjfv if (hw->phy.type == e1000_phy_ife) 3960203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3961169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 3962169240Sjfv 3963203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 3964203049Sjfv return E1000_SUCCESS; 3965169240Sjfv} 3966169240Sjfv 3967169240Sjfv/** 3968176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 3969169589Sjfv * @hw: pointer to the HW structure 3970169240Sjfv * 3971176667Sjfv * Turn off the LEDs. 3972169240Sjfv **/ 3973177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 3974169240Sjfv{ 3975169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 3976169240Sjfv 3977169240Sjfv if (hw->phy.type == e1000_phy_ife) 3978203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3979169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3980169240Sjfv 3981203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 3982203049Sjfv return E1000_SUCCESS; 3983169240Sjfv} 3984169240Sjfv 3985169240Sjfv/** 3986194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 3987194865Sjfv * @hw: pointer to the HW structure 3988194865Sjfv * 3989194865Sjfv * This prepares the SW controllable LED for use. 3990194865Sjfv **/ 3991194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3992194865Sjfv{ 3993194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 3994194865Sjfv 3995194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3996194865Sjfv (u16)hw->mac.ledctl_mode1); 3997194865Sjfv} 3998194865Sjfv 3999194865Sjfv/** 4000194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 4001194865Sjfv * @hw: pointer to the HW structure 4002194865Sjfv * 4003194865Sjfv * Return the LED back to the default configuration. 4004194865Sjfv **/ 4005194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 4006194865Sjfv{ 4007194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 4008194865Sjfv 4009194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 4010194865Sjfv (u16)hw->mac.ledctl_default); 4011194865Sjfv} 4012194865Sjfv 4013194865Sjfv/** 4014194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 4015194865Sjfv * @hw: pointer to the HW structure 4016194865Sjfv * 4017194865Sjfv * Turn on the LEDs. 4018194865Sjfv **/ 4019194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 4020194865Sjfv{ 4021194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 4022194865Sjfv u32 i, led; 4023194865Sjfv 4024194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 4025194865Sjfv 4026194865Sjfv /* 4027194865Sjfv * If no link, then turn LED on by setting the invert bit 4028194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 4029194865Sjfv */ 4030194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 4031194865Sjfv for (i = 0; i < 3; i++) { 4032194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4033194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 4034194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 4035194865Sjfv continue; 4036194865Sjfv if (led & E1000_PHY_LED0_IVRT) 4037194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4038194865Sjfv else 4039194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4040194865Sjfv } 4041194865Sjfv } 4042194865Sjfv 4043194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 4044194865Sjfv} 4045194865Sjfv 4046194865Sjfv/** 4047194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 4048194865Sjfv * @hw: pointer to the HW structure 4049194865Sjfv * 4050194865Sjfv * Turn off the LEDs. 4051194865Sjfv **/ 4052194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 4053194865Sjfv{ 4054194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 4055194865Sjfv u32 i, led; 4056194865Sjfv 4057194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 4058194865Sjfv 4059194865Sjfv /* 4060194865Sjfv * If no link, then turn LED off by clearing the invert bit 4061194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 4062194865Sjfv */ 4063194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 4064194865Sjfv for (i = 0; i < 3; i++) { 4065194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4066194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 4067194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 4068194865Sjfv continue; 4069194865Sjfv if (led & E1000_PHY_LED0_IVRT) 4070194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4071194865Sjfv else 4072194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4073194865Sjfv } 4074194865Sjfv } 4075194865Sjfv 4076194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 4077194865Sjfv} 4078194865Sjfv 4079194865Sjfv/** 4080213234Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 4081169589Sjfv * @hw: pointer to the HW structure 4082169240Sjfv * 4083213234Sjfv * Read appropriate register for the config done bit for completion status 4084213234Sjfv * and configure the PHY through s/w for EEPROM-less parts. 4085213234Sjfv * 4086213234Sjfv * NOTE: some silicon which is EEPROM-less will fail trying to read the 4087213234Sjfv * config done bit, so only an error is logged and continues. If we were 4088213234Sjfv * to return with error, EEPROM-less silicon would not be able to be reset 4089213234Sjfv * or change link. 4090169240Sjfv **/ 4091177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 4092169240Sjfv{ 4093173788Sjfv s32 ret_val = E1000_SUCCESS; 4094178523Sjfv u32 bank = 0; 4095213234Sjfv u32 status; 4096173788Sjfv 4097213234Sjfv DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 4098194865Sjfv 4099213234Sjfv e1000_get_cfg_done_generic(hw); 4100213234Sjfv 4101213234Sjfv /* Wait for indication from h/w that it has completed basic config */ 4102213234Sjfv if (hw->mac.type >= e1000_ich10lan) { 4103213234Sjfv e1000_lan_init_done_ich8lan(hw); 4104213234Sjfv } else { 4105213234Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 4106213234Sjfv if (ret_val) { 4107213234Sjfv /* 4108213234Sjfv * When auto config read does not complete, do not 4109213234Sjfv * return with an error. This can happen in situations 4110213234Sjfv * where there is no eeprom and prevents getting link. 4111213234Sjfv */ 4112213234Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 4113213234Sjfv ret_val = E1000_SUCCESS; 4114213234Sjfv } 4115194865Sjfv } 4116194865Sjfv 4117213234Sjfv /* Clear PHY Reset Asserted bit */ 4118213234Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 4119213234Sjfv if (status & E1000_STATUS_PHYRA) 4120213234Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 4121213234Sjfv else 4122213234Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 4123169240Sjfv 4124169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 4125200243Sjfv if (hw->mac.type <= e1000_ich9lan) { 4126178523Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 4127185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 4128178523Sjfv e1000_phy_init_script_igp3(hw); 4129178523Sjfv } 4130178523Sjfv } else { 4131178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 4132185353Sjfv /* Maybe we should do a basic PHY config */ 4133178523Sjfv DEBUGOUT("EEPROM not present\n"); 4134178523Sjfv ret_val = -E1000_ERR_CONFIG; 4135178523Sjfv } 4136169240Sjfv } 4137169240Sjfv 4138173788Sjfv return ret_val; 4139169240Sjfv} 4140169240Sjfv 4141169240Sjfv/** 4142173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 4143173788Sjfv * @hw: pointer to the HW structure 4144173788Sjfv * 4145173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 4146173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 4147173788Sjfv **/ 4148177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 4149173788Sjfv{ 4150173788Sjfv /* If the management interface is not enabled, then power down */ 4151185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 4152185353Sjfv hw->phy.ops.check_reset_block(hw))) 4153173788Sjfv e1000_power_down_phy_copper(hw); 4154173788Sjfv 4155173788Sjfv return; 4156173788Sjfv} 4157173788Sjfv 4158173788Sjfv/** 4159169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 4160169589Sjfv * @hw: pointer to the HW structure 4161169240Sjfv * 4162169240Sjfv * Clears hardware counters specific to the silicon family and calls 4163169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 4164169240Sjfv **/ 4165177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 4166169240Sjfv{ 4167194865Sjfv u16 phy_data; 4168194865Sjfv 4169169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 4170169240Sjfv 4171169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 4172169240Sjfv 4173185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 4174185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 4175185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 4176185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 4177185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 4178185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 4179169240Sjfv 4180185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 4181185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 4182185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 4183169240Sjfv 4184185353Sjfv E1000_READ_REG(hw, E1000_IAC); 4185185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 4186194865Sjfv 4187194865Sjfv /* Clear PHY statistics registers */ 4188194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 4189213234Sjfv (hw->phy.type == e1000_phy_82579) || 4190194865Sjfv (hw->phy.type == e1000_phy_82577)) { 4191194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 4192194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 4193194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 4194194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 4195194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 4196194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 4197194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 4198194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 4199194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 4200194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 4201194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 4202194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 4203194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 4204194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 4205194865Sjfv } 4206169240Sjfv} 4207169240Sjfv 4208