e1000_ich8lan.c revision 200243
1177867Sjfv/****************************************************************************** 2169240Sjfv 3190872Sjfv Copyright (c) 2001-2009, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 200243 2009-12-08 01:07:44Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82562G 10/100 Network Connection 37185353Sjfv * 82562G-2 10/100 Network Connection 38185353Sjfv * 82562GT 10/100 Network Connection 39185353Sjfv * 82562GT-2 10/100 Network Connection 40185353Sjfv * 82562V 10/100 Network Connection 41185353Sjfv * 82562V-2 10/100 Network Connection 42185353Sjfv * 82566DC-2 Gigabit Network Connection 43185353Sjfv * 82566DC Gigabit Network Connection 44185353Sjfv * 82566DM-2 Gigabit Network Connection 45185353Sjfv * 82566DM Gigabit Network Connection 46185353Sjfv * 82566MC Gigabit Network Connection 47185353Sjfv * 82566MM Gigabit Network Connection 48185353Sjfv * 82567LM Gigabit Network Connection 49185353Sjfv * 82567LF Gigabit Network Connection 50185353Sjfv * 82567V Gigabit Network Connection 51185353Sjfv * 82567LM-2 Gigabit Network Connection 52185353Sjfv * 82567LF-2 Gigabit Network Connection 53185353Sjfv * 82567V-2 Gigabit Network Connection 54185353Sjfv * 82567LF-3 Gigabit Network Connection 55185353Sjfv * 82567LM-3 Gigabit Network Connection 56185353Sjfv * 82567LM-4 Gigabit Network Connection 57194865Sjfv * 82577LM Gigabit Network Connection 58194865Sjfv * 82577LC Gigabit Network Connection 59194865Sjfv * 82578DM Gigabit Network Connection 60194865Sjfv * 82578DC Gigabit Network Connection 61169240Sjfv */ 62169240Sjfv 63169589Sjfv#include "e1000_api.h" 64169240Sjfv 65177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 66194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); 67177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 68177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 69177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 71200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 72200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 73177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 74177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 75177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 76200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 77177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 78173788Sjfv bool active); 79177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 80173788Sjfv bool active); 81177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 82173788Sjfv u16 words, u16 *data); 83177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 84173788Sjfv u16 words, u16 *data); 85177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 86177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 87177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 88173788Sjfv u16 *data); 89194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 90177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 91177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 92177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 93177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 94177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 95177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 96173788Sjfv u16 *speed, u16 *duplex); 97177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 98177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 99177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 100200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 101194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 102194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 103194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 104194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 105177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 106177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 107173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 108173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 109173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 110173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 111178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 112185353Sjfv u32 offset, u8 *data); 113173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 114185353Sjfv u8 size, u16 *data); 115177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 116173788Sjfv u32 offset, u16 *data); 117173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 118173788Sjfv u32 offset, u8 byte); 119177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 120173788Sjfv u32 offset, u8 data); 121173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 122173788Sjfv u8 size, u16 data); 123177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 124177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 125200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 126200243Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 127200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 128169240Sjfv 129169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 130169240Sjfv/* Offset 04h HSFSTS */ 131169240Sjfvunion ich8_hws_flash_status { 132169240Sjfv struct ich8_hsfsts { 133169240Sjfv u16 flcdone :1; /* bit 0 Flash Cycle Done */ 134169240Sjfv u16 flcerr :1; /* bit 1 Flash Cycle Error */ 135169240Sjfv u16 dael :1; /* bit 2 Direct Access error Log */ 136169240Sjfv u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 137169240Sjfv u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 138169240Sjfv u16 reserved1 :2; /* bit 13:6 Reserved */ 139169240Sjfv u16 reserved2 :6; /* bit 13:6 Reserved */ 140169240Sjfv u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 141169240Sjfv u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 142169240Sjfv } hsf_status; 143169240Sjfv u16 regval; 144169240Sjfv}; 145169240Sjfv 146169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 147169240Sjfv/* Offset 06h FLCTL */ 148169240Sjfvunion ich8_hws_flash_ctrl { 149169240Sjfv struct ich8_hsflctl { 150169240Sjfv u16 flcgo :1; /* 0 Flash Cycle Go */ 151169240Sjfv u16 flcycle :2; /* 2:1 Flash Cycle */ 152169240Sjfv u16 reserved :5; /* 7:3 Reserved */ 153169240Sjfv u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 154169240Sjfv u16 flockdn :6; /* 15:10 Reserved */ 155169240Sjfv } hsf_ctrl; 156169240Sjfv u16 regval; 157169240Sjfv}; 158169240Sjfv 159169240Sjfv/* ICH Flash Region Access Permissions */ 160169240Sjfvunion ich8_hws_flash_regacc { 161169240Sjfv struct ich8_flracc { 162169240Sjfv u32 grra :8; /* 0:7 GbE region Read Access */ 163169240Sjfv u32 grwa :8; /* 8:15 GbE region Write Access */ 164169240Sjfv u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 165169240Sjfv u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 166169240Sjfv } hsf_flregacc; 167169240Sjfv u16 regval; 168169240Sjfv}; 169169240Sjfv 170169240Sjfv/** 171194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 172194865Sjfv * @hw: pointer to the HW structure 173194865Sjfv * 174194865Sjfv * Initialize family-specific PHY parameters and function pointers. 175194865Sjfv **/ 176194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 177194865Sjfv{ 178194865Sjfv struct e1000_phy_info *phy = &hw->phy; 179194865Sjfv s32 ret_val = E1000_SUCCESS; 180194865Sjfv 181194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 182194865Sjfv 183194865Sjfv phy->addr = 1; 184194865Sjfv phy->reset_delay_us = 100; 185194865Sjfv 186194865Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 187194865Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 188194865Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 189194865Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 190200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 191194865Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 192194865Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 193200243Sjfv phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 194200243Sjfv phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 195194865Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 196200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 197194865Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 198194865Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 199194865Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 200194865Sjfv 201194865Sjfv phy->id = e1000_phy_unknown; 202194865Sjfv e1000_get_phy_id(hw); 203194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 204194865Sjfv 205200243Sjfv switch (phy->type) { 206200243Sjfv case e1000_phy_82577: 207194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 208194865Sjfv phy->ops.force_speed_duplex = 209194865Sjfv e1000_phy_force_speed_duplex_82577; 210200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 211194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 212194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 213200243Sjfv case e1000_phy_82578: 214200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 215200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 216200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 217200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 218200243Sjfv break; 219200243Sjfv default: 220200243Sjfv ret_val = -E1000_ERR_PHY; 221200243Sjfv break; 222194865Sjfv } 223194865Sjfv 224194865Sjfv return ret_val; 225194865Sjfv} 226194865Sjfv 227194865Sjfv/** 228169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 229169589Sjfv * @hw: pointer to the HW structure 230169240Sjfv * 231169240Sjfv * Initialize family-specific PHY parameters and function pointers. 232169240Sjfv **/ 233177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 234169240Sjfv{ 235169240Sjfv struct e1000_phy_info *phy = &hw->phy; 236169240Sjfv s32 ret_val = E1000_SUCCESS; 237169589Sjfv u16 i = 0; 238169240Sjfv 239169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 240169240Sjfv 241177867Sjfv phy->addr = 1; 242177867Sjfv phy->reset_delay_us = 100; 243169240Sjfv 244177867Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 245177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 246177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 247177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 248177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 249177867Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 250177867Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 251177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 252177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 253177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 254177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 255177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 256169240Sjfv 257176667Sjfv /* 258176667Sjfv * We may need to do this twice - once for IGP and if that fails, 259176667Sjfv * we'll set BM func pointers and try again 260176667Sjfv */ 261176667Sjfv ret_val = e1000_determine_phy_address(hw); 262176667Sjfv if (ret_val) { 263177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 264177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 265176667Sjfv ret_val = e1000_determine_phy_address(hw); 266176667Sjfv if (ret_val) { 267190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 268176667Sjfv goto out; 269176667Sjfv } 270176667Sjfv } 271169240Sjfv 272169589Sjfv phy->id = 0; 273169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 274169589Sjfv (i++ < 100)) { 275169589Sjfv msec_delay(1); 276169589Sjfv ret_val = e1000_get_phy_id(hw); 277169589Sjfv if (ret_val) 278169589Sjfv goto out; 279169589Sjfv } 280169589Sjfv 281169240Sjfv /* Verify phy id */ 282169240Sjfv switch (phy->id) { 283169240Sjfv case IGP03E1000_E_PHY_ID: 284169240Sjfv phy->type = e1000_phy_igp_3; 285169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 286200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 287200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 288200243Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 289200243Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 290200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 291169240Sjfv break; 292169240Sjfv case IFE_E_PHY_ID: 293169240Sjfv case IFE_PLUS_E_PHY_ID: 294169240Sjfv case IFE_C_E_PHY_ID: 295169240Sjfv phy->type = e1000_phy_ife; 296169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 297200243Sjfv phy->ops.get_info = e1000_get_phy_info_ife; 298200243Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 299200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 300169240Sjfv break; 301176667Sjfv case BME1000_E_PHY_ID: 302176667Sjfv phy->type = e1000_phy_bm; 303176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 304177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 305177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 306177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 307200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 308200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 309200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 310176667Sjfv break; 311169240Sjfv default: 312169240Sjfv ret_val = -E1000_ERR_PHY; 313169240Sjfv goto out; 314169240Sjfv } 315169240Sjfv 316169240Sjfvout: 317169240Sjfv return ret_val; 318169240Sjfv} 319169240Sjfv 320169240Sjfv/** 321169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 322169589Sjfv * @hw: pointer to the HW structure 323169240Sjfv * 324169240Sjfv * Initialize family-specific NVM parameters and function 325169240Sjfv * pointers. 326169240Sjfv **/ 327177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 328169240Sjfv{ 329169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 330185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 331169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 332173788Sjfv s32 ret_val = E1000_SUCCESS; 333169240Sjfv u16 i; 334169240Sjfv 335169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 336169240Sjfv 337173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 338169240Sjfv if (!hw->flash_address) { 339169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 340169240Sjfv ret_val = -E1000_ERR_CONFIG; 341169240Sjfv goto out; 342169240Sjfv } 343169240Sjfv 344185353Sjfv nvm->type = e1000_nvm_flash_sw; 345169240Sjfv 346169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 347169240Sjfv 348173788Sjfv /* 349173788Sjfv * sector_X_addr is a "sector"-aligned address (4096 bytes) 350169240Sjfv * Add 1 to sector_end_addr since this sector is included in 351173788Sjfv * the overall size. 352173788Sjfv */ 353169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 354169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 355169240Sjfv 356169240Sjfv /* flash_base_addr is byte-aligned */ 357185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 358169240Sjfv 359173788Sjfv /* 360173788Sjfv * find total size of the NVM, then cut in half since the total 361173788Sjfv * size represents two separate NVM banks. 362173788Sjfv */ 363185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 364169240Sjfv << FLASH_SECTOR_ADDR_SHIFT; 365185353Sjfv nvm->flash_bank_size /= 2; 366169240Sjfv /* Adjust to word count */ 367185353Sjfv nvm->flash_bank_size /= sizeof(u16); 368169240Sjfv 369185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 370169240Sjfv 371169240Sjfv /* Clear shadow ram */ 372169240Sjfv for (i = 0; i < nvm->word_size; i++) { 373169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 374169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 375169240Sjfv } 376169240Sjfv 377200243Sjfv E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 378200243Sjfv E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 379200243Sjfv 380169240Sjfv /* Function Pointers */ 381200243Sjfv nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 382200243Sjfv nvm->ops.release = e1000_release_nvm_ich8lan; 383177867Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 384177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 385177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 386177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 387177867Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 388169240Sjfv 389169240Sjfvout: 390169240Sjfv return ret_val; 391169240Sjfv} 392169240Sjfv 393169240Sjfv/** 394169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 395169589Sjfv * @hw: pointer to the HW structure 396169240Sjfv * 397169240Sjfv * Initialize family-specific MAC parameters and function 398169240Sjfv * pointers. 399169240Sjfv **/ 400177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 401169240Sjfv{ 402169240Sjfv struct e1000_mac_info *mac = &hw->mac; 403190872Sjfv u16 pci_cfg; 404169240Sjfv 405169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 406169240Sjfv 407169240Sjfv /* Set media type function pointer */ 408173788Sjfv hw->phy.media_type = e1000_media_type_copper; 409169240Sjfv 410169240Sjfv /* Set mta register count */ 411169240Sjfv mac->mta_reg_count = 32; 412169240Sjfv /* Set rar entry count */ 413169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 414169240Sjfv if (mac->type == e1000_ich8lan) 415169240Sjfv mac->rar_entry_count--; 416169240Sjfv /* Set if part includes ASF firmware */ 417169240Sjfv mac->asf_firmware_present = TRUE; 418169240Sjfv /* Set if manageability features are enabled. */ 419169240Sjfv mac->arc_subsystem_valid = TRUE; 420200243Sjfv /* Adaptive IFS supported */ 421200243Sjfv mac->adaptive_ifs = TRUE; 422169240Sjfv 423169240Sjfv /* Function pointers */ 424169240Sjfv 425169240Sjfv /* bus type/speed/width */ 426177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 427185353Sjfv /* function id */ 428185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 429169240Sjfv /* reset */ 430177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 431169240Sjfv /* hw initialization */ 432177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 433169240Sjfv /* link setup */ 434177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 435169240Sjfv /* physical interface setup */ 436177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 437169240Sjfv /* check for link */ 438200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 439169240Sjfv /* check management mode */ 440177867Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 441169240Sjfv /* link info */ 442177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 443169240Sjfv /* multicast address update */ 444177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 445169240Sjfv /* setting MTA */ 446177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 447169240Sjfv /* clear hardware counters */ 448177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 449169240Sjfv 450190872Sjfv /* LED operations */ 451190872Sjfv switch (mac->type) { 452190872Sjfv case e1000_ich8lan: 453190872Sjfv case e1000_ich9lan: 454190872Sjfv case e1000_ich10lan: 455190872Sjfv /* ID LED init */ 456190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 457190872Sjfv /* blink LED */ 458190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 459190872Sjfv /* setup LED */ 460190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 461190872Sjfv /* cleanup LED */ 462190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 463190872Sjfv /* turn on/off LED */ 464190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 465190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 466190872Sjfv break; 467194865Sjfv case e1000_pchlan: 468194865Sjfv /* save PCH revision_id */ 469194865Sjfv e1000_read_pci_cfg(hw, 0x2, &pci_cfg); 470194865Sjfv hw->revision_id = (u8)(pci_cfg &= 0x000F); 471194865Sjfv /* ID LED init */ 472194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 473194865Sjfv /* setup LED */ 474194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 475194865Sjfv /* cleanup LED */ 476194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 477194865Sjfv /* turn on/off LED */ 478194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 479194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 480194865Sjfv break; 481190872Sjfv default: 482190872Sjfv break; 483190872Sjfv } 484190872Sjfv 485169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 486169240Sjfv if (mac->type == e1000_ich8lan) 487169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 488169240Sjfv 489185353Sjfv return E1000_SUCCESS; 490169240Sjfv} 491169240Sjfv 492169240Sjfv/** 493200243Sjfv * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 494200243Sjfv * @hw: pointer to the HW structure 495200243Sjfv * 496200243Sjfv * Checks to see of the link status of the hardware has changed. If a 497200243Sjfv * change in link status has been detected, then we read the PHY registers 498200243Sjfv * to get the current speed/duplex if link exists. 499200243Sjfv **/ 500200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 501200243Sjfv{ 502200243Sjfv struct e1000_mac_info *mac = &hw->mac; 503200243Sjfv s32 ret_val; 504200243Sjfv bool link; 505200243Sjfv 506200243Sjfv DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 507200243Sjfv 508200243Sjfv /* 509200243Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 510200243Sjfv * has completed and/or if our link status has changed. The 511200243Sjfv * get_link_status flag is set upon receiving a Link Status 512200243Sjfv * Change or Rx Sequence Error interrupt. 513200243Sjfv */ 514200243Sjfv if (!mac->get_link_status) { 515200243Sjfv ret_val = E1000_SUCCESS; 516200243Sjfv goto out; 517200243Sjfv } 518200243Sjfv 519200243Sjfv /* 520200243Sjfv * First we want to see if the MII Status Register reports 521200243Sjfv * link. If so, then we want to get the current speed/duplex 522200243Sjfv * of the PHY. 523200243Sjfv */ 524200243Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 525200243Sjfv if (ret_val) 526200243Sjfv goto out; 527200243Sjfv 528200243Sjfv if (hw->mac.type == e1000_pchlan) { 529200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, link); 530200243Sjfv if (ret_val) 531200243Sjfv goto out; 532200243Sjfv } 533200243Sjfv 534200243Sjfv if (!link) 535200243Sjfv goto out; /* No link detected */ 536200243Sjfv 537200243Sjfv mac->get_link_status = FALSE; 538200243Sjfv 539200243Sjfv if (hw->phy.type == e1000_phy_82578) { 540200243Sjfv ret_val = e1000_link_stall_workaround_hv(hw); 541200243Sjfv if (ret_val) 542200243Sjfv goto out; 543200243Sjfv } 544200243Sjfv 545200243Sjfv /* 546200243Sjfv * Check if there was DownShift, must be checked 547200243Sjfv * immediately after link-up 548200243Sjfv */ 549200243Sjfv e1000_check_downshift_generic(hw); 550200243Sjfv 551200243Sjfv /* 552200243Sjfv * If we are forcing speed/duplex, then we simply return since 553200243Sjfv * we have already determined whether we have link or not. 554200243Sjfv */ 555200243Sjfv if (!mac->autoneg) { 556200243Sjfv ret_val = -E1000_ERR_CONFIG; 557200243Sjfv goto out; 558200243Sjfv } 559200243Sjfv 560200243Sjfv /* 561200243Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 562200243Sjfv * of MAC speed/duplex configuration. So we only need to 563200243Sjfv * configure Collision Distance in the MAC. 564200243Sjfv */ 565200243Sjfv e1000_config_collision_dist_generic(hw); 566200243Sjfv 567200243Sjfv /* 568200243Sjfv * Configure Flow Control now that Auto-Neg has completed. 569200243Sjfv * First, we need to restore the desired flow control 570200243Sjfv * settings because we may have had to re-autoneg with a 571200243Sjfv * different link partner. 572200243Sjfv */ 573200243Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 574200243Sjfv if (ret_val) 575200243Sjfv DEBUGOUT("Error configuring flow control\n"); 576200243Sjfv 577200243Sjfvout: 578200243Sjfv return ret_val; 579200243Sjfv} 580200243Sjfv 581200243Sjfv/** 582169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 583169589Sjfv * @hw: pointer to the HW structure 584169240Sjfv * 585169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 586169240Sjfv **/ 587173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 588169240Sjfv{ 589169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 590169240Sjfv 591177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 592177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 593194865Sjfv switch (hw->mac.type) { 594194865Sjfv case e1000_ich8lan: 595194865Sjfv case e1000_ich9lan: 596194865Sjfv case e1000_ich10lan: 597194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 598194865Sjfv break; 599194865Sjfv case e1000_pchlan: 600194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 601194865Sjfv break; 602194865Sjfv default: 603194865Sjfv break; 604194865Sjfv } 605169240Sjfv} 606169240Sjfv 607169240Sjfv/** 608200243Sjfv * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 609200243Sjfv * @hw: pointer to the HW structure 610200243Sjfv * 611200243Sjfv * Acquires the mutex for performing NVM operations. 612200243Sjfv **/ 613200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 614200243Sjfv{ 615200243Sjfv DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 616200243Sjfv 617200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 618200243Sjfv 619200243Sjfv return E1000_SUCCESS; 620200243Sjfv} 621200243Sjfv 622200243Sjfv/** 623200243Sjfv * e1000_release_nvm_ich8lan - Release NVM mutex 624200243Sjfv * @hw: pointer to the HW structure 625200243Sjfv * 626200243Sjfv * Releases the mutex used while performing NVM operations. 627200243Sjfv **/ 628200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 629200243Sjfv{ 630200243Sjfv DEBUGFUNC("e1000_release_nvm_ich8lan"); 631200243Sjfv 632200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 633200243Sjfv 634200243Sjfv return; 635200243Sjfv} 636200243Sjfv 637200243Sjfv/** 638169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 639169589Sjfv * @hw: pointer to the HW structure 640169240Sjfv * 641200243Sjfv * Acquires the software control flag for performing PHY and select 642200243Sjfv * MAC CSR accesses. 643169240Sjfv **/ 644177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 645169240Sjfv{ 646169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 647169240Sjfv s32 ret_val = E1000_SUCCESS; 648169240Sjfv 649169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 650169240Sjfv 651200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 652200243Sjfv 653169240Sjfv while (timeout) { 654169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 655200243Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 656200243Sjfv break; 657169240Sjfv 658200243Sjfv msec_delay_irq(1); 659200243Sjfv timeout--; 660200243Sjfv } 661194865Sjfv 662200243Sjfv if (!timeout) { 663200243Sjfv DEBUGOUT("SW/FW/HW has locked the resource for too long.\n"); 664200243Sjfv ret_val = -E1000_ERR_CONFIG; 665200243Sjfv goto out; 666200243Sjfv } 667200243Sjfv 668200243Sjfv timeout = SW_FLAG_TIMEOUT; 669200243Sjfv 670200243Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 671200243Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 672200243Sjfv 673200243Sjfv while (timeout) { 674200243Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 675200243Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 676200243Sjfv break; 677200243Sjfv 678169240Sjfv msec_delay_irq(1); 679169240Sjfv timeout--; 680169240Sjfv } 681169240Sjfv 682169240Sjfv if (!timeout) { 683200243Sjfv DEBUGOUT("Failed to acquire the semaphore.\n"); 684173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 685173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 686169240Sjfv ret_val = -E1000_ERR_CONFIG; 687169240Sjfv goto out; 688169240Sjfv } 689169240Sjfv 690169240Sjfvout: 691200243Sjfv if (ret_val) 692200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 693200243Sjfv 694169240Sjfv return ret_val; 695169240Sjfv} 696169240Sjfv 697169240Sjfv/** 698169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 699169589Sjfv * @hw: pointer to the HW structure 700169240Sjfv * 701200243Sjfv * Releases the software control flag for performing PHY and select 702200243Sjfv * MAC CSR accesses. 703169240Sjfv **/ 704177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 705169240Sjfv{ 706169240Sjfv u32 extcnf_ctrl; 707169240Sjfv 708169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 709169240Sjfv 710169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 711169240Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 712169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 713169240Sjfv 714200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 715200243Sjfv 716169240Sjfv return; 717169240Sjfv} 718169240Sjfv 719169240Sjfv/** 720169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 721169589Sjfv * @hw: pointer to the HW structure 722169240Sjfv * 723169240Sjfv * This checks if the adapter has manageability enabled. 724169240Sjfv * This is a function pointer entry point only called by read/write 725169240Sjfv * routines for the PHY and NVM parts. 726169240Sjfv **/ 727177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 728169240Sjfv{ 729169240Sjfv u32 fwsm; 730169240Sjfv 731169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 732169240Sjfv 733169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 734169240Sjfv 735185353Sjfv return (fwsm & E1000_FWSM_MODE_MASK) == 736185353Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 737169240Sjfv} 738169240Sjfv 739169240Sjfv/** 740169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 741169589Sjfv * @hw: pointer to the HW structure 742169240Sjfv * 743169240Sjfv * Checks if firmware is blocking the reset of the PHY. 744169240Sjfv * This is a function pointer entry point only called by 745169240Sjfv * reset routines. 746169240Sjfv **/ 747177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 748169240Sjfv{ 749169240Sjfv u32 fwsm; 750169240Sjfv 751169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 752169240Sjfv 753169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 754169240Sjfv 755169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 756169240Sjfv : E1000_BLK_PHY_RESET; 757169240Sjfv} 758169240Sjfv 759169240Sjfv/** 760200243Sjfv * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 761200243Sjfv * @hw: pointer to the HW structure 762200243Sjfv * 763200243Sjfv * SW should configure the LCD from the NVM extended configuration region 764200243Sjfv * as a workaround for certain parts. 765200243Sjfv **/ 766200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 767200243Sjfv{ 768200243Sjfv struct e1000_phy_info *phy = &hw->phy; 769200243Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 770200243Sjfv s32 ret_val; 771200243Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 772200243Sjfv 773200243Sjfv ret_val = hw->phy.ops.acquire(hw); 774200243Sjfv if (ret_val) 775200243Sjfv return ret_val; 776200243Sjfv 777200243Sjfv /* 778200243Sjfv * Initialize the PHY from the NVM on ICH platforms. This 779200243Sjfv * is needed due to an issue where the NVM configuration is 780200243Sjfv * not properly autoloaded after power transitions. 781200243Sjfv * Therefore, after each PHY reset, we will load the 782200243Sjfv * configuration data out of the NVM manually. 783200243Sjfv */ 784200243Sjfv if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) || 785200243Sjfv (hw->mac.type == e1000_pchlan)) { 786200243Sjfv /* Check if SW needs to configure the PHY */ 787200243Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 788200243Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) || 789200243Sjfv (hw->mac.type == e1000_pchlan)) 790200243Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 791200243Sjfv else 792200243Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 793200243Sjfv 794200243Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 795200243Sjfv if (!(data & sw_cfg_mask)) 796200243Sjfv goto out; 797200243Sjfv 798200243Sjfv /* Wait for basic configuration completes before proceeding */ 799200243Sjfv e1000_lan_init_done_ich8lan(hw); 800200243Sjfv 801200243Sjfv /* 802200243Sjfv * Make sure HW does not configure LCD from PHY 803200243Sjfv * extended configuration before SW configuration 804200243Sjfv */ 805200243Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 806200243Sjfv if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 807200243Sjfv goto out; 808200243Sjfv 809200243Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 810200243Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 811200243Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 812200243Sjfv if (!cnf_size) 813200243Sjfv goto out; 814200243Sjfv 815200243Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 816200243Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 817200243Sjfv 818200243Sjfv if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && 819200243Sjfv (hw->mac.type == e1000_pchlan)) { 820200243Sjfv /* 821200243Sjfv * HW configures the SMBus address and LEDs when the 822200243Sjfv * OEM and LCD Write Enable bits are set in the NVM. 823200243Sjfv * When both NVM bits are cleared, SW will configure 824200243Sjfv * them instead. 825200243Sjfv */ 826200243Sjfv data = E1000_READ_REG(hw, E1000_STRAP); 827200243Sjfv data &= E1000_STRAP_SMBUS_ADDRESS_MASK; 828200243Sjfv reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT; 829200243Sjfv reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 830200243Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, 831200243Sjfv reg_data); 832200243Sjfv if (ret_val) 833200243Sjfv goto out; 834200243Sjfv 835200243Sjfv data = E1000_READ_REG(hw, E1000_LEDCTL); 836200243Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, 837200243Sjfv HV_LED_CONFIG, 838200243Sjfv (u16)data); 839200243Sjfv if (ret_val) 840200243Sjfv goto out; 841200243Sjfv } 842200243Sjfv 843200243Sjfv /* Configure LCD from extended configuration region. */ 844200243Sjfv 845200243Sjfv /* cnf_base_addr is in DWORD */ 846200243Sjfv word_addr = (u16)(cnf_base_addr << 1); 847200243Sjfv 848200243Sjfv for (i = 0; i < cnf_size; i++) { 849200243Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 850200243Sjfv ®_data); 851200243Sjfv if (ret_val) 852200243Sjfv goto out; 853200243Sjfv 854200243Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 855200243Sjfv 1, ®_addr); 856200243Sjfv if (ret_val) 857200243Sjfv goto out; 858200243Sjfv 859200243Sjfv /* Save off the PHY page for future writes. */ 860200243Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 861200243Sjfv phy_page = reg_data; 862200243Sjfv continue; 863200243Sjfv } 864200243Sjfv 865200243Sjfv reg_addr &= PHY_REG_MASK; 866200243Sjfv reg_addr |= phy_page; 867200243Sjfv 868200243Sjfv ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 869200243Sjfv reg_data); 870200243Sjfv if (ret_val) 871200243Sjfv goto out; 872200243Sjfv } 873200243Sjfv } 874200243Sjfv 875200243Sjfvout: 876200243Sjfv hw->phy.ops.release(hw); 877200243Sjfv return ret_val; 878200243Sjfv} 879200243Sjfv 880200243Sjfv/** 881200243Sjfv * e1000_k1_gig_workaround_hv - K1 Si workaround 882200243Sjfv * @hw: pointer to the HW structure 883200243Sjfv * @link: link up bool flag 884200243Sjfv * 885200243Sjfv * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 886200243Sjfv * from a lower speed. This workaround disables K1 whenever link is at 1Gig 887200243Sjfv * If link is down, the function will restore the default K1 setting located 888200243Sjfv * in the NVM. 889200243Sjfv **/ 890200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 891200243Sjfv{ 892200243Sjfv s32 ret_val = E1000_SUCCESS; 893200243Sjfv u16 status_reg = 0; 894200243Sjfv bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 895200243Sjfv 896200243Sjfv DEBUGFUNC("e1000_k1_gig_workaround_hv"); 897200243Sjfv 898200243Sjfv if (hw->mac.type != e1000_pchlan) 899200243Sjfv goto out; 900200243Sjfv 901200243Sjfv /* Wrap the whole flow with the sw flag */ 902200243Sjfv ret_val = hw->phy.ops.acquire(hw); 903200243Sjfv if (ret_val) 904200243Sjfv goto out; 905200243Sjfv 906200243Sjfv /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 907200243Sjfv if (link) { 908200243Sjfv if (hw->phy.type == e1000_phy_82578) { 909200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 910200243Sjfv &status_reg); 911200243Sjfv if (ret_val) 912200243Sjfv goto release; 913200243Sjfv 914200243Sjfv status_reg &= BM_CS_STATUS_LINK_UP | 915200243Sjfv BM_CS_STATUS_RESOLVED | 916200243Sjfv BM_CS_STATUS_SPEED_MASK; 917200243Sjfv 918200243Sjfv if (status_reg == (BM_CS_STATUS_LINK_UP | 919200243Sjfv BM_CS_STATUS_RESOLVED | 920200243Sjfv BM_CS_STATUS_SPEED_1000)) 921200243Sjfv k1_enable = FALSE; 922200243Sjfv } 923200243Sjfv 924200243Sjfv if (hw->phy.type == e1000_phy_82577) { 925200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 926200243Sjfv &status_reg); 927200243Sjfv if (ret_val) 928200243Sjfv goto release; 929200243Sjfv 930200243Sjfv status_reg &= HV_M_STATUS_LINK_UP | 931200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 932200243Sjfv HV_M_STATUS_SPEED_MASK; 933200243Sjfv 934200243Sjfv if (status_reg == (HV_M_STATUS_LINK_UP | 935200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 936200243Sjfv HV_M_STATUS_SPEED_1000)) 937200243Sjfv k1_enable = FALSE; 938200243Sjfv } 939200243Sjfv 940200243Sjfv /* Link stall fix for link up */ 941200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 942200243Sjfv 0x0100); 943200243Sjfv if (ret_val) 944200243Sjfv goto release; 945200243Sjfv 946200243Sjfv } else { 947200243Sjfv /* Link stall fix for link down */ 948200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 949200243Sjfv 0x4100); 950200243Sjfv if (ret_val) 951200243Sjfv goto release; 952200243Sjfv } 953200243Sjfv 954200243Sjfv ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 955200243Sjfv 956200243Sjfvrelease: 957200243Sjfv hw->phy.ops.release(hw); 958200243Sjfvout: 959200243Sjfv return ret_val; 960200243Sjfv} 961200243Sjfv 962200243Sjfv/** 963200243Sjfv * e1000_configure_k1_ich8lan - Configure K1 power state 964200243Sjfv * @hw: pointer to the HW structure 965200243Sjfv * @enable: K1 state to configure 966200243Sjfv * 967200243Sjfv * Configure the K1 power state based on the provided parameter. 968200243Sjfv * Assumes semaphore already acquired. 969200243Sjfv * 970200243Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 971200243Sjfv **/ 972200243Sjfvs32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 973200243Sjfv{ 974200243Sjfv s32 ret_val = E1000_SUCCESS; 975200243Sjfv u32 ctrl_reg = 0; 976200243Sjfv u32 ctrl_ext = 0; 977200243Sjfv u32 reg = 0; 978200243Sjfv u16 kmrn_reg = 0; 979200243Sjfv 980200243Sjfv ret_val = e1000_read_kmrn_reg_locked(hw, 981200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 982200243Sjfv &kmrn_reg); 983200243Sjfv if (ret_val) 984200243Sjfv goto out; 985200243Sjfv 986200243Sjfv if (k1_enable) 987200243Sjfv kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 988200243Sjfv else 989200243Sjfv kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 990200243Sjfv 991200243Sjfv ret_val = e1000_write_kmrn_reg_locked(hw, 992200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 993200243Sjfv kmrn_reg); 994200243Sjfv if (ret_val) 995200243Sjfv goto out; 996200243Sjfv 997200243Sjfv usec_delay(20); 998200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 999200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1000200243Sjfv 1001200243Sjfv reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1002200243Sjfv reg |= E1000_CTRL_FRCSPD; 1003200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1004200243Sjfv 1005200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1006200243Sjfv usec_delay(20); 1007200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1008200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1009200243Sjfv usec_delay(20); 1010200243Sjfv 1011200243Sjfvout: 1012200243Sjfv return ret_val; 1013200243Sjfv} 1014200243Sjfv 1015200243Sjfv/** 1016200243Sjfv * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1017200243Sjfv * @hw: pointer to the HW structure 1018200243Sjfv * @d0_state: boolean if entering d0 or d3 device state 1019200243Sjfv * 1020200243Sjfv * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1021200243Sjfv * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1022200243Sjfv * in NVM determines whether HW should configure LPLU and Gbe Disable. 1023200243Sjfv **/ 1024200243Sjfvs32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1025200243Sjfv{ 1026200243Sjfv s32 ret_val = 0; 1027200243Sjfv u32 mac_reg; 1028200243Sjfv u16 oem_reg; 1029200243Sjfv 1030200243Sjfv if (hw->mac.type != e1000_pchlan) 1031200243Sjfv return ret_val; 1032200243Sjfv 1033200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1034200243Sjfv if (ret_val) 1035200243Sjfv return ret_val; 1036200243Sjfv 1037200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1038200243Sjfv if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1039200243Sjfv goto out; 1040200243Sjfv 1041200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 1042200243Sjfv if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1043200243Sjfv goto out; 1044200243Sjfv 1045200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 1046200243Sjfv 1047200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1048200243Sjfv if (ret_val) 1049200243Sjfv goto out; 1050200243Sjfv 1051200243Sjfv oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1052200243Sjfv 1053200243Sjfv if (d0_state) { 1054200243Sjfv if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1055200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1056200243Sjfv 1057200243Sjfv if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1058200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1059200243Sjfv } else { 1060200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 1061200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1062200243Sjfv 1063200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 1064200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1065200243Sjfv } 1066200243Sjfv /* Restart auto-neg to activate the bits */ 1067200243Sjfv if (!hw->phy.ops.check_reset_block(hw)) 1068200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1069200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 1070200243Sjfv 1071200243Sjfvout: 1072200243Sjfv hw->phy.ops.release(hw); 1073200243Sjfv 1074200243Sjfv return ret_val; 1075200243Sjfv} 1076200243Sjfv 1077200243Sjfv 1078200243Sjfv/** 1079194865Sjfv * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx 1080169589Sjfv * @hw: pointer to the HW structure 1081169240Sjfv **/ 1082194865Sjfvs32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 1083169240Sjfv{ 1084194865Sjfv if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2)) 1085194865Sjfv return E1000_SUCCESS; 1086169240Sjfv 1087194865Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444); 1088194865Sjfv} 1089169240Sjfv 1090194865Sjfv/** 1091194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1092194865Sjfv * done after every PHY reset. 1093194865Sjfv **/ 1094194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1095194865Sjfv{ 1096194865Sjfv s32 ret_val = E1000_SUCCESS; 1097194865Sjfv 1098194865Sjfv if (hw->mac.type != e1000_pchlan) 1099200243Sjfv goto out; 1100194865Sjfv 1101194865Sjfv /* Hanksville M Phy init for IEEE. */ 1102194865Sjfv if ((hw->revision_id == 2) && 1103194865Sjfv (hw->phy.type == e1000_phy_82577) && 1104194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1105194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8823); 1106194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0018); 1107194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8824); 1108194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0016); 1109194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8825); 1110194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x001A); 1111194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888C); 1112194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1113194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888D); 1114194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1115194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888E); 1116194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1117194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8827); 1118194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1119194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8835); 1120194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1121194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8834); 1122194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1123194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8833); 1124194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0002); 1125169240Sjfv } 1126169240Sjfv 1127194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 1128194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1129194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1130194865Sjfv /* Disable generation of early preamble */ 1131194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1132194865Sjfv if (ret_val) 1133200243Sjfv goto out; 1134169240Sjfv 1135194865Sjfv /* Preamble tuning for SSC */ 1136194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1137194865Sjfv if (ret_val) 1138200243Sjfv goto out; 1139194865Sjfv } 1140169240Sjfv 1141194865Sjfv if (hw->phy.type == e1000_phy_82578) { 1142194865Sjfv if (hw->revision_id < 3) { 1143194865Sjfv /* PHY config */ 1144194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 1145194865Sjfv 0x66C0); 1146194865Sjfv if (ret_val) 1147200243Sjfv goto out; 1148169240Sjfv 1149194865Sjfv /* PHY config */ 1150194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 1151194865Sjfv 0xFFFF); 1152194865Sjfv if (ret_val) 1153200243Sjfv goto out; 1154194865Sjfv } 1155169240Sjfv 1156194865Sjfv /* 1157194865Sjfv * Return registers to default by doing a soft reset then 1158194865Sjfv * writing 0x3140 to the control register. 1159194865Sjfv */ 1160194865Sjfv if (hw->phy.revision < 2) { 1161194865Sjfv e1000_phy_sw_reset_generic(hw); 1162194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 1163194865Sjfv 0x3140); 1164194865Sjfv } 1165194865Sjfv } 1166169240Sjfv 1167194865Sjfv if ((hw->revision_id == 2) && 1168194865Sjfv (hw->phy.type == e1000_phy_82577) && 1169194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1170194865Sjfv /* 1171194865Sjfv * Workaround for OEM (GbE) not operating after reset - 1172194865Sjfv * restart AN (twice) 1173194865Sjfv */ 1174194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1175194865Sjfv if (ret_val) 1176200243Sjfv goto out; 1177194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1178194865Sjfv if (ret_val) 1179200243Sjfv goto out; 1180194865Sjfv } 1181194865Sjfv 1182194865Sjfv /* Select page 0 */ 1183194865Sjfv ret_val = hw->phy.ops.acquire(hw); 1184169240Sjfv if (ret_val) 1185200243Sjfv goto out; 1186200243Sjfv 1187194865Sjfv hw->phy.addr = 1; 1188200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1189200243Sjfv if (ret_val) 1190200243Sjfv goto out; 1191194865Sjfv hw->phy.ops.release(hw); 1192169240Sjfv 1193200243Sjfv /* 1194200243Sjfv * Configure the K1 Si workaround during phy reset assuming there is 1195200243Sjfv * link so that it disables K1 if link is in 1Gbps. 1196200243Sjfv */ 1197200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 1198200243Sjfv 1199200243Sjfvout: 1200194865Sjfv return ret_val; 1201194865Sjfv} 1202169240Sjfv 1203194865Sjfv/** 1204194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 1205194865Sjfv * @hw: pointer to the HW structure 1206194865Sjfv * 1207194865Sjfv * Check the appropriate indication the MAC has finished configuring the 1208194865Sjfv * PHY after a software reset. 1209194865Sjfv **/ 1210194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 1211194865Sjfv{ 1212194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 1213169240Sjfv 1214194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 1215169240Sjfv 1216194865Sjfv /* Wait for basic configuration completes before proceeding */ 1217194865Sjfv do { 1218194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1219194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 1220194865Sjfv usec_delay(100); 1221194865Sjfv } while ((!data) && --loop); 1222169240Sjfv 1223194865Sjfv /* 1224194865Sjfv * If basic configuration is incomplete before the above loop 1225194865Sjfv * count reaches 0, loading the configuration from NVM will 1226194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 1227194865Sjfv */ 1228194865Sjfv if (loop == 0) 1229194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 1230169240Sjfv 1231194865Sjfv /* Clear the Init Done bit for the next init event */ 1232194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1233194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 1234194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 1235169240Sjfv} 1236169240Sjfv 1237169240Sjfv/** 1238169240Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 1239169589Sjfv * @hw: pointer to the HW structure 1240169240Sjfv * 1241169240Sjfv * Resets the PHY 1242169240Sjfv * This is a function pointer entry point called by drivers 1243169240Sjfv * or other shared routines. 1244169240Sjfv **/ 1245177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 1246169240Sjfv{ 1247200243Sjfv s32 ret_val = E1000_SUCCESS; 1248200243Sjfv u16 reg; 1249169240Sjfv 1250169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 1251169240Sjfv 1252169240Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 1253169240Sjfv if (ret_val) 1254169240Sjfv goto out; 1255169240Sjfv 1256194865Sjfv /* Allow time for h/w to get to a quiescent state after reset */ 1257194865Sjfv msec_delay(10); 1258194865Sjfv 1259194865Sjfv if (hw->mac.type == e1000_pchlan) { 1260194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 1261194865Sjfv if (ret_val) 1262194865Sjfv goto out; 1263194865Sjfv } 1264194865Sjfv 1265200243Sjfv /* Dummy read to clear the phy wakeup bit after lcd reset */ 1266200243Sjfv if (hw->mac.type == e1000_pchlan) 1267200243Sjfv hw->phy.ops.read_reg(hw, BM_WUC, ®); 1268169240Sjfv 1269200243Sjfv /* Configure the LCD with the extended configuration region in NVM */ 1270200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 1271200243Sjfv if (ret_val) 1272200243Sjfv goto out; 1273169240Sjfv 1274200243Sjfv /* Configure the LCD with the OEM bits in NVM */ 1275200243Sjfv if (hw->mac.type == e1000_pchlan) 1276200243Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 1277169240Sjfv 1278169240Sjfvout: 1279169240Sjfv return ret_val; 1280169240Sjfv} 1281169240Sjfv 1282169240Sjfv/** 1283200243Sjfv * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 1284169589Sjfv * @hw: pointer to the HW structure 1285200243Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1286169240Sjfv * 1287200243Sjfv * Sets the LPLU state according to the active flag. For PCH, if OEM write 1288200243Sjfv * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 1289200243Sjfv * the phy speed. This function will manually set the LPLU bit and restart 1290200243Sjfv * auto-neg as hw would do. D3 and D0 LPLU will call the same function 1291200243Sjfv * since it configures the same bit. 1292169240Sjfv **/ 1293200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 1294169240Sjfv{ 1295200243Sjfv s32 ret_val = E1000_SUCCESS; 1296200243Sjfv u16 oem_reg; 1297169240Sjfv 1298200243Sjfv DEBUGFUNC("e1000_set_lplu_state_pchlan"); 1299169240Sjfv 1300200243Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 1301169240Sjfv if (ret_val) 1302169240Sjfv goto out; 1303169240Sjfv 1304200243Sjfv if (active) 1305200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1306200243Sjfv else 1307200243Sjfv oem_reg &= ~HV_OEM_BITS_LPLU; 1308169240Sjfv 1309200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1310200243Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 1311169240Sjfv 1312169240Sjfvout: 1313169240Sjfv return ret_val; 1314169240Sjfv} 1315169240Sjfv 1316169240Sjfv/** 1317169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 1318169589Sjfv * @hw: pointer to the HW structure 1319169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1320169240Sjfv * 1321169240Sjfv * Sets the LPLU D0 state according to the active flag. When 1322169240Sjfv * activating LPLU this function also disables smart speed 1323169240Sjfv * and vice versa. LPLU will not be activated unless the 1324169240Sjfv * device autonegotiation advertisement meets standards of 1325169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 1326169240Sjfv * This is a function pointer entry point only called by 1327169240Sjfv * PHY setup routines. 1328169240Sjfv **/ 1329185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1330169240Sjfv{ 1331169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1332169240Sjfv u32 phy_ctrl; 1333169240Sjfv s32 ret_val = E1000_SUCCESS; 1334169240Sjfv u16 data; 1335169240Sjfv 1336169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 1337169240Sjfv 1338173788Sjfv if (phy->type == e1000_phy_ife) 1339169240Sjfv goto out; 1340169240Sjfv 1341169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 1342169240Sjfv 1343169240Sjfv if (active) { 1344169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 1345169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1346169240Sjfv 1347194865Sjfv if (phy->type != e1000_phy_igp_3) 1348194865Sjfv goto out; 1349194865Sjfv 1350173788Sjfv /* 1351173788Sjfv * Call gig speed drop workaround on LPLU before accessing 1352173788Sjfv * any PHY registers 1353173788Sjfv */ 1354194865Sjfv if (hw->mac.type == e1000_ich8lan) 1355169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 1356169240Sjfv 1357169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1358177867Sjfv ret_val = phy->ops.read_reg(hw, 1359169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1360169240Sjfv &data); 1361169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1362177867Sjfv ret_val = phy->ops.write_reg(hw, 1363169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1364169240Sjfv data); 1365169240Sjfv if (ret_val) 1366169240Sjfv goto out; 1367169240Sjfv } else { 1368169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 1369169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1370169240Sjfv 1371194865Sjfv if (phy->type != e1000_phy_igp_3) 1372194865Sjfv goto out; 1373194865Sjfv 1374173788Sjfv /* 1375173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1376169240Sjfv * during Dx states where the power conservation is most 1377169240Sjfv * important. During driver activity we should enable 1378173788Sjfv * SmartSpeed, so performance is maintained. 1379173788Sjfv */ 1380169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1381177867Sjfv ret_val = phy->ops.read_reg(hw, 1382169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1383169240Sjfv &data); 1384169240Sjfv if (ret_val) 1385169240Sjfv goto out; 1386169240Sjfv 1387169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1388177867Sjfv ret_val = phy->ops.write_reg(hw, 1389169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1390169240Sjfv data); 1391169240Sjfv if (ret_val) 1392169240Sjfv goto out; 1393169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1394177867Sjfv ret_val = phy->ops.read_reg(hw, 1395169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1396169240Sjfv &data); 1397169240Sjfv if (ret_val) 1398169240Sjfv goto out; 1399169240Sjfv 1400169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1401177867Sjfv ret_val = phy->ops.write_reg(hw, 1402169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1403169240Sjfv data); 1404169240Sjfv if (ret_val) 1405169240Sjfv goto out; 1406169240Sjfv } 1407169240Sjfv } 1408169240Sjfv 1409169240Sjfvout: 1410169240Sjfv return ret_val; 1411169240Sjfv} 1412169240Sjfv 1413169240Sjfv/** 1414169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 1415169589Sjfv * @hw: pointer to the HW structure 1416169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1417169240Sjfv * 1418169240Sjfv * Sets the LPLU D3 state according to the active flag. When 1419169240Sjfv * activating LPLU this function also disables smart speed 1420169240Sjfv * and vice versa. LPLU will not be activated unless the 1421169240Sjfv * device autonegotiation advertisement meets standards of 1422169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 1423169240Sjfv * This is a function pointer entry point only called by 1424169240Sjfv * PHY setup routines. 1425169240Sjfv **/ 1426185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1427169240Sjfv{ 1428169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1429169240Sjfv u32 phy_ctrl; 1430169240Sjfv s32 ret_val = E1000_SUCCESS; 1431169240Sjfv u16 data; 1432169240Sjfv 1433169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 1434169240Sjfv 1435169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 1436169240Sjfv 1437169240Sjfv if (!active) { 1438169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 1439169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1440194865Sjfv 1441194865Sjfv if (phy->type != e1000_phy_igp_3) 1442194865Sjfv goto out; 1443194865Sjfv 1444173788Sjfv /* 1445173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1446169240Sjfv * during Dx states where the power conservation is most 1447169240Sjfv * important. During driver activity we should enable 1448173788Sjfv * SmartSpeed, so performance is maintained. 1449173788Sjfv */ 1450169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1451177867Sjfv ret_val = phy->ops.read_reg(hw, 1452169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1453169240Sjfv &data); 1454169240Sjfv if (ret_val) 1455169240Sjfv goto out; 1456169240Sjfv 1457169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1458177867Sjfv ret_val = phy->ops.write_reg(hw, 1459169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1460169240Sjfv data); 1461169240Sjfv if (ret_val) 1462169240Sjfv goto out; 1463169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1464177867Sjfv ret_val = phy->ops.read_reg(hw, 1465169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1466169240Sjfv &data); 1467169240Sjfv if (ret_val) 1468169240Sjfv goto out; 1469169240Sjfv 1470169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1471177867Sjfv ret_val = phy->ops.write_reg(hw, 1472169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1473169240Sjfv data); 1474169240Sjfv if (ret_val) 1475169240Sjfv goto out; 1476169240Sjfv } 1477169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1478169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1479169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1480169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 1481169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1482169240Sjfv 1483194865Sjfv if (phy->type != e1000_phy_igp_3) 1484194865Sjfv goto out; 1485194865Sjfv 1486173788Sjfv /* 1487173788Sjfv * Call gig speed drop workaround on LPLU before accessing 1488173788Sjfv * any PHY registers 1489173788Sjfv */ 1490194865Sjfv if (hw->mac.type == e1000_ich8lan) 1491169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 1492169240Sjfv 1493169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1494177867Sjfv ret_val = phy->ops.read_reg(hw, 1495169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1496169240Sjfv &data); 1497169240Sjfv if (ret_val) 1498169240Sjfv goto out; 1499169240Sjfv 1500169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1501177867Sjfv ret_val = phy->ops.write_reg(hw, 1502169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1503169240Sjfv data); 1504169240Sjfv } 1505169240Sjfv 1506169240Sjfvout: 1507169240Sjfv return ret_val; 1508169240Sjfv} 1509169240Sjfv 1510169240Sjfv/** 1511173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1512173788Sjfv * @hw: pointer to the HW structure 1513173788Sjfv * @bank: pointer to the variable that returns the active bank 1514173788Sjfv * 1515173788Sjfv * Reads signature byte from the NVM using the flash access registers. 1516190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 1517173788Sjfv **/ 1518177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1519173788Sjfv{ 1520190872Sjfv u32 eecd; 1521178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1522178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1523178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1524190872Sjfv u8 sig_byte = 0; 1525190872Sjfv s32 ret_val = E1000_SUCCESS; 1526178523Sjfv 1527190872Sjfv switch (hw->mac.type) { 1528190872Sjfv case e1000_ich8lan: 1529190872Sjfv case e1000_ich9lan: 1530190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 1531190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 1532190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 1533190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 1534190872Sjfv *bank = 1; 1535190872Sjfv else 1536190872Sjfv *bank = 0; 1537190872Sjfv 1538190872Sjfv goto out; 1539190872Sjfv } 1540190872Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - " 1541190872Sjfv "reading flash signature\n"); 1542190872Sjfv /* fall-thru */ 1543190872Sjfv default: 1544190872Sjfv /* set bank to 0 in case flash read fails */ 1545190872Sjfv *bank = 0; 1546190872Sjfv 1547190872Sjfv /* Check bank 0 */ 1548190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 1549190872Sjfv &sig_byte); 1550190872Sjfv if (ret_val) 1551190872Sjfv goto out; 1552190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1553200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 1554178523Sjfv *bank = 0; 1555190872Sjfv goto out; 1556190872Sjfv } 1557185353Sjfv 1558190872Sjfv /* Check bank 1 */ 1559190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 1560190872Sjfv bank1_offset, 1561200243Sjfv &sig_byte); 1562190872Sjfv if (ret_val) 1563190872Sjfv goto out; 1564190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1565200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 1566190872Sjfv *bank = 1; 1567190872Sjfv goto out; 1568178523Sjfv } 1569190872Sjfv 1570190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 1571190872Sjfv ret_val = -E1000_ERR_NVM; 1572190872Sjfv break; 1573178523Sjfv } 1574190872Sjfvout: 1575173788Sjfv return ret_val; 1576173788Sjfv} 1577173788Sjfv 1578173788Sjfv/** 1579169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1580169589Sjfv * @hw: pointer to the HW structure 1581169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 1582169589Sjfv * @words: Size of data to read in words 1583169589Sjfv * @data: Pointer to the word(s) to read at offset. 1584169240Sjfv * 1585169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 1586169240Sjfv **/ 1587177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1588173788Sjfv u16 *data) 1589169240Sjfv{ 1590169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1591185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1592169240Sjfv u32 act_offset; 1593169240Sjfv s32 ret_val = E1000_SUCCESS; 1594173788Sjfv u32 bank = 0; 1595169240Sjfv u16 i, word; 1596169240Sjfv 1597169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 1598169240Sjfv 1599169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1600169240Sjfv (words == 0)) { 1601169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1602169240Sjfv ret_val = -E1000_ERR_NVM; 1603169240Sjfv goto out; 1604169240Sjfv } 1605169240Sjfv 1606200243Sjfv nvm->ops.acquire(hw); 1607169240Sjfv 1608173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1609200243Sjfv if (ret_val != E1000_SUCCESS) { 1610200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 1611200243Sjfv bank = 0; 1612200243Sjfv } 1613173788Sjfv 1614173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 1615169240Sjfv act_offset += offset; 1616169240Sjfv 1617200243Sjfv ret_val = E1000_SUCCESS; 1618169240Sjfv for (i = 0; i < words; i++) { 1619173788Sjfv if ((dev_spec->shadow_ram) && 1620173788Sjfv (dev_spec->shadow_ram[offset+i].modified)) { 1621169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 1622169240Sjfv } else { 1623169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 1624169240Sjfv act_offset + i, 1625169240Sjfv &word); 1626169240Sjfv if (ret_val) 1627169240Sjfv break; 1628169240Sjfv data[i] = word; 1629169240Sjfv } 1630169240Sjfv } 1631169240Sjfv 1632177867Sjfv nvm->ops.release(hw); 1633169240Sjfv 1634169240Sjfvout: 1635190872Sjfv if (ret_val) 1636190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 1637190872Sjfv 1638169240Sjfv return ret_val; 1639169240Sjfv} 1640169240Sjfv 1641169240Sjfv/** 1642169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 1643169589Sjfv * @hw: pointer to the HW structure 1644169240Sjfv * 1645169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 1646169240Sjfv * can be started. 1647169240Sjfv **/ 1648173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1649169240Sjfv{ 1650169240Sjfv union ich8_hws_flash_status hsfsts; 1651169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1652169240Sjfv s32 i = 0; 1653169240Sjfv 1654169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1655169240Sjfv 1656169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1657169240Sjfv 1658169240Sjfv /* Check if the flash descriptor is valid */ 1659169240Sjfv if (hsfsts.hsf_status.fldesvalid == 0) { 1660169240Sjfv DEBUGOUT("Flash descriptor invalid. " 1661169240Sjfv "SW Sequencing must be used."); 1662169240Sjfv goto out; 1663169240Sjfv } 1664169240Sjfv 1665169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 1666169240Sjfv hsfsts.hsf_status.flcerr = 1; 1667169240Sjfv hsfsts.hsf_status.dael = 1; 1668169240Sjfv 1669169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1670169240Sjfv 1671173788Sjfv /* 1672173788Sjfv * Either we should have a hardware SPI cycle in progress 1673169240Sjfv * bit to check against, in order to start a new cycle or 1674169240Sjfv * FDONE bit should be changed in the hardware so that it 1675176667Sjfv * is 1 after hardware reset, which can then be used as an 1676169240Sjfv * indication whether a cycle is in progress or has been 1677169240Sjfv * completed. 1678169240Sjfv */ 1679169240Sjfv 1680169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1681173788Sjfv /* 1682173788Sjfv * There is no cycle running at present, 1683173788Sjfv * so we can start a cycle. 1684173788Sjfv * Begin by setting Flash Cycle Done. 1685173788Sjfv */ 1686169240Sjfv hsfsts.hsf_status.flcdone = 1; 1687169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1688169240Sjfv ret_val = E1000_SUCCESS; 1689169240Sjfv } else { 1690173788Sjfv /* 1691173788Sjfv * Otherwise poll for sometime so the current 1692173788Sjfv * cycle has a chance to end before giving up. 1693173788Sjfv */ 1694169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1695169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1696169240Sjfv ICH_FLASH_HSFSTS); 1697169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1698169240Sjfv ret_val = E1000_SUCCESS; 1699169240Sjfv break; 1700169240Sjfv } 1701169240Sjfv usec_delay(1); 1702169240Sjfv } 1703169240Sjfv if (ret_val == E1000_SUCCESS) { 1704173788Sjfv /* 1705173788Sjfv * Successful in waiting for previous cycle to timeout, 1706173788Sjfv * now set the Flash Cycle Done. 1707173788Sjfv */ 1708169240Sjfv hsfsts.hsf_status.flcdone = 1; 1709185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 1710169240Sjfv hsfsts.regval); 1711169240Sjfv } else { 1712169240Sjfv DEBUGOUT("Flash controller busy, cannot get access"); 1713169240Sjfv } 1714169240Sjfv } 1715169240Sjfv 1716169240Sjfvout: 1717169240Sjfv return ret_val; 1718169240Sjfv} 1719169240Sjfv 1720169240Sjfv/** 1721169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1722169589Sjfv * @hw: pointer to the HW structure 1723169589Sjfv * @timeout: maximum time to wait for completion 1724169240Sjfv * 1725169240Sjfv * This function starts a flash cycle and waits for its completion. 1726169240Sjfv **/ 1727173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1728169240Sjfv{ 1729169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1730169240Sjfv union ich8_hws_flash_status hsfsts; 1731169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1732169240Sjfv u32 i = 0; 1733169240Sjfv 1734169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1735169240Sjfv 1736169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1737169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1738169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 1739169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1740169240Sjfv 1741169240Sjfv /* wait till FDONE bit is set to 1 */ 1742169240Sjfv do { 1743169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1744169240Sjfv if (hsfsts.hsf_status.flcdone == 1) 1745169240Sjfv break; 1746169240Sjfv usec_delay(1); 1747169240Sjfv } while (i++ < timeout); 1748169240Sjfv 1749169240Sjfv if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1750169240Sjfv ret_val = E1000_SUCCESS; 1751169240Sjfv 1752169240Sjfv return ret_val; 1753169240Sjfv} 1754169240Sjfv 1755169240Sjfv/** 1756169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 1757169589Sjfv * @hw: pointer to the HW structure 1758169589Sjfv * @offset: offset to data location 1759169589Sjfv * @data: pointer to the location for storing the data 1760169240Sjfv * 1761169240Sjfv * Reads the flash word at offset into data. Offset is converted 1762169240Sjfv * to bytes before read. 1763169240Sjfv **/ 1764177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1765173788Sjfv u16 *data) 1766169240Sjfv{ 1767169240Sjfv s32 ret_val; 1768169240Sjfv 1769169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1770169240Sjfv 1771173788Sjfv if (!data) { 1772169240Sjfv ret_val = -E1000_ERR_NVM; 1773169240Sjfv goto out; 1774169240Sjfv } 1775169240Sjfv 1776169240Sjfv /* Must convert offset into bytes. */ 1777169240Sjfv offset <<= 1; 1778169240Sjfv 1779169240Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1780169240Sjfv 1781169240Sjfvout: 1782169240Sjfv return ret_val; 1783169240Sjfv} 1784169240Sjfv 1785169240Sjfv/** 1786178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 1787178523Sjfv * @hw: pointer to the HW structure 1788178523Sjfv * @offset: The offset of the byte to read. 1789178523Sjfv * @data: Pointer to a byte to store the value read. 1790178523Sjfv * 1791178523Sjfv * Reads a single byte from the NVM using the flash access registers. 1792178523Sjfv **/ 1793178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1794185353Sjfv u8 *data) 1795178523Sjfv{ 1796178523Sjfv s32 ret_val = E1000_SUCCESS; 1797178523Sjfv u16 word = 0; 1798178523Sjfv 1799178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1800178523Sjfv if (ret_val) 1801178523Sjfv goto out; 1802178523Sjfv 1803178523Sjfv *data = (u8)word; 1804178523Sjfv 1805178523Sjfvout: 1806178523Sjfv return ret_val; 1807178523Sjfv} 1808178523Sjfv 1809178523Sjfv/** 1810169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1811169589Sjfv * @hw: pointer to the HW structure 1812169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 1813169589Sjfv * @size: Size of data to read, 1=byte 2=word 1814169589Sjfv * @data: Pointer to the word to store the value read. 1815169240Sjfv * 1816169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 1817169240Sjfv **/ 1818173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1819185353Sjfv u8 size, u16 *data) 1820169240Sjfv{ 1821169240Sjfv union ich8_hws_flash_status hsfsts; 1822169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1823169240Sjfv u32 flash_linear_addr; 1824169240Sjfv u32 flash_data = 0; 1825169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1826169240Sjfv u8 count = 0; 1827169240Sjfv 1828169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1829169240Sjfv 1830173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1831169240Sjfv goto out; 1832169240Sjfv 1833169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1834169240Sjfv hw->nvm.flash_base_addr; 1835169240Sjfv 1836169240Sjfv do { 1837169240Sjfv usec_delay(1); 1838169240Sjfv /* Steps */ 1839169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1840169240Sjfv if (ret_val != E1000_SUCCESS) 1841169240Sjfv break; 1842169240Sjfv 1843169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1844169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1845169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 1846169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1847169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1848169240Sjfv 1849169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1850169240Sjfv 1851169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1852169240Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 1853169240Sjfv 1854173788Sjfv /* 1855173788Sjfv * Check if FCERR is set to 1, if set to 1, clear it 1856169240Sjfv * and try the whole sequence a few more times, else 1857169240Sjfv * read in (shift in) the Flash Data0, the order is 1858173788Sjfv * least significant byte first msb to lsb 1859173788Sjfv */ 1860169240Sjfv if (ret_val == E1000_SUCCESS) { 1861169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1862185353Sjfv if (size == 1) 1863169240Sjfv *data = (u8)(flash_data & 0x000000FF); 1864185353Sjfv else if (size == 2) 1865169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 1866169240Sjfv break; 1867169240Sjfv } else { 1868173788Sjfv /* 1869173788Sjfv * If we've gotten here, then things are probably 1870169240Sjfv * completely hosed, but if the error condition is 1871169240Sjfv * detected, it won't hurt to give it another try... 1872169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1873169240Sjfv */ 1874169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1875169240Sjfv ICH_FLASH_HSFSTS); 1876169240Sjfv if (hsfsts.hsf_status.flcerr == 1) { 1877169240Sjfv /* Repeat for some time before giving up. */ 1878169240Sjfv continue; 1879169240Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 1880169240Sjfv DEBUGOUT("Timeout error - flash cycle " 1881169240Sjfv "did not complete."); 1882169240Sjfv break; 1883169240Sjfv } 1884169240Sjfv } 1885169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1886169240Sjfv 1887169240Sjfvout: 1888169240Sjfv return ret_val; 1889169240Sjfv} 1890169240Sjfv 1891169240Sjfv/** 1892169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1893169589Sjfv * @hw: pointer to the HW structure 1894169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 1895169589Sjfv * @words: Size of data to write in words 1896169589Sjfv * @data: Pointer to the word(s) to write at offset. 1897169240Sjfv * 1898169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 1899169240Sjfv **/ 1900177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1901173788Sjfv u16 *data) 1902169240Sjfv{ 1903169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1904185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1905169240Sjfv s32 ret_val = E1000_SUCCESS; 1906169240Sjfv u16 i; 1907169240Sjfv 1908169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 1909169240Sjfv 1910169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1911169240Sjfv (words == 0)) { 1912169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1913169240Sjfv ret_val = -E1000_ERR_NVM; 1914169240Sjfv goto out; 1915169240Sjfv } 1916169240Sjfv 1917200243Sjfv nvm->ops.acquire(hw); 1918169240Sjfv 1919169240Sjfv for (i = 0; i < words; i++) { 1920169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 1921169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 1922169240Sjfv } 1923169240Sjfv 1924177867Sjfv nvm->ops.release(hw); 1925169240Sjfv 1926169240Sjfvout: 1927169240Sjfv return ret_val; 1928169240Sjfv} 1929169240Sjfv 1930169240Sjfv/** 1931169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1932169589Sjfv * @hw: pointer to the HW structure 1933169240Sjfv * 1934169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 1935169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 1936169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 1937169240Sjfv * checking for the modified bit and writing only the pending changes. 1938176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 1939169240Sjfv * future writes. 1940169240Sjfv **/ 1941177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1942169240Sjfv{ 1943169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1944185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1945173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1946169240Sjfv s32 ret_val; 1947169240Sjfv u16 data; 1948169240Sjfv 1949169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1950169240Sjfv 1951169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 1952169240Sjfv if (ret_val) 1953169240Sjfv goto out; 1954169240Sjfv 1955169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 1956169240Sjfv goto out; 1957169240Sjfv 1958200243Sjfv nvm->ops.acquire(hw); 1959169240Sjfv 1960173788Sjfv /* 1961173788Sjfv * We're writing to the opposite bank so if we're on bank 1, 1962169240Sjfv * write to bank 0 etc. We also need to erase the segment that 1963173788Sjfv * is going to be written 1964173788Sjfv */ 1965173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1966190872Sjfv if (ret_val != E1000_SUCCESS) { 1967200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 1968200243Sjfv bank = 0; 1969190872Sjfv } 1970173788Sjfv 1971173788Sjfv if (bank == 0) { 1972169240Sjfv new_bank_offset = nvm->flash_bank_size; 1973169240Sjfv old_bank_offset = 0; 1974190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 1975190872Sjfv if (ret_val) { 1976190872Sjfv nvm->ops.release(hw); 1977190872Sjfv goto out; 1978190872Sjfv } 1979169240Sjfv } else { 1980169240Sjfv old_bank_offset = nvm->flash_bank_size; 1981169240Sjfv new_bank_offset = 0; 1982190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 1983190872Sjfv if (ret_val) { 1984190872Sjfv nvm->ops.release(hw); 1985190872Sjfv goto out; 1986190872Sjfv } 1987169240Sjfv } 1988169240Sjfv 1989169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1990173788Sjfv /* 1991173788Sjfv * Determine whether to write the value stored 1992169240Sjfv * in the other NVM bank or a modified value stored 1993173788Sjfv * in the shadow RAM 1994173788Sjfv */ 1995173788Sjfv if (dev_spec->shadow_ram[i].modified) { 1996169240Sjfv data = dev_spec->shadow_ram[i].value; 1997169240Sjfv } else { 1998190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 1999190872Sjfv old_bank_offset, 2000190872Sjfv &data); 2001190872Sjfv if (ret_val) 2002190872Sjfv break; 2003169240Sjfv } 2004169240Sjfv 2005173788Sjfv /* 2006173788Sjfv * If the word is 0x13, then make sure the signature bits 2007169240Sjfv * (15:14) are 11b until the commit has completed. 2008169240Sjfv * This will allow us to write 10b which indicates the 2009169240Sjfv * signature is valid. We want to do this after the write 2010169240Sjfv * has completed so that we don't mark the segment valid 2011173788Sjfv * while the write is still in progress 2012173788Sjfv */ 2013169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 2014169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 2015169240Sjfv 2016169240Sjfv /* Convert offset to bytes. */ 2017169240Sjfv act_offset = (i + new_bank_offset) << 1; 2018169240Sjfv 2019169240Sjfv usec_delay(100); 2020169240Sjfv /* Write the bytes to the new bank. */ 2021169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2022169240Sjfv act_offset, 2023169240Sjfv (u8)data); 2024169240Sjfv if (ret_val) 2025169240Sjfv break; 2026169240Sjfv 2027169240Sjfv usec_delay(100); 2028169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2029169240Sjfv act_offset + 1, 2030169240Sjfv (u8)(data >> 8)); 2031169240Sjfv if (ret_val) 2032169240Sjfv break; 2033169240Sjfv } 2034169240Sjfv 2035173788Sjfv /* 2036173788Sjfv * Don't bother writing the segment valid bits if sector 2037173788Sjfv * programming failed. 2038173788Sjfv */ 2039169240Sjfv if (ret_val) { 2040169240Sjfv DEBUGOUT("Flash commit failed.\n"); 2041177867Sjfv nvm->ops.release(hw); 2042169240Sjfv goto out; 2043169240Sjfv } 2044169240Sjfv 2045173788Sjfv /* 2046173788Sjfv * Finally validate the new segment by setting bit 15:14 2047169240Sjfv * to 10b in word 0x13 , this can be done without an 2048169240Sjfv * erase as well since these bits are 11 to start with 2049173788Sjfv * and we need to change bit 14 to 0b 2050173788Sjfv */ 2051169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2052190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2053190872Sjfv if (ret_val) { 2054190872Sjfv nvm->ops.release(hw); 2055190872Sjfv goto out; 2056190872Sjfv } 2057200243Sjfv 2058169240Sjfv data &= 0xBFFF; 2059169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2060169240Sjfv act_offset * 2 + 1, 2061169240Sjfv (u8)(data >> 8)); 2062169240Sjfv if (ret_val) { 2063177867Sjfv nvm->ops.release(hw); 2064169240Sjfv goto out; 2065169240Sjfv } 2066169240Sjfv 2067173788Sjfv /* 2068173788Sjfv * And invalidate the previously valid segment by setting 2069169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 2070169240Sjfv * done without an erase because flash erase sets all bits 2071173788Sjfv * to 1's. We can write 1's to 0's without an erase 2072173788Sjfv */ 2073169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2074169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2075169240Sjfv if (ret_val) { 2076177867Sjfv nvm->ops.release(hw); 2077169240Sjfv goto out; 2078169240Sjfv } 2079169240Sjfv 2080169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 2081169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 2082169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 2083169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 2084169240Sjfv } 2085169240Sjfv 2086177867Sjfv nvm->ops.release(hw); 2087169240Sjfv 2088173788Sjfv /* 2089173788Sjfv * Reload the EEPROM, or else modifications will not appear 2090169240Sjfv * until after the next adapter reset. 2091169240Sjfv */ 2092177867Sjfv nvm->ops.reload(hw); 2093169240Sjfv msec_delay(10); 2094169240Sjfv 2095169240Sjfvout: 2096190872Sjfv if (ret_val) 2097190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 2098190872Sjfv 2099169240Sjfv return ret_val; 2100169240Sjfv} 2101169240Sjfv 2102169240Sjfv/** 2103169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 2104169589Sjfv * @hw: pointer to the HW structure 2105169240Sjfv * 2106169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 2107185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 2108185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 2109169240Sjfv **/ 2110177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 2111169240Sjfv{ 2112169240Sjfv s32 ret_val = E1000_SUCCESS; 2113169240Sjfv u16 data; 2114169240Sjfv 2115169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 2116169240Sjfv 2117173788Sjfv /* 2118173788Sjfv * Read 0x19 and check bit 6. If this bit is 0, the checksum 2119169240Sjfv * needs to be fixed. This bit is an indication that the NVM 2120169240Sjfv * was prepared by OEM software and did not calculate the 2121169240Sjfv * checksum...a likely scenario. 2122169240Sjfv */ 2123177867Sjfv ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 2124169240Sjfv if (ret_val) 2125169240Sjfv goto out; 2126169240Sjfv 2127169240Sjfv if ((data & 0x40) == 0) { 2128169240Sjfv data |= 0x40; 2129177867Sjfv ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 2130169240Sjfv if (ret_val) 2131169240Sjfv goto out; 2132177867Sjfv ret_val = hw->nvm.ops.update(hw); 2133169240Sjfv if (ret_val) 2134169240Sjfv goto out; 2135169240Sjfv } 2136169240Sjfv 2137169240Sjfv ret_val = e1000_validate_nvm_checksum_generic(hw); 2138169240Sjfv 2139169240Sjfvout: 2140169240Sjfv return ret_val; 2141169240Sjfv} 2142169240Sjfv 2143169240Sjfv/** 2144169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 2145169589Sjfv * @hw: pointer to the HW structure 2146169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 2147169589Sjfv * @size: Size of data to read, 1=byte 2=word 2148169589Sjfv * @data: The byte(s) to write to the NVM. 2149169240Sjfv * 2150169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 2151169240Sjfv **/ 2152173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2153173788Sjfv u8 size, u16 data) 2154169240Sjfv{ 2155169240Sjfv union ich8_hws_flash_status hsfsts; 2156169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2157169240Sjfv u32 flash_linear_addr; 2158169240Sjfv u32 flash_data = 0; 2159169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2160169240Sjfv u8 count = 0; 2161169240Sjfv 2162169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 2163169240Sjfv 2164169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 2165169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 2166169240Sjfv goto out; 2167169240Sjfv 2168169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2169169240Sjfv hw->nvm.flash_base_addr; 2170169240Sjfv 2171169240Sjfv do { 2172169240Sjfv usec_delay(1); 2173169240Sjfv /* Steps */ 2174169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2175169240Sjfv if (ret_val != E1000_SUCCESS) 2176169240Sjfv break; 2177169240Sjfv 2178169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2179169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2180185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 2181169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 2182169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2183169240Sjfv 2184169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 2185169240Sjfv 2186169240Sjfv if (size == 1) 2187169240Sjfv flash_data = (u32)data & 0x00FF; 2188169240Sjfv else 2189169240Sjfv flash_data = (u32)data; 2190169240Sjfv 2191169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 2192169240Sjfv 2193173788Sjfv /* 2194173788Sjfv * check if FCERR is set to 1 , if set to 1, clear it 2195173788Sjfv * and try the whole sequence a few more times else done 2196173788Sjfv */ 2197169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2198169240Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 2199185353Sjfv if (ret_val == E1000_SUCCESS) 2200169240Sjfv break; 2201185353Sjfv 2202185353Sjfv /* 2203185353Sjfv * If we're here, then things are most likely 2204185353Sjfv * completely hosed, but if the error condition 2205185353Sjfv * is detected, it won't hurt to give it another 2206185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 2207185353Sjfv */ 2208185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2209200243Sjfv if (hsfsts.hsf_status.flcerr == 1) 2210185353Sjfv /* Repeat for some time before giving up. */ 2211185353Sjfv continue; 2212200243Sjfv if (hsfsts.hsf_status.flcdone == 0) { 2213185353Sjfv DEBUGOUT("Timeout error - flash cycle " 2214185353Sjfv "did not complete."); 2215185353Sjfv break; 2216169240Sjfv } 2217169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2218169240Sjfv 2219169240Sjfvout: 2220169240Sjfv return ret_val; 2221169240Sjfv} 2222169240Sjfv 2223169240Sjfv/** 2224169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 2225169589Sjfv * @hw: pointer to the HW structure 2226169589Sjfv * @offset: The index of the byte to read. 2227169589Sjfv * @data: The byte to write to the NVM. 2228169240Sjfv * 2229169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2230169240Sjfv **/ 2231177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2232173788Sjfv u8 data) 2233169240Sjfv{ 2234169240Sjfv u16 word = (u16)data; 2235169240Sjfv 2236169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 2237169240Sjfv 2238169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 2239169240Sjfv} 2240169240Sjfv 2241169240Sjfv/** 2242169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 2243169589Sjfv * @hw: pointer to the HW structure 2244169589Sjfv * @offset: The offset of the byte to write. 2245169589Sjfv * @byte: The byte to write to the NVM. 2246169240Sjfv * 2247169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2248169240Sjfv * Goes through a retry algorithm before giving up. 2249169240Sjfv **/ 2250176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 2251176667Sjfv u32 offset, u8 byte) 2252169240Sjfv{ 2253169240Sjfv s32 ret_val; 2254169240Sjfv u16 program_retries; 2255169240Sjfv 2256169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 2257169240Sjfv 2258169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2259173788Sjfv if (ret_val == E1000_SUCCESS) 2260169240Sjfv goto out; 2261169240Sjfv 2262169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 2263169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 2264169240Sjfv usec_delay(100); 2265169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2266169240Sjfv if (ret_val == E1000_SUCCESS) 2267169240Sjfv break; 2268169240Sjfv } 2269169240Sjfv if (program_retries == 100) { 2270169240Sjfv ret_val = -E1000_ERR_NVM; 2271169240Sjfv goto out; 2272169240Sjfv } 2273169240Sjfv 2274169240Sjfvout: 2275169240Sjfv return ret_val; 2276169240Sjfv} 2277169240Sjfv 2278169240Sjfv/** 2279169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 2280169589Sjfv * @hw: pointer to the HW structure 2281169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 2282169240Sjfv * 2283169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 2284169240Sjfv * bank N is 4096 * N + flash_reg_addr. 2285169240Sjfv **/ 2286177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 2287169240Sjfv{ 2288169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2289169240Sjfv union ich8_hws_flash_status hsfsts; 2290169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2291169240Sjfv u32 flash_linear_addr; 2292173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 2293173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 2294185353Sjfv s32 ret_val = E1000_SUCCESS; 2295185353Sjfv s32 count = 0; 2296185353Sjfv s32 j, iteration, sector_size; 2297169240Sjfv 2298169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 2299169240Sjfv 2300169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2301169240Sjfv 2302173788Sjfv /* 2303173788Sjfv * Determine HW Sector size: Read BERASE bits of hw flash status 2304173788Sjfv * register 2305173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 2306169240Sjfv * consecutive sectors. The start index for the nth Hw sector 2307169240Sjfv * can be calculated as = bank * 4096 + n * 256 2308169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 2309169240Sjfv * The start index for the nth Hw sector can be calculated 2310169240Sjfv * as = bank * 4096 2311169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 2312169240Sjfv * (ich9 only, otherwise error condition) 2313169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 2314169240Sjfv */ 2315169240Sjfv switch (hsfsts.hsf_status.berasesz) { 2316169240Sjfv case 0: 2317169240Sjfv /* Hw sector size 256 */ 2318169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 2319169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 2320169240Sjfv break; 2321169240Sjfv case 1: 2322169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 2323194865Sjfv iteration = 1; 2324169240Sjfv break; 2325169240Sjfv case 2: 2326195850Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 2327195850Sjfv iteration = 1; 2328169240Sjfv break; 2329169240Sjfv case 3: 2330169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 2331194865Sjfv iteration = 1; 2332169240Sjfv break; 2333169240Sjfv default: 2334169240Sjfv ret_val = -E1000_ERR_NVM; 2335169240Sjfv goto out; 2336169240Sjfv } 2337169240Sjfv 2338169240Sjfv /* Start with the base address, then add the sector offset. */ 2339169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 2340200243Sjfv flash_linear_addr += (bank) ? flash_bank_size : 0; 2341169240Sjfv 2342169240Sjfv for (j = 0; j < iteration ; j++) { 2343169240Sjfv do { 2344169240Sjfv /* Steps */ 2345169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2346169240Sjfv if (ret_val) 2347169240Sjfv goto out; 2348169240Sjfv 2349173788Sjfv /* 2350173788Sjfv * Write a value 11 (block Erase) in Flash 2351173788Sjfv * Cycle field in hw flash control 2352173788Sjfv */ 2353169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 2354169240Sjfv ICH_FLASH_HSFCTL); 2355169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 2356185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 2357169240Sjfv hsflctl.regval); 2358169240Sjfv 2359173788Sjfv /* 2360173788Sjfv * Write the last 24 bits of an index within the 2361169240Sjfv * block into Flash Linear address field in Flash 2362169240Sjfv * Address. 2363169240Sjfv */ 2364169240Sjfv flash_linear_addr += (j * sector_size); 2365185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 2366169240Sjfv flash_linear_addr); 2367169240Sjfv 2368169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2369169240Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 2370185353Sjfv if (ret_val == E1000_SUCCESS) 2371169240Sjfv break; 2372185353Sjfv 2373185353Sjfv /* 2374185353Sjfv * Check if FCERR is set to 1. If 1, 2375185353Sjfv * clear it and try the whole sequence 2376185353Sjfv * a few more times else Done 2377185353Sjfv */ 2378185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2379185353Sjfv ICH_FLASH_HSFSTS); 2380185353Sjfv if (hsfsts.hsf_status.flcerr == 1) 2381185353Sjfv /* repeat for some time before giving up */ 2382185353Sjfv continue; 2383185353Sjfv else if (hsfsts.hsf_status.flcdone == 0) 2384185353Sjfv goto out; 2385169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 2386169240Sjfv } 2387169240Sjfv 2388169240Sjfvout: 2389169240Sjfv return ret_val; 2390169240Sjfv} 2391169240Sjfv 2392169240Sjfv/** 2393169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 2394169589Sjfv * @hw: pointer to the HW structure 2395169589Sjfv * @data: Pointer to the LED settings 2396169240Sjfv * 2397169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 2398169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 2399169240Sjfv * setting. 2400169240Sjfv **/ 2401177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 2402169240Sjfv{ 2403169240Sjfv s32 ret_val; 2404169240Sjfv 2405169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 2406169240Sjfv 2407177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 2408169240Sjfv if (ret_val) { 2409169240Sjfv DEBUGOUT("NVM Read Error\n"); 2410169240Sjfv goto out; 2411169240Sjfv } 2412169240Sjfv 2413169240Sjfv if (*data == ID_LED_RESERVED_0000 || 2414169240Sjfv *data == ID_LED_RESERVED_FFFF) 2415169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 2416169240Sjfv 2417169240Sjfvout: 2418169240Sjfv return ret_val; 2419169240Sjfv} 2420169240Sjfv 2421169240Sjfv/** 2422194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 2423194865Sjfv * @hw: pointer to the HW structure 2424194865Sjfv * 2425194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 2426194865Sjfv * the PHY LED configuration register. 2427194865Sjfv * 2428194865Sjfv * PCH also does not have an "always on" or "always off" mode which 2429194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 2430194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 2431194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 2432194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 2433194865Sjfv **/ 2434194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 2435194865Sjfv{ 2436194865Sjfv struct e1000_mac_info *mac = &hw->mac; 2437194865Sjfv s32 ret_val; 2438194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 2439194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 2440194865Sjfv u16 data, i, temp, shift; 2441194865Sjfv 2442194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 2443194865Sjfv 2444194865Sjfv /* Get default ID LED modes */ 2445194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 2446194865Sjfv if (ret_val) 2447194865Sjfv goto out; 2448194865Sjfv 2449194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 2450194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 2451194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 2452194865Sjfv 2453194865Sjfv for (i = 0; i < 4; i++) { 2454194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 2455194865Sjfv shift = (i * 5); 2456194865Sjfv switch (temp) { 2457194865Sjfv case ID_LED_ON1_DEF2: 2458194865Sjfv case ID_LED_ON1_ON2: 2459194865Sjfv case ID_LED_ON1_OFF2: 2460194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2461194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 2462194865Sjfv break; 2463194865Sjfv case ID_LED_OFF1_DEF2: 2464194865Sjfv case ID_LED_OFF1_ON2: 2465194865Sjfv case ID_LED_OFF1_OFF2: 2466194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2467194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 2468194865Sjfv break; 2469194865Sjfv default: 2470194865Sjfv /* Do nothing */ 2471194865Sjfv break; 2472194865Sjfv } 2473194865Sjfv switch (temp) { 2474194865Sjfv case ID_LED_DEF1_ON2: 2475194865Sjfv case ID_LED_ON1_ON2: 2476194865Sjfv case ID_LED_OFF1_ON2: 2477194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2478194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 2479194865Sjfv break; 2480194865Sjfv case ID_LED_DEF1_OFF2: 2481194865Sjfv case ID_LED_ON1_OFF2: 2482194865Sjfv case ID_LED_OFF1_OFF2: 2483194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2484194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 2485194865Sjfv break; 2486194865Sjfv default: 2487194865Sjfv /* Do nothing */ 2488194865Sjfv break; 2489194865Sjfv } 2490194865Sjfv } 2491194865Sjfv 2492194865Sjfvout: 2493194865Sjfv return ret_val; 2494194865Sjfv} 2495194865Sjfv 2496194865Sjfv/** 2497169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 2498169589Sjfv * @hw: pointer to the HW structure 2499169240Sjfv * 2500169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 2501169240Sjfv * register, so the the bus width is hard coded. 2502169240Sjfv **/ 2503177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 2504169240Sjfv{ 2505169240Sjfv struct e1000_bus_info *bus = &hw->bus; 2506169240Sjfv s32 ret_val; 2507169240Sjfv 2508169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 2509169240Sjfv 2510169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 2511169240Sjfv 2512173788Sjfv /* 2513173788Sjfv * ICH devices are "PCI Express"-ish. They have 2514169240Sjfv * a configuration space, but do not contain 2515169240Sjfv * PCI Express Capability registers, so bus width 2516169240Sjfv * must be hardcoded. 2517169240Sjfv */ 2518169240Sjfv if (bus->width == e1000_bus_width_unknown) 2519169240Sjfv bus->width = e1000_bus_width_pcie_x1; 2520169240Sjfv 2521169240Sjfv return ret_val; 2522169240Sjfv} 2523169240Sjfv 2524169240Sjfv/** 2525169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 2526169589Sjfv * @hw: pointer to the HW structure 2527169240Sjfv * 2528169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 2529169240Sjfv * MAC. 2530169240Sjfv **/ 2531177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 2532169240Sjfv{ 2533200243Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2534200243Sjfv u16 reg; 2535169240Sjfv u32 ctrl, icr, kab; 2536169240Sjfv s32 ret_val; 2537169240Sjfv 2538169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 2539169240Sjfv 2540173788Sjfv /* 2541173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 2542169240Sjfv * on the last TLP read/write transaction when MAC is reset. 2543169240Sjfv */ 2544169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 2545185353Sjfv if (ret_val) 2546169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2547169240Sjfv 2548169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 2549169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2550169240Sjfv 2551173788Sjfv /* 2552173788Sjfv * Disable the Transmit and Receive units. Then delay to allow 2553169240Sjfv * any pending transactions to complete before we hit the MAC 2554169240Sjfv * with the global reset. 2555169240Sjfv */ 2556169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 2557169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2558169240Sjfv E1000_WRITE_FLUSH(hw); 2559169240Sjfv 2560169240Sjfv msec_delay(10); 2561169240Sjfv 2562169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 2563169240Sjfv if (hw->mac.type == e1000_ich8lan) { 2564169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 2565169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 2566169240Sjfv /* Set Packet Buffer Size to 16k. */ 2567169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 2568169240Sjfv } 2569169240Sjfv 2570200243Sjfv if (hw->mac.type == e1000_pchlan) { 2571200243Sjfv /* Save the NVM K1 bit setting*/ 2572200243Sjfv ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); 2573200243Sjfv if (ret_val) 2574200243Sjfv return ret_val; 2575200243Sjfv 2576200243Sjfv if (reg & E1000_NVM_K1_ENABLE) 2577200243Sjfv dev_spec->nvm_k1_enabled = TRUE; 2578200243Sjfv else 2579200243Sjfv dev_spec->nvm_k1_enabled = FALSE; 2580200243Sjfv } 2581200243Sjfv 2582169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2583169240Sjfv 2584177867Sjfv if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 2585194865Sjfv /* Clear PHY Reset Asserted bit */ 2586194865Sjfv if (hw->mac.type >= e1000_pchlan) { 2587194865Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 2588194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & 2589194865Sjfv ~E1000_STATUS_PHYRA); 2590194865Sjfv } 2591194865Sjfv 2592173788Sjfv /* 2593173788Sjfv * PHY HW reset requires MAC CORE reset at the same 2594169240Sjfv * time to make sure the interface between MAC and the 2595169240Sjfv * external PHY is reset. 2596169240Sjfv */ 2597169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 2598169240Sjfv } 2599169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 2600185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 2601169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2602169240Sjfv msec_delay(20); 2603169240Sjfv 2604194865Sjfv if (!ret_val) 2605194865Sjfv e1000_release_swflag_ich8lan(hw); 2606194865Sjfv 2607194865Sjfv if (ctrl & E1000_CTRL_PHY_RST) 2608194865Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 2609194865Sjfv 2610194865Sjfv if (hw->mac.type >= e1000_ich10lan) { 2611194865Sjfv e1000_lan_init_done_ich8lan(hw); 2612194865Sjfv } else { 2613194865Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 2614194865Sjfv if (ret_val) { 2615194865Sjfv /* 2616194865Sjfv * When auto config read does not complete, do not 2617194865Sjfv * return with an error. This can happen in situations 2618194865Sjfv * where there is no eeprom and prevents getting link. 2619194865Sjfv */ 2620194865Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 2621194865Sjfv } 2622169240Sjfv } 2623200243Sjfv /* Dummy read to clear the phy wakeup bit after lcd reset */ 2624200243Sjfv if (hw->mac.type == e1000_pchlan) 2625200243Sjfv hw->phy.ops.read_reg(hw, BM_WUC, ®); 2626169240Sjfv 2627200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 2628200243Sjfv if (ret_val) 2629200243Sjfv goto out; 2630200243Sjfv 2631200243Sjfv if (hw->mac.type == e1000_pchlan) { 2632200243Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 2633200243Sjfv if (ret_val) 2634200243Sjfv goto out; 2635200243Sjfv } 2636200243Sjfv /* 2637200243Sjfv * For PCH, this write will make sure that any noise 2638200243Sjfv * will be detected as a CRC error and be dropped rather than show up 2639200243Sjfv * as a bad packet to the DMA engine. 2640200243Sjfv */ 2641200243Sjfv if (hw->mac.type == e1000_pchlan) 2642200243Sjfv E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 2643200243Sjfv 2644169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2645169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 2646169240Sjfv 2647169240Sjfv kab = E1000_READ_REG(hw, E1000_KABGTXD); 2648169240Sjfv kab |= E1000_KABGTXD_BGSQLBIAS; 2649169240Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2650169240Sjfv 2651194865Sjfv if (hw->mac.type == e1000_pchlan) 2652194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2653194865Sjfv 2654200243Sjfvout: 2655169240Sjfv return ret_val; 2656169240Sjfv} 2657169240Sjfv 2658169240Sjfv/** 2659169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 2660169589Sjfv * @hw: pointer to the HW structure 2661169240Sjfv * 2662169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 2663169240Sjfv * - initialize hardware bits 2664169240Sjfv * - initialize LED identification 2665169240Sjfv * - setup receive address registers 2666169240Sjfv * - setup flow control 2667176667Sjfv * - setup transmit descriptors 2668169240Sjfv * - clear statistics 2669169240Sjfv **/ 2670177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2671169240Sjfv{ 2672169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2673169240Sjfv u32 ctrl_ext, txdctl, snoop; 2674169240Sjfv s32 ret_val; 2675169240Sjfv u16 i; 2676169240Sjfv 2677169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 2678169240Sjfv 2679169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 2680169240Sjfv 2681169240Sjfv /* Initialize identification LED */ 2682190872Sjfv ret_val = mac->ops.id_led_init(hw); 2683190872Sjfv if (ret_val) 2684200243Sjfv DEBUGOUT("Error initializing identification LED\n"); 2685190872Sjfv /* This is not fatal and we should not stop init due to this */ 2686169240Sjfv 2687169240Sjfv /* Setup the receive address. */ 2688169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2689169240Sjfv 2690169240Sjfv /* Zero out the Multicast HASH table */ 2691169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 2692169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 2693169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2694169240Sjfv 2695194865Sjfv /* 2696194865Sjfv * The 82578 Rx buffer will stall if wakeup is enabled in host and 2697194865Sjfv * the ME. Reading the BM_WUC register will clear the host wakeup bit. 2698194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 2699194865Sjfv */ 2700194865Sjfv if (hw->phy.type == e1000_phy_82578) { 2701194865Sjfv hw->phy.ops.read_reg(hw, BM_WUC, &i); 2702194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 2703194865Sjfv if (ret_val) 2704194865Sjfv return ret_val; 2705194865Sjfv } 2706194865Sjfv 2707169240Sjfv /* Setup link and flow control */ 2708177867Sjfv ret_val = mac->ops.setup_link(hw); 2709169240Sjfv 2710169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 2711173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2712169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2713169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2714169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2715169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2716173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2717173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2718169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2719169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2720169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2721169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2722173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2723169240Sjfv 2724173788Sjfv /* 2725173788Sjfv * ICH8 has opposite polarity of no_snoop bits. 2726173788Sjfv * By default, we should use snoop behavior. 2727173788Sjfv */ 2728169240Sjfv if (mac->type == e1000_ich8lan) 2729169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 2730169240Sjfv else 2731200243Sjfv snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 2732169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 2733169240Sjfv 2734169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2735169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2736169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2737169240Sjfv 2738173788Sjfv /* 2739173788Sjfv * Clear all of the statistics registers (clear on read). It is 2740169240Sjfv * important that we do this after we have tried to establish link 2741169240Sjfv * because the symbol error count will increment wildly if there 2742169240Sjfv * is no link. 2743169240Sjfv */ 2744169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 2745169240Sjfv 2746169240Sjfv return ret_val; 2747169240Sjfv} 2748169240Sjfv/** 2749169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2750169589Sjfv * @hw: pointer to the HW structure 2751169240Sjfv * 2752169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 2753169240Sjfv * hardware for transmit and receive. 2754169240Sjfv **/ 2755173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2756169240Sjfv{ 2757169240Sjfv u32 reg; 2758169240Sjfv 2759169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2760169240Sjfv 2761169240Sjfv /* Extended Device Control */ 2762169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2763169240Sjfv reg |= (1 << 22); 2764194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 2765194865Sjfv if (hw->mac.type >= e1000_pchlan) 2766194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 2767169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2768169240Sjfv 2769169240Sjfv /* Transmit Descriptor Control 0 */ 2770173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2771169240Sjfv reg |= (1 << 22); 2772173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2773169240Sjfv 2774169240Sjfv /* Transmit Descriptor Control 1 */ 2775173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2776169240Sjfv reg |= (1 << 22); 2777173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2778169240Sjfv 2779169240Sjfv /* Transmit Arbitration Control 0 */ 2780173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 2781169240Sjfv if (hw->mac.type == e1000_ich8lan) 2782169240Sjfv reg |= (1 << 28) | (1 << 29); 2783169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2784173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2785169240Sjfv 2786169240Sjfv /* Transmit Arbitration Control 1 */ 2787173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 2788169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2789169240Sjfv reg &= ~(1 << 28); 2790169240Sjfv else 2791169240Sjfv reg |= (1 << 28); 2792169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 2793173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2794169240Sjfv 2795169240Sjfv /* Device Status */ 2796169240Sjfv if (hw->mac.type == e1000_ich8lan) { 2797169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 2798169240Sjfv reg &= ~(1 << 31); 2799169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 2800169240Sjfv } 2801169240Sjfv 2802169240Sjfv return; 2803169240Sjfv} 2804169240Sjfv 2805169240Sjfv/** 2806169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 2807169589Sjfv * @hw: pointer to the HW structure 2808169240Sjfv * 2809169240Sjfv * Determines which flow control settings to use, then configures flow 2810169240Sjfv * control. Calls the appropriate media-specific link configuration 2811169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 2812169240Sjfv * should be established. Assumes the hardware has previously been reset 2813169240Sjfv * and the transmitter and receiver are not enabled. 2814169240Sjfv **/ 2815177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2816169240Sjfv{ 2817169240Sjfv s32 ret_val = E1000_SUCCESS; 2818169240Sjfv 2819169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 2820169240Sjfv 2821177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 2822169240Sjfv goto out; 2823169240Sjfv 2824173788Sjfv /* 2825173788Sjfv * ICH parts do not have a word in the NVM to determine 2826169240Sjfv * the default flow control setting, so we explicitly 2827169240Sjfv * set it to full. 2828169240Sjfv */ 2829185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 2830185353Sjfv hw->fc.requested_mode = e1000_fc_full; 2831169240Sjfv 2832185353Sjfv /* 2833185353Sjfv * Save off the requested flow control mode for use later. Depending 2834185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 2835185353Sjfv */ 2836185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 2837169240Sjfv 2838185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 2839190872Sjfv hw->fc.current_mode); 2840169240Sjfv 2841169240Sjfv /* Continue to configure the copper link. */ 2842177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 2843169240Sjfv if (ret_val) 2844169240Sjfv goto out; 2845169240Sjfv 2846173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2847194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 2848194865Sjfv (hw->phy.type == e1000_phy_82577)) { 2849194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 2850194865Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 2851194865Sjfv hw->fc.pause_time); 2852194865Sjfv if (ret_val) 2853194865Sjfv goto out; 2854194865Sjfv } 2855169240Sjfv 2856169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 2857169240Sjfv 2858169240Sjfvout: 2859169240Sjfv return ret_val; 2860169240Sjfv} 2861169240Sjfv 2862169240Sjfv/** 2863169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2864169589Sjfv * @hw: pointer to the HW structure 2865169240Sjfv * 2866169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 2867169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 2868169240Sjfv * configuring the copper link. 2869169240Sjfv **/ 2870177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2871169240Sjfv{ 2872169240Sjfv u32 ctrl; 2873169240Sjfv s32 ret_val; 2874169240Sjfv u16 reg_data; 2875169240Sjfv 2876169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2877169240Sjfv 2878169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2879169240Sjfv ctrl |= E1000_CTRL_SLU; 2880169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2881169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2882169240Sjfv 2883173788Sjfv /* 2884173788Sjfv * Set the mac to wait the maximum time between each iteration 2885169240Sjfv * and increase the max iterations when polling the phy; 2886173788Sjfv * this fixes erroneous timeouts at 10Mbps. 2887173788Sjfv */ 2888200243Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 2889181027Sjfv 0xFFFF); 2890169240Sjfv if (ret_val) 2891169240Sjfv goto out; 2892194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2893194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 2894181027Sjfv ®_data); 2895169240Sjfv if (ret_val) 2896169240Sjfv goto out; 2897169240Sjfv reg_data |= 0x3F; 2898194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2899194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 2900181027Sjfv reg_data); 2901169240Sjfv if (ret_val) 2902169240Sjfv goto out; 2903169240Sjfv 2904190872Sjfv switch (hw->phy.type) { 2905190872Sjfv case e1000_phy_igp_3: 2906169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 2907169240Sjfv if (ret_val) 2908169240Sjfv goto out; 2909190872Sjfv break; 2910190872Sjfv case e1000_phy_bm: 2911194865Sjfv case e1000_phy_82578: 2912176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 2913176667Sjfv if (ret_val) 2914176667Sjfv goto out; 2915190872Sjfv break; 2916194865Sjfv case e1000_phy_82577: 2917194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 2918194865Sjfv if (ret_val) 2919194865Sjfv goto out; 2920194865Sjfv break; 2921190872Sjfv case e1000_phy_ife: 2922177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2923177867Sjfv ®_data); 2924173788Sjfv if (ret_val) 2925173788Sjfv goto out; 2926173788Sjfv 2927173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 2928173788Sjfv 2929173788Sjfv switch (hw->phy.mdix) { 2930173788Sjfv case 1: 2931173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 2932173788Sjfv break; 2933173788Sjfv case 2: 2934173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 2935173788Sjfv break; 2936173788Sjfv case 0: 2937173788Sjfv default: 2938173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 2939173788Sjfv break; 2940173788Sjfv } 2941177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2942177867Sjfv reg_data); 2943173788Sjfv if (ret_val) 2944173788Sjfv goto out; 2945190872Sjfv break; 2946190872Sjfv default: 2947190872Sjfv break; 2948173788Sjfv } 2949169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 2950169240Sjfv 2951169240Sjfvout: 2952169240Sjfv return ret_val; 2953169240Sjfv} 2954169240Sjfv 2955169240Sjfv/** 2956169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2957169589Sjfv * @hw: pointer to the HW structure 2958169589Sjfv * @speed: pointer to store current link speed 2959169589Sjfv * @duplex: pointer to store the current link duplex 2960169240Sjfv * 2961176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 2962169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 2963169240Sjfv * gigabit speeds. 2964169240Sjfv **/ 2965177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2966173788Sjfv u16 *duplex) 2967169240Sjfv{ 2968169240Sjfv s32 ret_val; 2969169240Sjfv 2970169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2971169240Sjfv 2972169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2973169240Sjfv if (ret_val) 2974169240Sjfv goto out; 2975169240Sjfv 2976169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 2977169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 2978169240Sjfv (*speed == SPEED_1000)) { 2979169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2980169240Sjfv } 2981169240Sjfv 2982169240Sjfvout: 2983169240Sjfv return ret_val; 2984169240Sjfv} 2985169240Sjfv 2986169240Sjfv/** 2987169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2988169589Sjfv * @hw: pointer to the HW structure 2989169240Sjfv * 2990169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 2991169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 2992169240Sjfv * speed is gigabit- 2993169240Sjfv * 0) if workaround is optionally disabled do nothing 2994169240Sjfv * 1) wait 1ms for Kumeran link to come up 2995169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 2996169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 2997169240Sjfv * 4) reset the PHY 2998169240Sjfv * 5) repeat up to 10 times 2999169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 3000169240Sjfv **/ 3001173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3002169240Sjfv{ 3003185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3004169240Sjfv u32 phy_ctrl; 3005169240Sjfv s32 ret_val = E1000_SUCCESS; 3006169240Sjfv u16 i, data; 3007173788Sjfv bool link; 3008169240Sjfv 3009169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 3010169240Sjfv 3011173788Sjfv if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 3012169240Sjfv goto out; 3013169240Sjfv 3014173788Sjfv /* 3015173788Sjfv * Make sure link is up before proceeding. If not just return. 3016169240Sjfv * Attempting this while link is negotiating fouled up link 3017173788Sjfv * stability 3018173788Sjfv */ 3019169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3020169240Sjfv if (!link) { 3021169240Sjfv ret_val = E1000_SUCCESS; 3022169240Sjfv goto out; 3023169240Sjfv } 3024169240Sjfv 3025169240Sjfv for (i = 0; i < 10; i++) { 3026169240Sjfv /* read once to clear */ 3027177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3028169240Sjfv if (ret_val) 3029169240Sjfv goto out; 3030169240Sjfv /* and again to get new status */ 3031177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3032169240Sjfv if (ret_val) 3033169240Sjfv goto out; 3034169240Sjfv 3035169240Sjfv /* check for PCS lock */ 3036169240Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 3037169240Sjfv ret_val = E1000_SUCCESS; 3038169240Sjfv goto out; 3039169240Sjfv } 3040169240Sjfv 3041169240Sjfv /* Issue PHY reset */ 3042177867Sjfv hw->phy.ops.reset(hw); 3043169240Sjfv msec_delay_irq(5); 3044169240Sjfv } 3045169240Sjfv /* Disable GigE link negotiation */ 3046169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3047169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 3048169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3049169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3050169240Sjfv 3051173788Sjfv /* 3052176667Sjfv * Call gig speed drop workaround on Gig disable before accessing 3053173788Sjfv * any PHY registers 3054173788Sjfv */ 3055169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3056169240Sjfv 3057169240Sjfv /* unable to acquire PCS lock */ 3058169240Sjfv ret_val = -E1000_ERR_PHY; 3059169240Sjfv 3060169240Sjfvout: 3061169240Sjfv return ret_val; 3062169240Sjfv} 3063169240Sjfv 3064169240Sjfv/** 3065176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 3066169589Sjfv * @hw: pointer to the HW structure 3067176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 3068169240Sjfv * 3069169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 3070169240Sjfv * /disabled - FALSE). 3071169240Sjfv **/ 3072173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3073173788Sjfv bool state) 3074169240Sjfv{ 3075185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3076169240Sjfv 3077169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 3078169240Sjfv 3079169240Sjfv if (hw->mac.type != e1000_ich8lan) { 3080169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 3081185353Sjfv return; 3082169240Sjfv } 3083169240Sjfv 3084169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 3085169240Sjfv 3086169240Sjfv return; 3087169240Sjfv} 3088169240Sjfv 3089169240Sjfv/** 3090169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 3091169589Sjfv * @hw: pointer to the HW structure 3092169240Sjfv * 3093169240Sjfv * Workaround for 82566 power-down on D3 entry: 3094169240Sjfv * 1) disable gigabit link 3095169240Sjfv * 2) write VR power-down enable 3096169240Sjfv * 3) read it back 3097169240Sjfv * Continue if successful, else issue LCD reset and repeat 3098169240Sjfv **/ 3099173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 3100169240Sjfv{ 3101169240Sjfv u32 reg; 3102169240Sjfv u16 data; 3103169240Sjfv u8 retry = 0; 3104169240Sjfv 3105169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 3106169240Sjfv 3107169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 3108169240Sjfv goto out; 3109169240Sjfv 3110169240Sjfv /* Try the workaround twice (if needed) */ 3111169240Sjfv do { 3112169240Sjfv /* Disable link */ 3113169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 3114169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 3115169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3116169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 3117169240Sjfv 3118173788Sjfv /* 3119176667Sjfv * Call gig speed drop workaround on Gig disable before 3120173788Sjfv * accessing any PHY registers 3121173788Sjfv */ 3122169240Sjfv if (hw->mac.type == e1000_ich8lan) 3123169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3124169240Sjfv 3125169240Sjfv /* Write VR power-down enable */ 3126177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3127169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3128185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 3129169240Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 3130169240Sjfv 3131169240Sjfv /* Read it back and test */ 3132177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3133169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3134169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 3135169240Sjfv break; 3136169240Sjfv 3137169240Sjfv /* Issue PHY reset and repeat at most one more time */ 3138169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 3139169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 3140169240Sjfv retry++; 3141169240Sjfv } while (retry); 3142169240Sjfv 3143169240Sjfvout: 3144169240Sjfv return; 3145169240Sjfv} 3146169240Sjfv 3147169240Sjfv/** 3148169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 3149169589Sjfv * @hw: pointer to the HW structure 3150169240Sjfv * 3151169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 3152176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 3153169240Sjfv * 1) Set Kumeran Near-end loopback 3154169240Sjfv * 2) Clear Kumeran Near-end loopback 3155169240Sjfv * Should only be called for ICH8[m] devices with IGP_3 Phy. 3156169240Sjfv **/ 3157173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 3158169240Sjfv{ 3159169240Sjfv s32 ret_val = E1000_SUCCESS; 3160169240Sjfv u16 reg_data; 3161169240Sjfv 3162169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 3163169240Sjfv 3164169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 3165169240Sjfv (hw->phy.type != e1000_phy_igp_3)) 3166169240Sjfv goto out; 3167169240Sjfv 3168181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3169181027Sjfv ®_data); 3170169240Sjfv if (ret_val) 3171169240Sjfv goto out; 3172169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 3173181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3174181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3175181027Sjfv reg_data); 3176169240Sjfv if (ret_val) 3177169240Sjfv goto out; 3178169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 3179181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3180181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3181181027Sjfv reg_data); 3182169240Sjfvout: 3183169240Sjfv return; 3184169240Sjfv} 3185169240Sjfv 3186169240Sjfv/** 3187176667Sjfv * e1000_disable_gig_wol_ich8lan - disable gig during WoL 3188176667Sjfv * @hw: pointer to the HW structure 3189176667Sjfv * 3190176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 3191176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 3192176667Sjfv * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 3193176667Sjfv * to a lower speed. 3194176667Sjfv * 3195190872Sjfv * Should only be called for applicable parts. 3196176667Sjfv **/ 3197176667Sjfvvoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 3198176667Sjfv{ 3199176667Sjfv u32 phy_ctrl; 3200176667Sjfv 3201190872Sjfv switch (hw->mac.type) { 3202200243Sjfv case e1000_ich8lan: 3203190872Sjfv case e1000_ich9lan: 3204190872Sjfv case e1000_ich10lan: 3205194865Sjfv case e1000_pchlan: 3206176667Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3207176667Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 3208176667Sjfv E1000_PHY_CTRL_GBE_DISABLE; 3209176667Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3210194865Sjfv 3211194865Sjfv if (hw->mac.type == e1000_pchlan) 3212200243Sjfv e1000_phy_hw_reset_ich8lan(hw); 3213190872Sjfv default: 3214190872Sjfv break; 3215176667Sjfv } 3216176667Sjfv 3217176667Sjfv return; 3218176667Sjfv} 3219176667Sjfv 3220176667Sjfv/** 3221169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 3222169589Sjfv * @hw: pointer to the HW structure 3223169240Sjfv * 3224169240Sjfv * Return the LED back to the default configuration. 3225169240Sjfv **/ 3226177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 3227169240Sjfv{ 3228169240Sjfv s32 ret_val = E1000_SUCCESS; 3229169240Sjfv 3230169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 3231169240Sjfv 3232169240Sjfv if (hw->phy.type == e1000_phy_ife) 3233185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3234176667Sjfv 0); 3235169240Sjfv else 3236169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 3237169240Sjfv 3238169240Sjfv return ret_val; 3239169240Sjfv} 3240169240Sjfv 3241169240Sjfv/** 3242176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 3243169589Sjfv * @hw: pointer to the HW structure 3244169240Sjfv * 3245176667Sjfv * Turn on the LEDs. 3246169240Sjfv **/ 3247177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 3248169240Sjfv{ 3249169240Sjfv s32 ret_val = E1000_SUCCESS; 3250169240Sjfv 3251169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 3252169240Sjfv 3253169240Sjfv if (hw->phy.type == e1000_phy_ife) 3254185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3255169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 3256169240Sjfv else 3257169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 3258169240Sjfv 3259169240Sjfv return ret_val; 3260169240Sjfv} 3261169240Sjfv 3262169240Sjfv/** 3263176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 3264169589Sjfv * @hw: pointer to the HW structure 3265169240Sjfv * 3266176667Sjfv * Turn off the LEDs. 3267169240Sjfv **/ 3268177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 3269169240Sjfv{ 3270169240Sjfv s32 ret_val = E1000_SUCCESS; 3271169240Sjfv 3272169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 3273169240Sjfv 3274169240Sjfv if (hw->phy.type == e1000_phy_ife) 3275177867Sjfv ret_val = hw->phy.ops.write_reg(hw, 3276169240Sjfv IFE_PHY_SPECIAL_CONTROL_LED, 3277169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3278169240Sjfv else 3279169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 3280169240Sjfv 3281169240Sjfv return ret_val; 3282169240Sjfv} 3283169240Sjfv 3284169240Sjfv/** 3285194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 3286194865Sjfv * @hw: pointer to the HW structure 3287194865Sjfv * 3288194865Sjfv * This prepares the SW controllable LED for use. 3289194865Sjfv **/ 3290194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3291194865Sjfv{ 3292194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 3293194865Sjfv 3294194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3295194865Sjfv (u16)hw->mac.ledctl_mode1); 3296194865Sjfv} 3297194865Sjfv 3298194865Sjfv/** 3299194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 3300194865Sjfv * @hw: pointer to the HW structure 3301194865Sjfv * 3302194865Sjfv * Return the LED back to the default configuration. 3303194865Sjfv **/ 3304194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3305194865Sjfv{ 3306194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 3307194865Sjfv 3308194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3309194865Sjfv (u16)hw->mac.ledctl_default); 3310194865Sjfv} 3311194865Sjfv 3312194865Sjfv/** 3313194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 3314194865Sjfv * @hw: pointer to the HW structure 3315194865Sjfv * 3316194865Sjfv * Turn on the LEDs. 3317194865Sjfv **/ 3318194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 3319194865Sjfv{ 3320194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 3321194865Sjfv u32 i, led; 3322194865Sjfv 3323194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 3324194865Sjfv 3325194865Sjfv /* 3326194865Sjfv * If no link, then turn LED on by setting the invert bit 3327194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 3328194865Sjfv */ 3329194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 3330194865Sjfv for (i = 0; i < 3; i++) { 3331194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 3332194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 3333194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 3334194865Sjfv continue; 3335194865Sjfv if (led & E1000_PHY_LED0_IVRT) 3336194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 3337194865Sjfv else 3338194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 3339194865Sjfv } 3340194865Sjfv } 3341194865Sjfv 3342194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3343194865Sjfv} 3344194865Sjfv 3345194865Sjfv/** 3346194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 3347194865Sjfv * @hw: pointer to the HW structure 3348194865Sjfv * 3349194865Sjfv * Turn off the LEDs. 3350194865Sjfv **/ 3351194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 3352194865Sjfv{ 3353194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 3354194865Sjfv u32 i, led; 3355194865Sjfv 3356194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 3357194865Sjfv 3358194865Sjfv /* 3359194865Sjfv * If no link, then turn LED off by clearing the invert bit 3360194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 3361194865Sjfv */ 3362194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 3363194865Sjfv for (i = 0; i < 3; i++) { 3364194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 3365194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 3366194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 3367194865Sjfv continue; 3368194865Sjfv if (led & E1000_PHY_LED0_IVRT) 3369194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 3370194865Sjfv else 3371194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 3372194865Sjfv } 3373194865Sjfv } 3374194865Sjfv 3375194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3376194865Sjfv} 3377194865Sjfv 3378194865Sjfv/** 3379169240Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit 3380169589Sjfv * @hw: pointer to the HW structure 3381169240Sjfv * 3382169240Sjfv * Read the management control register for the config done bit for 3383169240Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 3384169240Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 3385169240Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 3386169240Sjfv * would not be able to be reset or change link. 3387169240Sjfv **/ 3388177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 3389169240Sjfv{ 3390173788Sjfv s32 ret_val = E1000_SUCCESS; 3391178523Sjfv u32 bank = 0; 3392173788Sjfv 3393194865Sjfv if (hw->mac.type >= e1000_pchlan) { 3394194865Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 3395194865Sjfv 3396200243Sjfv if (status & E1000_STATUS_PHYRA) 3397194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & 3398194865Sjfv ~E1000_STATUS_PHYRA); 3399200243Sjfv else 3400194865Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 3401194865Sjfv } 3402194865Sjfv 3403169240Sjfv e1000_get_cfg_done_generic(hw); 3404169240Sjfv 3405169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3406200243Sjfv if (hw->mac.type <= e1000_ich9lan) { 3407178523Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 3408185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 3409178523Sjfv e1000_phy_init_script_igp3(hw); 3410178523Sjfv } 3411178523Sjfv } else { 3412178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 3413185353Sjfv /* Maybe we should do a basic PHY config */ 3414178523Sjfv DEBUGOUT("EEPROM not present\n"); 3415178523Sjfv ret_val = -E1000_ERR_CONFIG; 3416178523Sjfv } 3417169240Sjfv } 3418169240Sjfv 3419173788Sjfv return ret_val; 3420169240Sjfv} 3421169240Sjfv 3422169240Sjfv/** 3423173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 3424173788Sjfv * @hw: pointer to the HW structure 3425173788Sjfv * 3426173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 3427173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 3428173788Sjfv **/ 3429177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 3430173788Sjfv{ 3431173788Sjfv /* If the management interface is not enabled, then power down */ 3432185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 3433185353Sjfv hw->phy.ops.check_reset_block(hw))) 3434173788Sjfv e1000_power_down_phy_copper(hw); 3435173788Sjfv 3436173788Sjfv return; 3437173788Sjfv} 3438173788Sjfv 3439173788Sjfv/** 3440169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 3441169589Sjfv * @hw: pointer to the HW structure 3442169240Sjfv * 3443169240Sjfv * Clears hardware counters specific to the silicon family and calls 3444169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 3445169240Sjfv **/ 3446177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 3447169240Sjfv{ 3448194865Sjfv u16 phy_data; 3449194865Sjfv 3450169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 3451169240Sjfv 3452169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 3453169240Sjfv 3454185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 3455185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 3456185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 3457185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 3458185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 3459185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 3460169240Sjfv 3461185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 3462185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 3463185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 3464169240Sjfv 3465185353Sjfv E1000_READ_REG(hw, E1000_IAC); 3466185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 3467194865Sjfv 3468194865Sjfv /* Clear PHY statistics registers */ 3469194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 3470194865Sjfv (hw->phy.type == e1000_phy_82577)) { 3471194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3472194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3473194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3474194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3475194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3476194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3477194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3478194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3479194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3480194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3481194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3482194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3483194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3484194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3485194865Sjfv } 3486169240Sjfv} 3487169240Sjfv 3488