e1000_ich8lan.c revision 194865
1177867Sjfv/****************************************************************************** 2169240Sjfv 3190872Sjfv Copyright (c) 2001-2009, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 194865 2009-06-24 17:41:29Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82562G 10/100 Network Connection 37185353Sjfv * 82562G-2 10/100 Network Connection 38185353Sjfv * 82562GT 10/100 Network Connection 39185353Sjfv * 82562GT-2 10/100 Network Connection 40185353Sjfv * 82562V 10/100 Network Connection 41185353Sjfv * 82562V-2 10/100 Network Connection 42185353Sjfv * 82566DC-2 Gigabit Network Connection 43185353Sjfv * 82566DC Gigabit Network Connection 44185353Sjfv * 82566DM-2 Gigabit Network Connection 45185353Sjfv * 82566DM Gigabit Network Connection 46185353Sjfv * 82566MC Gigabit Network Connection 47185353Sjfv * 82566MM Gigabit Network Connection 48185353Sjfv * 82567LM Gigabit Network Connection 49185353Sjfv * 82567LF Gigabit Network Connection 50185353Sjfv * 82567V Gigabit Network Connection 51185353Sjfv * 82567LM-2 Gigabit Network Connection 52185353Sjfv * 82567LF-2 Gigabit Network Connection 53185353Sjfv * 82567V-2 Gigabit Network Connection 54185353Sjfv * 82567LF-3 Gigabit Network Connection 55185353Sjfv * 82567LM-3 Gigabit Network Connection 56185353Sjfv * 82567LM-4 Gigabit Network Connection 57194865Sjfv * 82577LM Gigabit Network Connection 58194865Sjfv * 82577LC Gigabit Network Connection 59194865Sjfv * 82578DM Gigabit Network Connection 60194865Sjfv * 82578DC Gigabit Network Connection 61169240Sjfv */ 62169240Sjfv 63169589Sjfv#include "e1000_api.h" 64169240Sjfv 65177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 66194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); 67177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 68177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 69177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 71177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 72177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 73177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 74177867Sjfvstatic s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 75177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 76173788Sjfv bool active); 77177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 78173788Sjfv bool active); 79177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 80173788Sjfv u16 words, u16 *data); 81177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 82173788Sjfv u16 words, u16 *data); 83177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 84177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 85177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 86173788Sjfv u16 *data); 87194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 88177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 89177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 90177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 91177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 92177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 93177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 94173788Sjfv u16 *speed, u16 *duplex); 95177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 96177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 97177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 98194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 99194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 100194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 101194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 102177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 103177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 104173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 105173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 106173788Sjfvstatic s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 107173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 108173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 109178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 110185353Sjfv u32 offset, u8 *data); 111173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 112185353Sjfv u8 size, u16 *data); 113177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 114173788Sjfv u32 offset, u16 *data); 115173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 116173788Sjfv u32 offset, u8 byte); 117177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 118173788Sjfv u32 offset, u8 data); 119173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 120173788Sjfv u8 size, u16 data); 121177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 122177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 123169240Sjfv 124169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 125169240Sjfv/* Offset 04h HSFSTS */ 126169240Sjfvunion ich8_hws_flash_status { 127169240Sjfv struct ich8_hsfsts { 128169240Sjfv u16 flcdone :1; /* bit 0 Flash Cycle Done */ 129169240Sjfv u16 flcerr :1; /* bit 1 Flash Cycle Error */ 130169240Sjfv u16 dael :1; /* bit 2 Direct Access error Log */ 131169240Sjfv u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 132169240Sjfv u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 133169240Sjfv u16 reserved1 :2; /* bit 13:6 Reserved */ 134169240Sjfv u16 reserved2 :6; /* bit 13:6 Reserved */ 135169240Sjfv u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 136169240Sjfv u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 137169240Sjfv } hsf_status; 138169240Sjfv u16 regval; 139169240Sjfv}; 140169240Sjfv 141169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 142169240Sjfv/* Offset 06h FLCTL */ 143169240Sjfvunion ich8_hws_flash_ctrl { 144169240Sjfv struct ich8_hsflctl { 145169240Sjfv u16 flcgo :1; /* 0 Flash Cycle Go */ 146169240Sjfv u16 flcycle :2; /* 2:1 Flash Cycle */ 147169240Sjfv u16 reserved :5; /* 7:3 Reserved */ 148169240Sjfv u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 149169240Sjfv u16 flockdn :6; /* 15:10 Reserved */ 150169240Sjfv } hsf_ctrl; 151169240Sjfv u16 regval; 152169240Sjfv}; 153169240Sjfv 154169240Sjfv/* ICH Flash Region Access Permissions */ 155169240Sjfvunion ich8_hws_flash_regacc { 156169240Sjfv struct ich8_flracc { 157169240Sjfv u32 grra :8; /* 0:7 GbE region Read Access */ 158169240Sjfv u32 grwa :8; /* 8:15 GbE region Write Access */ 159169240Sjfv u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 160169240Sjfv u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 161169240Sjfv } hsf_flregacc; 162169240Sjfv u16 regval; 163169240Sjfv}; 164169240Sjfv 165169240Sjfv/** 166194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 167194865Sjfv * @hw: pointer to the HW structure 168194865Sjfv * 169194865Sjfv * Initialize family-specific PHY parameters and function pointers. 170194865Sjfv **/ 171194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 172194865Sjfv{ 173194865Sjfv struct e1000_phy_info *phy = &hw->phy; 174194865Sjfv s32 ret_val = E1000_SUCCESS; 175194865Sjfv 176194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 177194865Sjfv 178194865Sjfv phy->addr = 1; 179194865Sjfv phy->reset_delay_us = 100; 180194865Sjfv 181194865Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 182194865Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 183194865Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 184194865Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 185194865Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 186194865Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 187194865Sjfv phy->ops.get_info = e1000_get_phy_info_ich8lan; 188194865Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 189194865Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 190194865Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 191194865Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 192194865Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 193194865Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 194194865Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 195194865Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 196194865Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 197194865Sjfv 198194865Sjfv phy->id = e1000_phy_unknown; 199194865Sjfv e1000_get_phy_id(hw); 200194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 201194865Sjfv 202194865Sjfv if (phy->type == e1000_phy_82577) { 203194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 204194865Sjfv phy->ops.force_speed_duplex = 205194865Sjfv e1000_phy_force_speed_duplex_82577; 206194865Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 207194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 208194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 209194865Sjfv } 210194865Sjfv 211194865Sjfv return ret_val; 212194865Sjfv} 213194865Sjfv 214194865Sjfv/** 215169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 216169589Sjfv * @hw: pointer to the HW structure 217169240Sjfv * 218169240Sjfv * Initialize family-specific PHY parameters and function pointers. 219169240Sjfv **/ 220177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 221169240Sjfv{ 222169240Sjfv struct e1000_phy_info *phy = &hw->phy; 223169240Sjfv s32 ret_val = E1000_SUCCESS; 224169589Sjfv u16 i = 0; 225169240Sjfv 226169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 227169240Sjfv 228177867Sjfv phy->addr = 1; 229177867Sjfv phy->reset_delay_us = 100; 230169240Sjfv 231177867Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 232194865Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 233177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 234194865Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 235177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 236177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 237177867Sjfv phy->ops.get_info = e1000_get_phy_info_ich8lan; 238177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 239177867Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 240177867Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 241177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 242177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 243177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 244177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 245177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 246169240Sjfv 247176667Sjfv /* 248176667Sjfv * We may need to do this twice - once for IGP and if that fails, 249176667Sjfv * we'll set BM func pointers and try again 250176667Sjfv */ 251176667Sjfv ret_val = e1000_determine_phy_address(hw); 252176667Sjfv if (ret_val) { 253177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 254177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 255176667Sjfv ret_val = e1000_determine_phy_address(hw); 256176667Sjfv if (ret_val) { 257190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 258176667Sjfv goto out; 259176667Sjfv } 260176667Sjfv } 261169240Sjfv 262169589Sjfv phy->id = 0; 263169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 264169589Sjfv (i++ < 100)) { 265169589Sjfv msec_delay(1); 266169589Sjfv ret_val = e1000_get_phy_id(hw); 267169589Sjfv if (ret_val) 268169589Sjfv goto out; 269169589Sjfv } 270169589Sjfv 271169240Sjfv /* Verify phy id */ 272169240Sjfv switch (phy->id) { 273169240Sjfv case IGP03E1000_E_PHY_ID: 274169240Sjfv phy->type = e1000_phy_igp_3; 275169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 276169240Sjfv break; 277169240Sjfv case IFE_E_PHY_ID: 278169240Sjfv case IFE_PLUS_E_PHY_ID: 279169240Sjfv case IFE_C_E_PHY_ID: 280169240Sjfv phy->type = e1000_phy_ife; 281169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 282169240Sjfv break; 283176667Sjfv case BME1000_E_PHY_ID: 284176667Sjfv phy->type = e1000_phy_bm; 285176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 286177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 287177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 288177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 289176667Sjfv break; 290169240Sjfv default: 291169240Sjfv ret_val = -E1000_ERR_PHY; 292169240Sjfv goto out; 293169240Sjfv } 294169240Sjfv 295169240Sjfvout: 296169240Sjfv return ret_val; 297169240Sjfv} 298169240Sjfv 299169240Sjfv/** 300169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 301169589Sjfv * @hw: pointer to the HW structure 302169240Sjfv * 303169240Sjfv * Initialize family-specific NVM parameters and function 304169240Sjfv * pointers. 305169240Sjfv **/ 306177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 307169240Sjfv{ 308169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 309185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 310194865Sjfv union ich8_hws_flash_status hsfsts; 311169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 312173788Sjfv s32 ret_val = E1000_SUCCESS; 313169240Sjfv u16 i; 314169240Sjfv 315169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 316169240Sjfv 317173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 318169240Sjfv if (!hw->flash_address) { 319169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 320169240Sjfv ret_val = -E1000_ERR_CONFIG; 321169240Sjfv goto out; 322169240Sjfv } 323169240Sjfv 324185353Sjfv nvm->type = e1000_nvm_flash_sw; 325169240Sjfv 326169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 327169240Sjfv 328173788Sjfv /* 329173788Sjfv * sector_X_addr is a "sector"-aligned address (4096 bytes) 330169240Sjfv * Add 1 to sector_end_addr since this sector is included in 331173788Sjfv * the overall size. 332173788Sjfv */ 333169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 334169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 335169240Sjfv 336169240Sjfv /* flash_base_addr is byte-aligned */ 337185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 338169240Sjfv 339173788Sjfv /* 340173788Sjfv * find total size of the NVM, then cut in half since the total 341173788Sjfv * size represents two separate NVM banks. 342173788Sjfv */ 343185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 344169240Sjfv << FLASH_SECTOR_ADDR_SHIFT; 345185353Sjfv nvm->flash_bank_size /= 2; 346169240Sjfv /* Adjust to word count */ 347185353Sjfv nvm->flash_bank_size /= sizeof(u16); 348169240Sjfv 349194865Sjfv /* 350194865Sjfv * Make sure the flash bank size does not overwrite the 4k 351194865Sjfv * sector ranges. We may have 64k allotted to us but we only care 352194865Sjfv * about the first 2 4k sectors. Therefore, if we have anything less 353194865Sjfv * than 64k set in the HSFSTS register, we will reduce the bank size 354194865Sjfv * down to 4k and let the rest remain unused. If berasesz == 3, then 355194865Sjfv * we are working in 64k mode. Otherwise we are not. 356194865Sjfv */ 357194865Sjfv if (nvm->flash_bank_size > E1000_SHADOW_RAM_WORDS) { 358194865Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 359194865Sjfv if (hsfsts.hsf_status.berasesz != 3) 360194865Sjfv nvm->flash_bank_size = E1000_SHADOW_RAM_WORDS; 361194865Sjfv } 362194865Sjfv 363185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 364169240Sjfv 365169240Sjfv /* Clear shadow ram */ 366169240Sjfv for (i = 0; i < nvm->word_size; i++) { 367169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 368169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 369169240Sjfv } 370169240Sjfv 371169240Sjfv /* Function Pointers */ 372177867Sjfv nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 373177867Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 374177867Sjfv nvm->ops.release = e1000_release_swflag_ich8lan; 375177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 376177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 377177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 378177867Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 379169240Sjfv 380169240Sjfvout: 381169240Sjfv return ret_val; 382169240Sjfv} 383169240Sjfv 384169240Sjfv/** 385169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 386169589Sjfv * @hw: pointer to the HW structure 387169240Sjfv * 388169240Sjfv * Initialize family-specific MAC parameters and function 389169240Sjfv * pointers. 390169240Sjfv **/ 391177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 392169240Sjfv{ 393169240Sjfv struct e1000_mac_info *mac = &hw->mac; 394190872Sjfv u16 pci_cfg; 395169240Sjfv 396169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 397169240Sjfv 398169240Sjfv /* Set media type function pointer */ 399173788Sjfv hw->phy.media_type = e1000_media_type_copper; 400169240Sjfv 401169240Sjfv /* Set mta register count */ 402169240Sjfv mac->mta_reg_count = 32; 403169240Sjfv /* Set rar entry count */ 404169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 405169240Sjfv if (mac->type == e1000_ich8lan) 406169240Sjfv mac->rar_entry_count--; 407169240Sjfv /* Set if part includes ASF firmware */ 408169240Sjfv mac->asf_firmware_present = TRUE; 409169240Sjfv /* Set if manageability features are enabled. */ 410169240Sjfv mac->arc_subsystem_valid = TRUE; 411169240Sjfv 412169240Sjfv /* Function pointers */ 413169240Sjfv 414169240Sjfv /* bus type/speed/width */ 415177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 416185353Sjfv /* function id */ 417185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 418169240Sjfv /* reset */ 419177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 420169240Sjfv /* hw initialization */ 421177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 422169240Sjfv /* link setup */ 423177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 424169240Sjfv /* physical interface setup */ 425177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 426169240Sjfv /* check for link */ 427177867Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 428169240Sjfv /* check management mode */ 429177867Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 430169240Sjfv /* link info */ 431177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 432169240Sjfv /* multicast address update */ 433177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 434169240Sjfv /* setting MTA */ 435177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 436169240Sjfv /* clear hardware counters */ 437177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 438169240Sjfv 439190872Sjfv /* LED operations */ 440190872Sjfv switch (mac->type) { 441190872Sjfv case e1000_ich8lan: 442190872Sjfv case e1000_ich9lan: 443190872Sjfv case e1000_ich10lan: 444190872Sjfv /* ID LED init */ 445190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 446190872Sjfv /* blink LED */ 447190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 448190872Sjfv /* setup LED */ 449190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 450190872Sjfv /* cleanup LED */ 451190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 452190872Sjfv /* turn on/off LED */ 453190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 454190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 455190872Sjfv break; 456194865Sjfv case e1000_pchlan: 457194865Sjfv /* save PCH revision_id */ 458194865Sjfv e1000_read_pci_cfg(hw, 0x2, &pci_cfg); 459194865Sjfv hw->revision_id = (u8)(pci_cfg &= 0x000F); 460194865Sjfv /* ID LED init */ 461194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 462194865Sjfv /* setup LED */ 463194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 464194865Sjfv /* cleanup LED */ 465194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 466194865Sjfv /* turn on/off LED */ 467194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 468194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 469194865Sjfv break; 470190872Sjfv default: 471190872Sjfv break; 472190872Sjfv } 473190872Sjfv 474169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 475169240Sjfv if (mac->type == e1000_ich8lan) 476169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 477169240Sjfv 478169240Sjfv 479185353Sjfv return E1000_SUCCESS; 480169240Sjfv} 481169240Sjfv 482169240Sjfv/** 483169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 484169589Sjfv * @hw: pointer to the HW structure 485169240Sjfv * 486169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 487169240Sjfv **/ 488173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 489169240Sjfv{ 490169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 491169240Sjfv 492177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 493177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 494194865Sjfv switch (hw->mac.type) { 495194865Sjfv case e1000_ich8lan: 496194865Sjfv case e1000_ich9lan: 497194865Sjfv case e1000_ich10lan: 498194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 499194865Sjfv break; 500194865Sjfv case e1000_pchlan: 501194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 502194865Sjfv break; 503194865Sjfv default: 504194865Sjfv break; 505194865Sjfv } 506169240Sjfv} 507169240Sjfv 508169240Sjfv/** 509169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 510169589Sjfv * @hw: pointer to the HW structure 511169240Sjfv * 512169240Sjfv * Acquires the software control flag for performing NVM and PHY 513169240Sjfv * operations. This is a function pointer entry point only called by 514169240Sjfv * read/write routines for the PHY and NVM parts. 515169240Sjfv **/ 516177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 517169240Sjfv{ 518169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 519169240Sjfv s32 ret_val = E1000_SUCCESS; 520169240Sjfv 521169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 522169240Sjfv 523169240Sjfv while (timeout) { 524169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 525169240Sjfv 526194865Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) { 527194865Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 528194865Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 529194865Sjfv 530194865Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 531194865Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 532194865Sjfv break; 533194865Sjfv } 534169240Sjfv msec_delay_irq(1); 535169240Sjfv timeout--; 536169240Sjfv } 537169240Sjfv 538169240Sjfv if (!timeout) { 539194865Sjfv DEBUGOUT("SW/FW/HW has locked the resource for too long.\n"); 540173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 541173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 542169240Sjfv ret_val = -E1000_ERR_CONFIG; 543169240Sjfv goto out; 544169240Sjfv } 545169240Sjfv 546169240Sjfvout: 547169240Sjfv return ret_val; 548169240Sjfv} 549169240Sjfv 550169240Sjfv/** 551169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 552169589Sjfv * @hw: pointer to the HW structure 553169240Sjfv * 554169240Sjfv * Releases the software control flag for performing NVM and PHY operations. 555169240Sjfv * This is a function pointer entry point only called by read/write 556169240Sjfv * routines for the PHY and NVM parts. 557169240Sjfv **/ 558177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 559169240Sjfv{ 560169240Sjfv u32 extcnf_ctrl; 561169240Sjfv 562169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 563169240Sjfv 564169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 565169240Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 566169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 567169240Sjfv 568169240Sjfv return; 569169240Sjfv} 570169240Sjfv 571169240Sjfv/** 572169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 573169589Sjfv * @hw: pointer to the HW structure 574169240Sjfv * 575169240Sjfv * This checks if the adapter has manageability enabled. 576169240Sjfv * This is a function pointer entry point only called by read/write 577169240Sjfv * routines for the PHY and NVM parts. 578169240Sjfv **/ 579177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 580169240Sjfv{ 581169240Sjfv u32 fwsm; 582169240Sjfv 583169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 584169240Sjfv 585169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 586169240Sjfv 587185353Sjfv return (fwsm & E1000_FWSM_MODE_MASK) == 588185353Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 589169240Sjfv} 590169240Sjfv 591169240Sjfv/** 592169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 593169589Sjfv * @hw: pointer to the HW structure 594169240Sjfv * 595169240Sjfv * Checks if firmware is blocking the reset of the PHY. 596169240Sjfv * This is a function pointer entry point only called by 597169240Sjfv * reset routines. 598169240Sjfv **/ 599177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 600169240Sjfv{ 601169240Sjfv u32 fwsm; 602169240Sjfv 603169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 604169240Sjfv 605169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 606169240Sjfv 607169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 608169240Sjfv : E1000_BLK_PHY_RESET; 609169240Sjfv} 610169240Sjfv 611169240Sjfv/** 612194865Sjfv * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx 613169589Sjfv * @hw: pointer to the HW structure 614169240Sjfv **/ 615194865Sjfvs32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 616169240Sjfv{ 617194865Sjfv if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2)) 618194865Sjfv return E1000_SUCCESS; 619169240Sjfv 620194865Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444); 621194865Sjfv} 622169240Sjfv 623194865Sjfv/** 624194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 625194865Sjfv * done after every PHY reset. 626194865Sjfv **/ 627194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 628194865Sjfv{ 629194865Sjfv s32 ret_val = E1000_SUCCESS; 630194865Sjfv 631194865Sjfv if (hw->mac.type != e1000_pchlan) 632194865Sjfv return ret_val; 633194865Sjfv 634194865Sjfv /* Hanksville M Phy init for IEEE. */ 635194865Sjfv if ((hw->revision_id == 2) && 636194865Sjfv (hw->phy.type == e1000_phy_82577) && 637194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 638194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8823); 639194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0018); 640194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8824); 641194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0016); 642194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8825); 643194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x001A); 644194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888C); 645194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 646194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888D); 647194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 648194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888E); 649194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 650194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8827); 651194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 652194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8835); 653194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 654194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8834); 655194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 656194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8833); 657194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0002); 658169240Sjfv } 659169240Sjfv 660194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 661194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 662194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 663194865Sjfv /* Disable generation of early preamble */ 664194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 665194865Sjfv if (ret_val) 666194865Sjfv return ret_val; 667169240Sjfv 668194865Sjfv /* Preamble tuning for SSC */ 669194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 670194865Sjfv if (ret_val) 671194865Sjfv return ret_val; 672194865Sjfv } 673169240Sjfv 674194865Sjfv if (hw->phy.type == e1000_phy_82578) { 675194865Sjfv if (hw->revision_id < 3) { 676194865Sjfv /* PHY config */ 677194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 678194865Sjfv 0x66C0); 679194865Sjfv if (ret_val) 680194865Sjfv return ret_val; 681169240Sjfv 682194865Sjfv /* PHY config */ 683194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 684194865Sjfv 0xFFFF); 685194865Sjfv if (ret_val) 686194865Sjfv return ret_val; 687194865Sjfv } 688169240Sjfv 689194865Sjfv /* 690194865Sjfv * Return registers to default by doing a soft reset then 691194865Sjfv * writing 0x3140 to the control register. 692194865Sjfv */ 693194865Sjfv if (hw->phy.revision < 2) { 694194865Sjfv e1000_phy_sw_reset_generic(hw); 695194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 696194865Sjfv 0x3140); 697194865Sjfv } 698194865Sjfv } 699169240Sjfv 700194865Sjfv if ((hw->revision_id == 2) && 701194865Sjfv (hw->phy.type == e1000_phy_82577) && 702194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 703194865Sjfv /* 704194865Sjfv * Workaround for OEM (GbE) not operating after reset - 705194865Sjfv * restart AN (twice) 706194865Sjfv */ 707194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 708194865Sjfv if (ret_val) 709194865Sjfv return ret_val; 710194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 711194865Sjfv if (ret_val) 712194865Sjfv return ret_val; 713194865Sjfv } 714194865Sjfv 715194865Sjfv /* Select page 0 */ 716194865Sjfv ret_val = hw->phy.ops.acquire(hw); 717169240Sjfv if (ret_val) 718194865Sjfv return ret_val; 719194865Sjfv hw->phy.addr = 1; 720194865Sjfv e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 721194865Sjfv hw->phy.ops.release(hw); 722169240Sjfv 723194865Sjfv return ret_val; 724194865Sjfv} 725169240Sjfv 726194865Sjfv/** 727194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 728194865Sjfv * @hw: pointer to the HW structure 729194865Sjfv * 730194865Sjfv * Check the appropriate indication the MAC has finished configuring the 731194865Sjfv * PHY after a software reset. 732194865Sjfv **/ 733194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 734194865Sjfv{ 735194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 736169240Sjfv 737194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 738169240Sjfv 739194865Sjfv /* Wait for basic configuration completes before proceeding */ 740194865Sjfv do { 741194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 742194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 743194865Sjfv usec_delay(100); 744194865Sjfv } while ((!data) && --loop); 745169240Sjfv 746194865Sjfv /* 747194865Sjfv * If basic configuration is incomplete before the above loop 748194865Sjfv * count reaches 0, loading the configuration from NVM will 749194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 750194865Sjfv */ 751194865Sjfv if (loop == 0) 752194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 753169240Sjfv 754194865Sjfv /* Clear the Init Done bit for the next init event */ 755194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 756194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 757194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 758169240Sjfv} 759169240Sjfv 760169240Sjfv/** 761169240Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 762169589Sjfv * @hw: pointer to the HW structure 763169240Sjfv * 764169240Sjfv * Resets the PHY 765169240Sjfv * This is a function pointer entry point called by drivers 766169240Sjfv * or other shared routines. 767169240Sjfv **/ 768177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 769169240Sjfv{ 770169240Sjfv struct e1000_phy_info *phy = &hw->phy; 771169240Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 772169240Sjfv s32 ret_val; 773169240Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 774169240Sjfv 775169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 776169240Sjfv 777169240Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 778169240Sjfv if (ret_val) 779169240Sjfv goto out; 780169240Sjfv 781194865Sjfv /* Allow time for h/w to get to a quiescent state after reset */ 782194865Sjfv msec_delay(10); 783194865Sjfv 784194865Sjfv if (hw->mac.type == e1000_pchlan) { 785194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 786194865Sjfv if (ret_val) 787194865Sjfv goto out; 788194865Sjfv } 789194865Sjfv 790173788Sjfv /* 791173788Sjfv * Initialize the PHY from the NVM on ICH platforms. This 792169240Sjfv * is needed due to an issue where the NVM configuration is 793169240Sjfv * not properly autoloaded after power transitions. 794169240Sjfv * Therefore, after each PHY reset, we will load the 795169240Sjfv * configuration data out of the NVM manually. 796169240Sjfv */ 797169240Sjfv if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 798169240Sjfv /* Check if SW needs configure the PHY */ 799169240Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 800169240Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 801169240Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 802169240Sjfv else 803169240Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 804169240Sjfv 805169240Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 806169240Sjfv if (!(data & sw_cfg_mask)) 807169240Sjfv goto out; 808169240Sjfv 809194865Sjfv /* Wait for basic configuration completes before proceeding */ 810194865Sjfv e1000_lan_init_done_ich8lan(hw); 811169240Sjfv 812173788Sjfv /* 813173788Sjfv * Make sure HW does not configure LCD from PHY 814173788Sjfv * extended configuration before SW configuration 815173788Sjfv */ 816169240Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 817169240Sjfv if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 818169240Sjfv goto out; 819169240Sjfv 820169240Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 821169240Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 822169240Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 823169240Sjfv if (!cnf_size) 824169240Sjfv goto out; 825169240Sjfv 826169240Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 827169240Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 828169240Sjfv 829185353Sjfv /* Configure LCD from extended configuration region. */ 830169240Sjfv 831169240Sjfv /* cnf_base_addr is in DWORD */ 832169240Sjfv word_addr = (u16)(cnf_base_addr << 1); 833169240Sjfv 834169240Sjfv for (i = 0; i < cnf_size; i++) { 835185353Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 836185353Sjfv ®_data); 837169240Sjfv if (ret_val) 838169240Sjfv goto out; 839169240Sjfv 840185353Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 841185353Sjfv 1, ®_addr); 842169240Sjfv if (ret_val) 843169240Sjfv goto out; 844169240Sjfv 845169240Sjfv /* Save off the PHY page for future writes. */ 846169240Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 847169240Sjfv phy_page = reg_data; 848169240Sjfv continue; 849169240Sjfv } 850169240Sjfv 851169240Sjfv reg_addr |= phy_page; 852169240Sjfv 853185353Sjfv ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data); 854169240Sjfv if (ret_val) 855169240Sjfv goto out; 856169240Sjfv } 857169240Sjfv } 858169240Sjfv 859169240Sjfvout: 860169240Sjfv return ret_val; 861169240Sjfv} 862169240Sjfv 863169240Sjfv/** 864169240Sjfv * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 865169589Sjfv * @hw: pointer to the HW structure 866169240Sjfv * 867169240Sjfv * Wrapper for calling the get_phy_info routines for the appropriate phy type. 868169240Sjfv **/ 869177867Sjfvstatic s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 870169240Sjfv{ 871169240Sjfv s32 ret_val = -E1000_ERR_PHY_TYPE; 872169240Sjfv 873169240Sjfv DEBUGFUNC("e1000_get_phy_info_ich8lan"); 874169240Sjfv 875169240Sjfv switch (hw->phy.type) { 876169240Sjfv case e1000_phy_ife: 877169240Sjfv ret_val = e1000_get_phy_info_ife_ich8lan(hw); 878169240Sjfv break; 879169240Sjfv case e1000_phy_igp_3: 880176667Sjfv case e1000_phy_bm: 881194865Sjfv case e1000_phy_82578: 882194865Sjfv case e1000_phy_82577: 883169240Sjfv ret_val = e1000_get_phy_info_igp(hw); 884169240Sjfv break; 885169240Sjfv default: 886169240Sjfv break; 887169240Sjfv } 888169240Sjfv 889169240Sjfv return ret_val; 890169240Sjfv} 891169240Sjfv 892169240Sjfv/** 893169240Sjfv * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 894169589Sjfv * @hw: pointer to the HW structure 895169240Sjfv * 896169240Sjfv * Populates "phy" structure with various feature states. 897169240Sjfv * This function is only called by other family-specific 898169240Sjfv * routines. 899169240Sjfv **/ 900173788Sjfvstatic s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 901169240Sjfv{ 902169240Sjfv struct e1000_phy_info *phy = &hw->phy; 903169240Sjfv s32 ret_val; 904169240Sjfv u16 data; 905173788Sjfv bool link; 906169240Sjfv 907169240Sjfv DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 908169240Sjfv 909169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 910169240Sjfv if (ret_val) 911169240Sjfv goto out; 912169240Sjfv 913169240Sjfv if (!link) { 914169240Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 915169240Sjfv ret_val = -E1000_ERR_CONFIG; 916169240Sjfv goto out; 917169240Sjfv } 918169240Sjfv 919177867Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 920169240Sjfv if (ret_val) 921169240Sjfv goto out; 922169240Sjfv phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 923169240Sjfv ? FALSE : TRUE; 924169240Sjfv 925169240Sjfv if (phy->polarity_correction) { 926194865Sjfv ret_val = e1000_check_polarity_ife(hw); 927169240Sjfv if (ret_val) 928169240Sjfv goto out; 929169240Sjfv } else { 930169240Sjfv /* Polarity is forced */ 931169240Sjfv phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 932169240Sjfv ? e1000_rev_polarity_reversed 933169240Sjfv : e1000_rev_polarity_normal; 934169240Sjfv } 935169240Sjfv 936177867Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 937169240Sjfv if (ret_val) 938169240Sjfv goto out; 939169240Sjfv 940169240Sjfv phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 941169240Sjfv 942169240Sjfv /* The following parameters are undefined for 10/100 operation. */ 943169240Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 944169240Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 945169240Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 946169240Sjfv 947169240Sjfvout: 948169240Sjfv return ret_val; 949169240Sjfv} 950169240Sjfv 951169240Sjfv/** 952169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 953169589Sjfv * @hw: pointer to the HW structure 954169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 955169240Sjfv * 956169240Sjfv * Sets the LPLU D0 state according to the active flag. When 957169240Sjfv * activating LPLU this function also disables smart speed 958169240Sjfv * and vice versa. LPLU will not be activated unless the 959169240Sjfv * device autonegotiation advertisement meets standards of 960169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 961169240Sjfv * This is a function pointer entry point only called by 962169240Sjfv * PHY setup routines. 963169240Sjfv **/ 964185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 965169240Sjfv{ 966169240Sjfv struct e1000_phy_info *phy = &hw->phy; 967169240Sjfv u32 phy_ctrl; 968169240Sjfv s32 ret_val = E1000_SUCCESS; 969169240Sjfv u16 data; 970169240Sjfv 971169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 972169240Sjfv 973173788Sjfv if (phy->type == e1000_phy_ife) 974169240Sjfv goto out; 975169240Sjfv 976169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 977169240Sjfv 978169240Sjfv if (active) { 979169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 980169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 981169240Sjfv 982194865Sjfv if (phy->type != e1000_phy_igp_3) 983194865Sjfv goto out; 984194865Sjfv 985173788Sjfv /* 986173788Sjfv * Call gig speed drop workaround on LPLU before accessing 987173788Sjfv * any PHY registers 988173788Sjfv */ 989194865Sjfv if (hw->mac.type == e1000_ich8lan) 990169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 991169240Sjfv 992169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 993177867Sjfv ret_val = phy->ops.read_reg(hw, 994169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 995169240Sjfv &data); 996169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 997177867Sjfv ret_val = phy->ops.write_reg(hw, 998169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 999169240Sjfv data); 1000169240Sjfv if (ret_val) 1001169240Sjfv goto out; 1002169240Sjfv } else { 1003169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 1004169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1005169240Sjfv 1006194865Sjfv if (phy->type != e1000_phy_igp_3) 1007194865Sjfv goto out; 1008194865Sjfv 1009173788Sjfv /* 1010173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1011169240Sjfv * during Dx states where the power conservation is most 1012169240Sjfv * important. During driver activity we should enable 1013173788Sjfv * SmartSpeed, so performance is maintained. 1014173788Sjfv */ 1015169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1016177867Sjfv ret_val = phy->ops.read_reg(hw, 1017169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1018169240Sjfv &data); 1019169240Sjfv if (ret_val) 1020169240Sjfv goto out; 1021169240Sjfv 1022169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1023177867Sjfv ret_val = phy->ops.write_reg(hw, 1024169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1025169240Sjfv data); 1026169240Sjfv if (ret_val) 1027169240Sjfv goto out; 1028169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1029177867Sjfv ret_val = phy->ops.read_reg(hw, 1030169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1031169240Sjfv &data); 1032169240Sjfv if (ret_val) 1033169240Sjfv goto out; 1034169240Sjfv 1035169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1036177867Sjfv ret_val = phy->ops.write_reg(hw, 1037169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1038169240Sjfv data); 1039169240Sjfv if (ret_val) 1040169240Sjfv goto out; 1041169240Sjfv } 1042169240Sjfv } 1043169240Sjfv 1044169240Sjfvout: 1045169240Sjfv return ret_val; 1046169240Sjfv} 1047169240Sjfv 1048169240Sjfv/** 1049169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 1050169589Sjfv * @hw: pointer to the HW structure 1051169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1052169240Sjfv * 1053169240Sjfv * Sets the LPLU D3 state according to the active flag. When 1054169240Sjfv * activating LPLU this function also disables smart speed 1055169240Sjfv * and vice versa. LPLU will not be activated unless the 1056169240Sjfv * device autonegotiation advertisement meets standards of 1057169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 1058169240Sjfv * This is a function pointer entry point only called by 1059169240Sjfv * PHY setup routines. 1060169240Sjfv **/ 1061185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1062169240Sjfv{ 1063169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1064169240Sjfv u32 phy_ctrl; 1065169240Sjfv s32 ret_val = E1000_SUCCESS; 1066169240Sjfv u16 data; 1067169240Sjfv 1068169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 1069169240Sjfv 1070169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 1071169240Sjfv 1072169240Sjfv if (!active) { 1073169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 1074169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1075194865Sjfv 1076194865Sjfv if (phy->type != e1000_phy_igp_3) 1077194865Sjfv goto out; 1078194865Sjfv 1079173788Sjfv /* 1080173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1081169240Sjfv * during Dx states where the power conservation is most 1082169240Sjfv * important. During driver activity we should enable 1083173788Sjfv * SmartSpeed, so performance is maintained. 1084173788Sjfv */ 1085169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1086177867Sjfv ret_val = phy->ops.read_reg(hw, 1087169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1088169240Sjfv &data); 1089169240Sjfv if (ret_val) 1090169240Sjfv goto out; 1091169240Sjfv 1092169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1093177867Sjfv ret_val = phy->ops.write_reg(hw, 1094169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1095169240Sjfv data); 1096169240Sjfv if (ret_val) 1097169240Sjfv goto out; 1098169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1099177867Sjfv ret_val = phy->ops.read_reg(hw, 1100169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1101169240Sjfv &data); 1102169240Sjfv if (ret_val) 1103169240Sjfv goto out; 1104169240Sjfv 1105169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1106177867Sjfv ret_val = phy->ops.write_reg(hw, 1107169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1108169240Sjfv data); 1109169240Sjfv if (ret_val) 1110169240Sjfv goto out; 1111169240Sjfv } 1112169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1113169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1114169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1115169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 1116169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1117169240Sjfv 1118194865Sjfv if (phy->type != e1000_phy_igp_3) 1119194865Sjfv goto out; 1120194865Sjfv 1121173788Sjfv /* 1122173788Sjfv * Call gig speed drop workaround on LPLU before accessing 1123173788Sjfv * any PHY registers 1124173788Sjfv */ 1125194865Sjfv if (hw->mac.type == e1000_ich8lan) 1126169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 1127169240Sjfv 1128169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1129177867Sjfv ret_val = phy->ops.read_reg(hw, 1130169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1131169240Sjfv &data); 1132169240Sjfv if (ret_val) 1133169240Sjfv goto out; 1134169240Sjfv 1135169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1136177867Sjfv ret_val = phy->ops.write_reg(hw, 1137169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1138169240Sjfv data); 1139169240Sjfv } 1140169240Sjfv 1141169240Sjfvout: 1142169240Sjfv return ret_val; 1143169240Sjfv} 1144169240Sjfv 1145169240Sjfv/** 1146173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1147173788Sjfv * @hw: pointer to the HW structure 1148173788Sjfv * @bank: pointer to the variable that returns the active bank 1149173788Sjfv * 1150173788Sjfv * Reads signature byte from the NVM using the flash access registers. 1151190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 1152173788Sjfv **/ 1153177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1154173788Sjfv{ 1155190872Sjfv u32 eecd; 1156178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1157178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1158178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1159190872Sjfv u8 sig_byte = 0; 1160190872Sjfv s32 ret_val = E1000_SUCCESS; 1161178523Sjfv 1162190872Sjfv switch (hw->mac.type) { 1163190872Sjfv case e1000_ich8lan: 1164190872Sjfv case e1000_ich9lan: 1165190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 1166190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 1167190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 1168190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 1169190872Sjfv *bank = 1; 1170190872Sjfv else 1171190872Sjfv *bank = 0; 1172190872Sjfv 1173190872Sjfv goto out; 1174190872Sjfv } 1175190872Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - " 1176190872Sjfv "reading flash signature\n"); 1177190872Sjfv /* fall-thru */ 1178190872Sjfv default: 1179190872Sjfv /* set bank to 0 in case flash read fails */ 1180190872Sjfv *bank = 0; 1181190872Sjfv 1182190872Sjfv /* Check bank 0 */ 1183190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 1184190872Sjfv &sig_byte); 1185190872Sjfv if (ret_val) 1186190872Sjfv goto out; 1187190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1188190872Sjfv E1000_ICH_NVM_SIG_VALUE) { 1189178523Sjfv *bank = 0; 1190190872Sjfv goto out; 1191190872Sjfv } 1192185353Sjfv 1193190872Sjfv /* Check bank 1 */ 1194190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 1195190872Sjfv bank1_offset, 1196190872Sjfv &sig_byte); 1197190872Sjfv if (ret_val) 1198190872Sjfv goto out; 1199190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1200190872Sjfv E1000_ICH_NVM_SIG_VALUE) { 1201190872Sjfv *bank = 1; 1202190872Sjfv goto out; 1203178523Sjfv } 1204190872Sjfv 1205190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 1206190872Sjfv ret_val = -E1000_ERR_NVM; 1207190872Sjfv break; 1208178523Sjfv } 1209190872Sjfvout: 1210173788Sjfv return ret_val; 1211173788Sjfv} 1212173788Sjfv 1213173788Sjfv/** 1214169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1215169589Sjfv * @hw: pointer to the HW structure 1216169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 1217169589Sjfv * @words: Size of data to read in words 1218169589Sjfv * @data: Pointer to the word(s) to read at offset. 1219169240Sjfv * 1220169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 1221169240Sjfv **/ 1222177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1223173788Sjfv u16 *data) 1224169240Sjfv{ 1225169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1226185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1227169240Sjfv u32 act_offset; 1228169240Sjfv s32 ret_val = E1000_SUCCESS; 1229173788Sjfv u32 bank = 0; 1230169240Sjfv u16 i, word; 1231169240Sjfv 1232169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 1233169240Sjfv 1234169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1235169240Sjfv (words == 0)) { 1236169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1237169240Sjfv ret_val = -E1000_ERR_NVM; 1238169240Sjfv goto out; 1239169240Sjfv } 1240169240Sjfv 1241177867Sjfv ret_val = nvm->ops.acquire(hw); 1242169240Sjfv if (ret_val) 1243169240Sjfv goto out; 1244169240Sjfv 1245173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1246173788Sjfv if (ret_val != E1000_SUCCESS) 1247190872Sjfv goto release; 1248173788Sjfv 1249173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 1250169240Sjfv act_offset += offset; 1251169240Sjfv 1252169240Sjfv for (i = 0; i < words; i++) { 1253173788Sjfv if ((dev_spec->shadow_ram) && 1254173788Sjfv (dev_spec->shadow_ram[offset+i].modified)) { 1255169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 1256169240Sjfv } else { 1257169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 1258169240Sjfv act_offset + i, 1259169240Sjfv &word); 1260169240Sjfv if (ret_val) 1261169240Sjfv break; 1262169240Sjfv data[i] = word; 1263169240Sjfv } 1264169240Sjfv } 1265169240Sjfv 1266190872Sjfvrelease: 1267177867Sjfv nvm->ops.release(hw); 1268169240Sjfv 1269169240Sjfvout: 1270190872Sjfv if (ret_val) 1271190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 1272190872Sjfv 1273169240Sjfv return ret_val; 1274169240Sjfv} 1275169240Sjfv 1276169240Sjfv/** 1277169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 1278169589Sjfv * @hw: pointer to the HW structure 1279169240Sjfv * 1280169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 1281169240Sjfv * can be started. 1282169240Sjfv **/ 1283173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1284169240Sjfv{ 1285169240Sjfv union ich8_hws_flash_status hsfsts; 1286169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1287169240Sjfv s32 i = 0; 1288169240Sjfv 1289169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1290169240Sjfv 1291169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1292169240Sjfv 1293169240Sjfv /* Check if the flash descriptor is valid */ 1294169240Sjfv if (hsfsts.hsf_status.fldesvalid == 0) { 1295169240Sjfv DEBUGOUT("Flash descriptor invalid. " 1296169240Sjfv "SW Sequencing must be used."); 1297169240Sjfv goto out; 1298169240Sjfv } 1299169240Sjfv 1300169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 1301169240Sjfv hsfsts.hsf_status.flcerr = 1; 1302169240Sjfv hsfsts.hsf_status.dael = 1; 1303169240Sjfv 1304169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1305169240Sjfv 1306173788Sjfv /* 1307173788Sjfv * Either we should have a hardware SPI cycle in progress 1308169240Sjfv * bit to check against, in order to start a new cycle or 1309169240Sjfv * FDONE bit should be changed in the hardware so that it 1310176667Sjfv * is 1 after hardware reset, which can then be used as an 1311169240Sjfv * indication whether a cycle is in progress or has been 1312169240Sjfv * completed. 1313169240Sjfv */ 1314169240Sjfv 1315169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1316173788Sjfv /* 1317173788Sjfv * There is no cycle running at present, 1318173788Sjfv * so we can start a cycle. 1319173788Sjfv * Begin by setting Flash Cycle Done. 1320173788Sjfv */ 1321169240Sjfv hsfsts.hsf_status.flcdone = 1; 1322169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1323169240Sjfv ret_val = E1000_SUCCESS; 1324169240Sjfv } else { 1325173788Sjfv /* 1326173788Sjfv * Otherwise poll for sometime so the current 1327173788Sjfv * cycle has a chance to end before giving up. 1328173788Sjfv */ 1329169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1330169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1331169240Sjfv ICH_FLASH_HSFSTS); 1332169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1333169240Sjfv ret_val = E1000_SUCCESS; 1334169240Sjfv break; 1335169240Sjfv } 1336169240Sjfv usec_delay(1); 1337169240Sjfv } 1338169240Sjfv if (ret_val == E1000_SUCCESS) { 1339173788Sjfv /* 1340173788Sjfv * Successful in waiting for previous cycle to timeout, 1341173788Sjfv * now set the Flash Cycle Done. 1342173788Sjfv */ 1343169240Sjfv hsfsts.hsf_status.flcdone = 1; 1344185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 1345169240Sjfv hsfsts.regval); 1346169240Sjfv } else { 1347169240Sjfv DEBUGOUT("Flash controller busy, cannot get access"); 1348169240Sjfv } 1349169240Sjfv } 1350169240Sjfv 1351169240Sjfvout: 1352169240Sjfv return ret_val; 1353169240Sjfv} 1354169240Sjfv 1355169240Sjfv/** 1356169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1357169589Sjfv * @hw: pointer to the HW structure 1358169589Sjfv * @timeout: maximum time to wait for completion 1359169240Sjfv * 1360169240Sjfv * This function starts a flash cycle and waits for its completion. 1361169240Sjfv **/ 1362173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1363169240Sjfv{ 1364169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1365169240Sjfv union ich8_hws_flash_status hsfsts; 1366169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1367169240Sjfv u32 i = 0; 1368169240Sjfv 1369169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1370169240Sjfv 1371169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1372169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1373169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 1374169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1375169240Sjfv 1376169240Sjfv /* wait till FDONE bit is set to 1 */ 1377169240Sjfv do { 1378169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1379169240Sjfv if (hsfsts.hsf_status.flcdone == 1) 1380169240Sjfv break; 1381169240Sjfv usec_delay(1); 1382169240Sjfv } while (i++ < timeout); 1383169240Sjfv 1384169240Sjfv if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1385169240Sjfv ret_val = E1000_SUCCESS; 1386169240Sjfv 1387169240Sjfv return ret_val; 1388169240Sjfv} 1389169240Sjfv 1390169240Sjfv/** 1391169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 1392169589Sjfv * @hw: pointer to the HW structure 1393169589Sjfv * @offset: offset to data location 1394169589Sjfv * @data: pointer to the location for storing the data 1395169240Sjfv * 1396169240Sjfv * Reads the flash word at offset into data. Offset is converted 1397169240Sjfv * to bytes before read. 1398169240Sjfv **/ 1399177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1400173788Sjfv u16 *data) 1401169240Sjfv{ 1402169240Sjfv s32 ret_val; 1403169240Sjfv 1404169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1405169240Sjfv 1406173788Sjfv if (!data) { 1407169240Sjfv ret_val = -E1000_ERR_NVM; 1408169240Sjfv goto out; 1409169240Sjfv } 1410169240Sjfv 1411169240Sjfv /* Must convert offset into bytes. */ 1412169240Sjfv offset <<= 1; 1413169240Sjfv 1414169240Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1415169240Sjfv 1416169240Sjfvout: 1417169240Sjfv return ret_val; 1418169240Sjfv} 1419169240Sjfv 1420169240Sjfv/** 1421178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 1422178523Sjfv * @hw: pointer to the HW structure 1423178523Sjfv * @offset: The offset of the byte to read. 1424178523Sjfv * @data: Pointer to a byte to store the value read. 1425178523Sjfv * 1426178523Sjfv * Reads a single byte from the NVM using the flash access registers. 1427178523Sjfv **/ 1428178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1429185353Sjfv u8 *data) 1430178523Sjfv{ 1431178523Sjfv s32 ret_val = E1000_SUCCESS; 1432178523Sjfv u16 word = 0; 1433178523Sjfv 1434178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1435178523Sjfv if (ret_val) 1436178523Sjfv goto out; 1437178523Sjfv 1438178523Sjfv *data = (u8)word; 1439178523Sjfv 1440178523Sjfvout: 1441178523Sjfv return ret_val; 1442178523Sjfv} 1443178523Sjfv 1444178523Sjfv/** 1445169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1446169589Sjfv * @hw: pointer to the HW structure 1447169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 1448169589Sjfv * @size: Size of data to read, 1=byte 2=word 1449169589Sjfv * @data: Pointer to the word to store the value read. 1450169240Sjfv * 1451169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 1452169240Sjfv **/ 1453173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1454185353Sjfv u8 size, u16 *data) 1455169240Sjfv{ 1456169240Sjfv union ich8_hws_flash_status hsfsts; 1457169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1458169240Sjfv u32 flash_linear_addr; 1459169240Sjfv u32 flash_data = 0; 1460169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1461169240Sjfv u8 count = 0; 1462169240Sjfv 1463169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1464169240Sjfv 1465173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1466169240Sjfv goto out; 1467169240Sjfv 1468169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1469169240Sjfv hw->nvm.flash_base_addr; 1470169240Sjfv 1471169240Sjfv do { 1472169240Sjfv usec_delay(1); 1473169240Sjfv /* Steps */ 1474169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1475169240Sjfv if (ret_val != E1000_SUCCESS) 1476169240Sjfv break; 1477169240Sjfv 1478169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1479169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1480169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 1481169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1482169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1483169240Sjfv 1484169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1485169240Sjfv 1486169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1487169240Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 1488169240Sjfv 1489173788Sjfv /* 1490173788Sjfv * Check if FCERR is set to 1, if set to 1, clear it 1491169240Sjfv * and try the whole sequence a few more times, else 1492169240Sjfv * read in (shift in) the Flash Data0, the order is 1493173788Sjfv * least significant byte first msb to lsb 1494173788Sjfv */ 1495169240Sjfv if (ret_val == E1000_SUCCESS) { 1496169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1497185353Sjfv if (size == 1) 1498169240Sjfv *data = (u8)(flash_data & 0x000000FF); 1499185353Sjfv else if (size == 2) 1500169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 1501169240Sjfv break; 1502169240Sjfv } else { 1503173788Sjfv /* 1504173788Sjfv * If we've gotten here, then things are probably 1505169240Sjfv * completely hosed, but if the error condition is 1506169240Sjfv * detected, it won't hurt to give it another try... 1507169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1508169240Sjfv */ 1509169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1510169240Sjfv ICH_FLASH_HSFSTS); 1511169240Sjfv if (hsfsts.hsf_status.flcerr == 1) { 1512169240Sjfv /* Repeat for some time before giving up. */ 1513169240Sjfv continue; 1514169240Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 1515169240Sjfv DEBUGOUT("Timeout error - flash cycle " 1516169240Sjfv "did not complete."); 1517169240Sjfv break; 1518169240Sjfv } 1519169240Sjfv } 1520169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1521169240Sjfv 1522169240Sjfvout: 1523169240Sjfv return ret_val; 1524169240Sjfv} 1525169240Sjfv 1526169240Sjfv/** 1527169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1528169589Sjfv * @hw: pointer to the HW structure 1529169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 1530169589Sjfv * @words: Size of data to write in words 1531169589Sjfv * @data: Pointer to the word(s) to write at offset. 1532169240Sjfv * 1533169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 1534169240Sjfv **/ 1535177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1536173788Sjfv u16 *data) 1537169240Sjfv{ 1538169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1539185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1540169240Sjfv s32 ret_val = E1000_SUCCESS; 1541169240Sjfv u16 i; 1542169240Sjfv 1543169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 1544169240Sjfv 1545169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1546169240Sjfv (words == 0)) { 1547169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1548169240Sjfv ret_val = -E1000_ERR_NVM; 1549169240Sjfv goto out; 1550169240Sjfv } 1551169240Sjfv 1552177867Sjfv ret_val = nvm->ops.acquire(hw); 1553169240Sjfv if (ret_val) 1554169240Sjfv goto out; 1555169240Sjfv 1556169240Sjfv for (i = 0; i < words; i++) { 1557169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 1558169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 1559169240Sjfv } 1560169240Sjfv 1561177867Sjfv nvm->ops.release(hw); 1562169240Sjfv 1563169240Sjfvout: 1564169240Sjfv return ret_val; 1565169240Sjfv} 1566169240Sjfv 1567169240Sjfv/** 1568169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1569169589Sjfv * @hw: pointer to the HW structure 1570169240Sjfv * 1571169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 1572169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 1573169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 1574169240Sjfv * checking for the modified bit and writing only the pending changes. 1575176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 1576169240Sjfv * future writes. 1577169240Sjfv **/ 1578177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1579169240Sjfv{ 1580169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1581185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1582173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1583169240Sjfv s32 ret_val; 1584169240Sjfv u16 data; 1585169240Sjfv 1586169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1587169240Sjfv 1588169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 1589169240Sjfv if (ret_val) 1590169240Sjfv goto out; 1591169240Sjfv 1592169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 1593169240Sjfv goto out; 1594169240Sjfv 1595177867Sjfv ret_val = nvm->ops.acquire(hw); 1596169240Sjfv if (ret_val) 1597169240Sjfv goto out; 1598169240Sjfv 1599173788Sjfv /* 1600173788Sjfv * We're writing to the opposite bank so if we're on bank 1, 1601169240Sjfv * write to bank 0 etc. We also need to erase the segment that 1602173788Sjfv * is going to be written 1603173788Sjfv */ 1604173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1605190872Sjfv if (ret_val != E1000_SUCCESS) { 1606190872Sjfv nvm->ops.release(hw); 1607173788Sjfv goto out; 1608190872Sjfv } 1609173788Sjfv 1610173788Sjfv if (bank == 0) { 1611169240Sjfv new_bank_offset = nvm->flash_bank_size; 1612169240Sjfv old_bank_offset = 0; 1613190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 1614190872Sjfv if (ret_val) { 1615190872Sjfv nvm->ops.release(hw); 1616190872Sjfv goto out; 1617190872Sjfv } 1618169240Sjfv } else { 1619169240Sjfv old_bank_offset = nvm->flash_bank_size; 1620169240Sjfv new_bank_offset = 0; 1621190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 1622190872Sjfv if (ret_val) { 1623190872Sjfv nvm->ops.release(hw); 1624190872Sjfv goto out; 1625190872Sjfv } 1626169240Sjfv } 1627169240Sjfv 1628169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1629173788Sjfv /* 1630173788Sjfv * Determine whether to write the value stored 1631169240Sjfv * in the other NVM bank or a modified value stored 1632173788Sjfv * in the shadow RAM 1633173788Sjfv */ 1634173788Sjfv if (dev_spec->shadow_ram[i].modified) { 1635169240Sjfv data = dev_spec->shadow_ram[i].value; 1636169240Sjfv } else { 1637190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 1638190872Sjfv old_bank_offset, 1639190872Sjfv &data); 1640190872Sjfv if (ret_val) 1641190872Sjfv break; 1642169240Sjfv } 1643169240Sjfv 1644173788Sjfv /* 1645173788Sjfv * If the word is 0x13, then make sure the signature bits 1646169240Sjfv * (15:14) are 11b until the commit has completed. 1647169240Sjfv * This will allow us to write 10b which indicates the 1648169240Sjfv * signature is valid. We want to do this after the write 1649169240Sjfv * has completed so that we don't mark the segment valid 1650173788Sjfv * while the write is still in progress 1651173788Sjfv */ 1652169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 1653169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 1654169240Sjfv 1655169240Sjfv /* Convert offset to bytes. */ 1656169240Sjfv act_offset = (i + new_bank_offset) << 1; 1657169240Sjfv 1658169240Sjfv usec_delay(100); 1659169240Sjfv /* Write the bytes to the new bank. */ 1660169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1661169240Sjfv act_offset, 1662169240Sjfv (u8)data); 1663169240Sjfv if (ret_val) 1664169240Sjfv break; 1665169240Sjfv 1666169240Sjfv usec_delay(100); 1667169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1668169240Sjfv act_offset + 1, 1669169240Sjfv (u8)(data >> 8)); 1670169240Sjfv if (ret_val) 1671169240Sjfv break; 1672169240Sjfv } 1673169240Sjfv 1674173788Sjfv /* 1675173788Sjfv * Don't bother writing the segment valid bits if sector 1676173788Sjfv * programming failed. 1677173788Sjfv */ 1678169240Sjfv if (ret_val) { 1679169240Sjfv DEBUGOUT("Flash commit failed.\n"); 1680177867Sjfv nvm->ops.release(hw); 1681169240Sjfv goto out; 1682169240Sjfv } 1683169240Sjfv 1684173788Sjfv /* 1685173788Sjfv * Finally validate the new segment by setting bit 15:14 1686169240Sjfv * to 10b in word 0x13 , this can be done without an 1687169240Sjfv * erase as well since these bits are 11 to start with 1688173788Sjfv * and we need to change bit 14 to 0b 1689173788Sjfv */ 1690169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1691190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1692190872Sjfv if (ret_val) { 1693190872Sjfv nvm->ops.release(hw); 1694190872Sjfv goto out; 1695190872Sjfv } 1696169240Sjfv data &= 0xBFFF; 1697169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1698169240Sjfv act_offset * 2 + 1, 1699169240Sjfv (u8)(data >> 8)); 1700169240Sjfv if (ret_val) { 1701177867Sjfv nvm->ops.release(hw); 1702169240Sjfv goto out; 1703169240Sjfv } 1704169240Sjfv 1705173788Sjfv /* 1706173788Sjfv * And invalidate the previously valid segment by setting 1707169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 1708169240Sjfv * done without an erase because flash erase sets all bits 1709173788Sjfv * to 1's. We can write 1's to 0's without an erase 1710173788Sjfv */ 1711169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1712169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1713169240Sjfv if (ret_val) { 1714177867Sjfv nvm->ops.release(hw); 1715169240Sjfv goto out; 1716169240Sjfv } 1717169240Sjfv 1718169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 1719169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1720169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 1721169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 1722169240Sjfv } 1723169240Sjfv 1724177867Sjfv nvm->ops.release(hw); 1725169240Sjfv 1726173788Sjfv /* 1727173788Sjfv * Reload the EEPROM, or else modifications will not appear 1728169240Sjfv * until after the next adapter reset. 1729169240Sjfv */ 1730177867Sjfv nvm->ops.reload(hw); 1731169240Sjfv msec_delay(10); 1732169240Sjfv 1733169240Sjfvout: 1734190872Sjfv if (ret_val) 1735190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 1736190872Sjfv 1737169240Sjfv return ret_val; 1738169240Sjfv} 1739169240Sjfv 1740169240Sjfv/** 1741169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1742169589Sjfv * @hw: pointer to the HW structure 1743169240Sjfv * 1744169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1745185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 1746185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 1747169240Sjfv **/ 1748177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1749169240Sjfv{ 1750169240Sjfv s32 ret_val = E1000_SUCCESS; 1751169240Sjfv u16 data; 1752169240Sjfv 1753169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1754169240Sjfv 1755173788Sjfv /* 1756173788Sjfv * Read 0x19 and check bit 6. If this bit is 0, the checksum 1757169240Sjfv * needs to be fixed. This bit is an indication that the NVM 1758169240Sjfv * was prepared by OEM software and did not calculate the 1759169240Sjfv * checksum...a likely scenario. 1760169240Sjfv */ 1761177867Sjfv ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1762169240Sjfv if (ret_val) 1763169240Sjfv goto out; 1764169240Sjfv 1765169240Sjfv if ((data & 0x40) == 0) { 1766169240Sjfv data |= 0x40; 1767177867Sjfv ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1768169240Sjfv if (ret_val) 1769169240Sjfv goto out; 1770177867Sjfv ret_val = hw->nvm.ops.update(hw); 1771169240Sjfv if (ret_val) 1772169240Sjfv goto out; 1773169240Sjfv } 1774169240Sjfv 1775169240Sjfv ret_val = e1000_validate_nvm_checksum_generic(hw); 1776169240Sjfv 1777169240Sjfvout: 1778169240Sjfv return ret_val; 1779169240Sjfv} 1780169240Sjfv 1781169240Sjfv/** 1782169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1783169589Sjfv * @hw: pointer to the HW structure 1784169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 1785169589Sjfv * @size: Size of data to read, 1=byte 2=word 1786169589Sjfv * @data: The byte(s) to write to the NVM. 1787169240Sjfv * 1788169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 1789169240Sjfv **/ 1790173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1791173788Sjfv u8 size, u16 data) 1792169240Sjfv{ 1793169240Sjfv union ich8_hws_flash_status hsfsts; 1794169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1795169240Sjfv u32 flash_linear_addr; 1796169240Sjfv u32 flash_data = 0; 1797169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1798169240Sjfv u8 count = 0; 1799169240Sjfv 1800169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 1801169240Sjfv 1802169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 1803169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 1804169240Sjfv goto out; 1805169240Sjfv 1806169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1807169240Sjfv hw->nvm.flash_base_addr; 1808169240Sjfv 1809169240Sjfv do { 1810169240Sjfv usec_delay(1); 1811169240Sjfv /* Steps */ 1812169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1813169240Sjfv if (ret_val != E1000_SUCCESS) 1814169240Sjfv break; 1815169240Sjfv 1816169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1817169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1818185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 1819169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1820169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1821169240Sjfv 1822169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1823169240Sjfv 1824169240Sjfv if (size == 1) 1825169240Sjfv flash_data = (u32)data & 0x00FF; 1826169240Sjfv else 1827169240Sjfv flash_data = (u32)data; 1828169240Sjfv 1829169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1830169240Sjfv 1831173788Sjfv /* 1832173788Sjfv * check if FCERR is set to 1 , if set to 1, clear it 1833173788Sjfv * and try the whole sequence a few more times else done 1834173788Sjfv */ 1835169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1836169240Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1837185353Sjfv if (ret_val == E1000_SUCCESS) 1838169240Sjfv break; 1839185353Sjfv 1840185353Sjfv /* 1841185353Sjfv * If we're here, then things are most likely 1842185353Sjfv * completely hosed, but if the error condition 1843185353Sjfv * is detected, it won't hurt to give it another 1844185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1845185353Sjfv */ 1846185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1847185353Sjfv if (hsfsts.hsf_status.flcerr == 1) { 1848185353Sjfv /* Repeat for some time before giving up. */ 1849185353Sjfv continue; 1850185353Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 1851185353Sjfv DEBUGOUT("Timeout error - flash cycle " 1852185353Sjfv "did not complete."); 1853185353Sjfv break; 1854169240Sjfv } 1855169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1856169240Sjfv 1857169240Sjfvout: 1858169240Sjfv return ret_val; 1859169240Sjfv} 1860169240Sjfv 1861169240Sjfv/** 1862169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1863169589Sjfv * @hw: pointer to the HW structure 1864169589Sjfv * @offset: The index of the byte to read. 1865169589Sjfv * @data: The byte to write to the NVM. 1866169240Sjfv * 1867169240Sjfv * Writes a single byte to the NVM using the flash access registers. 1868169240Sjfv **/ 1869177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1870173788Sjfv u8 data) 1871169240Sjfv{ 1872169240Sjfv u16 word = (u16)data; 1873169240Sjfv 1874169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1875169240Sjfv 1876169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1877169240Sjfv} 1878169240Sjfv 1879169240Sjfv/** 1880169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1881169589Sjfv * @hw: pointer to the HW structure 1882169589Sjfv * @offset: The offset of the byte to write. 1883169589Sjfv * @byte: The byte to write to the NVM. 1884169240Sjfv * 1885169240Sjfv * Writes a single byte to the NVM using the flash access registers. 1886169240Sjfv * Goes through a retry algorithm before giving up. 1887169240Sjfv **/ 1888176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1889176667Sjfv u32 offset, u8 byte) 1890169240Sjfv{ 1891169240Sjfv s32 ret_val; 1892169240Sjfv u16 program_retries; 1893169240Sjfv 1894169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1895169240Sjfv 1896169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1897173788Sjfv if (ret_val == E1000_SUCCESS) 1898169240Sjfv goto out; 1899169240Sjfv 1900169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 1901169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1902169240Sjfv usec_delay(100); 1903169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1904169240Sjfv if (ret_val == E1000_SUCCESS) 1905169240Sjfv break; 1906169240Sjfv } 1907169240Sjfv if (program_retries == 100) { 1908169240Sjfv ret_val = -E1000_ERR_NVM; 1909169240Sjfv goto out; 1910169240Sjfv } 1911169240Sjfv 1912169240Sjfvout: 1913169240Sjfv return ret_val; 1914169240Sjfv} 1915169240Sjfv 1916169240Sjfv/** 1917169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1918169589Sjfv * @hw: pointer to the HW structure 1919169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 1920169240Sjfv * 1921169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1922169240Sjfv * bank N is 4096 * N + flash_reg_addr. 1923169240Sjfv **/ 1924177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1925169240Sjfv{ 1926169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1927169240Sjfv union ich8_hws_flash_status hsfsts; 1928169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1929169240Sjfv u32 flash_linear_addr; 1930173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 1931173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 1932185353Sjfv s32 ret_val = E1000_SUCCESS; 1933185353Sjfv s32 count = 0; 1934185353Sjfv s32 j, iteration, sector_size; 1935169240Sjfv 1936169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1937169240Sjfv 1938169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1939169240Sjfv 1940173788Sjfv /* 1941173788Sjfv * Determine HW Sector size: Read BERASE bits of hw flash status 1942173788Sjfv * register 1943173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 1944169240Sjfv * consecutive sectors. The start index for the nth Hw sector 1945169240Sjfv * can be calculated as = bank * 4096 + n * 256 1946169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1947169240Sjfv * The start index for the nth Hw sector can be calculated 1948169240Sjfv * as = bank * 4096 1949169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1950169240Sjfv * (ich9 only, otherwise error condition) 1951169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1952169240Sjfv */ 1953169240Sjfv switch (hsfsts.hsf_status.berasesz) { 1954169240Sjfv case 0: 1955169240Sjfv /* Hw sector size 256 */ 1956169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 1957169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1958169240Sjfv break; 1959169240Sjfv case 1: 1960169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 1961194865Sjfv iteration = 1; 1962169240Sjfv break; 1963169240Sjfv case 2: 1964169240Sjfv if (hw->mac.type == e1000_ich9lan) { 1965169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 1966169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1967169240Sjfv } else { 1968169240Sjfv ret_val = -E1000_ERR_NVM; 1969169240Sjfv goto out; 1970169240Sjfv } 1971169240Sjfv break; 1972169240Sjfv case 3: 1973169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 1974194865Sjfv iteration = 1; 1975169240Sjfv break; 1976169240Sjfv default: 1977169240Sjfv ret_val = -E1000_ERR_NVM; 1978169240Sjfv goto out; 1979169240Sjfv } 1980169240Sjfv 1981169240Sjfv /* Start with the base address, then add the sector offset. */ 1982169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 1983169240Sjfv flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1984169240Sjfv 1985169240Sjfv for (j = 0; j < iteration ; j++) { 1986169240Sjfv do { 1987169240Sjfv /* Steps */ 1988169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1989169240Sjfv if (ret_val) 1990169240Sjfv goto out; 1991169240Sjfv 1992173788Sjfv /* 1993173788Sjfv * Write a value 11 (block Erase) in Flash 1994173788Sjfv * Cycle field in hw flash control 1995173788Sjfv */ 1996169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1997169240Sjfv ICH_FLASH_HSFCTL); 1998169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1999185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 2000169240Sjfv hsflctl.regval); 2001169240Sjfv 2002173788Sjfv /* 2003173788Sjfv * Write the last 24 bits of an index within the 2004169240Sjfv * block into Flash Linear address field in Flash 2005169240Sjfv * Address. 2006169240Sjfv */ 2007169240Sjfv flash_linear_addr += (j * sector_size); 2008185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 2009169240Sjfv flash_linear_addr); 2010169240Sjfv 2011169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2012169240Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 2013185353Sjfv if (ret_val == E1000_SUCCESS) 2014169240Sjfv break; 2015185353Sjfv 2016185353Sjfv /* 2017185353Sjfv * Check if FCERR is set to 1. If 1, 2018185353Sjfv * clear it and try the whole sequence 2019185353Sjfv * a few more times else Done 2020185353Sjfv */ 2021185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2022185353Sjfv ICH_FLASH_HSFSTS); 2023185353Sjfv if (hsfsts.hsf_status.flcerr == 1) 2024185353Sjfv /* repeat for some time before giving up */ 2025185353Sjfv continue; 2026185353Sjfv else if (hsfsts.hsf_status.flcdone == 0) 2027185353Sjfv goto out; 2028169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 2029169240Sjfv } 2030169240Sjfv 2031169240Sjfvout: 2032169240Sjfv return ret_val; 2033169240Sjfv} 2034169240Sjfv 2035169240Sjfv/** 2036169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 2037169589Sjfv * @hw: pointer to the HW structure 2038169589Sjfv * @data: Pointer to the LED settings 2039169240Sjfv * 2040169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 2041169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 2042169240Sjfv * setting. 2043169240Sjfv **/ 2044177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 2045169240Sjfv{ 2046169240Sjfv s32 ret_val; 2047169240Sjfv 2048169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 2049169240Sjfv 2050177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 2051169240Sjfv if (ret_val) { 2052169240Sjfv DEBUGOUT("NVM Read Error\n"); 2053169240Sjfv goto out; 2054169240Sjfv } 2055169240Sjfv 2056169240Sjfv if (*data == ID_LED_RESERVED_0000 || 2057169240Sjfv *data == ID_LED_RESERVED_FFFF) 2058169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 2059169240Sjfv 2060169240Sjfvout: 2061169240Sjfv return ret_val; 2062169240Sjfv} 2063169240Sjfv 2064169240Sjfv/** 2065194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 2066194865Sjfv * @hw: pointer to the HW structure 2067194865Sjfv * 2068194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 2069194865Sjfv * the PHY LED configuration register. 2070194865Sjfv * 2071194865Sjfv * PCH also does not have an "always on" or "always off" mode which 2072194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 2073194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 2074194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 2075194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 2076194865Sjfv **/ 2077194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 2078194865Sjfv{ 2079194865Sjfv struct e1000_mac_info *mac = &hw->mac; 2080194865Sjfv s32 ret_val; 2081194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 2082194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 2083194865Sjfv u16 data, i, temp, shift; 2084194865Sjfv 2085194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 2086194865Sjfv 2087194865Sjfv /* Get default ID LED modes */ 2088194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 2089194865Sjfv if (ret_val) 2090194865Sjfv goto out; 2091194865Sjfv 2092194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 2093194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 2094194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 2095194865Sjfv 2096194865Sjfv for (i = 0; i < 4; i++) { 2097194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 2098194865Sjfv shift = (i * 5); 2099194865Sjfv switch (temp) { 2100194865Sjfv case ID_LED_ON1_DEF2: 2101194865Sjfv case ID_LED_ON1_ON2: 2102194865Sjfv case ID_LED_ON1_OFF2: 2103194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2104194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 2105194865Sjfv break; 2106194865Sjfv case ID_LED_OFF1_DEF2: 2107194865Sjfv case ID_LED_OFF1_ON2: 2108194865Sjfv case ID_LED_OFF1_OFF2: 2109194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2110194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 2111194865Sjfv break; 2112194865Sjfv default: 2113194865Sjfv /* Do nothing */ 2114194865Sjfv break; 2115194865Sjfv } 2116194865Sjfv switch (temp) { 2117194865Sjfv case ID_LED_DEF1_ON2: 2118194865Sjfv case ID_LED_ON1_ON2: 2119194865Sjfv case ID_LED_OFF1_ON2: 2120194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2121194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 2122194865Sjfv break; 2123194865Sjfv case ID_LED_DEF1_OFF2: 2124194865Sjfv case ID_LED_ON1_OFF2: 2125194865Sjfv case ID_LED_OFF1_OFF2: 2126194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2127194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 2128194865Sjfv break; 2129194865Sjfv default: 2130194865Sjfv /* Do nothing */ 2131194865Sjfv break; 2132194865Sjfv } 2133194865Sjfv } 2134194865Sjfv 2135194865Sjfvout: 2136194865Sjfv return ret_val; 2137194865Sjfv} 2138194865Sjfv 2139194865Sjfv/** 2140169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 2141169589Sjfv * @hw: pointer to the HW structure 2142169240Sjfv * 2143169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 2144169240Sjfv * register, so the the bus width is hard coded. 2145169240Sjfv **/ 2146177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 2147169240Sjfv{ 2148169240Sjfv struct e1000_bus_info *bus = &hw->bus; 2149169240Sjfv s32 ret_val; 2150169240Sjfv 2151169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 2152169240Sjfv 2153169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 2154169240Sjfv 2155173788Sjfv /* 2156173788Sjfv * ICH devices are "PCI Express"-ish. They have 2157169240Sjfv * a configuration space, but do not contain 2158169240Sjfv * PCI Express Capability registers, so bus width 2159169240Sjfv * must be hardcoded. 2160169240Sjfv */ 2161169240Sjfv if (bus->width == e1000_bus_width_unknown) 2162169240Sjfv bus->width = e1000_bus_width_pcie_x1; 2163169240Sjfv 2164169240Sjfv return ret_val; 2165169240Sjfv} 2166169240Sjfv 2167169240Sjfv/** 2168169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 2169169589Sjfv * @hw: pointer to the HW structure 2170169240Sjfv * 2171169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 2172169240Sjfv * MAC. 2173169240Sjfv **/ 2174177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 2175169240Sjfv{ 2176169240Sjfv u32 ctrl, icr, kab; 2177169240Sjfv s32 ret_val; 2178169240Sjfv 2179169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 2180169240Sjfv 2181173788Sjfv /* 2182173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 2183169240Sjfv * on the last TLP read/write transaction when MAC is reset. 2184169240Sjfv */ 2185169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 2186185353Sjfv if (ret_val) 2187169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2188169240Sjfv 2189169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 2190169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2191169240Sjfv 2192173788Sjfv /* 2193173788Sjfv * Disable the Transmit and Receive units. Then delay to allow 2194169240Sjfv * any pending transactions to complete before we hit the MAC 2195169240Sjfv * with the global reset. 2196169240Sjfv */ 2197169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 2198169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2199169240Sjfv E1000_WRITE_FLUSH(hw); 2200169240Sjfv 2201169240Sjfv msec_delay(10); 2202169240Sjfv 2203169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 2204169240Sjfv if (hw->mac.type == e1000_ich8lan) { 2205169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 2206169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 2207169240Sjfv /* Set Packet Buffer Size to 16k. */ 2208169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 2209169240Sjfv } 2210169240Sjfv 2211169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2212169240Sjfv 2213177867Sjfv if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 2214194865Sjfv /* Clear PHY Reset Asserted bit */ 2215194865Sjfv if (hw->mac.type >= e1000_pchlan) { 2216194865Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 2217194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & 2218194865Sjfv ~E1000_STATUS_PHYRA); 2219194865Sjfv } 2220194865Sjfv 2221173788Sjfv /* 2222173788Sjfv * PHY HW reset requires MAC CORE reset at the same 2223169240Sjfv * time to make sure the interface between MAC and the 2224169240Sjfv * external PHY is reset. 2225169240Sjfv */ 2226169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 2227169240Sjfv } 2228169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 2229185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 2230169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2231169240Sjfv msec_delay(20); 2232169240Sjfv 2233194865Sjfv if (!ret_val) 2234194865Sjfv e1000_release_swflag_ich8lan(hw); 2235194865Sjfv 2236194865Sjfv if (ctrl & E1000_CTRL_PHY_RST) 2237194865Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 2238194865Sjfv 2239194865Sjfv if (hw->mac.type >= e1000_ich10lan) { 2240194865Sjfv e1000_lan_init_done_ich8lan(hw); 2241194865Sjfv } else { 2242194865Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 2243194865Sjfv if (ret_val) { 2244194865Sjfv /* 2245194865Sjfv * When auto config read does not complete, do not 2246194865Sjfv * return with an error. This can happen in situations 2247194865Sjfv * where there is no eeprom and prevents getting link. 2248194865Sjfv */ 2249194865Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 2250194865Sjfv } 2251169240Sjfv } 2252169240Sjfv 2253169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2254169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 2255169240Sjfv 2256169240Sjfv kab = E1000_READ_REG(hw, E1000_KABGTXD); 2257169240Sjfv kab |= E1000_KABGTXD_BGSQLBIAS; 2258169240Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2259169240Sjfv 2260194865Sjfv if (hw->mac.type == e1000_pchlan) 2261194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2262194865Sjfv 2263169240Sjfv return ret_val; 2264169240Sjfv} 2265169240Sjfv 2266169240Sjfv/** 2267169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 2268169589Sjfv * @hw: pointer to the HW structure 2269169240Sjfv * 2270169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 2271169240Sjfv * - initialize hardware bits 2272169240Sjfv * - initialize LED identification 2273169240Sjfv * - setup receive address registers 2274169240Sjfv * - setup flow control 2275176667Sjfv * - setup transmit descriptors 2276169240Sjfv * - clear statistics 2277169240Sjfv **/ 2278177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2279169240Sjfv{ 2280169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2281169240Sjfv u32 ctrl_ext, txdctl, snoop; 2282169240Sjfv s32 ret_val; 2283169240Sjfv u16 i; 2284169240Sjfv 2285169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 2286169240Sjfv 2287169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 2288169240Sjfv 2289169240Sjfv /* Initialize identification LED */ 2290190872Sjfv ret_val = mac->ops.id_led_init(hw); 2291190872Sjfv if (ret_val) 2292190872Sjfv /* This is not fatal and we should not stop init due to this */ 2293169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 2294169240Sjfv 2295169240Sjfv /* Setup the receive address. */ 2296169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2297169240Sjfv 2298169240Sjfv /* Zero out the Multicast HASH table */ 2299169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 2300169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 2301169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2302169240Sjfv 2303194865Sjfv /* 2304194865Sjfv * The 82578 Rx buffer will stall if wakeup is enabled in host and 2305194865Sjfv * the ME. Reading the BM_WUC register will clear the host wakeup bit. 2306194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 2307194865Sjfv */ 2308194865Sjfv if (hw->phy.type == e1000_phy_82578) { 2309194865Sjfv hw->phy.ops.read_reg(hw, BM_WUC, &i); 2310194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 2311194865Sjfv if (ret_val) 2312194865Sjfv return ret_val; 2313194865Sjfv } 2314194865Sjfv 2315169240Sjfv /* Setup link and flow control */ 2316177867Sjfv ret_val = mac->ops.setup_link(hw); 2317169240Sjfv 2318169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 2319173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2320169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2321169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2322169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2323169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2324173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2325173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2326169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2327169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2328169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2329169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2330173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2331169240Sjfv 2332173788Sjfv /* 2333173788Sjfv * ICH8 has opposite polarity of no_snoop bits. 2334173788Sjfv * By default, we should use snoop behavior. 2335173788Sjfv */ 2336169240Sjfv if (mac->type == e1000_ich8lan) 2337169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 2338169240Sjfv else 2339169240Sjfv snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2340169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 2341169240Sjfv 2342169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2343169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2344169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2345169240Sjfv 2346173788Sjfv /* 2347173788Sjfv * Clear all of the statistics registers (clear on read). It is 2348169240Sjfv * important that we do this after we have tried to establish link 2349169240Sjfv * because the symbol error count will increment wildly if there 2350169240Sjfv * is no link. 2351169240Sjfv */ 2352169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 2353169240Sjfv 2354169240Sjfv return ret_val; 2355169240Sjfv} 2356169240Sjfv/** 2357169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2358169589Sjfv * @hw: pointer to the HW structure 2359169240Sjfv * 2360169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 2361169240Sjfv * hardware for transmit and receive. 2362169240Sjfv **/ 2363173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2364169240Sjfv{ 2365169240Sjfv u32 reg; 2366169240Sjfv 2367169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2368169240Sjfv 2369169240Sjfv /* Extended Device Control */ 2370169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2371169240Sjfv reg |= (1 << 22); 2372194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 2373194865Sjfv if (hw->mac.type >= e1000_pchlan) 2374194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 2375169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2376169240Sjfv 2377169240Sjfv /* Transmit Descriptor Control 0 */ 2378173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2379169240Sjfv reg |= (1 << 22); 2380173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2381169240Sjfv 2382169240Sjfv /* Transmit Descriptor Control 1 */ 2383173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2384169240Sjfv reg |= (1 << 22); 2385173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2386169240Sjfv 2387169240Sjfv /* Transmit Arbitration Control 0 */ 2388173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 2389169240Sjfv if (hw->mac.type == e1000_ich8lan) 2390169240Sjfv reg |= (1 << 28) | (1 << 29); 2391169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2392173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2393169240Sjfv 2394169240Sjfv /* Transmit Arbitration Control 1 */ 2395173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 2396169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2397169240Sjfv reg &= ~(1 << 28); 2398169240Sjfv else 2399169240Sjfv reg |= (1 << 28); 2400169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 2401173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2402169240Sjfv 2403169240Sjfv /* Device Status */ 2404169240Sjfv if (hw->mac.type == e1000_ich8lan) { 2405169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 2406169240Sjfv reg &= ~(1 << 31); 2407169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 2408169240Sjfv } 2409169240Sjfv 2410169240Sjfv return; 2411169240Sjfv} 2412169240Sjfv 2413169240Sjfv/** 2414169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 2415169589Sjfv * @hw: pointer to the HW structure 2416169240Sjfv * 2417169240Sjfv * Determines which flow control settings to use, then configures flow 2418169240Sjfv * control. Calls the appropriate media-specific link configuration 2419169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 2420169240Sjfv * should be established. Assumes the hardware has previously been reset 2421169240Sjfv * and the transmitter and receiver are not enabled. 2422169240Sjfv **/ 2423177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2424169240Sjfv{ 2425169240Sjfv s32 ret_val = E1000_SUCCESS; 2426169240Sjfv 2427169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 2428169240Sjfv 2429177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 2430169240Sjfv goto out; 2431169240Sjfv 2432173788Sjfv /* 2433173788Sjfv * ICH parts do not have a word in the NVM to determine 2434169240Sjfv * the default flow control setting, so we explicitly 2435169240Sjfv * set it to full. 2436169240Sjfv */ 2437185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 2438185353Sjfv hw->fc.requested_mode = e1000_fc_full; 2439169240Sjfv 2440185353Sjfv /* 2441185353Sjfv * Save off the requested flow control mode for use later. Depending 2442185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 2443185353Sjfv */ 2444185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 2445169240Sjfv 2446185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 2447190872Sjfv hw->fc.current_mode); 2448169240Sjfv 2449169240Sjfv /* Continue to configure the copper link. */ 2450177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 2451169240Sjfv if (ret_val) 2452169240Sjfv goto out; 2453169240Sjfv 2454173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2455194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 2456194865Sjfv (hw->phy.type == e1000_phy_82577)) { 2457194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 2458194865Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 2459194865Sjfv hw->fc.pause_time); 2460194865Sjfv if (ret_val) 2461194865Sjfv goto out; 2462194865Sjfv } 2463169240Sjfv 2464169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 2465169240Sjfv 2466169240Sjfvout: 2467169240Sjfv return ret_val; 2468169240Sjfv} 2469169240Sjfv 2470169240Sjfv/** 2471169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2472169589Sjfv * @hw: pointer to the HW structure 2473169240Sjfv * 2474169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 2475169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 2476169240Sjfv * configuring the copper link. 2477169240Sjfv **/ 2478177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2479169240Sjfv{ 2480169240Sjfv u32 ctrl; 2481169240Sjfv s32 ret_val; 2482169240Sjfv u16 reg_data; 2483169240Sjfv 2484169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2485169240Sjfv 2486169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2487169240Sjfv ctrl |= E1000_CTRL_SLU; 2488169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2489169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2490169240Sjfv 2491173788Sjfv /* 2492173788Sjfv * Set the mac to wait the maximum time between each iteration 2493169240Sjfv * and increase the max iterations when polling the phy; 2494173788Sjfv * this fixes erroneous timeouts at 10Mbps. 2495173788Sjfv */ 2496194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2497194865Sjfv E1000_KMRNCTRLSTA_TIMEOUTS, 2498181027Sjfv 0xFFFF); 2499169240Sjfv if (ret_val) 2500169240Sjfv goto out; 2501194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2502194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 2503181027Sjfv ®_data); 2504169240Sjfv if (ret_val) 2505169240Sjfv goto out; 2506169240Sjfv reg_data |= 0x3F; 2507194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2508194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 2509181027Sjfv reg_data); 2510169240Sjfv if (ret_val) 2511169240Sjfv goto out; 2512169240Sjfv 2513190872Sjfv switch (hw->phy.type) { 2514190872Sjfv case e1000_phy_igp_3: 2515169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 2516169240Sjfv if (ret_val) 2517169240Sjfv goto out; 2518190872Sjfv break; 2519190872Sjfv case e1000_phy_bm: 2520194865Sjfv case e1000_phy_82578: 2521176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 2522176667Sjfv if (ret_val) 2523176667Sjfv goto out; 2524190872Sjfv break; 2525194865Sjfv case e1000_phy_82577: 2526194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 2527194865Sjfv if (ret_val) 2528194865Sjfv goto out; 2529194865Sjfv break; 2530190872Sjfv case e1000_phy_ife: 2531177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2532177867Sjfv ®_data); 2533173788Sjfv if (ret_val) 2534173788Sjfv goto out; 2535173788Sjfv 2536173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 2537173788Sjfv 2538173788Sjfv switch (hw->phy.mdix) { 2539173788Sjfv case 1: 2540173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 2541173788Sjfv break; 2542173788Sjfv case 2: 2543173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 2544173788Sjfv break; 2545173788Sjfv case 0: 2546173788Sjfv default: 2547173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 2548173788Sjfv break; 2549173788Sjfv } 2550177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2551177867Sjfv reg_data); 2552173788Sjfv if (ret_val) 2553173788Sjfv goto out; 2554190872Sjfv break; 2555190872Sjfv default: 2556190872Sjfv break; 2557173788Sjfv } 2558169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 2559169240Sjfv 2560169240Sjfvout: 2561169240Sjfv return ret_val; 2562169240Sjfv} 2563169240Sjfv 2564169240Sjfv/** 2565169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2566169589Sjfv * @hw: pointer to the HW structure 2567169589Sjfv * @speed: pointer to store current link speed 2568169589Sjfv * @duplex: pointer to store the current link duplex 2569169240Sjfv * 2570176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 2571169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 2572169240Sjfv * gigabit speeds. 2573169240Sjfv **/ 2574177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2575173788Sjfv u16 *duplex) 2576169240Sjfv{ 2577169240Sjfv s32 ret_val; 2578169240Sjfv 2579169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2580169240Sjfv 2581169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2582169240Sjfv if (ret_val) 2583169240Sjfv goto out; 2584169240Sjfv 2585169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 2586169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 2587169240Sjfv (*speed == SPEED_1000)) { 2588169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2589169240Sjfv } 2590169240Sjfv 2591169240Sjfvout: 2592169240Sjfv return ret_val; 2593169240Sjfv} 2594169240Sjfv 2595169240Sjfv/** 2596169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2597169589Sjfv * @hw: pointer to the HW structure 2598169240Sjfv * 2599169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 2600169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 2601169240Sjfv * speed is gigabit- 2602169240Sjfv * 0) if workaround is optionally disabled do nothing 2603169240Sjfv * 1) wait 1ms for Kumeran link to come up 2604169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 2605169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 2606169240Sjfv * 4) reset the PHY 2607169240Sjfv * 5) repeat up to 10 times 2608169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 2609169240Sjfv **/ 2610173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2611169240Sjfv{ 2612185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2613169240Sjfv u32 phy_ctrl; 2614169240Sjfv s32 ret_val = E1000_SUCCESS; 2615169240Sjfv u16 i, data; 2616173788Sjfv bool link; 2617169240Sjfv 2618169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2619169240Sjfv 2620173788Sjfv if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2621169240Sjfv goto out; 2622169240Sjfv 2623173788Sjfv /* 2624173788Sjfv * Make sure link is up before proceeding. If not just return. 2625169240Sjfv * Attempting this while link is negotiating fouled up link 2626173788Sjfv * stability 2627173788Sjfv */ 2628169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2629169240Sjfv if (!link) { 2630169240Sjfv ret_val = E1000_SUCCESS; 2631169240Sjfv goto out; 2632169240Sjfv } 2633169240Sjfv 2634169240Sjfv for (i = 0; i < 10; i++) { 2635169240Sjfv /* read once to clear */ 2636177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2637169240Sjfv if (ret_val) 2638169240Sjfv goto out; 2639169240Sjfv /* and again to get new status */ 2640177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2641169240Sjfv if (ret_val) 2642169240Sjfv goto out; 2643169240Sjfv 2644169240Sjfv /* check for PCS lock */ 2645169240Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2646169240Sjfv ret_val = E1000_SUCCESS; 2647169240Sjfv goto out; 2648169240Sjfv } 2649169240Sjfv 2650169240Sjfv /* Issue PHY reset */ 2651177867Sjfv hw->phy.ops.reset(hw); 2652169240Sjfv msec_delay_irq(5); 2653169240Sjfv } 2654169240Sjfv /* Disable GigE link negotiation */ 2655169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2656169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2657169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2658169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2659169240Sjfv 2660173788Sjfv /* 2661176667Sjfv * Call gig speed drop workaround on Gig disable before accessing 2662173788Sjfv * any PHY registers 2663173788Sjfv */ 2664169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2665169240Sjfv 2666169240Sjfv /* unable to acquire PCS lock */ 2667169240Sjfv ret_val = -E1000_ERR_PHY; 2668169240Sjfv 2669169240Sjfvout: 2670169240Sjfv return ret_val; 2671169240Sjfv} 2672169240Sjfv 2673169240Sjfv/** 2674176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2675169589Sjfv * @hw: pointer to the HW structure 2676176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 2677169240Sjfv * 2678169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2679169240Sjfv * /disabled - FALSE). 2680169240Sjfv **/ 2681173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2682173788Sjfv bool state) 2683169240Sjfv{ 2684185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2685169240Sjfv 2686169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2687169240Sjfv 2688169240Sjfv if (hw->mac.type != e1000_ich8lan) { 2689169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 2690185353Sjfv return; 2691169240Sjfv } 2692169240Sjfv 2693169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 2694169240Sjfv 2695169240Sjfv return; 2696169240Sjfv} 2697169240Sjfv 2698169240Sjfv/** 2699169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2700169589Sjfv * @hw: pointer to the HW structure 2701169240Sjfv * 2702169240Sjfv * Workaround for 82566 power-down on D3 entry: 2703169240Sjfv * 1) disable gigabit link 2704169240Sjfv * 2) write VR power-down enable 2705169240Sjfv * 3) read it back 2706169240Sjfv * Continue if successful, else issue LCD reset and repeat 2707169240Sjfv **/ 2708173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2709169240Sjfv{ 2710169240Sjfv u32 reg; 2711169240Sjfv u16 data; 2712169240Sjfv u8 retry = 0; 2713169240Sjfv 2714169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2715169240Sjfv 2716169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 2717169240Sjfv goto out; 2718169240Sjfv 2719169240Sjfv /* Try the workaround twice (if needed) */ 2720169240Sjfv do { 2721169240Sjfv /* Disable link */ 2722169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2723169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2724169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2725169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2726169240Sjfv 2727173788Sjfv /* 2728176667Sjfv * Call gig speed drop workaround on Gig disable before 2729173788Sjfv * accessing any PHY registers 2730173788Sjfv */ 2731169240Sjfv if (hw->mac.type == e1000_ich8lan) 2732169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2733169240Sjfv 2734169240Sjfv /* Write VR power-down enable */ 2735177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2736169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2737185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 2738169240Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2739169240Sjfv 2740169240Sjfv /* Read it back and test */ 2741177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2742169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2743169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2744169240Sjfv break; 2745169240Sjfv 2746169240Sjfv /* Issue PHY reset and repeat at most one more time */ 2747169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 2748169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2749169240Sjfv retry++; 2750169240Sjfv } while (retry); 2751169240Sjfv 2752169240Sjfvout: 2753169240Sjfv return; 2754169240Sjfv} 2755169240Sjfv 2756169240Sjfv/** 2757169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2758169589Sjfv * @hw: pointer to the HW structure 2759169240Sjfv * 2760169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2761176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 2762169240Sjfv * 1) Set Kumeran Near-end loopback 2763169240Sjfv * 2) Clear Kumeran Near-end loopback 2764169240Sjfv * Should only be called for ICH8[m] devices with IGP_3 Phy. 2765169240Sjfv **/ 2766173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2767169240Sjfv{ 2768169240Sjfv s32 ret_val = E1000_SUCCESS; 2769169240Sjfv u16 reg_data; 2770169240Sjfv 2771169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2772169240Sjfv 2773169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 2774169240Sjfv (hw->phy.type != e1000_phy_igp_3)) 2775169240Sjfv goto out; 2776169240Sjfv 2777181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2778181027Sjfv ®_data); 2779169240Sjfv if (ret_val) 2780169240Sjfv goto out; 2781169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2782181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2783181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 2784181027Sjfv reg_data); 2785169240Sjfv if (ret_val) 2786169240Sjfv goto out; 2787169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2788181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2789181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 2790181027Sjfv reg_data); 2791169240Sjfvout: 2792169240Sjfv return; 2793169240Sjfv} 2794169240Sjfv 2795169240Sjfv/** 2796176667Sjfv * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2797176667Sjfv * @hw: pointer to the HW structure 2798176667Sjfv * 2799176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 2800176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 2801176667Sjfv * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2802176667Sjfv * to a lower speed. 2803176667Sjfv * 2804190872Sjfv * Should only be called for applicable parts. 2805176667Sjfv **/ 2806176667Sjfvvoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2807176667Sjfv{ 2808176667Sjfv u32 phy_ctrl; 2809176667Sjfv 2810190872Sjfv switch (hw->mac.type) { 2811190872Sjfv case e1000_ich9lan: 2812190872Sjfv case e1000_ich10lan: 2813194865Sjfv case e1000_pchlan: 2814176667Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2815176667Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2816176667Sjfv E1000_PHY_CTRL_GBE_DISABLE; 2817176667Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2818194865Sjfv 2819194865Sjfv /* Workaround SWFLAG unexpectedly set during S0->Sx */ 2820194865Sjfv if (hw->mac.type == e1000_pchlan) 2821194865Sjfv usec_delay(500); 2822190872Sjfv default: 2823190872Sjfv break; 2824176667Sjfv } 2825176667Sjfv 2826176667Sjfv return; 2827176667Sjfv} 2828176667Sjfv 2829176667Sjfv/** 2830169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 2831169589Sjfv * @hw: pointer to the HW structure 2832169240Sjfv * 2833169240Sjfv * Return the LED back to the default configuration. 2834169240Sjfv **/ 2835177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2836169240Sjfv{ 2837169240Sjfv s32 ret_val = E1000_SUCCESS; 2838169240Sjfv 2839169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2840169240Sjfv 2841169240Sjfv if (hw->phy.type == e1000_phy_ife) 2842185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2843176667Sjfv 0); 2844169240Sjfv else 2845169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2846169240Sjfv 2847169240Sjfv return ret_val; 2848169240Sjfv} 2849169240Sjfv 2850169240Sjfv/** 2851176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 2852169589Sjfv * @hw: pointer to the HW structure 2853169240Sjfv * 2854176667Sjfv * Turn on the LEDs. 2855169240Sjfv **/ 2856177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2857169240Sjfv{ 2858169240Sjfv s32 ret_val = E1000_SUCCESS; 2859169240Sjfv 2860169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 2861169240Sjfv 2862169240Sjfv if (hw->phy.type == e1000_phy_ife) 2863185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2864169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2865169240Sjfv else 2866169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2867169240Sjfv 2868169240Sjfv return ret_val; 2869169240Sjfv} 2870169240Sjfv 2871169240Sjfv/** 2872176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 2873169589Sjfv * @hw: pointer to the HW structure 2874169240Sjfv * 2875176667Sjfv * Turn off the LEDs. 2876169240Sjfv **/ 2877177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2878169240Sjfv{ 2879169240Sjfv s32 ret_val = E1000_SUCCESS; 2880169240Sjfv 2881169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 2882169240Sjfv 2883169240Sjfv if (hw->phy.type == e1000_phy_ife) 2884177867Sjfv ret_val = hw->phy.ops.write_reg(hw, 2885169240Sjfv IFE_PHY_SPECIAL_CONTROL_LED, 2886169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2887169240Sjfv else 2888169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2889169240Sjfv 2890169240Sjfv return ret_val; 2891169240Sjfv} 2892169240Sjfv 2893169240Sjfv/** 2894194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 2895194865Sjfv * @hw: pointer to the HW structure 2896194865Sjfv * 2897194865Sjfv * This prepares the SW controllable LED for use. 2898194865Sjfv **/ 2899194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 2900194865Sjfv{ 2901194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 2902194865Sjfv 2903194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 2904194865Sjfv (u16)hw->mac.ledctl_mode1); 2905194865Sjfv} 2906194865Sjfv 2907194865Sjfv/** 2908194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 2909194865Sjfv * @hw: pointer to the HW structure 2910194865Sjfv * 2911194865Sjfv * Return the LED back to the default configuration. 2912194865Sjfv **/ 2913194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 2914194865Sjfv{ 2915194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 2916194865Sjfv 2917194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 2918194865Sjfv (u16)hw->mac.ledctl_default); 2919194865Sjfv} 2920194865Sjfv 2921194865Sjfv/** 2922194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 2923194865Sjfv * @hw: pointer to the HW structure 2924194865Sjfv * 2925194865Sjfv * Turn on the LEDs. 2926194865Sjfv **/ 2927194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 2928194865Sjfv{ 2929194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 2930194865Sjfv u32 i, led; 2931194865Sjfv 2932194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 2933194865Sjfv 2934194865Sjfv /* 2935194865Sjfv * If no link, then turn LED on by setting the invert bit 2936194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 2937194865Sjfv */ 2938194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2939194865Sjfv for (i = 0; i < 3; i++) { 2940194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 2941194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 2942194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 2943194865Sjfv continue; 2944194865Sjfv if (led & E1000_PHY_LED0_IVRT) 2945194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 2946194865Sjfv else 2947194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 2948194865Sjfv } 2949194865Sjfv } 2950194865Sjfv 2951194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 2952194865Sjfv} 2953194865Sjfv 2954194865Sjfv/** 2955194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 2956194865Sjfv * @hw: pointer to the HW structure 2957194865Sjfv * 2958194865Sjfv * Turn off the LEDs. 2959194865Sjfv **/ 2960194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 2961194865Sjfv{ 2962194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 2963194865Sjfv u32 i, led; 2964194865Sjfv 2965194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 2966194865Sjfv 2967194865Sjfv /* 2968194865Sjfv * If no link, then turn LED off by clearing the invert bit 2969194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 2970194865Sjfv */ 2971194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2972194865Sjfv for (i = 0; i < 3; i++) { 2973194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 2974194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 2975194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 2976194865Sjfv continue; 2977194865Sjfv if (led & E1000_PHY_LED0_IVRT) 2978194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 2979194865Sjfv else 2980194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 2981194865Sjfv } 2982194865Sjfv } 2983194865Sjfv 2984194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 2985194865Sjfv} 2986194865Sjfv 2987194865Sjfv/** 2988169240Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit 2989169589Sjfv * @hw: pointer to the HW structure 2990169240Sjfv * 2991169240Sjfv * Read the management control register for the config done bit for 2992169240Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 2993169240Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 2994169240Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2995169240Sjfv * would not be able to be reset or change link. 2996169240Sjfv **/ 2997177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2998169240Sjfv{ 2999173788Sjfv s32 ret_val = E1000_SUCCESS; 3000178523Sjfv u32 bank = 0; 3001173788Sjfv 3002194865Sjfv if (hw->mac.type >= e1000_pchlan) { 3003194865Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 3004194865Sjfv 3005194865Sjfv if (status & E1000_STATUS_PHYRA) { 3006194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & 3007194865Sjfv ~E1000_STATUS_PHYRA); 3008194865Sjfv } else 3009194865Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 3010194865Sjfv } 3011194865Sjfv 3012169240Sjfv e1000_get_cfg_done_generic(hw); 3013169240Sjfv 3014169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3015194865Sjfv if ((hw->mac.type != e1000_ich10lan) && 3016194865Sjfv (hw->mac.type != e1000_pchlan)) { 3017178523Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 3018185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 3019178523Sjfv e1000_phy_init_script_igp3(hw); 3020178523Sjfv } 3021178523Sjfv } else { 3022178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 3023185353Sjfv /* Maybe we should do a basic PHY config */ 3024178523Sjfv DEBUGOUT("EEPROM not present\n"); 3025178523Sjfv ret_val = -E1000_ERR_CONFIG; 3026178523Sjfv } 3027169240Sjfv } 3028169240Sjfv 3029173788Sjfv return ret_val; 3030169240Sjfv} 3031169240Sjfv 3032169240Sjfv/** 3033173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 3034173788Sjfv * @hw: pointer to the HW structure 3035173788Sjfv * 3036173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 3037173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 3038173788Sjfv **/ 3039177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 3040173788Sjfv{ 3041173788Sjfv /* If the management interface is not enabled, then power down */ 3042185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 3043185353Sjfv hw->phy.ops.check_reset_block(hw))) 3044173788Sjfv e1000_power_down_phy_copper(hw); 3045173788Sjfv 3046173788Sjfv return; 3047173788Sjfv} 3048173788Sjfv 3049173788Sjfv/** 3050169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 3051169589Sjfv * @hw: pointer to the HW structure 3052169240Sjfv * 3053169240Sjfv * Clears hardware counters specific to the silicon family and calls 3054169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 3055169240Sjfv **/ 3056177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 3057169240Sjfv{ 3058194865Sjfv u16 phy_data; 3059194865Sjfv 3060169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 3061169240Sjfv 3062169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 3063169240Sjfv 3064185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 3065185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 3066185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 3067185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 3068185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 3069185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 3070169240Sjfv 3071185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 3072185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 3073185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 3074169240Sjfv 3075185353Sjfv E1000_READ_REG(hw, E1000_IAC); 3076185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 3077194865Sjfv 3078194865Sjfv /* Clear PHY statistics registers */ 3079194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 3080194865Sjfv (hw->phy.type == e1000_phy_82577)) { 3081194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3082194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3083194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3084194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3085194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3086194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3087194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3088194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3089194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3090194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3091194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3092194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3093194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3094194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3095194865Sjfv } 3096169240Sjfv} 3097169240Sjfv 3098