e1000_ich8lan.c revision 185353
1177867Sjfv/****************************************************************************** 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 185353 2008-11-26 23:57:23Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82562G 10/100 Network Connection 37185353Sjfv * 82562G-2 10/100 Network Connection 38185353Sjfv * 82562GT 10/100 Network Connection 39185353Sjfv * 82562GT-2 10/100 Network Connection 40185353Sjfv * 82562V 10/100 Network Connection 41185353Sjfv * 82562V-2 10/100 Network Connection 42185353Sjfv * 82566DC-2 Gigabit Network Connection 43185353Sjfv * 82566DC Gigabit Network Connection 44185353Sjfv * 82566DM-2 Gigabit Network Connection 45185353Sjfv * 82566DM Gigabit Network Connection 46185353Sjfv * 82566MC Gigabit Network Connection 47185353Sjfv * 82566MM Gigabit Network Connection 48185353Sjfv * 82567LM Gigabit Network Connection 49185353Sjfv * 82567LF Gigabit Network Connection 50185353Sjfv * 82567V Gigabit Network Connection 51185353Sjfv * 82567LM-2 Gigabit Network Connection 52185353Sjfv * 82567LF-2 Gigabit Network Connection 53185353Sjfv * 82567V-2 Gigabit Network Connection 54185353Sjfv * 82567LF-3 Gigabit Network Connection 55185353Sjfv * 82567LM-3 Gigabit Network Connection 56185353Sjfv * 82567LM-4 Gigabit Network Connection 57169240Sjfv */ 58169240Sjfv 59169589Sjfv#include "e1000_api.h" 60169240Sjfv 61177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 62177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 64177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 65177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 66177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 67177867Sjfvstatic s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 68177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 69177867Sjfvstatic s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 71177867Sjfvstatic s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 72177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 73173788Sjfv bool active); 74177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 75173788Sjfv bool active); 76177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 77173788Sjfv u16 words, u16 *data); 78177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 79173788Sjfv u16 words, u16 *data); 80177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 81177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 82177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 83173788Sjfv u16 *data); 84177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 85177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 86177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 87177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 88177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 89177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 90173788Sjfv u16 *speed, u16 *duplex); 91177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 92177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 93177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 94177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 95177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 96173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 97173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 98173788Sjfvstatic s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 99173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 100173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 101178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 102185353Sjfv u32 offset, u8 *data); 103173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 104185353Sjfv u8 size, u16 *data); 105177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 106173788Sjfv u32 offset, u16 *data); 107173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 108173788Sjfv u32 offset, u8 byte); 109177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 110173788Sjfv u32 offset, u8 data); 111173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 112173788Sjfv u8 size, u16 data); 113177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 114177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 115169240Sjfv 116169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 117169240Sjfv/* Offset 04h HSFSTS */ 118169240Sjfvunion ich8_hws_flash_status { 119169240Sjfv struct ich8_hsfsts { 120169240Sjfv u16 flcdone :1; /* bit 0 Flash Cycle Done */ 121169240Sjfv u16 flcerr :1; /* bit 1 Flash Cycle Error */ 122169240Sjfv u16 dael :1; /* bit 2 Direct Access error Log */ 123169240Sjfv u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 124169240Sjfv u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 125169240Sjfv u16 reserved1 :2; /* bit 13:6 Reserved */ 126169240Sjfv u16 reserved2 :6; /* bit 13:6 Reserved */ 127169240Sjfv u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 128169240Sjfv u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 129169240Sjfv } hsf_status; 130169240Sjfv u16 regval; 131169240Sjfv}; 132169240Sjfv 133169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 134169240Sjfv/* Offset 06h FLCTL */ 135169240Sjfvunion ich8_hws_flash_ctrl { 136169240Sjfv struct ich8_hsflctl { 137169240Sjfv u16 flcgo :1; /* 0 Flash Cycle Go */ 138169240Sjfv u16 flcycle :2; /* 2:1 Flash Cycle */ 139169240Sjfv u16 reserved :5; /* 7:3 Reserved */ 140169240Sjfv u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 141169240Sjfv u16 flockdn :6; /* 15:10 Reserved */ 142169240Sjfv } hsf_ctrl; 143169240Sjfv u16 regval; 144169240Sjfv}; 145169240Sjfv 146169240Sjfv/* ICH Flash Region Access Permissions */ 147169240Sjfvunion ich8_hws_flash_regacc { 148169240Sjfv struct ich8_flracc { 149169240Sjfv u32 grra :8; /* 0:7 GbE region Read Access */ 150169240Sjfv u32 grwa :8; /* 8:15 GbE region Write Access */ 151169240Sjfv u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 152169240Sjfv u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 153169240Sjfv } hsf_flregacc; 154169240Sjfv u16 regval; 155169240Sjfv}; 156169240Sjfv 157169240Sjfv/** 158169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 159169589Sjfv * @hw: pointer to the HW structure 160169240Sjfv * 161169240Sjfv * Initialize family-specific PHY parameters and function pointers. 162169240Sjfv **/ 163177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 164169240Sjfv{ 165169240Sjfv struct e1000_phy_info *phy = &hw->phy; 166169240Sjfv s32 ret_val = E1000_SUCCESS; 167169589Sjfv u16 i = 0; 168169240Sjfv 169169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 170169240Sjfv 171177867Sjfv phy->addr = 1; 172177867Sjfv phy->reset_delay_us = 100; 173169240Sjfv 174177867Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 175177867Sjfv phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 176177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 177177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 178177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 179177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 180177867Sjfv phy->ops.get_info = e1000_get_phy_info_ich8lan; 181177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 182177867Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 183177867Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 184177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 185177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 186177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 187177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 188177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 189169240Sjfv 190176667Sjfv /* 191176667Sjfv * We may need to do this twice - once for IGP and if that fails, 192176667Sjfv * we'll set BM func pointers and try again 193176667Sjfv */ 194176667Sjfv ret_val = e1000_determine_phy_address(hw); 195176667Sjfv if (ret_val) { 196177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 197177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 198176667Sjfv ret_val = e1000_determine_phy_address(hw); 199176667Sjfv if (ret_val) { 200176667Sjfv DEBUGOUT("Cannot determine PHY address. Erroring out\n"); 201176667Sjfv goto out; 202176667Sjfv } 203176667Sjfv } 204169240Sjfv 205169589Sjfv phy->id = 0; 206169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 207169589Sjfv (i++ < 100)) { 208169589Sjfv msec_delay(1); 209169589Sjfv ret_val = e1000_get_phy_id(hw); 210169589Sjfv if (ret_val) 211169589Sjfv goto out; 212169589Sjfv } 213169589Sjfv 214169240Sjfv /* Verify phy id */ 215169240Sjfv switch (phy->id) { 216169240Sjfv case IGP03E1000_E_PHY_ID: 217169240Sjfv phy->type = e1000_phy_igp_3; 218169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 219169240Sjfv break; 220169240Sjfv case IFE_E_PHY_ID: 221169240Sjfv case IFE_PLUS_E_PHY_ID: 222169240Sjfv case IFE_C_E_PHY_ID: 223169240Sjfv phy->type = e1000_phy_ife; 224169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 225169240Sjfv break; 226176667Sjfv case BME1000_E_PHY_ID: 227176667Sjfv phy->type = e1000_phy_bm; 228176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 229177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 230177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 231177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 232176667Sjfv break; 233169240Sjfv default: 234169240Sjfv ret_val = -E1000_ERR_PHY; 235169240Sjfv goto out; 236169240Sjfv } 237169240Sjfv 238169240Sjfvout: 239169240Sjfv return ret_val; 240169240Sjfv} 241169240Sjfv 242169240Sjfv/** 243169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 244169589Sjfv * @hw: pointer to the HW structure 245169240Sjfv * 246169240Sjfv * Initialize family-specific NVM parameters and function 247169240Sjfv * pointers. 248169240Sjfv **/ 249177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 250169240Sjfv{ 251169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 252185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 253169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 254173788Sjfv s32 ret_val = E1000_SUCCESS; 255169240Sjfv u16 i; 256169240Sjfv 257169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 258169240Sjfv 259173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 260169240Sjfv if (!hw->flash_address) { 261169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 262169240Sjfv ret_val = -E1000_ERR_CONFIG; 263169240Sjfv goto out; 264169240Sjfv } 265169240Sjfv 266185353Sjfv nvm->type = e1000_nvm_flash_sw; 267169240Sjfv 268169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 269169240Sjfv 270173788Sjfv /* 271173788Sjfv * sector_X_addr is a "sector"-aligned address (4096 bytes) 272169240Sjfv * Add 1 to sector_end_addr since this sector is included in 273173788Sjfv * the overall size. 274173788Sjfv */ 275169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 276169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 277169240Sjfv 278169240Sjfv /* flash_base_addr is byte-aligned */ 279185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 280169240Sjfv 281173788Sjfv /* 282173788Sjfv * find total size of the NVM, then cut in half since the total 283173788Sjfv * size represents two separate NVM banks. 284173788Sjfv */ 285185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 286169240Sjfv << FLASH_SECTOR_ADDR_SHIFT; 287185353Sjfv nvm->flash_bank_size /= 2; 288169240Sjfv /* Adjust to word count */ 289185353Sjfv nvm->flash_bank_size /= sizeof(u16); 290169240Sjfv 291185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 292169240Sjfv 293169240Sjfv /* Clear shadow ram */ 294169240Sjfv for (i = 0; i < nvm->word_size; i++) { 295169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 296169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 297169240Sjfv } 298169240Sjfv 299169240Sjfv /* Function Pointers */ 300177867Sjfv nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 301177867Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 302177867Sjfv nvm->ops.release = e1000_release_swflag_ich8lan; 303177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 304177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 305177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 306177867Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 307169240Sjfv 308169240Sjfvout: 309169240Sjfv return ret_val; 310169240Sjfv} 311169240Sjfv 312169240Sjfv/** 313169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 314169589Sjfv * @hw: pointer to the HW structure 315169240Sjfv * 316169240Sjfv * Initialize family-specific MAC parameters and function 317169240Sjfv * pointers. 318169240Sjfv **/ 319177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 320169240Sjfv{ 321169240Sjfv struct e1000_mac_info *mac = &hw->mac; 322169240Sjfv 323169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 324169240Sjfv 325169240Sjfv /* Set media type function pointer */ 326173788Sjfv hw->phy.media_type = e1000_media_type_copper; 327169240Sjfv 328169240Sjfv /* Set mta register count */ 329169240Sjfv mac->mta_reg_count = 32; 330169240Sjfv /* Set rar entry count */ 331169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 332169240Sjfv if (mac->type == e1000_ich8lan) 333169240Sjfv mac->rar_entry_count--; 334169240Sjfv /* Set if part includes ASF firmware */ 335169240Sjfv mac->asf_firmware_present = TRUE; 336169240Sjfv /* Set if manageability features are enabled. */ 337169240Sjfv mac->arc_subsystem_valid = TRUE; 338169240Sjfv 339169240Sjfv /* Function pointers */ 340169240Sjfv 341169240Sjfv /* bus type/speed/width */ 342177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 343185353Sjfv /* function id */ 344185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 345169240Sjfv /* reset */ 346177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 347169240Sjfv /* hw initialization */ 348177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 349169240Sjfv /* link setup */ 350177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 351169240Sjfv /* physical interface setup */ 352177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 353169240Sjfv /* check for link */ 354177867Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 355169240Sjfv /* check management mode */ 356177867Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 357169240Sjfv /* link info */ 358177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 359169240Sjfv /* multicast address update */ 360177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 361169240Sjfv /* setting MTA */ 362177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 363169240Sjfv /* blink LED */ 364177867Sjfv mac->ops.blink_led = e1000_blink_led_generic; 365169240Sjfv /* setup LED */ 366177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 367169240Sjfv /* cleanup LED */ 368177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 369169240Sjfv /* turn on/off LED */ 370177867Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 371177867Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 372169240Sjfv /* clear hardware counters */ 373177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 374169240Sjfv 375169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 376169240Sjfv if (mac->type == e1000_ich8lan) 377169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 378169240Sjfv 379169240Sjfv 380185353Sjfv return E1000_SUCCESS; 381169240Sjfv} 382169240Sjfv 383169240Sjfv/** 384169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 385169589Sjfv * @hw: pointer to the HW structure 386169240Sjfv * 387169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 388169240Sjfv **/ 389173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 390169240Sjfv{ 391169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 392169240Sjfv 393177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 394177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 395177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 396169240Sjfv} 397169240Sjfv 398169240Sjfv/** 399169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 400169589Sjfv * @hw: pointer to the HW structure 401169240Sjfv * 402169240Sjfv * Acquires the software control flag for performing NVM and PHY 403169240Sjfv * operations. This is a function pointer entry point only called by 404169240Sjfv * read/write routines for the PHY and NVM parts. 405169240Sjfv **/ 406177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 407169240Sjfv{ 408169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 409169240Sjfv s32 ret_val = E1000_SUCCESS; 410169240Sjfv 411169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 412169240Sjfv 413169240Sjfv while (timeout) { 414169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 415169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 416169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 417169240Sjfv 418169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 419169240Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 420169240Sjfv break; 421169240Sjfv msec_delay_irq(1); 422169240Sjfv timeout--; 423169240Sjfv } 424169240Sjfv 425169240Sjfv if (!timeout) { 426169240Sjfv DEBUGOUT("FW or HW has locked the resource for too long.\n"); 427173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 428173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 429169240Sjfv ret_val = -E1000_ERR_CONFIG; 430169240Sjfv goto out; 431169240Sjfv } 432169240Sjfv 433169240Sjfvout: 434169240Sjfv return ret_val; 435169240Sjfv} 436169240Sjfv 437169240Sjfv/** 438169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 439169589Sjfv * @hw: pointer to the HW structure 440169240Sjfv * 441169240Sjfv * Releases the software control flag for performing NVM and PHY operations. 442169240Sjfv * This is a function pointer entry point only called by read/write 443169240Sjfv * routines for the PHY and NVM parts. 444169240Sjfv **/ 445177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 446169240Sjfv{ 447169240Sjfv u32 extcnf_ctrl; 448169240Sjfv 449169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 450169240Sjfv 451169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 452169240Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 453169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 454169240Sjfv 455169240Sjfv return; 456169240Sjfv} 457169240Sjfv 458169240Sjfv/** 459169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 460169589Sjfv * @hw: pointer to the HW structure 461169240Sjfv * 462169240Sjfv * This checks if the adapter has manageability enabled. 463169240Sjfv * This is a function pointer entry point only called by read/write 464169240Sjfv * routines for the PHY and NVM parts. 465169240Sjfv **/ 466177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 467169240Sjfv{ 468169240Sjfv u32 fwsm; 469169240Sjfv 470169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 471169240Sjfv 472169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 473169240Sjfv 474185353Sjfv return (fwsm & E1000_FWSM_MODE_MASK) == 475185353Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 476169240Sjfv} 477169240Sjfv 478169240Sjfv/** 479169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 480169589Sjfv * @hw: pointer to the HW structure 481169240Sjfv * 482169240Sjfv * Checks if firmware is blocking the reset of the PHY. 483169240Sjfv * This is a function pointer entry point only called by 484169240Sjfv * reset routines. 485169240Sjfv **/ 486177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 487169240Sjfv{ 488169240Sjfv u32 fwsm; 489169240Sjfv 490169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 491169240Sjfv 492169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 493169240Sjfv 494169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 495169240Sjfv : E1000_BLK_PHY_RESET; 496169240Sjfv} 497169240Sjfv 498169240Sjfv/** 499169240Sjfv * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 500169589Sjfv * @hw: pointer to the HW structure 501169240Sjfv * 502169240Sjfv * Forces the speed and duplex settings of the PHY. 503169240Sjfv * This is a function pointer entry point only called by 504169240Sjfv * PHY setup routines. 505169240Sjfv **/ 506177867Sjfvstatic s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 507169240Sjfv{ 508169240Sjfv struct e1000_phy_info *phy = &hw->phy; 509169240Sjfv s32 ret_val; 510169240Sjfv u16 data; 511173788Sjfv bool link; 512169240Sjfv 513169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 514169240Sjfv 515169240Sjfv if (phy->type != e1000_phy_ife) { 516169240Sjfv ret_val = e1000_phy_force_speed_duplex_igp(hw); 517169240Sjfv goto out; 518169240Sjfv } 519169240Sjfv 520177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 521169240Sjfv if (ret_val) 522169240Sjfv goto out; 523169240Sjfv 524169240Sjfv e1000_phy_force_speed_duplex_setup(hw, &data); 525169240Sjfv 526177867Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 527169240Sjfv if (ret_val) 528169240Sjfv goto out; 529169240Sjfv 530169240Sjfv /* Disable MDI-X support for 10/100 */ 531177867Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 532169240Sjfv if (ret_val) 533169240Sjfv goto out; 534169240Sjfv 535169240Sjfv data &= ~IFE_PMC_AUTO_MDIX; 536169240Sjfv data &= ~IFE_PMC_FORCE_MDIX; 537169240Sjfv 538177867Sjfv ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 539169240Sjfv if (ret_val) 540169240Sjfv goto out; 541169240Sjfv 542169240Sjfv DEBUGOUT1("IFE PMC: %X\n", data); 543169240Sjfv 544169240Sjfv usec_delay(1); 545169240Sjfv 546173788Sjfv if (phy->autoneg_wait_to_complete) { 547169240Sjfv DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 548169240Sjfv 549169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 550169240Sjfv PHY_FORCE_LIMIT, 551169240Sjfv 100000, 552169240Sjfv &link); 553169240Sjfv if (ret_val) 554169240Sjfv goto out; 555169240Sjfv 556185353Sjfv if (!link) 557169240Sjfv DEBUGOUT("Link taking longer than expected.\n"); 558169240Sjfv 559169240Sjfv /* Try once more */ 560169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 561169240Sjfv PHY_FORCE_LIMIT, 562169240Sjfv 100000, 563169240Sjfv &link); 564169240Sjfv if (ret_val) 565169240Sjfv goto out; 566169240Sjfv } 567169240Sjfv 568169240Sjfvout: 569169240Sjfv return ret_val; 570169240Sjfv} 571169240Sjfv 572169240Sjfv/** 573169240Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 574169589Sjfv * @hw: pointer to the HW structure 575169240Sjfv * 576169240Sjfv * Resets the PHY 577169240Sjfv * This is a function pointer entry point called by drivers 578169240Sjfv * or other shared routines. 579169240Sjfv **/ 580177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 581169240Sjfv{ 582169240Sjfv struct e1000_phy_info *phy = &hw->phy; 583169240Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 584169240Sjfv s32 ret_val; 585169240Sjfv u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 586169240Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 587169240Sjfv 588169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 589169240Sjfv 590169240Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 591169240Sjfv if (ret_val) 592169240Sjfv goto out; 593169240Sjfv 594173788Sjfv /* 595173788Sjfv * Initialize the PHY from the NVM on ICH platforms. This 596169240Sjfv * is needed due to an issue where the NVM configuration is 597169240Sjfv * not properly autoloaded after power transitions. 598169240Sjfv * Therefore, after each PHY reset, we will load the 599169240Sjfv * configuration data out of the NVM manually. 600169240Sjfv */ 601169240Sjfv if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 602169240Sjfv /* Check if SW needs configure the PHY */ 603169240Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 604169240Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 605169240Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 606169240Sjfv else 607169240Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 608169240Sjfv 609169240Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 610169240Sjfv if (!(data & sw_cfg_mask)) 611169240Sjfv goto out; 612169240Sjfv 613169240Sjfv /* Wait for basic configuration completes before proceeding*/ 614169240Sjfv do { 615169240Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 616169240Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 617169240Sjfv usec_delay(100); 618169240Sjfv } while ((!data) && --loop); 619169240Sjfv 620173788Sjfv /* 621173788Sjfv * If basic configuration is incomplete before the above loop 622169240Sjfv * count reaches 0, loading the configuration from NVM will 623169240Sjfv * leave the PHY in a bad state possibly resulting in no link. 624169240Sjfv */ 625185353Sjfv if (loop == 0) 626169240Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 627169240Sjfv 628169240Sjfv /* Clear the Init Done bit for the next init event */ 629169240Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 630169240Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 631169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 632169240Sjfv 633173788Sjfv /* 634173788Sjfv * Make sure HW does not configure LCD from PHY 635173788Sjfv * extended configuration before SW configuration 636173788Sjfv */ 637169240Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 638169240Sjfv if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 639169240Sjfv goto out; 640169240Sjfv 641169240Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 642169240Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 643169240Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 644169240Sjfv if (!cnf_size) 645169240Sjfv goto out; 646169240Sjfv 647169240Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 648169240Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 649169240Sjfv 650185353Sjfv /* Configure LCD from extended configuration region. */ 651169240Sjfv 652169240Sjfv /* cnf_base_addr is in DWORD */ 653169240Sjfv word_addr = (u16)(cnf_base_addr << 1); 654169240Sjfv 655169240Sjfv for (i = 0; i < cnf_size; i++) { 656185353Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 657185353Sjfv ®_data); 658169240Sjfv if (ret_val) 659169240Sjfv goto out; 660169240Sjfv 661185353Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 662185353Sjfv 1, ®_addr); 663169240Sjfv if (ret_val) 664169240Sjfv goto out; 665169240Sjfv 666169240Sjfv /* Save off the PHY page for future writes. */ 667169240Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 668169240Sjfv phy_page = reg_data; 669169240Sjfv continue; 670169240Sjfv } 671169240Sjfv 672169240Sjfv reg_addr |= phy_page; 673169240Sjfv 674185353Sjfv ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data); 675169240Sjfv if (ret_val) 676169240Sjfv goto out; 677169240Sjfv } 678169240Sjfv } 679169240Sjfv 680169240Sjfvout: 681169240Sjfv return ret_val; 682169240Sjfv} 683169240Sjfv 684169240Sjfv/** 685169240Sjfv * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 686169589Sjfv * @hw: pointer to the HW structure 687169240Sjfv * 688169240Sjfv * Wrapper for calling the get_phy_info routines for the appropriate phy type. 689169240Sjfv **/ 690177867Sjfvstatic s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 691169240Sjfv{ 692169240Sjfv s32 ret_val = -E1000_ERR_PHY_TYPE; 693169240Sjfv 694169240Sjfv DEBUGFUNC("e1000_get_phy_info_ich8lan"); 695169240Sjfv 696169240Sjfv switch (hw->phy.type) { 697169240Sjfv case e1000_phy_ife: 698169240Sjfv ret_val = e1000_get_phy_info_ife_ich8lan(hw); 699169240Sjfv break; 700169240Sjfv case e1000_phy_igp_3: 701176667Sjfv case e1000_phy_bm: 702169240Sjfv ret_val = e1000_get_phy_info_igp(hw); 703169240Sjfv break; 704169240Sjfv default: 705169240Sjfv break; 706169240Sjfv } 707169240Sjfv 708169240Sjfv return ret_val; 709169240Sjfv} 710169240Sjfv 711169240Sjfv/** 712169240Sjfv * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 713169589Sjfv * @hw: pointer to the HW structure 714169240Sjfv * 715169240Sjfv * Populates "phy" structure with various feature states. 716169240Sjfv * This function is only called by other family-specific 717169240Sjfv * routines. 718169240Sjfv **/ 719173788Sjfvstatic s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 720169240Sjfv{ 721169240Sjfv struct e1000_phy_info *phy = &hw->phy; 722169240Sjfv s32 ret_val; 723169240Sjfv u16 data; 724173788Sjfv bool link; 725169240Sjfv 726169240Sjfv DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 727169240Sjfv 728169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 729169240Sjfv if (ret_val) 730169240Sjfv goto out; 731169240Sjfv 732169240Sjfv if (!link) { 733169240Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 734169240Sjfv ret_val = -E1000_ERR_CONFIG; 735169240Sjfv goto out; 736169240Sjfv } 737169240Sjfv 738177867Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 739169240Sjfv if (ret_val) 740169240Sjfv goto out; 741169240Sjfv phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 742169240Sjfv ? FALSE : TRUE; 743169240Sjfv 744169240Sjfv if (phy->polarity_correction) { 745169240Sjfv ret_val = e1000_check_polarity_ife_ich8lan(hw); 746169240Sjfv if (ret_val) 747169240Sjfv goto out; 748169240Sjfv } else { 749169240Sjfv /* Polarity is forced */ 750169240Sjfv phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 751169240Sjfv ? e1000_rev_polarity_reversed 752169240Sjfv : e1000_rev_polarity_normal; 753169240Sjfv } 754169240Sjfv 755177867Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 756169240Sjfv if (ret_val) 757169240Sjfv goto out; 758169240Sjfv 759169240Sjfv phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 760169240Sjfv 761169240Sjfv /* The following parameters are undefined for 10/100 operation. */ 762169240Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 763169240Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 764169240Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 765169240Sjfv 766169240Sjfvout: 767169240Sjfv return ret_val; 768169240Sjfv} 769169240Sjfv 770169240Sjfv/** 771169240Sjfv * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 772169589Sjfv * @hw: pointer to the HW structure 773169240Sjfv * 774176667Sjfv * Polarity is determined on the polarity reversal feature being enabled. 775169240Sjfv * This function is only called by other family-specific 776169240Sjfv * routines. 777169240Sjfv **/ 778177867Sjfvstatic s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 779169240Sjfv{ 780169240Sjfv struct e1000_phy_info *phy = &hw->phy; 781169240Sjfv s32 ret_val; 782169240Sjfv u16 phy_data, offset, mask; 783169240Sjfv 784169240Sjfv DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 785169240Sjfv 786173788Sjfv /* 787185353Sjfv * Polarity is determined based on the reversal feature being enabled. 788169240Sjfv */ 789169240Sjfv if (phy->polarity_correction) { 790169240Sjfv offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 791169240Sjfv mask = IFE_PESC_POLARITY_REVERSED; 792169240Sjfv } else { 793169240Sjfv offset = IFE_PHY_SPECIAL_CONTROL; 794169240Sjfv mask = IFE_PSC_FORCE_POLARITY; 795169240Sjfv } 796169240Sjfv 797177867Sjfv ret_val = phy->ops.read_reg(hw, offset, &phy_data); 798169240Sjfv 799169240Sjfv if (!ret_val) 800169240Sjfv phy->cable_polarity = (phy_data & mask) 801169240Sjfv ? e1000_rev_polarity_reversed 802169240Sjfv : e1000_rev_polarity_normal; 803169240Sjfv 804169240Sjfv return ret_val; 805169240Sjfv} 806169240Sjfv 807169240Sjfv/** 808169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 809169589Sjfv * @hw: pointer to the HW structure 810169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 811169240Sjfv * 812169240Sjfv * Sets the LPLU D0 state according to the active flag. When 813169240Sjfv * activating LPLU this function also disables smart speed 814169240Sjfv * and vice versa. LPLU will not be activated unless the 815169240Sjfv * device autonegotiation advertisement meets standards of 816169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 817169240Sjfv * This is a function pointer entry point only called by 818169240Sjfv * PHY setup routines. 819169240Sjfv **/ 820185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 821169240Sjfv{ 822169240Sjfv struct e1000_phy_info *phy = &hw->phy; 823169240Sjfv u32 phy_ctrl; 824169240Sjfv s32 ret_val = E1000_SUCCESS; 825169240Sjfv u16 data; 826169240Sjfv 827169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 828169240Sjfv 829173788Sjfv if (phy->type == e1000_phy_ife) 830169240Sjfv goto out; 831169240Sjfv 832169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 833169240Sjfv 834169240Sjfv if (active) { 835169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 836169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 837169240Sjfv 838173788Sjfv /* 839173788Sjfv * Call gig speed drop workaround on LPLU before accessing 840173788Sjfv * any PHY registers 841173788Sjfv */ 842169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 843169240Sjfv (hw->phy.type == e1000_phy_igp_3)) 844169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 845169240Sjfv 846169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 847177867Sjfv ret_val = phy->ops.read_reg(hw, 848169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 849169240Sjfv &data); 850169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 851177867Sjfv ret_val = phy->ops.write_reg(hw, 852169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 853169240Sjfv data); 854169240Sjfv if (ret_val) 855169240Sjfv goto out; 856169240Sjfv } else { 857169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 858169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 859169240Sjfv 860173788Sjfv /* 861173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 862169240Sjfv * during Dx states where the power conservation is most 863169240Sjfv * important. During driver activity we should enable 864173788Sjfv * SmartSpeed, so performance is maintained. 865173788Sjfv */ 866169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 867177867Sjfv ret_val = phy->ops.read_reg(hw, 868169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 869169240Sjfv &data); 870169240Sjfv if (ret_val) 871169240Sjfv goto out; 872169240Sjfv 873169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 874177867Sjfv ret_val = phy->ops.write_reg(hw, 875169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 876169240Sjfv data); 877169240Sjfv if (ret_val) 878169240Sjfv goto out; 879169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 880177867Sjfv ret_val = phy->ops.read_reg(hw, 881169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 882169240Sjfv &data); 883169240Sjfv if (ret_val) 884169240Sjfv goto out; 885169240Sjfv 886169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 887177867Sjfv ret_val = phy->ops.write_reg(hw, 888169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 889169240Sjfv data); 890169240Sjfv if (ret_val) 891169240Sjfv goto out; 892169240Sjfv } 893169240Sjfv } 894169240Sjfv 895169240Sjfvout: 896169240Sjfv return ret_val; 897169240Sjfv} 898169240Sjfv 899169240Sjfv/** 900169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 901169589Sjfv * @hw: pointer to the HW structure 902169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 903169240Sjfv * 904169240Sjfv * Sets the LPLU D3 state according to the active flag. When 905169240Sjfv * activating LPLU this function also disables smart speed 906169240Sjfv * and vice versa. LPLU will not be activated unless the 907169240Sjfv * device autonegotiation advertisement meets standards of 908169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 909169240Sjfv * This is a function pointer entry point only called by 910169240Sjfv * PHY setup routines. 911169240Sjfv **/ 912185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 913169240Sjfv{ 914169240Sjfv struct e1000_phy_info *phy = &hw->phy; 915169240Sjfv u32 phy_ctrl; 916169240Sjfv s32 ret_val = E1000_SUCCESS; 917169240Sjfv u16 data; 918169240Sjfv 919169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 920169240Sjfv 921169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 922169240Sjfv 923169240Sjfv if (!active) { 924169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 925169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 926173788Sjfv /* 927173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 928169240Sjfv * during Dx states where the power conservation is most 929169240Sjfv * important. During driver activity we should enable 930173788Sjfv * SmartSpeed, so performance is maintained. 931173788Sjfv */ 932169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 933177867Sjfv ret_val = phy->ops.read_reg(hw, 934169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 935169240Sjfv &data); 936169240Sjfv if (ret_val) 937169240Sjfv goto out; 938169240Sjfv 939169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 940177867Sjfv ret_val = phy->ops.write_reg(hw, 941169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 942169240Sjfv data); 943169240Sjfv if (ret_val) 944169240Sjfv goto out; 945169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 946177867Sjfv ret_val = phy->ops.read_reg(hw, 947169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 948169240Sjfv &data); 949169240Sjfv if (ret_val) 950169240Sjfv goto out; 951169240Sjfv 952169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 953177867Sjfv ret_val = phy->ops.write_reg(hw, 954169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 955169240Sjfv data); 956169240Sjfv if (ret_val) 957169240Sjfv goto out; 958169240Sjfv } 959169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 960169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 961169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 962169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 963169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 964169240Sjfv 965173788Sjfv /* 966173788Sjfv * Call gig speed drop workaround on LPLU before accessing 967173788Sjfv * any PHY registers 968173788Sjfv */ 969169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 970169240Sjfv (hw->phy.type == e1000_phy_igp_3)) 971169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 972169240Sjfv 973169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 974177867Sjfv ret_val = phy->ops.read_reg(hw, 975169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 976169240Sjfv &data); 977169240Sjfv if (ret_val) 978169240Sjfv goto out; 979169240Sjfv 980169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 981177867Sjfv ret_val = phy->ops.write_reg(hw, 982169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 983169240Sjfv data); 984169240Sjfv } 985169240Sjfv 986169240Sjfvout: 987169240Sjfv return ret_val; 988169240Sjfv} 989169240Sjfv 990169240Sjfv/** 991173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 992173788Sjfv * @hw: pointer to the HW structure 993173788Sjfv * @bank: pointer to the variable that returns the active bank 994173788Sjfv * 995173788Sjfv * Reads signature byte from the NVM using the flash access registers. 996173788Sjfv **/ 997177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 998173788Sjfv{ 999173788Sjfv s32 ret_val = E1000_SUCCESS; 1000178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1001178523Sjfv /* flash bank size is in words */ 1002178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1003178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1004178523Sjfv u8 bank_high_byte = 0; 1005178523Sjfv 1006178523Sjfv if (hw->mac.type != e1000_ich10lan) { 1007178523Sjfv if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) 1008178523Sjfv *bank = 1; 1009178523Sjfv else 1010178523Sjfv *bank = 0; 1011185353Sjfv } else { 1012178523Sjfv /* 1013178523Sjfv * Make sure the signature for bank 0 is valid, 1014178523Sjfv * if not check for bank1 1015178523Sjfv */ 1016178523Sjfv e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte); 1017178523Sjfv if ((bank_high_byte & 0xC0) == 0x80) { 1018178523Sjfv *bank = 0; 1019178523Sjfv } else { 1020178523Sjfv /* 1021178523Sjfv * find if segment 1 is valid by verifying 1022178523Sjfv * bit 15:14 = 10b in word 0x13 1023178523Sjfv */ 1024178523Sjfv e1000_read_flash_byte_ich8lan(hw, 1025178523Sjfv act_offset + bank1_offset, 1026178523Sjfv &bank_high_byte); 1027185353Sjfv 1028178523Sjfv /* bank1 has a valid signature equivalent to SEC1V */ 1029178523Sjfv if ((bank_high_byte & 0xC0) == 0x80) { 1030178523Sjfv *bank = 1; 1031178523Sjfv } else { 1032178523Sjfv DEBUGOUT("ERROR: EEPROM not present\n"); 1033178523Sjfv ret_val = -E1000_ERR_NVM; 1034178523Sjfv } 1035178523Sjfv } 1036178523Sjfv } 1037185353Sjfv 1038173788Sjfv return ret_val; 1039173788Sjfv} 1040173788Sjfv 1041173788Sjfv/** 1042169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1043169589Sjfv * @hw: pointer to the HW structure 1044169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 1045169589Sjfv * @words: Size of data to read in words 1046169589Sjfv * @data: Pointer to the word(s) to read at offset. 1047169240Sjfv * 1048169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 1049169240Sjfv **/ 1050177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1051173788Sjfv u16 *data) 1052169240Sjfv{ 1053169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1054185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1055169240Sjfv u32 act_offset; 1056169240Sjfv s32 ret_val = E1000_SUCCESS; 1057173788Sjfv u32 bank = 0; 1058169240Sjfv u16 i, word; 1059169240Sjfv 1060169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 1061169240Sjfv 1062169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1063169240Sjfv (words == 0)) { 1064169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1065169240Sjfv ret_val = -E1000_ERR_NVM; 1066169240Sjfv goto out; 1067169240Sjfv } 1068169240Sjfv 1069177867Sjfv ret_val = nvm->ops.acquire(hw); 1070169240Sjfv if (ret_val) 1071169240Sjfv goto out; 1072169240Sjfv 1073173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1074173788Sjfv if (ret_val != E1000_SUCCESS) 1075173788Sjfv goto out; 1076173788Sjfv 1077173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 1078169240Sjfv act_offset += offset; 1079169240Sjfv 1080169240Sjfv for (i = 0; i < words; i++) { 1081173788Sjfv if ((dev_spec->shadow_ram) && 1082173788Sjfv (dev_spec->shadow_ram[offset+i].modified)) { 1083169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 1084169240Sjfv } else { 1085169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 1086169240Sjfv act_offset + i, 1087169240Sjfv &word); 1088169240Sjfv if (ret_val) 1089169240Sjfv break; 1090169240Sjfv data[i] = word; 1091169240Sjfv } 1092169240Sjfv } 1093169240Sjfv 1094177867Sjfv nvm->ops.release(hw); 1095169240Sjfv 1096169240Sjfvout: 1097169240Sjfv return ret_val; 1098169240Sjfv} 1099169240Sjfv 1100169240Sjfv/** 1101169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 1102169589Sjfv * @hw: pointer to the HW structure 1103169240Sjfv * 1104169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 1105169240Sjfv * can be started. 1106169240Sjfv **/ 1107173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1108169240Sjfv{ 1109169240Sjfv union ich8_hws_flash_status hsfsts; 1110169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1111169240Sjfv s32 i = 0; 1112169240Sjfv 1113169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1114169240Sjfv 1115169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1116169240Sjfv 1117169240Sjfv /* Check if the flash descriptor is valid */ 1118169240Sjfv if (hsfsts.hsf_status.fldesvalid == 0) { 1119169240Sjfv DEBUGOUT("Flash descriptor invalid. " 1120169240Sjfv "SW Sequencing must be used."); 1121169240Sjfv goto out; 1122169240Sjfv } 1123169240Sjfv 1124169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 1125169240Sjfv hsfsts.hsf_status.flcerr = 1; 1126169240Sjfv hsfsts.hsf_status.dael = 1; 1127169240Sjfv 1128169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1129169240Sjfv 1130173788Sjfv /* 1131173788Sjfv * Either we should have a hardware SPI cycle in progress 1132169240Sjfv * bit to check against, in order to start a new cycle or 1133169240Sjfv * FDONE bit should be changed in the hardware so that it 1134176667Sjfv * is 1 after hardware reset, which can then be used as an 1135169240Sjfv * indication whether a cycle is in progress or has been 1136169240Sjfv * completed. 1137169240Sjfv */ 1138169240Sjfv 1139169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1140173788Sjfv /* 1141173788Sjfv * There is no cycle running at present, 1142173788Sjfv * so we can start a cycle. 1143173788Sjfv * Begin by setting Flash Cycle Done. 1144173788Sjfv */ 1145169240Sjfv hsfsts.hsf_status.flcdone = 1; 1146169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1147169240Sjfv ret_val = E1000_SUCCESS; 1148169240Sjfv } else { 1149173788Sjfv /* 1150173788Sjfv * Otherwise poll for sometime so the current 1151173788Sjfv * cycle has a chance to end before giving up. 1152173788Sjfv */ 1153169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1154169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1155169240Sjfv ICH_FLASH_HSFSTS); 1156169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 1157169240Sjfv ret_val = E1000_SUCCESS; 1158169240Sjfv break; 1159169240Sjfv } 1160169240Sjfv usec_delay(1); 1161169240Sjfv } 1162169240Sjfv if (ret_val == E1000_SUCCESS) { 1163173788Sjfv /* 1164173788Sjfv * Successful in waiting for previous cycle to timeout, 1165173788Sjfv * now set the Flash Cycle Done. 1166173788Sjfv */ 1167169240Sjfv hsfsts.hsf_status.flcdone = 1; 1168185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 1169169240Sjfv hsfsts.regval); 1170169240Sjfv } else { 1171169240Sjfv DEBUGOUT("Flash controller busy, cannot get access"); 1172169240Sjfv } 1173169240Sjfv } 1174169240Sjfv 1175169240Sjfvout: 1176169240Sjfv return ret_val; 1177169240Sjfv} 1178169240Sjfv 1179169240Sjfv/** 1180169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1181169589Sjfv * @hw: pointer to the HW structure 1182169589Sjfv * @timeout: maximum time to wait for completion 1183169240Sjfv * 1184169240Sjfv * This function starts a flash cycle and waits for its completion. 1185169240Sjfv **/ 1186173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1187169240Sjfv{ 1188169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1189169240Sjfv union ich8_hws_flash_status hsfsts; 1190169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1191169240Sjfv u32 i = 0; 1192169240Sjfv 1193169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1194169240Sjfv 1195169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1196169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1197169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 1198169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1199169240Sjfv 1200169240Sjfv /* wait till FDONE bit is set to 1 */ 1201169240Sjfv do { 1202169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1203169240Sjfv if (hsfsts.hsf_status.flcdone == 1) 1204169240Sjfv break; 1205169240Sjfv usec_delay(1); 1206169240Sjfv } while (i++ < timeout); 1207169240Sjfv 1208169240Sjfv if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1209169240Sjfv ret_val = E1000_SUCCESS; 1210169240Sjfv 1211169240Sjfv return ret_val; 1212169240Sjfv} 1213169240Sjfv 1214169240Sjfv/** 1215169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 1216169589Sjfv * @hw: pointer to the HW structure 1217169589Sjfv * @offset: offset to data location 1218169589Sjfv * @data: pointer to the location for storing the data 1219169240Sjfv * 1220169240Sjfv * Reads the flash word at offset into data. Offset is converted 1221169240Sjfv * to bytes before read. 1222169240Sjfv **/ 1223177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1224173788Sjfv u16 *data) 1225169240Sjfv{ 1226169240Sjfv s32 ret_val; 1227169240Sjfv 1228169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1229169240Sjfv 1230173788Sjfv if (!data) { 1231169240Sjfv ret_val = -E1000_ERR_NVM; 1232169240Sjfv goto out; 1233169240Sjfv } 1234169240Sjfv 1235169240Sjfv /* Must convert offset into bytes. */ 1236169240Sjfv offset <<= 1; 1237169240Sjfv 1238169240Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1239169240Sjfv 1240169240Sjfvout: 1241169240Sjfv return ret_val; 1242169240Sjfv} 1243169240Sjfv 1244169240Sjfv/** 1245178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 1246178523Sjfv * @hw: pointer to the HW structure 1247178523Sjfv * @offset: The offset of the byte to read. 1248178523Sjfv * @data: Pointer to a byte to store the value read. 1249178523Sjfv * 1250178523Sjfv * Reads a single byte from the NVM using the flash access registers. 1251178523Sjfv **/ 1252178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1253185353Sjfv u8 *data) 1254178523Sjfv{ 1255178523Sjfv s32 ret_val = E1000_SUCCESS; 1256178523Sjfv u16 word = 0; 1257178523Sjfv 1258178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1259178523Sjfv if (ret_val) 1260178523Sjfv goto out; 1261178523Sjfv 1262178523Sjfv *data = (u8)word; 1263178523Sjfv 1264178523Sjfvout: 1265178523Sjfv return ret_val; 1266178523Sjfv} 1267178523Sjfv 1268178523Sjfv/** 1269169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1270169589Sjfv * @hw: pointer to the HW structure 1271169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 1272169589Sjfv * @size: Size of data to read, 1=byte 2=word 1273169589Sjfv * @data: Pointer to the word to store the value read. 1274169240Sjfv * 1275169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 1276169240Sjfv **/ 1277173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1278185353Sjfv u8 size, u16 *data) 1279169240Sjfv{ 1280169240Sjfv union ich8_hws_flash_status hsfsts; 1281169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1282169240Sjfv u32 flash_linear_addr; 1283169240Sjfv u32 flash_data = 0; 1284169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1285169240Sjfv u8 count = 0; 1286169240Sjfv 1287169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1288169240Sjfv 1289173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1290169240Sjfv goto out; 1291169240Sjfv 1292169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1293169240Sjfv hw->nvm.flash_base_addr; 1294169240Sjfv 1295169240Sjfv do { 1296169240Sjfv usec_delay(1); 1297169240Sjfv /* Steps */ 1298169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1299169240Sjfv if (ret_val != E1000_SUCCESS) 1300169240Sjfv break; 1301169240Sjfv 1302169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1303169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1304169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 1305169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1306169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1307169240Sjfv 1308169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1309169240Sjfv 1310169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1311169240Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 1312169240Sjfv 1313173788Sjfv /* 1314173788Sjfv * Check if FCERR is set to 1, if set to 1, clear it 1315169240Sjfv * and try the whole sequence a few more times, else 1316169240Sjfv * read in (shift in) the Flash Data0, the order is 1317173788Sjfv * least significant byte first msb to lsb 1318173788Sjfv */ 1319169240Sjfv if (ret_val == E1000_SUCCESS) { 1320169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1321185353Sjfv if (size == 1) 1322169240Sjfv *data = (u8)(flash_data & 0x000000FF); 1323185353Sjfv else if (size == 2) 1324169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 1325169240Sjfv break; 1326169240Sjfv } else { 1327173788Sjfv /* 1328173788Sjfv * If we've gotten here, then things are probably 1329169240Sjfv * completely hosed, but if the error condition is 1330169240Sjfv * detected, it won't hurt to give it another try... 1331169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1332169240Sjfv */ 1333169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1334169240Sjfv ICH_FLASH_HSFSTS); 1335169240Sjfv if (hsfsts.hsf_status.flcerr == 1) { 1336169240Sjfv /* Repeat for some time before giving up. */ 1337169240Sjfv continue; 1338169240Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 1339169240Sjfv DEBUGOUT("Timeout error - flash cycle " 1340169240Sjfv "did not complete."); 1341169240Sjfv break; 1342169240Sjfv } 1343169240Sjfv } 1344169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1345169240Sjfv 1346169240Sjfvout: 1347169240Sjfv return ret_val; 1348169240Sjfv} 1349169240Sjfv 1350169240Sjfv/** 1351169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1352169589Sjfv * @hw: pointer to the HW structure 1353169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 1354169589Sjfv * @words: Size of data to write in words 1355169589Sjfv * @data: Pointer to the word(s) to write at offset. 1356169240Sjfv * 1357169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 1358169240Sjfv **/ 1359177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1360173788Sjfv u16 *data) 1361169240Sjfv{ 1362169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1363185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1364169240Sjfv s32 ret_val = E1000_SUCCESS; 1365169240Sjfv u16 i; 1366169240Sjfv 1367169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 1368169240Sjfv 1369169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1370169240Sjfv (words == 0)) { 1371169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 1372169240Sjfv ret_val = -E1000_ERR_NVM; 1373169240Sjfv goto out; 1374169240Sjfv } 1375169240Sjfv 1376177867Sjfv ret_val = nvm->ops.acquire(hw); 1377169240Sjfv if (ret_val) 1378169240Sjfv goto out; 1379169240Sjfv 1380169240Sjfv for (i = 0; i < words; i++) { 1381169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 1382169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 1383169240Sjfv } 1384169240Sjfv 1385177867Sjfv nvm->ops.release(hw); 1386169240Sjfv 1387169240Sjfvout: 1388169240Sjfv return ret_val; 1389169240Sjfv} 1390169240Sjfv 1391169240Sjfv/** 1392169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1393169589Sjfv * @hw: pointer to the HW structure 1394169240Sjfv * 1395169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 1396169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 1397169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 1398169240Sjfv * checking for the modified bit and writing only the pending changes. 1399176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 1400169240Sjfv * future writes. 1401169240Sjfv **/ 1402177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1403169240Sjfv{ 1404169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1405185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1406173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1407169240Sjfv s32 ret_val; 1408169240Sjfv u16 data; 1409169240Sjfv 1410169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1411169240Sjfv 1412169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 1413169240Sjfv if (ret_val) 1414169240Sjfv goto out; 1415169240Sjfv 1416169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 1417169240Sjfv goto out; 1418169240Sjfv 1419177867Sjfv ret_val = nvm->ops.acquire(hw); 1420169240Sjfv if (ret_val) 1421169240Sjfv goto out; 1422169240Sjfv 1423173788Sjfv /* 1424173788Sjfv * We're writing to the opposite bank so if we're on bank 1, 1425169240Sjfv * write to bank 0 etc. We also need to erase the segment that 1426173788Sjfv * is going to be written 1427173788Sjfv */ 1428173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1429173788Sjfv if (ret_val != E1000_SUCCESS) 1430173788Sjfv goto out; 1431173788Sjfv 1432173788Sjfv if (bank == 0) { 1433169240Sjfv new_bank_offset = nvm->flash_bank_size; 1434169240Sjfv old_bank_offset = 0; 1435169240Sjfv e1000_erase_flash_bank_ich8lan(hw, 1); 1436169240Sjfv } else { 1437169240Sjfv old_bank_offset = nvm->flash_bank_size; 1438169240Sjfv new_bank_offset = 0; 1439169240Sjfv e1000_erase_flash_bank_ich8lan(hw, 0); 1440169240Sjfv } 1441169240Sjfv 1442169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1443173788Sjfv /* 1444173788Sjfv * Determine whether to write the value stored 1445169240Sjfv * in the other NVM bank or a modified value stored 1446173788Sjfv * in the shadow RAM 1447173788Sjfv */ 1448173788Sjfv if (dev_spec->shadow_ram[i].modified) { 1449169240Sjfv data = dev_spec->shadow_ram[i].value; 1450169240Sjfv } else { 1451169240Sjfv e1000_read_flash_word_ich8lan(hw, 1452169240Sjfv i + old_bank_offset, 1453169240Sjfv &data); 1454169240Sjfv } 1455169240Sjfv 1456173788Sjfv /* 1457173788Sjfv * If the word is 0x13, then make sure the signature bits 1458169240Sjfv * (15:14) are 11b until the commit has completed. 1459169240Sjfv * This will allow us to write 10b which indicates the 1460169240Sjfv * signature is valid. We want to do this after the write 1461169240Sjfv * has completed so that we don't mark the segment valid 1462173788Sjfv * while the write is still in progress 1463173788Sjfv */ 1464169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 1465169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 1466169240Sjfv 1467169240Sjfv /* Convert offset to bytes. */ 1468169240Sjfv act_offset = (i + new_bank_offset) << 1; 1469169240Sjfv 1470169240Sjfv usec_delay(100); 1471169240Sjfv /* Write the bytes to the new bank. */ 1472169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1473169240Sjfv act_offset, 1474169240Sjfv (u8)data); 1475169240Sjfv if (ret_val) 1476169240Sjfv break; 1477169240Sjfv 1478169240Sjfv usec_delay(100); 1479169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1480169240Sjfv act_offset + 1, 1481169240Sjfv (u8)(data >> 8)); 1482169240Sjfv if (ret_val) 1483169240Sjfv break; 1484169240Sjfv } 1485169240Sjfv 1486173788Sjfv /* 1487173788Sjfv * Don't bother writing the segment valid bits if sector 1488173788Sjfv * programming failed. 1489173788Sjfv */ 1490169240Sjfv if (ret_val) { 1491169240Sjfv DEBUGOUT("Flash commit failed.\n"); 1492177867Sjfv nvm->ops.release(hw); 1493169240Sjfv goto out; 1494169240Sjfv } 1495169240Sjfv 1496173788Sjfv /* 1497173788Sjfv * Finally validate the new segment by setting bit 15:14 1498169240Sjfv * to 10b in word 0x13 , this can be done without an 1499169240Sjfv * erase as well since these bits are 11 to start with 1500173788Sjfv * and we need to change bit 14 to 0b 1501173788Sjfv */ 1502169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1503169240Sjfv e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1504169240Sjfv data &= 0xBFFF; 1505169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1506169240Sjfv act_offset * 2 + 1, 1507169240Sjfv (u8)(data >> 8)); 1508169240Sjfv if (ret_val) { 1509177867Sjfv nvm->ops.release(hw); 1510169240Sjfv goto out; 1511169240Sjfv } 1512169240Sjfv 1513173788Sjfv /* 1514173788Sjfv * And invalidate the previously valid segment by setting 1515169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 1516169240Sjfv * done without an erase because flash erase sets all bits 1517173788Sjfv * to 1's. We can write 1's to 0's without an erase 1518173788Sjfv */ 1519169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1520169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1521169240Sjfv if (ret_val) { 1522177867Sjfv nvm->ops.release(hw); 1523169240Sjfv goto out; 1524169240Sjfv } 1525169240Sjfv 1526169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 1527169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1528169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 1529169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 1530169240Sjfv } 1531169240Sjfv 1532177867Sjfv nvm->ops.release(hw); 1533169240Sjfv 1534173788Sjfv /* 1535173788Sjfv * Reload the EEPROM, or else modifications will not appear 1536169240Sjfv * until after the next adapter reset. 1537169240Sjfv */ 1538177867Sjfv nvm->ops.reload(hw); 1539169240Sjfv msec_delay(10); 1540169240Sjfv 1541169240Sjfvout: 1542169240Sjfv return ret_val; 1543169240Sjfv} 1544169240Sjfv 1545169240Sjfv/** 1546169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1547169589Sjfv * @hw: pointer to the HW structure 1548169240Sjfv * 1549169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1550185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 1551185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 1552169240Sjfv **/ 1553177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1554169240Sjfv{ 1555169240Sjfv s32 ret_val = E1000_SUCCESS; 1556169240Sjfv u16 data; 1557169240Sjfv 1558169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1559169240Sjfv 1560173788Sjfv /* 1561173788Sjfv * Read 0x19 and check bit 6. If this bit is 0, the checksum 1562169240Sjfv * needs to be fixed. This bit is an indication that the NVM 1563169240Sjfv * was prepared by OEM software and did not calculate the 1564169240Sjfv * checksum...a likely scenario. 1565169240Sjfv */ 1566177867Sjfv ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1567169240Sjfv if (ret_val) 1568169240Sjfv goto out; 1569169240Sjfv 1570169240Sjfv if ((data & 0x40) == 0) { 1571169240Sjfv data |= 0x40; 1572177867Sjfv ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1573169240Sjfv if (ret_val) 1574169240Sjfv goto out; 1575177867Sjfv ret_val = hw->nvm.ops.update(hw); 1576169240Sjfv if (ret_val) 1577169240Sjfv goto out; 1578169240Sjfv } 1579169240Sjfv 1580169240Sjfv ret_val = e1000_validate_nvm_checksum_generic(hw); 1581169240Sjfv 1582169240Sjfvout: 1583169240Sjfv return ret_val; 1584169240Sjfv} 1585169240Sjfv 1586169240Sjfv/** 1587169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1588169589Sjfv * @hw: pointer to the HW structure 1589169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 1590169589Sjfv * @size: Size of data to read, 1=byte 2=word 1591169589Sjfv * @data: The byte(s) to write to the NVM. 1592169240Sjfv * 1593169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 1594169240Sjfv **/ 1595173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1596173788Sjfv u8 size, u16 data) 1597169240Sjfv{ 1598169240Sjfv union ich8_hws_flash_status hsfsts; 1599169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1600169240Sjfv u32 flash_linear_addr; 1601169240Sjfv u32 flash_data = 0; 1602169240Sjfv s32 ret_val = -E1000_ERR_NVM; 1603169240Sjfv u8 count = 0; 1604169240Sjfv 1605169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 1606169240Sjfv 1607169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 1608169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 1609169240Sjfv goto out; 1610169240Sjfv 1611169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1612169240Sjfv hw->nvm.flash_base_addr; 1613169240Sjfv 1614169240Sjfv do { 1615169240Sjfv usec_delay(1); 1616169240Sjfv /* Steps */ 1617169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1618169240Sjfv if (ret_val != E1000_SUCCESS) 1619169240Sjfv break; 1620169240Sjfv 1621169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1622169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1623185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 1624169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1625169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1626169240Sjfv 1627169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1628169240Sjfv 1629169240Sjfv if (size == 1) 1630169240Sjfv flash_data = (u32)data & 0x00FF; 1631169240Sjfv else 1632169240Sjfv flash_data = (u32)data; 1633169240Sjfv 1634169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1635169240Sjfv 1636173788Sjfv /* 1637173788Sjfv * check if FCERR is set to 1 , if set to 1, clear it 1638173788Sjfv * and try the whole sequence a few more times else done 1639173788Sjfv */ 1640169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1641169240Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1642185353Sjfv if (ret_val == E1000_SUCCESS) 1643169240Sjfv break; 1644185353Sjfv 1645185353Sjfv /* 1646185353Sjfv * If we're here, then things are most likely 1647185353Sjfv * completely hosed, but if the error condition 1648185353Sjfv * is detected, it won't hurt to give it another 1649185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1650185353Sjfv */ 1651185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1652185353Sjfv if (hsfsts.hsf_status.flcerr == 1) { 1653185353Sjfv /* Repeat for some time before giving up. */ 1654185353Sjfv continue; 1655185353Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 1656185353Sjfv DEBUGOUT("Timeout error - flash cycle " 1657185353Sjfv "did not complete."); 1658185353Sjfv break; 1659169240Sjfv } 1660169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1661169240Sjfv 1662169240Sjfvout: 1663169240Sjfv return ret_val; 1664169240Sjfv} 1665169240Sjfv 1666169240Sjfv/** 1667169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1668169589Sjfv * @hw: pointer to the HW structure 1669169589Sjfv * @offset: The index of the byte to read. 1670169589Sjfv * @data: The byte to write to the NVM. 1671169240Sjfv * 1672169240Sjfv * Writes a single byte to the NVM using the flash access registers. 1673169240Sjfv **/ 1674177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1675173788Sjfv u8 data) 1676169240Sjfv{ 1677169240Sjfv u16 word = (u16)data; 1678169240Sjfv 1679169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1680169240Sjfv 1681169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1682169240Sjfv} 1683169240Sjfv 1684169240Sjfv/** 1685169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1686169589Sjfv * @hw: pointer to the HW structure 1687169589Sjfv * @offset: The offset of the byte to write. 1688169589Sjfv * @byte: The byte to write to the NVM. 1689169240Sjfv * 1690169240Sjfv * Writes a single byte to the NVM using the flash access registers. 1691169240Sjfv * Goes through a retry algorithm before giving up. 1692169240Sjfv **/ 1693176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1694176667Sjfv u32 offset, u8 byte) 1695169240Sjfv{ 1696169240Sjfv s32 ret_val; 1697169240Sjfv u16 program_retries; 1698169240Sjfv 1699169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1700169240Sjfv 1701169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1702173788Sjfv if (ret_val == E1000_SUCCESS) 1703169240Sjfv goto out; 1704169240Sjfv 1705169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 1706169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1707169240Sjfv usec_delay(100); 1708169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1709169240Sjfv if (ret_val == E1000_SUCCESS) 1710169240Sjfv break; 1711169240Sjfv } 1712169240Sjfv if (program_retries == 100) { 1713169240Sjfv ret_val = -E1000_ERR_NVM; 1714169240Sjfv goto out; 1715169240Sjfv } 1716169240Sjfv 1717169240Sjfvout: 1718169240Sjfv return ret_val; 1719169240Sjfv} 1720169240Sjfv 1721169240Sjfv/** 1722169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1723169589Sjfv * @hw: pointer to the HW structure 1724169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 1725169240Sjfv * 1726169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1727169240Sjfv * bank N is 4096 * N + flash_reg_addr. 1728169240Sjfv **/ 1729177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1730169240Sjfv{ 1731169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1732169240Sjfv union ich8_hws_flash_status hsfsts; 1733169240Sjfv union ich8_hws_flash_ctrl hsflctl; 1734169240Sjfv u32 flash_linear_addr; 1735173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 1736173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 1737185353Sjfv s32 ret_val = E1000_SUCCESS; 1738185353Sjfv s32 count = 0; 1739185353Sjfv s32 j, iteration, sector_size; 1740169240Sjfv 1741169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1742169240Sjfv 1743169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1744169240Sjfv 1745173788Sjfv /* 1746173788Sjfv * Determine HW Sector size: Read BERASE bits of hw flash status 1747173788Sjfv * register 1748173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 1749169240Sjfv * consecutive sectors. The start index for the nth Hw sector 1750169240Sjfv * can be calculated as = bank * 4096 + n * 256 1751169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1752169240Sjfv * The start index for the nth Hw sector can be calculated 1753169240Sjfv * as = bank * 4096 1754169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1755169240Sjfv * (ich9 only, otherwise error condition) 1756169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1757169240Sjfv */ 1758169240Sjfv switch (hsfsts.hsf_status.berasesz) { 1759169240Sjfv case 0: 1760169240Sjfv /* Hw sector size 256 */ 1761169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 1762169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1763169240Sjfv break; 1764169240Sjfv case 1: 1765169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 1766169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1767169240Sjfv break; 1768169240Sjfv case 2: 1769169240Sjfv if (hw->mac.type == e1000_ich9lan) { 1770169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 1771169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1772169240Sjfv } else { 1773169240Sjfv ret_val = -E1000_ERR_NVM; 1774169240Sjfv goto out; 1775169240Sjfv } 1776169240Sjfv break; 1777169240Sjfv case 3: 1778169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 1779169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1780169240Sjfv break; 1781169240Sjfv default: 1782169240Sjfv ret_val = -E1000_ERR_NVM; 1783169240Sjfv goto out; 1784169240Sjfv } 1785169240Sjfv 1786169240Sjfv /* Start with the base address, then add the sector offset. */ 1787169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 1788169240Sjfv flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1789169240Sjfv 1790169240Sjfv for (j = 0; j < iteration ; j++) { 1791169240Sjfv do { 1792169240Sjfv /* Steps */ 1793169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 1794169240Sjfv if (ret_val) 1795169240Sjfv goto out; 1796169240Sjfv 1797173788Sjfv /* 1798173788Sjfv * Write a value 11 (block Erase) in Flash 1799173788Sjfv * Cycle field in hw flash control 1800173788Sjfv */ 1801169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1802169240Sjfv ICH_FLASH_HSFCTL); 1803169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1804185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 1805169240Sjfv hsflctl.regval); 1806169240Sjfv 1807173788Sjfv /* 1808173788Sjfv * Write the last 24 bits of an index within the 1809169240Sjfv * block into Flash Linear address field in Flash 1810169240Sjfv * Address. 1811169240Sjfv */ 1812169240Sjfv flash_linear_addr += (j * sector_size); 1813185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 1814169240Sjfv flash_linear_addr); 1815169240Sjfv 1816169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 1817169240Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1818185353Sjfv if (ret_val == E1000_SUCCESS) 1819169240Sjfv break; 1820185353Sjfv 1821185353Sjfv /* 1822185353Sjfv * Check if FCERR is set to 1. If 1, 1823185353Sjfv * clear it and try the whole sequence 1824185353Sjfv * a few more times else Done 1825185353Sjfv */ 1826185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1827185353Sjfv ICH_FLASH_HSFSTS); 1828185353Sjfv if (hsfsts.hsf_status.flcerr == 1) 1829185353Sjfv /* repeat for some time before giving up */ 1830185353Sjfv continue; 1831185353Sjfv else if (hsfsts.hsf_status.flcdone == 0) 1832185353Sjfv goto out; 1833169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1834169240Sjfv } 1835169240Sjfv 1836169240Sjfvout: 1837169240Sjfv return ret_val; 1838169240Sjfv} 1839169240Sjfv 1840169240Sjfv/** 1841169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 1842169589Sjfv * @hw: pointer to the HW structure 1843169589Sjfv * @data: Pointer to the LED settings 1844169240Sjfv * 1845169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 1846169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 1847169240Sjfv * setting. 1848169240Sjfv **/ 1849177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1850169240Sjfv{ 1851169240Sjfv s32 ret_val; 1852169240Sjfv 1853169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1854169240Sjfv 1855177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1856169240Sjfv if (ret_val) { 1857169240Sjfv DEBUGOUT("NVM Read Error\n"); 1858169240Sjfv goto out; 1859169240Sjfv } 1860169240Sjfv 1861169240Sjfv if (*data == ID_LED_RESERVED_0000 || 1862169240Sjfv *data == ID_LED_RESERVED_FFFF) 1863169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 1864169240Sjfv 1865169240Sjfvout: 1866169240Sjfv return ret_val; 1867169240Sjfv} 1868169240Sjfv 1869169240Sjfv/** 1870169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1871169589Sjfv * @hw: pointer to the HW structure 1872169240Sjfv * 1873169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1874169240Sjfv * register, so the the bus width is hard coded. 1875169240Sjfv **/ 1876177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1877169240Sjfv{ 1878169240Sjfv struct e1000_bus_info *bus = &hw->bus; 1879169240Sjfv s32 ret_val; 1880169240Sjfv 1881169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1882169240Sjfv 1883169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 1884169240Sjfv 1885173788Sjfv /* 1886173788Sjfv * ICH devices are "PCI Express"-ish. They have 1887169240Sjfv * a configuration space, but do not contain 1888169240Sjfv * PCI Express Capability registers, so bus width 1889169240Sjfv * must be hardcoded. 1890169240Sjfv */ 1891169240Sjfv if (bus->width == e1000_bus_width_unknown) 1892169240Sjfv bus->width = e1000_bus_width_pcie_x1; 1893169240Sjfv 1894169240Sjfv return ret_val; 1895169240Sjfv} 1896169240Sjfv 1897169240Sjfv/** 1898169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 1899169589Sjfv * @hw: pointer to the HW structure 1900169240Sjfv * 1901169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 1902169240Sjfv * MAC. 1903169240Sjfv **/ 1904177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1905169240Sjfv{ 1906169240Sjfv u32 ctrl, icr, kab; 1907169240Sjfv s32 ret_val; 1908169240Sjfv 1909169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 1910169240Sjfv 1911173788Sjfv /* 1912173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 1913169240Sjfv * on the last TLP read/write transaction when MAC is reset. 1914169240Sjfv */ 1915169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1916185353Sjfv if (ret_val) 1917169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1918169240Sjfv 1919169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 1920169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1921169240Sjfv 1922173788Sjfv /* 1923173788Sjfv * Disable the Transmit and Receive units. Then delay to allow 1924169240Sjfv * any pending transactions to complete before we hit the MAC 1925169240Sjfv * with the global reset. 1926169240Sjfv */ 1927169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1928169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1929169240Sjfv E1000_WRITE_FLUSH(hw); 1930169240Sjfv 1931169240Sjfv msec_delay(10); 1932169240Sjfv 1933169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1934169240Sjfv if (hw->mac.type == e1000_ich8lan) { 1935169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 1936169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1937169240Sjfv /* Set Packet Buffer Size to 16k. */ 1938169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 1939169240Sjfv } 1940169240Sjfv 1941169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1942169240Sjfv 1943177867Sjfv if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 1944173788Sjfv /* 1945173788Sjfv * PHY HW reset requires MAC CORE reset at the same 1946169240Sjfv * time to make sure the interface between MAC and the 1947169240Sjfv * external PHY is reset. 1948169240Sjfv */ 1949169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 1950169240Sjfv } 1951169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 1952185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 1953169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 1954169240Sjfv msec_delay(20); 1955169240Sjfv 1956169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1957169240Sjfv if (ret_val) { 1958169589Sjfv /* 1959169240Sjfv * When auto config read does not complete, do not 1960169240Sjfv * return with an error. This can happen in situations 1961169240Sjfv * where there is no eeprom and prevents getting link. 1962169240Sjfv */ 1963169240Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 1964169240Sjfv } 1965169240Sjfv 1966169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1967169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1968169240Sjfv 1969169240Sjfv kab = E1000_READ_REG(hw, E1000_KABGTXD); 1970169240Sjfv kab |= E1000_KABGTXD_BGSQLBIAS; 1971169240Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 1972169240Sjfv 1973169240Sjfv return ret_val; 1974169240Sjfv} 1975169240Sjfv 1976169240Sjfv/** 1977169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 1978169589Sjfv * @hw: pointer to the HW structure 1979169240Sjfv * 1980169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 1981169240Sjfv * - initialize hardware bits 1982169240Sjfv * - initialize LED identification 1983169240Sjfv * - setup receive address registers 1984169240Sjfv * - setup flow control 1985176667Sjfv * - setup transmit descriptors 1986169240Sjfv * - clear statistics 1987169240Sjfv **/ 1988177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 1989169240Sjfv{ 1990169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1991169240Sjfv u32 ctrl_ext, txdctl, snoop; 1992169240Sjfv s32 ret_val; 1993169240Sjfv u16 i; 1994169240Sjfv 1995169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 1996169240Sjfv 1997169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 1998169240Sjfv 1999169240Sjfv /* Initialize identification LED */ 2000169240Sjfv ret_val = e1000_id_led_init_generic(hw); 2001169240Sjfv if (ret_val) { 2002169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 2003173788Sjfv /* This is not fatal and we should not stop init due to this */ 2004169240Sjfv } 2005169240Sjfv 2006169240Sjfv /* Setup the receive address. */ 2007169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2008169240Sjfv 2009169240Sjfv /* Zero out the Multicast HASH table */ 2010169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 2011169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 2012169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2013169240Sjfv 2014169240Sjfv /* Setup link and flow control */ 2015177867Sjfv ret_val = mac->ops.setup_link(hw); 2016169240Sjfv 2017169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 2018173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2019169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2020169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2021169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2022169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2023173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2024173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2025169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2026169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 2027169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2028169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2029173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2030169240Sjfv 2031173788Sjfv /* 2032173788Sjfv * ICH8 has opposite polarity of no_snoop bits. 2033173788Sjfv * By default, we should use snoop behavior. 2034173788Sjfv */ 2035169240Sjfv if (mac->type == e1000_ich8lan) 2036169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 2037169240Sjfv else 2038169240Sjfv snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2039169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 2040169240Sjfv 2041169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2042169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2043169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2044169240Sjfv 2045173788Sjfv /* 2046173788Sjfv * Clear all of the statistics registers (clear on read). It is 2047169240Sjfv * important that we do this after we have tried to establish link 2048169240Sjfv * because the symbol error count will increment wildly if there 2049169240Sjfv * is no link. 2050169240Sjfv */ 2051169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 2052169240Sjfv 2053169240Sjfv return ret_val; 2054169240Sjfv} 2055169240Sjfv/** 2056169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2057169589Sjfv * @hw: pointer to the HW structure 2058169240Sjfv * 2059169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 2060169240Sjfv * hardware for transmit and receive. 2061169240Sjfv **/ 2062173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2063169240Sjfv{ 2064169240Sjfv u32 reg; 2065169240Sjfv 2066169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2067169240Sjfv 2068169240Sjfv /* Extended Device Control */ 2069169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2070169240Sjfv reg |= (1 << 22); 2071169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2072169240Sjfv 2073169240Sjfv /* Transmit Descriptor Control 0 */ 2074173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2075169240Sjfv reg |= (1 << 22); 2076173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2077169240Sjfv 2078169240Sjfv /* Transmit Descriptor Control 1 */ 2079173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2080169240Sjfv reg |= (1 << 22); 2081173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2082169240Sjfv 2083169240Sjfv /* Transmit Arbitration Control 0 */ 2084173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 2085169240Sjfv if (hw->mac.type == e1000_ich8lan) 2086169240Sjfv reg |= (1 << 28) | (1 << 29); 2087169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2088173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2089169240Sjfv 2090169240Sjfv /* Transmit Arbitration Control 1 */ 2091173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 2092169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2093169240Sjfv reg &= ~(1 << 28); 2094169240Sjfv else 2095169240Sjfv reg |= (1 << 28); 2096169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 2097173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2098169240Sjfv 2099169240Sjfv /* Device Status */ 2100169240Sjfv if (hw->mac.type == e1000_ich8lan) { 2101169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 2102169240Sjfv reg &= ~(1 << 31); 2103169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 2104169240Sjfv } 2105169240Sjfv 2106169240Sjfv return; 2107169240Sjfv} 2108169240Sjfv 2109169240Sjfv/** 2110169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 2111169589Sjfv * @hw: pointer to the HW structure 2112169240Sjfv * 2113169240Sjfv * Determines which flow control settings to use, then configures flow 2114169240Sjfv * control. Calls the appropriate media-specific link configuration 2115169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 2116169240Sjfv * should be established. Assumes the hardware has previously been reset 2117169240Sjfv * and the transmitter and receiver are not enabled. 2118169240Sjfv **/ 2119177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2120169240Sjfv{ 2121169240Sjfv s32 ret_val = E1000_SUCCESS; 2122169240Sjfv 2123169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 2124169240Sjfv 2125177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 2126169240Sjfv goto out; 2127169240Sjfv 2128173788Sjfv /* 2129173788Sjfv * ICH parts do not have a word in the NVM to determine 2130169240Sjfv * the default flow control setting, so we explicitly 2131169240Sjfv * set it to full. 2132169240Sjfv */ 2133185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 2134185353Sjfv hw->fc.requested_mode = e1000_fc_full; 2135169240Sjfv 2136185353Sjfv /* 2137185353Sjfv * Save off the requested flow control mode for use later. Depending 2138185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 2139185353Sjfv */ 2140185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 2141169240Sjfv 2142185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 2143185353Sjfv hw->fc.current_mode); 2144169240Sjfv 2145169240Sjfv /* Continue to configure the copper link. */ 2146177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 2147169240Sjfv if (ret_val) 2148169240Sjfv goto out; 2149169240Sjfv 2150173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2151169240Sjfv 2152169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 2153169240Sjfv 2154169240Sjfvout: 2155169240Sjfv return ret_val; 2156169240Sjfv} 2157169240Sjfv 2158169240Sjfv/** 2159169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2160169589Sjfv * @hw: pointer to the HW structure 2161169240Sjfv * 2162169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 2163169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 2164169240Sjfv * configuring the copper link. 2165169240Sjfv **/ 2166177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2167169240Sjfv{ 2168169240Sjfv u32 ctrl; 2169169240Sjfv s32 ret_val; 2170169240Sjfv u16 reg_data; 2171169240Sjfv 2172169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2173169240Sjfv 2174169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2175169240Sjfv ctrl |= E1000_CTRL_SLU; 2176169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2177169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2178169240Sjfv 2179173788Sjfv /* 2180173788Sjfv * Set the mac to wait the maximum time between each iteration 2181169240Sjfv * and increase the max iterations when polling the phy; 2182173788Sjfv * this fixes erroneous timeouts at 10Mbps. 2183173788Sjfv */ 2184181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4), 2185181027Sjfv 0xFFFF); 2186169240Sjfv if (ret_val) 2187169240Sjfv goto out; 2188181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2189181027Sjfv ®_data); 2190169240Sjfv if (ret_val) 2191169240Sjfv goto out; 2192169240Sjfv reg_data |= 0x3F; 2193181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2194181027Sjfv reg_data); 2195169240Sjfv if (ret_val) 2196169240Sjfv goto out; 2197169240Sjfv 2198169240Sjfv if (hw->phy.type == e1000_phy_igp_3) { 2199169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 2200169240Sjfv if (ret_val) 2201169240Sjfv goto out; 2202176667Sjfv } else if (hw->phy.type == e1000_phy_bm) { 2203176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 2204176667Sjfv if (ret_val) 2205176667Sjfv goto out; 2206169240Sjfv } 2207169240Sjfv 2208173788Sjfv if (hw->phy.type == e1000_phy_ife) { 2209177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2210177867Sjfv ®_data); 2211173788Sjfv if (ret_val) 2212173788Sjfv goto out; 2213173788Sjfv 2214173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 2215173788Sjfv 2216173788Sjfv switch (hw->phy.mdix) { 2217173788Sjfv case 1: 2218173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 2219173788Sjfv break; 2220173788Sjfv case 2: 2221173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 2222173788Sjfv break; 2223173788Sjfv case 0: 2224173788Sjfv default: 2225173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 2226173788Sjfv break; 2227173788Sjfv } 2228177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2229177867Sjfv reg_data); 2230173788Sjfv if (ret_val) 2231173788Sjfv goto out; 2232173788Sjfv } 2233169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 2234169240Sjfv 2235169240Sjfvout: 2236169240Sjfv return ret_val; 2237169240Sjfv} 2238169240Sjfv 2239169240Sjfv/** 2240169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2241169589Sjfv * @hw: pointer to the HW structure 2242169589Sjfv * @speed: pointer to store current link speed 2243169589Sjfv * @duplex: pointer to store the current link duplex 2244169240Sjfv * 2245176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 2246169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 2247169240Sjfv * gigabit speeds. 2248169240Sjfv **/ 2249177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2250173788Sjfv u16 *duplex) 2251169240Sjfv{ 2252169240Sjfv s32 ret_val; 2253169240Sjfv 2254169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2255169240Sjfv 2256169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2257169240Sjfv if (ret_val) 2258169240Sjfv goto out; 2259169240Sjfv 2260169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 2261169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 2262169240Sjfv (*speed == SPEED_1000)) { 2263169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2264169240Sjfv } 2265169240Sjfv 2266169240Sjfvout: 2267169240Sjfv return ret_val; 2268169240Sjfv} 2269169240Sjfv 2270169240Sjfv/** 2271169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2272169589Sjfv * @hw: pointer to the HW structure 2273169240Sjfv * 2274169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 2275169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 2276169240Sjfv * speed is gigabit- 2277169240Sjfv * 0) if workaround is optionally disabled do nothing 2278169240Sjfv * 1) wait 1ms for Kumeran link to come up 2279169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 2280169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 2281169240Sjfv * 4) reset the PHY 2282169240Sjfv * 5) repeat up to 10 times 2283169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 2284169240Sjfv **/ 2285173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2286169240Sjfv{ 2287185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2288169240Sjfv u32 phy_ctrl; 2289169240Sjfv s32 ret_val = E1000_SUCCESS; 2290169240Sjfv u16 i, data; 2291173788Sjfv bool link; 2292169240Sjfv 2293169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2294169240Sjfv 2295173788Sjfv if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2296169240Sjfv goto out; 2297169240Sjfv 2298173788Sjfv /* 2299173788Sjfv * Make sure link is up before proceeding. If not just return. 2300169240Sjfv * Attempting this while link is negotiating fouled up link 2301173788Sjfv * stability 2302173788Sjfv */ 2303169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2304169240Sjfv if (!link) { 2305169240Sjfv ret_val = E1000_SUCCESS; 2306169240Sjfv goto out; 2307169240Sjfv } 2308169240Sjfv 2309169240Sjfv for (i = 0; i < 10; i++) { 2310169240Sjfv /* read once to clear */ 2311177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2312169240Sjfv if (ret_val) 2313169240Sjfv goto out; 2314169240Sjfv /* and again to get new status */ 2315177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2316169240Sjfv if (ret_val) 2317169240Sjfv goto out; 2318169240Sjfv 2319169240Sjfv /* check for PCS lock */ 2320169240Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2321169240Sjfv ret_val = E1000_SUCCESS; 2322169240Sjfv goto out; 2323169240Sjfv } 2324169240Sjfv 2325169240Sjfv /* Issue PHY reset */ 2326177867Sjfv hw->phy.ops.reset(hw); 2327169240Sjfv msec_delay_irq(5); 2328169240Sjfv } 2329169240Sjfv /* Disable GigE link negotiation */ 2330169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2331169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2332169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2333169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2334169240Sjfv 2335173788Sjfv /* 2336176667Sjfv * Call gig speed drop workaround on Gig disable before accessing 2337173788Sjfv * any PHY registers 2338173788Sjfv */ 2339169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2340169240Sjfv 2341169240Sjfv /* unable to acquire PCS lock */ 2342169240Sjfv ret_val = -E1000_ERR_PHY; 2343169240Sjfv 2344169240Sjfvout: 2345169240Sjfv return ret_val; 2346169240Sjfv} 2347169240Sjfv 2348169240Sjfv/** 2349176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2350169589Sjfv * @hw: pointer to the HW structure 2351176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 2352169240Sjfv * 2353169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2354169240Sjfv * /disabled - FALSE). 2355169240Sjfv **/ 2356173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2357173788Sjfv bool state) 2358169240Sjfv{ 2359185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2360169240Sjfv 2361169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2362169240Sjfv 2363169240Sjfv if (hw->mac.type != e1000_ich8lan) { 2364169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 2365185353Sjfv return; 2366169240Sjfv } 2367169240Sjfv 2368169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 2369169240Sjfv 2370169240Sjfv return; 2371169240Sjfv} 2372169240Sjfv 2373169240Sjfv/** 2374169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2375169589Sjfv * @hw: pointer to the HW structure 2376169240Sjfv * 2377169240Sjfv * Workaround for 82566 power-down on D3 entry: 2378169240Sjfv * 1) disable gigabit link 2379169240Sjfv * 2) write VR power-down enable 2380169240Sjfv * 3) read it back 2381169240Sjfv * Continue if successful, else issue LCD reset and repeat 2382169240Sjfv **/ 2383173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2384169240Sjfv{ 2385169240Sjfv u32 reg; 2386169240Sjfv u16 data; 2387169240Sjfv u8 retry = 0; 2388169240Sjfv 2389169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2390169240Sjfv 2391169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 2392169240Sjfv goto out; 2393169240Sjfv 2394169240Sjfv /* Try the workaround twice (if needed) */ 2395169240Sjfv do { 2396169240Sjfv /* Disable link */ 2397169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2398169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2399169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2400169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2401169240Sjfv 2402173788Sjfv /* 2403176667Sjfv * Call gig speed drop workaround on Gig disable before 2404173788Sjfv * accessing any PHY registers 2405173788Sjfv */ 2406169240Sjfv if (hw->mac.type == e1000_ich8lan) 2407169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2408169240Sjfv 2409169240Sjfv /* Write VR power-down enable */ 2410177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2411169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2412185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 2413169240Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2414169240Sjfv 2415169240Sjfv /* Read it back and test */ 2416177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2417169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2418169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2419169240Sjfv break; 2420169240Sjfv 2421169240Sjfv /* Issue PHY reset and repeat at most one more time */ 2422169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 2423169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2424169240Sjfv retry++; 2425169240Sjfv } while (retry); 2426169240Sjfv 2427169240Sjfvout: 2428169240Sjfv return; 2429169240Sjfv} 2430169240Sjfv 2431169240Sjfv/** 2432169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2433169589Sjfv * @hw: pointer to the HW structure 2434169240Sjfv * 2435169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2436176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 2437169240Sjfv * 1) Set Kumeran Near-end loopback 2438169240Sjfv * 2) Clear Kumeran Near-end loopback 2439169240Sjfv * Should only be called for ICH8[m] devices with IGP_3 Phy. 2440169240Sjfv **/ 2441173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2442169240Sjfv{ 2443169240Sjfv s32 ret_val = E1000_SUCCESS; 2444169240Sjfv u16 reg_data; 2445169240Sjfv 2446169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2447169240Sjfv 2448169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 2449169240Sjfv (hw->phy.type != e1000_phy_igp_3)) 2450169240Sjfv goto out; 2451169240Sjfv 2452181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2453181027Sjfv ®_data); 2454169240Sjfv if (ret_val) 2455169240Sjfv goto out; 2456169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2457181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2458181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 2459181027Sjfv reg_data); 2460169240Sjfv if (ret_val) 2461169240Sjfv goto out; 2462169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2463181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2464181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 2465181027Sjfv reg_data); 2466169240Sjfvout: 2467169240Sjfv return; 2468169240Sjfv} 2469169240Sjfv 2470169240Sjfv/** 2471176667Sjfv * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2472176667Sjfv * @hw: pointer to the HW structure 2473176667Sjfv * 2474176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 2475176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 2476176667Sjfv * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2477176667Sjfv * to a lower speed. 2478176667Sjfv * 2479178523Sjfv * Should only be called for ICH9 and ICH10 devices. 2480176667Sjfv **/ 2481176667Sjfvvoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2482176667Sjfv{ 2483176667Sjfv u32 phy_ctrl; 2484176667Sjfv 2485178523Sjfv if ((hw->mac.type == e1000_ich10lan) || 2486178523Sjfv (hw->mac.type == e1000_ich9lan)) { 2487176667Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2488176667Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2489176667Sjfv E1000_PHY_CTRL_GBE_DISABLE; 2490176667Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2491176667Sjfv } 2492176667Sjfv 2493176667Sjfv return; 2494176667Sjfv} 2495176667Sjfv 2496176667Sjfv/** 2497169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 2498169589Sjfv * @hw: pointer to the HW structure 2499169240Sjfv * 2500169240Sjfv * Return the LED back to the default configuration. 2501169240Sjfv **/ 2502177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2503169240Sjfv{ 2504169240Sjfv s32 ret_val = E1000_SUCCESS; 2505169240Sjfv 2506169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2507169240Sjfv 2508169240Sjfv if (hw->phy.type == e1000_phy_ife) 2509185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2510176667Sjfv 0); 2511169240Sjfv else 2512169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2513169240Sjfv 2514169240Sjfv return ret_val; 2515169240Sjfv} 2516169240Sjfv 2517169240Sjfv/** 2518176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 2519169589Sjfv * @hw: pointer to the HW structure 2520169240Sjfv * 2521176667Sjfv * Turn on the LEDs. 2522169240Sjfv **/ 2523177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2524169240Sjfv{ 2525169240Sjfv s32 ret_val = E1000_SUCCESS; 2526169240Sjfv 2527169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 2528169240Sjfv 2529169240Sjfv if (hw->phy.type == e1000_phy_ife) 2530185353Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2531169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2532169240Sjfv else 2533169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2534169240Sjfv 2535169240Sjfv return ret_val; 2536169240Sjfv} 2537169240Sjfv 2538169240Sjfv/** 2539176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 2540169589Sjfv * @hw: pointer to the HW structure 2541169240Sjfv * 2542176667Sjfv * Turn off the LEDs. 2543169240Sjfv **/ 2544177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2545169240Sjfv{ 2546169240Sjfv s32 ret_val = E1000_SUCCESS; 2547169240Sjfv 2548169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 2549169240Sjfv 2550169240Sjfv if (hw->phy.type == e1000_phy_ife) 2551177867Sjfv ret_val = hw->phy.ops.write_reg(hw, 2552169240Sjfv IFE_PHY_SPECIAL_CONTROL_LED, 2553169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2554169240Sjfv else 2555169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2556169240Sjfv 2557169240Sjfv return ret_val; 2558169240Sjfv} 2559169240Sjfv 2560169240Sjfv/** 2561169240Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit 2562169589Sjfv * @hw: pointer to the HW structure 2563169240Sjfv * 2564169240Sjfv * Read the management control register for the config done bit for 2565169240Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 2566169240Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 2567169240Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2568169240Sjfv * would not be able to be reset or change link. 2569169240Sjfv **/ 2570177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2571169240Sjfv{ 2572173788Sjfv s32 ret_val = E1000_SUCCESS; 2573178523Sjfv u32 bank = 0; 2574173788Sjfv 2575169240Sjfv e1000_get_cfg_done_generic(hw); 2576169240Sjfv 2577169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2578178523Sjfv if (hw->mac.type != e1000_ich10lan) { 2579178523Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2580185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 2581178523Sjfv e1000_phy_init_script_igp3(hw); 2582178523Sjfv } 2583178523Sjfv } else { 2584178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 2585185353Sjfv /* Maybe we should do a basic PHY config */ 2586178523Sjfv DEBUGOUT("EEPROM not present\n"); 2587178523Sjfv ret_val = -E1000_ERR_CONFIG; 2588178523Sjfv } 2589169240Sjfv } 2590169240Sjfv 2591173788Sjfv return ret_val; 2592169240Sjfv} 2593169240Sjfv 2594169240Sjfv/** 2595173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 2596173788Sjfv * @hw: pointer to the HW structure 2597173788Sjfv * 2598173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 2599173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 2600173788Sjfv **/ 2601177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 2602173788Sjfv{ 2603173788Sjfv /* If the management interface is not enabled, then power down */ 2604185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 2605185353Sjfv hw->phy.ops.check_reset_block(hw))) 2606173788Sjfv e1000_power_down_phy_copper(hw); 2607173788Sjfv 2608173788Sjfv return; 2609173788Sjfv} 2610173788Sjfv 2611173788Sjfv/** 2612169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2613169589Sjfv * @hw: pointer to the HW structure 2614169240Sjfv * 2615169240Sjfv * Clears hardware counters specific to the silicon family and calls 2616169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 2617169240Sjfv **/ 2618177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2619169240Sjfv{ 2620169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2621169240Sjfv 2622169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 2623169240Sjfv 2624185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 2625185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 2626185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 2627185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 2628185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 2629185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 2630169240Sjfv 2631185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 2632185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 2633185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 2634169240Sjfv 2635185353Sjfv E1000_READ_REG(hw, E1000_IAC); 2636185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 2637169240Sjfv} 2638169240Sjfv 2639