e1000_ich8lan.c revision 178523
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 178523 2008-04-25 21:19:41Z jfv $*/ 34 35/* e1000_ich8lan 36 * e1000_ich9lan 37 */ 38 39#include "e1000_api.h" 40#include "e1000_ich8lan.h" 41 42static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 43static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 44static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 45static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 46static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 47static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 48static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 49static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 50static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 51static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 52static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 53static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 54 bool active); 55static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 56 bool active); 57static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 58 u16 words, u16 *data); 59static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 60 u16 words, u16 *data); 61static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 62static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 63static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 64 u16 *data); 65static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 66static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 67static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 68static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 69static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 70static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 71 u16 *speed, u16 *duplex); 72static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 73static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 74static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 75static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 76static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 77static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 78static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 79static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 80static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 81static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 82static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 83 u32 offset, u8* data); 84static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 85 u8 size, u16* data); 86static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 87 u32 offset, u16 *data); 88static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 89 u32 offset, u8 byte); 90static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 91 u32 offset, u8 data); 92static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 93 u8 size, u16 data); 94static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 95static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 96 97/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 98/* Offset 04h HSFSTS */ 99union ich8_hws_flash_status { 100 struct ich8_hsfsts { 101 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 102 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 103 u16 dael :1; /* bit 2 Direct Access error Log */ 104 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 105 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 106 u16 reserved1 :2; /* bit 13:6 Reserved */ 107 u16 reserved2 :6; /* bit 13:6 Reserved */ 108 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 109 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 110 } hsf_status; 111 u16 regval; 112}; 113 114/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 115/* Offset 06h FLCTL */ 116union ich8_hws_flash_ctrl { 117 struct ich8_hsflctl { 118 u16 flcgo :1; /* 0 Flash Cycle Go */ 119 u16 flcycle :2; /* 2:1 Flash Cycle */ 120 u16 reserved :5; /* 7:3 Reserved */ 121 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 122 u16 flockdn :6; /* 15:10 Reserved */ 123 } hsf_ctrl; 124 u16 regval; 125}; 126 127/* ICH Flash Region Access Permissions */ 128union ich8_hws_flash_regacc { 129 struct ich8_flracc { 130 u32 grra :8; /* 0:7 GbE region Read Access */ 131 u32 grwa :8; /* 8:15 GbE region Write Access */ 132 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 133 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 134 } hsf_flregacc; 135 u16 regval; 136}; 137 138struct e1000_shadow_ram { 139 u16 value; 140 bool modified; 141}; 142 143struct e1000_dev_spec_ich8lan { 144 bool kmrn_lock_loss_workaround_enabled; 145 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 146}; 147 148/** 149 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 150 * @hw: pointer to the HW structure 151 * 152 * Initialize family-specific PHY parameters and function pointers. 153 **/ 154static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 155{ 156 struct e1000_phy_info *phy = &hw->phy; 157 s32 ret_val = E1000_SUCCESS; 158 u16 i = 0; 159 160 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 161 162 phy->addr = 1; 163 phy->reset_delay_us = 100; 164 165 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 166 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 167 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 168 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 169 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 170 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 171 phy->ops.get_info = e1000_get_phy_info_ich8lan; 172 phy->ops.read_reg = e1000_read_phy_reg_igp; 173 phy->ops.release = e1000_release_swflag_ich8lan; 174 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 175 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 176 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 177 phy->ops.write_reg = e1000_write_phy_reg_igp; 178 phy->ops.power_up = e1000_power_up_phy_copper; 179 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 180 181 /* 182 * We may need to do this twice - once for IGP and if that fails, 183 * we'll set BM func pointers and try again 184 */ 185 ret_val = e1000_determine_phy_address(hw); 186 if (ret_val) { 187 phy->ops.write_reg = e1000_write_phy_reg_bm; 188 phy->ops.read_reg = e1000_read_phy_reg_bm; 189 ret_val = e1000_determine_phy_address(hw); 190 if (ret_val) { 191 DEBUGOUT("Cannot determine PHY address. Erroring out\n"); 192 goto out; 193 } 194 } 195 196 phy->id = 0; 197 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 198 (i++ < 100)) { 199 msec_delay(1); 200 ret_val = e1000_get_phy_id(hw); 201 if (ret_val) 202 goto out; 203 } 204 205 /* Verify phy id */ 206 switch (phy->id) { 207 case IGP03E1000_E_PHY_ID: 208 phy->type = e1000_phy_igp_3; 209 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 210 break; 211 case IFE_E_PHY_ID: 212 case IFE_PLUS_E_PHY_ID: 213 case IFE_C_E_PHY_ID: 214 phy->type = e1000_phy_ife; 215 phy->autoneg_mask = E1000_ALL_NOT_GIG; 216 break; 217 case BME1000_E_PHY_ID: 218 phy->type = e1000_phy_bm; 219 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 220 phy->ops.read_reg = e1000_read_phy_reg_bm; 221 phy->ops.write_reg = e1000_write_phy_reg_bm; 222 phy->ops.commit = e1000_phy_sw_reset_generic; 223 break; 224 default: 225 ret_val = -E1000_ERR_PHY; 226 goto out; 227 } 228 229out: 230 return ret_val; 231} 232 233/** 234 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 235 * @hw: pointer to the HW structure 236 * 237 * Initialize family-specific NVM parameters and function 238 * pointers. 239 **/ 240static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 241{ 242 struct e1000_nvm_info *nvm = &hw->nvm; 243 struct e1000_dev_spec_ich8lan *dev_spec; 244 u32 gfpreg, sector_base_addr, sector_end_addr; 245 s32 ret_val = E1000_SUCCESS; 246 u16 i; 247 248 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 249 250 /* Can't read flash registers if the register set isn't mapped. */ 251 if (!hw->flash_address) { 252 DEBUGOUT("ERROR: Flash registers not mapped\n"); 253 ret_val = -E1000_ERR_CONFIG; 254 goto out; 255 } 256 257 nvm->type = e1000_nvm_flash_sw; 258 259 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 260 261 /* 262 * sector_X_addr is a "sector"-aligned address (4096 bytes) 263 * Add 1 to sector_end_addr since this sector is included in 264 * the overall size. 265 */ 266 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 267 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 268 269 /* flash_base_addr is byte-aligned */ 270 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 271 272 /* 273 * find total size of the NVM, then cut in half since the total 274 * size represents two separate NVM banks. 275 */ 276 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 277 << FLASH_SECTOR_ADDR_SHIFT; 278 nvm->flash_bank_size /= 2; 279 /* Adjust to word count */ 280 nvm->flash_bank_size /= sizeof(u16); 281 282 nvm->word_size = E1000_SHADOW_RAM_WORDS; 283 284 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 285 286 if (!dev_spec) { 287 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 288 ret_val = -E1000_ERR_CONFIG; 289 goto out; 290 } 291 292 /* Clear shadow ram */ 293 for (i = 0; i < nvm->word_size; i++) { 294 dev_spec->shadow_ram[i].modified = FALSE; 295 dev_spec->shadow_ram[i].value = 0xFFFF; 296 } 297 298 /* Function Pointers */ 299 nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 300 nvm->ops.read = e1000_read_nvm_ich8lan; 301 nvm->ops.release = e1000_release_swflag_ich8lan; 302 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 303 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 304 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 305 nvm->ops.write = e1000_write_nvm_ich8lan; 306 307out: 308 return ret_val; 309} 310 311/** 312 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 313 * @hw: pointer to the HW structure 314 * 315 * Initialize family-specific MAC parameters and function 316 * pointers. 317 **/ 318static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 319{ 320 struct e1000_mac_info *mac = &hw->mac; 321 s32 ret_val = E1000_SUCCESS; 322 323 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 324 325 /* Set media type function pointer */ 326 hw->phy.media_type = e1000_media_type_copper; 327 328 /* Set mta register count */ 329 mac->mta_reg_count = 32; 330 /* Set rar entry count */ 331 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 332 if (mac->type == e1000_ich8lan) 333 mac->rar_entry_count--; 334 /* Set if part includes ASF firmware */ 335 mac->asf_firmware_present = TRUE; 336 /* Set if manageability features are enabled. */ 337 mac->arc_subsystem_valid = TRUE; 338 339 /* Function pointers */ 340 341 /* bus type/speed/width */ 342 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 343 /* reset */ 344 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 345 /* hw initialization */ 346 mac->ops.init_hw = e1000_init_hw_ich8lan; 347 /* link setup */ 348 mac->ops.setup_link = e1000_setup_link_ich8lan; 349 /* physical interface setup */ 350 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 351 /* check for link */ 352 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 353 /* check management mode */ 354 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 355 /* link info */ 356 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 357 /* multicast address update */ 358 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 359 /* setting MTA */ 360 mac->ops.mta_set = e1000_mta_set_generic; 361 /* blink LED */ 362 mac->ops.blink_led = e1000_blink_led_generic; 363 /* setup LED */ 364 mac->ops.setup_led = e1000_setup_led_generic; 365 /* cleanup LED */ 366 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 367 /* turn on/off LED */ 368 mac->ops.led_on = e1000_led_on_ich8lan; 369 mac->ops.led_off = e1000_led_off_ich8lan; 370 /* remove device */ 371 mac->ops.remove_device = e1000_remove_device_generic; 372 /* clear hardware counters */ 373 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 374 375 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan); 376 377 /* Device-specific structure allocation */ 378 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 379 if (ret_val) 380 goto out; 381 382 /* Enable PCS Lock-loss workaround for ICH8 */ 383 if (mac->type == e1000_ich8lan) 384 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 385 386 387out: 388 return ret_val; 389} 390 391/** 392 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 393 * @hw: pointer to the HW structure 394 * 395 * Initialize family-specific function pointers for PHY, MAC, and NVM. 396 **/ 397void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 398{ 399 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 400 401 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 402 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 403 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 404} 405 406/** 407 * e1000_acquire_swflag_ich8lan - Acquire software control flag 408 * @hw: pointer to the HW structure 409 * 410 * Acquires the software control flag for performing NVM and PHY 411 * operations. This is a function pointer entry point only called by 412 * read/write routines for the PHY and NVM parts. 413 **/ 414static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 415{ 416 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 417 s32 ret_val = E1000_SUCCESS; 418 419 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 420 421 while (timeout) { 422 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 423 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 424 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 425 426 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 427 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 428 break; 429 msec_delay_irq(1); 430 timeout--; 431 } 432 433 if (!timeout) { 434 DEBUGOUT("FW or HW has locked the resource for too long.\n"); 435 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 436 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 437 ret_val = -E1000_ERR_CONFIG; 438 goto out; 439 } 440 441out: 442 return ret_val; 443} 444 445/** 446 * e1000_release_swflag_ich8lan - Release software control flag 447 * @hw: pointer to the HW structure 448 * 449 * Releases the software control flag for performing NVM and PHY operations. 450 * This is a function pointer entry point only called by read/write 451 * routines for the PHY and NVM parts. 452 **/ 453static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 454{ 455 u32 extcnf_ctrl; 456 457 DEBUGFUNC("e1000_release_swflag_ich8lan"); 458 459 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 460 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 461 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 462 463 return; 464} 465 466/** 467 * e1000_check_mng_mode_ich8lan - Checks management mode 468 * @hw: pointer to the HW structure 469 * 470 * This checks if the adapter has manageability enabled. 471 * This is a function pointer entry point only called by read/write 472 * routines for the PHY and NVM parts. 473 **/ 474static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 475{ 476 u32 fwsm; 477 478 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 479 480 fwsm = E1000_READ_REG(hw, E1000_FWSM); 481 482 return ((fwsm & E1000_FWSM_MODE_MASK) == 483 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 484} 485 486/** 487 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 488 * @hw: pointer to the HW structure 489 * 490 * Checks if firmware is blocking the reset of the PHY. 491 * This is a function pointer entry point only called by 492 * reset routines. 493 **/ 494static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 495{ 496 u32 fwsm; 497 498 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 499 500 fwsm = E1000_READ_REG(hw, E1000_FWSM); 501 502 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 503 : E1000_BLK_PHY_RESET; 504} 505 506/** 507 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 508 * @hw: pointer to the HW structure 509 * 510 * Forces the speed and duplex settings of the PHY. 511 * This is a function pointer entry point only called by 512 * PHY setup routines. 513 **/ 514static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 515{ 516 struct e1000_phy_info *phy = &hw->phy; 517 s32 ret_val; 518 u16 data; 519 bool link; 520 521 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 522 523 if (phy->type != e1000_phy_ife) { 524 ret_val = e1000_phy_force_speed_duplex_igp(hw); 525 goto out; 526 } 527 528 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 529 if (ret_val) 530 goto out; 531 532 e1000_phy_force_speed_duplex_setup(hw, &data); 533 534 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 535 if (ret_val) 536 goto out; 537 538 /* Disable MDI-X support for 10/100 */ 539 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 540 if (ret_val) 541 goto out; 542 543 data &= ~IFE_PMC_AUTO_MDIX; 544 data &= ~IFE_PMC_FORCE_MDIX; 545 546 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 547 if (ret_val) 548 goto out; 549 550 DEBUGOUT1("IFE PMC: %X\n", data); 551 552 usec_delay(1); 553 554 if (phy->autoneg_wait_to_complete) { 555 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 556 557 ret_val = e1000_phy_has_link_generic(hw, 558 PHY_FORCE_LIMIT, 559 100000, 560 &link); 561 if (ret_val) 562 goto out; 563 564 if (!link) { 565 DEBUGOUT("Link taking longer than expected.\n"); 566 } 567 568 /* Try once more */ 569 ret_val = e1000_phy_has_link_generic(hw, 570 PHY_FORCE_LIMIT, 571 100000, 572 &link); 573 if (ret_val) 574 goto out; 575 } 576 577out: 578 return ret_val; 579} 580 581/** 582 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 583 * @hw: pointer to the HW structure 584 * 585 * Resets the PHY 586 * This is a function pointer entry point called by drivers 587 * or other shared routines. 588 **/ 589static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 590{ 591 struct e1000_phy_info *phy = &hw->phy; 592 struct e1000_nvm_info *nvm = &hw->nvm; 593 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 594 s32 ret_val; 595 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 596 u16 word_addr, reg_data, reg_addr, phy_page = 0; 597 598 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 599 600 ret_val = e1000_phy_hw_reset_generic(hw); 601 if (ret_val) 602 goto out; 603 604 /* 605 * Initialize the PHY from the NVM on ICH platforms. This 606 * is needed due to an issue where the NVM configuration is 607 * not properly autoloaded after power transitions. 608 * Therefore, after each PHY reset, we will load the 609 * configuration data out of the NVM manually. 610 */ 611 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 612 /* Check if SW needs configure the PHY */ 613 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 614 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 615 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 616 else 617 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 618 619 data = E1000_READ_REG(hw, E1000_FEXTNVM); 620 if (!(data & sw_cfg_mask)) 621 goto out; 622 623 /* Wait for basic configuration completes before proceeding*/ 624 do { 625 data = E1000_READ_REG(hw, E1000_STATUS); 626 data &= E1000_STATUS_LAN_INIT_DONE; 627 usec_delay(100); 628 } while ((!data) && --loop); 629 630 /* 631 * If basic configuration is incomplete before the above loop 632 * count reaches 0, loading the configuration from NVM will 633 * leave the PHY in a bad state possibly resulting in no link. 634 */ 635 if (loop == 0) { 636 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 637 } 638 639 /* Clear the Init Done bit for the next init event */ 640 data = E1000_READ_REG(hw, E1000_STATUS); 641 data &= ~E1000_STATUS_LAN_INIT_DONE; 642 E1000_WRITE_REG(hw, E1000_STATUS, data); 643 644 /* 645 * Make sure HW does not configure LCD from PHY 646 * extended configuration before SW configuration 647 */ 648 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 649 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 650 goto out; 651 652 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 653 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 654 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 655 if (!cnf_size) 656 goto out; 657 658 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 659 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 660 661 /* 662 * Configure LCD from extended configuration 663 * region. 664 */ 665 666 /* cnf_base_addr is in DWORD */ 667 word_addr = (u16)(cnf_base_addr << 1); 668 669 for (i = 0; i < cnf_size; i++) { 670 ret_val = nvm->ops.read(hw, 671 (word_addr + i * 2), 672 1, 673 ®_data); 674 if (ret_val) 675 goto out; 676 677 ret_val = nvm->ops.read(hw, 678 (word_addr + i * 2 + 1), 679 1, 680 ®_addr); 681 if (ret_val) 682 goto out; 683 684 /* Save off the PHY page for future writes. */ 685 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 686 phy_page = reg_data; 687 continue; 688 } 689 690 reg_addr |= phy_page; 691 692 ret_val = phy->ops.write_reg(hw, 693 (u32)reg_addr, 694 reg_data); 695 if (ret_val) 696 goto out; 697 } 698 } 699 700out: 701 return ret_val; 702} 703 704/** 705 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 706 * @hw: pointer to the HW structure 707 * 708 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 709 * This is a function pointer entry point called by drivers 710 * or other shared routines. 711 **/ 712static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 713{ 714 s32 ret_val = -E1000_ERR_PHY_TYPE; 715 716 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 717 718 switch (hw->phy.type) { 719 case e1000_phy_ife: 720 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 721 break; 722 case e1000_phy_igp_3: 723 case e1000_phy_bm: 724 ret_val = e1000_get_phy_info_igp(hw); 725 break; 726 default: 727 break; 728 } 729 730 return ret_val; 731} 732 733/** 734 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 735 * @hw: pointer to the HW structure 736 * 737 * Populates "phy" structure with various feature states. 738 * This function is only called by other family-specific 739 * routines. 740 **/ 741static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 742{ 743 struct e1000_phy_info *phy = &hw->phy; 744 s32 ret_val; 745 u16 data; 746 bool link; 747 748 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 749 750 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 751 if (ret_val) 752 goto out; 753 754 if (!link) { 755 DEBUGOUT("Phy info is only valid if link is up\n"); 756 ret_val = -E1000_ERR_CONFIG; 757 goto out; 758 } 759 760 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 761 if (ret_val) 762 goto out; 763 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 764 ? FALSE : TRUE; 765 766 if (phy->polarity_correction) { 767 ret_val = e1000_check_polarity_ife_ich8lan(hw); 768 if (ret_val) 769 goto out; 770 } else { 771 /* Polarity is forced */ 772 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 773 ? e1000_rev_polarity_reversed 774 : e1000_rev_polarity_normal; 775 } 776 777 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 778 if (ret_val) 779 goto out; 780 781 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 782 783 /* The following parameters are undefined for 10/100 operation. */ 784 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 785 phy->local_rx = e1000_1000t_rx_status_undefined; 786 phy->remote_rx = e1000_1000t_rx_status_undefined; 787 788out: 789 return ret_val; 790} 791 792/** 793 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 794 * @hw: pointer to the HW structure 795 * 796 * Polarity is determined on the polarity reversal feature being enabled. 797 * This function is only called by other family-specific 798 * routines. 799 **/ 800static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 801{ 802 struct e1000_phy_info *phy = &hw->phy; 803 s32 ret_val; 804 u16 phy_data, offset, mask; 805 806 DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 807 808 /* 809 * Polarity is determined based on the reversal feature 810 * being enabled. 811 */ 812 if (phy->polarity_correction) { 813 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 814 mask = IFE_PESC_POLARITY_REVERSED; 815 } else { 816 offset = IFE_PHY_SPECIAL_CONTROL; 817 mask = IFE_PSC_FORCE_POLARITY; 818 } 819 820 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 821 822 if (!ret_val) 823 phy->cable_polarity = (phy_data & mask) 824 ? e1000_rev_polarity_reversed 825 : e1000_rev_polarity_normal; 826 827 return ret_val; 828} 829 830/** 831 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 832 * @hw: pointer to the HW structure 833 * @active: TRUE to enable LPLU, FALSE to disable 834 * 835 * Sets the LPLU D0 state according to the active flag. When 836 * activating LPLU this function also disables smart speed 837 * and vice versa. LPLU will not be activated unless the 838 * device autonegotiation advertisement meets standards of 839 * either 10 or 10/100 or 10/100/1000 at all duplexes. 840 * This is a function pointer entry point only called by 841 * PHY setup routines. 842 **/ 843static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 844 bool active) 845{ 846 struct e1000_phy_info *phy = &hw->phy; 847 u32 phy_ctrl; 848 s32 ret_val = E1000_SUCCESS; 849 u16 data; 850 851 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 852 853 if (phy->type == e1000_phy_ife) 854 goto out; 855 856 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 857 858 if (active) { 859 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 860 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 861 862 /* 863 * Call gig speed drop workaround on LPLU before accessing 864 * any PHY registers 865 */ 866 if ((hw->mac.type == e1000_ich8lan) && 867 (hw->phy.type == e1000_phy_igp_3)) 868 e1000_gig_downshift_workaround_ich8lan(hw); 869 870 /* When LPLU is enabled, we should disable SmartSpeed */ 871 ret_val = phy->ops.read_reg(hw, 872 IGP01E1000_PHY_PORT_CONFIG, 873 &data); 874 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 875 ret_val = phy->ops.write_reg(hw, 876 IGP01E1000_PHY_PORT_CONFIG, 877 data); 878 if (ret_val) 879 goto out; 880 } else { 881 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 882 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 883 884 /* 885 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 886 * during Dx states where the power conservation is most 887 * important. During driver activity we should enable 888 * SmartSpeed, so performance is maintained. 889 */ 890 if (phy->smart_speed == e1000_smart_speed_on) { 891 ret_val = phy->ops.read_reg(hw, 892 IGP01E1000_PHY_PORT_CONFIG, 893 &data); 894 if (ret_val) 895 goto out; 896 897 data |= IGP01E1000_PSCFR_SMART_SPEED; 898 ret_val = phy->ops.write_reg(hw, 899 IGP01E1000_PHY_PORT_CONFIG, 900 data); 901 if (ret_val) 902 goto out; 903 } else if (phy->smart_speed == e1000_smart_speed_off) { 904 ret_val = phy->ops.read_reg(hw, 905 IGP01E1000_PHY_PORT_CONFIG, 906 &data); 907 if (ret_val) 908 goto out; 909 910 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 911 ret_val = phy->ops.write_reg(hw, 912 IGP01E1000_PHY_PORT_CONFIG, 913 data); 914 if (ret_val) 915 goto out; 916 } 917 } 918 919out: 920 return ret_val; 921} 922 923/** 924 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 925 * @hw: pointer to the HW structure 926 * @active: TRUE to enable LPLU, FALSE to disable 927 * 928 * Sets the LPLU D3 state according to the active flag. When 929 * activating LPLU this function also disables smart speed 930 * and vice versa. LPLU will not be activated unless the 931 * device autonegotiation advertisement meets standards of 932 * either 10 or 10/100 or 10/100/1000 at all duplexes. 933 * This is a function pointer entry point only called by 934 * PHY setup routines. 935 **/ 936static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 937 bool active) 938{ 939 struct e1000_phy_info *phy = &hw->phy; 940 u32 phy_ctrl; 941 s32 ret_val = E1000_SUCCESS; 942 u16 data; 943 944 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 945 946 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 947 948 if (!active) { 949 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 950 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 951 /* 952 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 953 * during Dx states where the power conservation is most 954 * important. During driver activity we should enable 955 * SmartSpeed, so performance is maintained. 956 */ 957 if (phy->smart_speed == e1000_smart_speed_on) { 958 ret_val = phy->ops.read_reg(hw, 959 IGP01E1000_PHY_PORT_CONFIG, 960 &data); 961 if (ret_val) 962 goto out; 963 964 data |= IGP01E1000_PSCFR_SMART_SPEED; 965 ret_val = phy->ops.write_reg(hw, 966 IGP01E1000_PHY_PORT_CONFIG, 967 data); 968 if (ret_val) 969 goto out; 970 } else if (phy->smart_speed == e1000_smart_speed_off) { 971 ret_val = phy->ops.read_reg(hw, 972 IGP01E1000_PHY_PORT_CONFIG, 973 &data); 974 if (ret_val) 975 goto out; 976 977 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 978 ret_val = phy->ops.write_reg(hw, 979 IGP01E1000_PHY_PORT_CONFIG, 980 data); 981 if (ret_val) 982 goto out; 983 } 984 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 985 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 986 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 987 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 988 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 989 990 /* 991 * Call gig speed drop workaround on LPLU before accessing 992 * any PHY registers 993 */ 994 if ((hw->mac.type == e1000_ich8lan) && 995 (hw->phy.type == e1000_phy_igp_3)) 996 e1000_gig_downshift_workaround_ich8lan(hw); 997 998 /* When LPLU is enabled, we should disable SmartSpeed */ 999 ret_val = phy->ops.read_reg(hw, 1000 IGP01E1000_PHY_PORT_CONFIG, 1001 &data); 1002 if (ret_val) 1003 goto out; 1004 1005 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1006 ret_val = phy->ops.write_reg(hw, 1007 IGP01E1000_PHY_PORT_CONFIG, 1008 data); 1009 } 1010 1011out: 1012 return ret_val; 1013} 1014 1015/** 1016 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1017 * @hw: pointer to the HW structure 1018 * @bank: pointer to the variable that returns the active bank 1019 * 1020 * Reads signature byte from the NVM using the flash access registers. 1021 **/ 1022static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1023{ 1024 s32 ret_val = E1000_SUCCESS; 1025 struct e1000_nvm_info *nvm = &hw->nvm; 1026 /* flash bank size is in words */ 1027 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1028 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1029 u8 bank_high_byte = 0; 1030 1031 if (hw->mac.type != e1000_ich10lan) { 1032 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) 1033 *bank = 1; 1034 else 1035 *bank = 0; 1036 } else if (hw->dev_spec != NULL) { 1037 /* 1038 * Make sure the signature for bank 0 is valid, 1039 * if not check for bank1 1040 */ 1041 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte); 1042 if ((bank_high_byte & 0xC0) == 0x80) { 1043 *bank = 0; 1044 } else { 1045 /* 1046 * find if segment 1 is valid by verifying 1047 * bit 15:14 = 10b in word 0x13 1048 */ 1049 e1000_read_flash_byte_ich8lan(hw, 1050 act_offset + bank1_offset, 1051 &bank_high_byte); 1052 1053 /* bank1 has a valid signature equivalent to SEC1V */ 1054 if ((bank_high_byte & 0xC0) == 0x80) { 1055 *bank = 1; 1056 } else { 1057 DEBUGOUT("ERROR: EEPROM not present\n"); 1058 ret_val = -E1000_ERR_NVM; 1059 } 1060 } 1061 } else { 1062 DEBUGOUT("DEV SPEC is NULL\n"); 1063 ret_val = -E1000_ERR_NVM; 1064 } 1065 1066 return ret_val; 1067} 1068 1069/** 1070 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1071 * @hw: pointer to the HW structure 1072 * @offset: The offset (in bytes) of the word(s) to read. 1073 * @words: Size of data to read in words 1074 * @data: Pointer to the word(s) to read at offset. 1075 * 1076 * Reads a word(s) from the NVM using the flash access registers. 1077 **/ 1078static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1079 u16 *data) 1080{ 1081 struct e1000_nvm_info *nvm = &hw->nvm; 1082 struct e1000_dev_spec_ich8lan *dev_spec; 1083 u32 act_offset; 1084 s32 ret_val = E1000_SUCCESS; 1085 u32 bank = 0; 1086 u16 i, word; 1087 1088 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1089 1090 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1091 1092 if (!dev_spec) { 1093 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1094 ret_val = -E1000_ERR_CONFIG; 1095 goto out; 1096 } 1097 1098 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1099 (words == 0)) { 1100 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1101 ret_val = -E1000_ERR_NVM; 1102 goto out; 1103 } 1104 1105 ret_val = nvm->ops.acquire(hw); 1106 if (ret_val) 1107 goto out; 1108 1109 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1110 if (ret_val != E1000_SUCCESS) 1111 goto out; 1112 1113 act_offset = (bank) ? nvm->flash_bank_size : 0; 1114 act_offset += offset; 1115 1116 for (i = 0; i < words; i++) { 1117 if ((dev_spec->shadow_ram) && 1118 (dev_spec->shadow_ram[offset+i].modified)) { 1119 data[i] = dev_spec->shadow_ram[offset+i].value; 1120 } else { 1121 ret_val = e1000_read_flash_word_ich8lan(hw, 1122 act_offset + i, 1123 &word); 1124 if (ret_val) 1125 break; 1126 data[i] = word; 1127 } 1128 } 1129 1130 nvm->ops.release(hw); 1131 1132out: 1133 return ret_val; 1134} 1135 1136/** 1137 * e1000_flash_cycle_init_ich8lan - Initialize flash 1138 * @hw: pointer to the HW structure 1139 * 1140 * This function does initial flash setup so that a new read/write/erase cycle 1141 * can be started. 1142 **/ 1143static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1144{ 1145 union ich8_hws_flash_status hsfsts; 1146 s32 ret_val = -E1000_ERR_NVM; 1147 s32 i = 0; 1148 1149 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1150 1151 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1152 1153 /* Check if the flash descriptor is valid */ 1154 if (hsfsts.hsf_status.fldesvalid == 0) { 1155 DEBUGOUT("Flash descriptor invalid. " 1156 "SW Sequencing must be used."); 1157 goto out; 1158 } 1159 1160 /* Clear FCERR and DAEL in hw status by writing 1 */ 1161 hsfsts.hsf_status.flcerr = 1; 1162 hsfsts.hsf_status.dael = 1; 1163 1164 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1165 1166 /* 1167 * Either we should have a hardware SPI cycle in progress 1168 * bit to check against, in order to start a new cycle or 1169 * FDONE bit should be changed in the hardware so that it 1170 * is 1 after hardware reset, which can then be used as an 1171 * indication whether a cycle is in progress or has been 1172 * completed. 1173 */ 1174 1175 if (hsfsts.hsf_status.flcinprog == 0) { 1176 /* 1177 * There is no cycle running at present, 1178 * so we can start a cycle. 1179 * Begin by setting Flash Cycle Done. 1180 */ 1181 hsfsts.hsf_status.flcdone = 1; 1182 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1183 ret_val = E1000_SUCCESS; 1184 } else { 1185 /* 1186 * Otherwise poll for sometime so the current 1187 * cycle has a chance to end before giving up. 1188 */ 1189 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1190 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1191 ICH_FLASH_HSFSTS); 1192 if (hsfsts.hsf_status.flcinprog == 0) { 1193 ret_val = E1000_SUCCESS; 1194 break; 1195 } 1196 usec_delay(1); 1197 } 1198 if (ret_val == E1000_SUCCESS) { 1199 /* 1200 * Successful in waiting for previous cycle to timeout, 1201 * now set the Flash Cycle Done. 1202 */ 1203 hsfsts.hsf_status.flcdone = 1; 1204 E1000_WRITE_FLASH_REG16(hw, 1205 ICH_FLASH_HSFSTS, 1206 hsfsts.regval); 1207 } else { 1208 DEBUGOUT("Flash controller busy, cannot get access"); 1209 } 1210 } 1211 1212out: 1213 return ret_val; 1214} 1215 1216/** 1217 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1218 * @hw: pointer to the HW structure 1219 * @timeout: maximum time to wait for completion 1220 * 1221 * This function starts a flash cycle and waits for its completion. 1222 **/ 1223static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1224{ 1225 union ich8_hws_flash_ctrl hsflctl; 1226 union ich8_hws_flash_status hsfsts; 1227 s32 ret_val = -E1000_ERR_NVM; 1228 u32 i = 0; 1229 1230 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1231 1232 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1233 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1234 hsflctl.hsf_ctrl.flcgo = 1; 1235 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1236 1237 /* wait till FDONE bit is set to 1 */ 1238 do { 1239 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1240 if (hsfsts.hsf_status.flcdone == 1) 1241 break; 1242 usec_delay(1); 1243 } while (i++ < timeout); 1244 1245 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1246 ret_val = E1000_SUCCESS; 1247 1248 return ret_val; 1249} 1250 1251/** 1252 * e1000_read_flash_word_ich8lan - Read word from flash 1253 * @hw: pointer to the HW structure 1254 * @offset: offset to data location 1255 * @data: pointer to the location for storing the data 1256 * 1257 * Reads the flash word at offset into data. Offset is converted 1258 * to bytes before read. 1259 **/ 1260static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1261 u16 *data) 1262{ 1263 s32 ret_val; 1264 1265 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1266 1267 if (!data) { 1268 ret_val = -E1000_ERR_NVM; 1269 goto out; 1270 } 1271 1272 /* Must convert offset into bytes. */ 1273 offset <<= 1; 1274 1275 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1276 1277out: 1278 return ret_val; 1279} 1280 1281/** 1282 * e1000_read_flash_byte_ich8lan - Read byte from flash 1283 * @hw: pointer to the HW structure 1284 * @offset: The offset of the byte to read. 1285 * @data: Pointer to a byte to store the value read. 1286 * 1287 * Reads a single byte from the NVM using the flash access registers. 1288 **/ 1289static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1290 u8* data) 1291{ 1292 s32 ret_val = E1000_SUCCESS; 1293 u16 word = 0; 1294 1295 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1296 if (ret_val) 1297 goto out; 1298 1299 *data = (u8)word; 1300 1301out: 1302 return ret_val; 1303} 1304 1305/** 1306 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1307 * @hw: pointer to the HW structure 1308 * @offset: The offset (in bytes) of the byte or word to read. 1309 * @size: Size of data to read, 1=byte 2=word 1310 * @data: Pointer to the word to store the value read. 1311 * 1312 * Reads a byte or word from the NVM using the flash access registers. 1313 **/ 1314static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1315 u8 size, u16* data) 1316{ 1317 union ich8_hws_flash_status hsfsts; 1318 union ich8_hws_flash_ctrl hsflctl; 1319 u32 flash_linear_addr; 1320 u32 flash_data = 0; 1321 s32 ret_val = -E1000_ERR_NVM; 1322 u8 count = 0; 1323 1324 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1325 1326 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1327 goto out; 1328 1329 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1330 hw->nvm.flash_base_addr; 1331 1332 do { 1333 usec_delay(1); 1334 /* Steps */ 1335 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1336 if (ret_val != E1000_SUCCESS) 1337 break; 1338 1339 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1340 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1341 hsflctl.hsf_ctrl.fldbcount = size - 1; 1342 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1343 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1344 1345 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1346 1347 ret_val = e1000_flash_cycle_ich8lan(hw, 1348 ICH_FLASH_READ_COMMAND_TIMEOUT); 1349 1350 /* 1351 * Check if FCERR is set to 1, if set to 1, clear it 1352 * and try the whole sequence a few more times, else 1353 * read in (shift in) the Flash Data0, the order is 1354 * least significant byte first msb to lsb 1355 */ 1356 if (ret_val == E1000_SUCCESS) { 1357 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1358 if (size == 1) { 1359 *data = (u8)(flash_data & 0x000000FF); 1360 } else if (size == 2) { 1361 *data = (u16)(flash_data & 0x0000FFFF); 1362 } 1363 break; 1364 } else { 1365 /* 1366 * If we've gotten here, then things are probably 1367 * completely hosed, but if the error condition is 1368 * detected, it won't hurt to give it another try... 1369 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1370 */ 1371 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1372 ICH_FLASH_HSFSTS); 1373 if (hsfsts.hsf_status.flcerr == 1) { 1374 /* Repeat for some time before giving up. */ 1375 continue; 1376 } else if (hsfsts.hsf_status.flcdone == 0) { 1377 DEBUGOUT("Timeout error - flash cycle " 1378 "did not complete."); 1379 break; 1380 } 1381 } 1382 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1383 1384out: 1385 return ret_val; 1386} 1387 1388/** 1389 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1390 * @hw: pointer to the HW structure 1391 * @offset: The offset (in bytes) of the word(s) to write. 1392 * @words: Size of data to write in words 1393 * @data: Pointer to the word(s) to write at offset. 1394 * 1395 * Writes a byte or word to the NVM using the flash access registers. 1396 **/ 1397static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1398 u16 *data) 1399{ 1400 struct e1000_nvm_info *nvm = &hw->nvm; 1401 struct e1000_dev_spec_ich8lan *dev_spec; 1402 s32 ret_val = E1000_SUCCESS; 1403 u16 i; 1404 1405 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1406 1407 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1408 1409 if (!dev_spec) { 1410 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1411 ret_val = -E1000_ERR_CONFIG; 1412 goto out; 1413 } 1414 1415 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1416 (words == 0)) { 1417 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1418 ret_val = -E1000_ERR_NVM; 1419 goto out; 1420 } 1421 1422 ret_val = nvm->ops.acquire(hw); 1423 if (ret_val) 1424 goto out; 1425 1426 for (i = 0; i < words; i++) { 1427 dev_spec->shadow_ram[offset+i].modified = TRUE; 1428 dev_spec->shadow_ram[offset+i].value = data[i]; 1429 } 1430 1431 nvm->ops.release(hw); 1432 1433out: 1434 return ret_val; 1435} 1436 1437/** 1438 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1439 * @hw: pointer to the HW structure 1440 * 1441 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1442 * which writes the checksum to the shadow ram. The changes in the shadow 1443 * ram are then committed to the EEPROM by processing each bank at a time 1444 * checking for the modified bit and writing only the pending changes. 1445 * After a successful commit, the shadow ram is cleared and is ready for 1446 * future writes. 1447 **/ 1448static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1449{ 1450 struct e1000_nvm_info *nvm = &hw->nvm; 1451 struct e1000_dev_spec_ich8lan *dev_spec; 1452 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1453 s32 ret_val; 1454 u16 data; 1455 1456 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1457 1458 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1459 1460 ret_val = e1000_update_nvm_checksum_generic(hw); 1461 if (ret_val) 1462 goto out; 1463 1464 if (nvm->type != e1000_nvm_flash_sw) 1465 goto out; 1466 1467 ret_val = nvm->ops.acquire(hw); 1468 if (ret_val) 1469 goto out; 1470 1471 /* 1472 * We're writing to the opposite bank so if we're on bank 1, 1473 * write to bank 0 etc. We also need to erase the segment that 1474 * is going to be written 1475 */ 1476 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1477 if (ret_val != E1000_SUCCESS) 1478 goto out; 1479 1480 if (bank == 0) { 1481 new_bank_offset = nvm->flash_bank_size; 1482 old_bank_offset = 0; 1483 e1000_erase_flash_bank_ich8lan(hw, 1); 1484 } else { 1485 old_bank_offset = nvm->flash_bank_size; 1486 new_bank_offset = 0; 1487 e1000_erase_flash_bank_ich8lan(hw, 0); 1488 } 1489 1490 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1491 /* 1492 * Determine whether to write the value stored 1493 * in the other NVM bank or a modified value stored 1494 * in the shadow RAM 1495 */ 1496 if (dev_spec->shadow_ram[i].modified) { 1497 data = dev_spec->shadow_ram[i].value; 1498 } else { 1499 e1000_read_flash_word_ich8lan(hw, 1500 i + old_bank_offset, 1501 &data); 1502 } 1503 1504 /* 1505 * If the word is 0x13, then make sure the signature bits 1506 * (15:14) are 11b until the commit has completed. 1507 * This will allow us to write 10b which indicates the 1508 * signature is valid. We want to do this after the write 1509 * has completed so that we don't mark the segment valid 1510 * while the write is still in progress 1511 */ 1512 if (i == E1000_ICH_NVM_SIG_WORD) 1513 data |= E1000_ICH_NVM_SIG_MASK; 1514 1515 /* Convert offset to bytes. */ 1516 act_offset = (i + new_bank_offset) << 1; 1517 1518 usec_delay(100); 1519 /* Write the bytes to the new bank. */ 1520 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1521 act_offset, 1522 (u8)data); 1523 if (ret_val) 1524 break; 1525 1526 usec_delay(100); 1527 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1528 act_offset + 1, 1529 (u8)(data >> 8)); 1530 if (ret_val) 1531 break; 1532 } 1533 1534 /* 1535 * Don't bother writing the segment valid bits if sector 1536 * programming failed. 1537 */ 1538 if (ret_val) { 1539 DEBUGOUT("Flash commit failed.\n"); 1540 nvm->ops.release(hw); 1541 goto out; 1542 } 1543 1544 /* 1545 * Finally validate the new segment by setting bit 15:14 1546 * to 10b in word 0x13 , this can be done without an 1547 * erase as well since these bits are 11 to start with 1548 * and we need to change bit 14 to 0b 1549 */ 1550 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1551 e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1552 data &= 0xBFFF; 1553 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1554 act_offset * 2 + 1, 1555 (u8)(data >> 8)); 1556 if (ret_val) { 1557 nvm->ops.release(hw); 1558 goto out; 1559 } 1560 1561 /* 1562 * And invalidate the previously valid segment by setting 1563 * its signature word (0x13) high_byte to 0b. This can be 1564 * done without an erase because flash erase sets all bits 1565 * to 1's. We can write 1's to 0's without an erase 1566 */ 1567 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1568 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1569 if (ret_val) { 1570 nvm->ops.release(hw); 1571 goto out; 1572 } 1573 1574 /* Great! Everything worked, we can now clear the cached entries. */ 1575 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1576 dev_spec->shadow_ram[i].modified = FALSE; 1577 dev_spec->shadow_ram[i].value = 0xFFFF; 1578 } 1579 1580 nvm->ops.release(hw); 1581 1582 /* 1583 * Reload the EEPROM, or else modifications will not appear 1584 * until after the next adapter reset. 1585 */ 1586 nvm->ops.reload(hw); 1587 msec_delay(10); 1588 1589out: 1590 return ret_val; 1591} 1592 1593/** 1594 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1595 * @hw: pointer to the HW structure 1596 * 1597 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1598 * If the bit is 0, that the EEPROM had been modified, but the checksum was 1599 * not calculated, in which case we need to calculate the checksum and set 1600 * bit 6. 1601 **/ 1602static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1603{ 1604 s32 ret_val = E1000_SUCCESS; 1605 u16 data; 1606 1607 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1608 1609 /* 1610 * Read 0x19 and check bit 6. If this bit is 0, the checksum 1611 * needs to be fixed. This bit is an indication that the NVM 1612 * was prepared by OEM software and did not calculate the 1613 * checksum...a likely scenario. 1614 */ 1615 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1616 if (ret_val) 1617 goto out; 1618 1619 if ((data & 0x40) == 0) { 1620 data |= 0x40; 1621 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1622 if (ret_val) 1623 goto out; 1624 ret_val = hw->nvm.ops.update(hw); 1625 if (ret_val) 1626 goto out; 1627 } 1628 1629 ret_val = e1000_validate_nvm_checksum_generic(hw); 1630 1631out: 1632 return ret_val; 1633} 1634 1635/** 1636 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1637 * @hw: pointer to the HW structure 1638 * @offset: The offset (in bytes) of the byte/word to read. 1639 * @size: Size of data to read, 1=byte 2=word 1640 * @data: The byte(s) to write to the NVM. 1641 * 1642 * Writes one/two bytes to the NVM using the flash access registers. 1643 **/ 1644static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1645 u8 size, u16 data) 1646{ 1647 union ich8_hws_flash_status hsfsts; 1648 union ich8_hws_flash_ctrl hsflctl; 1649 u32 flash_linear_addr; 1650 u32 flash_data = 0; 1651 s32 ret_val = -E1000_ERR_NVM; 1652 u8 count = 0; 1653 1654 DEBUGFUNC("e1000_write_ich8_data"); 1655 1656 if (size < 1 || size > 2 || data > size * 0xff || 1657 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1658 goto out; 1659 1660 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1661 hw->nvm.flash_base_addr; 1662 1663 do { 1664 usec_delay(1); 1665 /* Steps */ 1666 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1667 if (ret_val != E1000_SUCCESS) 1668 break; 1669 1670 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1671 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1672 hsflctl.hsf_ctrl.fldbcount = size -1; 1673 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1674 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1675 1676 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1677 1678 if (size == 1) 1679 flash_data = (u32)data & 0x00FF; 1680 else 1681 flash_data = (u32)data; 1682 1683 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1684 1685 /* 1686 * check if FCERR is set to 1 , if set to 1, clear it 1687 * and try the whole sequence a few more times else done 1688 */ 1689 ret_val = e1000_flash_cycle_ich8lan(hw, 1690 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1691 if (ret_val == E1000_SUCCESS) { 1692 break; 1693 } else { 1694 /* 1695 * If we're here, then things are most likely 1696 * completely hosed, but if the error condition 1697 * is detected, it won't hurt to give it another 1698 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1699 */ 1700 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1701 ICH_FLASH_HSFSTS); 1702 if (hsfsts.hsf_status.flcerr == 1) { 1703 /* Repeat for some time before giving up. */ 1704 continue; 1705 } else if (hsfsts.hsf_status.flcdone == 0) { 1706 DEBUGOUT("Timeout error - flash cycle " 1707 "did not complete."); 1708 break; 1709 } 1710 } 1711 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1712 1713out: 1714 return ret_val; 1715} 1716 1717/** 1718 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1719 * @hw: pointer to the HW structure 1720 * @offset: The index of the byte to read. 1721 * @data: The byte to write to the NVM. 1722 * 1723 * Writes a single byte to the NVM using the flash access registers. 1724 **/ 1725static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1726 u8 data) 1727{ 1728 u16 word = (u16)data; 1729 1730 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1731 1732 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1733} 1734 1735/** 1736 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1737 * @hw: pointer to the HW structure 1738 * @offset: The offset of the byte to write. 1739 * @byte: The byte to write to the NVM. 1740 * 1741 * Writes a single byte to the NVM using the flash access registers. 1742 * Goes through a retry algorithm before giving up. 1743 **/ 1744static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1745 u32 offset, u8 byte) 1746{ 1747 s32 ret_val; 1748 u16 program_retries; 1749 1750 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1751 1752 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1753 if (ret_val == E1000_SUCCESS) 1754 goto out; 1755 1756 for (program_retries = 0; program_retries < 100; program_retries++) { 1757 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1758 usec_delay(100); 1759 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1760 if (ret_val == E1000_SUCCESS) 1761 break; 1762 } 1763 if (program_retries == 100) { 1764 ret_val = -E1000_ERR_NVM; 1765 goto out; 1766 } 1767 1768out: 1769 return ret_val; 1770} 1771 1772/** 1773 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1774 * @hw: pointer to the HW structure 1775 * @bank: 0 for first bank, 1 for second bank, etc. 1776 * 1777 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1778 * bank N is 4096 * N + flash_reg_addr. 1779 **/ 1780static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1781{ 1782 struct e1000_nvm_info *nvm = &hw->nvm; 1783 union ich8_hws_flash_status hsfsts; 1784 union ich8_hws_flash_ctrl hsflctl; 1785 u32 flash_linear_addr; 1786 /* bank size is in 16bit words - adjust to bytes */ 1787 u32 flash_bank_size = nvm->flash_bank_size * 2; 1788 s32 ret_val = E1000_SUCCESS; 1789 s32 count = 0; 1790 s32 j, iteration, sector_size; 1791 1792 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1793 1794 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1795 1796 /* 1797 * Determine HW Sector size: Read BERASE bits of hw flash status 1798 * register 1799 * 00: The Hw sector is 256 bytes, hence we need to erase 16 1800 * consecutive sectors. The start index for the nth Hw sector 1801 * can be calculated as = bank * 4096 + n * 256 1802 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1803 * The start index for the nth Hw sector can be calculated 1804 * as = bank * 4096 1805 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1806 * (ich9 only, otherwise error condition) 1807 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1808 */ 1809 switch (hsfsts.hsf_status.berasesz) { 1810 case 0: 1811 /* Hw sector size 256 */ 1812 sector_size = ICH_FLASH_SEG_SIZE_256; 1813 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1814 break; 1815 case 1: 1816 sector_size = ICH_FLASH_SEG_SIZE_4K; 1817 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1818 break; 1819 case 2: 1820 if (hw->mac.type == e1000_ich9lan) { 1821 sector_size = ICH_FLASH_SEG_SIZE_8K; 1822 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1823 } else { 1824 ret_val = -E1000_ERR_NVM; 1825 goto out; 1826 } 1827 break; 1828 case 3: 1829 sector_size = ICH_FLASH_SEG_SIZE_64K; 1830 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1831 break; 1832 default: 1833 ret_val = -E1000_ERR_NVM; 1834 goto out; 1835 } 1836 1837 /* Start with the base address, then add the sector offset. */ 1838 flash_linear_addr = hw->nvm.flash_base_addr; 1839 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1840 1841 for (j = 0; j < iteration ; j++) { 1842 do { 1843 /* Steps */ 1844 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1845 if (ret_val) 1846 goto out; 1847 1848 /* 1849 * Write a value 11 (block Erase) in Flash 1850 * Cycle field in hw flash control 1851 */ 1852 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1853 ICH_FLASH_HSFCTL); 1854 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1855 E1000_WRITE_FLASH_REG16(hw, 1856 ICH_FLASH_HSFCTL, 1857 hsflctl.regval); 1858 1859 /* 1860 * Write the last 24 bits of an index within the 1861 * block into Flash Linear address field in Flash 1862 * Address. 1863 */ 1864 flash_linear_addr += (j * sector_size); 1865 E1000_WRITE_FLASH_REG(hw, 1866 ICH_FLASH_FADDR, 1867 flash_linear_addr); 1868 1869 ret_val = e1000_flash_cycle_ich8lan(hw, 1870 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1871 if (ret_val == E1000_SUCCESS) { 1872 break; 1873 } else { 1874 /* 1875 * Check if FCERR is set to 1. If 1, 1876 * clear it and try the whole sequence 1877 * a few more times else Done 1878 */ 1879 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1880 ICH_FLASH_HSFSTS); 1881 if (hsfsts.hsf_status.flcerr == 1) { 1882 /* 1883 * repeat for some time before 1884 * giving up 1885 */ 1886 continue; 1887 } else if (hsfsts.hsf_status.flcdone == 0) 1888 goto out; 1889 } 1890 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1891 } 1892 1893out: 1894 return ret_val; 1895} 1896 1897/** 1898 * e1000_valid_led_default_ich8lan - Set the default LED settings 1899 * @hw: pointer to the HW structure 1900 * @data: Pointer to the LED settings 1901 * 1902 * Reads the LED default settings from the NVM to data. If the NVM LED 1903 * settings is all 0's or F's, set the LED default to a valid LED default 1904 * setting. 1905 **/ 1906static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1907{ 1908 s32 ret_val; 1909 1910 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1911 1912 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1913 if (ret_val) { 1914 DEBUGOUT("NVM Read Error\n"); 1915 goto out; 1916 } 1917 1918 if (*data == ID_LED_RESERVED_0000 || 1919 *data == ID_LED_RESERVED_FFFF) 1920 *data = ID_LED_DEFAULT_ICH8LAN; 1921 1922out: 1923 return ret_val; 1924} 1925 1926/** 1927 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1928 * @hw: pointer to the HW structure 1929 * 1930 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1931 * register, so the the bus width is hard coded. 1932 **/ 1933static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1934{ 1935 struct e1000_bus_info *bus = &hw->bus; 1936 s32 ret_val; 1937 1938 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1939 1940 ret_val = e1000_get_bus_info_pcie_generic(hw); 1941 1942 /* 1943 * ICH devices are "PCI Express"-ish. They have 1944 * a configuration space, but do not contain 1945 * PCI Express Capability registers, so bus width 1946 * must be hardcoded. 1947 */ 1948 if (bus->width == e1000_bus_width_unknown) 1949 bus->width = e1000_bus_width_pcie_x1; 1950 1951 return ret_val; 1952} 1953 1954/** 1955 * e1000_reset_hw_ich8lan - Reset the hardware 1956 * @hw: pointer to the HW structure 1957 * 1958 * Does a full reset of the hardware which includes a reset of the PHY and 1959 * MAC. 1960 **/ 1961static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1962{ 1963 u32 ctrl, icr, kab; 1964 s32 ret_val; 1965 1966 DEBUGFUNC("e1000_reset_hw_ich8lan"); 1967 1968 /* 1969 * Prevent the PCI-E bus from sticking if there is no TLP connection 1970 * on the last TLP read/write transaction when MAC is reset. 1971 */ 1972 ret_val = e1000_disable_pcie_master_generic(hw); 1973 if (ret_val) { 1974 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1975 } 1976 1977 DEBUGOUT("Masking off all interrupts\n"); 1978 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1979 1980 /* 1981 * Disable the Transmit and Receive units. Then delay to allow 1982 * any pending transactions to complete before we hit the MAC 1983 * with the global reset. 1984 */ 1985 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1986 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1987 E1000_WRITE_FLUSH(hw); 1988 1989 msec_delay(10); 1990 1991 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1992 if (hw->mac.type == e1000_ich8lan) { 1993 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1994 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1995 /* Set Packet Buffer Size to 16k. */ 1996 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 1997 } 1998 1999 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2000 2001 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 2002 /* 2003 * PHY HW reset requires MAC CORE reset at the same 2004 * time to make sure the interface between MAC and the 2005 * external PHY is reset. 2006 */ 2007 ctrl |= E1000_CTRL_PHY_RST; 2008 } 2009 ret_val = e1000_acquire_swflag_ich8lan(hw); 2010 DEBUGOUT("Issuing a global reset to ich8lan"); 2011 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2012 msec_delay(20); 2013 2014 ret_val = e1000_get_auto_rd_done_generic(hw); 2015 if (ret_val) { 2016 /* 2017 * When auto config read does not complete, do not 2018 * return with an error. This can happen in situations 2019 * where there is no eeprom and prevents getting link. 2020 */ 2021 DEBUGOUT("Auto Read Done did not complete\n"); 2022 } 2023 2024 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2025 icr = E1000_READ_REG(hw, E1000_ICR); 2026 2027 kab = E1000_READ_REG(hw, E1000_KABGTXD); 2028 kab |= E1000_KABGTXD_BGSQLBIAS; 2029 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2030 2031 return ret_val; 2032} 2033 2034/** 2035 * e1000_init_hw_ich8lan - Initialize the hardware 2036 * @hw: pointer to the HW structure 2037 * 2038 * Prepares the hardware for transmit and receive by doing the following: 2039 * - initialize hardware bits 2040 * - initialize LED identification 2041 * - setup receive address registers 2042 * - setup flow control 2043 * - setup transmit descriptors 2044 * - clear statistics 2045 **/ 2046static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2047{ 2048 struct e1000_mac_info *mac = &hw->mac; 2049 u32 ctrl_ext, txdctl, snoop; 2050 s32 ret_val; 2051 u16 i; 2052 2053 DEBUGFUNC("e1000_init_hw_ich8lan"); 2054 2055 e1000_initialize_hw_bits_ich8lan(hw); 2056 2057 /* Initialize identification LED */ 2058 ret_val = e1000_id_led_init_generic(hw); 2059 if (ret_val) { 2060 DEBUGOUT("Error initializing identification LED\n"); 2061 /* This is not fatal and we should not stop init due to this */ 2062 } 2063 2064 /* Setup the receive address. */ 2065 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2066 2067 /* Zero out the Multicast HASH table */ 2068 DEBUGOUT("Zeroing the MTA\n"); 2069 for (i = 0; i < mac->mta_reg_count; i++) 2070 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2071 2072 /* Setup link and flow control */ 2073 ret_val = mac->ops.setup_link(hw); 2074 2075 /* Set the transmit descriptor write-back policy for both queues */ 2076 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2077 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2078 E1000_TXDCTL_FULL_TX_DESC_WB; 2079 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2080 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2081 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2082 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2083 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2084 E1000_TXDCTL_FULL_TX_DESC_WB; 2085 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2086 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2087 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2088 2089 /* 2090 * ICH8 has opposite polarity of no_snoop bits. 2091 * By default, we should use snoop behavior. 2092 */ 2093 if (mac->type == e1000_ich8lan) 2094 snoop = PCIE_ICH8_SNOOP_ALL; 2095 else 2096 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2097 e1000_set_pcie_no_snoop_generic(hw, snoop); 2098 2099 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2100 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2101 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2102 2103 /* 2104 * Clear all of the statistics registers (clear on read). It is 2105 * important that we do this after we have tried to establish link 2106 * because the symbol error count will increment wildly if there 2107 * is no link. 2108 */ 2109 e1000_clear_hw_cntrs_ich8lan(hw); 2110 2111 return ret_val; 2112} 2113/** 2114 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2115 * @hw: pointer to the HW structure 2116 * 2117 * Sets/Clears required hardware bits necessary for correctly setting up the 2118 * hardware for transmit and receive. 2119 **/ 2120static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2121{ 2122 u32 reg; 2123 2124 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2125 2126 if (hw->mac.disable_hw_init_bits) 2127 goto out; 2128 2129 /* Extended Device Control */ 2130 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2131 reg |= (1 << 22); 2132 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2133 2134 /* Transmit Descriptor Control 0 */ 2135 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2136 reg |= (1 << 22); 2137 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2138 2139 /* Transmit Descriptor Control 1 */ 2140 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2141 reg |= (1 << 22); 2142 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2143 2144 /* Transmit Arbitration Control 0 */ 2145 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2146 if (hw->mac.type == e1000_ich8lan) 2147 reg |= (1 << 28) | (1 << 29); 2148 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2149 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2150 2151 /* Transmit Arbitration Control 1 */ 2152 reg = E1000_READ_REG(hw, E1000_TARC(1)); 2153 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2154 reg &= ~(1 << 28); 2155 else 2156 reg |= (1 << 28); 2157 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2158 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2159 2160 /* Device Status */ 2161 if (hw->mac.type == e1000_ich8lan) { 2162 reg = E1000_READ_REG(hw, E1000_STATUS); 2163 reg &= ~(1 << 31); 2164 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2165 } 2166 2167out: 2168 return; 2169} 2170 2171/** 2172 * e1000_setup_link_ich8lan - Setup flow control and link settings 2173 * @hw: pointer to the HW structure 2174 * 2175 * Determines which flow control settings to use, then configures flow 2176 * control. Calls the appropriate media-specific link configuration 2177 * function. Assuming the adapter has a valid link partner, a valid link 2178 * should be established. Assumes the hardware has previously been reset 2179 * and the transmitter and receiver are not enabled. 2180 **/ 2181static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2182{ 2183 s32 ret_val = E1000_SUCCESS; 2184 2185 DEBUGFUNC("e1000_setup_link_ich8lan"); 2186 2187 if (hw->phy.ops.check_reset_block(hw)) 2188 goto out; 2189 2190 /* 2191 * ICH parts do not have a word in the NVM to determine 2192 * the default flow control setting, so we explicitly 2193 * set it to full. 2194 */ 2195 if (hw->fc.type == e1000_fc_default) 2196 hw->fc.type = e1000_fc_full; 2197 2198 hw->fc.original_type = hw->fc.type; 2199 2200 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 2201 2202 /* Continue to configure the copper link. */ 2203 ret_val = hw->mac.ops.setup_physical_interface(hw); 2204 if (ret_val) 2205 goto out; 2206 2207 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2208 2209 ret_val = e1000_set_fc_watermarks_generic(hw); 2210 2211out: 2212 return ret_val; 2213} 2214 2215/** 2216 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2217 * @hw: pointer to the HW structure 2218 * 2219 * Configures the kumeran interface to the PHY to wait the appropriate time 2220 * when polling the PHY, then call the generic setup_copper_link to finish 2221 * configuring the copper link. 2222 **/ 2223static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2224{ 2225 u32 ctrl; 2226 s32 ret_val; 2227 u16 reg_data; 2228 2229 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2230 2231 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2232 ctrl |= E1000_CTRL_SLU; 2233 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2234 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2235 2236 /* 2237 * Set the mac to wait the maximum time between each iteration 2238 * and increase the max iterations when polling the phy; 2239 * this fixes erroneous timeouts at 10Mbps. 2240 */ 2241 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2242 if (ret_val) 2243 goto out; 2244 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 2245 if (ret_val) 2246 goto out; 2247 reg_data |= 0x3F; 2248 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 2249 if (ret_val) 2250 goto out; 2251 2252 if (hw->phy.type == e1000_phy_igp_3) { 2253 ret_val = e1000_copper_link_setup_igp(hw); 2254 if (ret_val) 2255 goto out; 2256 } else if (hw->phy.type == e1000_phy_bm) { 2257 ret_val = e1000_copper_link_setup_m88(hw); 2258 if (ret_val) 2259 goto out; 2260 } 2261 2262 if (hw->phy.type == e1000_phy_ife) { 2263 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2264 ®_data); 2265 if (ret_val) 2266 goto out; 2267 2268 reg_data &= ~IFE_PMC_AUTO_MDIX; 2269 2270 switch (hw->phy.mdix) { 2271 case 1: 2272 reg_data &= ~IFE_PMC_FORCE_MDIX; 2273 break; 2274 case 2: 2275 reg_data |= IFE_PMC_FORCE_MDIX; 2276 break; 2277 case 0: 2278 default: 2279 reg_data |= IFE_PMC_AUTO_MDIX; 2280 break; 2281 } 2282 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2283 reg_data); 2284 if (ret_val) 2285 goto out; 2286 } 2287 ret_val = e1000_setup_copper_link_generic(hw); 2288 2289out: 2290 return ret_val; 2291} 2292 2293/** 2294 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2295 * @hw: pointer to the HW structure 2296 * @speed: pointer to store current link speed 2297 * @duplex: pointer to store the current link duplex 2298 * 2299 * Calls the generic get_speed_and_duplex to retrieve the current link 2300 * information and then calls the Kumeran lock loss workaround for links at 2301 * gigabit speeds. 2302 **/ 2303static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2304 u16 *duplex) 2305{ 2306 s32 ret_val; 2307 2308 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2309 2310 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2311 if (ret_val) 2312 goto out; 2313 2314 if ((hw->mac.type == e1000_ich8lan) && 2315 (hw->phy.type == e1000_phy_igp_3) && 2316 (*speed == SPEED_1000)) { 2317 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2318 } 2319 2320out: 2321 return ret_val; 2322} 2323 2324/** 2325 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2326 * @hw: pointer to the HW structure 2327 * 2328 * Work-around for 82566 Kumeran PCS lock loss: 2329 * On link status change (i.e. PCI reset, speed change) and link is up and 2330 * speed is gigabit- 2331 * 0) if workaround is optionally disabled do nothing 2332 * 1) wait 1ms for Kumeran link to come up 2333 * 2) check Kumeran Diagnostic register PCS lock loss bit 2334 * 3) if not set the link is locked (all is good), otherwise... 2335 * 4) reset the PHY 2336 * 5) repeat up to 10 times 2337 * Note: this is only called for IGP3 copper when speed is 1gb. 2338 **/ 2339static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2340{ 2341 struct e1000_dev_spec_ich8lan *dev_spec; 2342 u32 phy_ctrl; 2343 s32 ret_val = E1000_SUCCESS; 2344 u16 i, data; 2345 bool link; 2346 2347 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2348 2349 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2350 2351 if (!dev_spec) { 2352 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2353 ret_val = -E1000_ERR_CONFIG; 2354 goto out; 2355 } 2356 2357 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2358 goto out; 2359 2360 /* 2361 * Make sure link is up before proceeding. If not just return. 2362 * Attempting this while link is negotiating fouled up link 2363 * stability 2364 */ 2365 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2366 if (!link) { 2367 ret_val = E1000_SUCCESS; 2368 goto out; 2369 } 2370 2371 for (i = 0; i < 10; i++) { 2372 /* read once to clear */ 2373 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2374 if (ret_val) 2375 goto out; 2376 /* and again to get new status */ 2377 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2378 if (ret_val) 2379 goto out; 2380 2381 /* check for PCS lock */ 2382 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2383 ret_val = E1000_SUCCESS; 2384 goto out; 2385 } 2386 2387 /* Issue PHY reset */ 2388 hw->phy.ops.reset(hw); 2389 msec_delay_irq(5); 2390 } 2391 /* Disable GigE link negotiation */ 2392 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2393 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2394 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2395 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2396 2397 /* 2398 * Call gig speed drop workaround on Gig disable before accessing 2399 * any PHY registers 2400 */ 2401 e1000_gig_downshift_workaround_ich8lan(hw); 2402 2403 /* unable to acquire PCS lock */ 2404 ret_val = -E1000_ERR_PHY; 2405 2406out: 2407 return ret_val; 2408} 2409 2410/** 2411 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2412 * @hw: pointer to the HW structure 2413 * @state: boolean value used to set the current Kumeran workaround state 2414 * 2415 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2416 * /disabled - FALSE). 2417 **/ 2418void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2419 bool state) 2420{ 2421 struct e1000_dev_spec_ich8lan *dev_spec; 2422 2423 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2424 2425 if (hw->mac.type != e1000_ich8lan) { 2426 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2427 goto out; 2428 } 2429 2430 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2431 2432 if (!dev_spec) { 2433 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2434 goto out; 2435 } 2436 2437 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2438 2439out: 2440 return; 2441} 2442 2443/** 2444 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2445 * @hw: pointer to the HW structure 2446 * 2447 * Workaround for 82566 power-down on D3 entry: 2448 * 1) disable gigabit link 2449 * 2) write VR power-down enable 2450 * 3) read it back 2451 * Continue if successful, else issue LCD reset and repeat 2452 **/ 2453void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2454{ 2455 u32 reg; 2456 u16 data; 2457 u8 retry = 0; 2458 2459 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2460 2461 if (hw->phy.type != e1000_phy_igp_3) 2462 goto out; 2463 2464 /* Try the workaround twice (if needed) */ 2465 do { 2466 /* Disable link */ 2467 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2468 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2469 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2470 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2471 2472 /* 2473 * Call gig speed drop workaround on Gig disable before 2474 * accessing any PHY registers 2475 */ 2476 if (hw->mac.type == e1000_ich8lan) 2477 e1000_gig_downshift_workaround_ich8lan(hw); 2478 2479 /* Write VR power-down enable */ 2480 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2481 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2482 hw->phy.ops.write_reg(hw, 2483 IGP3_VR_CTRL, 2484 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2485 2486 /* Read it back and test */ 2487 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2488 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2489 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2490 break; 2491 2492 /* Issue PHY reset and repeat at most one more time */ 2493 reg = E1000_READ_REG(hw, E1000_CTRL); 2494 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2495 retry++; 2496 } while (retry); 2497 2498out: 2499 return; 2500} 2501 2502/** 2503 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2504 * @hw: pointer to the HW structure 2505 * 2506 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2507 * LPLU, Gig disable, MDIC PHY reset): 2508 * 1) Set Kumeran Near-end loopback 2509 * 2) Clear Kumeran Near-end loopback 2510 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2511 **/ 2512void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2513{ 2514 s32 ret_val = E1000_SUCCESS; 2515 u16 reg_data; 2516 2517 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2518 2519 if ((hw->mac.type != e1000_ich8lan) || 2520 (hw->phy.type != e1000_phy_igp_3)) 2521 goto out; 2522 2523 ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2524 ®_data); 2525 if (ret_val) 2526 goto out; 2527 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2528 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2529 reg_data); 2530 if (ret_val) 2531 goto out; 2532 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2533 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2534 reg_data); 2535out: 2536 return; 2537} 2538 2539/** 2540 * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2541 * @hw: pointer to the HW structure 2542 * 2543 * During S0 to Sx transition, it is possible the link remains at gig 2544 * instead of negotiating to a lower speed. Before going to Sx, set 2545 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2546 * to a lower speed. 2547 * 2548 * Should only be called for ICH9 and ICH10 devices. 2549 **/ 2550void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2551{ 2552 u32 phy_ctrl; 2553 2554 if ((hw->mac.type == e1000_ich10lan) || 2555 (hw->mac.type == e1000_ich9lan)) { 2556 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2557 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2558 E1000_PHY_CTRL_GBE_DISABLE; 2559 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2560 } 2561 2562 return; 2563} 2564 2565/** 2566 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2567 * @hw: pointer to the HW structure 2568 * 2569 * Return the LED back to the default configuration. 2570 **/ 2571static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2572{ 2573 s32 ret_val = E1000_SUCCESS; 2574 2575 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2576 2577 if (hw->phy.type == e1000_phy_ife) 2578 ret_val = hw->phy.ops.write_reg(hw, 2579 IFE_PHY_SPECIAL_CONTROL_LED, 2580 0); 2581 else 2582 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2583 2584 return ret_val; 2585} 2586 2587/** 2588 * e1000_led_on_ich8lan - Turn LEDs on 2589 * @hw: pointer to the HW structure 2590 * 2591 * Turn on the LEDs. 2592 **/ 2593static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2594{ 2595 s32 ret_val = E1000_SUCCESS; 2596 2597 DEBUGFUNC("e1000_led_on_ich8lan"); 2598 2599 if (hw->phy.type == e1000_phy_ife) 2600 ret_val = hw->phy.ops.write_reg(hw, 2601 IFE_PHY_SPECIAL_CONTROL_LED, 2602 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2603 else 2604 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2605 2606 return ret_val; 2607} 2608 2609/** 2610 * e1000_led_off_ich8lan - Turn LEDs off 2611 * @hw: pointer to the HW structure 2612 * 2613 * Turn off the LEDs. 2614 **/ 2615static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2616{ 2617 s32 ret_val = E1000_SUCCESS; 2618 2619 DEBUGFUNC("e1000_led_off_ich8lan"); 2620 2621 if (hw->phy.type == e1000_phy_ife) 2622 ret_val = hw->phy.ops.write_reg(hw, 2623 IFE_PHY_SPECIAL_CONTROL_LED, 2624 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2625 else 2626 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2627 2628 return ret_val; 2629} 2630 2631/** 2632 * e1000_get_cfg_done_ich8lan - Read config done bit 2633 * @hw: pointer to the HW structure 2634 * 2635 * Read the management control register for the config done bit for 2636 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2637 * to read the config done bit, so an error is *ONLY* logged and returns 2638 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2639 * would not be able to be reset or change link. 2640 **/ 2641static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2642{ 2643 s32 ret_val = E1000_SUCCESS; 2644 u32 bank = 0; 2645 2646 e1000_get_cfg_done_generic(hw); 2647 2648 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2649 if (hw->mac.type != e1000_ich10lan) { 2650 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2651 (hw->phy.type == e1000_phy_igp_3)) { 2652 e1000_phy_init_script_igp3(hw); 2653 } 2654 } else { 2655 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 2656 /* Maybe we should do a basic Boazman config */ 2657 DEBUGOUT("EEPROM not present\n"); 2658 ret_val = -E1000_ERR_CONFIG; 2659 } 2660 } 2661 2662 return ret_val; 2663} 2664 2665/** 2666 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 2667 * @hw: pointer to the HW structure 2668 * 2669 * In the case of a PHY power down to save power, or to turn off link during a 2670 * driver unload, or wake on lan is not enabled, remove the link. 2671 **/ 2672static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 2673{ 2674 struct e1000_phy_info *phy = &hw->phy; 2675 struct e1000_mac_info *mac = &hw->mac; 2676 2677 /* If the management interface is not enabled, then power down */ 2678 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 2679 e1000_power_down_phy_copper(hw); 2680 2681 return; 2682} 2683 2684/** 2685 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2686 * @hw: pointer to the HW structure 2687 * 2688 * Clears hardware counters specific to the silicon family and calls 2689 * clear_hw_cntrs_generic to clear all general purpose counters. 2690 **/ 2691static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2692{ 2693 volatile u32 temp; 2694 2695 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2696 2697 e1000_clear_hw_cntrs_base_generic(hw); 2698 2699 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 2700 temp = E1000_READ_REG(hw, E1000_RXERRC); 2701 temp = E1000_READ_REG(hw, E1000_TNCRS); 2702 temp = E1000_READ_REG(hw, E1000_CEXTERR); 2703 temp = E1000_READ_REG(hw, E1000_TSCTC); 2704 temp = E1000_READ_REG(hw, E1000_TSCTFC); 2705 2706 temp = E1000_READ_REG(hw, E1000_MGTPRC); 2707 temp = E1000_READ_REG(hw, E1000_MGTPDC); 2708 temp = E1000_READ_REG(hw, E1000_MGTPTC); 2709 2710 temp = E1000_READ_REG(hw, E1000_IAC); 2711 temp = E1000_READ_REG(hw, E1000_ICRXOC); 2712} 2713 2714