e1000_ich8lan.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_ich8lan.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36/* e1000_ich8lan 37 * e1000_ich9lan 38 */ 39 40#include "e1000_api.h" 41#include "e1000_ich8lan.h" 42 43STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 44STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 45STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 46STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 47STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 48STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 49STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 50STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 51STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 52STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 53STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 54STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 55 bool active); 56STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 57 bool active); 58STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 59 u16 words, u16 *data); 60STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 61 u16 words, u16 *data); 62STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 63STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 64STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 65 u16 *data); 66STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 67STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 68STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 69STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 70STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 71STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 72 u16 *speed, u16 *duplex); 73STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 74STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 75STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 76STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 77STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 78static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 79static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 80static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 81static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 82static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 83STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 84 u32 offset, u8* data); 85static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 86 u8 size, u16* data); 87STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 88 u32 offset, u16 *data); 89static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 90 u32 offset, u8 byte); 91STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 92 u32 offset, u8 data); 93static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 94 u8 size, u16 data); 95STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 96STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 97 98/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 99/* Offset 04h HSFSTS */ 100union ich8_hws_flash_status { 101 struct ich8_hsfsts { 102 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 103 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 104 u16 dael :1; /* bit 2 Direct Access error Log */ 105 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 106 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 107 u16 reserved1 :2; /* bit 13:6 Reserved */ 108 u16 reserved2 :6; /* bit 13:6 Reserved */ 109 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 110 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 111 } hsf_status; 112 u16 regval; 113}; 114 115/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 116/* Offset 06h FLCTL */ 117union ich8_hws_flash_ctrl { 118 struct ich8_hsflctl { 119 u16 flcgo :1; /* 0 Flash Cycle Go */ 120 u16 flcycle :2; /* 2:1 Flash Cycle */ 121 u16 reserved :5; /* 7:3 Reserved */ 122 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 123 u16 flockdn :6; /* 15:10 Reserved */ 124 } hsf_ctrl; 125 u16 regval; 126}; 127 128/* ICH Flash Region Access Permissions */ 129union ich8_hws_flash_regacc { 130 struct ich8_flracc { 131 u32 grra :8; /* 0:7 GbE region Read Access */ 132 u32 grwa :8; /* 8:15 GbE region Write Access */ 133 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 134 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 135 } hsf_flregacc; 136 u16 regval; 137}; 138 139struct e1000_shadow_ram { 140 u16 value; 141 bool modified; 142}; 143 144struct e1000_dev_spec_ich8lan { 145 bool kmrn_lock_loss_workaround_enabled; 146 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 147}; 148 149/** 150 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 151 * @hw: pointer to the HW structure 152 * 153 * Initialize family-specific PHY parameters and function pointers. 154 **/ 155STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 156{ 157 struct e1000_phy_info *phy = &hw->phy; 158 struct e1000_functions *func = &hw->func; 159 s32 ret_val = E1000_SUCCESS; 160 u16 i = 0; 161 162 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 163 164 phy->addr = 1; 165 phy->reset_delay_us = 100; 166 167 func->acquire_phy = e1000_acquire_swflag_ich8lan; 168 func->check_polarity = e1000_check_polarity_ife_ich8lan; 169 func->check_reset_block = e1000_check_reset_block_ich8lan; 170 func->force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 171 func->get_cable_length = e1000_get_cable_length_igp_2; 172 func->get_cfg_done = e1000_get_cfg_done_ich8lan; 173 func->get_phy_info = e1000_get_phy_info_ich8lan; 174 func->read_phy_reg = e1000_read_phy_reg_igp; 175 func->release_phy = e1000_release_swflag_ich8lan; 176 func->reset_phy = e1000_phy_hw_reset_ich8lan; 177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 179 func->write_phy_reg = e1000_write_phy_reg_igp; 180 func->power_up_phy = e1000_power_up_phy_copper; 181 func->power_down_phy = e1000_power_down_phy_copper_ich8lan; 182 183 /* 184 * We may need to do this twice - once for IGP and if that fails, 185 * we'll set BM func pointers and try again 186 */ 187 ret_val = e1000_determine_phy_address(hw); 188 if (ret_val) { 189 func->write_phy_reg = e1000_write_phy_reg_bm; 190 func->read_phy_reg = e1000_read_phy_reg_bm; 191 ret_val = e1000_determine_phy_address(hw); 192 if (ret_val) { 193 DEBUGOUT("Cannot determine PHY address. Erroring out\n"); 194 goto out; 195 } 196 } 197 198 phy->id = 0; 199 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 200 (i++ < 100)) { 201 msec_delay(1); 202 ret_val = e1000_get_phy_id(hw); 203 if (ret_val) 204 goto out; 205 } 206 207 /* Verify phy id */ 208 switch (phy->id) { 209 case IGP03E1000_E_PHY_ID: 210 phy->type = e1000_phy_igp_3; 211 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 212 break; 213 case IFE_E_PHY_ID: 214 case IFE_PLUS_E_PHY_ID: 215 case IFE_C_E_PHY_ID: 216 phy->type = e1000_phy_ife; 217 phy->autoneg_mask = E1000_ALL_NOT_GIG; 218 break; 219 case BME1000_E_PHY_ID: 220 phy->type = e1000_phy_bm; 221 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 222 func->read_phy_reg = e1000_read_phy_reg_bm; 223 func->write_phy_reg = e1000_write_phy_reg_bm; 224 func->commit_phy = e1000_phy_sw_reset_generic; 225 break; 226 default: 227 ret_val = -E1000_ERR_PHY; 228 goto out; 229 } 230 231out: 232 return ret_val; 233} 234 235/** 236 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 237 * @hw: pointer to the HW structure 238 * 239 * Initialize family-specific NVM parameters and function 240 * pointers. 241 **/ 242STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 243{ 244 struct e1000_nvm_info *nvm = &hw->nvm; 245 struct e1000_functions *func = &hw->func; 246 struct e1000_dev_spec_ich8lan *dev_spec; 247 u32 gfpreg, sector_base_addr, sector_end_addr; 248 s32 ret_val = E1000_SUCCESS; 249 u16 i; 250 251 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 252 253 /* Can't read flash registers if the register set isn't mapped. */ 254 if (!hw->flash_address) { 255 DEBUGOUT("ERROR: Flash registers not mapped\n"); 256 ret_val = -E1000_ERR_CONFIG; 257 goto out; 258 } 259 260 nvm->type = e1000_nvm_flash_sw; 261 262 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 263 264 /* 265 * sector_X_addr is a "sector"-aligned address (4096 bytes) 266 * Add 1 to sector_end_addr since this sector is included in 267 * the overall size. 268 */ 269 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 270 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 271 272 /* flash_base_addr is byte-aligned */ 273 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 274 275 /* 276 * find total size of the NVM, then cut in half since the total 277 * size represents two separate NVM banks. 278 */ 279 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 280 << FLASH_SECTOR_ADDR_SHIFT; 281 nvm->flash_bank_size /= 2; 282 /* Adjust to word count */ 283 nvm->flash_bank_size /= sizeof(u16); 284 285 nvm->word_size = E1000_SHADOW_RAM_WORDS; 286 287 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 288 289 if (!dev_spec) { 290 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 291 ret_val = -E1000_ERR_CONFIG; 292 goto out; 293 } 294 295 /* Clear shadow ram */ 296 for (i = 0; i < nvm->word_size; i++) { 297 dev_spec->shadow_ram[i].modified = FALSE; 298 dev_spec->shadow_ram[i].value = 0xFFFF; 299 } 300 301 /* Function Pointers */ 302 func->acquire_nvm = e1000_acquire_swflag_ich8lan; 303 func->read_nvm = e1000_read_nvm_ich8lan; 304 func->release_nvm = e1000_release_swflag_ich8lan; 305 func->update_nvm = e1000_update_nvm_checksum_ich8lan; 306 func->valid_led_default = e1000_valid_led_default_ich8lan; 307 func->validate_nvm = e1000_validate_nvm_checksum_ich8lan; 308 func->write_nvm = e1000_write_nvm_ich8lan; 309 310out: 311 return ret_val; 312} 313 314/** 315 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 316 * @hw: pointer to the HW structure 317 * 318 * Initialize family-specific MAC parameters and function 319 * pointers. 320 **/ 321STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 322{ 323 struct e1000_mac_info *mac = &hw->mac; 324 struct e1000_functions *func = &hw->func; 325 s32 ret_val = E1000_SUCCESS; 326 327 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 328 329 /* Set media type function pointer */ 330 hw->phy.media_type = e1000_media_type_copper; 331 332 /* Set mta register count */ 333 mac->mta_reg_count = 32; 334 /* Set rar entry count */ 335 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 336 if (mac->type == e1000_ich8lan) 337 mac->rar_entry_count--; 338 /* Set if part includes ASF firmware */ 339 mac->asf_firmware_present = TRUE; 340 /* Set if manageability features are enabled. */ 341 mac->arc_subsystem_valid = TRUE; 342 343 /* Function pointers */ 344 345 /* bus type/speed/width */ 346 func->get_bus_info = e1000_get_bus_info_ich8lan; 347 /* reset */ 348 func->reset_hw = e1000_reset_hw_ich8lan; 349 /* hw initialization */ 350 func->init_hw = e1000_init_hw_ich8lan; 351 /* link setup */ 352 func->setup_link = e1000_setup_link_ich8lan; 353 /* physical interface setup */ 354 func->setup_physical_interface = e1000_setup_copper_link_ich8lan; 355 /* check for link */ 356 func->check_for_link = e1000_check_for_copper_link_generic; 357 /* check management mode */ 358 func->check_mng_mode = e1000_check_mng_mode_ich8lan; 359 /* link info */ 360 func->get_link_up_info = e1000_get_link_up_info_ich8lan; 361 /* multicast address update */ 362 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 363 /* setting MTA */ 364 func->mta_set = e1000_mta_set_generic; 365 /* blink LED */ 366 func->blink_led = e1000_blink_led_generic; 367 /* setup LED */ 368 func->setup_led = e1000_setup_led_generic; 369 /* cleanup LED */ 370 func->cleanup_led = e1000_cleanup_led_ich8lan; 371 /* turn on/off LED */ 372 func->led_on = e1000_led_on_ich8lan; 373 func->led_off = e1000_led_off_ich8lan; 374 /* remove device */ 375 func->remove_device = e1000_remove_device_generic; 376 /* clear hardware counters */ 377 func->clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 378 379 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan); 380 381 /* Device-specific structure allocation */ 382 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 383 if (ret_val) 384 goto out; 385 386 /* Enable PCS Lock-loss workaround for ICH8 */ 387 if (mac->type == e1000_ich8lan) 388 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 389 390 391out: 392 return ret_val; 393} 394 395/** 396 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 397 * @hw: pointer to the HW structure 398 * 399 * Initialize family-specific function pointers for PHY, MAC, and NVM. 400 **/ 401void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 402{ 403 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 404 405 hw->func.init_mac_params = e1000_init_mac_params_ich8lan; 406 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan; 407 hw->func.init_phy_params = e1000_init_phy_params_ich8lan; 408} 409 410/** 411 * e1000_acquire_swflag_ich8lan - Acquire software control flag 412 * @hw: pointer to the HW structure 413 * 414 * Acquires the software control flag for performing NVM and PHY 415 * operations. This is a function pointer entry point only called by 416 * read/write routines for the PHY and NVM parts. 417 **/ 418STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 419{ 420 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 421 s32 ret_val = E1000_SUCCESS; 422 423 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 424 425 while (timeout) { 426 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 427 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 428 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 429 430 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 431 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 432 break; 433 msec_delay_irq(1); 434 timeout--; 435 } 436 437 if (!timeout) { 438 DEBUGOUT("FW or HW has locked the resource for too long.\n"); 439 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 440 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 441 ret_val = -E1000_ERR_CONFIG; 442 goto out; 443 } 444 445out: 446 return ret_val; 447} 448 449/** 450 * e1000_release_swflag_ich8lan - Release software control flag 451 * @hw: pointer to the HW structure 452 * 453 * Releases the software control flag for performing NVM and PHY operations. 454 * This is a function pointer entry point only called by read/write 455 * routines for the PHY and NVM parts. 456 **/ 457STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 458{ 459 u32 extcnf_ctrl; 460 461 DEBUGFUNC("e1000_release_swflag_ich8lan"); 462 463 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 464 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 465 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 466 467 return; 468} 469 470/** 471 * e1000_check_mng_mode_ich8lan - Checks management mode 472 * @hw: pointer to the HW structure 473 * 474 * This checks if the adapter has manageability enabled. 475 * This is a function pointer entry point only called by read/write 476 * routines for the PHY and NVM parts. 477 **/ 478STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 479{ 480 u32 fwsm; 481 482 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 483 484 fwsm = E1000_READ_REG(hw, E1000_FWSM); 485 486 return ((fwsm & E1000_FWSM_MODE_MASK) == 487 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 488} 489 490/** 491 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 492 * @hw: pointer to the HW structure 493 * 494 * Checks if firmware is blocking the reset of the PHY. 495 * This is a function pointer entry point only called by 496 * reset routines. 497 **/ 498STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 499{ 500 u32 fwsm; 501 502 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 503 504 fwsm = E1000_READ_REG(hw, E1000_FWSM); 505 506 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 507 : E1000_BLK_PHY_RESET; 508} 509 510/** 511 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 512 * @hw: pointer to the HW structure 513 * 514 * Forces the speed and duplex settings of the PHY. 515 * This is a function pointer entry point only called by 516 * PHY setup routines. 517 **/ 518STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 519{ 520 struct e1000_phy_info *phy = &hw->phy; 521 s32 ret_val; 522 u16 data; 523 bool link; 524 525 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 526 527 if (phy->type != e1000_phy_ife) { 528 ret_val = e1000_phy_force_speed_duplex_igp(hw); 529 goto out; 530 } 531 532 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &data); 533 if (ret_val) 534 goto out; 535 536 e1000_phy_force_speed_duplex_setup(hw, &data); 537 538 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, data); 539 if (ret_val) 540 goto out; 541 542 /* Disable MDI-X support for 10/100 */ 543 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 544 if (ret_val) 545 goto out; 546 547 data &= ~IFE_PMC_AUTO_MDIX; 548 data &= ~IFE_PMC_FORCE_MDIX; 549 550 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data); 551 if (ret_val) 552 goto out; 553 554 DEBUGOUT1("IFE PMC: %X\n", data); 555 556 usec_delay(1); 557 558 if (phy->autoneg_wait_to_complete) { 559 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 560 561 ret_val = e1000_phy_has_link_generic(hw, 562 PHY_FORCE_LIMIT, 563 100000, 564 &link); 565 if (ret_val) 566 goto out; 567 568 if (!link) { 569 DEBUGOUT("Link taking longer than expected.\n"); 570 } 571 572 /* Try once more */ 573 ret_val = e1000_phy_has_link_generic(hw, 574 PHY_FORCE_LIMIT, 575 100000, 576 &link); 577 if (ret_val) 578 goto out; 579 } 580 581out: 582 return ret_val; 583} 584 585/** 586 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 587 * @hw: pointer to the HW structure 588 * 589 * Resets the PHY 590 * This is a function pointer entry point called by drivers 591 * or other shared routines. 592 **/ 593STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 594{ 595 struct e1000_phy_info *phy = &hw->phy; 596 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 597 s32 ret_val; 598 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 599 u16 word_addr, reg_data, reg_addr, phy_page = 0; 600 601 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 602 603 ret_val = e1000_phy_hw_reset_generic(hw); 604 if (ret_val) 605 goto out; 606 607 /* 608 * Initialize the PHY from the NVM on ICH platforms. This 609 * is needed due to an issue where the NVM configuration is 610 * not properly autoloaded after power transitions. 611 * Therefore, after each PHY reset, we will load the 612 * configuration data out of the NVM manually. 613 */ 614 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 615 /* Check if SW needs configure the PHY */ 616 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 617 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 618 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 619 else 620 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 621 622 data = E1000_READ_REG(hw, E1000_FEXTNVM); 623 if (!(data & sw_cfg_mask)) 624 goto out; 625 626 /* Wait for basic configuration completes before proceeding*/ 627 do { 628 data = E1000_READ_REG(hw, E1000_STATUS); 629 data &= E1000_STATUS_LAN_INIT_DONE; 630 usec_delay(100); 631 } while ((!data) && --loop); 632 633 /* 634 * If basic configuration is incomplete before the above loop 635 * count reaches 0, loading the configuration from NVM will 636 * leave the PHY in a bad state possibly resulting in no link. 637 */ 638 if (loop == 0) { 639 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 640 } 641 642 /* Clear the Init Done bit for the next init event */ 643 data = E1000_READ_REG(hw, E1000_STATUS); 644 data &= ~E1000_STATUS_LAN_INIT_DONE; 645 E1000_WRITE_REG(hw, E1000_STATUS, data); 646 647 /* 648 * Make sure HW does not configure LCD from PHY 649 * extended configuration before SW configuration 650 */ 651 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 652 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 653 goto out; 654 655 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 656 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 657 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 658 if (!cnf_size) 659 goto out; 660 661 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 662 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 663 664 /* 665 * Configure LCD from extended configuration 666 * region. 667 */ 668 669 /* cnf_base_addr is in DWORD */ 670 word_addr = (u16)(cnf_base_addr << 1); 671 672 for (i = 0; i < cnf_size; i++) { 673 ret_val = e1000_read_nvm(hw, 674 (word_addr + i * 2), 675 1, 676 ®_data); 677 if (ret_val) 678 goto out; 679 680 ret_val = e1000_read_nvm(hw, 681 (word_addr + i * 2 + 1), 682 1, 683 ®_addr); 684 if (ret_val) 685 goto out; 686 687 /* Save off the PHY page for future writes. */ 688 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 689 phy_page = reg_data; 690 continue; 691 } 692 693 reg_addr |= phy_page; 694 695 ret_val = e1000_write_phy_reg(hw, 696 (u32)reg_addr, 697 reg_data); 698 if (ret_val) 699 goto out; 700 } 701 } 702 703out: 704 return ret_val; 705} 706 707/** 708 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 709 * @hw: pointer to the HW structure 710 * 711 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 712 * This is a function pointer entry point called by drivers 713 * or other shared routines. 714 **/ 715STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 716{ 717 s32 ret_val = -E1000_ERR_PHY_TYPE; 718 719 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 720 721 switch (hw->phy.type) { 722 case e1000_phy_ife: 723 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 724 break; 725 case e1000_phy_igp_3: 726 case e1000_phy_bm: 727 ret_val = e1000_get_phy_info_igp(hw); 728 break; 729 default: 730 break; 731 } 732 733 return ret_val; 734} 735 736/** 737 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 738 * @hw: pointer to the HW structure 739 * 740 * Populates "phy" structure with various feature states. 741 * This function is only called by other family-specific 742 * routines. 743 **/ 744static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 745{ 746 struct e1000_phy_info *phy = &hw->phy; 747 s32 ret_val; 748 u16 data; 749 bool link; 750 751 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 752 753 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 754 if (ret_val) 755 goto out; 756 757 if (!link) { 758 DEBUGOUT("Phy info is only valid if link is up\n"); 759 ret_val = -E1000_ERR_CONFIG; 760 goto out; 761 } 762 763 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 764 if (ret_val) 765 goto out; 766 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 767 ? FALSE : TRUE; 768 769 if (phy->polarity_correction) { 770 ret_val = e1000_check_polarity_ife_ich8lan(hw); 771 if (ret_val) 772 goto out; 773 } else { 774 /* Polarity is forced */ 775 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 776 ? e1000_rev_polarity_reversed 777 : e1000_rev_polarity_normal; 778 } 779 780 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 781 if (ret_val) 782 goto out; 783 784 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 785 786 /* The following parameters are undefined for 10/100 operation. */ 787 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 788 phy->local_rx = e1000_1000t_rx_status_undefined; 789 phy->remote_rx = e1000_1000t_rx_status_undefined; 790 791out: 792 return ret_val; 793} 794 795/** 796 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 797 * @hw: pointer to the HW structure 798 * 799 * Polarity is determined on the polarity reversal feature being enabled. 800 * This function is only called by other family-specific 801 * routines. 802 **/ 803STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 804{ 805 struct e1000_phy_info *phy = &hw->phy; 806 s32 ret_val; 807 u16 phy_data, offset, mask; 808 809 DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 810 811 /* 812 * Polarity is determined based on the reversal feature 813 * being enabled. 814 */ 815 if (phy->polarity_correction) { 816 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 817 mask = IFE_PESC_POLARITY_REVERSED; 818 } else { 819 offset = IFE_PHY_SPECIAL_CONTROL; 820 mask = IFE_PSC_FORCE_POLARITY; 821 } 822 823 ret_val = e1000_read_phy_reg(hw, offset, &phy_data); 824 825 if (!ret_val) 826 phy->cable_polarity = (phy_data & mask) 827 ? e1000_rev_polarity_reversed 828 : e1000_rev_polarity_normal; 829 830 return ret_val; 831} 832 833/** 834 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 835 * @hw: pointer to the HW structure 836 * @active: TRUE to enable LPLU, FALSE to disable 837 * 838 * Sets the LPLU D0 state according to the active flag. When 839 * activating LPLU this function also disables smart speed 840 * and vice versa. LPLU will not be activated unless the 841 * device autonegotiation advertisement meets standards of 842 * either 10 or 10/100 or 10/100/1000 at all duplexes. 843 * This is a function pointer entry point only called by 844 * PHY setup routines. 845 **/ 846STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 847 bool active) 848{ 849 struct e1000_phy_info *phy = &hw->phy; 850 u32 phy_ctrl; 851 s32 ret_val = E1000_SUCCESS; 852 u16 data; 853 854 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 855 856 if (phy->type == e1000_phy_ife) 857 goto out; 858 859 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 860 861 if (active) { 862 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 863 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 864 865 /* 866 * Call gig speed drop workaround on LPLU before accessing 867 * any PHY registers 868 */ 869 if ((hw->mac.type == e1000_ich8lan) && 870 (hw->phy.type == e1000_phy_igp_3)) 871 e1000_gig_downshift_workaround_ich8lan(hw); 872 873 /* When LPLU is enabled, we should disable SmartSpeed */ 874 ret_val = e1000_read_phy_reg(hw, 875 IGP01E1000_PHY_PORT_CONFIG, 876 &data); 877 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 878 ret_val = e1000_write_phy_reg(hw, 879 IGP01E1000_PHY_PORT_CONFIG, 880 data); 881 if (ret_val) 882 goto out; 883 } else { 884 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 885 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 886 887 /* 888 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 889 * during Dx states where the power conservation is most 890 * important. During driver activity we should enable 891 * SmartSpeed, so performance is maintained. 892 */ 893 if (phy->smart_speed == e1000_smart_speed_on) { 894 ret_val = e1000_read_phy_reg(hw, 895 IGP01E1000_PHY_PORT_CONFIG, 896 &data); 897 if (ret_val) 898 goto out; 899 900 data |= IGP01E1000_PSCFR_SMART_SPEED; 901 ret_val = e1000_write_phy_reg(hw, 902 IGP01E1000_PHY_PORT_CONFIG, 903 data); 904 if (ret_val) 905 goto out; 906 } else if (phy->smart_speed == e1000_smart_speed_off) { 907 ret_val = e1000_read_phy_reg(hw, 908 IGP01E1000_PHY_PORT_CONFIG, 909 &data); 910 if (ret_val) 911 goto out; 912 913 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 914 ret_val = e1000_write_phy_reg(hw, 915 IGP01E1000_PHY_PORT_CONFIG, 916 data); 917 if (ret_val) 918 goto out; 919 } 920 } 921 922out: 923 return ret_val; 924} 925 926/** 927 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 928 * @hw: pointer to the HW structure 929 * @active: TRUE to enable LPLU, FALSE to disable 930 * 931 * Sets the LPLU D3 state according to the active flag. When 932 * activating LPLU this function also disables smart speed 933 * and vice versa. LPLU will not be activated unless the 934 * device autonegotiation advertisement meets standards of 935 * either 10 or 10/100 or 10/100/1000 at all duplexes. 936 * This is a function pointer entry point only called by 937 * PHY setup routines. 938 **/ 939STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 940 bool active) 941{ 942 struct e1000_phy_info *phy = &hw->phy; 943 u32 phy_ctrl; 944 s32 ret_val = E1000_SUCCESS; 945 u16 data; 946 947 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 948 949 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 950 951 if (!active) { 952 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 953 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 954 /* 955 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 956 * during Dx states where the power conservation is most 957 * important. During driver activity we should enable 958 * SmartSpeed, so performance is maintained. 959 */ 960 if (phy->smart_speed == e1000_smart_speed_on) { 961 ret_val = e1000_read_phy_reg(hw, 962 IGP01E1000_PHY_PORT_CONFIG, 963 &data); 964 if (ret_val) 965 goto out; 966 967 data |= IGP01E1000_PSCFR_SMART_SPEED; 968 ret_val = e1000_write_phy_reg(hw, 969 IGP01E1000_PHY_PORT_CONFIG, 970 data); 971 if (ret_val) 972 goto out; 973 } else if (phy->smart_speed == e1000_smart_speed_off) { 974 ret_val = e1000_read_phy_reg(hw, 975 IGP01E1000_PHY_PORT_CONFIG, 976 &data); 977 if (ret_val) 978 goto out; 979 980 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 981 ret_val = e1000_write_phy_reg(hw, 982 IGP01E1000_PHY_PORT_CONFIG, 983 data); 984 if (ret_val) 985 goto out; 986 } 987 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 988 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 989 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 990 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 991 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 992 993 /* 994 * Call gig speed drop workaround on LPLU before accessing 995 * any PHY registers 996 */ 997 if ((hw->mac.type == e1000_ich8lan) && 998 (hw->phy.type == e1000_phy_igp_3)) 999 e1000_gig_downshift_workaround_ich8lan(hw); 1000 1001 /* When LPLU is enabled, we should disable SmartSpeed */ 1002 ret_val = e1000_read_phy_reg(hw, 1003 IGP01E1000_PHY_PORT_CONFIG, 1004 &data); 1005 if (ret_val) 1006 goto out; 1007 1008 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1009 ret_val = e1000_write_phy_reg(hw, 1010 IGP01E1000_PHY_PORT_CONFIG, 1011 data); 1012 } 1013 1014out: 1015 return ret_val; 1016} 1017 1018/** 1019 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1020 * @hw: pointer to the HW structure 1021 * @bank: pointer to the variable that returns the active bank 1022 * 1023 * Reads signature byte from the NVM using the flash access registers. 1024 **/ 1025STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1026{ 1027 s32 ret_val = E1000_SUCCESS; 1028 struct e1000_nvm_info *nvm = &hw->nvm; 1029 /* flash bank size is in words */ 1030 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1031 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1032 u8 bank_high_byte = 0; 1033 1034 if (hw->mac.type != e1000_ich10lan) { 1035 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) 1036 *bank = 1; 1037 else 1038 *bank = 0; 1039 } else if (hw->dev_spec != NULL) { 1040 /* 1041 * Make sure the signature for bank 0 is valid, 1042 * if not check for bank1 1043 */ 1044 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte); 1045 if ((bank_high_byte & 0xC0) == 0x80) { 1046 *bank = 0; 1047 } else { 1048 /* 1049 * find if segment 1 is valid by verifying 1050 * bit 15:14 = 10b in word 0x13 1051 */ 1052 e1000_read_flash_byte_ich8lan(hw, 1053 act_offset + bank1_offset, 1054 &bank_high_byte); 1055 1056 /* bank1 has a valid signature equivalent to SEC1V */ 1057 if ((bank_high_byte & 0xC0) == 0x80) { 1058 *bank = 1; 1059 } else { 1060 DEBUGOUT("ERROR: EEPROM not present\n"); 1061 ret_val = -E1000_ERR_NVM; 1062 } 1063 } 1064 } else { 1065 DEBUGOUT("DEV SPEC is NULL\n"); 1066 ret_val = -E1000_ERR_NVM; 1067 } 1068 1069 return ret_val; 1070} 1071 1072/** 1073 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1074 * @hw: pointer to the HW structure 1075 * @offset: The offset (in bytes) of the word(s) to read. 1076 * @words: Size of data to read in words 1077 * @data: Pointer to the word(s) to read at offset. 1078 * 1079 * Reads a word(s) from the NVM using the flash access registers. 1080 **/ 1081STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1082 u16 *data) 1083{ 1084 struct e1000_nvm_info *nvm = &hw->nvm; 1085 struct e1000_dev_spec_ich8lan *dev_spec; 1086 u32 act_offset; 1087 s32 ret_val = E1000_SUCCESS; 1088 u32 bank = 0; 1089 u16 i, word; 1090 1091 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1092 1093 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1094 1095 if (!dev_spec) { 1096 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1097 ret_val = -E1000_ERR_CONFIG; 1098 goto out; 1099 } 1100 1101 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1102 (words == 0)) { 1103 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1104 ret_val = -E1000_ERR_NVM; 1105 goto out; 1106 } 1107 1108 ret_val = e1000_acquire_nvm(hw); 1109 if (ret_val) 1110 goto out; 1111 1112 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1113 if (ret_val != E1000_SUCCESS) 1114 goto out; 1115 1116 act_offset = (bank) ? nvm->flash_bank_size : 0; 1117 act_offset += offset; 1118 1119 for (i = 0; i < words; i++) { 1120 if ((dev_spec->shadow_ram) && 1121 (dev_spec->shadow_ram[offset+i].modified)) { 1122 data[i] = dev_spec->shadow_ram[offset+i].value; 1123 } else { 1124 ret_val = e1000_read_flash_word_ich8lan(hw, 1125 act_offset + i, 1126 &word); 1127 if (ret_val) 1128 break; 1129 data[i] = word; 1130 } 1131 } 1132 1133 e1000_release_nvm(hw); 1134 1135out: 1136 return ret_val; 1137} 1138 1139/** 1140 * e1000_flash_cycle_init_ich8lan - Initialize flash 1141 * @hw: pointer to the HW structure 1142 * 1143 * This function does initial flash setup so that a new read/write/erase cycle 1144 * can be started. 1145 **/ 1146static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1147{ 1148 union ich8_hws_flash_status hsfsts; 1149 s32 ret_val = -E1000_ERR_NVM; 1150 s32 i = 0; 1151 1152 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1153 1154 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1155 1156 /* Check if the flash descriptor is valid */ 1157 if (hsfsts.hsf_status.fldesvalid == 0) { 1158 DEBUGOUT("Flash descriptor invalid. " 1159 "SW Sequencing must be used."); 1160 goto out; 1161 } 1162 1163 /* Clear FCERR and DAEL in hw status by writing 1 */ 1164 hsfsts.hsf_status.flcerr = 1; 1165 hsfsts.hsf_status.dael = 1; 1166 1167 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1168 1169 /* 1170 * Either we should have a hardware SPI cycle in progress 1171 * bit to check against, in order to start a new cycle or 1172 * FDONE bit should be changed in the hardware so that it 1173 * is 1 after hardware reset, which can then be used as an 1174 * indication whether a cycle is in progress or has been 1175 * completed. 1176 */ 1177 1178 if (hsfsts.hsf_status.flcinprog == 0) { 1179 /* 1180 * There is no cycle running at present, 1181 * so we can start a cycle. 1182 * Begin by setting Flash Cycle Done. 1183 */ 1184 hsfsts.hsf_status.flcdone = 1; 1185 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1186 ret_val = E1000_SUCCESS; 1187 } else { 1188 /* 1189 * Otherwise poll for sometime so the current 1190 * cycle has a chance to end before giving up. 1191 */ 1192 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1193 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1194 ICH_FLASH_HSFSTS); 1195 if (hsfsts.hsf_status.flcinprog == 0) { 1196 ret_val = E1000_SUCCESS; 1197 break; 1198 } 1199 usec_delay(1); 1200 } 1201 if (ret_val == E1000_SUCCESS) { 1202 /* 1203 * Successful in waiting for previous cycle to timeout, 1204 * now set the Flash Cycle Done. 1205 */ 1206 hsfsts.hsf_status.flcdone = 1; 1207 E1000_WRITE_FLASH_REG16(hw, 1208 ICH_FLASH_HSFSTS, 1209 hsfsts.regval); 1210 } else { 1211 DEBUGOUT("Flash controller busy, cannot get access"); 1212 } 1213 } 1214 1215out: 1216 return ret_val; 1217} 1218 1219/** 1220 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1221 * @hw: pointer to the HW structure 1222 * @timeout: maximum time to wait for completion 1223 * 1224 * This function starts a flash cycle and waits for its completion. 1225 **/ 1226static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1227{ 1228 union ich8_hws_flash_ctrl hsflctl; 1229 union ich8_hws_flash_status hsfsts; 1230 s32 ret_val = -E1000_ERR_NVM; 1231 u32 i = 0; 1232 1233 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1234 1235 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1236 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1237 hsflctl.hsf_ctrl.flcgo = 1; 1238 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1239 1240 /* wait till FDONE bit is set to 1 */ 1241 do { 1242 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1243 if (hsfsts.hsf_status.flcdone == 1) 1244 break; 1245 usec_delay(1); 1246 } while (i++ < timeout); 1247 1248 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1249 ret_val = E1000_SUCCESS; 1250 1251 return ret_val; 1252} 1253 1254/** 1255 * e1000_read_flash_word_ich8lan - Read word from flash 1256 * @hw: pointer to the HW structure 1257 * @offset: offset to data location 1258 * @data: pointer to the location for storing the data 1259 * 1260 * Reads the flash word at offset into data. Offset is converted 1261 * to bytes before read. 1262 **/ 1263STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1264 u16 *data) 1265{ 1266 s32 ret_val; 1267 1268 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1269 1270 if (!data) { 1271 ret_val = -E1000_ERR_NVM; 1272 goto out; 1273 } 1274 1275 /* Must convert offset into bytes. */ 1276 offset <<= 1; 1277 1278 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1279 1280out: 1281 return ret_val; 1282} 1283 1284/** 1285 * e1000_read_flash_byte_ich8lan - Read byte from flash 1286 * @hw: pointer to the HW structure 1287 * @offset: The offset of the byte to read. 1288 * @data: Pointer to a byte to store the value read. 1289 * 1290 * Reads a single byte from the NVM using the flash access registers. 1291 **/ 1292STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1293 u8* data) 1294{ 1295 s32 ret_val = E1000_SUCCESS; 1296 u16 word = 0; 1297 1298 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1299 if (ret_val) 1300 goto out; 1301 1302 *data = (u8)word; 1303 1304out: 1305 return ret_val; 1306} 1307 1308/** 1309 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1310 * @hw: pointer to the HW structure 1311 * @offset: The offset (in bytes) of the byte or word to read. 1312 * @size: Size of data to read, 1=byte 2=word 1313 * @data: Pointer to the word to store the value read. 1314 * 1315 * Reads a byte or word from the NVM using the flash access registers. 1316 **/ 1317static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1318 u8 size, u16* data) 1319{ 1320 union ich8_hws_flash_status hsfsts; 1321 union ich8_hws_flash_ctrl hsflctl; 1322 u32 flash_linear_addr; 1323 u32 flash_data = 0; 1324 s32 ret_val = -E1000_ERR_NVM; 1325 u8 count = 0; 1326 1327 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1328 1329 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1330 goto out; 1331 1332 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1333 hw->nvm.flash_base_addr; 1334 1335 do { 1336 usec_delay(1); 1337 /* Steps */ 1338 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1339 if (ret_val != E1000_SUCCESS) 1340 break; 1341 1342 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1343 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1344 hsflctl.hsf_ctrl.fldbcount = size - 1; 1345 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1346 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1347 1348 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1349 1350 ret_val = e1000_flash_cycle_ich8lan(hw, 1351 ICH_FLASH_READ_COMMAND_TIMEOUT); 1352 1353 /* 1354 * Check if FCERR is set to 1, if set to 1, clear it 1355 * and try the whole sequence a few more times, else 1356 * read in (shift in) the Flash Data0, the order is 1357 * least significant byte first msb to lsb 1358 */ 1359 if (ret_val == E1000_SUCCESS) { 1360 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1361 if (size == 1) { 1362 *data = (u8)(flash_data & 0x000000FF); 1363 } else if (size == 2) { 1364 *data = (u16)(flash_data & 0x0000FFFF); 1365 } 1366 break; 1367 } else { 1368 /* 1369 * If we've gotten here, then things are probably 1370 * completely hosed, but if the error condition is 1371 * detected, it won't hurt to give it another try... 1372 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1373 */ 1374 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1375 ICH_FLASH_HSFSTS); 1376 if (hsfsts.hsf_status.flcerr == 1) { 1377 /* Repeat for some time before giving up. */ 1378 continue; 1379 } else if (hsfsts.hsf_status.flcdone == 0) { 1380 DEBUGOUT("Timeout error - flash cycle " 1381 "did not complete."); 1382 break; 1383 } 1384 } 1385 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1386 1387out: 1388 return ret_val; 1389} 1390 1391/** 1392 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1393 * @hw: pointer to the HW structure 1394 * @offset: The offset (in bytes) of the word(s) to write. 1395 * @words: Size of data to write in words 1396 * @data: Pointer to the word(s) to write at offset. 1397 * 1398 * Writes a byte or word to the NVM using the flash access registers. 1399 **/ 1400STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1401 u16 *data) 1402{ 1403 struct e1000_nvm_info *nvm = &hw->nvm; 1404 struct e1000_dev_spec_ich8lan *dev_spec; 1405 s32 ret_val = E1000_SUCCESS; 1406 u16 i; 1407 1408 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1409 1410 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1411 1412 if (!dev_spec) { 1413 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1414 ret_val = -E1000_ERR_CONFIG; 1415 goto out; 1416 } 1417 1418 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1419 (words == 0)) { 1420 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1421 ret_val = -E1000_ERR_NVM; 1422 goto out; 1423 } 1424 1425 ret_val = e1000_acquire_nvm(hw); 1426 if (ret_val) 1427 goto out; 1428 1429 for (i = 0; i < words; i++) { 1430 dev_spec->shadow_ram[offset+i].modified = TRUE; 1431 dev_spec->shadow_ram[offset+i].value = data[i]; 1432 } 1433 1434 e1000_release_nvm(hw); 1435 1436out: 1437 return ret_val; 1438} 1439 1440/** 1441 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1442 * @hw: pointer to the HW structure 1443 * 1444 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1445 * which writes the checksum to the shadow ram. The changes in the shadow 1446 * ram are then committed to the EEPROM by processing each bank at a time 1447 * checking for the modified bit and writing only the pending changes. 1448 * After a successful commit, the shadow ram is cleared and is ready for 1449 * future writes. 1450 **/ 1451STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1452{ 1453 struct e1000_nvm_info *nvm = &hw->nvm; 1454 struct e1000_dev_spec_ich8lan *dev_spec; 1455 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1456 s32 ret_val; 1457 u16 data; 1458 1459 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1460 1461 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1462 1463 ret_val = e1000_update_nvm_checksum_generic(hw); 1464 if (ret_val) 1465 goto out; 1466 1467 if (nvm->type != e1000_nvm_flash_sw) 1468 goto out; 1469 1470 ret_val = e1000_acquire_nvm(hw); 1471 if (ret_val) 1472 goto out; 1473 1474 /* 1475 * We're writing to the opposite bank so if we're on bank 1, 1476 * write to bank 0 etc. We also need to erase the segment that 1477 * is going to be written 1478 */ 1479 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1480 if (ret_val != E1000_SUCCESS) 1481 goto out; 1482 1483 if (bank == 0) { 1484 new_bank_offset = nvm->flash_bank_size; 1485 old_bank_offset = 0; 1486 e1000_erase_flash_bank_ich8lan(hw, 1); 1487 } else { 1488 old_bank_offset = nvm->flash_bank_size; 1489 new_bank_offset = 0; 1490 e1000_erase_flash_bank_ich8lan(hw, 0); 1491 } 1492 1493 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1494 /* 1495 * Determine whether to write the value stored 1496 * in the other NVM bank or a modified value stored 1497 * in the shadow RAM 1498 */ 1499 if (dev_spec->shadow_ram[i].modified) { 1500 data = dev_spec->shadow_ram[i].value; 1501 } else { 1502 e1000_read_flash_word_ich8lan(hw, 1503 i + old_bank_offset, 1504 &data); 1505 } 1506 1507 /* 1508 * If the word is 0x13, then make sure the signature bits 1509 * (15:14) are 11b until the commit has completed. 1510 * This will allow us to write 10b which indicates the 1511 * signature is valid. We want to do this after the write 1512 * has completed so that we don't mark the segment valid 1513 * while the write is still in progress 1514 */ 1515 if (i == E1000_ICH_NVM_SIG_WORD) 1516 data |= E1000_ICH_NVM_SIG_MASK; 1517 1518 /* Convert offset to bytes. */ 1519 act_offset = (i + new_bank_offset) << 1; 1520 1521 usec_delay(100); 1522 /* Write the bytes to the new bank. */ 1523 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1524 act_offset, 1525 (u8)data); 1526 if (ret_val) 1527 break; 1528 1529 usec_delay(100); 1530 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1531 act_offset + 1, 1532 (u8)(data >> 8)); 1533 if (ret_val) 1534 break; 1535 } 1536 1537 /* 1538 * Don't bother writing the segment valid bits if sector 1539 * programming failed. 1540 */ 1541 if (ret_val) { 1542 DEBUGOUT("Flash commit failed.\n"); 1543 e1000_release_nvm(hw); 1544 goto out; 1545 } 1546 1547 /* 1548 * Finally validate the new segment by setting bit 15:14 1549 * to 10b in word 0x13 , this can be done without an 1550 * erase as well since these bits are 11 to start with 1551 * and we need to change bit 14 to 0b 1552 */ 1553 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1554 e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1555 data &= 0xBFFF; 1556 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1557 act_offset * 2 + 1, 1558 (u8)(data >> 8)); 1559 if (ret_val) { 1560 e1000_release_nvm(hw); 1561 goto out; 1562 } 1563 1564 /* 1565 * And invalidate the previously valid segment by setting 1566 * its signature word (0x13) high_byte to 0b. This can be 1567 * done without an erase because flash erase sets all bits 1568 * to 1's. We can write 1's to 0's without an erase 1569 */ 1570 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1571 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1572 if (ret_val) { 1573 e1000_release_nvm(hw); 1574 goto out; 1575 } 1576 1577 /* Great! Everything worked, we can now clear the cached entries. */ 1578 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1579 dev_spec->shadow_ram[i].modified = FALSE; 1580 dev_spec->shadow_ram[i].value = 0xFFFF; 1581 } 1582 1583 e1000_release_nvm(hw); 1584 1585 /* 1586 * Reload the EEPROM, or else modifications will not appear 1587 * until after the next adapter reset. 1588 */ 1589 e1000_reload_nvm(hw); 1590 msec_delay(10); 1591 1592out: 1593 return ret_val; 1594} 1595 1596/** 1597 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1598 * @hw: pointer to the HW structure 1599 * 1600 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1601 * If the bit is 0, that the EEPROM had been modified, but the checksum was 1602 * not calculated, in which case we need to calculate the checksum and set 1603 * bit 6. 1604 **/ 1605STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1606{ 1607 s32 ret_val = E1000_SUCCESS; 1608 u16 data; 1609 1610 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1611 1612 /* 1613 * Read 0x19 and check bit 6. If this bit is 0, the checksum 1614 * needs to be fixed. This bit is an indication that the NVM 1615 * was prepared by OEM software and did not calculate the 1616 * checksum...a likely scenario. 1617 */ 1618 ret_val = e1000_read_nvm(hw, 0x19, 1, &data); 1619 if (ret_val) 1620 goto out; 1621 1622 if ((data & 0x40) == 0) { 1623 data |= 0x40; 1624 ret_val = e1000_write_nvm(hw, 0x19, 1, &data); 1625 if (ret_val) 1626 goto out; 1627 ret_val = e1000_update_nvm_checksum(hw); 1628 if (ret_val) 1629 goto out; 1630 } 1631 1632 ret_val = e1000_validate_nvm_checksum_generic(hw); 1633 1634out: 1635 return ret_val; 1636} 1637 1638/** 1639 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1640 * @hw: pointer to the HW structure 1641 * @offset: The offset (in bytes) of the byte/word to read. 1642 * @size: Size of data to read, 1=byte 2=word 1643 * @data: The byte(s) to write to the NVM. 1644 * 1645 * Writes one/two bytes to the NVM using the flash access registers. 1646 **/ 1647static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1648 u8 size, u16 data) 1649{ 1650 union ich8_hws_flash_status hsfsts; 1651 union ich8_hws_flash_ctrl hsflctl; 1652 u32 flash_linear_addr; 1653 u32 flash_data = 0; 1654 s32 ret_val = -E1000_ERR_NVM; 1655 u8 count = 0; 1656 1657 DEBUGFUNC("e1000_write_ich8_data"); 1658 1659 if (size < 1 || size > 2 || data > size * 0xff || 1660 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1661 goto out; 1662 1663 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1664 hw->nvm.flash_base_addr; 1665 1666 do { 1667 usec_delay(1); 1668 /* Steps */ 1669 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1670 if (ret_val != E1000_SUCCESS) 1671 break; 1672 1673 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1674 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1675 hsflctl.hsf_ctrl.fldbcount = size -1; 1676 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1677 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1678 1679 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1680 1681 if (size == 1) 1682 flash_data = (u32)data & 0x00FF; 1683 else 1684 flash_data = (u32)data; 1685 1686 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1687 1688 /* 1689 * check if FCERR is set to 1 , if set to 1, clear it 1690 * and try the whole sequence a few more times else done 1691 */ 1692 ret_val = e1000_flash_cycle_ich8lan(hw, 1693 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1694 if (ret_val == E1000_SUCCESS) { 1695 break; 1696 } else { 1697 /* 1698 * If we're here, then things are most likely 1699 * completely hosed, but if the error condition 1700 * is detected, it won't hurt to give it another 1701 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1702 */ 1703 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1704 ICH_FLASH_HSFSTS); 1705 if (hsfsts.hsf_status.flcerr == 1) { 1706 /* Repeat for some time before giving up. */ 1707 continue; 1708 } else if (hsfsts.hsf_status.flcdone == 0) { 1709 DEBUGOUT("Timeout error - flash cycle " 1710 "did not complete."); 1711 break; 1712 } 1713 } 1714 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1715 1716out: 1717 return ret_val; 1718} 1719 1720/** 1721 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1722 * @hw: pointer to the HW structure 1723 * @offset: The index of the byte to read. 1724 * @data: The byte to write to the NVM. 1725 * 1726 * Writes a single byte to the NVM using the flash access registers. 1727 **/ 1728STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1729 u8 data) 1730{ 1731 u16 word = (u16)data; 1732 1733 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1734 1735 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1736} 1737 1738/** 1739 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1740 * @hw: pointer to the HW structure 1741 * @offset: The offset of the byte to write. 1742 * @byte: The byte to write to the NVM. 1743 * 1744 * Writes a single byte to the NVM using the flash access registers. 1745 * Goes through a retry algorithm before giving up. 1746 **/ 1747static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1748 u32 offset, u8 byte) 1749{ 1750 s32 ret_val; 1751 u16 program_retries; 1752 1753 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1754 1755 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1756 if (ret_val == E1000_SUCCESS) 1757 goto out; 1758 1759 for (program_retries = 0; program_retries < 100; program_retries++) { 1760 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1761 usec_delay(100); 1762 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1763 if (ret_val == E1000_SUCCESS) 1764 break; 1765 } 1766 if (program_retries == 100) { 1767 ret_val = -E1000_ERR_NVM; 1768 goto out; 1769 } 1770 1771out: 1772 return ret_val; 1773} 1774 1775/** 1776 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1777 * @hw: pointer to the HW structure 1778 * @bank: 0 for first bank, 1 for second bank, etc. 1779 * 1780 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1781 * bank N is 4096 * N + flash_reg_addr. 1782 **/ 1783STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1784{ 1785 struct e1000_nvm_info *nvm = &hw->nvm; 1786 union ich8_hws_flash_status hsfsts; 1787 union ich8_hws_flash_ctrl hsflctl; 1788 u32 flash_linear_addr; 1789 /* bank size is in 16bit words - adjust to bytes */ 1790 u32 flash_bank_size = nvm->flash_bank_size * 2; 1791 s32 ret_val = E1000_SUCCESS; 1792 s32 count = 0; 1793 s32 j, iteration, sector_size; 1794 1795 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1796 1797 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1798 1799 /* 1800 * Determine HW Sector size: Read BERASE bits of hw flash status 1801 * register 1802 * 00: The Hw sector is 256 bytes, hence we need to erase 16 1803 * consecutive sectors. The start index for the nth Hw sector 1804 * can be calculated as = bank * 4096 + n * 256 1805 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1806 * The start index for the nth Hw sector can be calculated 1807 * as = bank * 4096 1808 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1809 * (ich9 only, otherwise error condition) 1810 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1811 */ 1812 switch (hsfsts.hsf_status.berasesz) { 1813 case 0: 1814 /* Hw sector size 256 */ 1815 sector_size = ICH_FLASH_SEG_SIZE_256; 1816 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1817 break; 1818 case 1: 1819 sector_size = ICH_FLASH_SEG_SIZE_4K; 1820 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1821 break; 1822 case 2: 1823 if (hw->mac.type == e1000_ich9lan) { 1824 sector_size = ICH_FLASH_SEG_SIZE_8K; 1825 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1826 } else { 1827 ret_val = -E1000_ERR_NVM; 1828 goto out; 1829 } 1830 break; 1831 case 3: 1832 sector_size = ICH_FLASH_SEG_SIZE_64K; 1833 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1834 break; 1835 default: 1836 ret_val = -E1000_ERR_NVM; 1837 goto out; 1838 } 1839 1840 /* Start with the base address, then add the sector offset. */ 1841 flash_linear_addr = hw->nvm.flash_base_addr; 1842 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1843 1844 for (j = 0; j < iteration ; j++) { 1845 do { 1846 /* Steps */ 1847 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1848 if (ret_val) 1849 goto out; 1850 1851 /* 1852 * Write a value 11 (block Erase) in Flash 1853 * Cycle field in hw flash control 1854 */ 1855 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1856 ICH_FLASH_HSFCTL); 1857 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1858 E1000_WRITE_FLASH_REG16(hw, 1859 ICH_FLASH_HSFCTL, 1860 hsflctl.regval); 1861 1862 /* 1863 * Write the last 24 bits of an index within the 1864 * block into Flash Linear address field in Flash 1865 * Address. 1866 */ 1867 flash_linear_addr += (j * sector_size); 1868 E1000_WRITE_FLASH_REG(hw, 1869 ICH_FLASH_FADDR, 1870 flash_linear_addr); 1871 1872 ret_val = e1000_flash_cycle_ich8lan(hw, 1873 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1874 if (ret_val == E1000_SUCCESS) { 1875 break; 1876 } else { 1877 /* 1878 * Check if FCERR is set to 1. If 1, 1879 * clear it and try the whole sequence 1880 * a few more times else Done 1881 */ 1882 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1883 ICH_FLASH_HSFSTS); 1884 if (hsfsts.hsf_status.flcerr == 1) { 1885 /* 1886 * repeat for some time before 1887 * giving up 1888 */ 1889 continue; 1890 } else if (hsfsts.hsf_status.flcdone == 0) 1891 goto out; 1892 } 1893 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1894 } 1895 1896out: 1897 return ret_val; 1898} 1899 1900/** 1901 * e1000_valid_led_default_ich8lan - Set the default LED settings 1902 * @hw: pointer to the HW structure 1903 * @data: Pointer to the LED settings 1904 * 1905 * Reads the LED default settings from the NVM to data. If the NVM LED 1906 * settings is all 0's or F's, set the LED default to a valid LED default 1907 * setting. 1908 **/ 1909STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1910{ 1911 s32 ret_val; 1912 1913 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1914 1915 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1916 if (ret_val) { 1917 DEBUGOUT("NVM Read Error\n"); 1918 goto out; 1919 } 1920 1921 if (*data == ID_LED_RESERVED_0000 || 1922 *data == ID_LED_RESERVED_FFFF) 1923 *data = ID_LED_DEFAULT_ICH8LAN; 1924 1925out: 1926 return ret_val; 1927} 1928 1929/** 1930 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1931 * @hw: pointer to the HW structure 1932 * 1933 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1934 * register, so the the bus width is hard coded. 1935 **/ 1936STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1937{ 1938 struct e1000_bus_info *bus = &hw->bus; 1939 s32 ret_val; 1940 1941 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1942 1943 ret_val = e1000_get_bus_info_pcie_generic(hw); 1944 1945 /* 1946 * ICH devices are "PCI Express"-ish. They have 1947 * a configuration space, but do not contain 1948 * PCI Express Capability registers, so bus width 1949 * must be hardcoded. 1950 */ 1951 if (bus->width == e1000_bus_width_unknown) 1952 bus->width = e1000_bus_width_pcie_x1; 1953 1954 return ret_val; 1955} 1956 1957/** 1958 * e1000_reset_hw_ich8lan - Reset the hardware 1959 * @hw: pointer to the HW structure 1960 * 1961 * Does a full reset of the hardware which includes a reset of the PHY and 1962 * MAC. 1963 **/ 1964STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1965{ 1966 u32 ctrl, icr, kab; 1967 s32 ret_val; 1968 1969 DEBUGFUNC("e1000_reset_hw_ich8lan"); 1970 1971 /* 1972 * Prevent the PCI-E bus from sticking if there is no TLP connection 1973 * on the last TLP read/write transaction when MAC is reset. 1974 */ 1975 ret_val = e1000_disable_pcie_master_generic(hw); 1976 if (ret_val) { 1977 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1978 } 1979 1980 DEBUGOUT("Masking off all interrupts\n"); 1981 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1982 1983 /* 1984 * Disable the Transmit and Receive units. Then delay to allow 1985 * any pending transactions to complete before we hit the MAC 1986 * with the global reset. 1987 */ 1988 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1989 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1990 E1000_WRITE_FLUSH(hw); 1991 1992 msec_delay(10); 1993 1994 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1995 if (hw->mac.type == e1000_ich8lan) { 1996 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1997 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1998 /* Set Packet Buffer Size to 16k. */ 1999 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 2000 } 2001 2002 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2003 2004 if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) { 2005 /* 2006 * PHY HW reset requires MAC CORE reset at the same 2007 * time to make sure the interface between MAC and the 2008 * external PHY is reset. 2009 */ 2010 ctrl |= E1000_CTRL_PHY_RST; 2011 } 2012 ret_val = e1000_acquire_swflag_ich8lan(hw); 2013 DEBUGOUT("Issuing a global reset to ich8lan"); 2014 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2015 msec_delay(20); 2016 2017 ret_val = e1000_get_auto_rd_done_generic(hw); 2018 if (ret_val) { 2019 /* 2020 * When auto config read does not complete, do not 2021 * return with an error. This can happen in situations 2022 * where there is no eeprom and prevents getting link. 2023 */ 2024 DEBUGOUT("Auto Read Done did not complete\n"); 2025 } 2026 2027 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2028 icr = E1000_READ_REG(hw, E1000_ICR); 2029 2030 kab = E1000_READ_REG(hw, E1000_KABGTXD); 2031 kab |= E1000_KABGTXD_BGSQLBIAS; 2032 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2033 2034 return ret_val; 2035} 2036 2037/** 2038 * e1000_init_hw_ich8lan - Initialize the hardware 2039 * @hw: pointer to the HW structure 2040 * 2041 * Prepares the hardware for transmit and receive by doing the following: 2042 * - initialize hardware bits 2043 * - initialize LED identification 2044 * - setup receive address registers 2045 * - setup flow control 2046 * - setup transmit descriptors 2047 * - clear statistics 2048 **/ 2049STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2050{ 2051 struct e1000_mac_info *mac = &hw->mac; 2052 u32 ctrl_ext, txdctl, snoop; 2053 s32 ret_val; 2054 u16 i; 2055 2056 DEBUGFUNC("e1000_init_hw_ich8lan"); 2057 2058 e1000_initialize_hw_bits_ich8lan(hw); 2059 2060 /* Initialize identification LED */ 2061 ret_val = e1000_id_led_init_generic(hw); 2062 if (ret_val) { 2063 DEBUGOUT("Error initializing identification LED\n"); 2064 /* This is not fatal and we should not stop init due to this */ 2065 } 2066 2067 /* Setup the receive address. */ 2068 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2069 2070 /* Zero out the Multicast HASH table */ 2071 DEBUGOUT("Zeroing the MTA\n"); 2072 for (i = 0; i < mac->mta_reg_count; i++) 2073 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2074 2075 /* Setup link and flow control */ 2076 ret_val = e1000_setup_link(hw); 2077 2078 /* Set the transmit descriptor write-back policy for both queues */ 2079 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2080 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2081 E1000_TXDCTL_FULL_TX_DESC_WB; 2082 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2083 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2084 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2085 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2086 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2087 E1000_TXDCTL_FULL_TX_DESC_WB; 2088 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2089 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2090 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2091 2092 /* 2093 * ICH8 has opposite polarity of no_snoop bits. 2094 * By default, we should use snoop behavior. 2095 */ 2096 if (mac->type == e1000_ich8lan) 2097 snoop = PCIE_ICH8_SNOOP_ALL; 2098 else 2099 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2100 e1000_set_pcie_no_snoop_generic(hw, snoop); 2101 2102 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2103 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2104 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2105 2106 /* 2107 * Clear all of the statistics registers (clear on read). It is 2108 * important that we do this after we have tried to establish link 2109 * because the symbol error count will increment wildly if there 2110 * is no link. 2111 */ 2112 e1000_clear_hw_cntrs_ich8lan(hw); 2113 2114 return ret_val; 2115} 2116/** 2117 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2118 * @hw: pointer to the HW structure 2119 * 2120 * Sets/Clears required hardware bits necessary for correctly setting up the 2121 * hardware for transmit and receive. 2122 **/ 2123static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2124{ 2125 u32 reg; 2126 2127 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2128 2129 if (hw->mac.disable_hw_init_bits) 2130 goto out; 2131 2132 /* Extended Device Control */ 2133 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2134 reg |= (1 << 22); 2135 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2136 2137 /* Transmit Descriptor Control 0 */ 2138 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2139 reg |= (1 << 22); 2140 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2141 2142 /* Transmit Descriptor Control 1 */ 2143 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2144 reg |= (1 << 22); 2145 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2146 2147 /* Transmit Arbitration Control 0 */ 2148 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2149 if (hw->mac.type == e1000_ich8lan) 2150 reg |= (1 << 28) | (1 << 29); 2151 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2152 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2153 2154 /* Transmit Arbitration Control 1 */ 2155 reg = E1000_READ_REG(hw, E1000_TARC(1)); 2156 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2157 reg &= ~(1 << 28); 2158 else 2159 reg |= (1 << 28); 2160 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2161 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2162 2163 /* Device Status */ 2164 if (hw->mac.type == e1000_ich8lan) { 2165 reg = E1000_READ_REG(hw, E1000_STATUS); 2166 reg &= ~(1 << 31); 2167 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2168 } 2169 2170out: 2171 return; 2172} 2173 2174/** 2175 * e1000_setup_link_ich8lan - Setup flow control and link settings 2176 * @hw: pointer to the HW structure 2177 * 2178 * Determines which flow control settings to use, then configures flow 2179 * control. Calls the appropriate media-specific link configuration 2180 * function. Assuming the adapter has a valid link partner, a valid link 2181 * should be established. Assumes the hardware has previously been reset 2182 * and the transmitter and receiver are not enabled. 2183 **/ 2184STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2185{ 2186 struct e1000_functions *func = &hw->func; 2187 s32 ret_val = E1000_SUCCESS; 2188 2189 DEBUGFUNC("e1000_setup_link_ich8lan"); 2190 2191 if (e1000_check_reset_block(hw)) 2192 goto out; 2193 2194 /* 2195 * ICH parts do not have a word in the NVM to determine 2196 * the default flow control setting, so we explicitly 2197 * set it to full. 2198 */ 2199 if (hw->fc.type == e1000_fc_default) 2200 hw->fc.type = e1000_fc_full; 2201 2202 hw->fc.original_type = hw->fc.type; 2203 2204 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 2205 2206 /* Continue to configure the copper link. */ 2207 ret_val = func->setup_physical_interface(hw); 2208 if (ret_val) 2209 goto out; 2210 2211 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2212 2213 ret_val = e1000_set_fc_watermarks_generic(hw); 2214 2215out: 2216 return ret_val; 2217} 2218 2219/** 2220 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2221 * @hw: pointer to the HW structure 2222 * 2223 * Configures the kumeran interface to the PHY to wait the appropriate time 2224 * when polling the PHY, then call the generic setup_copper_link to finish 2225 * configuring the copper link. 2226 **/ 2227STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2228{ 2229 u32 ctrl; 2230 s32 ret_val; 2231 u16 reg_data; 2232 2233 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2234 2235 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2236 ctrl |= E1000_CTRL_SLU; 2237 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2238 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2239 2240 /* 2241 * Set the mac to wait the maximum time between each iteration 2242 * and increase the max iterations when polling the phy; 2243 * this fixes erroneous timeouts at 10Mbps. 2244 */ 2245 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2246 if (ret_val) 2247 goto out; 2248 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 2249 if (ret_val) 2250 goto out; 2251 reg_data |= 0x3F; 2252 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 2253 if (ret_val) 2254 goto out; 2255 2256 if (hw->phy.type == e1000_phy_igp_3) { 2257 ret_val = e1000_copper_link_setup_igp(hw); 2258 if (ret_val) 2259 goto out; 2260 } else if (hw->phy.type == e1000_phy_bm) { 2261 ret_val = e1000_copper_link_setup_m88(hw); 2262 if (ret_val) 2263 goto out; 2264 } 2265 2266 if (hw->phy.type == e1000_phy_ife) { 2267 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, ®_data); 2268 if (ret_val) 2269 goto out; 2270 2271 reg_data &= ~IFE_PMC_AUTO_MDIX; 2272 2273 switch (hw->phy.mdix) { 2274 case 1: 2275 reg_data &= ~IFE_PMC_FORCE_MDIX; 2276 break; 2277 case 2: 2278 reg_data |= IFE_PMC_FORCE_MDIX; 2279 break; 2280 case 0: 2281 default: 2282 reg_data |= IFE_PMC_AUTO_MDIX; 2283 break; 2284 } 2285 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data); 2286 if (ret_val) 2287 goto out; 2288 } 2289 ret_val = e1000_setup_copper_link_generic(hw); 2290 2291out: 2292 return ret_val; 2293} 2294 2295/** 2296 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2297 * @hw: pointer to the HW structure 2298 * @speed: pointer to store current link speed 2299 * @duplex: pointer to store the current link duplex 2300 * 2301 * Calls the generic get_speed_and_duplex to retrieve the current link 2302 * information and then calls the Kumeran lock loss workaround for links at 2303 * gigabit speeds. 2304 **/ 2305STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2306 u16 *duplex) 2307{ 2308 s32 ret_val; 2309 2310 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2311 2312 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2313 if (ret_val) 2314 goto out; 2315 2316 if ((hw->mac.type == e1000_ich8lan) && 2317 (hw->phy.type == e1000_phy_igp_3) && 2318 (*speed == SPEED_1000)) { 2319 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2320 } 2321 2322out: 2323 return ret_val; 2324} 2325 2326/** 2327 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2328 * @hw: pointer to the HW structure 2329 * 2330 * Work-around for 82566 Kumeran PCS lock loss: 2331 * On link status change (i.e. PCI reset, speed change) and link is up and 2332 * speed is gigabit- 2333 * 0) if workaround is optionally disabled do nothing 2334 * 1) wait 1ms for Kumeran link to come up 2335 * 2) check Kumeran Diagnostic register PCS lock loss bit 2336 * 3) if not set the link is locked (all is good), otherwise... 2337 * 4) reset the PHY 2338 * 5) repeat up to 10 times 2339 * Note: this is only called for IGP3 copper when speed is 1gb. 2340 **/ 2341static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2342{ 2343 struct e1000_dev_spec_ich8lan *dev_spec; 2344 u32 phy_ctrl; 2345 s32 ret_val = E1000_SUCCESS; 2346 u16 i, data; 2347 bool link; 2348 2349 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2350 2351 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2352 2353 if (!dev_spec) { 2354 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2355 ret_val = -E1000_ERR_CONFIG; 2356 goto out; 2357 } 2358 2359 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2360 goto out; 2361 2362 /* 2363 * Make sure link is up before proceeding. If not just return. 2364 * Attempting this while link is negotiating fouled up link 2365 * stability 2366 */ 2367 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2368 if (!link) { 2369 ret_val = E1000_SUCCESS; 2370 goto out; 2371 } 2372 2373 for (i = 0; i < 10; i++) { 2374 /* read once to clear */ 2375 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); 2376 if (ret_val) 2377 goto out; 2378 /* and again to get new status */ 2379 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); 2380 if (ret_val) 2381 goto out; 2382 2383 /* check for PCS lock */ 2384 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2385 ret_val = E1000_SUCCESS; 2386 goto out; 2387 } 2388 2389 /* Issue PHY reset */ 2390 e1000_phy_hw_reset(hw); 2391 msec_delay_irq(5); 2392 } 2393 /* Disable GigE link negotiation */ 2394 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2395 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2396 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2397 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2398 2399 /* 2400 * Call gig speed drop workaround on Gig disable before accessing 2401 * any PHY registers 2402 */ 2403 e1000_gig_downshift_workaround_ich8lan(hw); 2404 2405 /* unable to acquire PCS lock */ 2406 ret_val = -E1000_ERR_PHY; 2407 2408out: 2409 return ret_val; 2410} 2411 2412/** 2413 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2414 * @hw: pointer to the HW structure 2415 * @state: boolean value used to set the current Kumeran workaround state 2416 * 2417 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2418 * /disabled - FALSE). 2419 **/ 2420void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2421 bool state) 2422{ 2423 struct e1000_dev_spec_ich8lan *dev_spec; 2424 2425 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2426 2427 if (hw->mac.type != e1000_ich8lan) { 2428 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2429 goto out; 2430 } 2431 2432 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2433 2434 if (!dev_spec) { 2435 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2436 goto out; 2437 } 2438 2439 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2440 2441out: 2442 return; 2443} 2444 2445/** 2446 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2447 * @hw: pointer to the HW structure 2448 * 2449 * Workaround for 82566 power-down on D3 entry: 2450 * 1) disable gigabit link 2451 * 2) write VR power-down enable 2452 * 3) read it back 2453 * Continue if successful, else issue LCD reset and repeat 2454 **/ 2455void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2456{ 2457 u32 reg; 2458 u16 data; 2459 u8 retry = 0; 2460 2461 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2462 2463 if (hw->phy.type != e1000_phy_igp_3) 2464 goto out; 2465 2466 /* Try the workaround twice (if needed) */ 2467 do { 2468 /* Disable link */ 2469 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2470 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2471 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2472 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2473 2474 /* 2475 * Call gig speed drop workaround on Gig disable before 2476 * accessing any PHY registers 2477 */ 2478 if (hw->mac.type == e1000_ich8lan) 2479 e1000_gig_downshift_workaround_ich8lan(hw); 2480 2481 /* Write VR power-down enable */ 2482 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); 2483 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2484 e1000_write_phy_reg(hw, 2485 IGP3_VR_CTRL, 2486 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2487 2488 /* Read it back and test */ 2489 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); 2490 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2491 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2492 break; 2493 2494 /* Issue PHY reset and repeat at most one more time */ 2495 reg = E1000_READ_REG(hw, E1000_CTRL); 2496 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2497 retry++; 2498 } while (retry); 2499 2500out: 2501 return; 2502} 2503 2504/** 2505 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2506 * @hw: pointer to the HW structure 2507 * 2508 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2509 * LPLU, Gig disable, MDIC PHY reset): 2510 * 1) Set Kumeran Near-end loopback 2511 * 2) Clear Kumeran Near-end loopback 2512 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2513 **/ 2514void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2515{ 2516 s32 ret_val = E1000_SUCCESS; 2517 u16 reg_data; 2518 2519 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2520 2521 if ((hw->mac.type != e1000_ich8lan) || 2522 (hw->phy.type != e1000_phy_igp_3)) 2523 goto out; 2524 2525 ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2526 ®_data); 2527 if (ret_val) 2528 goto out; 2529 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2530 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2531 reg_data); 2532 if (ret_val) 2533 goto out; 2534 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2535 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2536 reg_data); 2537out: 2538 return; 2539} 2540 2541/** 2542 * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2543 * @hw: pointer to the HW structure 2544 * 2545 * During S0 to Sx transition, it is possible the link remains at gig 2546 * instead of negotiating to a lower speed. Before going to Sx, set 2547 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2548 * to a lower speed. 2549 * 2550 * Should only be called for ICH9m and ICH10 devices. 2551 **/ 2552void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2553{ 2554 u32 phy_ctrl; 2555 2556 if ((hw->mac.type == e1000_ich10lan) || 2557 ((hw->mac.type == e1000_ich9lan) && 2558 ((hw->device_id == E1000_DEV_ID_ICH9_IGP_M) || 2559 (hw->device_id == E1000_DEV_ID_ICH9_IGP_M_AMT)))) { 2560 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2561 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2562 E1000_PHY_CTRL_GBE_DISABLE; 2563 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2564 } 2565 2566 return; 2567} 2568 2569/** 2570 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2571 * @hw: pointer to the HW structure 2572 * 2573 * Return the LED back to the default configuration. 2574 **/ 2575STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2576{ 2577 s32 ret_val = E1000_SUCCESS; 2578 2579 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2580 2581 if (hw->phy.type == e1000_phy_ife) 2582 ret_val = e1000_write_phy_reg(hw, 2583 IFE_PHY_SPECIAL_CONTROL_LED, 2584 0); 2585 else 2586 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2587 2588 return ret_val; 2589} 2590 2591/** 2592 * e1000_led_on_ich8lan - Turn LEDs on 2593 * @hw: pointer to the HW structure 2594 * 2595 * Turn on the LEDs. 2596 **/ 2597STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2598{ 2599 s32 ret_val = E1000_SUCCESS; 2600 2601 DEBUGFUNC("e1000_led_on_ich8lan"); 2602 2603 if (hw->phy.type == e1000_phy_ife) 2604 ret_val = e1000_write_phy_reg(hw, 2605 IFE_PHY_SPECIAL_CONTROL_LED, 2606 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2607 else 2608 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2609 2610 return ret_val; 2611} 2612 2613/** 2614 * e1000_led_off_ich8lan - Turn LEDs off 2615 * @hw: pointer to the HW structure 2616 * 2617 * Turn off the LEDs. 2618 **/ 2619STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2620{ 2621 s32 ret_val = E1000_SUCCESS; 2622 2623 DEBUGFUNC("e1000_led_off_ich8lan"); 2624 2625 if (hw->phy.type == e1000_phy_ife) 2626 ret_val = e1000_write_phy_reg(hw, 2627 IFE_PHY_SPECIAL_CONTROL_LED, 2628 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2629 else 2630 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2631 2632 return ret_val; 2633} 2634 2635/** 2636 * e1000_get_cfg_done_ich8lan - Read config done bit 2637 * @hw: pointer to the HW structure 2638 * 2639 * Read the management control register for the config done bit for 2640 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2641 * to read the config done bit, so an error is *ONLY* logged and returns 2642 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2643 * would not be able to be reset or change link. 2644 **/ 2645STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2646{ 2647 s32 ret_val = E1000_SUCCESS; 2648 u32 bank = 0; 2649 2650 e1000_get_cfg_done_generic(hw); 2651 2652 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2653 if (hw->mac.type != e1000_ich10lan) { 2654 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2655 (hw->phy.type == e1000_phy_igp_3)) { 2656 e1000_phy_init_script_igp3(hw); 2657 } 2658 } else { 2659 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 2660 /* Maybe we should do a basic Boazman config */ 2661 DEBUGOUT("EEPROM not present\n"); 2662 ret_val = -E1000_ERR_CONFIG; 2663 } 2664 } 2665 2666 return ret_val; 2667} 2668 2669/** 2670 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 2671 * @hw: pointer to the HW structure 2672 * 2673 * In the case of a PHY power down to save power, or to turn off link during a 2674 * driver unload, or wake on lan is not enabled, remove the link. 2675 **/ 2676STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 2677{ 2678 /* If the management interface is not enabled, then power down */ 2679 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw))) 2680 e1000_power_down_phy_copper(hw); 2681 2682 return; 2683} 2684 2685/** 2686 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2687 * @hw: pointer to the HW structure 2688 * 2689 * Clears hardware counters specific to the silicon family and calls 2690 * clear_hw_cntrs_generic to clear all general purpose counters. 2691 **/ 2692STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2693{ 2694 volatile u32 temp; 2695 2696 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2697 2698 e1000_clear_hw_cntrs_base_generic(hw); 2699 2700 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 2701 temp = E1000_READ_REG(hw, E1000_RXERRC); 2702 temp = E1000_READ_REG(hw, E1000_TNCRS); 2703 temp = E1000_READ_REG(hw, E1000_CEXTERR); 2704 temp = E1000_READ_REG(hw, E1000_TSCTC); 2705 temp = E1000_READ_REG(hw, E1000_TSCTFC); 2706 2707 temp = E1000_READ_REG(hw, E1000_MGTPRC); 2708 temp = E1000_READ_REG(hw, E1000_MGTPDC); 2709 temp = E1000_READ_REG(hw, E1000_MGTPTC); 2710 2711 temp = E1000_READ_REG(hw, E1000_IAC); 2712 temp = E1000_READ_REG(hw, E1000_ICRXOC); 2713} 2714 2715