e1000_ich8lan.c revision 169589
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 169589 2007-05-16 00:14:23Z jfv $*/ 34 35 36/* e1000_ich8lan 37 * e1000_ich9lan 38 */ 39 40#include "e1000_api.h" 41#include "e1000_ich8lan.h" 42 43void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw); 44 45STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 48STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 49STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 50STATIC boolean_t e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 51STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 52STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 53STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 54STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 55STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 56STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 57 boolean_t active); 58STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 59 boolean_t active); 60STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 61 u16 words, u16 *data); 62STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 63 u16 words, u16 *data); 64STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 65STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 66STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 67 u16 *data); 68STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 69STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 70STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 71STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 72STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 73STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 74 u16 *speed, u16 *duplex); 75STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 76STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 77STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 78STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 79STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 80static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 81static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 82static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 83static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 84static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 85static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 86 u8 size, u16* data); 87STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 88 u32 offset, u16 *data); 89static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 90 u32 offset, u8 byte); 91STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 92 u32 offset, u8 data); 93static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 94 u8 size, u16 data); 95STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 96 97/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 98/* Offset 04h HSFSTS */ 99union ich8_hws_flash_status { 100 struct ich8_hsfsts { 101 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 102 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 103 u16 dael :1; /* bit 2 Direct Access error Log */ 104 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 105 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 106 u16 reserved1 :2; /* bit 13:6 Reserved */ 107 u16 reserved2 :6; /* bit 13:6 Reserved */ 108 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 109 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 110 } hsf_status; 111 u16 regval; 112}; 113 114/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 115/* Offset 06h FLCTL */ 116union ich8_hws_flash_ctrl { 117 struct ich8_hsflctl { 118 u16 flcgo :1; /* 0 Flash Cycle Go */ 119 u16 flcycle :2; /* 2:1 Flash Cycle */ 120 u16 reserved :5; /* 7:3 Reserved */ 121 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 122 u16 flockdn :6; /* 15:10 Reserved */ 123 } hsf_ctrl; 124 u16 regval; 125}; 126 127/* ICH Flash Region Access Permissions */ 128union ich8_hws_flash_regacc { 129 struct ich8_flracc { 130 u32 grra :8; /* 0:7 GbE region Read Access */ 131 u32 grwa :8; /* 8:15 GbE region Write Access */ 132 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 133 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 134 } hsf_flregacc; 135 u16 regval; 136}; 137 138struct e1000_shadow_ram { 139 u16 value; 140 boolean_t modified; 141}; 142 143struct e1000_dev_spec_ich8lan { 144 boolean_t kmrn_lock_loss_workaround_enabled; 145 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 146}; 147 148/** 149 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 150 * @hw: pointer to the HW structure 151 * 152 * Initialize family-specific PHY parameters and function pointers. 153 **/ 154STATIC s32 155e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 156{ 157 struct e1000_phy_info *phy = &hw->phy; 158 struct e1000_functions *func = &hw->func; 159 s32 ret_val = E1000_SUCCESS; 160 u16 i = 0; 161 162 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 163 164 phy->addr = 1; 165 phy->reset_delay_us = 100; 166 167 func->acquire_phy = e1000_acquire_swflag_ich8lan; 168 func->check_polarity = e1000_check_polarity_ife_ich8lan; 169 func->check_reset_block = e1000_check_reset_block_ich8lan; 170 func->force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 171 func->get_cable_length = e1000_get_cable_length_igp_2; 172 func->get_cfg_done = e1000_get_cfg_done_ich8lan; 173 func->get_phy_info = e1000_get_phy_info_ich8lan; 174 func->read_phy_reg = e1000_read_phy_reg_igp; 175 func->release_phy = e1000_release_swflag_ich8lan; 176 func->reset_phy = e1000_phy_hw_reset_ich8lan; 177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 179 func->write_phy_reg = e1000_write_phy_reg_igp; 180 181 182 phy->id = 0; 183 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 184 (i++ < 100)) { 185 msec_delay(1); 186 ret_val = e1000_get_phy_id(hw); 187 if (ret_val) 188 goto out; 189 } 190 191 /* Verify phy id */ 192 switch (phy->id) { 193 case IGP03E1000_E_PHY_ID: 194 phy->type = e1000_phy_igp_3; 195 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 196 break; 197 case IFE_E_PHY_ID: 198 case IFE_PLUS_E_PHY_ID: 199 case IFE_C_E_PHY_ID: 200 phy->type = e1000_phy_ife; 201 phy->autoneg_mask = E1000_ALL_NOT_GIG; 202 break; 203 default: 204 ret_val = -E1000_ERR_PHY; 205 goto out; 206 } 207 208out: 209 return ret_val; 210} 211 212/** 213 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 214 * @hw: pointer to the HW structure 215 * 216 * Initialize family-specific NVM parameters and function 217 * pointers. 218 **/ 219STATIC s32 220e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 221{ 222 struct e1000_nvm_info *nvm = &hw->nvm; 223 struct e1000_functions *func = &hw->func; 224 struct e1000_dev_spec_ich8lan *dev_spec; 225 u32 gfpreg, sector_base_addr, sector_end_addr; 226 s32 ret_val = E1000_SUCCESS; 227 u16 i; 228 229 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 230 231 /* Can't read flash registers if the register set isn't mapped. 232 */ 233 if (!hw->flash_address) { 234 DEBUGOUT("ERROR: Flash registers not mapped\n"); 235 ret_val = -E1000_ERR_CONFIG; 236 goto out; 237 } 238 239 nvm->type = e1000_nvm_flash_sw; 240 241 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 242 243 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 244 * Add 1 to sector_end_addr since this sector is included in 245 * the overall size. */ 246 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 247 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 248 249 /* flash_base_addr is byte-aligned */ 250 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 251 252 /* find total size of the NVM, then cut in half since the total 253 * size represents two separate NVM banks. */ 254 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 255 << FLASH_SECTOR_ADDR_SHIFT; 256 nvm->flash_bank_size /= 2; 257 /* Adjust to word count */ 258 nvm->flash_bank_size /= sizeof(u16); 259 260 nvm->word_size = E1000_SHADOW_RAM_WORDS; 261 262 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 263 264 if (dev_spec == NULL) { 265 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 266 ret_val = -E1000_ERR_CONFIG; 267 goto out; 268 } 269 270 /* Clear shadow ram */ 271 for (i = 0; i < nvm->word_size; i++) { 272 dev_spec->shadow_ram[i].modified = FALSE; 273 dev_spec->shadow_ram[i].value = 0xFFFF; 274 } 275 276 /* Function Pointers */ 277 func->acquire_nvm = e1000_acquire_swflag_ich8lan; 278 func->read_nvm = e1000_read_nvm_ich8lan; 279 func->release_nvm = e1000_release_swflag_ich8lan; 280 func->update_nvm = e1000_update_nvm_checksum_ich8lan; 281 func->valid_led_default = e1000_valid_led_default_ich8lan; 282 func->validate_nvm = e1000_validate_nvm_checksum_ich8lan; 283 func->write_nvm = e1000_write_nvm_ich8lan; 284 285out: 286 return ret_val; 287} 288 289/** 290 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 291 * @hw: pointer to the HW structure 292 * 293 * Initialize family-specific MAC parameters and function 294 * pointers. 295 **/ 296STATIC s32 297e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 298{ 299 struct e1000_mac_info *mac = &hw->mac; 300 struct e1000_functions *func = &hw->func; 301 s32 ret_val = E1000_SUCCESS; 302 303 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 304 305 /* Set media type function pointer */ 306 hw->media_type = e1000_media_type_copper; 307 308 /* Set mta register count */ 309 mac->mta_reg_count = 32; 310 /* Set rar entry count */ 311 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 312 if (mac->type == e1000_ich8lan) 313 mac->rar_entry_count--; 314 /* Set if part includes ASF firmware */ 315 mac->asf_firmware_present = TRUE; 316 /* Set if manageability features are enabled. */ 317 mac->arc_subsystem_valid = TRUE; 318 319 /* Function pointers */ 320 321 /* bus type/speed/width */ 322 func->get_bus_info = e1000_get_bus_info_ich8lan; 323 /* reset */ 324 func->reset_hw = e1000_reset_hw_ich8lan; 325 /* hw initialization */ 326 func->init_hw = e1000_init_hw_ich8lan; 327 /* link setup */ 328 func->setup_link = e1000_setup_link_ich8lan; 329 /* physical interface setup */ 330 func->setup_physical_interface = e1000_setup_copper_link_ich8lan; 331 /* check for link */ 332 func->check_for_link = e1000_check_for_copper_link_generic; 333 /* check management mode */ 334 func->check_mng_mode = e1000_check_mng_mode_ich8lan; 335 /* link info */ 336 func->get_link_up_info = e1000_get_link_up_info_ich8lan; 337 /* multicast address update */ 338 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 339 /* setting MTA */ 340 func->mta_set = e1000_mta_set_generic; 341 /* blink LED */ 342 func->blink_led = e1000_blink_led_generic; 343 /* setup LED */ 344 func->setup_led = e1000_setup_led_generic; 345 /* cleanup LED */ 346 func->cleanup_led = e1000_cleanup_led_ich8lan; 347 /* turn on/off LED */ 348 func->led_on = e1000_led_on_ich8lan; 349 func->led_off = e1000_led_off_ich8lan; 350 /* remove device */ 351 func->remove_device = e1000_remove_device_generic; 352 /* clear hardware counters */ 353 func->clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 354 355 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan); 356 357 /* Device-specific structure allocation */ 358 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 359 if (ret_val) 360 goto out; 361 362 /* Enable PCS Lock-loss workaround for ICH8 */ 363 if (mac->type == e1000_ich8lan) 364 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 365 366 367out: 368 return ret_val; 369} 370 371/** 372 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 373 * @hw: pointer to the HW structure 374 * 375 * Initialize family-specific function pointers for PHY, MAC, and NVM. 376 **/ 377void 378e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 379{ 380 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 381 382 hw->func.init_mac_params = e1000_init_mac_params_ich8lan; 383 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan; 384 hw->func.init_phy_params = e1000_init_phy_params_ich8lan; 385} 386 387/** 388 * e1000_acquire_swflag_ich8lan - Acquire software control flag 389 * @hw: pointer to the HW structure 390 * 391 * Acquires the software control flag for performing NVM and PHY 392 * operations. This is a function pointer entry point only called by 393 * read/write routines for the PHY and NVM parts. 394 **/ 395STATIC s32 396e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 397{ 398 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 399 s32 ret_val = E1000_SUCCESS; 400 401 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 402 403 while (timeout) { 404 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 405 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 406 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 407 408 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 409 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 410 break; 411 msec_delay_irq(1); 412 timeout--; 413 } 414 415 if (!timeout) { 416 DEBUGOUT("FW or HW has locked the resource for too long.\n"); 417 ret_val = -E1000_ERR_CONFIG; 418 goto out; 419 } 420 421out: 422 return ret_val; 423} 424 425/** 426 * e1000_release_swflag_ich8lan - Release software control flag 427 * @hw: pointer to the HW structure 428 * 429 * Releases the software control flag for performing NVM and PHY operations. 430 * This is a function pointer entry point only called by read/write 431 * routines for the PHY and NVM parts. 432 **/ 433STATIC void 434e1000_release_swflag_ich8lan(struct e1000_hw *hw) 435{ 436 u32 extcnf_ctrl; 437 438 DEBUGFUNC("e1000_release_swflag_ich8lan"); 439 440 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 441 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 442 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 443 444 return; 445} 446 447/** 448 * e1000_check_mng_mode_ich8lan - Checks management mode 449 * @hw: pointer to the HW structure 450 * 451 * This checks if the adapter has manageability enabled. 452 * This is a function pointer entry point only called by read/write 453 * routines for the PHY and NVM parts. 454 **/ 455STATIC boolean_t 456e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 457{ 458 u32 fwsm; 459 460 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 461 462 fwsm = E1000_READ_REG(hw, E1000_FWSM); 463 464 return ((fwsm & E1000_FWSM_MODE_MASK) == 465 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 466} 467 468/** 469 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 470 * @hw: pointer to the HW structure 471 * 472 * Checks if firmware is blocking the reset of the PHY. 473 * This is a function pointer entry point only called by 474 * reset routines. 475 **/ 476STATIC s32 477e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 478{ 479 u32 fwsm; 480 481 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 482 483 fwsm = E1000_READ_REG(hw, E1000_FWSM); 484 485 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 486 : E1000_BLK_PHY_RESET; 487} 488 489/** 490 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 491 * @hw: pointer to the HW structure 492 * 493 * Forces the speed and duplex settings of the PHY. 494 * This is a function pointer entry point only called by 495 * PHY setup routines. 496 **/ 497STATIC s32 498e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 499{ 500 struct e1000_phy_info *phy = &hw->phy; 501 s32 ret_val; 502 u16 data; 503 boolean_t link; 504 505 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 506 507 if (phy->type != e1000_phy_ife) { 508 ret_val = e1000_phy_force_speed_duplex_igp(hw); 509 goto out; 510 } 511 512 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &data); 513 if (ret_val) 514 goto out; 515 516 e1000_phy_force_speed_duplex_setup(hw, &data); 517 518 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, data); 519 if (ret_val) 520 goto out; 521 522 /* Disable MDI-X support for 10/100 */ 523 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 524 if (ret_val) 525 goto out; 526 527 data &= ~IFE_PMC_AUTO_MDIX; 528 data &= ~IFE_PMC_FORCE_MDIX; 529 530 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data); 531 if (ret_val) 532 goto out; 533 534 DEBUGOUT1("IFE PMC: %X\n", data); 535 536 usec_delay(1); 537 538 if (phy->wait_for_link) { 539 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 540 541 ret_val = e1000_phy_has_link_generic(hw, 542 PHY_FORCE_LIMIT, 543 100000, 544 &link); 545 if (ret_val) 546 goto out; 547 548 if (!link) { 549 DEBUGOUT("Link taking longer than expected.\n"); 550 } 551 552 /* Try once more */ 553 ret_val = e1000_phy_has_link_generic(hw, 554 PHY_FORCE_LIMIT, 555 100000, 556 &link); 557 if (ret_val) 558 goto out; 559 } 560 561out: 562 return ret_val; 563} 564 565/** 566 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 567 * @hw: pointer to the HW structure 568 * 569 * Resets the PHY 570 * This is a function pointer entry point called by drivers 571 * or other shared routines. 572 **/ 573STATIC s32 574e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 575{ 576 struct e1000_phy_info *phy = &hw->phy; 577 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 578 s32 ret_val; 579 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 580 u16 word_addr, reg_data, reg_addr, phy_page = 0; 581 582 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 583 584 ret_val = e1000_phy_hw_reset_generic(hw); 585 if (ret_val) 586 goto out; 587 588 /* Initialize the PHY from the NVM on ICH platforms. This 589 * is needed due to an issue where the NVM configuration is 590 * not properly autoloaded after power transitions. 591 * Therefore, after each PHY reset, we will load the 592 * configuration data out of the NVM manually. 593 */ 594 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 595 /* Check if SW needs configure the PHY */ 596 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 597 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 598 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 599 else 600 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 601 602 data = E1000_READ_REG(hw, E1000_FEXTNVM); 603 if (!(data & sw_cfg_mask)) 604 goto out; 605 606 /* Wait for basic configuration completes before proceeding*/ 607 do { 608 data = E1000_READ_REG(hw, E1000_STATUS); 609 data &= E1000_STATUS_LAN_INIT_DONE; 610 usec_delay(100); 611 } while ((!data) && --loop); 612 613 /* If basic configuration is incomplete before the above loop 614 * count reaches 0, loading the configuration from NVM will 615 * leave the PHY in a bad state possibly resulting in no link. 616 */ 617 if (loop == 0) { 618 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 619 } 620 621 /* Clear the Init Done bit for the next init event */ 622 data = E1000_READ_REG(hw, E1000_STATUS); 623 data &= ~E1000_STATUS_LAN_INIT_DONE; 624 E1000_WRITE_REG(hw, E1000_STATUS, data); 625 626 /* Make sure HW does not configure LCD from PHY 627 * extended configuration before SW configuration */ 628 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 629 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 630 goto out; 631 632 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 633 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 634 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 635 if (!cnf_size) 636 goto out; 637 638 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 639 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 640 641 /* Configure LCD from extended configuration 642 * region. */ 643 644 /* cnf_base_addr is in DWORD */ 645 word_addr = (u16)(cnf_base_addr << 1); 646 647 for (i = 0; i < cnf_size; i++) { 648 ret_val = e1000_read_nvm(hw, 649 (word_addr + i * 2), 650 1, 651 ®_data); 652 if (ret_val) 653 goto out; 654 655 ret_val = e1000_read_nvm(hw, 656 (word_addr + i * 2 + 1), 657 1, 658 ®_addr); 659 if (ret_val) 660 goto out; 661 662 /* Save off the PHY page for future writes. */ 663 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 664 phy_page = reg_data; 665 continue; 666 } 667 668 reg_addr |= phy_page; 669 670 ret_val = e1000_write_phy_reg(hw, 671 (u32)reg_addr, 672 reg_data); 673 if (ret_val) 674 goto out; 675 } 676 } 677 678out: 679 return ret_val; 680} 681 682/** 683 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 684 * @hw: pointer to the HW structure 685 * 686 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 687 * This is a function pointer entry point called by drivers 688 * or other shared routines. 689 **/ 690STATIC s32 691e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 692{ 693 s32 ret_val = -E1000_ERR_PHY_TYPE; 694 695 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 696 697 switch (hw->phy.type) { 698 case e1000_phy_ife: 699 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 700 break; 701 case e1000_phy_igp_3: 702 ret_val = e1000_get_phy_info_igp(hw); 703 break; 704 default: 705 break; 706 } 707 708 return ret_val; 709} 710 711/** 712 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 713 * @hw: pointer to the HW structure 714 * 715 * Populates "phy" structure with various feature states. 716 * This function is only called by other family-specific 717 * routines. 718 **/ 719static s32 720e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 721{ 722 struct e1000_phy_info *phy = &hw->phy; 723 s32 ret_val; 724 u16 data; 725 boolean_t link; 726 727 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 728 729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730 if (ret_val) 731 goto out; 732 733 if (!link) { 734 DEBUGOUT("Phy info is only valid if link is up\n"); 735 ret_val = -E1000_ERR_CONFIG; 736 goto out; 737 } 738 739 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 740 if (ret_val) 741 goto out; 742 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 743 ? FALSE : TRUE; 744 745 if (phy->polarity_correction) { 746 ret_val = e1000_check_polarity_ife_ich8lan(hw); 747 if (ret_val) 748 goto out; 749 } else { 750 /* Polarity is forced */ 751 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 752 ? e1000_rev_polarity_reversed 753 : e1000_rev_polarity_normal; 754 } 755 756 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 757 if (ret_val) 758 goto out; 759 760 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 761 762 /* The following parameters are undefined for 10/100 operation. */ 763 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 764 phy->local_rx = e1000_1000t_rx_status_undefined; 765 phy->remote_rx = e1000_1000t_rx_status_undefined; 766 767out: 768 return ret_val; 769} 770 771/** 772 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 773 * @hw: pointer to the HW structure 774 * 775 * Polarity is determined on the polarity reveral feature being enabled. 776 * This function is only called by other family-specific 777 * routines. 778 **/ 779STATIC s32 780e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 781{ 782 struct e1000_phy_info *phy = &hw->phy; 783 s32 ret_val; 784 u16 phy_data, offset, mask; 785 786 DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 787 788 /* Polarity is determined based on the reversal feature 789 * being enabled. 790 */ 791 if (phy->polarity_correction) { 792 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 793 mask = IFE_PESC_POLARITY_REVERSED; 794 } else { 795 offset = IFE_PHY_SPECIAL_CONTROL; 796 mask = IFE_PSC_FORCE_POLARITY; 797 } 798 799 ret_val = e1000_read_phy_reg(hw, offset, &phy_data); 800 801 if (!ret_val) 802 phy->cable_polarity = (phy_data & mask) 803 ? e1000_rev_polarity_reversed 804 : e1000_rev_polarity_normal; 805 806 return ret_val; 807} 808 809/** 810 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 811 * @hw: pointer to the HW structure 812 * @active: TRUE to enable LPLU, FALSE to disable 813 * 814 * Sets the LPLU D0 state according to the active flag. When 815 * activating LPLU this function also disables smart speed 816 * and vice versa. LPLU will not be activated unless the 817 * device autonegotiation advertisement meets standards of 818 * either 10 or 10/100 or 10/100/1000 at all duplexes. 819 * This is a function pointer entry point only called by 820 * PHY setup routines. 821 **/ 822STATIC s32 823e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active) 824{ 825 struct e1000_phy_info *phy = &hw->phy; 826 u32 phy_ctrl; 827 s32 ret_val = E1000_SUCCESS; 828 u16 data; 829 830 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 831 832 if (phy->type != e1000_phy_igp_3) 833 goto out; 834 835 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 836 837 if (active) { 838 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 839 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 840 841 /* Call gig speed drop workaround on LPLU before accessing 842 * any PHY registers */ 843 if ((hw->mac.type == e1000_ich8lan) && 844 (hw->phy.type == e1000_phy_igp_3)) 845 e1000_gig_downshift_workaround_ich8lan(hw); 846 847 /* When LPLU is enabled, we should disable SmartSpeed */ 848 ret_val = e1000_read_phy_reg(hw, 849 IGP01E1000_PHY_PORT_CONFIG, 850 &data); 851 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 852 ret_val = e1000_write_phy_reg(hw, 853 IGP01E1000_PHY_PORT_CONFIG, 854 data); 855 if (ret_val) 856 goto out; 857 } else { 858 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 859 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 860 861 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 862 * during Dx states where the power conservation is most 863 * important. During driver activity we should enable 864 * SmartSpeed, so performance is maintained. */ 865 if (phy->smart_speed == e1000_smart_speed_on) { 866 ret_val = e1000_read_phy_reg(hw, 867 IGP01E1000_PHY_PORT_CONFIG, 868 &data); 869 if (ret_val) 870 goto out; 871 872 data |= IGP01E1000_PSCFR_SMART_SPEED; 873 ret_val = e1000_write_phy_reg(hw, 874 IGP01E1000_PHY_PORT_CONFIG, 875 data); 876 if (ret_val) 877 goto out; 878 } else if (phy->smart_speed == e1000_smart_speed_off) { 879 ret_val = e1000_read_phy_reg(hw, 880 IGP01E1000_PHY_PORT_CONFIG, 881 &data); 882 if (ret_val) 883 goto out; 884 885 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 886 ret_val = e1000_write_phy_reg(hw, 887 IGP01E1000_PHY_PORT_CONFIG, 888 data); 889 if (ret_val) 890 goto out; 891 } 892 } 893 894out: 895 return ret_val; 896} 897 898/** 899 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 900 * @hw: pointer to the HW structure 901 * @active: TRUE to enable LPLU, FALSE to disable 902 * 903 * Sets the LPLU D3 state according to the active flag. When 904 * activating LPLU this function also disables smart speed 905 * and vice versa. LPLU will not be activated unless the 906 * device autonegotiation advertisement meets standards of 907 * either 10 or 10/100 or 10/100/1000 at all duplexes. 908 * This is a function pointer entry point only called by 909 * PHY setup routines. 910 **/ 911STATIC s32 912e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active) 913{ 914 struct e1000_phy_info *phy = &hw->phy; 915 u32 phy_ctrl; 916 s32 ret_val = E1000_SUCCESS; 917 u16 data; 918 919 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 920 921 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 922 923 if (!active) { 924 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 925 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 926 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 927 * during Dx states where the power conservation is most 928 * important. During driver activity we should enable 929 * SmartSpeed, so performance is maintained. */ 930 if (phy->smart_speed == e1000_smart_speed_on) { 931 ret_val = e1000_read_phy_reg(hw, 932 IGP01E1000_PHY_PORT_CONFIG, 933 &data); 934 if (ret_val) 935 goto out; 936 937 data |= IGP01E1000_PSCFR_SMART_SPEED; 938 ret_val = e1000_write_phy_reg(hw, 939 IGP01E1000_PHY_PORT_CONFIG, 940 data); 941 if (ret_val) 942 goto out; 943 } else if (phy->smart_speed == e1000_smart_speed_off) { 944 ret_val = e1000_read_phy_reg(hw, 945 IGP01E1000_PHY_PORT_CONFIG, 946 &data); 947 if (ret_val) 948 goto out; 949 950 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 951 ret_val = e1000_write_phy_reg(hw, 952 IGP01E1000_PHY_PORT_CONFIG, 953 data); 954 if (ret_val) 955 goto out; 956 } 957 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 958 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 959 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 960 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 961 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 962 963 /* Call gig speed drop workaround on LPLU before accessing 964 * any PHY registers */ 965 if ((hw->mac.type == e1000_ich8lan) && 966 (hw->phy.type == e1000_phy_igp_3)) 967 e1000_gig_downshift_workaround_ich8lan(hw); 968 969 /* When LPLU is enabled, we should disable SmartSpeed */ 970 ret_val = e1000_read_phy_reg(hw, 971 IGP01E1000_PHY_PORT_CONFIG, 972 &data); 973 if (ret_val) 974 goto out; 975 976 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 977 ret_val = e1000_write_phy_reg(hw, 978 IGP01E1000_PHY_PORT_CONFIG, 979 data); 980 } 981 982out: 983 return ret_val; 984} 985 986/** 987 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 988 * @hw: pointer to the HW structure 989 * @offset: The offset (in bytes) of the word(s) to read. 990 * @words: Size of data to read in words 991 * @data: Pointer to the word(s) to read at offset. 992 * 993 * Reads a word(s) from the NVM using the flash access registers. 994 **/ 995STATIC s32 996e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 997{ 998 struct e1000_nvm_info *nvm = &hw->nvm; 999 struct e1000_dev_spec_ich8lan *dev_spec; 1000 u32 act_offset; 1001 s32 ret_val = E1000_SUCCESS; 1002 u16 i, word; 1003 1004 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1005 1006 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1007 1008 if (dev_spec == NULL) { 1009 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1010 ret_val = -E1000_ERR_CONFIG; 1011 goto out; 1012 } 1013 1014 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1015 (words == 0)) { 1016 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1017 ret_val = -E1000_ERR_NVM; 1018 goto out; 1019 } 1020 1021 ret_val = e1000_acquire_nvm(hw); 1022 if (ret_val) 1023 goto out; 1024 1025 /* Start with the bank offset, then add the relative offset. */ 1026 act_offset = (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) 1027 ? nvm->flash_bank_size 1028 : 0; 1029 act_offset += offset; 1030 1031 for (i = 0; i < words; i++) { 1032 if ((dev_spec->shadow_ram != NULL) && 1033 (dev_spec->shadow_ram[offset+i].modified == TRUE)) { 1034 data[i] = dev_spec->shadow_ram[offset+i].value; 1035 } else { 1036 ret_val = e1000_read_flash_word_ich8lan(hw, 1037 act_offset + i, 1038 &word); 1039 if (ret_val) 1040 break; 1041 data[i] = word; 1042 } 1043 } 1044 1045 e1000_release_nvm(hw); 1046 1047out: 1048 return ret_val; 1049} 1050 1051/** 1052 * e1000_flash_cycle_init_ich8lan - Initialize flash 1053 * @hw: pointer to the HW structure 1054 * 1055 * This function does initial flash setup so that a new read/write/erase cycle 1056 * can be started. 1057 **/ 1058static s32 1059e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1060{ 1061 union ich8_hws_flash_status hsfsts; 1062 s32 ret_val = -E1000_ERR_NVM; 1063 s32 i = 0; 1064 1065 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1066 1067 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1068 1069 /* Check if the flash descriptor is valid */ 1070 if (hsfsts.hsf_status.fldesvalid == 0) { 1071 DEBUGOUT("Flash descriptor invalid. " 1072 "SW Sequencing must be used."); 1073 goto out; 1074 } 1075 1076 /* Clear FCERR and DAEL in hw status by writing 1 */ 1077 hsfsts.hsf_status.flcerr = 1; 1078 hsfsts.hsf_status.dael = 1; 1079 1080 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1081 1082 /* Either we should have a hardware SPI cycle in progress 1083 * bit to check against, in order to start a new cycle or 1084 * FDONE bit should be changed in the hardware so that it 1085 * is 1 after harware reset, which can then be used as an 1086 * indication whether a cycle is in progress or has been 1087 * completed. 1088 */ 1089 1090 if (hsfsts.hsf_status.flcinprog == 0) { 1091 /* There is no cycle running at present, 1092 * so we can start a cycle */ 1093 /* Begin by setting Flash Cycle Done. */ 1094 hsfsts.hsf_status.flcdone = 1; 1095 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1096 ret_val = E1000_SUCCESS; 1097 } else { 1098 /* otherwise poll for sometime so the current 1099 * cycle has a chance to end before giving up. */ 1100 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1101 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1102 ICH_FLASH_HSFSTS); 1103 if (hsfsts.hsf_status.flcinprog == 0) { 1104 ret_val = E1000_SUCCESS; 1105 break; 1106 } 1107 usec_delay(1); 1108 } 1109 if (ret_val == E1000_SUCCESS) { 1110 /* Successful in waiting for previous cycle to timeout, 1111 * now set the Flash Cycle Done. */ 1112 hsfsts.hsf_status.flcdone = 1; 1113 E1000_WRITE_FLASH_REG16(hw, 1114 ICH_FLASH_HSFSTS, 1115 hsfsts.regval); 1116 } else { 1117 DEBUGOUT("Flash controller busy, cannot get access"); 1118 } 1119 } 1120 1121out: 1122 return ret_val; 1123} 1124 1125/** 1126 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1127 * @hw: pointer to the HW structure 1128 * @timeout: maximum time to wait for completion 1129 * 1130 * This function starts a flash cycle and waits for its completion. 1131 **/ 1132static s32 1133e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1134{ 1135 union ich8_hws_flash_ctrl hsflctl; 1136 union ich8_hws_flash_status hsfsts; 1137 s32 ret_val = -E1000_ERR_NVM; 1138 u32 i = 0; 1139 1140 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1141 1142 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1143 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1144 hsflctl.hsf_ctrl.flcgo = 1; 1145 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1146 1147 /* wait till FDONE bit is set to 1 */ 1148 do { 1149 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1150 if (hsfsts.hsf_status.flcdone == 1) 1151 break; 1152 usec_delay(1); 1153 } while (i++ < timeout); 1154 1155 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1156 ret_val = E1000_SUCCESS; 1157 1158 return ret_val; 1159} 1160 1161/** 1162 * e1000_read_flash_word_ich8lan - Read word from flash 1163 * @hw: pointer to the HW structure 1164 * @offset: offset to data location 1165 * @data: pointer to the location for storing the data 1166 * 1167 * Reads the flash word at offset into data. Offset is converted 1168 * to bytes before read. 1169 **/ 1170STATIC s32 1171e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data) 1172{ 1173 s32 ret_val; 1174 1175 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1176 1177 if (data == NULL) { 1178 ret_val = -E1000_ERR_NVM; 1179 goto out; 1180 } 1181 1182 /* Must convert offset into bytes. */ 1183 offset <<= 1; 1184 1185 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1186 1187out: 1188 return ret_val; 1189} 1190 1191/** 1192 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1193 * @hw: pointer to the HW structure 1194 * @offset: The offset (in bytes) of the byte or word to read. 1195 * @size: Size of data to read, 1=byte 2=word 1196 * @data: Pointer to the word to store the value read. 1197 * 1198 * Reads a byte or word from the NVM using the flash access registers. 1199 **/ 1200static s32 1201e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1202 u8 size, u16* data) 1203{ 1204 union ich8_hws_flash_status hsfsts; 1205 union ich8_hws_flash_ctrl hsflctl; 1206 u32 flash_linear_addr; 1207 u32 flash_data = 0; 1208 s32 ret_val = -E1000_ERR_NVM; 1209 u8 count = 0; 1210 1211 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1212 1213 if (size < 1 || size > 2 || data == 0x0 || 1214 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1215 goto out; 1216 1217 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1218 hw->nvm.flash_base_addr; 1219 1220 do { 1221 usec_delay(1); 1222 /* Steps */ 1223 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1224 if (ret_val != E1000_SUCCESS) 1225 break; 1226 1227 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1228 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1229 hsflctl.hsf_ctrl.fldbcount = size - 1; 1230 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1231 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1232 1233 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1234 1235 ret_val = e1000_flash_cycle_ich8lan(hw, 1236 ICH_FLASH_READ_COMMAND_TIMEOUT); 1237 1238 /* Check if FCERR is set to 1, if set to 1, clear it 1239 * and try the whole sequence a few more times, else 1240 * read in (shift in) the Flash Data0, the order is 1241 * least significant byte first msb to lsb */ 1242 if (ret_val == E1000_SUCCESS) { 1243 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1244 if (size == 1) { 1245 *data = (u8)(flash_data & 0x000000FF); 1246 } else if (size == 2) { 1247 *data = (u16)(flash_data & 0x0000FFFF); 1248 } 1249 break; 1250 } else { 1251 /* If we've gotten here, then things are probably 1252 * completely hosed, but if the error condition is 1253 * detected, it won't hurt to give it another try... 1254 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1255 */ 1256 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1257 ICH_FLASH_HSFSTS); 1258 if (hsfsts.hsf_status.flcerr == 1) { 1259 /* Repeat for some time before giving up. */ 1260 continue; 1261 } else if (hsfsts.hsf_status.flcdone == 0) { 1262 DEBUGOUT("Timeout error - flash cycle " 1263 "did not complete."); 1264 break; 1265 } 1266 } 1267 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1268 1269out: 1270 return ret_val; 1271} 1272 1273/** 1274 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1275 * @hw: pointer to the HW structure 1276 * @offset: The offset (in bytes) of the word(s) to write. 1277 * @words: Size of data to write in words 1278 * @data: Pointer to the word(s) to write at offset. 1279 * 1280 * Writes a byte or word to the NVM using the flash access registers. 1281 **/ 1282STATIC s32 1283e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 1284{ 1285 struct e1000_nvm_info *nvm = &hw->nvm; 1286 struct e1000_dev_spec_ich8lan *dev_spec; 1287 s32 ret_val = E1000_SUCCESS; 1288 u16 i; 1289 1290 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1291 1292 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1293 1294 if (dev_spec == NULL) { 1295 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1296 ret_val = -E1000_ERR_CONFIG; 1297 goto out; 1298 } 1299 1300 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1301 (words == 0)) { 1302 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1303 ret_val = -E1000_ERR_NVM; 1304 goto out; 1305 } 1306 1307 ret_val = e1000_acquire_nvm(hw); 1308 if (ret_val) 1309 goto out; 1310 1311 for (i = 0; i < words; i++) { 1312 dev_spec->shadow_ram[offset+i].modified = TRUE; 1313 dev_spec->shadow_ram[offset+i].value = data[i]; 1314 } 1315 1316 e1000_release_nvm(hw); 1317 1318out: 1319 return ret_val; 1320} 1321 1322/** 1323 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1324 * @hw: pointer to the HW structure 1325 * 1326 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1327 * which writes the checksum to the shadow ram. The changes in the shadow 1328 * ram are then committed to the EEPROM by processing each bank at a time 1329 * checking for the modified bit and writing only the pending changes. 1330 * After a succesful commit, the shadow ram is cleared and is ready for 1331 * future writes. 1332 **/ 1333STATIC s32 1334e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1335{ 1336 struct e1000_nvm_info *nvm = &hw->nvm; 1337 struct e1000_dev_spec_ich8lan *dev_spec; 1338 u32 i, act_offset, new_bank_offset, old_bank_offset; 1339 s32 ret_val; 1340 u16 data; 1341 1342 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1343 1344 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1345 1346 ret_val = e1000_update_nvm_checksum_generic(hw); 1347 if (ret_val) 1348 goto out; 1349 1350 if (nvm->type != e1000_nvm_flash_sw) 1351 goto out; 1352 1353 ret_val = e1000_acquire_nvm(hw); 1354 if (ret_val) 1355 goto out; 1356 1357 /* We're writing to the opposite bank so if we're on bank 1, 1358 * write to bank 0 etc. We also need to erase the segment that 1359 * is going to be written */ 1360 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)) { 1361 new_bank_offset = nvm->flash_bank_size; 1362 old_bank_offset = 0; 1363 e1000_erase_flash_bank_ich8lan(hw, 1); 1364 } else { 1365 old_bank_offset = nvm->flash_bank_size; 1366 new_bank_offset = 0; 1367 e1000_erase_flash_bank_ich8lan(hw, 0); 1368 } 1369 1370 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1371 /* Determine whether to write the value stored 1372 * in the other NVM bank or a modified value stored 1373 * in the shadow RAM */ 1374 if (dev_spec->shadow_ram[i].modified == TRUE) { 1375 data = dev_spec->shadow_ram[i].value; 1376 } else { 1377 e1000_read_flash_word_ich8lan(hw, 1378 i + old_bank_offset, 1379 &data); 1380 } 1381 1382 /* If the word is 0x13, then make sure the signature bits 1383 * (15:14) are 11b until the commit has completed. 1384 * This will allow us to write 10b which indicates the 1385 * signature is valid. We want to do this after the write 1386 * has completed so that we don't mark the segment valid 1387 * while the write is still in progress */ 1388 if (i == E1000_ICH_NVM_SIG_WORD) 1389 data |= E1000_ICH_NVM_SIG_MASK; 1390 1391 /* Convert offset to bytes. */ 1392 act_offset = (i + new_bank_offset) << 1; 1393 1394 usec_delay(100); 1395 /* Write the bytes to the new bank. */ 1396 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1397 act_offset, 1398 (u8)data); 1399 if (ret_val) 1400 break; 1401 1402 usec_delay(100); 1403 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1404 act_offset + 1, 1405 (u8)(data >> 8)); 1406 if (ret_val) 1407 break; 1408 } 1409 1410 /* Don't bother writing the segment valid bits if sector 1411 * programming failed. */ 1412 if (ret_val) { 1413 DEBUGOUT("Flash commit failed.\n"); 1414 e1000_release_nvm(hw); 1415 goto out; 1416 } 1417 1418 /* Finally validate the new segment by setting bit 15:14 1419 * to 10b in word 0x13 , this can be done without an 1420 * erase as well since these bits are 11 to start with 1421 * and we need to change bit 14 to 0b */ 1422 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1423 e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1424 data &= 0xBFFF; 1425 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1426 act_offset * 2 + 1, 1427 (u8)(data >> 8)); 1428 if (ret_val) { 1429 e1000_release_nvm(hw); 1430 goto out; 1431 } 1432 1433 /* And invalidate the previously valid segment by setting 1434 * its signature word (0x13) high_byte to 0b. This can be 1435 * done without an erase because flash erase sets all bits 1436 * to 1's. We can write 1's to 0's without an erase */ 1437 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1438 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1439 if (ret_val) { 1440 e1000_release_nvm(hw); 1441 goto out; 1442 } 1443 1444 /* Great! Everything worked, we can now clear the cached entries. */ 1445 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1446 dev_spec->shadow_ram[i].modified = FALSE; 1447 dev_spec->shadow_ram[i].value = 0xFFFF; 1448 } 1449 1450 e1000_release_nvm(hw); 1451 1452 /* Reload the EEPROM, or else modifications will not appear 1453 * until after the next adapter reset. 1454 */ 1455 e1000_reload_nvm(hw); 1456 msec_delay(10); 1457 1458out: 1459 return ret_val; 1460} 1461 1462/** 1463 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1464 * @hw: pointer to the HW structure 1465 * 1466 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1467 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 1468 * calculated, in which case we need to calculate the checksum and set bit 6. 1469 **/ 1470STATIC s32 1471e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1472{ 1473 s32 ret_val = E1000_SUCCESS; 1474 u16 data; 1475 1476 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1477 1478 /* Read 0x19 and check bit 6. If this bit is 0, the checksum 1479 * needs to be fixed. This bit is an indication that the NVM 1480 * was prepared by OEM software and did not calculate the 1481 * checksum...a likely scenario. 1482 */ 1483 ret_val = e1000_read_nvm(hw, 0x19, 1, &data); 1484 if (ret_val) 1485 goto out; 1486 1487 if ((data & 0x40) == 0) { 1488 data |= 0x40; 1489 ret_val = e1000_write_nvm(hw, 0x19, 1, &data); 1490 if (ret_val) 1491 goto out; 1492 ret_val = e1000_update_nvm_checksum(hw); 1493 if (ret_val) 1494 goto out; 1495 } 1496 1497 ret_val = e1000_validate_nvm_checksum_generic(hw); 1498 1499out: 1500 return ret_val; 1501} 1502 1503/** 1504 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1505 * @hw: pointer to the HW structure 1506 * @offset: The offset (in bytes) of the byte/word to read. 1507 * @size: Size of data to read, 1=byte 2=word 1508 * @data: The byte(s) to write to the NVM. 1509 * 1510 * Writes one/two bytes to the NVM using the flash access registers. 1511 **/ 1512static s32 1513e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1514 u8 size, u16 data) 1515{ 1516 union ich8_hws_flash_status hsfsts; 1517 union ich8_hws_flash_ctrl hsflctl; 1518 u32 flash_linear_addr; 1519 u32 flash_data = 0; 1520 s32 ret_val = -E1000_ERR_NVM; 1521 u8 count = 0; 1522 1523 DEBUGFUNC("e1000_write_ich8_data"); 1524 1525 if (size < 1 || size > 2 || data > size * 0xff || 1526 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1527 goto out; 1528 1529 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1530 hw->nvm.flash_base_addr; 1531 1532 do { 1533 usec_delay(1); 1534 /* Steps */ 1535 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1536 if (ret_val != E1000_SUCCESS) 1537 break; 1538 1539 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1540 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1541 hsflctl.hsf_ctrl.fldbcount = size -1; 1542 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1543 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1544 1545 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1546 1547 if (size == 1) 1548 flash_data = (u32)data & 0x00FF; 1549 else 1550 flash_data = (u32)data; 1551 1552 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1553 1554 /* check if FCERR is set to 1 , if set to 1, clear it 1555 * and try the whole sequence a few more times else done */ 1556 ret_val = e1000_flash_cycle_ich8lan(hw, 1557 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1558 if (ret_val == E1000_SUCCESS) { 1559 break; 1560 } else { 1561 /* If we're here, then things are most likely 1562 * completely hosed, but if the error condition 1563 * is detected, it won't hurt to give it another 1564 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1565 */ 1566 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1567 ICH_FLASH_HSFSTS); 1568 if (hsfsts.hsf_status.flcerr == 1) { 1569 /* Repeat for some time before giving up. */ 1570 continue; 1571 } else if (hsfsts.hsf_status.flcdone == 0) { 1572 DEBUGOUT("Timeout error - flash cycle " 1573 "did not complete."); 1574 break; 1575 } 1576 } 1577 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1578 1579out: 1580 return ret_val; 1581} 1582 1583/** 1584 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1585 * @hw: pointer to the HW structure 1586 * @offset: The index of the byte to read. 1587 * @data: The byte to write to the NVM. 1588 * 1589 * Writes a single byte to the NVM using the flash access registers. 1590 **/ 1591STATIC s32 1592e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data) 1593{ 1594 u16 word = (u16)data; 1595 1596 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1597 1598 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1599} 1600 1601/** 1602 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1603 * @hw: pointer to the HW structure 1604 * @offset: The offset of the byte to write. 1605 * @byte: The byte to write to the NVM. 1606 * 1607 * Writes a single byte to the NVM using the flash access registers. 1608 * Goes through a retry algorithm before giving up. 1609 **/ 1610static s32 1611e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte) 1612{ 1613 s32 ret_val; 1614 u16 program_retries; 1615 1616 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1617 1618 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1619 if (ret_val) 1620 goto out; 1621 1622 usec_delay(100); 1623 1624 for (program_retries = 0; program_retries < 100; program_retries++) { 1625 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1626 usec_delay(100); 1627 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1628 if (ret_val == E1000_SUCCESS) 1629 break; 1630 } 1631 if (program_retries == 100) { 1632 ret_val = -E1000_ERR_NVM; 1633 goto out; 1634 } 1635 1636out: 1637 return ret_val; 1638} 1639 1640/** 1641 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1642 * @hw: pointer to the HW structure 1643 * @bank: 0 for first bank, 1 for second bank, etc. 1644 * 1645 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1646 * bank N is 4096 * N + flash_reg_addr. 1647 **/ 1648STATIC s32 1649e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1650{ 1651 struct e1000_nvm_info *nvm = &hw->nvm; 1652 union ich8_hws_flash_status hsfsts; 1653 union ich8_hws_flash_ctrl hsflctl; 1654 u32 flash_linear_addr; 1655 u32 flash_bank_size = nvm->flash_bank_size * 2; /* bank size is in 16bit words - adjust to bytes */ 1656 s32 ret_val = E1000_SUCCESS; 1657 s32 count = 0; 1658 s32 j, iteration, sector_size; 1659 1660 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1661 1662 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1663 1664 /* Determine HW Sector size: Read BERASE bits of hw flash status 1665 * register */ 1666 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 1667 * consecutive sectors. The start index for the nth Hw sector 1668 * can be calculated as = bank * 4096 + n * 256 1669 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1670 * The start index for the nth Hw sector can be calculated 1671 * as = bank * 4096 1672 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1673 * (ich9 only, otherwise error condition) 1674 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1675 */ 1676 switch (hsfsts.hsf_status.berasesz) { 1677 case 0: 1678 /* Hw sector size 256 */ 1679 sector_size = ICH_FLASH_SEG_SIZE_256; 1680 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1681 break; 1682 case 1: 1683 sector_size = ICH_FLASH_SEG_SIZE_4K; 1684 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1685 break; 1686 case 2: 1687 if (hw->mac.type == e1000_ich9lan) { 1688 sector_size = ICH_FLASH_SEG_SIZE_8K; 1689 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1690 } else { 1691 ret_val = -E1000_ERR_NVM; 1692 goto out; 1693 } 1694 break; 1695 case 3: 1696 sector_size = ICH_FLASH_SEG_SIZE_64K; 1697 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1698 break; 1699 default: 1700 ret_val = -E1000_ERR_NVM; 1701 goto out; 1702 } 1703 1704 /* Start with the base address, then add the sector offset. */ 1705 flash_linear_addr = hw->nvm.flash_base_addr; 1706 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1707 1708 for (j = 0; j < iteration ; j++) { 1709 do { 1710 /* Steps */ 1711 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1712 if (ret_val) 1713 goto out; 1714 1715 /* Write a value 11 (block Erase) in Flash 1716 * Cycle field in hw flash control */ 1717 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1718 ICH_FLASH_HSFCTL); 1719 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1720 E1000_WRITE_FLASH_REG16(hw, 1721 ICH_FLASH_HSFCTL, 1722 hsflctl.regval); 1723 1724 /* Write the last 24 bits of an index within the 1725 * block into Flash Linear address field in Flash 1726 * Address. 1727 */ 1728 flash_linear_addr += (j * sector_size); 1729 E1000_WRITE_FLASH_REG(hw, 1730 ICH_FLASH_FADDR, 1731 flash_linear_addr); 1732 1733 ret_val = e1000_flash_cycle_ich8lan(hw, 1734 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1735 if (ret_val == E1000_SUCCESS) { 1736 break; 1737 } else { 1738 /* Check if FCERR is set to 1. If 1, 1739 * clear it and try the whole sequence 1740 * a few more times else Done */ 1741 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1742 ICH_FLASH_HSFSTS); 1743 if (hsfsts.hsf_status.flcerr == 1) { 1744 /* repeat for some time before 1745 * giving up */ 1746 continue; 1747 } else if (hsfsts.hsf_status.flcdone == 0) 1748 goto out; 1749 } 1750 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1751 } 1752 1753out: 1754 return ret_val; 1755} 1756 1757/** 1758 * e1000_valid_led_default_ich8lan - Set the default LED settings 1759 * @hw: pointer to the HW structure 1760 * @data: Pointer to the LED settings 1761 * 1762 * Reads the LED default settings from the NVM to data. If the NVM LED 1763 * settings is all 0's or F's, set the LED default to a valid LED default 1764 * setting. 1765 **/ 1766STATIC s32 1767e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1768{ 1769 s32 ret_val; 1770 1771 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1772 1773 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1774 if (ret_val) { 1775 DEBUGOUT("NVM Read Error\n"); 1776 goto out; 1777 } 1778 1779 if (*data == ID_LED_RESERVED_0000 || 1780 *data == ID_LED_RESERVED_FFFF) 1781 *data = ID_LED_DEFAULT_ICH8LAN; 1782 1783out: 1784 return ret_val; 1785} 1786 1787/** 1788 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1789 * @hw: pointer to the HW structure 1790 * 1791 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1792 * register, so the the bus width is hard coded. 1793 **/ 1794STATIC s32 1795e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1796{ 1797 struct e1000_bus_info *bus = &hw->bus; 1798 s32 ret_val; 1799 1800 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1801 1802 ret_val = e1000_get_bus_info_pcie_generic(hw); 1803 1804 /* ICH devices are "PCI Express"-ish. They have 1805 * a configuration space, but do not contain 1806 * PCI Express Capability registers, so bus width 1807 * must be hardcoded. 1808 */ 1809 if (bus->width == e1000_bus_width_unknown) 1810 bus->width = e1000_bus_width_pcie_x1; 1811 1812 return ret_val; 1813} 1814 1815/** 1816 * e1000_reset_hw_ich8lan - Reset the hardware 1817 * @hw: pointer to the HW structure 1818 * 1819 * Does a full reset of the hardware which includes a reset of the PHY and 1820 * MAC. 1821 **/ 1822STATIC s32 1823e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1824{ 1825 u32 ctrl, icr, kab; 1826 s32 ret_val; 1827 1828 DEBUGFUNC("e1000_reset_hw_ich8lan"); 1829 1830 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1831 * on the last TLP read/write transaction when MAC is reset. 1832 */ 1833 ret_val = e1000_disable_pcie_master_generic(hw); 1834 if (ret_val) { 1835 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1836 } 1837 1838 DEBUGOUT("Masking off all interrupts\n"); 1839 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1840 1841 /* Disable the Transmit and Receive units. Then delay to allow 1842 * any pending transactions to complete before we hit the MAC 1843 * with the global reset. 1844 */ 1845 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1846 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1847 E1000_WRITE_FLUSH(hw); 1848 1849 msec_delay(10); 1850 1851 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1852 if (hw->mac.type == e1000_ich8lan) { 1853 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1854 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1855 /* Set Packet Buffer Size to 16k. */ 1856 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 1857 } 1858 1859 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1860 1861 if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) { 1862 /* PHY HW reset requires MAC CORE reset at the same 1863 * time to make sure the interface between MAC and the 1864 * external PHY is reset. 1865 */ 1866 ctrl |= E1000_CTRL_PHY_RST; 1867 } 1868 ret_val = e1000_acquire_swflag_ich8lan(hw); 1869 DEBUGOUT("Issuing a global reset to ich8lan"); 1870 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 1871 msec_delay(20); 1872 1873 ret_val = e1000_get_auto_rd_done_generic(hw); 1874 if (ret_val) { 1875 /* 1876 * When auto config read does not complete, do not 1877 * return with an error. This can happen in situations 1878 * where there is no eeprom and prevents getting link. 1879 */ 1880 DEBUGOUT("Auto Read Done did not complete\n"); 1881 } 1882 1883 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1884 icr = E1000_READ_REG(hw, E1000_ICR); 1885 1886 kab = E1000_READ_REG(hw, E1000_KABGTXD); 1887 kab |= E1000_KABGTXD_BGSQLBIAS; 1888 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 1889 1890 return ret_val; 1891} 1892 1893/** 1894 * e1000_init_hw_ich8lan - Initialize the hardware 1895 * @hw: pointer to the HW structure 1896 * 1897 * Prepares the hardware for transmit and receive by doing the following: 1898 * - initialize hardware bits 1899 * - initialize LED identification 1900 * - setup receive address registers 1901 * - setup flow control 1902 * - setup transmit discriptors 1903 * - clear statistics 1904 **/ 1905STATIC s32 1906e1000_init_hw_ich8lan(struct e1000_hw *hw) 1907{ 1908 struct e1000_mac_info *mac = &hw->mac; 1909 u32 ctrl_ext, txdctl, snoop; 1910 s32 ret_val; 1911 u16 i; 1912 1913 DEBUGFUNC("e1000_init_hw_ich8lan"); 1914 1915 e1000_initialize_hw_bits_ich8lan(hw); 1916 1917 /* Initialize identification LED */ 1918 ret_val = e1000_id_led_init_generic(hw); 1919 if (ret_val) { 1920 DEBUGOUT("Error initializing identification LED\n"); 1921 goto out; 1922 } 1923 1924 /* Setup the receive address. */ 1925 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1926 1927 /* Zero out the Multicast HASH table */ 1928 DEBUGOUT("Zeroing the MTA\n"); 1929 for (i = 0; i < mac->mta_reg_count; i++) 1930 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1931 1932 /* Setup link and flow control */ 1933 ret_val = e1000_setup_link(hw); 1934 1935 /* Set the transmit descriptor write-back policy for both queues */ 1936 txdctl = E1000_READ_REG(hw, E1000_TXDCTL); 1937 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 1938 E1000_TXDCTL_FULL_TX_DESC_WB; 1939 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 1940 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 1941 E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl); 1942 txdctl = E1000_READ_REG(hw, E1000_TXDCTL1); 1943 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 1944 E1000_TXDCTL_FULL_TX_DESC_WB; 1945 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 1946 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 1947 E1000_WRITE_REG(hw, E1000_TXDCTL1, txdctl); 1948 1949 /* ICH8 has opposite polarity of no_snoop bits. 1950 * By default, we should use snoop behavior. */ 1951 if (mac->type == e1000_ich8lan) 1952 snoop = PCIE_ICH8_SNOOP_ALL; 1953 else 1954 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 1955 e1000_set_pcie_no_snoop_generic(hw, snoop); 1956 1957 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1958 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1959 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1960 1961 /* Clear all of the statistics registers (clear on read). It is 1962 * important that we do this after we have tried to establish link 1963 * because the symbol error count will increment wildly if there 1964 * is no link. 1965 */ 1966 e1000_clear_hw_cntrs_ich8lan(hw); 1967 1968out: 1969 return ret_val; 1970} 1971/** 1972 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 1973 * @hw: pointer to the HW structure 1974 * 1975 * Sets/Clears required hardware bits necessary for correctly setting up the 1976 * hardware for transmit and receive. 1977 **/ 1978static void 1979e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 1980{ 1981 u32 reg; 1982 1983 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 1984 1985 if (hw->mac.disable_hw_init_bits) 1986 goto out; 1987 1988 /* Extended Device Control */ 1989 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1990 reg |= (1 << 22); 1991 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1992 1993 /* Transmit Descriptor Control 0 */ 1994 reg = E1000_READ_REG(hw, E1000_TXDCTL); 1995 reg |= (1 << 22); 1996 E1000_WRITE_REG(hw, E1000_TXDCTL, reg); 1997 1998 /* Transmit Descriptor Control 1 */ 1999 reg = E1000_READ_REG(hw, E1000_TXDCTL1); 2000 reg |= (1 << 22); 2001 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); 2002 2003 /* Transmit Arbitration Control 0 */ 2004 reg = E1000_READ_REG(hw, E1000_TARC0); 2005 if (hw->mac.type == e1000_ich8lan) 2006 reg |= (1 << 28) | (1 << 29); 2007 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2008 E1000_WRITE_REG(hw, E1000_TARC0, reg); 2009 2010 /* Transmit Arbitration Control 1 */ 2011 reg = E1000_READ_REG(hw, E1000_TARC1); 2012 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2013 reg &= ~(1 << 28); 2014 else 2015 reg |= (1 << 28); 2016 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2017 E1000_WRITE_REG(hw, E1000_TARC1, reg); 2018 2019 /* Device Status */ 2020 if (hw->mac.type == e1000_ich8lan) { 2021 reg = E1000_READ_REG(hw, E1000_STATUS); 2022 reg &= ~(1 << 31); 2023 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2024 } 2025 2026out: 2027 return; 2028} 2029 2030/** 2031 * e1000_setup_link_ich8lan - Setup flow control and link settings 2032 * @hw: pointer to the HW structure 2033 * 2034 * Determines which flow control settings to use, then configures flow 2035 * control. Calls the appropriate media-specific link configuration 2036 * function. Assuming the adapter has a valid link partner, a valid link 2037 * should be established. Assumes the hardware has previously been reset 2038 * and the transmitter and receiver are not enabled. 2039 **/ 2040STATIC s32 2041e1000_setup_link_ich8lan(struct e1000_hw *hw) 2042{ 2043 struct e1000_mac_info *mac = &hw->mac; 2044 struct e1000_functions *func = &hw->func; 2045 s32 ret_val = E1000_SUCCESS; 2046 2047 DEBUGFUNC("e1000_setup_link_ich8lan"); 2048 2049 if (e1000_check_reset_block(hw)) 2050 goto out; 2051 2052 /* ICH parts do not have a word in the NVM to determine 2053 * the default flow control setting, so we explicitly 2054 * set it to full. 2055 */ 2056 if (mac->fc == e1000_fc_default) 2057 mac->fc = e1000_fc_full; 2058 2059 mac->original_fc = mac->fc; 2060 2061 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); 2062 2063 /* Continue to configure the copper link. */ 2064 ret_val = func->setup_physical_interface(hw); 2065 if (ret_val) 2066 goto out; 2067 2068 E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); 2069 2070 ret_val = e1000_set_fc_watermarks_generic(hw); 2071 2072out: 2073 return ret_val; 2074} 2075 2076/** 2077 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2078 * @hw: pointer to the HW structure 2079 * 2080 * Configures the kumeran interface to the PHY to wait the appropriate time 2081 * when polling the PHY, then call the generic setup_copper_link to finish 2082 * configuring the copper link. 2083 **/ 2084STATIC s32 2085e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2086{ 2087 u32 ctrl; 2088 s32 ret_val; 2089 u16 reg_data; 2090 2091 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2092 2093 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2094 ctrl |= E1000_CTRL_SLU; 2095 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2097 2098 /* Set the mac to wait the maximum time between each iteration 2099 * and increase the max iterations when polling the phy; 2100 * this fixes erroneous timeouts at 10Mbps. */ 2101 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2102 if (ret_val) 2103 goto out; 2104 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 2105 if (ret_val) 2106 goto out; 2107 reg_data |= 0x3F; 2108 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 2109 if (ret_val) 2110 goto out; 2111 2112 if (hw->phy.type == e1000_phy_igp_3) { 2113 ret_val = e1000_copper_link_setup_igp(hw); 2114 if (ret_val) 2115 goto out; 2116 } 2117 2118 ret_val = e1000_setup_copper_link_generic(hw); 2119 2120out: 2121 return ret_val; 2122} 2123 2124/** 2125 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2126 * @hw: pointer to the HW structure 2127 * @speed: pointer to store current link speed 2128 * @duplex: pointer to store the current link duplex 2129 * 2130 * Calls the generic get_speed_and_duplex to retreive the current link 2131 * information and then calls the Kumeran lock loss workaround for links at 2132 * gigabit speeds. 2133 **/ 2134STATIC s32 2135e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2136{ 2137 s32 ret_val; 2138 2139 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2140 2141 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2142 if (ret_val) 2143 goto out; 2144 2145 if ((hw->mac.type == e1000_ich8lan) && 2146 (hw->phy.type == e1000_phy_igp_3) && 2147 (*speed == SPEED_1000)) { 2148 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2149 } 2150 2151out: 2152 return ret_val; 2153} 2154 2155/** 2156 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2157 * @hw: pointer to the HW structure 2158 * 2159 * Work-around for 82566 Kumeran PCS lock loss: 2160 * On link status change (i.e. PCI reset, speed change) and link is up and 2161 * speed is gigabit- 2162 * 0) if workaround is optionally disabled do nothing 2163 * 1) wait 1ms for Kumeran link to come up 2164 * 2) check Kumeran Diagnostic register PCS lock loss bit 2165 * 3) if not set the link is locked (all is good), otherwise... 2166 * 4) reset the PHY 2167 * 5) repeat up to 10 times 2168 * Note: this is only called for IGP3 copper when speed is 1gb. 2169 **/ 2170static s32 2171e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2172{ 2173 struct e1000_dev_spec_ich8lan *dev_spec; 2174 u32 phy_ctrl; 2175 s32 ret_val = E1000_SUCCESS; 2176 u16 i, data; 2177 boolean_t link; 2178 2179 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2180 2181 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2182 2183 if (dev_spec == NULL) { 2184 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2185 ret_val = -E1000_ERR_CONFIG; 2186 goto out; 2187 } 2188 2189 if (dev_spec->kmrn_lock_loss_workaround_enabled == FALSE) 2190 goto out; 2191 2192 /* Make sure link is up before proceeding. If not just return. 2193 * Attempting this while link is negotiating fouled up link 2194 * stability */ 2195 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2196 if (!link) { 2197 ret_val = E1000_SUCCESS; 2198 goto out; 2199 } 2200 2201 for (i = 0; i < 10; i++) { 2202 /* read once to clear */ 2203 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); 2204 if (ret_val) 2205 goto out; 2206 /* and again to get new status */ 2207 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data); 2208 if (ret_val) 2209 goto out; 2210 2211 /* check for PCS lock */ 2212 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2213 ret_val = E1000_SUCCESS; 2214 goto out; 2215 } 2216 2217 /* Issue PHY reset */ 2218 e1000_phy_hw_reset(hw); 2219 msec_delay_irq(5); 2220 } 2221 /* Disable GigE link negotiation */ 2222 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2223 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2224 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2225 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2226 2227 /* Call gig speed drop workaround on Giga disable before accessing 2228 * any PHY registers */ 2229 e1000_gig_downshift_workaround_ich8lan(hw); 2230 2231 /* unable to acquire PCS lock */ 2232 ret_val = -E1000_ERR_PHY; 2233 2234out: 2235 return ret_val; 2236} 2237 2238/** 2239 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state 2240 * @hw: pointer to the HW structure 2241 * @state: boolean value used to set the current Kumaran workaround state 2242 * 2243 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2244 * /disabled - FALSE). 2245 **/ 2246void 2247e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2248 boolean_t state) 2249{ 2250 struct e1000_dev_spec_ich8lan *dev_spec; 2251 2252 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2253 2254 if (hw->mac.type != e1000_ich8lan) { 2255 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2256 goto out; 2257 } 2258 2259 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2260 2261 if (dev_spec == NULL) { 2262 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2263 goto out; 2264 } 2265 2266 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2267 2268out: 2269 return; 2270} 2271 2272/** 2273 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2274 * @hw: pointer to the HW structure 2275 * 2276 * Workaround for 82566 power-down on D3 entry: 2277 * 1) disable gigabit link 2278 * 2) write VR power-down enable 2279 * 3) read it back 2280 * Continue if successful, else issue LCD reset and repeat 2281 **/ 2282void 2283e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2284{ 2285 u32 reg; 2286 u16 data; 2287 u8 retry = 0; 2288 2289 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2290 2291 if (hw->phy.type != e1000_phy_igp_3) 2292 goto out; 2293 2294 /* Try the workaround twice (if needed) */ 2295 do { 2296 /* Disable link */ 2297 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2298 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2299 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2300 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2301 2302 /* Call gig speed drop workaround on Giga disable before 2303 * accessing any PHY registers */ 2304 if (hw->mac.type == e1000_ich8lan) 2305 e1000_gig_downshift_workaround_ich8lan(hw); 2306 2307 /* Write VR power-down enable */ 2308 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); 2309 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2310 e1000_write_phy_reg(hw, 2311 IGP3_VR_CTRL, 2312 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2313 2314 /* Read it back and test */ 2315 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data); 2316 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2317 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2318 break; 2319 2320 /* Issue PHY reset and repeat at most one more time */ 2321 reg = E1000_READ_REG(hw, E1000_CTRL); 2322 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2323 retry++; 2324 } while (retry); 2325 2326out: 2327 return; 2328} 2329 2330/** 2331 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2332 * @hw: pointer to the HW structure 2333 * 2334 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2335 * LPLU, Giga disable, MDIC PHY reset): 2336 * 1) Set Kumeran Near-end loopback 2337 * 2) Clear Kumeran Near-end loopback 2338 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2339 **/ 2340void 2341e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2342{ 2343 s32 ret_val = E1000_SUCCESS; 2344 u16 reg_data; 2345 2346 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2347 2348 if ((hw->mac.type != e1000_ich8lan) || 2349 (hw->phy.type != e1000_phy_igp_3)) 2350 goto out; 2351 2352 ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2353 ®_data); 2354 if (ret_val) 2355 goto out; 2356 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2357 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2358 reg_data); 2359 if (ret_val) 2360 goto out; 2361 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2362 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2363 reg_data); 2364out: 2365 return; 2366} 2367 2368/** 2369 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2370 * @hw: pointer to the HW structure 2371 * 2372 * Return the LED back to the default configuration. 2373 **/ 2374STATIC s32 2375e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2376{ 2377 s32 ret_val = E1000_SUCCESS; 2378 2379 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2380 2381 if (hw->phy.type == e1000_phy_ife) 2382 ret_val = e1000_write_phy_reg(hw, 2383 IFE_PHY_SPECIAL_CONTROL_LED, 2384 0); 2385 else 2386 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2387 2388 return ret_val; 2389} 2390 2391/** 2392 * e1000_led_on_ich8lan - Turn LED's on 2393 * @hw: pointer to the HW structure 2394 * 2395 * Turn on the LED's. 2396 **/ 2397STATIC s32 2398e1000_led_on_ich8lan(struct e1000_hw *hw) 2399{ 2400 s32 ret_val = E1000_SUCCESS; 2401 2402 DEBUGFUNC("e1000_led_on_ich8lan"); 2403 2404 if (hw->phy.type == e1000_phy_ife) 2405 ret_val = e1000_write_phy_reg(hw, 2406 IFE_PHY_SPECIAL_CONTROL_LED, 2407 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2408 else 2409 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2410 2411 return ret_val; 2412} 2413 2414/** 2415 * e1000_led_off_ich8lan - Turn LED's off 2416 * @hw: pointer to the HW structure 2417 * 2418 * Turn off the LED's. 2419 **/ 2420STATIC s32 2421e1000_led_off_ich8lan(struct e1000_hw *hw) 2422{ 2423 s32 ret_val = E1000_SUCCESS; 2424 2425 DEBUGFUNC("e1000_led_off_ich8lan"); 2426 2427 if (hw->phy.type == e1000_phy_ife) 2428 ret_val = e1000_write_phy_reg(hw, 2429 IFE_PHY_SPECIAL_CONTROL_LED, 2430 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2431 else 2432 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2433 2434 return ret_val; 2435} 2436 2437/** 2438 * e1000_get_cfg_done_ich8lan - Read config done bit 2439 * @hw: pointer to the HW structure 2440 * 2441 * Read the management control register for the config done bit for 2442 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2443 * to read the config done bit, so an error is *ONLY* logged and returns 2444 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2445 * would not be able to be reset or change link. 2446 **/ 2447STATIC s32 2448e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2449{ 2450 e1000_get_cfg_done_generic(hw); 2451 2452 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2453 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2454 (hw->phy.type == e1000_phy_igp_3)) { 2455 e1000_phy_init_script_igp3(hw); 2456 } 2457 2458 return E1000_SUCCESS; 2459} 2460 2461/** 2462 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2463 * @hw: pointer to the HW structure 2464 * 2465 * Clears hardware counters specific to the silicon family and calls 2466 * clear_hw_cntrs_generic to clear all general purpose counters. 2467 **/ 2468STATIC void 2469e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2470{ 2471 volatile u32 temp; 2472 2473 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2474 2475 e1000_clear_hw_cntrs_base_generic(hw); 2476 2477 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 2478 temp = E1000_READ_REG(hw, E1000_RXERRC); 2479 temp = E1000_READ_REG(hw, E1000_TNCRS); 2480 temp = E1000_READ_REG(hw, E1000_CEXTERR); 2481 temp = E1000_READ_REG(hw, E1000_TSCTC); 2482 temp = E1000_READ_REG(hw, E1000_TSCTFC); 2483 2484 temp = E1000_READ_REG(hw, E1000_MGTPRC); 2485 temp = E1000_READ_REG(hw, E1000_MGTPDC); 2486 temp = E1000_READ_REG(hw, E1000_MGTPTC); 2487 2488 temp = E1000_READ_REG(hw, E1000_IAC); 2489 temp = E1000_READ_REG(hw, E1000_ICRXOC); 2490} 2491 2492