1177867Sjfv/****************************************************************************** 2169240Sjfv 3248292Sjfv Copyright (c) 2001-2013, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35248292Sjfv/* 82562G 10/100 Network Connection 36185353Sjfv * 82562G-2 10/100 Network Connection 37185353Sjfv * 82562GT 10/100 Network Connection 38185353Sjfv * 82562GT-2 10/100 Network Connection 39185353Sjfv * 82562V 10/100 Network Connection 40185353Sjfv * 82562V-2 10/100 Network Connection 41185353Sjfv * 82566DC-2 Gigabit Network Connection 42185353Sjfv * 82566DC Gigabit Network Connection 43185353Sjfv * 82566DM-2 Gigabit Network Connection 44185353Sjfv * 82566DM Gigabit Network Connection 45185353Sjfv * 82566MC Gigabit Network Connection 46185353Sjfv * 82566MM Gigabit Network Connection 47185353Sjfv * 82567LM Gigabit Network Connection 48185353Sjfv * 82567LF Gigabit Network Connection 49185353Sjfv * 82567V Gigabit Network Connection 50185353Sjfv * 82567LM-2 Gigabit Network Connection 51185353Sjfv * 82567LF-2 Gigabit Network Connection 52185353Sjfv * 82567V-2 Gigabit Network Connection 53185353Sjfv * 82567LF-3 Gigabit Network Connection 54185353Sjfv * 82567LM-3 Gigabit Network Connection 55185353Sjfv * 82567LM-4 Gigabit Network Connection 56194865Sjfv * 82577LM Gigabit Network Connection 57194865Sjfv * 82577LC Gigabit Network Connection 58194865Sjfv * 82578DM Gigabit Network Connection 59194865Sjfv * 82578DC Gigabit Network Connection 60213234Sjfv * 82579LM Gigabit Network Connection 61213234Sjfv * 82579V Gigabit Network Connection 62169240Sjfv */ 63169240Sjfv 64169589Sjfv#include "e1000_api.h" 65169240Sjfv 66177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 67177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 68200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 69200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 71213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 72213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 73248292Sjfvstatic void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 74218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 75235527Sjfv u8 *mc_addr_list, 76235527Sjfv u32 mc_addr_count); 77177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 78177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 79200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 80177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 81235527Sjfv bool active); 82177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 83235527Sjfv bool active); 84177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 85235527Sjfv u16 words, u16 *data); 86177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 87235527Sjfv u16 words, u16 *data); 88177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 89177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 90177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 91235527Sjfv u16 *data); 92194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 93177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 94177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 95177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 96177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 97177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 98248292Sjfvstatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 99177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 100235527Sjfv u16 *speed, u16 *duplex); 101177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 102177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 103177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 104200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 105194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 106194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 107194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 108194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 109177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 110177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 111173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 112173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 113178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 114235527Sjfv u32 offset, u8 *data); 115173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 116235527Sjfv u8 size, u16 *data); 117177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 118235527Sjfv u32 offset, u16 *data); 119173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 120235527Sjfv u32 offset, u8 byte); 121177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 122177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 123200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 124203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 125213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 126213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 127248292Sjfvstatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); 128169240Sjfv 129169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 130169240Sjfv/* Offset 04h HSFSTS */ 131169240Sjfvunion ich8_hws_flash_status { 132169240Sjfv struct ich8_hsfsts { 133235527Sjfv u16 flcdone:1; /* bit 0 Flash Cycle Done */ 134235527Sjfv u16 flcerr:1; /* bit 1 Flash Cycle Error */ 135235527Sjfv u16 dael:1; /* bit 2 Direct Access error Log */ 136235527Sjfv u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 137235527Sjfv u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 138235527Sjfv u16 reserved1:2; /* bit 13:6 Reserved */ 139235527Sjfv u16 reserved2:6; /* bit 13:6 Reserved */ 140235527Sjfv u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 141235527Sjfv u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 142169240Sjfv } hsf_status; 143169240Sjfv u16 regval; 144169240Sjfv}; 145169240Sjfv 146169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 147169240Sjfv/* Offset 06h FLCTL */ 148169240Sjfvunion ich8_hws_flash_ctrl { 149169240Sjfv struct ich8_hsflctl { 150235527Sjfv u16 flcgo:1; /* 0 Flash Cycle Go */ 151235527Sjfv u16 flcycle:2; /* 2:1 Flash Cycle */ 152235527Sjfv u16 reserved:5; /* 7:3 Reserved */ 153235527Sjfv u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 154235527Sjfv u16 flockdn:6; /* 15:10 Reserved */ 155169240Sjfv } hsf_ctrl; 156169240Sjfv u16 regval; 157169240Sjfv}; 158169240Sjfv 159169240Sjfv/* ICH Flash Region Access Permissions */ 160169240Sjfvunion ich8_hws_flash_regacc { 161169240Sjfv struct ich8_flracc { 162235527Sjfv u32 grra:8; /* 0:7 GbE region Read Access */ 163235527Sjfv u32 grwa:8; /* 8:15 GbE region Write Access */ 164235527Sjfv u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 165235527Sjfv u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 166169240Sjfv } hsf_flregacc; 167169240Sjfv u16 regval; 168169240Sjfv}; 169169240Sjfv 170248292Sjfv/** 171248292Sjfv * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 172248292Sjfv * @hw: pointer to the HW structure 173248292Sjfv * 174248292Sjfv * Test access to the PHY registers by reading the PHY ID registers. If 175248292Sjfv * the PHY ID is already known (e.g. resume path) compare it with known ID, 176248292Sjfv * otherwise assume the read PHY ID is correct if it is valid. 177248292Sjfv * 178248292Sjfv * Assumes the sw/fw/hw semaphore is already acquired. 179248292Sjfv **/ 180248292Sjfvstatic bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 181235527Sjfv{ 182248292Sjfv u16 phy_reg = 0; 183248292Sjfv u32 phy_id = 0; 184248292Sjfv s32 ret_val; 185248292Sjfv u16 retry_count; 186235527Sjfv 187248292Sjfv for (retry_count = 0; retry_count < 2; retry_count++) { 188248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); 189248292Sjfv if (ret_val || (phy_reg == 0xFFFF)) 190248292Sjfv continue; 191248292Sjfv phy_id = (u32)(phy_reg << 16); 192235527Sjfv 193248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); 194248292Sjfv if (ret_val || (phy_reg == 0xFFFF)) { 195248292Sjfv phy_id = 0; 196248292Sjfv continue; 197248292Sjfv } 198248292Sjfv phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 199248292Sjfv break; 200248292Sjfv } 201248292Sjfv 202248292Sjfv if (hw->phy.id) { 203248292Sjfv if (hw->phy.id == phy_id) 204248292Sjfv return TRUE; 205248292Sjfv } else if (phy_id) { 206248292Sjfv hw->phy.id = phy_id; 207248292Sjfv hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 208248292Sjfv return TRUE; 209248292Sjfv } 210248292Sjfv 211248292Sjfv /* In case the PHY needs to be in mdio slow mode, 212248292Sjfv * set slow mode and try to get the PHY id again. 213248292Sjfv */ 214248292Sjfv hw->phy.ops.release(hw); 215248292Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 216248292Sjfv if (!ret_val) 217248292Sjfv ret_val = e1000_get_phy_id(hw); 218248292Sjfv hw->phy.ops.acquire(hw); 219248292Sjfv 220248292Sjfv return !ret_val; 221235527Sjfv} 222235527Sjfv 223169240Sjfv/** 224248292Sjfv * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 225248292Sjfv * @hw: pointer to the HW structure 226248292Sjfv * 227248292Sjfv * Workarounds/flow necessary for PHY initialization during driver load 228248292Sjfv * and resume paths. 229248292Sjfv **/ 230248292Sjfvstatic s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 231248292Sjfv{ 232248292Sjfv u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); 233248292Sjfv s32 ret_val; 234248292Sjfv u16 phy_reg; 235248292Sjfv 236248292Sjfv DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); 237248292Sjfv 238248292Sjfv /* Gate automatic PHY configuration by hardware on managed and 239248292Sjfv * non-managed 82579 and newer adapters. 240248292Sjfv */ 241248292Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 242248292Sjfv 243248292Sjfv ret_val = hw->phy.ops.acquire(hw); 244248292Sjfv if (ret_val) { 245248292Sjfv DEBUGOUT("Failed to initialize PHY flow\n"); 246248292Sjfv goto out; 247248292Sjfv } 248248292Sjfv 249248292Sjfv /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 250248292Sjfv * inaccessible and resetting the PHY is not blocked, toggle the 251248292Sjfv * LANPHYPC Value bit to force the interconnect to PCIe mode. 252248292Sjfv */ 253248292Sjfv switch (hw->mac.type) { 254248292Sjfv case e1000_pch_lpt: 255248292Sjfv if (e1000_phy_is_accessible_pchlan(hw)) 256248292Sjfv break; 257248292Sjfv 258248292Sjfv /* Before toggling LANPHYPC, see if PHY is accessible by 259248292Sjfv * forcing MAC to SMBus mode first. 260248292Sjfv */ 261248292Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 262248292Sjfv mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 263248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 264248292Sjfv 265248292Sjfv /* fall-through */ 266248292Sjfv case e1000_pch2lan: 267248292Sjfv if (e1000_phy_is_accessible_pchlan(hw)) { 268248292Sjfv if (hw->mac.type == e1000_pch_lpt) { 269248292Sjfv /* Unforce SMBus mode in PHY */ 270248292Sjfv hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, 271248292Sjfv &phy_reg); 272248292Sjfv phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 273248292Sjfv hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, 274248292Sjfv phy_reg); 275248292Sjfv 276248292Sjfv /* Unforce SMBus mode in MAC */ 277248292Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 278248292Sjfv mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 279248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 280248292Sjfv } 281248292Sjfv break; 282248292Sjfv } 283248292Sjfv 284248292Sjfv /* fall-through */ 285248292Sjfv case e1000_pchlan: 286248292Sjfv if ((hw->mac.type == e1000_pchlan) && 287248292Sjfv (fwsm & E1000_ICH_FWSM_FW_VALID)) 288248292Sjfv break; 289248292Sjfv 290248292Sjfv if (hw->phy.ops.check_reset_block(hw)) { 291248292Sjfv DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); 292248292Sjfv break; 293248292Sjfv } 294248292Sjfv 295248292Sjfv DEBUGOUT("Toggling LANPHYPC\n"); 296248292Sjfv 297248292Sjfv /* Set Phy Config Counter to 50msec */ 298248292Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 299248292Sjfv mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 300248292Sjfv mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 301248292Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); 302248292Sjfv 303248292Sjfv if (hw->mac.type == e1000_pch_lpt) { 304248292Sjfv /* Toggling LANPHYPC brings the PHY out of SMBus mode 305248292Sjfv * So ensure that the MAC is also out of SMBus mode 306248292Sjfv */ 307248292Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 308248292Sjfv mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 309248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 310248292Sjfv } 311248292Sjfv 312248292Sjfv /* Toggle LANPHYPC Value bit */ 313248292Sjfv mac_reg = E1000_READ_REG(hw, E1000_CTRL); 314248292Sjfv mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 315248292Sjfv mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 316248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 317248292Sjfv E1000_WRITE_FLUSH(hw); 318248292Sjfv usec_delay(10); 319248292Sjfv mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 320248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 321248292Sjfv E1000_WRITE_FLUSH(hw); 322248292Sjfv if (hw->mac.type < e1000_pch_lpt) { 323248292Sjfv msec_delay(50); 324248292Sjfv } else { 325248292Sjfv u16 count = 20; 326248292Sjfv do { 327248292Sjfv msec_delay(5); 328248292Sjfv } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & 329248292Sjfv E1000_CTRL_EXT_LPCD) && count--); 330248292Sjfv } 331248292Sjfv break; 332248292Sjfv default: 333248292Sjfv break; 334248292Sjfv } 335248292Sjfv 336248292Sjfv hw->phy.ops.release(hw); 337248292Sjfv 338248292Sjfv /* Reset the PHY before any access to it. Doing so, ensures 339248292Sjfv * that the PHY is in a known good state before we read/write 340248292Sjfv * PHY registers. The generic reset is sufficient here, 341248292Sjfv * because we haven't determined the PHY type yet. 342248292Sjfv */ 343248292Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 344248292Sjfv 345248292Sjfvout: 346248292Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 347248292Sjfv if ((hw->mac.type == e1000_pch2lan) && 348248292Sjfv !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 349248292Sjfv msec_delay(10); 350248292Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 351248292Sjfv } 352248292Sjfv 353248292Sjfv return ret_val; 354248292Sjfv} 355248292Sjfv 356248292Sjfv/** 357194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 358194865Sjfv * @hw: pointer to the HW structure 359194865Sjfv * 360194865Sjfv * Initialize family-specific PHY parameters and function pointers. 361194865Sjfv **/ 362194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 363194865Sjfv{ 364194865Sjfv struct e1000_phy_info *phy = &hw->phy; 365248292Sjfv s32 ret_val; 366194865Sjfv 367194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 368194865Sjfv 369235527Sjfv phy->addr = 1; 370235527Sjfv phy->reset_delay_us = 100; 371194865Sjfv 372235527Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 373235527Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 374235527Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 375235527Sjfv phy->ops.set_page = e1000_set_page_igp; 376235527Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 377235527Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 378235527Sjfv phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 379235527Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 380235527Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 381235527Sjfv phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 382235527Sjfv phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 383235527Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 384235527Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 385235527Sjfv phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 386235527Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 387235527Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 388235527Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 389194865Sjfv 390248292Sjfv phy->id = e1000_phy_unknown; 391235527Sjfv 392248292Sjfv ret_val = e1000_init_phy_workarounds_pchlan(hw); 393248292Sjfv if (ret_val) 394248292Sjfv return ret_val; 395213234Sjfv 396248292Sjfv if (phy->id == e1000_phy_unknown) 397248292Sjfv switch (hw->mac.type) { 398248292Sjfv default: 399248292Sjfv ret_val = e1000_get_phy_id(hw); 400248292Sjfv if (ret_val) 401248292Sjfv return ret_val; 402248292Sjfv if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 403248292Sjfv break; 404248292Sjfv /* fall-through */ 405248292Sjfv case e1000_pch2lan: 406248292Sjfv case e1000_pch_lpt: 407248292Sjfv /* In case the PHY needs to be in mdio slow mode, 408248292Sjfv * set slow mode and try to get the PHY id again. 409248292Sjfv */ 410248292Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 411248292Sjfv if (ret_val) 412248292Sjfv return ret_val; 413248292Sjfv ret_val = e1000_get_phy_id(hw); 414248292Sjfv if (ret_val) 415248292Sjfv return ret_val; 416248292Sjfv break; 417235527Sjfv } 418194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 419194865Sjfv 420200243Sjfv switch (phy->type) { 421200243Sjfv case e1000_phy_82577: 422213234Sjfv case e1000_phy_82579: 423248292Sjfv case e1000_phy_i217: 424194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 425194865Sjfv phy->ops.force_speed_duplex = 426194865Sjfv e1000_phy_force_speed_duplex_82577; 427200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 428194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 429194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 430205869Sjfv break; 431200243Sjfv case e1000_phy_82578: 432200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 433200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 434200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 435200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 436200243Sjfv break; 437200243Sjfv default: 438200243Sjfv ret_val = -E1000_ERR_PHY; 439200243Sjfv break; 440194865Sjfv } 441194865Sjfv 442194865Sjfv return ret_val; 443194865Sjfv} 444194865Sjfv 445194865Sjfv/** 446169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 447169589Sjfv * @hw: pointer to the HW structure 448169240Sjfv * 449169240Sjfv * Initialize family-specific PHY parameters and function pointers. 450169240Sjfv **/ 451177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 452169240Sjfv{ 453169240Sjfv struct e1000_phy_info *phy = &hw->phy; 454248292Sjfv s32 ret_val; 455169589Sjfv u16 i = 0; 456169240Sjfv 457169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 458169240Sjfv 459235527Sjfv phy->addr = 1; 460235527Sjfv phy->reset_delay_us = 100; 461169240Sjfv 462235527Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 463235527Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 464235527Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 465235527Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 466235527Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 467235527Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 468235527Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 469235527Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 470235527Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 471235527Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 472235527Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 473235527Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 474169240Sjfv 475248292Sjfv /* We may need to do this twice - once for IGP and if that fails, 476176667Sjfv * we'll set BM func pointers and try again 477176667Sjfv */ 478176667Sjfv ret_val = e1000_determine_phy_address(hw); 479176667Sjfv if (ret_val) { 480177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 481177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 482176667Sjfv ret_val = e1000_determine_phy_address(hw); 483176667Sjfv if (ret_val) { 484190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 485248292Sjfv return ret_val; 486176667Sjfv } 487176667Sjfv } 488169240Sjfv 489169589Sjfv phy->id = 0; 490169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 491169589Sjfv (i++ < 100)) { 492169589Sjfv msec_delay(1); 493169589Sjfv ret_val = e1000_get_phy_id(hw); 494169589Sjfv if (ret_val) 495248292Sjfv return ret_val; 496169589Sjfv } 497169589Sjfv 498169240Sjfv /* Verify phy id */ 499169240Sjfv switch (phy->id) { 500169240Sjfv case IGP03E1000_E_PHY_ID: 501169240Sjfv phy->type = e1000_phy_igp_3; 502169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 503200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 504200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 505200243Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 506200243Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 507200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 508169240Sjfv break; 509169240Sjfv case IFE_E_PHY_ID: 510169240Sjfv case IFE_PLUS_E_PHY_ID: 511169240Sjfv case IFE_C_E_PHY_ID: 512169240Sjfv phy->type = e1000_phy_ife; 513169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 514200243Sjfv phy->ops.get_info = e1000_get_phy_info_ife; 515200243Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 516200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 517169240Sjfv break; 518176667Sjfv case BME1000_E_PHY_ID: 519176667Sjfv phy->type = e1000_phy_bm; 520176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 521177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 522177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 523177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 524200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 525200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 526200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 527176667Sjfv break; 528169240Sjfv default: 529248292Sjfv return -E1000_ERR_PHY; 530248292Sjfv break; 531169240Sjfv } 532169240Sjfv 533248292Sjfv return E1000_SUCCESS; 534169240Sjfv} 535169240Sjfv 536169240Sjfv/** 537169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 538169589Sjfv * @hw: pointer to the HW structure 539169240Sjfv * 540169240Sjfv * Initialize family-specific NVM parameters and function 541169240Sjfv * pointers. 542169240Sjfv **/ 543177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 544169240Sjfv{ 545169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 546185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 547169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 548169240Sjfv u16 i; 549169240Sjfv 550169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 551169240Sjfv 552173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 553169240Sjfv if (!hw->flash_address) { 554169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 555248292Sjfv return -E1000_ERR_CONFIG; 556169240Sjfv } 557169240Sjfv 558185353Sjfv nvm->type = e1000_nvm_flash_sw; 559169240Sjfv 560169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 561169240Sjfv 562248292Sjfv /* sector_X_addr is a "sector"-aligned address (4096 bytes) 563169240Sjfv * Add 1 to sector_end_addr since this sector is included in 564173788Sjfv * the overall size. 565173788Sjfv */ 566169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 567169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 568169240Sjfv 569169240Sjfv /* flash_base_addr is byte-aligned */ 570185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 571169240Sjfv 572248292Sjfv /* find total size of the NVM, then cut in half since the total 573173788Sjfv * size represents two separate NVM banks. 574173788Sjfv */ 575185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 576235527Sjfv << FLASH_SECTOR_ADDR_SHIFT; 577185353Sjfv nvm->flash_bank_size /= 2; 578169240Sjfv /* Adjust to word count */ 579185353Sjfv nvm->flash_bank_size /= sizeof(u16); 580169240Sjfv 581185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 582169240Sjfv 583169240Sjfv /* Clear shadow ram */ 584169240Sjfv for (i = 0; i < nvm->word_size; i++) { 585169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 586169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 587169240Sjfv } 588169240Sjfv 589200243Sjfv E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 590200243Sjfv E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 591200243Sjfv 592169240Sjfv /* Function Pointers */ 593235527Sjfv nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 594235527Sjfv nvm->ops.release = e1000_release_nvm_ich8lan; 595235527Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 596235527Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 597177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 598235527Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 599235527Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 600169240Sjfv 601248292Sjfv return E1000_SUCCESS; 602169240Sjfv} 603169240Sjfv 604169240Sjfv/** 605169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 606169589Sjfv * @hw: pointer to the HW structure 607169240Sjfv * 608169240Sjfv * Initialize family-specific MAC parameters and function 609169240Sjfv * pointers. 610169240Sjfv **/ 611177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 612169240Sjfv{ 613169240Sjfv struct e1000_mac_info *mac = &hw->mac; 614169240Sjfv 615169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 616169240Sjfv 617169240Sjfv /* Set media type function pointer */ 618173788Sjfv hw->phy.media_type = e1000_media_type_copper; 619169240Sjfv 620169240Sjfv /* Set mta register count */ 621169240Sjfv mac->mta_reg_count = 32; 622169240Sjfv /* Set rar entry count */ 623169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 624169240Sjfv if (mac->type == e1000_ich8lan) 625169240Sjfv mac->rar_entry_count--; 626169240Sjfv /* Set if part includes ASF firmware */ 627169240Sjfv mac->asf_firmware_present = TRUE; 628205869Sjfv /* FWSM register */ 629205869Sjfv mac->has_fwsm = TRUE; 630205869Sjfv /* ARC subsystem not supported */ 631205869Sjfv mac->arc_subsystem_valid = FALSE; 632200243Sjfv /* Adaptive IFS supported */ 633200243Sjfv mac->adaptive_ifs = TRUE; 634169240Sjfv 635169240Sjfv /* Function pointers */ 636169240Sjfv 637169240Sjfv /* bus type/speed/width */ 638177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 639185353Sjfv /* function id */ 640185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 641169240Sjfv /* reset */ 642177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 643169240Sjfv /* hw initialization */ 644177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 645169240Sjfv /* link setup */ 646177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 647169240Sjfv /* physical interface setup */ 648177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 649169240Sjfv /* check for link */ 650200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 651169240Sjfv /* link info */ 652177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 653169240Sjfv /* multicast address update */ 654177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 655169240Sjfv /* clear hardware counters */ 656177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 657169240Sjfv 658248292Sjfv /* LED and other operations */ 659190872Sjfv switch (mac->type) { 660190872Sjfv case e1000_ich8lan: 661190872Sjfv case e1000_ich9lan: 662190872Sjfv case e1000_ich10lan: 663213234Sjfv /* check management mode */ 664213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 665190872Sjfv /* ID LED init */ 666190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 667190872Sjfv /* blink LED */ 668190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 669190872Sjfv /* setup LED */ 670190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 671190872Sjfv /* cleanup LED */ 672190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 673190872Sjfv /* turn on/off LED */ 674190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 675190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 676190872Sjfv break; 677213234Sjfv case e1000_pch2lan: 678213234Sjfv mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 679213234Sjfv mac->ops.rar_set = e1000_rar_set_pch2lan; 680248292Sjfv /* fall-through */ 681248292Sjfv case e1000_pch_lpt: 682218588Sjfv /* multicast address update for pch2 */ 683218588Sjfv mac->ops.update_mc_addr_list = 684218588Sjfv e1000_update_mc_addr_list_pch2lan; 685194865Sjfv case e1000_pchlan: 686213234Sjfv /* check management mode */ 687213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 688194865Sjfv /* ID LED init */ 689194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 690194865Sjfv /* setup LED */ 691194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 692194865Sjfv /* cleanup LED */ 693194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 694194865Sjfv /* turn on/off LED */ 695194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 696194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 697194865Sjfv break; 698190872Sjfv default: 699190872Sjfv break; 700190872Sjfv } 701190872Sjfv 702235527Sjfv if (mac->type == e1000_pch_lpt) { 703248292Sjfv mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 704248292Sjfv mac->ops.rar_set = e1000_rar_set_pch_lpt; 705248292Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; 706248292Sjfv mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; 707235527Sjfv } 708235527Sjfv 709169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 710169240Sjfv if (mac->type == e1000_ich8lan) 711169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 712169240Sjfv 713185353Sjfv return E1000_SUCCESS; 714169240Sjfv} 715169240Sjfv 716169240Sjfv/** 717248292Sjfv * __e1000_access_emi_reg_locked - Read/write EMI register 718248292Sjfv * @hw: pointer to the HW structure 719248292Sjfv * @addr: EMI address to program 720248292Sjfv * @data: pointer to value to read/write from/to the EMI address 721248292Sjfv * @read: boolean flag to indicate read or write 722248292Sjfv * 723248292Sjfv * This helper function assumes the SW/FW/HW Semaphore is already acquired. 724248292Sjfv **/ 725248292Sjfvstatic s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 726248292Sjfv u16 *data, bool read) 727248292Sjfv{ 728248292Sjfv s32 ret_val; 729248292Sjfv 730248292Sjfv DEBUGFUNC("__e1000_access_emi_reg_locked"); 731248292Sjfv 732248292Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); 733248292Sjfv if (ret_val) 734248292Sjfv return ret_val; 735248292Sjfv 736248292Sjfv if (read) 737248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, 738248292Sjfv data); 739248292Sjfv else 740248292Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 741248292Sjfv *data); 742248292Sjfv 743248292Sjfv return ret_val; 744248292Sjfv} 745248292Sjfv 746248292Sjfv/** 747248292Sjfv * e1000_read_emi_reg_locked - Read Extended Management Interface register 748248292Sjfv * @hw: pointer to the HW structure 749248292Sjfv * @addr: EMI address to program 750248292Sjfv * @data: value to be read from the EMI address 751248292Sjfv * 752248292Sjfv * Assumes the SW/FW/HW Semaphore is already acquired. 753248292Sjfv **/ 754248292Sjfvs32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 755248292Sjfv{ 756248292Sjfv DEBUGFUNC("e1000_read_emi_reg_locked"); 757248292Sjfv 758248292Sjfv return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); 759248292Sjfv} 760248292Sjfv 761248292Sjfv/** 762248292Sjfv * e1000_write_emi_reg_locked - Write Extended Management Interface register 763248292Sjfv * @hw: pointer to the HW structure 764248292Sjfv * @addr: EMI address to program 765248292Sjfv * @data: value to be written to the EMI address 766248292Sjfv * 767248292Sjfv * Assumes the SW/FW/HW Semaphore is already acquired. 768248292Sjfv **/ 769248292Sjfvstatic s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 770248292Sjfv{ 771248292Sjfv DEBUGFUNC("e1000_read_emi_reg_locked"); 772248292Sjfv 773248292Sjfv return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); 774248292Sjfv} 775248292Sjfv 776248292Sjfv/** 777213234Sjfv * e1000_set_eee_pchlan - Enable/disable EEE support 778213234Sjfv * @hw: pointer to the HW structure 779213234Sjfv * 780248292Sjfv * Enable/disable EEE based on setting in dev_spec structure, the duplex of 781248292Sjfv * the link and the EEE capabilities of the link partner. The LPI Control 782248292Sjfv * register bits will remain set only if/when link is up. 783213234Sjfv **/ 784213234Sjfvstatic s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 785213234Sjfv{ 786235527Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 787248292Sjfv s32 ret_val; 788248292Sjfv u16 lpi_ctrl; 789213234Sjfv 790213234Sjfv DEBUGFUNC("e1000_set_eee_pchlan"); 791213234Sjfv 792248292Sjfv if ((hw->phy.type != e1000_phy_82579) && 793248292Sjfv (hw->phy.type != e1000_phy_i217)) 794248292Sjfv return E1000_SUCCESS; 795213234Sjfv 796248292Sjfv ret_val = hw->phy.ops.acquire(hw); 797213234Sjfv if (ret_val) 798248292Sjfv return ret_val; 799213234Sjfv 800248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 801248292Sjfv if (ret_val) 802248292Sjfv goto release; 803213234Sjfv 804248292Sjfv /* Clear bits that enable EEE in various speeds */ 805248292Sjfv lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 806248292Sjfv 807248292Sjfv /* Enable EEE if not disabled by user */ 808248292Sjfv if (!dev_spec->eee_disable) { 809248292Sjfv u16 lpa, pcs_status, data; 810248292Sjfv 811248292Sjfv /* Save off link partner's EEE ability */ 812248292Sjfv switch (hw->phy.type) { 813248292Sjfv case e1000_phy_82579: 814248292Sjfv lpa = I82579_EEE_LP_ABILITY; 815248292Sjfv pcs_status = I82579_EEE_PCS_STATUS; 816248292Sjfv break; 817248292Sjfv case e1000_phy_i217: 818248292Sjfv lpa = I217_EEE_LP_ABILITY; 819248292Sjfv pcs_status = I217_EEE_PCS_STATUS; 820248292Sjfv break; 821248292Sjfv default: 822248292Sjfv ret_val = -E1000_ERR_PHY; 823248292Sjfv goto release; 824248292Sjfv } 825248292Sjfv ret_val = e1000_read_emi_reg_locked(hw, lpa, 826248292Sjfv &dev_spec->eee_lp_ability); 827248292Sjfv if (ret_val) 828248292Sjfv goto release; 829248292Sjfv 830248292Sjfv /* Enable EEE only for speeds in which the link partner is 831248292Sjfv * EEE capable. 832248292Sjfv */ 833248292Sjfv if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 834248292Sjfv lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 835248292Sjfv 836248292Sjfv if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 837248292Sjfv hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); 838248292Sjfv if (data & NWAY_LPAR_100TX_FD_CAPS) 839248292Sjfv lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 840248292Sjfv else 841248292Sjfv /* EEE is not supported in 100Half, so ignore 842248292Sjfv * partner's EEE in 100 ability if full-duplex 843248292Sjfv * is not advertised. 844248292Sjfv */ 845248292Sjfv dev_spec->eee_lp_ability &= 846248292Sjfv ~I82579_EEE_100_SUPPORTED; 847248292Sjfv } 848248292Sjfv 849248292Sjfv /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 850248292Sjfv ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 851248292Sjfv if (ret_val) 852248292Sjfv goto release; 853248292Sjfv } 854248292Sjfv 855248292Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 856248292Sjfvrelease: 857248292Sjfv hw->phy.ops.release(hw); 858248292Sjfv 859213234Sjfv return ret_val; 860213234Sjfv} 861213234Sjfv 862213234Sjfv/** 863248292Sjfv * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 864248292Sjfv * @hw: pointer to the HW structure 865248292Sjfv * @link: link up bool flag 866248292Sjfv * 867248292Sjfv * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 868248292Sjfv * preventing further DMA write requests. Workaround the issue by disabling 869248292Sjfv * the de-assertion of the clock request when in 1Gpbs mode. 870248292Sjfv **/ 871248292Sjfvstatic s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 872248292Sjfv{ 873248292Sjfv u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 874248292Sjfv s32 ret_val = E1000_SUCCESS; 875248292Sjfv 876248292Sjfv if (link && (E1000_READ_REG(hw, E1000_STATUS) & 877248292Sjfv E1000_STATUS_SPEED_1000)) { 878248292Sjfv u16 kmrn_reg; 879248292Sjfv 880248292Sjfv ret_val = hw->phy.ops.acquire(hw); 881248292Sjfv if (ret_val) 882248292Sjfv return ret_val; 883248292Sjfv 884248292Sjfv ret_val = 885248292Sjfv e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 886248292Sjfv &kmrn_reg); 887248292Sjfv if (ret_val) 888248292Sjfv goto release; 889248292Sjfv 890248292Sjfv ret_val = 891248292Sjfv e1000_write_kmrn_reg_locked(hw, 892248292Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 893248292Sjfv kmrn_reg & 894248292Sjfv ~E1000_KMRNCTRLSTA_K1_ENABLE); 895248292Sjfv if (ret_val) 896248292Sjfv goto release; 897248292Sjfv 898248292Sjfv usec_delay(10); 899248292Sjfv 900248292Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, 901248292Sjfv fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 902248292Sjfv 903248292Sjfv ret_val = 904248292Sjfv e1000_write_kmrn_reg_locked(hw, 905248292Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 906248292Sjfv kmrn_reg); 907248292Sjfvrelease: 908248292Sjfv hw->phy.ops.release(hw); 909248292Sjfv } else { 910248292Sjfv /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 911248292Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, 912248292Sjfv fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 913248292Sjfv } 914248292Sjfv 915248292Sjfv return ret_val; 916248292Sjfv} 917248292Sjfv 918248292Sjfvstatic u64 e1000_ltr2ns(u16 ltr) 919248292Sjfv{ 920248292Sjfv u32 value, scale; 921248292Sjfv 922248292Sjfv /* Determine the latency in nsec based on the LTR value & scale */ 923248292Sjfv value = ltr & E1000_LTRV_VALUE_MASK; 924248292Sjfv scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; 925248292Sjfv 926248292Sjfv return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); 927248292Sjfv} 928248292Sjfv 929248292Sjfv/** 930248292Sjfv * e1000_platform_pm_pch_lpt - Set platform power management values 931248292Sjfv * @hw: pointer to the HW structure 932248292Sjfv * @link: bool indicating link status 933248292Sjfv * 934248292Sjfv * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 935248292Sjfv * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 936248292Sjfv * when link is up (which must not exceed the maximum latency supported 937248292Sjfv * by the platform), otherwise specify there is no LTR requirement. 938248292Sjfv * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop 939248292Sjfv * latencies in the LTR Extended Capability Structure in the PCIe Extended 940248292Sjfv * Capability register set, on this device LTR is set by writing the 941248292Sjfv * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 942248292Sjfv * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 943248292Sjfv * message to the PMC. 944248292Sjfv * 945248292Sjfv * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) 946248292Sjfv * high-water mark. 947248292Sjfv **/ 948248292Sjfvstatic s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 949248292Sjfv{ 950248292Sjfv u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 951248292Sjfv link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 952248292Sjfv u16 lat_enc = 0; /* latency encoded */ 953248292Sjfv s32 obff_hwm = 0; 954248292Sjfv 955248292Sjfv DEBUGFUNC("e1000_platform_pm_pch_lpt"); 956248292Sjfv 957248292Sjfv if (link) { 958248292Sjfv u16 speed, duplex, scale = 0; 959248292Sjfv u16 max_snoop, max_nosnoop; 960248292Sjfv u16 max_ltr_enc; /* max LTR latency encoded */ 961248292Sjfv s64 lat_ns; /* latency (ns) */ 962248292Sjfv s64 value; 963248292Sjfv u32 rxa; 964248292Sjfv 965248292Sjfv if (!hw->mac.max_frame_size) { 966248292Sjfv DEBUGOUT("max_frame_size not set.\n"); 967248292Sjfv return -E1000_ERR_CONFIG; 968248292Sjfv } 969248292Sjfv 970248292Sjfv hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 971248292Sjfv if (!speed) { 972248292Sjfv DEBUGOUT("Speed not set.\n"); 973248292Sjfv return -E1000_ERR_CONFIG; 974248292Sjfv } 975248292Sjfv 976248292Sjfv /* Rx Packet Buffer Allocation size (KB) */ 977248292Sjfv rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; 978248292Sjfv 979248292Sjfv /* Determine the maximum latency tolerated by the device. 980248292Sjfv * 981248292Sjfv * Per the PCIe spec, the tolerated latencies are encoded as 982248292Sjfv * a 3-bit encoded scale (only 0-5 are valid) multiplied by 983248292Sjfv * a 10-bit value (0-1023) to provide a range from 1 ns to 984248292Sjfv * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 985248292Sjfv * 1=2^5ns, 2=2^10ns,...5=2^25ns. 986248292Sjfv */ 987248292Sjfv lat_ns = ((s64)rxa * 1024 - 988248292Sjfv (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; 989248292Sjfv if (lat_ns < 0) 990248292Sjfv lat_ns = 0; 991248292Sjfv else 992248292Sjfv lat_ns /= speed; 993248292Sjfv 994248292Sjfv value = lat_ns; 995248292Sjfv while (value > E1000_LTRV_VALUE_MASK) { 996248292Sjfv scale++; 997248292Sjfv value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); 998248292Sjfv } 999248292Sjfv if (scale > E1000_LTRV_SCALE_MAX) { 1000248292Sjfv DEBUGOUT1("Invalid LTR latency scale %d\n", scale); 1001248292Sjfv return -E1000_ERR_CONFIG; 1002248292Sjfv } 1003248292Sjfv lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); 1004248292Sjfv 1005248292Sjfv /* Determine the maximum latency tolerated by the platform */ 1006248292Sjfv e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); 1007248292Sjfv e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1008248292Sjfv max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); 1009248292Sjfv 1010248292Sjfv if (lat_enc > max_ltr_enc) { 1011248292Sjfv lat_enc = max_ltr_enc; 1012248292Sjfv lat_ns = e1000_ltr2ns(max_ltr_enc); 1013248292Sjfv } 1014248292Sjfv 1015248292Sjfv if (lat_ns) { 1016248292Sjfv lat_ns *= speed * 1000; 1017248292Sjfv lat_ns /= 8; 1018248292Sjfv lat_ns /= 1000000000; 1019248292Sjfv obff_hwm = (s32)(rxa - lat_ns); 1020248292Sjfv } 1021248292Sjfv 1022248292Sjfv if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { 1023248292Sjfv DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); 1024248292Sjfv return -E1000_ERR_CONFIG; 1025248292Sjfv } 1026248292Sjfv } 1027248292Sjfv 1028248292Sjfv /* Set Snoop and No-Snoop latencies the same */ 1029248292Sjfv reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1030248292Sjfv E1000_WRITE_REG(hw, E1000_LTRV, reg); 1031248292Sjfv 1032248292Sjfv /* Set OBFF high water mark */ 1033248292Sjfv reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; 1034248292Sjfv reg |= obff_hwm; 1035248292Sjfv E1000_WRITE_REG(hw, E1000_SVT, reg); 1036248292Sjfv 1037248292Sjfv /* Enable OBFF */ 1038248292Sjfv reg = E1000_READ_REG(hw, E1000_SVCR); 1039248292Sjfv reg |= E1000_SVCR_OFF_EN; 1040248292Sjfv /* Always unblock interrupts to the CPU even when the system is 1041248292Sjfv * in OBFF mode. This ensures that small round-robin traffic 1042248292Sjfv * (like ping) does not get dropped or experience long latency. 1043248292Sjfv */ 1044248292Sjfv reg |= E1000_SVCR_OFF_MASKINT; 1045248292Sjfv E1000_WRITE_REG(hw, E1000_SVCR, reg); 1046248292Sjfv 1047248292Sjfv return E1000_SUCCESS; 1048248292Sjfv} 1049248292Sjfv 1050248292Sjfv/** 1051248292Sjfv * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer 1052248292Sjfv * @hw: pointer to the HW structure 1053248292Sjfv * @itr: interrupt throttling rate 1054248292Sjfv * 1055248292Sjfv * Configure OBFF with the updated interrupt rate. 1056248292Sjfv **/ 1057248292Sjfvstatic s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) 1058248292Sjfv{ 1059248292Sjfv u32 svcr; 1060248292Sjfv s32 timer; 1061248292Sjfv 1062248292Sjfv DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); 1063248292Sjfv 1064248292Sjfv /* Convert ITR value into microseconds for OBFF timer */ 1065248292Sjfv timer = itr & E1000_ITR_MASK; 1066248292Sjfv timer = (timer * E1000_ITR_MULT) / 1000; 1067248292Sjfv 1068248292Sjfv if ((timer < 0) || (timer > E1000_ITR_MASK)) { 1069248292Sjfv DEBUGOUT1("Invalid OBFF timer %d\n", timer); 1070248292Sjfv return -E1000_ERR_CONFIG; 1071248292Sjfv } 1072248292Sjfv 1073248292Sjfv svcr = E1000_READ_REG(hw, E1000_SVCR); 1074248292Sjfv svcr &= ~E1000_SVCR_OFF_TIMER_MASK; 1075248292Sjfv svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; 1076248292Sjfv E1000_WRITE_REG(hw, E1000_SVCR, svcr); 1077248292Sjfv 1078248292Sjfv return E1000_SUCCESS; 1079248292Sjfv} 1080248292Sjfv 1081248292Sjfv/** 1082200243Sjfv * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1083200243Sjfv * @hw: pointer to the HW structure 1084200243Sjfv * 1085200243Sjfv * Checks to see of the link status of the hardware has changed. If a 1086200243Sjfv * change in link status has been detected, then we read the PHY registers 1087200243Sjfv * to get the current speed/duplex if link exists. 1088200243Sjfv **/ 1089200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1090200243Sjfv{ 1091200243Sjfv struct e1000_mac_info *mac = &hw->mac; 1092200243Sjfv s32 ret_val; 1093200243Sjfv bool link; 1094235527Sjfv u16 phy_reg; 1095200243Sjfv 1096200243Sjfv DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 1097200243Sjfv 1098248292Sjfv /* We only want to go out to the PHY registers to see if Auto-Neg 1099200243Sjfv * has completed and/or if our link status has changed. The 1100200243Sjfv * get_link_status flag is set upon receiving a Link Status 1101200243Sjfv * Change or Rx Sequence Error interrupt. 1102200243Sjfv */ 1103248292Sjfv if (!mac->get_link_status) 1104248292Sjfv return E1000_SUCCESS; 1105200243Sjfv 1106248292Sjfv /* First we want to see if the MII Status Register reports 1107200243Sjfv * link. If so, then we want to get the current speed/duplex 1108200243Sjfv * of the PHY. 1109200243Sjfv */ 1110200243Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1111200243Sjfv if (ret_val) 1112248292Sjfv return ret_val; 1113200243Sjfv 1114200243Sjfv if (hw->mac.type == e1000_pchlan) { 1115200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, link); 1116200243Sjfv if (ret_val) 1117248292Sjfv return ret_val; 1118200243Sjfv } 1119200243Sjfv 1120248292Sjfv /* When connected at 10Mbps half-duplex, 82579 parts are excessively 1121248292Sjfv * aggressive resulting in many collisions. To avoid this, increase 1122248292Sjfv * the IPG and reduce Rx latency in the PHY. 1123248292Sjfv */ 1124248292Sjfv if ((hw->mac.type == e1000_pch2lan) && link) { 1125248292Sjfv u32 reg; 1126248292Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 1127248292Sjfv if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { 1128248292Sjfv reg = E1000_READ_REG(hw, E1000_TIPG); 1129248292Sjfv reg &= ~E1000_TIPG_IPGT_MASK; 1130248292Sjfv reg |= 0xFF; 1131248292Sjfv E1000_WRITE_REG(hw, E1000_TIPG, reg); 1132248292Sjfv 1133248292Sjfv /* Reduce Rx latency in analog PHY */ 1134248292Sjfv ret_val = hw->phy.ops.acquire(hw); 1135248292Sjfv if (ret_val) 1136248292Sjfv return ret_val; 1137248292Sjfv 1138248292Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0); 1139248292Sjfv 1140248292Sjfv hw->phy.ops.release(hw); 1141248292Sjfv 1142248292Sjfv if (ret_val) 1143248292Sjfv return ret_val; 1144248292Sjfv } 1145248292Sjfv } 1146248292Sjfv 1147248292Sjfv /* Work-around I218 hang issue */ 1148248292Sjfv if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1149248292Sjfv (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { 1150248292Sjfv ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1151248292Sjfv if (ret_val) 1152248292Sjfv return ret_val; 1153248292Sjfv } 1154248292Sjfv 1155235527Sjfv if (hw->mac.type == e1000_pch_lpt) { 1156248292Sjfv /* Set platform power management values for Latency Tolerance 1157248292Sjfv * Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF). 1158248292Sjfv */ 1159248292Sjfv ret_val = e1000_platform_pm_pch_lpt(hw, link); 1160248292Sjfv if (ret_val) 1161248292Sjfv return ret_val; 1162235527Sjfv } 1163235527Sjfv 1164248292Sjfv /* Clear link partner's EEE ability */ 1165248292Sjfv hw->dev_spec.ich8lan.eee_lp_ability = 0; 1166248292Sjfv 1167200243Sjfv if (!link) 1168248292Sjfv return E1000_SUCCESS; /* No link detected */ 1169200243Sjfv 1170200243Sjfv mac->get_link_status = FALSE; 1171200243Sjfv 1172235527Sjfv switch (hw->mac.type) { 1173235527Sjfv case e1000_pch2lan: 1174235527Sjfv ret_val = e1000_k1_workaround_lv(hw); 1175200243Sjfv if (ret_val) 1176248292Sjfv return ret_val; 1177235527Sjfv /* fall-thru */ 1178235527Sjfv case e1000_pchlan: 1179235527Sjfv if (hw->phy.type == e1000_phy_82578) { 1180235527Sjfv ret_val = e1000_link_stall_workaround_hv(hw); 1181235527Sjfv if (ret_val) 1182248292Sjfv return ret_val; 1183235527Sjfv } 1184200243Sjfv 1185248292Sjfv /* Workaround for PCHx parts in half-duplex: 1186235527Sjfv * Set the number of preambles removed from the packet 1187235527Sjfv * when it is passed from the PHY to the MAC to prevent 1188235527Sjfv * the MAC from misinterpreting the packet type. 1189235527Sjfv */ 1190235527Sjfv hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1191235527Sjfv phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1192235527Sjfv 1193235527Sjfv if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != 1194235527Sjfv E1000_STATUS_FD) 1195235527Sjfv phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1196235527Sjfv 1197235527Sjfv hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1198235527Sjfv break; 1199235527Sjfv default: 1200235527Sjfv break; 1201213234Sjfv } 1202213234Sjfv 1203248292Sjfv /* Check if there was DownShift, must be checked 1204200243Sjfv * immediately after link-up 1205200243Sjfv */ 1206200243Sjfv e1000_check_downshift_generic(hw); 1207200243Sjfv 1208213234Sjfv /* Enable/Disable EEE after link up */ 1209213234Sjfv ret_val = e1000_set_eee_pchlan(hw); 1210213234Sjfv if (ret_val) 1211248292Sjfv return ret_val; 1212213234Sjfv 1213248292Sjfv /* If we are forcing speed/duplex, then we simply return since 1214200243Sjfv * we have already determined whether we have link or not. 1215200243Sjfv */ 1216248292Sjfv if (!mac->autoneg) 1217248292Sjfv return -E1000_ERR_CONFIG; 1218200243Sjfv 1219248292Sjfv /* Auto-Neg is enabled. Auto Speed Detection takes care 1220200243Sjfv * of MAC speed/duplex configuration. So we only need to 1221200243Sjfv * configure Collision Distance in the MAC. 1222200243Sjfv */ 1223248292Sjfv mac->ops.config_collision_dist(hw); 1224200243Sjfv 1225248292Sjfv /* Configure Flow Control now that Auto-Neg has completed. 1226200243Sjfv * First, we need to restore the desired flow control 1227200243Sjfv * settings because we may have had to re-autoneg with a 1228200243Sjfv * different link partner. 1229200243Sjfv */ 1230200243Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1231200243Sjfv if (ret_val) 1232200243Sjfv DEBUGOUT("Error configuring flow control\n"); 1233200243Sjfv 1234200243Sjfv return ret_val; 1235200243Sjfv} 1236200243Sjfv 1237200243Sjfv/** 1238169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 1239169589Sjfv * @hw: pointer to the HW structure 1240169240Sjfv * 1241169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 1242169240Sjfv **/ 1243173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 1244169240Sjfv{ 1245169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 1246169240Sjfv 1247177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 1248177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 1249194865Sjfv switch (hw->mac.type) { 1250194865Sjfv case e1000_ich8lan: 1251194865Sjfv case e1000_ich9lan: 1252194865Sjfv case e1000_ich10lan: 1253194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 1254194865Sjfv break; 1255194865Sjfv case e1000_pchlan: 1256213234Sjfv case e1000_pch2lan: 1257248292Sjfv case e1000_pch_lpt: 1258194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 1259194865Sjfv break; 1260194865Sjfv default: 1261194865Sjfv break; 1262194865Sjfv } 1263169240Sjfv} 1264169240Sjfv 1265169240Sjfv/** 1266200243Sjfv * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1267200243Sjfv * @hw: pointer to the HW structure 1268200243Sjfv * 1269200243Sjfv * Acquires the mutex for performing NVM operations. 1270200243Sjfv **/ 1271200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 1272200243Sjfv{ 1273200243Sjfv DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 1274200243Sjfv 1275200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1276200243Sjfv 1277200243Sjfv return E1000_SUCCESS; 1278200243Sjfv} 1279200243Sjfv 1280200243Sjfv/** 1281200243Sjfv * e1000_release_nvm_ich8lan - Release NVM mutex 1282200243Sjfv * @hw: pointer to the HW structure 1283200243Sjfv * 1284200243Sjfv * Releases the mutex used while performing NVM operations. 1285200243Sjfv **/ 1286200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 1287200243Sjfv{ 1288200243Sjfv DEBUGFUNC("e1000_release_nvm_ich8lan"); 1289200243Sjfv 1290200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1291200243Sjfv 1292200243Sjfv return; 1293200243Sjfv} 1294200243Sjfv 1295200243Sjfv/** 1296169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 1297169589Sjfv * @hw: pointer to the HW structure 1298169240Sjfv * 1299200243Sjfv * Acquires the software control flag for performing PHY and select 1300200243Sjfv * MAC CSR accesses. 1301169240Sjfv **/ 1302177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1303169240Sjfv{ 1304169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1305169240Sjfv s32 ret_val = E1000_SUCCESS; 1306169240Sjfv 1307169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 1308169240Sjfv 1309200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1310200243Sjfv 1311169240Sjfv while (timeout) { 1312169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1313200243Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1314200243Sjfv break; 1315169240Sjfv 1316200243Sjfv msec_delay_irq(1); 1317200243Sjfv timeout--; 1318200243Sjfv } 1319194865Sjfv 1320200243Sjfv if (!timeout) { 1321235527Sjfv DEBUGOUT("SW has already locked the resource.\n"); 1322200243Sjfv ret_val = -E1000_ERR_CONFIG; 1323200243Sjfv goto out; 1324200243Sjfv } 1325200243Sjfv 1326200243Sjfv timeout = SW_FLAG_TIMEOUT; 1327200243Sjfv 1328200243Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1329200243Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1330200243Sjfv 1331200243Sjfv while (timeout) { 1332200243Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1333200243Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1334200243Sjfv break; 1335200243Sjfv 1336169240Sjfv msec_delay_irq(1); 1337169240Sjfv timeout--; 1338169240Sjfv } 1339169240Sjfv 1340169240Sjfv if (!timeout) { 1341235527Sjfv DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1342235527Sjfv E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); 1343173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1344173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1345169240Sjfv ret_val = -E1000_ERR_CONFIG; 1346169240Sjfv goto out; 1347169240Sjfv } 1348169240Sjfv 1349169240Sjfvout: 1350200243Sjfv if (ret_val) 1351200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1352200243Sjfv 1353169240Sjfv return ret_val; 1354169240Sjfv} 1355169240Sjfv 1356169240Sjfv/** 1357169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 1358169589Sjfv * @hw: pointer to the HW structure 1359169240Sjfv * 1360200243Sjfv * Releases the software control flag for performing PHY and select 1361200243Sjfv * MAC CSR accesses. 1362169240Sjfv **/ 1363177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1364169240Sjfv{ 1365169240Sjfv u32 extcnf_ctrl; 1366169240Sjfv 1367169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 1368169240Sjfv 1369169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1370169240Sjfv 1371218588Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1372218588Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1373218588Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1374218588Sjfv } else { 1375218588Sjfv DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 1376218588Sjfv } 1377218588Sjfv 1378200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1379200243Sjfv 1380169240Sjfv return; 1381169240Sjfv} 1382169240Sjfv 1383169240Sjfv/** 1384169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 1385169589Sjfv * @hw: pointer to the HW structure 1386169240Sjfv * 1387213234Sjfv * This checks if the adapter has any manageability enabled. 1388169240Sjfv * This is a function pointer entry point only called by read/write 1389169240Sjfv * routines for the PHY and NVM parts. 1390169240Sjfv **/ 1391177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1392169240Sjfv{ 1393169240Sjfv u32 fwsm; 1394169240Sjfv 1395169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 1396169240Sjfv 1397169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1398169240Sjfv 1399213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1400213234Sjfv ((fwsm & E1000_FWSM_MODE_MASK) == 1401213234Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1402169240Sjfv} 1403169240Sjfv 1404169240Sjfv/** 1405213234Sjfv * e1000_check_mng_mode_pchlan - Checks management mode 1406213234Sjfv * @hw: pointer to the HW structure 1407213234Sjfv * 1408213234Sjfv * This checks if the adapter has iAMT enabled. 1409213234Sjfv * This is a function pointer entry point only called by read/write 1410213234Sjfv * routines for the PHY and NVM parts. 1411213234Sjfv **/ 1412213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1413213234Sjfv{ 1414213234Sjfv u32 fwsm; 1415213234Sjfv 1416213234Sjfv DEBUGFUNC("e1000_check_mng_mode_pchlan"); 1417213234Sjfv 1418213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1419213234Sjfv 1420213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1421213234Sjfv (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1422213234Sjfv} 1423213234Sjfv 1424213234Sjfv/** 1425213234Sjfv * e1000_rar_set_pch2lan - Set receive address register 1426213234Sjfv * @hw: pointer to the HW structure 1427213234Sjfv * @addr: pointer to the receive address 1428213234Sjfv * @index: receive address array register 1429213234Sjfv * 1430213234Sjfv * Sets the receive address array register at index to the address passed 1431213234Sjfv * in by addr. For 82579, RAR[0] is the base address register that is to 1432213234Sjfv * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1433213234Sjfv * Use SHRA[0-3] in place of those reserved for ME. 1434213234Sjfv **/ 1435213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1436213234Sjfv{ 1437213234Sjfv u32 rar_low, rar_high; 1438213234Sjfv 1439213234Sjfv DEBUGFUNC("e1000_rar_set_pch2lan"); 1440213234Sjfv 1441248292Sjfv /* HW expects these in little endian so we reverse the byte order 1442213234Sjfv * from network order (big endian) to little endian 1443213234Sjfv */ 1444213234Sjfv rar_low = ((u32) addr[0] | 1445235527Sjfv ((u32) addr[1] << 8) | 1446235527Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 1447213234Sjfv 1448213234Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 1449213234Sjfv 1450213234Sjfv /* If MAC address zero, no need to set the AV bit */ 1451213234Sjfv if (rar_low || rar_high) 1452213234Sjfv rar_high |= E1000_RAH_AV; 1453213234Sjfv 1454213234Sjfv if (index == 0) { 1455213234Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 1456213234Sjfv E1000_WRITE_FLUSH(hw); 1457213234Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 1458213234Sjfv E1000_WRITE_FLUSH(hw); 1459213234Sjfv return; 1460213234Sjfv } 1461213234Sjfv 1462213234Sjfv if (index < hw->mac.rar_entry_count) { 1463248292Sjfv s32 ret_val; 1464248292Sjfv 1465248292Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 1466248292Sjfv if (ret_val) 1467248292Sjfv goto out; 1468248292Sjfv 1469213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 1470213234Sjfv E1000_WRITE_FLUSH(hw); 1471213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 1472213234Sjfv E1000_WRITE_FLUSH(hw); 1473213234Sjfv 1474248292Sjfv e1000_release_swflag_ich8lan(hw); 1475248292Sjfv 1476213234Sjfv /* verify the register updates */ 1477213234Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 1478213234Sjfv (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 1479213234Sjfv return; 1480213234Sjfv 1481213234Sjfv DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1482213234Sjfv (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 1483213234Sjfv } 1484213234Sjfv 1485248292Sjfvout: 1486213234Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 1487213234Sjfv} 1488213234Sjfv 1489213234Sjfv/** 1490248292Sjfv * e1000_rar_set_pch_lpt - Set receive address registers 1491248292Sjfv * @hw: pointer to the HW structure 1492248292Sjfv * @addr: pointer to the receive address 1493248292Sjfv * @index: receive address array register 1494248292Sjfv * 1495248292Sjfv * Sets the receive address register array at index to the address passed 1496248292Sjfv * in by addr. For LPT, RAR[0] is the base address register that is to 1497248292Sjfv * contain the MAC address. SHRA[0-10] are the shared receive address 1498248292Sjfv * registers that are shared between the Host and manageability engine (ME). 1499248292Sjfv **/ 1500248292Sjfvstatic void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1501248292Sjfv{ 1502248292Sjfv u32 rar_low, rar_high; 1503248292Sjfv u32 wlock_mac; 1504248292Sjfv 1505248292Sjfv DEBUGFUNC("e1000_rar_set_pch_lpt"); 1506248292Sjfv 1507248292Sjfv /* HW expects these in little endian so we reverse the byte order 1508248292Sjfv * from network order (big endian) to little endian 1509248292Sjfv */ 1510248292Sjfv rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 1511248292Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 1512248292Sjfv 1513248292Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 1514248292Sjfv 1515248292Sjfv /* If MAC address zero, no need to set the AV bit */ 1516248292Sjfv if (rar_low || rar_high) 1517248292Sjfv rar_high |= E1000_RAH_AV; 1518248292Sjfv 1519248292Sjfv if (index == 0) { 1520248292Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 1521248292Sjfv E1000_WRITE_FLUSH(hw); 1522248292Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 1523248292Sjfv E1000_WRITE_FLUSH(hw); 1524248292Sjfv return; 1525248292Sjfv } 1526248292Sjfv 1527248292Sjfv /* The manageability engine (ME) can lock certain SHRAR registers that 1528248292Sjfv * it is using - those registers are unavailable for use. 1529248292Sjfv */ 1530248292Sjfv if (index < hw->mac.rar_entry_count) { 1531248292Sjfv wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & 1532248292Sjfv E1000_FWSM_WLOCK_MAC_MASK; 1533248292Sjfv wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1534248292Sjfv 1535248292Sjfv /* Check if all SHRAR registers are locked */ 1536248292Sjfv if (wlock_mac == 1) 1537248292Sjfv goto out; 1538248292Sjfv 1539248292Sjfv if ((wlock_mac == 0) || (index <= wlock_mac)) { 1540248292Sjfv s32 ret_val; 1541248292Sjfv 1542248292Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 1543248292Sjfv 1544248292Sjfv if (ret_val) 1545248292Sjfv goto out; 1546248292Sjfv 1547248292Sjfv E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), 1548248292Sjfv rar_low); 1549248292Sjfv E1000_WRITE_FLUSH(hw); 1550248292Sjfv E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), 1551248292Sjfv rar_high); 1552248292Sjfv E1000_WRITE_FLUSH(hw); 1553248292Sjfv 1554248292Sjfv e1000_release_swflag_ich8lan(hw); 1555248292Sjfv 1556248292Sjfv /* verify the register updates */ 1557248292Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && 1558248292Sjfv (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) 1559248292Sjfv return; 1560248292Sjfv } 1561248292Sjfv } 1562248292Sjfv 1563248292Sjfvout: 1564248292Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 1565248292Sjfv} 1566248292Sjfv 1567248292Sjfv/** 1568218588Sjfv * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 1569218588Sjfv * @hw: pointer to the HW structure 1570218588Sjfv * @mc_addr_list: array of multicast addresses to program 1571218588Sjfv * @mc_addr_count: number of multicast addresses to program 1572218588Sjfv * 1573218588Sjfv * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 1574218588Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 1575218588Sjfv **/ 1576218588Sjfvstatic void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 1577235527Sjfv u8 *mc_addr_list, 1578235527Sjfv u32 mc_addr_count) 1579218588Sjfv{ 1580235527Sjfv u16 phy_reg = 0; 1581218588Sjfv int i; 1582235527Sjfv s32 ret_val; 1583218588Sjfv 1584218588Sjfv DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 1585218588Sjfv 1586218588Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 1587218588Sjfv 1588235527Sjfv ret_val = hw->phy.ops.acquire(hw); 1589235527Sjfv if (ret_val) 1590235527Sjfv return; 1591235527Sjfv 1592235527Sjfv ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1593235527Sjfv if (ret_val) 1594235527Sjfv goto release; 1595235527Sjfv 1596218588Sjfv for (i = 0; i < hw->mac.mta_reg_count; i++) { 1597235527Sjfv hw->phy.ops.write_reg_page(hw, BM_MTA(i), 1598235527Sjfv (u16)(hw->mac.mta_shadow[i] & 1599235527Sjfv 0xFFFF)); 1600235527Sjfv hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), 1601235527Sjfv (u16)((hw->mac.mta_shadow[i] >> 16) & 1602235527Sjfv 0xFFFF)); 1603218588Sjfv } 1604235527Sjfv 1605235527Sjfv e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1606235527Sjfv 1607235527Sjfvrelease: 1608235527Sjfv hw->phy.ops.release(hw); 1609218588Sjfv} 1610218588Sjfv 1611218588Sjfv/** 1612169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 1613169589Sjfv * @hw: pointer to the HW structure 1614169240Sjfv * 1615169240Sjfv * Checks if firmware is blocking the reset of the PHY. 1616169240Sjfv * This is a function pointer entry point only called by 1617169240Sjfv * reset routines. 1618169240Sjfv **/ 1619177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 1620169240Sjfv{ 1621169240Sjfv u32 fwsm; 1622169240Sjfv 1623169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 1624169240Sjfv 1625169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 1626169240Sjfv 1627169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 1628235527Sjfv : E1000_BLK_PHY_RESET; 1629169240Sjfv} 1630169240Sjfv 1631169240Sjfv/** 1632213234Sjfv * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 1633213234Sjfv * @hw: pointer to the HW structure 1634213234Sjfv * 1635213234Sjfv * Assumes semaphore already acquired. 1636213234Sjfv * 1637213234Sjfv **/ 1638213234Sjfvstatic s32 e1000_write_smbus_addr(struct e1000_hw *hw) 1639213234Sjfv{ 1640213234Sjfv u16 phy_data; 1641213234Sjfv u32 strap = E1000_READ_REG(hw, E1000_STRAP); 1642248292Sjfv u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 1643248292Sjfv E1000_STRAP_SMT_FREQ_SHIFT; 1644248292Sjfv s32 ret_val; 1645213234Sjfv 1646213234Sjfv strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 1647213234Sjfv 1648213234Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1649213234Sjfv if (ret_val) 1650248292Sjfv return ret_val; 1651213234Sjfv 1652213234Sjfv phy_data &= ~HV_SMB_ADDR_MASK; 1653213234Sjfv phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1654213234Sjfv phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1655213234Sjfv 1656248292Sjfv if (hw->phy.type == e1000_phy_i217) { 1657248292Sjfv /* Restore SMBus frequency */ 1658248292Sjfv if (freq--) { 1659248292Sjfv phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 1660248292Sjfv phy_data |= (freq & (1 << 0)) << 1661248292Sjfv HV_SMB_ADDR_FREQ_LOW_SHIFT; 1662248292Sjfv phy_data |= (freq & (1 << 1)) << 1663248292Sjfv (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 1664248292Sjfv } else { 1665248292Sjfv DEBUGOUT("Unsupported SMB frequency in PHY\n"); 1666248292Sjfv } 1667248292Sjfv } 1668248292Sjfv 1669248292Sjfv return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 1670213234Sjfv} 1671213234Sjfv 1672213234Sjfv/** 1673200243Sjfv * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 1674200243Sjfv * @hw: pointer to the HW structure 1675200243Sjfv * 1676200243Sjfv * SW should configure the LCD from the NVM extended configuration region 1677200243Sjfv * as a workaround for certain parts. 1678200243Sjfv **/ 1679200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1680200243Sjfv{ 1681200243Sjfv struct e1000_phy_info *phy = &hw->phy; 1682200243Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1683203049Sjfv s32 ret_val = E1000_SUCCESS; 1684200243Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 1685200243Sjfv 1686213234Sjfv DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 1687203049Sjfv 1688248292Sjfv /* Initialize the PHY from the NVM on ICH platforms. This 1689200243Sjfv * is needed due to an issue where the NVM configuration is 1690200243Sjfv * not properly autoloaded after power transitions. 1691200243Sjfv * Therefore, after each PHY reset, we will load the 1692200243Sjfv * configuration data out of the NVM manually. 1693200243Sjfv */ 1694213234Sjfv switch (hw->mac.type) { 1695213234Sjfv case e1000_ich8lan: 1696213234Sjfv if (phy->type != e1000_phy_igp_3) 1697213234Sjfv return ret_val; 1698213234Sjfv 1699213234Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 1700213234Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 1701213234Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1702213234Sjfv break; 1703213234Sjfv } 1704213234Sjfv /* Fall-thru */ 1705213234Sjfv case e1000_pchlan: 1706213234Sjfv case e1000_pch2lan: 1707248292Sjfv case e1000_pch_lpt: 1708203049Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1709213234Sjfv break; 1710213234Sjfv default: 1711213234Sjfv return ret_val; 1712213234Sjfv } 1713200243Sjfv 1714213234Sjfv ret_val = hw->phy.ops.acquire(hw); 1715213234Sjfv if (ret_val) 1716213234Sjfv return ret_val; 1717213234Sjfv 1718203049Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 1719203049Sjfv if (!(data & sw_cfg_mask)) 1720248292Sjfv goto release; 1721200243Sjfv 1722248292Sjfv /* Make sure HW does not configure LCD from PHY 1723203049Sjfv * extended configuration before SW configuration 1724203049Sjfv */ 1725203049Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1726248292Sjfv if ((hw->mac.type < e1000_pch2lan) && 1727248292Sjfv (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 1728248292Sjfv goto release; 1729203049Sjfv 1730203049Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 1731203049Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1732203049Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1733203049Sjfv if (!cnf_size) 1734248292Sjfv goto release; 1735203049Sjfv 1736203049Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1737203049Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1738203049Sjfv 1739248292Sjfv if (((hw->mac.type == e1000_pchlan) && 1740248292Sjfv !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 1741248292Sjfv (hw->mac.type > e1000_pchlan)) { 1742248292Sjfv /* HW configures the SMBus address and LEDs when the 1743203049Sjfv * OEM and LCD Write Enable bits are set in the NVM. 1744203049Sjfv * When both NVM bits are cleared, SW will configure 1745203049Sjfv * them instead. 1746200243Sjfv */ 1747213234Sjfv ret_val = e1000_write_smbus_addr(hw); 1748203049Sjfv if (ret_val) 1749248292Sjfv goto release; 1750200243Sjfv 1751203049Sjfv data = E1000_READ_REG(hw, E1000_LEDCTL); 1752203049Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1753203049Sjfv (u16)data); 1754203049Sjfv if (ret_val) 1755248292Sjfv goto release; 1756203049Sjfv } 1757200243Sjfv 1758203049Sjfv /* Configure LCD from extended configuration region. */ 1759200243Sjfv 1760203049Sjfv /* cnf_base_addr is in DWORD */ 1761203049Sjfv word_addr = (u16)(cnf_base_addr << 1); 1762200243Sjfv 1763203049Sjfv for (i = 0; i < cnf_size; i++) { 1764203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 1765203049Sjfv ®_data); 1766203049Sjfv if (ret_val) 1767248292Sjfv goto release; 1768200243Sjfv 1769203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 1770203049Sjfv 1, ®_addr); 1771203049Sjfv if (ret_val) 1772248292Sjfv goto release; 1773200243Sjfv 1774203049Sjfv /* Save off the PHY page for future writes. */ 1775203049Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1776203049Sjfv phy_page = reg_data; 1777203049Sjfv continue; 1778203049Sjfv } 1779200243Sjfv 1780203049Sjfv reg_addr &= PHY_REG_MASK; 1781203049Sjfv reg_addr |= phy_page; 1782200243Sjfv 1783203049Sjfv ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 1784203049Sjfv reg_data); 1785203049Sjfv if (ret_val) 1786248292Sjfv goto release; 1787200243Sjfv } 1788200243Sjfv 1789248292Sjfvrelease: 1790200243Sjfv hw->phy.ops.release(hw); 1791200243Sjfv return ret_val; 1792200243Sjfv} 1793200243Sjfv 1794200243Sjfv/** 1795200243Sjfv * e1000_k1_gig_workaround_hv - K1 Si workaround 1796200243Sjfv * @hw: pointer to the HW structure 1797200243Sjfv * @link: link up bool flag 1798200243Sjfv * 1799200243Sjfv * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 1800200243Sjfv * from a lower speed. This workaround disables K1 whenever link is at 1Gig 1801200243Sjfv * If link is down, the function will restore the default K1 setting located 1802200243Sjfv * in the NVM. 1803200243Sjfv **/ 1804200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1805200243Sjfv{ 1806200243Sjfv s32 ret_val = E1000_SUCCESS; 1807200243Sjfv u16 status_reg = 0; 1808200243Sjfv bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1809200243Sjfv 1810200243Sjfv DEBUGFUNC("e1000_k1_gig_workaround_hv"); 1811200243Sjfv 1812200243Sjfv if (hw->mac.type != e1000_pchlan) 1813248292Sjfv return E1000_SUCCESS; 1814200243Sjfv 1815200243Sjfv /* Wrap the whole flow with the sw flag */ 1816200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1817200243Sjfv if (ret_val) 1818248292Sjfv return ret_val; 1819200243Sjfv 1820200243Sjfv /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1821200243Sjfv if (link) { 1822200243Sjfv if (hw->phy.type == e1000_phy_82578) { 1823200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 1824235527Sjfv &status_reg); 1825200243Sjfv if (ret_val) 1826200243Sjfv goto release; 1827200243Sjfv 1828200243Sjfv status_reg &= BM_CS_STATUS_LINK_UP | 1829235527Sjfv BM_CS_STATUS_RESOLVED | 1830235527Sjfv BM_CS_STATUS_SPEED_MASK; 1831200243Sjfv 1832200243Sjfv if (status_reg == (BM_CS_STATUS_LINK_UP | 1833235527Sjfv BM_CS_STATUS_RESOLVED | 1834235527Sjfv BM_CS_STATUS_SPEED_1000)) 1835200243Sjfv k1_enable = FALSE; 1836200243Sjfv } 1837200243Sjfv 1838200243Sjfv if (hw->phy.type == e1000_phy_82577) { 1839200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 1840235527Sjfv &status_reg); 1841200243Sjfv if (ret_val) 1842200243Sjfv goto release; 1843200243Sjfv 1844200243Sjfv status_reg &= HV_M_STATUS_LINK_UP | 1845235527Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1846235527Sjfv HV_M_STATUS_SPEED_MASK; 1847200243Sjfv 1848200243Sjfv if (status_reg == (HV_M_STATUS_LINK_UP | 1849235527Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1850235527Sjfv HV_M_STATUS_SPEED_1000)) 1851200243Sjfv k1_enable = FALSE; 1852200243Sjfv } 1853200243Sjfv 1854200243Sjfv /* Link stall fix for link up */ 1855200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1856235527Sjfv 0x0100); 1857200243Sjfv if (ret_val) 1858200243Sjfv goto release; 1859200243Sjfv 1860200243Sjfv } else { 1861200243Sjfv /* Link stall fix for link down */ 1862200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1863235527Sjfv 0x4100); 1864200243Sjfv if (ret_val) 1865200243Sjfv goto release; 1866200243Sjfv } 1867200243Sjfv 1868200243Sjfv ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1869200243Sjfv 1870200243Sjfvrelease: 1871200243Sjfv hw->phy.ops.release(hw); 1872248292Sjfv 1873200243Sjfv return ret_val; 1874200243Sjfv} 1875200243Sjfv 1876200243Sjfv/** 1877200243Sjfv * e1000_configure_k1_ich8lan - Configure K1 power state 1878200243Sjfv * @hw: pointer to the HW structure 1879200243Sjfv * @enable: K1 state to configure 1880200243Sjfv * 1881200243Sjfv * Configure the K1 power state based on the provided parameter. 1882200243Sjfv * Assumes semaphore already acquired. 1883200243Sjfv * 1884200243Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1885200243Sjfv **/ 1886200243Sjfvs32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1887200243Sjfv{ 1888248292Sjfv s32 ret_val; 1889200243Sjfv u32 ctrl_reg = 0; 1890200243Sjfv u32 ctrl_ext = 0; 1891200243Sjfv u32 reg = 0; 1892200243Sjfv u16 kmrn_reg = 0; 1893200243Sjfv 1894213234Sjfv DEBUGFUNC("e1000_configure_k1_ich8lan"); 1895213234Sjfv 1896235527Sjfv ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1897235527Sjfv &kmrn_reg); 1898200243Sjfv if (ret_val) 1899248292Sjfv return ret_val; 1900200243Sjfv 1901200243Sjfv if (k1_enable) 1902200243Sjfv kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1903200243Sjfv else 1904200243Sjfv kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1905200243Sjfv 1906235527Sjfv ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1907235527Sjfv kmrn_reg); 1908200243Sjfv if (ret_val) 1909248292Sjfv return ret_val; 1910200243Sjfv 1911200243Sjfv usec_delay(20); 1912200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1913200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1914200243Sjfv 1915200243Sjfv reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1916200243Sjfv reg |= E1000_CTRL_FRCSPD; 1917200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1918200243Sjfv 1919200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1920235527Sjfv E1000_WRITE_FLUSH(hw); 1921200243Sjfv usec_delay(20); 1922200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1923200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1924235527Sjfv E1000_WRITE_FLUSH(hw); 1925200243Sjfv usec_delay(20); 1926200243Sjfv 1927248292Sjfv return E1000_SUCCESS; 1928200243Sjfv} 1929200243Sjfv 1930200243Sjfv/** 1931200243Sjfv * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1932200243Sjfv * @hw: pointer to the HW structure 1933200243Sjfv * @d0_state: boolean if entering d0 or d3 device state 1934200243Sjfv * 1935200243Sjfv * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1936200243Sjfv * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1937200243Sjfv * in NVM determines whether HW should configure LPLU and Gbe Disable. 1938200243Sjfv **/ 1939235527Sjfvstatic s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1940200243Sjfv{ 1941200243Sjfv s32 ret_val = 0; 1942200243Sjfv u32 mac_reg; 1943200243Sjfv u16 oem_reg; 1944200243Sjfv 1945213234Sjfv DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 1946213234Sjfv 1947248292Sjfv if (hw->mac.type < e1000_pchlan) 1948200243Sjfv return ret_val; 1949200243Sjfv 1950200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1951200243Sjfv if (ret_val) 1952200243Sjfv return ret_val; 1953200243Sjfv 1954248292Sjfv if (hw->mac.type == e1000_pchlan) { 1955213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1956213234Sjfv if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1957248292Sjfv goto release; 1958213234Sjfv } 1959200243Sjfv 1960200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 1961200243Sjfv if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1962248292Sjfv goto release; 1963200243Sjfv 1964200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 1965200243Sjfv 1966200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1967200243Sjfv if (ret_val) 1968248292Sjfv goto release; 1969200243Sjfv 1970200243Sjfv oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1971200243Sjfv 1972200243Sjfv if (d0_state) { 1973200243Sjfv if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1974200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1975200243Sjfv 1976200243Sjfv if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1977200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1978200243Sjfv } else { 1979235527Sjfv if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 1980235527Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 1981200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1982200243Sjfv 1983235527Sjfv if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 1984235527Sjfv E1000_PHY_CTRL_NOND0A_LPLU)) 1985200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1986200243Sjfv } 1987235527Sjfv 1988248292Sjfv /* Set Restart auto-neg to activate the bits */ 1989248292Sjfv if ((d0_state || (hw->mac.type != e1000_pchlan)) && 1990248292Sjfv !hw->phy.ops.check_reset_block(hw)) 1991248292Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1992248292Sjfv 1993200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 1994200243Sjfv 1995248292Sjfvrelease: 1996200243Sjfv hw->phy.ops.release(hw); 1997200243Sjfv 1998200243Sjfv return ret_val; 1999200243Sjfv} 2000200243Sjfv 2001200243Sjfv 2002200243Sjfv/** 2003203049Sjfv * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2004203049Sjfv * @hw: pointer to the HW structure 2005203049Sjfv **/ 2006203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2007203049Sjfv{ 2008203049Sjfv s32 ret_val; 2009203049Sjfv u16 data; 2010203049Sjfv 2011213234Sjfv DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 2012213234Sjfv 2013203049Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 2014203049Sjfv if (ret_val) 2015203049Sjfv return ret_val; 2016203049Sjfv 2017203049Sjfv data |= HV_KMRN_MDIO_SLOW; 2018203049Sjfv 2019203049Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2020203049Sjfv 2021203049Sjfv return ret_val; 2022203049Sjfv} 2023203049Sjfv 2024203049Sjfv/** 2025194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2026194865Sjfv * done after every PHY reset. 2027194865Sjfv **/ 2028194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2029194865Sjfv{ 2030194865Sjfv s32 ret_val = E1000_SUCCESS; 2031203049Sjfv u16 phy_data; 2032194865Sjfv 2033213234Sjfv DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 2034213234Sjfv 2035194865Sjfv if (hw->mac.type != e1000_pchlan) 2036248292Sjfv return E1000_SUCCESS; 2037194865Sjfv 2038203049Sjfv /* Set MDIO slow mode before any other MDIO access */ 2039203049Sjfv if (hw->phy.type == e1000_phy_82577) { 2040203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 2041203049Sjfv if (ret_val) 2042248292Sjfv return ret_val; 2043203049Sjfv } 2044203049Sjfv 2045194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 2046194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2047194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2048194865Sjfv /* Disable generation of early preamble */ 2049194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2050194865Sjfv if (ret_val) 2051248292Sjfv return ret_val; 2052169240Sjfv 2053194865Sjfv /* Preamble tuning for SSC */ 2054235527Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2055235527Sjfv 0xA204); 2056194865Sjfv if (ret_val) 2057248292Sjfv return ret_val; 2058194865Sjfv } 2059169240Sjfv 2060194865Sjfv if (hw->phy.type == e1000_phy_82578) { 2061248292Sjfv /* Return registers to default by doing a soft reset then 2062194865Sjfv * writing 0x3140 to the control register. 2063194865Sjfv */ 2064194865Sjfv if (hw->phy.revision < 2) { 2065194865Sjfv e1000_phy_sw_reset_generic(hw); 2066194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 2067235527Sjfv 0x3140); 2068194865Sjfv } 2069194865Sjfv } 2070169240Sjfv 2071194865Sjfv /* Select page 0 */ 2072194865Sjfv ret_val = hw->phy.ops.acquire(hw); 2073169240Sjfv if (ret_val) 2074248292Sjfv return ret_val; 2075200243Sjfv 2076194865Sjfv hw->phy.addr = 1; 2077200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2078203049Sjfv hw->phy.ops.release(hw); 2079200243Sjfv if (ret_val) 2080248292Sjfv return ret_val; 2081169240Sjfv 2082248292Sjfv /* Configure the K1 Si workaround during phy reset assuming there is 2083200243Sjfv * link so that it disables K1 if link is in 1Gbps. 2084200243Sjfv */ 2085200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 2086203049Sjfv if (ret_val) 2087248292Sjfv return ret_val; 2088200243Sjfv 2089203049Sjfv /* Workaround for link disconnects on a busy hub in half duplex */ 2090203049Sjfv ret_val = hw->phy.ops.acquire(hw); 2091203049Sjfv if (ret_val) 2092248292Sjfv return ret_val; 2093235527Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2094203049Sjfv if (ret_val) 2095203049Sjfv goto release; 2096235527Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, 2097235527Sjfv phy_data & 0x00FF); 2098248292Sjfv if (ret_val) 2099248292Sjfv goto release; 2100248292Sjfv 2101248292Sjfv /* set MSE higher to enable link to stay up when noise is high */ 2102248292Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2103203049Sjfvrelease: 2104203049Sjfv hw->phy.ops.release(hw); 2105248292Sjfv 2106194865Sjfv return ret_val; 2107194865Sjfv} 2108169240Sjfv 2109194865Sjfv/** 2110213234Sjfv * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2111213234Sjfv * @hw: pointer to the HW structure 2112213234Sjfv **/ 2113213234Sjfvvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2114213234Sjfv{ 2115213234Sjfv u32 mac_reg; 2116235527Sjfv u16 i, phy_reg = 0; 2117235527Sjfv s32 ret_val; 2118213234Sjfv 2119213234Sjfv DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 2120213234Sjfv 2121235527Sjfv ret_val = hw->phy.ops.acquire(hw); 2122235527Sjfv if (ret_val) 2123235527Sjfv return; 2124235527Sjfv ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2125235527Sjfv if (ret_val) 2126235527Sjfv goto release; 2127235527Sjfv 2128213234Sjfv /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 2129213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 2130213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 2131235527Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2132235527Sjfv (u16)(mac_reg & 0xFFFF)); 2133235527Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2134235527Sjfv (u16)((mac_reg >> 16) & 0xFFFF)); 2135235527Sjfv 2136213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 2137235527Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2138235527Sjfv (u16)(mac_reg & 0xFFFF)); 2139235527Sjfv hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2140235527Sjfv (u16)((mac_reg & E1000_RAH_AV) 2141235527Sjfv >> 16)); 2142213234Sjfv } 2143235527Sjfv 2144235527Sjfv e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2145235527Sjfv 2146235527Sjfvrelease: 2147235527Sjfv hw->phy.ops.release(hw); 2148213234Sjfv} 2149213234Sjfv 2150213234Sjfvstatic u32 e1000_calc_rx_da_crc(u8 mac[]) 2151213234Sjfv{ 2152213234Sjfv u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 2153213234Sjfv u32 i, j, mask, crc; 2154213234Sjfv 2155213234Sjfv DEBUGFUNC("e1000_calc_rx_da_crc"); 2156213234Sjfv 2157213234Sjfv crc = 0xffffffff; 2158213234Sjfv for (i = 0; i < 6; i++) { 2159213234Sjfv crc = crc ^ mac[i]; 2160213234Sjfv for (j = 8; j > 0; j--) { 2161213234Sjfv mask = (crc & 1) * (-1); 2162213234Sjfv crc = (crc >> 1) ^ (poly & mask); 2163213234Sjfv } 2164213234Sjfv } 2165213234Sjfv return ~crc; 2166213234Sjfv} 2167213234Sjfv 2168213234Sjfv/** 2169213234Sjfv * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2170213234Sjfv * with 82579 PHY 2171213234Sjfv * @hw: pointer to the HW structure 2172213234Sjfv * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2173213234Sjfv **/ 2174213234Sjfvs32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2175213234Sjfv{ 2176213234Sjfv s32 ret_val = E1000_SUCCESS; 2177213234Sjfv u16 phy_reg, data; 2178213234Sjfv u32 mac_reg; 2179213234Sjfv u16 i; 2180213234Sjfv 2181213234Sjfv DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 2182213234Sjfv 2183248292Sjfv if (hw->mac.type < e1000_pch2lan) 2184248292Sjfv return E1000_SUCCESS; 2185213234Sjfv 2186213234Sjfv /* disable Rx path while enabling/disabling workaround */ 2187213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 2188235527Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), 2189235527Sjfv phy_reg | (1 << 14)); 2190213234Sjfv if (ret_val) 2191248292Sjfv return ret_val; 2192213234Sjfv 2193213234Sjfv if (enable) { 2194248292Sjfv /* Write Rx addresses (rar_entry_count for RAL/H, +4 for 2195213234Sjfv * SHRAL/H) and initial CRC values to the MAC 2196213234Sjfv */ 2197213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 2198213234Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 2199213234Sjfv u32 addr_high, addr_low; 2200213234Sjfv 2201213234Sjfv addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 2202213234Sjfv if (!(addr_high & E1000_RAH_AV)) 2203213234Sjfv continue; 2204213234Sjfv addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 2205213234Sjfv mac_addr[0] = (addr_low & 0xFF); 2206213234Sjfv mac_addr[1] = ((addr_low >> 8) & 0xFF); 2207213234Sjfv mac_addr[2] = ((addr_low >> 16) & 0xFF); 2208213234Sjfv mac_addr[3] = ((addr_low >> 24) & 0xFF); 2209213234Sjfv mac_addr[4] = (addr_high & 0xFF); 2210213234Sjfv mac_addr[5] = ((addr_high >> 8) & 0xFF); 2211213234Sjfv 2212213234Sjfv E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 2213213234Sjfv e1000_calc_rx_da_crc(mac_addr)); 2214213234Sjfv } 2215213234Sjfv 2216213234Sjfv /* Write Rx addresses to the PHY */ 2217213234Sjfv e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2218213234Sjfv 2219213234Sjfv /* Enable jumbo frame workaround in the MAC */ 2220213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2221213234Sjfv mac_reg &= ~(1 << 14); 2222213234Sjfv mac_reg |= (7 << 15); 2223213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2224213234Sjfv 2225213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2226213234Sjfv mac_reg |= E1000_RCTL_SECRC; 2227213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2228213234Sjfv 2229213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2230213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2231213234Sjfv &data); 2232213234Sjfv if (ret_val) 2233248292Sjfv return ret_val; 2234213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2235213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2236213234Sjfv data | (1 << 0)); 2237213234Sjfv if (ret_val) 2238248292Sjfv return ret_val; 2239213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2240213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2241213234Sjfv &data); 2242213234Sjfv if (ret_val) 2243248292Sjfv return ret_val; 2244213234Sjfv data &= ~(0xF << 8); 2245213234Sjfv data |= (0xB << 8); 2246213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2247213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2248213234Sjfv data); 2249213234Sjfv if (ret_val) 2250248292Sjfv return ret_val; 2251213234Sjfv 2252213234Sjfv /* Enable jumbo frame workaround in the PHY */ 2253213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2254213234Sjfv data &= ~(0x7F << 5); 2255213234Sjfv data |= (0x37 << 5); 2256213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2257213234Sjfv if (ret_val) 2258248292Sjfv return ret_val; 2259213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2260213234Sjfv data &= ~(1 << 13); 2261213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2262213234Sjfv if (ret_val) 2263248292Sjfv return ret_val; 2264213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2265213234Sjfv data &= ~(0x3FF << 2); 2266213234Sjfv data |= (0x1A << 2); 2267213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2268213234Sjfv if (ret_val) 2269248292Sjfv return ret_val; 2270235527Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); 2271213234Sjfv if (ret_val) 2272248292Sjfv return ret_val; 2273213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2274235527Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | 2275235527Sjfv (1 << 10)); 2276213234Sjfv if (ret_val) 2277248292Sjfv return ret_val; 2278213234Sjfv } else { 2279213234Sjfv /* Write MAC register values back to h/w defaults */ 2280213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2281213234Sjfv mac_reg &= ~(0xF << 14); 2282213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2283213234Sjfv 2284213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2285213234Sjfv mac_reg &= ~E1000_RCTL_SECRC; 2286213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2287213234Sjfv 2288213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2289213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2290213234Sjfv &data); 2291213234Sjfv if (ret_val) 2292248292Sjfv return ret_val; 2293213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2294213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 2295213234Sjfv data & ~(1 << 0)); 2296213234Sjfv if (ret_val) 2297248292Sjfv return ret_val; 2298213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 2299213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2300213234Sjfv &data); 2301213234Sjfv if (ret_val) 2302248292Sjfv return ret_val; 2303213234Sjfv data &= ~(0xF << 8); 2304213234Sjfv data |= (0xB << 8); 2305213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 2306213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 2307213234Sjfv data); 2308213234Sjfv if (ret_val) 2309248292Sjfv return ret_val; 2310213234Sjfv 2311213234Sjfv /* Write PHY register values back to h/w defaults */ 2312213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2313213234Sjfv data &= ~(0x7F << 5); 2314213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2315213234Sjfv if (ret_val) 2316248292Sjfv return ret_val; 2317213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2318213234Sjfv data |= (1 << 13); 2319213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2320213234Sjfv if (ret_val) 2321248292Sjfv return ret_val; 2322213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2323213234Sjfv data &= ~(0x3FF << 2); 2324213234Sjfv data |= (0x8 << 2); 2325213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2326213234Sjfv if (ret_val) 2327248292Sjfv return ret_val; 2328213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 2329213234Sjfv if (ret_val) 2330248292Sjfv return ret_val; 2331213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2332235527Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & 2333235527Sjfv ~(1 << 10)); 2334213234Sjfv if (ret_val) 2335248292Sjfv return ret_val; 2336213234Sjfv } 2337213234Sjfv 2338213234Sjfv /* re-enable Rx path after enabling/disabling workaround */ 2339248292Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & 2340248292Sjfv ~(1 << 14)); 2341213234Sjfv} 2342213234Sjfv 2343213234Sjfv/** 2344213234Sjfv * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2345213234Sjfv * done after every PHY reset. 2346213234Sjfv **/ 2347213234Sjfvstatic s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2348213234Sjfv{ 2349213234Sjfv s32 ret_val = E1000_SUCCESS; 2350213234Sjfv 2351213234Sjfv DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 2352213234Sjfv 2353213234Sjfv if (hw->mac.type != e1000_pch2lan) 2354248292Sjfv return E1000_SUCCESS; 2355213234Sjfv 2356213234Sjfv /* Set MDIO slow mode before any other MDIO access */ 2357213234Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 2358248292Sjfv if (ret_val) 2359248292Sjfv return ret_val; 2360213234Sjfv 2361235527Sjfv ret_val = hw->phy.ops.acquire(hw); 2362235527Sjfv if (ret_val) 2363248292Sjfv return ret_val; 2364235527Sjfv /* set MSE higher to enable link to stay up when noise is high */ 2365248292Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2366235527Sjfv if (ret_val) 2367235527Sjfv goto release; 2368235527Sjfv /* drop link after 5 times MSE threshold was reached */ 2369248292Sjfv ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2370235527Sjfvrelease: 2371235527Sjfv hw->phy.ops.release(hw); 2372235527Sjfv 2373213234Sjfv return ret_val; 2374213234Sjfv} 2375213234Sjfv 2376213234Sjfv/** 2377213234Sjfv * e1000_k1_gig_workaround_lv - K1 Si workaround 2378213234Sjfv * @hw: pointer to the HW structure 2379213234Sjfv * 2380213234Sjfv * Workaround to set the K1 beacon duration for 82579 parts 2381213234Sjfv **/ 2382213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2383213234Sjfv{ 2384213234Sjfv s32 ret_val = E1000_SUCCESS; 2385213234Sjfv u16 status_reg = 0; 2386213234Sjfv u32 mac_reg; 2387235527Sjfv u16 phy_reg; 2388213234Sjfv 2389213234Sjfv DEBUGFUNC("e1000_k1_workaround_lv"); 2390213234Sjfv 2391213234Sjfv if (hw->mac.type != e1000_pch2lan) 2392248292Sjfv return E1000_SUCCESS; 2393213234Sjfv 2394213234Sjfv /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 2395213234Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 2396213234Sjfv if (ret_val) 2397248292Sjfv return ret_val; 2398213234Sjfv 2399213234Sjfv if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2400213234Sjfv == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2401213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 2402213234Sjfv mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2403213234Sjfv 2404235527Sjfv ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); 2405235527Sjfv if (ret_val) 2406248292Sjfv return ret_val; 2407235527Sjfv 2408235527Sjfv if (status_reg & HV_M_STATUS_SPEED_1000) { 2409248292Sjfv u16 pm_phy_reg; 2410248292Sjfv 2411213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 2412235527Sjfv phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 2413248292Sjfv /* LV 1G Packet drop issue wa */ 2414248292Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, 2415248292Sjfv &pm_phy_reg); 2416248292Sjfv if (ret_val) 2417248292Sjfv return ret_val; 2418248292Sjfv pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; 2419248292Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, 2420248292Sjfv pm_phy_reg); 2421248292Sjfv if (ret_val) 2422248292Sjfv return ret_val; 2423235527Sjfv } else { 2424213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2425235527Sjfv phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 2426235527Sjfv } 2427213234Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 2428235527Sjfv ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); 2429213234Sjfv } 2430213234Sjfv 2431213234Sjfv return ret_val; 2432213234Sjfv} 2433213234Sjfv 2434213234Sjfv/** 2435213234Sjfv * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2436213234Sjfv * @hw: pointer to the HW structure 2437218588Sjfv * @gate: boolean set to TRUE to gate, FALSE to ungate 2438213234Sjfv * 2439213234Sjfv * Gate/ungate the automatic PHY configuration via hardware; perform 2440213234Sjfv * the configuration via software instead. 2441213234Sjfv **/ 2442213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2443213234Sjfv{ 2444213234Sjfv u32 extcnf_ctrl; 2445213234Sjfv 2446213234Sjfv DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 2447213234Sjfv 2448248292Sjfv if (hw->mac.type < e1000_pch2lan) 2449213234Sjfv return; 2450213234Sjfv 2451213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2452213234Sjfv 2453213234Sjfv if (gate) 2454213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2455213234Sjfv else 2456213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2457213234Sjfv 2458213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 2459213234Sjfv} 2460213234Sjfv 2461213234Sjfv/** 2462194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 2463194865Sjfv * @hw: pointer to the HW structure 2464194865Sjfv * 2465194865Sjfv * Check the appropriate indication the MAC has finished configuring the 2466194865Sjfv * PHY after a software reset. 2467194865Sjfv **/ 2468194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2469194865Sjfv{ 2470194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2471169240Sjfv 2472194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 2473169240Sjfv 2474194865Sjfv /* Wait for basic configuration completes before proceeding */ 2475194865Sjfv do { 2476194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 2477194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 2478194865Sjfv usec_delay(100); 2479194865Sjfv } while ((!data) && --loop); 2480169240Sjfv 2481248292Sjfv /* If basic configuration is incomplete before the above loop 2482194865Sjfv * count reaches 0, loading the configuration from NVM will 2483194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 2484194865Sjfv */ 2485194865Sjfv if (loop == 0) 2486194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 2487169240Sjfv 2488194865Sjfv /* Clear the Init Done bit for the next init event */ 2489194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 2490194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 2491194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 2492169240Sjfv} 2493169240Sjfv 2494169240Sjfv/** 2495213234Sjfv * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2496169589Sjfv * @hw: pointer to the HW structure 2497169240Sjfv **/ 2498213234Sjfvstatic s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2499169240Sjfv{ 2500200243Sjfv s32 ret_val = E1000_SUCCESS; 2501200243Sjfv u16 reg; 2502169240Sjfv 2503213234Sjfv DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 2504169240Sjfv 2505213234Sjfv if (hw->phy.ops.check_reset_block(hw)) 2506248292Sjfv return E1000_SUCCESS; 2507169240Sjfv 2508213234Sjfv /* Allow time for h/w to get to quiescent state after reset */ 2509194865Sjfv msec_delay(10); 2510194865Sjfv 2511203049Sjfv /* Perform any necessary post-reset workarounds */ 2512203049Sjfv switch (hw->mac.type) { 2513203049Sjfv case e1000_pchlan: 2514194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2515194865Sjfv if (ret_val) 2516248292Sjfv return ret_val; 2517203049Sjfv break; 2518213234Sjfv case e1000_pch2lan: 2519213234Sjfv ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2520213234Sjfv if (ret_val) 2521248292Sjfv return ret_val; 2522213234Sjfv break; 2523203049Sjfv default: 2524203049Sjfv break; 2525194865Sjfv } 2526194865Sjfv 2527235527Sjfv /* Clear the host wakeup bit after lcd reset */ 2528235527Sjfv if (hw->mac.type >= e1000_pchlan) { 2529235527Sjfv hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); 2530235527Sjfv reg &= ~BM_WUC_HOST_WU_BIT; 2531235527Sjfv hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); 2532213234Sjfv } 2533213234Sjfv 2534200243Sjfv /* Configure the LCD with the extended configuration region in NVM */ 2535200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 2536200243Sjfv if (ret_val) 2537248292Sjfv return ret_val; 2538169240Sjfv 2539200243Sjfv /* Configure the LCD with the OEM bits in NVM */ 2540203049Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 2541169240Sjfv 2542218588Sjfv if (hw->mac.type == e1000_pch2lan) { 2543218588Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 2544218588Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 2545218588Sjfv E1000_ICH_FWSM_FW_VALID)) { 2546218588Sjfv msec_delay(10); 2547218588Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 2548218588Sjfv } 2549218588Sjfv 2550218588Sjfv /* Set EEE LPI Update Timer to 200usec */ 2551218588Sjfv ret_val = hw->phy.ops.acquire(hw); 2552218588Sjfv if (ret_val) 2553248292Sjfv return ret_val; 2554248292Sjfv ret_val = e1000_write_emi_reg_locked(hw, 2555248292Sjfv I82579_LPI_UPDATE_TIMER, 2556248292Sjfv 0x1387); 2557218588Sjfv hw->phy.ops.release(hw); 2558213234Sjfv } 2559213234Sjfv 2560169240Sjfv return ret_val; 2561169240Sjfv} 2562169240Sjfv 2563169240Sjfv/** 2564213234Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2565213234Sjfv * @hw: pointer to the HW structure 2566213234Sjfv * 2567213234Sjfv * Resets the PHY 2568213234Sjfv * This is a function pointer entry point called by drivers 2569213234Sjfv * or other shared routines. 2570213234Sjfv **/ 2571213234Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2572213234Sjfv{ 2573213234Sjfv s32 ret_val = E1000_SUCCESS; 2574213234Sjfv 2575213234Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 2576213234Sjfv 2577213234Sjfv /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2578213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 2579213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 2580213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 2581213234Sjfv 2582213234Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 2583213234Sjfv if (ret_val) 2584248292Sjfv return ret_val; 2585213234Sjfv 2586248292Sjfv return e1000_post_phy_reset_ich8lan(hw); 2587213234Sjfv} 2588213234Sjfv 2589213234Sjfv/** 2590200243Sjfv * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2591169589Sjfv * @hw: pointer to the HW structure 2592200243Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2593169240Sjfv * 2594200243Sjfv * Sets the LPLU state according to the active flag. For PCH, if OEM write 2595200243Sjfv * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2596200243Sjfv * the phy speed. This function will manually set the LPLU bit and restart 2597200243Sjfv * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2598200243Sjfv * since it configures the same bit. 2599169240Sjfv **/ 2600200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2601169240Sjfv{ 2602248292Sjfv s32 ret_val; 2603200243Sjfv u16 oem_reg; 2604169240Sjfv 2605200243Sjfv DEBUGFUNC("e1000_set_lplu_state_pchlan"); 2606169240Sjfv 2607200243Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 2608169240Sjfv if (ret_val) 2609248292Sjfv return ret_val; 2610169240Sjfv 2611200243Sjfv if (active) 2612200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 2613200243Sjfv else 2614200243Sjfv oem_reg &= ~HV_OEM_BITS_LPLU; 2615169240Sjfv 2616235527Sjfv if (!hw->phy.ops.check_reset_block(hw)) 2617235527Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 2618235527Sjfv 2619248292Sjfv return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 2620169240Sjfv} 2621169240Sjfv 2622169240Sjfv/** 2623169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2624169589Sjfv * @hw: pointer to the HW structure 2625169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2626169240Sjfv * 2627169240Sjfv * Sets the LPLU D0 state according to the active flag. When 2628169240Sjfv * activating LPLU this function also disables smart speed 2629169240Sjfv * and vice versa. LPLU will not be activated unless the 2630169240Sjfv * device autonegotiation advertisement meets standards of 2631169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 2632169240Sjfv * This is a function pointer entry point only called by 2633169240Sjfv * PHY setup routines. 2634169240Sjfv **/ 2635185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2636169240Sjfv{ 2637169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2638169240Sjfv u32 phy_ctrl; 2639169240Sjfv s32 ret_val = E1000_SUCCESS; 2640169240Sjfv u16 data; 2641169240Sjfv 2642169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 2643169240Sjfv 2644173788Sjfv if (phy->type == e1000_phy_ife) 2645248292Sjfv return E1000_SUCCESS; 2646169240Sjfv 2647169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2648169240Sjfv 2649169240Sjfv if (active) { 2650169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2651169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2652169240Sjfv 2653194865Sjfv if (phy->type != e1000_phy_igp_3) 2654248292Sjfv return E1000_SUCCESS; 2655194865Sjfv 2656248292Sjfv /* Call gig speed drop workaround on LPLU before accessing 2657173788Sjfv * any PHY registers 2658173788Sjfv */ 2659194865Sjfv if (hw->mac.type == e1000_ich8lan) 2660169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2661169240Sjfv 2662169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2663177867Sjfv ret_val = phy->ops.read_reg(hw, 2664235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2665235527Sjfv &data); 2666248292Sjfv if (ret_val) 2667248292Sjfv return ret_val; 2668169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2669177867Sjfv ret_val = phy->ops.write_reg(hw, 2670235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2671235527Sjfv data); 2672169240Sjfv if (ret_val) 2673248292Sjfv return ret_val; 2674169240Sjfv } else { 2675169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2676169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2677169240Sjfv 2678194865Sjfv if (phy->type != e1000_phy_igp_3) 2679248292Sjfv return E1000_SUCCESS; 2680194865Sjfv 2681248292Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2682169240Sjfv * during Dx states where the power conservation is most 2683169240Sjfv * important. During driver activity we should enable 2684173788Sjfv * SmartSpeed, so performance is maintained. 2685173788Sjfv */ 2686169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2687177867Sjfv ret_val = phy->ops.read_reg(hw, 2688235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2689235527Sjfv &data); 2690169240Sjfv if (ret_val) 2691248292Sjfv return ret_val; 2692169240Sjfv 2693169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2694177867Sjfv ret_val = phy->ops.write_reg(hw, 2695235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2696235527Sjfv data); 2697169240Sjfv if (ret_val) 2698248292Sjfv return ret_val; 2699169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2700177867Sjfv ret_val = phy->ops.read_reg(hw, 2701235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2702235527Sjfv &data); 2703169240Sjfv if (ret_val) 2704248292Sjfv return ret_val; 2705169240Sjfv 2706169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2707177867Sjfv ret_val = phy->ops.write_reg(hw, 2708235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2709235527Sjfv data); 2710169240Sjfv if (ret_val) 2711248292Sjfv return ret_val; 2712169240Sjfv } 2713169240Sjfv } 2714169240Sjfv 2715248292Sjfv return E1000_SUCCESS; 2716169240Sjfv} 2717169240Sjfv 2718169240Sjfv/** 2719169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2720169589Sjfv * @hw: pointer to the HW structure 2721169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2722169240Sjfv * 2723169240Sjfv * Sets the LPLU D3 state according to the active flag. When 2724169240Sjfv * activating LPLU this function also disables smart speed 2725169240Sjfv * and vice versa. LPLU will not be activated unless the 2726169240Sjfv * device autonegotiation advertisement meets standards of 2727169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 2728169240Sjfv * This is a function pointer entry point only called by 2729169240Sjfv * PHY setup routines. 2730169240Sjfv **/ 2731185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2732169240Sjfv{ 2733169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2734169240Sjfv u32 phy_ctrl; 2735169240Sjfv s32 ret_val = E1000_SUCCESS; 2736169240Sjfv u16 data; 2737169240Sjfv 2738169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 2739169240Sjfv 2740169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2741169240Sjfv 2742169240Sjfv if (!active) { 2743169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2744169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2745194865Sjfv 2746194865Sjfv if (phy->type != e1000_phy_igp_3) 2747248292Sjfv return E1000_SUCCESS; 2748194865Sjfv 2749248292Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2750169240Sjfv * during Dx states where the power conservation is most 2751169240Sjfv * important. During driver activity we should enable 2752173788Sjfv * SmartSpeed, so performance is maintained. 2753173788Sjfv */ 2754169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2755177867Sjfv ret_val = phy->ops.read_reg(hw, 2756235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2757235527Sjfv &data); 2758169240Sjfv if (ret_val) 2759248292Sjfv return ret_val; 2760169240Sjfv 2761169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2762177867Sjfv ret_val = phy->ops.write_reg(hw, 2763235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2764235527Sjfv data); 2765169240Sjfv if (ret_val) 2766248292Sjfv return ret_val; 2767169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2768177867Sjfv ret_val = phy->ops.read_reg(hw, 2769235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2770235527Sjfv &data); 2771169240Sjfv if (ret_val) 2772248292Sjfv return ret_val; 2773169240Sjfv 2774169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2775177867Sjfv ret_val = phy->ops.write_reg(hw, 2776235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2777235527Sjfv data); 2778169240Sjfv if (ret_val) 2779248292Sjfv return ret_val; 2780169240Sjfv } 2781169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2782235527Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2783235527Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2784169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2785169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2786169240Sjfv 2787194865Sjfv if (phy->type != e1000_phy_igp_3) 2788248292Sjfv return E1000_SUCCESS; 2789194865Sjfv 2790248292Sjfv /* Call gig speed drop workaround on LPLU before accessing 2791173788Sjfv * any PHY registers 2792173788Sjfv */ 2793194865Sjfv if (hw->mac.type == e1000_ich8lan) 2794169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2795169240Sjfv 2796169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2797177867Sjfv ret_val = phy->ops.read_reg(hw, 2798235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2799235527Sjfv &data); 2800169240Sjfv if (ret_val) 2801248292Sjfv return ret_val; 2802169240Sjfv 2803169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2804177867Sjfv ret_val = phy->ops.write_reg(hw, 2805235527Sjfv IGP01E1000_PHY_PORT_CONFIG, 2806235527Sjfv data); 2807169240Sjfv } 2808169240Sjfv 2809169240Sjfv return ret_val; 2810169240Sjfv} 2811169240Sjfv 2812169240Sjfv/** 2813173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 2814173788Sjfv * @hw: pointer to the HW structure 2815173788Sjfv * @bank: pointer to the variable that returns the active bank 2816173788Sjfv * 2817173788Sjfv * Reads signature byte from the NVM using the flash access registers. 2818190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 2819173788Sjfv **/ 2820177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 2821173788Sjfv{ 2822190872Sjfv u32 eecd; 2823178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2824178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 2825178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 2826190872Sjfv u8 sig_byte = 0; 2827248292Sjfv s32 ret_val; 2828178523Sjfv 2829213234Sjfv DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 2830213234Sjfv 2831190872Sjfv switch (hw->mac.type) { 2832190872Sjfv case e1000_ich8lan: 2833190872Sjfv case e1000_ich9lan: 2834190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 2835190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 2836190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 2837190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 2838190872Sjfv *bank = 1; 2839190872Sjfv else 2840190872Sjfv *bank = 0; 2841190872Sjfv 2842248292Sjfv return E1000_SUCCESS; 2843190872Sjfv } 2844235527Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 2845190872Sjfv /* fall-thru */ 2846190872Sjfv default: 2847190872Sjfv /* set bank to 0 in case flash read fails */ 2848190872Sjfv *bank = 0; 2849190872Sjfv 2850190872Sjfv /* Check bank 0 */ 2851190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 2852235527Sjfv &sig_byte); 2853190872Sjfv if (ret_val) 2854248292Sjfv return ret_val; 2855190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2856200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2857178523Sjfv *bank = 0; 2858248292Sjfv return E1000_SUCCESS; 2859190872Sjfv } 2860185353Sjfv 2861190872Sjfv /* Check bank 1 */ 2862190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 2863235527Sjfv bank1_offset, 2864235527Sjfv &sig_byte); 2865190872Sjfv if (ret_val) 2866248292Sjfv return ret_val; 2867190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2868200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2869190872Sjfv *bank = 1; 2870248292Sjfv return E1000_SUCCESS; 2871178523Sjfv } 2872190872Sjfv 2873190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 2874248292Sjfv return -E1000_ERR_NVM; 2875178523Sjfv } 2876173788Sjfv} 2877173788Sjfv 2878173788Sjfv/** 2879169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2880169589Sjfv * @hw: pointer to the HW structure 2881169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 2882169589Sjfv * @words: Size of data to read in words 2883169589Sjfv * @data: Pointer to the word(s) to read at offset. 2884169240Sjfv * 2885169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 2886169240Sjfv **/ 2887177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2888235527Sjfv u16 *data) 2889169240Sjfv{ 2890169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2891185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2892169240Sjfv u32 act_offset; 2893169240Sjfv s32 ret_val = E1000_SUCCESS; 2894173788Sjfv u32 bank = 0; 2895169240Sjfv u16 i, word; 2896169240Sjfv 2897169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 2898169240Sjfv 2899169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2900169240Sjfv (words == 0)) { 2901169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 2902169240Sjfv ret_val = -E1000_ERR_NVM; 2903169240Sjfv goto out; 2904169240Sjfv } 2905169240Sjfv 2906200243Sjfv nvm->ops.acquire(hw); 2907169240Sjfv 2908173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2909200243Sjfv if (ret_val != E1000_SUCCESS) { 2910200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 2911200243Sjfv bank = 0; 2912200243Sjfv } 2913173788Sjfv 2914173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 2915169240Sjfv act_offset += offset; 2916169240Sjfv 2917200243Sjfv ret_val = E1000_SUCCESS; 2918169240Sjfv for (i = 0; i < words; i++) { 2919235527Sjfv if (dev_spec->shadow_ram[offset+i].modified) { 2920169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 2921169240Sjfv } else { 2922169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 2923235527Sjfv act_offset + i, 2924235527Sjfv &word); 2925169240Sjfv if (ret_val) 2926169240Sjfv break; 2927169240Sjfv data[i] = word; 2928169240Sjfv } 2929169240Sjfv } 2930169240Sjfv 2931177867Sjfv nvm->ops.release(hw); 2932169240Sjfv 2933169240Sjfvout: 2934190872Sjfv if (ret_val) 2935190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 2936190872Sjfv 2937169240Sjfv return ret_val; 2938169240Sjfv} 2939169240Sjfv 2940169240Sjfv/** 2941169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 2942169589Sjfv * @hw: pointer to the HW structure 2943169240Sjfv * 2944169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 2945169240Sjfv * can be started. 2946169240Sjfv **/ 2947173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2948169240Sjfv{ 2949169240Sjfv union ich8_hws_flash_status hsfsts; 2950169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2951169240Sjfv 2952169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 2953169240Sjfv 2954169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2955169240Sjfv 2956169240Sjfv /* Check if the flash descriptor is valid */ 2957248292Sjfv if (!hsfsts.hsf_status.fldesvalid) { 2958235527Sjfv DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); 2959248292Sjfv return -E1000_ERR_NVM; 2960169240Sjfv } 2961169240Sjfv 2962169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 2963169240Sjfv hsfsts.hsf_status.flcerr = 1; 2964169240Sjfv hsfsts.hsf_status.dael = 1; 2965169240Sjfv 2966169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2967169240Sjfv 2968248292Sjfv /* Either we should have a hardware SPI cycle in progress 2969169240Sjfv * bit to check against, in order to start a new cycle or 2970169240Sjfv * FDONE bit should be changed in the hardware so that it 2971176667Sjfv * is 1 after hardware reset, which can then be used as an 2972169240Sjfv * indication whether a cycle is in progress or has been 2973169240Sjfv * completed. 2974169240Sjfv */ 2975169240Sjfv 2976248292Sjfv if (!hsfsts.hsf_status.flcinprog) { 2977248292Sjfv /* There is no cycle running at present, 2978173788Sjfv * so we can start a cycle. 2979173788Sjfv * Begin by setting Flash Cycle Done. 2980173788Sjfv */ 2981169240Sjfv hsfsts.hsf_status.flcdone = 1; 2982169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2983169240Sjfv ret_val = E1000_SUCCESS; 2984169240Sjfv } else { 2985218588Sjfv s32 i; 2986218588Sjfv 2987248292Sjfv /* Otherwise poll for sometime so the current 2988173788Sjfv * cycle has a chance to end before giving up. 2989173788Sjfv */ 2990169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2991169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2992235527Sjfv ICH_FLASH_HSFSTS); 2993248292Sjfv if (!hsfsts.hsf_status.flcinprog) { 2994169240Sjfv ret_val = E1000_SUCCESS; 2995169240Sjfv break; 2996169240Sjfv } 2997169240Sjfv usec_delay(1); 2998169240Sjfv } 2999169240Sjfv if (ret_val == E1000_SUCCESS) { 3000248292Sjfv /* Successful in waiting for previous cycle to timeout, 3001173788Sjfv * now set the Flash Cycle Done. 3002173788Sjfv */ 3003169240Sjfv hsfsts.hsf_status.flcdone = 1; 3004185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3005235527Sjfv hsfsts.regval); 3006169240Sjfv } else { 3007235527Sjfv DEBUGOUT("Flash controller busy, cannot get access\n"); 3008169240Sjfv } 3009169240Sjfv } 3010169240Sjfv 3011169240Sjfv return ret_val; 3012169240Sjfv} 3013169240Sjfv 3014169240Sjfv/** 3015169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3016169589Sjfv * @hw: pointer to the HW structure 3017169589Sjfv * @timeout: maximum time to wait for completion 3018169240Sjfv * 3019169240Sjfv * This function starts a flash cycle and waits for its completion. 3020169240Sjfv **/ 3021173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3022169240Sjfv{ 3023169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3024169240Sjfv union ich8_hws_flash_status hsfsts; 3025169240Sjfv u32 i = 0; 3026169240Sjfv 3027169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 3028169240Sjfv 3029169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3030169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3031169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 3032169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3033169240Sjfv 3034169240Sjfv /* wait till FDONE bit is set to 1 */ 3035169240Sjfv do { 3036169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3037248292Sjfv if (hsfsts.hsf_status.flcdone) 3038169240Sjfv break; 3039169240Sjfv usec_delay(1); 3040169240Sjfv } while (i++ < timeout); 3041169240Sjfv 3042248292Sjfv if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3043248292Sjfv return E1000_SUCCESS; 3044169240Sjfv 3045248292Sjfv return -E1000_ERR_NVM; 3046169240Sjfv} 3047169240Sjfv 3048169240Sjfv/** 3049169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 3050169589Sjfv * @hw: pointer to the HW structure 3051169589Sjfv * @offset: offset to data location 3052169589Sjfv * @data: pointer to the location for storing the data 3053169240Sjfv * 3054169240Sjfv * Reads the flash word at offset into data. Offset is converted 3055169240Sjfv * to bytes before read. 3056169240Sjfv **/ 3057177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3058235527Sjfv u16 *data) 3059169240Sjfv{ 3060169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 3061169240Sjfv 3062248292Sjfv if (!data) 3063248292Sjfv return -E1000_ERR_NVM; 3064169240Sjfv 3065169240Sjfv /* Must convert offset into bytes. */ 3066169240Sjfv offset <<= 1; 3067169240Sjfv 3068248292Sjfv return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3069169240Sjfv} 3070169240Sjfv 3071169240Sjfv/** 3072178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 3073178523Sjfv * @hw: pointer to the HW structure 3074178523Sjfv * @offset: The offset of the byte to read. 3075178523Sjfv * @data: Pointer to a byte to store the value read. 3076178523Sjfv * 3077178523Sjfv * Reads a single byte from the NVM using the flash access registers. 3078178523Sjfv **/ 3079178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3080235527Sjfv u8 *data) 3081178523Sjfv{ 3082248292Sjfv s32 ret_val; 3083178523Sjfv u16 word = 0; 3084178523Sjfv 3085178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3086178523Sjfv if (ret_val) 3087248292Sjfv return ret_val; 3088178523Sjfv 3089178523Sjfv *data = (u8)word; 3090178523Sjfv 3091248292Sjfv return E1000_SUCCESS; 3092178523Sjfv} 3093178523Sjfv 3094178523Sjfv/** 3095169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3096169589Sjfv * @hw: pointer to the HW structure 3097169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 3098169589Sjfv * @size: Size of data to read, 1=byte 2=word 3099169589Sjfv * @data: Pointer to the word to store the value read. 3100169240Sjfv * 3101169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 3102169240Sjfv **/ 3103173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3104235527Sjfv u8 size, u16 *data) 3105169240Sjfv{ 3106169240Sjfv union ich8_hws_flash_status hsfsts; 3107169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3108169240Sjfv u32 flash_linear_addr; 3109169240Sjfv u32 flash_data = 0; 3110169240Sjfv s32 ret_val = -E1000_ERR_NVM; 3111169240Sjfv u8 count = 0; 3112169240Sjfv 3113169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3114169240Sjfv 3115173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3116248292Sjfv return -E1000_ERR_NVM; 3117169240Sjfv 3118169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3119235527Sjfv hw->nvm.flash_base_addr; 3120169240Sjfv 3121169240Sjfv do { 3122169240Sjfv usec_delay(1); 3123169240Sjfv /* Steps */ 3124169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3125169240Sjfv if (ret_val != E1000_SUCCESS) 3126169240Sjfv break; 3127169240Sjfv 3128169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3129169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3130169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 3131169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3132169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3133169240Sjfv 3134169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3135169240Sjfv 3136169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3137235527Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 3138169240Sjfv 3139248292Sjfv /* Check if FCERR is set to 1, if set to 1, clear it 3140169240Sjfv * and try the whole sequence a few more times, else 3141169240Sjfv * read in (shift in) the Flash Data0, the order is 3142173788Sjfv * least significant byte first msb to lsb 3143173788Sjfv */ 3144169240Sjfv if (ret_val == E1000_SUCCESS) { 3145169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3146185353Sjfv if (size == 1) 3147169240Sjfv *data = (u8)(flash_data & 0x000000FF); 3148185353Sjfv else if (size == 2) 3149169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 3150169240Sjfv break; 3151169240Sjfv } else { 3152248292Sjfv /* If we've gotten here, then things are probably 3153169240Sjfv * completely hosed, but if the error condition is 3154169240Sjfv * detected, it won't hurt to give it another try... 3155169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3156169240Sjfv */ 3157169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3158235527Sjfv ICH_FLASH_HSFSTS); 3159248292Sjfv if (hsfsts.hsf_status.flcerr) { 3160169240Sjfv /* Repeat for some time before giving up. */ 3161169240Sjfv continue; 3162248292Sjfv } else if (!hsfsts.hsf_status.flcdone) { 3163235527Sjfv DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3164169240Sjfv break; 3165169240Sjfv } 3166169240Sjfv } 3167169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3168169240Sjfv 3169169240Sjfv return ret_val; 3170169240Sjfv} 3171169240Sjfv 3172169240Sjfv/** 3173169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3174169589Sjfv * @hw: pointer to the HW structure 3175169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 3176169589Sjfv * @words: Size of data to write in words 3177169589Sjfv * @data: Pointer to the word(s) to write at offset. 3178169240Sjfv * 3179169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 3180169240Sjfv **/ 3181177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3182235527Sjfv u16 *data) 3183169240Sjfv{ 3184169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3185185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3186169240Sjfv u16 i; 3187169240Sjfv 3188169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 3189169240Sjfv 3190169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3191169240Sjfv (words == 0)) { 3192169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 3193248292Sjfv return -E1000_ERR_NVM; 3194169240Sjfv } 3195169240Sjfv 3196200243Sjfv nvm->ops.acquire(hw); 3197169240Sjfv 3198169240Sjfv for (i = 0; i < words; i++) { 3199169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 3200169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 3201169240Sjfv } 3202169240Sjfv 3203177867Sjfv nvm->ops.release(hw); 3204169240Sjfv 3205248292Sjfv return E1000_SUCCESS; 3206169240Sjfv} 3207169240Sjfv 3208169240Sjfv/** 3209169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3210169589Sjfv * @hw: pointer to the HW structure 3211169240Sjfv * 3212169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 3213169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 3214169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 3215169240Sjfv * checking for the modified bit and writing only the pending changes. 3216176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 3217169240Sjfv * future writes. 3218169240Sjfv **/ 3219177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3220169240Sjfv{ 3221169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3222185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3223173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3224169240Sjfv s32 ret_val; 3225169240Sjfv u16 data; 3226169240Sjfv 3227169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 3228169240Sjfv 3229169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 3230169240Sjfv if (ret_val) 3231169240Sjfv goto out; 3232169240Sjfv 3233169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 3234169240Sjfv goto out; 3235169240Sjfv 3236200243Sjfv nvm->ops.acquire(hw); 3237169240Sjfv 3238248292Sjfv /* We're writing to the opposite bank so if we're on bank 1, 3239169240Sjfv * write to bank 0 etc. We also need to erase the segment that 3240173788Sjfv * is going to be written 3241173788Sjfv */ 3242173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3243190872Sjfv if (ret_val != E1000_SUCCESS) { 3244200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3245200243Sjfv bank = 0; 3246190872Sjfv } 3247173788Sjfv 3248173788Sjfv if (bank == 0) { 3249169240Sjfv new_bank_offset = nvm->flash_bank_size; 3250169240Sjfv old_bank_offset = 0; 3251190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3252203049Sjfv if (ret_val) 3253203049Sjfv goto release; 3254169240Sjfv } else { 3255169240Sjfv old_bank_offset = nvm->flash_bank_size; 3256169240Sjfv new_bank_offset = 0; 3257190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3258203049Sjfv if (ret_val) 3259203049Sjfv goto release; 3260169240Sjfv } 3261169240Sjfv 3262169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 3263248292Sjfv /* Determine whether to write the value stored 3264169240Sjfv * in the other NVM bank or a modified value stored 3265173788Sjfv * in the shadow RAM 3266173788Sjfv */ 3267173788Sjfv if (dev_spec->shadow_ram[i].modified) { 3268169240Sjfv data = dev_spec->shadow_ram[i].value; 3269169240Sjfv } else { 3270190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 3271235527Sjfv old_bank_offset, 3272235527Sjfv &data); 3273190872Sjfv if (ret_val) 3274190872Sjfv break; 3275169240Sjfv } 3276169240Sjfv 3277248292Sjfv /* If the word is 0x13, then make sure the signature bits 3278169240Sjfv * (15:14) are 11b until the commit has completed. 3279169240Sjfv * This will allow us to write 10b which indicates the 3280169240Sjfv * signature is valid. We want to do this after the write 3281169240Sjfv * has completed so that we don't mark the segment valid 3282173788Sjfv * while the write is still in progress 3283173788Sjfv */ 3284169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 3285169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 3286169240Sjfv 3287169240Sjfv /* Convert offset to bytes. */ 3288169240Sjfv act_offset = (i + new_bank_offset) << 1; 3289169240Sjfv 3290169240Sjfv usec_delay(100); 3291169240Sjfv /* Write the bytes to the new bank. */ 3292169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3293235527Sjfv act_offset, 3294235527Sjfv (u8)data); 3295169240Sjfv if (ret_val) 3296169240Sjfv break; 3297169240Sjfv 3298169240Sjfv usec_delay(100); 3299169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3300235527Sjfv act_offset + 1, 3301235527Sjfv (u8)(data >> 8)); 3302169240Sjfv if (ret_val) 3303169240Sjfv break; 3304169240Sjfv } 3305169240Sjfv 3306248292Sjfv /* Don't bother writing the segment valid bits if sector 3307173788Sjfv * programming failed. 3308173788Sjfv */ 3309169240Sjfv if (ret_val) { 3310169240Sjfv DEBUGOUT("Flash commit failed.\n"); 3311203049Sjfv goto release; 3312169240Sjfv } 3313169240Sjfv 3314248292Sjfv /* Finally validate the new segment by setting bit 15:14 3315169240Sjfv * to 10b in word 0x13 , this can be done without an 3316169240Sjfv * erase as well since these bits are 11 to start with 3317173788Sjfv * and we need to change bit 14 to 0b 3318173788Sjfv */ 3319169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3320190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 3321203049Sjfv if (ret_val) 3322203049Sjfv goto release; 3323200243Sjfv 3324169240Sjfv data &= 0xBFFF; 3325169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3326235527Sjfv act_offset * 2 + 1, 3327235527Sjfv (u8)(data >> 8)); 3328203049Sjfv if (ret_val) 3329203049Sjfv goto release; 3330169240Sjfv 3331248292Sjfv /* And invalidate the previously valid segment by setting 3332169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 3333169240Sjfv * done without an erase because flash erase sets all bits 3334173788Sjfv * to 1's. We can write 1's to 0's without an erase 3335173788Sjfv */ 3336169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3337169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 3338203049Sjfv if (ret_val) 3339203049Sjfv goto release; 3340169240Sjfv 3341169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 3342169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 3343169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 3344169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 3345169240Sjfv } 3346169240Sjfv 3347203049Sjfvrelease: 3348177867Sjfv nvm->ops.release(hw); 3349169240Sjfv 3350248292Sjfv /* Reload the EEPROM, or else modifications will not appear 3351169240Sjfv * until after the next adapter reset. 3352169240Sjfv */ 3353203049Sjfv if (!ret_val) { 3354203049Sjfv nvm->ops.reload(hw); 3355203049Sjfv msec_delay(10); 3356203049Sjfv } 3357169240Sjfv 3358169240Sjfvout: 3359190872Sjfv if (ret_val) 3360190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 3361190872Sjfv 3362169240Sjfv return ret_val; 3363169240Sjfv} 3364169240Sjfv 3365169240Sjfv/** 3366169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 3367169589Sjfv * @hw: pointer to the HW structure 3368169240Sjfv * 3369169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 3370185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 3371185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 3372169240Sjfv **/ 3373177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 3374169240Sjfv{ 3375248292Sjfv s32 ret_val; 3376169240Sjfv u16 data; 3377248292Sjfv u16 word; 3378248292Sjfv u16 valid_csum_mask; 3379169240Sjfv 3380169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 3381169240Sjfv 3382248292Sjfv /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 3383248292Sjfv * the checksum needs to be fixed. This bit is an indication that 3384248292Sjfv * the NVM was prepared by OEM software and did not calculate 3385248292Sjfv * the checksum...a likely scenario. 3386169240Sjfv */ 3387248292Sjfv switch (hw->mac.type) { 3388248292Sjfv case e1000_pch_lpt: 3389248292Sjfv word = NVM_COMPAT; 3390248292Sjfv valid_csum_mask = NVM_COMPAT_VALID_CSUM; 3391248292Sjfv break; 3392248292Sjfv default: 3393248292Sjfv word = NVM_FUTURE_INIT_WORD1; 3394248292Sjfv valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 3395248292Sjfv break; 3396248292Sjfv } 3397248292Sjfv 3398248292Sjfv ret_val = hw->nvm.ops.read(hw, word, 1, &data); 3399169240Sjfv if (ret_val) 3400248292Sjfv return ret_val; 3401169240Sjfv 3402248292Sjfv if (!(data & valid_csum_mask)) { 3403248292Sjfv data |= valid_csum_mask; 3404248292Sjfv ret_val = hw->nvm.ops.write(hw, word, 1, &data); 3405169240Sjfv if (ret_val) 3406248292Sjfv return ret_val; 3407177867Sjfv ret_val = hw->nvm.ops.update(hw); 3408169240Sjfv if (ret_val) 3409248292Sjfv return ret_val; 3410169240Sjfv } 3411169240Sjfv 3412248292Sjfv return e1000_validate_nvm_checksum_generic(hw); 3413169240Sjfv} 3414169240Sjfv 3415169240Sjfv/** 3416169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 3417169589Sjfv * @hw: pointer to the HW structure 3418169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 3419169589Sjfv * @size: Size of data to read, 1=byte 2=word 3420169589Sjfv * @data: The byte(s) to write to the NVM. 3421169240Sjfv * 3422169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 3423169240Sjfv **/ 3424173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3425235527Sjfv u8 size, u16 data) 3426169240Sjfv{ 3427169240Sjfv union ich8_hws_flash_status hsfsts; 3428169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3429169240Sjfv u32 flash_linear_addr; 3430169240Sjfv u32 flash_data = 0; 3431248292Sjfv s32 ret_val; 3432169240Sjfv u8 count = 0; 3433169240Sjfv 3434169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 3435169240Sjfv 3436169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 3437169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 3438248292Sjfv return -E1000_ERR_NVM; 3439169240Sjfv 3440169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3441235527Sjfv hw->nvm.flash_base_addr; 3442169240Sjfv 3443169240Sjfv do { 3444169240Sjfv usec_delay(1); 3445169240Sjfv /* Steps */ 3446169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3447169240Sjfv if (ret_val != E1000_SUCCESS) 3448169240Sjfv break; 3449169240Sjfv 3450169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3451169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3452185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 3453169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 3454169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3455169240Sjfv 3456169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3457169240Sjfv 3458169240Sjfv if (size == 1) 3459169240Sjfv flash_data = (u32)data & 0x00FF; 3460169240Sjfv else 3461169240Sjfv flash_data = (u32)data; 3462169240Sjfv 3463169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 3464169240Sjfv 3465248292Sjfv /* check if FCERR is set to 1 , if set to 1, clear it 3466173788Sjfv * and try the whole sequence a few more times else done 3467173788Sjfv */ 3468169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3469235527Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 3470185353Sjfv if (ret_val == E1000_SUCCESS) 3471169240Sjfv break; 3472185353Sjfv 3473248292Sjfv /* If we're here, then things are most likely 3474185353Sjfv * completely hosed, but if the error condition 3475185353Sjfv * is detected, it won't hurt to give it another 3476185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 3477185353Sjfv */ 3478185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3479248292Sjfv if (hsfsts.hsf_status.flcerr) 3480185353Sjfv /* Repeat for some time before giving up. */ 3481185353Sjfv continue; 3482248292Sjfv if (!hsfsts.hsf_status.flcdone) { 3483235527Sjfv DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3484185353Sjfv break; 3485169240Sjfv } 3486169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3487169240Sjfv 3488169240Sjfv return ret_val; 3489169240Sjfv} 3490169240Sjfv 3491169240Sjfv/** 3492169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 3493169589Sjfv * @hw: pointer to the HW structure 3494169589Sjfv * @offset: The index of the byte to read. 3495169589Sjfv * @data: The byte to write to the NVM. 3496169240Sjfv * 3497169240Sjfv * Writes a single byte to the NVM using the flash access registers. 3498169240Sjfv **/ 3499177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3500235527Sjfv u8 data) 3501169240Sjfv{ 3502169240Sjfv u16 word = (u16)data; 3503169240Sjfv 3504169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 3505169240Sjfv 3506169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 3507169240Sjfv} 3508169240Sjfv 3509169240Sjfv/** 3510169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 3511169589Sjfv * @hw: pointer to the HW structure 3512169589Sjfv * @offset: The offset of the byte to write. 3513169589Sjfv * @byte: The byte to write to the NVM. 3514169240Sjfv * 3515169240Sjfv * Writes a single byte to the NVM using the flash access registers. 3516169240Sjfv * Goes through a retry algorithm before giving up. 3517169240Sjfv **/ 3518176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 3519235527Sjfv u32 offset, u8 byte) 3520169240Sjfv{ 3521169240Sjfv s32 ret_val; 3522169240Sjfv u16 program_retries; 3523169240Sjfv 3524169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 3525169240Sjfv 3526169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3527248292Sjfv if (!ret_val) 3528248292Sjfv return ret_val; 3529169240Sjfv 3530169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 3531169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 3532169240Sjfv usec_delay(100); 3533169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3534169240Sjfv if (ret_val == E1000_SUCCESS) 3535169240Sjfv break; 3536169240Sjfv } 3537248292Sjfv if (program_retries == 100) 3538248292Sjfv return -E1000_ERR_NVM; 3539169240Sjfv 3540248292Sjfv return E1000_SUCCESS; 3541169240Sjfv} 3542169240Sjfv 3543169240Sjfv/** 3544169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 3545169589Sjfv * @hw: pointer to the HW structure 3546169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 3547169240Sjfv * 3548169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 3549169240Sjfv * bank N is 4096 * N + flash_reg_addr. 3550169240Sjfv **/ 3551177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 3552169240Sjfv{ 3553169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 3554169240Sjfv union ich8_hws_flash_status hsfsts; 3555169240Sjfv union ich8_hws_flash_ctrl hsflctl; 3556169240Sjfv u32 flash_linear_addr; 3557173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 3558173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 3559248292Sjfv s32 ret_val; 3560185353Sjfv s32 count = 0; 3561185353Sjfv s32 j, iteration, sector_size; 3562169240Sjfv 3563169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 3564169240Sjfv 3565169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3566169240Sjfv 3567248292Sjfv /* Determine HW Sector size: Read BERASE bits of hw flash status 3568173788Sjfv * register 3569173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 3570169240Sjfv * consecutive sectors. The start index for the nth Hw sector 3571169240Sjfv * can be calculated as = bank * 4096 + n * 256 3572169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 3573169240Sjfv * The start index for the nth Hw sector can be calculated 3574169240Sjfv * as = bank * 4096 3575169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 3576169240Sjfv * (ich9 only, otherwise error condition) 3577169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 3578169240Sjfv */ 3579169240Sjfv switch (hsfsts.hsf_status.berasesz) { 3580169240Sjfv case 0: 3581169240Sjfv /* Hw sector size 256 */ 3582169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 3583169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 3584169240Sjfv break; 3585169240Sjfv case 1: 3586169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 3587194865Sjfv iteration = 1; 3588169240Sjfv break; 3589169240Sjfv case 2: 3590195850Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 3591195850Sjfv iteration = 1; 3592169240Sjfv break; 3593169240Sjfv case 3: 3594169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 3595194865Sjfv iteration = 1; 3596169240Sjfv break; 3597169240Sjfv default: 3598248292Sjfv return -E1000_ERR_NVM; 3599169240Sjfv } 3600169240Sjfv 3601169240Sjfv /* Start with the base address, then add the sector offset. */ 3602169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 3603200243Sjfv flash_linear_addr += (bank) ? flash_bank_size : 0; 3604169240Sjfv 3605169240Sjfv for (j = 0; j < iteration ; j++) { 3606169240Sjfv do { 3607169240Sjfv /* Steps */ 3608169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3609169240Sjfv if (ret_val) 3610248292Sjfv return ret_val; 3611169240Sjfv 3612248292Sjfv /* Write a value 11 (block Erase) in Flash 3613173788Sjfv * Cycle field in hw flash control 3614173788Sjfv */ 3615169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 3616235527Sjfv ICH_FLASH_HSFCTL); 3617169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3618185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 3619235527Sjfv hsflctl.regval); 3620169240Sjfv 3621248292Sjfv /* Write the last 24 bits of an index within the 3622169240Sjfv * block into Flash Linear address field in Flash 3623169240Sjfv * Address. 3624169240Sjfv */ 3625169240Sjfv flash_linear_addr += (j * sector_size); 3626185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 3627235527Sjfv flash_linear_addr); 3628169240Sjfv 3629169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3630235527Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 3631185353Sjfv if (ret_val == E1000_SUCCESS) 3632169240Sjfv break; 3633185353Sjfv 3634248292Sjfv /* Check if FCERR is set to 1. If 1, 3635185353Sjfv * clear it and try the whole sequence 3636185353Sjfv * a few more times else Done 3637185353Sjfv */ 3638185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3639185353Sjfv ICH_FLASH_HSFSTS); 3640248292Sjfv if (hsfsts.hsf_status.flcerr) 3641185353Sjfv /* repeat for some time before giving up */ 3642185353Sjfv continue; 3643248292Sjfv else if (!hsfsts.hsf_status.flcdone) 3644248292Sjfv return ret_val; 3645169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 3646169240Sjfv } 3647169240Sjfv 3648248292Sjfv return E1000_SUCCESS; 3649169240Sjfv} 3650169240Sjfv 3651169240Sjfv/** 3652169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 3653169589Sjfv * @hw: pointer to the HW structure 3654169589Sjfv * @data: Pointer to the LED settings 3655169240Sjfv * 3656169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 3657169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 3658169240Sjfv * setting. 3659169240Sjfv **/ 3660177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 3661169240Sjfv{ 3662169240Sjfv s32 ret_val; 3663169240Sjfv 3664169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 3665169240Sjfv 3666177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 3667169240Sjfv if (ret_val) { 3668169240Sjfv DEBUGOUT("NVM Read Error\n"); 3669248292Sjfv return ret_val; 3670169240Sjfv } 3671169240Sjfv 3672235527Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 3673169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 3674169240Sjfv 3675248292Sjfv return E1000_SUCCESS; 3676169240Sjfv} 3677169240Sjfv 3678169240Sjfv/** 3679194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 3680194865Sjfv * @hw: pointer to the HW structure 3681194865Sjfv * 3682194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 3683194865Sjfv * the PHY LED configuration register. 3684194865Sjfv * 3685194865Sjfv * PCH also does not have an "always on" or "always off" mode which 3686194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 3687194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 3688194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 3689194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 3690194865Sjfv **/ 3691194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 3692194865Sjfv{ 3693194865Sjfv struct e1000_mac_info *mac = &hw->mac; 3694194865Sjfv s32 ret_val; 3695194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 3696194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 3697194865Sjfv u16 data, i, temp, shift; 3698194865Sjfv 3699194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 3700194865Sjfv 3701194865Sjfv /* Get default ID LED modes */ 3702194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 3703194865Sjfv if (ret_val) 3704248292Sjfv return ret_val; 3705194865Sjfv 3706194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 3707194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 3708194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 3709194865Sjfv 3710194865Sjfv for (i = 0; i < 4; i++) { 3711194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 3712194865Sjfv shift = (i * 5); 3713194865Sjfv switch (temp) { 3714194865Sjfv case ID_LED_ON1_DEF2: 3715194865Sjfv case ID_LED_ON1_ON2: 3716194865Sjfv case ID_LED_ON1_OFF2: 3717194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3718194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 3719194865Sjfv break; 3720194865Sjfv case ID_LED_OFF1_DEF2: 3721194865Sjfv case ID_LED_OFF1_ON2: 3722194865Sjfv case ID_LED_OFF1_OFF2: 3723194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3724194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 3725194865Sjfv break; 3726194865Sjfv default: 3727194865Sjfv /* Do nothing */ 3728194865Sjfv break; 3729194865Sjfv } 3730194865Sjfv switch (temp) { 3731194865Sjfv case ID_LED_DEF1_ON2: 3732194865Sjfv case ID_LED_ON1_ON2: 3733194865Sjfv case ID_LED_OFF1_ON2: 3734194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3735194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 3736194865Sjfv break; 3737194865Sjfv case ID_LED_DEF1_OFF2: 3738194865Sjfv case ID_LED_ON1_OFF2: 3739194865Sjfv case ID_LED_OFF1_OFF2: 3740194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3741194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 3742194865Sjfv break; 3743194865Sjfv default: 3744194865Sjfv /* Do nothing */ 3745194865Sjfv break; 3746194865Sjfv } 3747194865Sjfv } 3748194865Sjfv 3749248292Sjfv return E1000_SUCCESS; 3750194865Sjfv} 3751194865Sjfv 3752194865Sjfv/** 3753169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 3754169589Sjfv * @hw: pointer to the HW structure 3755169240Sjfv * 3756169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 3757248292Sjfv * register, so the the bus width is hard coded. 3758169240Sjfv **/ 3759177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 3760169240Sjfv{ 3761169240Sjfv struct e1000_bus_info *bus = &hw->bus; 3762169240Sjfv s32 ret_val; 3763169240Sjfv 3764169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 3765169240Sjfv 3766169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 3767169240Sjfv 3768248292Sjfv /* ICH devices are "PCI Express"-ish. They have 3769169240Sjfv * a configuration space, but do not contain 3770169240Sjfv * PCI Express Capability registers, so bus width 3771169240Sjfv * must be hardcoded. 3772169240Sjfv */ 3773169240Sjfv if (bus->width == e1000_bus_width_unknown) 3774169240Sjfv bus->width = e1000_bus_width_pcie_x1; 3775169240Sjfv 3776169240Sjfv return ret_val; 3777169240Sjfv} 3778169240Sjfv 3779169240Sjfv/** 3780169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 3781169589Sjfv * @hw: pointer to the HW structure 3782169240Sjfv * 3783169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 3784169240Sjfv * MAC. 3785169240Sjfv **/ 3786177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 3787169240Sjfv{ 3788200243Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3789248292Sjfv u16 kum_cfg; 3790248292Sjfv u32 ctrl, reg; 3791169240Sjfv s32 ret_val; 3792169240Sjfv 3793169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 3794169240Sjfv 3795248292Sjfv /* Prevent the PCI-E bus from sticking if there is no TLP connection 3796169240Sjfv * on the last TLP read/write transaction when MAC is reset. 3797169240Sjfv */ 3798169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 3799185353Sjfv if (ret_val) 3800169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 3801169240Sjfv 3802169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 3803169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3804169240Sjfv 3805248292Sjfv /* Disable the Transmit and Receive units. Then delay to allow 3806169240Sjfv * any pending transactions to complete before we hit the MAC 3807169240Sjfv * with the global reset. 3808169240Sjfv */ 3809169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 3810169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 3811169240Sjfv E1000_WRITE_FLUSH(hw); 3812169240Sjfv 3813169240Sjfv msec_delay(10); 3814169240Sjfv 3815169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 3816169240Sjfv if (hw->mac.type == e1000_ich8lan) { 3817169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 3818169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 3819169240Sjfv /* Set Packet Buffer Size to 16k. */ 3820169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 3821169240Sjfv } 3822169240Sjfv 3823200243Sjfv if (hw->mac.type == e1000_pchlan) { 3824200243Sjfv /* Save the NVM K1 bit setting*/ 3825248292Sjfv ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 3826200243Sjfv if (ret_val) 3827200243Sjfv return ret_val; 3828200243Sjfv 3829248292Sjfv if (kum_cfg & E1000_NVM_K1_ENABLE) 3830200243Sjfv dev_spec->nvm_k1_enabled = TRUE; 3831200243Sjfv else 3832200243Sjfv dev_spec->nvm_k1_enabled = FALSE; 3833200243Sjfv } 3834200243Sjfv 3835169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 3836169240Sjfv 3837213234Sjfv if (!hw->phy.ops.check_reset_block(hw)) { 3838248292Sjfv /* Full-chip reset requires MAC and PHY reset at the same 3839169240Sjfv * time to make sure the interface between MAC and the 3840169240Sjfv * external PHY is reset. 3841169240Sjfv */ 3842169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 3843213234Sjfv 3844248292Sjfv /* Gate automatic PHY configuration by hardware on 3845213234Sjfv * non-managed 82579 3846213234Sjfv */ 3847213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 3848213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3849213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3850169240Sjfv } 3851169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 3852185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 3853169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 3854235527Sjfv /* cannot issue a flush here because it hangs the hardware */ 3855169240Sjfv msec_delay(20); 3856169240Sjfv 3857248292Sjfv /* Set Phy Config Counter to 50msec */ 3858248292Sjfv if (hw->mac.type == e1000_pch2lan) { 3859248292Sjfv reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 3860248292Sjfv reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 3861248292Sjfv reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 3862248292Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); 3863248292Sjfv } 3864248292Sjfv 3865194865Sjfv if (!ret_val) 3866235527Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 3867194865Sjfv 3868213234Sjfv if (ctrl & E1000_CTRL_PHY_RST) { 3869213234Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 3870203049Sjfv if (ret_val) 3871248292Sjfv return ret_val; 3872203049Sjfv 3873213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 3874213234Sjfv if (ret_val) 3875248292Sjfv return ret_val; 3876169240Sjfv } 3877169240Sjfv 3878248292Sjfv /* For PCH, this write will make sure that any noise 3879200243Sjfv * will be detected as a CRC error and be dropped rather than show up 3880200243Sjfv * as a bad packet to the DMA engine. 3881200243Sjfv */ 3882200243Sjfv if (hw->mac.type == e1000_pchlan) 3883200243Sjfv E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 3884200243Sjfv 3885169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3886218588Sjfv E1000_READ_REG(hw, E1000_ICR); 3887169240Sjfv 3888248292Sjfv reg = E1000_READ_REG(hw, E1000_KABGTXD); 3889248292Sjfv reg |= E1000_KABGTXD_BGSQLBIAS; 3890248292Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, reg); 3891169240Sjfv 3892248292Sjfv return E1000_SUCCESS; 3893169240Sjfv} 3894169240Sjfv 3895169240Sjfv/** 3896169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 3897169589Sjfv * @hw: pointer to the HW structure 3898169240Sjfv * 3899169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 3900169240Sjfv * - initialize hardware bits 3901169240Sjfv * - initialize LED identification 3902169240Sjfv * - setup receive address registers 3903169240Sjfv * - setup flow control 3904176667Sjfv * - setup transmit descriptors 3905169240Sjfv * - clear statistics 3906169240Sjfv **/ 3907177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3908169240Sjfv{ 3909169240Sjfv struct e1000_mac_info *mac = &hw->mac; 3910169240Sjfv u32 ctrl_ext, txdctl, snoop; 3911169240Sjfv s32 ret_val; 3912169240Sjfv u16 i; 3913169240Sjfv 3914169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 3915169240Sjfv 3916169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 3917169240Sjfv 3918169240Sjfv /* Initialize identification LED */ 3919190872Sjfv ret_val = mac->ops.id_led_init(hw); 3920248292Sjfv /* An error is not fatal and we should not stop init due to this */ 3921190872Sjfv if (ret_val) 3922200243Sjfv DEBUGOUT("Error initializing identification LED\n"); 3923169240Sjfv 3924169240Sjfv /* Setup the receive address. */ 3925169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 3926169240Sjfv 3927169240Sjfv /* Zero out the Multicast HASH table */ 3928169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 3929169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 3930169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3931169240Sjfv 3932248292Sjfv /* The 82578 Rx buffer will stall if wakeup is enabled in host and 3933235527Sjfv * the ME. Disable wakeup by clearing the host wakeup bit. 3934194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 3935194865Sjfv */ 3936194865Sjfv if (hw->phy.type == e1000_phy_82578) { 3937235527Sjfv hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); 3938235527Sjfv i &= ~BM_WUC_HOST_WU_BIT; 3939235527Sjfv hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); 3940194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 3941194865Sjfv if (ret_val) 3942194865Sjfv return ret_val; 3943194865Sjfv } 3944194865Sjfv 3945169240Sjfv /* Setup link and flow control */ 3946177867Sjfv ret_val = mac->ops.setup_link(hw); 3947169240Sjfv 3948169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 3949173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 3950169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3951169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3952169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3953235527Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3954173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 3955173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 3956169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3957169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3958169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3959235527Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3960173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 3961169240Sjfv 3962248292Sjfv /* ICH8 has opposite polarity of no_snoop bits. 3963173788Sjfv * By default, we should use snoop behavior. 3964173788Sjfv */ 3965169240Sjfv if (mac->type == e1000_ich8lan) 3966169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 3967169240Sjfv else 3968200243Sjfv snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 3969169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 3970169240Sjfv 3971169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3972169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3973169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3974169240Sjfv 3975248292Sjfv /* Clear all of the statistics registers (clear on read). It is 3976169240Sjfv * important that we do this after we have tried to establish link 3977169240Sjfv * because the symbol error count will increment wildly if there 3978169240Sjfv * is no link. 3979169240Sjfv */ 3980169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 3981169240Sjfv 3982169240Sjfv return ret_val; 3983169240Sjfv} 3984248292Sjfv 3985169240Sjfv/** 3986169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3987169589Sjfv * @hw: pointer to the HW structure 3988169240Sjfv * 3989169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 3990169240Sjfv * hardware for transmit and receive. 3991169240Sjfv **/ 3992173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3993169240Sjfv{ 3994169240Sjfv u32 reg; 3995169240Sjfv 3996169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 3997169240Sjfv 3998169240Sjfv /* Extended Device Control */ 3999169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 4000169240Sjfv reg |= (1 << 22); 4001194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4002194865Sjfv if (hw->mac.type >= e1000_pchlan) 4003194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 4004169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 4005169240Sjfv 4006169240Sjfv /* Transmit Descriptor Control 0 */ 4007173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 4008169240Sjfv reg |= (1 << 22); 4009173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 4010169240Sjfv 4011169240Sjfv /* Transmit Descriptor Control 1 */ 4012173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 4013169240Sjfv reg |= (1 << 22); 4014173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 4015169240Sjfv 4016169240Sjfv /* Transmit Arbitration Control 0 */ 4017173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 4018169240Sjfv if (hw->mac.type == e1000_ich8lan) 4019169240Sjfv reg |= (1 << 28) | (1 << 29); 4020169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 4021173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 4022169240Sjfv 4023169240Sjfv /* Transmit Arbitration Control 1 */ 4024173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 4025169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 4026169240Sjfv reg &= ~(1 << 28); 4027169240Sjfv else 4028169240Sjfv reg |= (1 << 28); 4029169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 4030173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 4031169240Sjfv 4032169240Sjfv /* Device Status */ 4033169240Sjfv if (hw->mac.type == e1000_ich8lan) { 4034169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 4035169240Sjfv reg &= ~(1 << 31); 4036169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 4037169240Sjfv } 4038169240Sjfv 4039248292Sjfv /* work-around descriptor data corruption issue during nfs v2 udp 4040205869Sjfv * traffic, just disable the nfs filtering capability 4041205869Sjfv */ 4042205869Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 4043205869Sjfv reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4044248292Sjfv /* Disable IPv6 extension header parsing because some malformed 4045248292Sjfv * IPv6 headers can hang the Rx. 4046248292Sjfv */ 4047248292Sjfv if (hw->mac.type == e1000_ich8lan) 4048248292Sjfv reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4049205869Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 4050205869Sjfv 4051248292Sjfv /* Enable ECC on Lynxpoint */ 4052248292Sjfv if (hw->mac.type == e1000_pch_lpt) { 4053248292Sjfv reg = E1000_READ_REG(hw, E1000_PBECCSTS); 4054248292Sjfv reg |= E1000_PBECCSTS_ECC_ENABLE; 4055248292Sjfv E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); 4056248292Sjfv 4057248292Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 4058248292Sjfv reg |= E1000_CTRL_MEHE; 4059248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 4060248292Sjfv } 4061248292Sjfv 4062169240Sjfv return; 4063169240Sjfv} 4064169240Sjfv 4065169240Sjfv/** 4066169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 4067169589Sjfv * @hw: pointer to the HW structure 4068169240Sjfv * 4069169240Sjfv * Determines which flow control settings to use, then configures flow 4070169240Sjfv * control. Calls the appropriate media-specific link configuration 4071169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 4072169240Sjfv * should be established. Assumes the hardware has previously been reset 4073169240Sjfv * and the transmitter and receiver are not enabled. 4074169240Sjfv **/ 4075177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4076169240Sjfv{ 4077248292Sjfv s32 ret_val; 4078169240Sjfv 4079169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 4080169240Sjfv 4081177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 4082248292Sjfv return E1000_SUCCESS; 4083169240Sjfv 4084248292Sjfv /* ICH parts do not have a word in the NVM to determine 4085169240Sjfv * the default flow control setting, so we explicitly 4086169240Sjfv * set it to full. 4087169240Sjfv */ 4088185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 4089185353Sjfv hw->fc.requested_mode = e1000_fc_full; 4090169240Sjfv 4091248292Sjfv /* Save off the requested flow control mode for use later. Depending 4092185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 4093185353Sjfv */ 4094185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 4095169240Sjfv 4096185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 4097190872Sjfv hw->fc.current_mode); 4098169240Sjfv 4099169240Sjfv /* Continue to configure the copper link. */ 4100177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 4101169240Sjfv if (ret_val) 4102248292Sjfv return ret_val; 4103169240Sjfv 4104173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 4105194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 4106213234Sjfv (hw->phy.type == e1000_phy_82579) || 4107248292Sjfv (hw->phy.type == e1000_phy_i217) || 4108194865Sjfv (hw->phy.type == e1000_phy_82577)) { 4109213234Sjfv E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 4110213234Sjfv 4111194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 4112235527Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 4113235527Sjfv hw->fc.pause_time); 4114194865Sjfv if (ret_val) 4115248292Sjfv return ret_val; 4116194865Sjfv } 4117169240Sjfv 4118248292Sjfv return e1000_set_fc_watermarks_generic(hw); 4119169240Sjfv} 4120169240Sjfv 4121169240Sjfv/** 4122169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4123169589Sjfv * @hw: pointer to the HW structure 4124169240Sjfv * 4125169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 4126169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 4127169240Sjfv * configuring the copper link. 4128169240Sjfv **/ 4129177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 4130169240Sjfv{ 4131169240Sjfv u32 ctrl; 4132169240Sjfv s32 ret_val; 4133169240Sjfv u16 reg_data; 4134169240Sjfv 4135169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 4136169240Sjfv 4137169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 4138169240Sjfv ctrl |= E1000_CTRL_SLU; 4139169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4140169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4141169240Sjfv 4142248292Sjfv /* Set the mac to wait the maximum time between each iteration 4143169240Sjfv * and increase the max iterations when polling the phy; 4144173788Sjfv * this fixes erroneous timeouts at 10Mbps. 4145173788Sjfv */ 4146200243Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 4147235527Sjfv 0xFFFF); 4148169240Sjfv if (ret_val) 4149248292Sjfv return ret_val; 4150194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 4151235527Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 4152235527Sjfv ®_data); 4153169240Sjfv if (ret_val) 4154248292Sjfv return ret_val; 4155169240Sjfv reg_data |= 0x3F; 4156194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 4157235527Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 4158235527Sjfv reg_data); 4159169240Sjfv if (ret_val) 4160248292Sjfv return ret_val; 4161169240Sjfv 4162190872Sjfv switch (hw->phy.type) { 4163190872Sjfv case e1000_phy_igp_3: 4164169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 4165169240Sjfv if (ret_val) 4166248292Sjfv return ret_val; 4167190872Sjfv break; 4168190872Sjfv case e1000_phy_bm: 4169194865Sjfv case e1000_phy_82578: 4170176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 4171176667Sjfv if (ret_val) 4172248292Sjfv return ret_val; 4173190872Sjfv break; 4174194865Sjfv case e1000_phy_82577: 4175213234Sjfv case e1000_phy_82579: 4176194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 4177194865Sjfv if (ret_val) 4178248292Sjfv return ret_val; 4179194865Sjfv break; 4180190872Sjfv case e1000_phy_ife: 4181177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 4182235527Sjfv ®_data); 4183173788Sjfv if (ret_val) 4184248292Sjfv return ret_val; 4185173788Sjfv 4186173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 4187173788Sjfv 4188173788Sjfv switch (hw->phy.mdix) { 4189173788Sjfv case 1: 4190173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 4191173788Sjfv break; 4192173788Sjfv case 2: 4193173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 4194173788Sjfv break; 4195173788Sjfv case 0: 4196173788Sjfv default: 4197173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 4198173788Sjfv break; 4199173788Sjfv } 4200177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 4201235527Sjfv reg_data); 4202173788Sjfv if (ret_val) 4203248292Sjfv return ret_val; 4204190872Sjfv break; 4205190872Sjfv default: 4206190872Sjfv break; 4207173788Sjfv } 4208169240Sjfv 4209248292Sjfv return e1000_setup_copper_link_generic(hw); 4210169240Sjfv} 4211169240Sjfv 4212169240Sjfv/** 4213248292Sjfv * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 4214248292Sjfv * @hw: pointer to the HW structure 4215248292Sjfv * 4216248292Sjfv * Calls the PHY specific link setup function and then calls the 4217248292Sjfv * generic setup_copper_link to finish configuring the link for 4218248292Sjfv * Lynxpoint PCH devices 4219248292Sjfv **/ 4220248292Sjfvstatic s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 4221248292Sjfv{ 4222248292Sjfv u32 ctrl; 4223248292Sjfv s32 ret_val; 4224248292Sjfv 4225248292Sjfv DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); 4226248292Sjfv 4227248292Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 4228248292Sjfv ctrl |= E1000_CTRL_SLU; 4229248292Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4230248292Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4231248292Sjfv 4232248292Sjfv ret_val = e1000_copper_link_setup_82577(hw); 4233248292Sjfv if (ret_val) 4234248292Sjfv return ret_val; 4235248292Sjfv 4236248292Sjfv return e1000_setup_copper_link_generic(hw); 4237248292Sjfv} 4238248292Sjfv 4239248292Sjfv/** 4240169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 4241169589Sjfv * @hw: pointer to the HW structure 4242169589Sjfv * @speed: pointer to store current link speed 4243169589Sjfv * @duplex: pointer to store the current link duplex 4244169240Sjfv * 4245176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 4246169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 4247169240Sjfv * gigabit speeds. 4248169240Sjfv **/ 4249177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 4250235527Sjfv u16 *duplex) 4251169240Sjfv{ 4252169240Sjfv s32 ret_val; 4253169240Sjfv 4254169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 4255169240Sjfv 4256169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 4257169240Sjfv if (ret_val) 4258248292Sjfv return ret_val; 4259169240Sjfv 4260169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 4261169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 4262169240Sjfv (*speed == SPEED_1000)) { 4263169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 4264169240Sjfv } 4265169240Sjfv 4266169240Sjfv return ret_val; 4267169240Sjfv} 4268169240Sjfv 4269169240Sjfv/** 4270169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 4271169589Sjfv * @hw: pointer to the HW structure 4272169240Sjfv * 4273169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 4274169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 4275169240Sjfv * speed is gigabit- 4276169240Sjfv * 0) if workaround is optionally disabled do nothing 4277169240Sjfv * 1) wait 1ms for Kumeran link to come up 4278169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 4279169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 4280169240Sjfv * 4) reset the PHY 4281169240Sjfv * 5) repeat up to 10 times 4282169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 4283169240Sjfv **/ 4284173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 4285169240Sjfv{ 4286185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4287169240Sjfv u32 phy_ctrl; 4288248292Sjfv s32 ret_val; 4289169240Sjfv u16 i, data; 4290173788Sjfv bool link; 4291169240Sjfv 4292169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 4293169240Sjfv 4294218588Sjfv if (!dev_spec->kmrn_lock_loss_workaround_enabled) 4295248292Sjfv return E1000_SUCCESS; 4296169240Sjfv 4297248292Sjfv /* Make sure link is up before proceeding. If not just return. 4298169240Sjfv * Attempting this while link is negotiating fouled up link 4299173788Sjfv * stability 4300173788Sjfv */ 4301169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 4302248292Sjfv if (!link) 4303248292Sjfv return E1000_SUCCESS; 4304169240Sjfv 4305169240Sjfv for (i = 0; i < 10; i++) { 4306169240Sjfv /* read once to clear */ 4307177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 4308169240Sjfv if (ret_val) 4309248292Sjfv return ret_val; 4310169240Sjfv /* and again to get new status */ 4311177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 4312169240Sjfv if (ret_val) 4313248292Sjfv return ret_val; 4314169240Sjfv 4315169240Sjfv /* check for PCS lock */ 4316248292Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 4317248292Sjfv return E1000_SUCCESS; 4318169240Sjfv 4319169240Sjfv /* Issue PHY reset */ 4320177867Sjfv hw->phy.ops.reset(hw); 4321169240Sjfv msec_delay_irq(5); 4322169240Sjfv } 4323169240Sjfv /* Disable GigE link negotiation */ 4324169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 4325169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 4326235527Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4327169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 4328169240Sjfv 4329248292Sjfv /* Call gig speed drop workaround on Gig disable before accessing 4330173788Sjfv * any PHY registers 4331173788Sjfv */ 4332169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 4333169240Sjfv 4334169240Sjfv /* unable to acquire PCS lock */ 4335248292Sjfv return -E1000_ERR_PHY; 4336169240Sjfv} 4337169240Sjfv 4338169240Sjfv/** 4339176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 4340169589Sjfv * @hw: pointer to the HW structure 4341176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 4342169240Sjfv * 4343169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 4344169240Sjfv * /disabled - FALSE). 4345169240Sjfv **/ 4346173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 4347235527Sjfv bool state) 4348169240Sjfv{ 4349185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4350169240Sjfv 4351169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 4352169240Sjfv 4353169240Sjfv if (hw->mac.type != e1000_ich8lan) { 4354169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 4355185353Sjfv return; 4356169240Sjfv } 4357169240Sjfv 4358169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 4359169240Sjfv 4360169240Sjfv return; 4361169240Sjfv} 4362169240Sjfv 4363169240Sjfv/** 4364169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 4365169589Sjfv * @hw: pointer to the HW structure 4366169240Sjfv * 4367169240Sjfv * Workaround for 82566 power-down on D3 entry: 4368169240Sjfv * 1) disable gigabit link 4369169240Sjfv * 2) write VR power-down enable 4370169240Sjfv * 3) read it back 4371169240Sjfv * Continue if successful, else issue LCD reset and repeat 4372169240Sjfv **/ 4373173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 4374169240Sjfv{ 4375169240Sjfv u32 reg; 4376169240Sjfv u16 data; 4377169240Sjfv u8 retry = 0; 4378169240Sjfv 4379169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 4380169240Sjfv 4381169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 4382248292Sjfv return; 4383169240Sjfv 4384169240Sjfv /* Try the workaround twice (if needed) */ 4385169240Sjfv do { 4386169240Sjfv /* Disable link */ 4387169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 4388169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 4389235527Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4390169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 4391169240Sjfv 4392248292Sjfv /* Call gig speed drop workaround on Gig disable before 4393173788Sjfv * accessing any PHY registers 4394173788Sjfv */ 4395169240Sjfv if (hw->mac.type == e1000_ich8lan) 4396169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 4397169240Sjfv 4398169240Sjfv /* Write VR power-down enable */ 4399177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 4400169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 4401185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 4402235527Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 4403169240Sjfv 4404169240Sjfv /* Read it back and test */ 4405177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 4406169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 4407169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 4408169240Sjfv break; 4409169240Sjfv 4410169240Sjfv /* Issue PHY reset and repeat at most one more time */ 4411169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 4412169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 4413169240Sjfv retry++; 4414169240Sjfv } while (retry); 4415169240Sjfv} 4416169240Sjfv 4417169240Sjfv/** 4418169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 4419169589Sjfv * @hw: pointer to the HW structure 4420169240Sjfv * 4421169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 4422176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 4423169240Sjfv * 1) Set Kumeran Near-end loopback 4424169240Sjfv * 2) Clear Kumeran Near-end loopback 4425235527Sjfv * Should only be called for ICH8[m] devices with any 1G Phy. 4426169240Sjfv **/ 4427173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 4428169240Sjfv{ 4429248292Sjfv s32 ret_val; 4430169240Sjfv u16 reg_data; 4431169240Sjfv 4432169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 4433169240Sjfv 4434169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 4435235527Sjfv (hw->phy.type == e1000_phy_ife)) 4436248292Sjfv return; 4437169240Sjfv 4438181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 4439235527Sjfv ®_data); 4440169240Sjfv if (ret_val) 4441248292Sjfv return; 4442169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 4443181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 4444235527Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 4445235527Sjfv reg_data); 4446169240Sjfv if (ret_val) 4447248292Sjfv return; 4448169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 4449248292Sjfv e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 4450248292Sjfv reg_data); 4451169240Sjfv} 4452169240Sjfv 4453169240Sjfv/** 4454235527Sjfv * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 4455176667Sjfv * @hw: pointer to the HW structure 4456176667Sjfv * 4457176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 4458176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 4459235527Sjfv * 'Gig Disable' to force link speed negotiation to a lower speed based on 4460235527Sjfv * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 4461235527Sjfv * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 4462235527Sjfv * needs to be written. 4463248292Sjfv * Parts that support (and are linked to a partner which support) EEE in 4464248292Sjfv * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 4465248292Sjfv * than 10Mbps w/o EEE. 4466176667Sjfv **/ 4467235527Sjfvvoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 4468176667Sjfv{ 4469248292Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4470176667Sjfv u32 phy_ctrl; 4471213234Sjfv s32 ret_val; 4472176667Sjfv 4473235527Sjfv DEBUGFUNC("e1000_suspend_workarounds_ich8lan"); 4474194865Sjfv 4475213234Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 4476235527Sjfv phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 4477248292Sjfv 4478248292Sjfv if (hw->phy.type == e1000_phy_i217) { 4479248292Sjfv u16 phy_reg, device_id = hw->device_id; 4480248292Sjfv 4481248292Sjfv if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4482248292Sjfv (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { 4483248292Sjfv u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 4484248292Sjfv 4485248292Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM6, 4486248292Sjfv fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 4487248292Sjfv } 4488248292Sjfv 4489248292Sjfv ret_val = hw->phy.ops.acquire(hw); 4490248292Sjfv if (ret_val) 4491248292Sjfv goto out; 4492248292Sjfv 4493248292Sjfv if (!dev_spec->eee_disable) { 4494248292Sjfv u16 eee_advert; 4495248292Sjfv 4496248292Sjfv ret_val = 4497248292Sjfv e1000_read_emi_reg_locked(hw, 4498248292Sjfv I217_EEE_ADVERTISEMENT, 4499248292Sjfv &eee_advert); 4500248292Sjfv if (ret_val) 4501248292Sjfv goto release; 4502248292Sjfv 4503248292Sjfv /* Disable LPLU if both link partners support 100BaseT 4504248292Sjfv * EEE and 100Full is advertised on both ends of the 4505248292Sjfv * link. 4506248292Sjfv */ 4507248292Sjfv if ((eee_advert & I82579_EEE_100_SUPPORTED) && 4508248292Sjfv (dev_spec->eee_lp_ability & 4509248292Sjfv I82579_EEE_100_SUPPORTED) && 4510248292Sjfv (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) 4511248292Sjfv phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 4512248292Sjfv E1000_PHY_CTRL_NOND0A_LPLU); 4513248292Sjfv } 4514248292Sjfv 4515248292Sjfv /* For i217 Intel Rapid Start Technology support, 4516248292Sjfv * when the system is going into Sx and no manageability engine 4517248292Sjfv * is present, the driver must configure proxy to reset only on 4518248292Sjfv * power good. LPI (Low Power Idle) state must also reset only 4519248292Sjfv * on power good, as well as the MTA (Multicast table array). 4520248292Sjfv * The SMBus release must also be disabled on LCD reset. 4521248292Sjfv */ 4522248292Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 4523248292Sjfv E1000_ICH_FWSM_FW_VALID)) { 4524248292Sjfv /* Enable proxy to reset only on power good. */ 4525248292Sjfv hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, 4526248292Sjfv &phy_reg); 4527248292Sjfv phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 4528248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 4529248292Sjfv phy_reg); 4530248292Sjfv 4531248292Sjfv /* Set bit enable LPI (EEE) to reset only on 4532248292Sjfv * power good. 4533248292Sjfv */ 4534248292Sjfv hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); 4535248292Sjfv phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 4536248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); 4537248292Sjfv 4538248292Sjfv /* Disable the SMB release on LCD reset. */ 4539248292Sjfv hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); 4540248292Sjfv phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 4541248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 4542248292Sjfv } 4543248292Sjfv 4544248292Sjfv /* Enable MTA to reset for Intel Rapid Start Technology 4545248292Sjfv * Support 4546248292Sjfv */ 4547248292Sjfv hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); 4548248292Sjfv phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 4549248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 4550248292Sjfv 4551248292Sjfvrelease: 4552248292Sjfv hw->phy.ops.release(hw); 4553248292Sjfv } 4554248292Sjfvout: 4555213234Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 4556248292Sjfv 4557235527Sjfv if (hw->mac.type == e1000_ich8lan) 4558235527Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 4559213234Sjfv 4560213234Sjfv if (hw->mac.type >= e1000_pchlan) { 4561213234Sjfv e1000_oem_bits_config_ich8lan(hw, FALSE); 4562248292Sjfv 4563248292Sjfv /* Reset PHY to activate OEM bits on 82577/8 */ 4564248292Sjfv if (hw->mac.type == e1000_pchlan) 4565248292Sjfv e1000_phy_hw_reset_generic(hw); 4566248292Sjfv 4567213234Sjfv ret_val = hw->phy.ops.acquire(hw); 4568213234Sjfv if (ret_val) 4569213234Sjfv return; 4570213234Sjfv e1000_write_smbus_addr(hw); 4571213234Sjfv hw->phy.ops.release(hw); 4572176667Sjfv } 4573176667Sjfv 4574176667Sjfv return; 4575176667Sjfv} 4576176667Sjfv 4577176667Sjfv/** 4578235527Sjfv * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 4579235527Sjfv * @hw: pointer to the HW structure 4580235527Sjfv * 4581235527Sjfv * During Sx to S0 transitions on non-managed devices or managed devices 4582235527Sjfv * on which PHY resets are not blocked, if the PHY registers cannot be 4583235527Sjfv * accessed properly by the s/w toggle the LANPHYPC value to power cycle 4584235527Sjfv * the PHY. 4585248292Sjfv * On i217, setup Intel Rapid Start Technology. 4586235527Sjfv **/ 4587235527Sjfvvoid e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 4588235527Sjfv{ 4589235527Sjfv s32 ret_val; 4590235527Sjfv 4591235527Sjfv DEBUGFUNC("e1000_resume_workarounds_pchlan"); 4592235527Sjfv 4593248292Sjfv if (hw->mac.type < e1000_pch2lan) 4594235527Sjfv return; 4595235527Sjfv 4596248292Sjfv ret_val = e1000_init_phy_workarounds_pchlan(hw); 4597235527Sjfv if (ret_val) { 4598248292Sjfv DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); 4599235527Sjfv return; 4600235527Sjfv } 4601235527Sjfv 4602248292Sjfv /* For i217 Intel Rapid Start Technology support when the system 4603248292Sjfv * is transitioning from Sx and no manageability engine is present 4604248292Sjfv * configure SMBus to restore on reset, disable proxy, and enable 4605248292Sjfv * the reset on MTA (Multicast table array). 4606248292Sjfv */ 4607248292Sjfv if (hw->phy.type == e1000_phy_i217) { 4608248292Sjfv u16 phy_reg; 4609235527Sjfv 4610248292Sjfv ret_val = hw->phy.ops.acquire(hw); 4611248292Sjfv if (ret_val) { 4612248292Sjfv DEBUGOUT("Failed to setup iRST\n"); 4613248292Sjfv return; 4614248292Sjfv } 4615235527Sjfv 4616248292Sjfv if (!(E1000_READ_REG(hw, E1000_FWSM) & 4617248292Sjfv E1000_ICH_FWSM_FW_VALID)) { 4618248292Sjfv /* Restore clear on SMB if no manageability engine 4619248292Sjfv * is present 4620248292Sjfv */ 4621248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, 4622248292Sjfv &phy_reg); 4623248292Sjfv if (ret_val) 4624248292Sjfv goto release; 4625248292Sjfv phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 4626248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 4627235527Sjfv 4628248292Sjfv /* Disable Proxy */ 4629248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); 4630248292Sjfv } 4631248292Sjfv /* Enable reset on MTA */ 4632248292Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, 4633248292Sjfv &phy_reg); 4634248292Sjfv if (ret_val) 4635248292Sjfv goto release; 4636248292Sjfv phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 4637248292Sjfv hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 4638235527Sjfvrelease: 4639248292Sjfv if (ret_val) 4640248292Sjfv DEBUGOUT1("Error %d in resume workarounds\n", ret_val); 4641248292Sjfv hw->phy.ops.release(hw); 4642248292Sjfv } 4643235527Sjfv} 4644235527Sjfv 4645235527Sjfv/** 4646169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 4647169589Sjfv * @hw: pointer to the HW structure 4648169240Sjfv * 4649169240Sjfv * Return the LED back to the default configuration. 4650169240Sjfv **/ 4651177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 4652169240Sjfv{ 4653169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 4654169240Sjfv 4655169240Sjfv if (hw->phy.type == e1000_phy_ife) 4656203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4657235527Sjfv 0); 4658169240Sjfv 4659203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 4660203049Sjfv return E1000_SUCCESS; 4661169240Sjfv} 4662169240Sjfv 4663169240Sjfv/** 4664176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 4665169589Sjfv * @hw: pointer to the HW structure 4666169240Sjfv * 4667176667Sjfv * Turn on the LEDs. 4668169240Sjfv **/ 4669177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 4670169240Sjfv{ 4671169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 4672169240Sjfv 4673169240Sjfv if (hw->phy.type == e1000_phy_ife) 4674203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4675235527Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 4676169240Sjfv 4677203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 4678203049Sjfv return E1000_SUCCESS; 4679169240Sjfv} 4680169240Sjfv 4681169240Sjfv/** 4682176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 4683169589Sjfv * @hw: pointer to the HW structure 4684169240Sjfv * 4685176667Sjfv * Turn off the LEDs. 4686169240Sjfv **/ 4687177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 4688169240Sjfv{ 4689169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 4690169240Sjfv 4691169240Sjfv if (hw->phy.type == e1000_phy_ife) 4692203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4693235527Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 4694169240Sjfv 4695203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 4696203049Sjfv return E1000_SUCCESS; 4697169240Sjfv} 4698169240Sjfv 4699169240Sjfv/** 4700194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 4701194865Sjfv * @hw: pointer to the HW structure 4702194865Sjfv * 4703194865Sjfv * This prepares the SW controllable LED for use. 4704194865Sjfv **/ 4705194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 4706194865Sjfv{ 4707194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 4708194865Sjfv 4709194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 4710235527Sjfv (u16)hw->mac.ledctl_mode1); 4711194865Sjfv} 4712194865Sjfv 4713194865Sjfv/** 4714194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 4715194865Sjfv * @hw: pointer to the HW structure 4716194865Sjfv * 4717194865Sjfv * Return the LED back to the default configuration. 4718194865Sjfv **/ 4719194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 4720194865Sjfv{ 4721194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 4722194865Sjfv 4723194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 4724235527Sjfv (u16)hw->mac.ledctl_default); 4725194865Sjfv} 4726194865Sjfv 4727194865Sjfv/** 4728194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 4729194865Sjfv * @hw: pointer to the HW structure 4730194865Sjfv * 4731194865Sjfv * Turn on the LEDs. 4732194865Sjfv **/ 4733194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 4734194865Sjfv{ 4735194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 4736194865Sjfv u32 i, led; 4737194865Sjfv 4738194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 4739194865Sjfv 4740248292Sjfv /* If no link, then turn LED on by setting the invert bit 4741194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 4742194865Sjfv */ 4743194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 4744194865Sjfv for (i = 0; i < 3; i++) { 4745194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4746194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 4747194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 4748194865Sjfv continue; 4749194865Sjfv if (led & E1000_PHY_LED0_IVRT) 4750194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4751194865Sjfv else 4752194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4753194865Sjfv } 4754194865Sjfv } 4755194865Sjfv 4756194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 4757194865Sjfv} 4758194865Sjfv 4759194865Sjfv/** 4760194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 4761194865Sjfv * @hw: pointer to the HW structure 4762194865Sjfv * 4763194865Sjfv * Turn off the LEDs. 4764194865Sjfv **/ 4765194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 4766194865Sjfv{ 4767194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 4768194865Sjfv u32 i, led; 4769194865Sjfv 4770194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 4771194865Sjfv 4772248292Sjfv /* If no link, then turn LED off by clearing the invert bit 4773194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 4774194865Sjfv */ 4775194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 4776194865Sjfv for (i = 0; i < 3; i++) { 4777194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4778194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 4779194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 4780194865Sjfv continue; 4781194865Sjfv if (led & E1000_PHY_LED0_IVRT) 4782194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4783194865Sjfv else 4784194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4785194865Sjfv } 4786194865Sjfv } 4787194865Sjfv 4788194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 4789194865Sjfv} 4790194865Sjfv 4791194865Sjfv/** 4792213234Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 4793169589Sjfv * @hw: pointer to the HW structure 4794169240Sjfv * 4795213234Sjfv * Read appropriate register for the config done bit for completion status 4796213234Sjfv * and configure the PHY through s/w for EEPROM-less parts. 4797213234Sjfv * 4798213234Sjfv * NOTE: some silicon which is EEPROM-less will fail trying to read the 4799213234Sjfv * config done bit, so only an error is logged and continues. If we were 4800213234Sjfv * to return with error, EEPROM-less silicon would not be able to be reset 4801213234Sjfv * or change link. 4802169240Sjfv **/ 4803177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 4804169240Sjfv{ 4805173788Sjfv s32 ret_val = E1000_SUCCESS; 4806178523Sjfv u32 bank = 0; 4807213234Sjfv u32 status; 4808173788Sjfv 4809213234Sjfv DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 4810194865Sjfv 4811213234Sjfv e1000_get_cfg_done_generic(hw); 4812213234Sjfv 4813213234Sjfv /* Wait for indication from h/w that it has completed basic config */ 4814213234Sjfv if (hw->mac.type >= e1000_ich10lan) { 4815213234Sjfv e1000_lan_init_done_ich8lan(hw); 4816213234Sjfv } else { 4817213234Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 4818213234Sjfv if (ret_val) { 4819248292Sjfv /* When auto config read does not complete, do not 4820213234Sjfv * return with an error. This can happen in situations 4821213234Sjfv * where there is no eeprom and prevents getting link. 4822213234Sjfv */ 4823213234Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 4824213234Sjfv ret_val = E1000_SUCCESS; 4825213234Sjfv } 4826194865Sjfv } 4827194865Sjfv 4828213234Sjfv /* Clear PHY Reset Asserted bit */ 4829213234Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 4830213234Sjfv if (status & E1000_STATUS_PHYRA) 4831213234Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 4832213234Sjfv else 4833213234Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 4834169240Sjfv 4835169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 4836200243Sjfv if (hw->mac.type <= e1000_ich9lan) { 4837248292Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 4838185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 4839178523Sjfv e1000_phy_init_script_igp3(hw); 4840178523Sjfv } 4841178523Sjfv } else { 4842178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 4843185353Sjfv /* Maybe we should do a basic PHY config */ 4844178523Sjfv DEBUGOUT("EEPROM not present\n"); 4845178523Sjfv ret_val = -E1000_ERR_CONFIG; 4846178523Sjfv } 4847169240Sjfv } 4848169240Sjfv 4849173788Sjfv return ret_val; 4850169240Sjfv} 4851169240Sjfv 4852169240Sjfv/** 4853173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 4854173788Sjfv * @hw: pointer to the HW structure 4855173788Sjfv * 4856173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 4857173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 4858173788Sjfv **/ 4859177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 4860173788Sjfv{ 4861173788Sjfv /* If the management interface is not enabled, then power down */ 4862185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 4863185353Sjfv hw->phy.ops.check_reset_block(hw))) 4864173788Sjfv e1000_power_down_phy_copper(hw); 4865173788Sjfv 4866173788Sjfv return; 4867173788Sjfv} 4868173788Sjfv 4869173788Sjfv/** 4870169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 4871169589Sjfv * @hw: pointer to the HW structure 4872169240Sjfv * 4873169240Sjfv * Clears hardware counters specific to the silicon family and calls 4874169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 4875169240Sjfv **/ 4876177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 4877169240Sjfv{ 4878194865Sjfv u16 phy_data; 4879235527Sjfv s32 ret_val; 4880194865Sjfv 4881169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 4882169240Sjfv 4883169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 4884169240Sjfv 4885185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 4886185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 4887185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 4888185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 4889185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 4890185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 4891169240Sjfv 4892185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 4893185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 4894185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 4895169240Sjfv 4896185353Sjfv E1000_READ_REG(hw, E1000_IAC); 4897185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 4898194865Sjfv 4899194865Sjfv /* Clear PHY statistics registers */ 4900194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 4901213234Sjfv (hw->phy.type == e1000_phy_82579) || 4902248292Sjfv (hw->phy.type == e1000_phy_i217) || 4903194865Sjfv (hw->phy.type == e1000_phy_82577)) { 4904235527Sjfv ret_val = hw->phy.ops.acquire(hw); 4905235527Sjfv if (ret_val) 4906235527Sjfv return; 4907235527Sjfv ret_val = hw->phy.ops.set_page(hw, 4908235527Sjfv HV_STATS_PAGE << IGP_PAGE_SHIFT); 4909235527Sjfv if (ret_val) 4910235527Sjfv goto release; 4911235527Sjfv hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4912235527Sjfv hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4913235527Sjfv hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4914235527Sjfv hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4915235527Sjfv hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4916235527Sjfv hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4917235527Sjfv hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4918235527Sjfv hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4919235527Sjfv hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4920235527Sjfv hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4921235527Sjfv hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4922235527Sjfv hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4923235527Sjfv hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4924235527Sjfv hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4925235527Sjfvrelease: 4926235527Sjfv hw->phy.ops.release(hw); 4927194865Sjfv } 4928169240Sjfv} 4929169240Sjfv 4930