e1000_defines.h revision 169240
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33$FreeBSD: head/sys/dev/em/e1000_defines.h 169240 2007-05-04 00:00:12Z jfv $ 34 35 36#ifndef _E1000_DEFINES_H_ 37#define _E1000_DEFINES_H_ 38 39#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 40#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 41#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 42#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 43#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 44#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 45#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 46#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 47#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 48#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 49#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 50#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 51#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 52#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 53#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 54#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 55#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 56#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 57 58/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 59#define REQ_TX_DESCRIPTOR_MULTIPLE 8 60#define REQ_RX_DESCRIPTOR_MULTIPLE 8 61 62/* Definitions for power management and wakeup registers */ 63/* Wake Up Control */ 64#define E1000_WUC_APME 0x00000001 /* APM Enable */ 65#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 66#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 67#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 68#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 69 70/* Wake Up Filter Control */ 71#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 72#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 73#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 74#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 75#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 76#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 77#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 78#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 79#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 80#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 81#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 82#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 83#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 84#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 85#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 86#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 87 88/* Wake Up Status */ 89#define E1000_WUS_LNKC E1000_WUFC_LNKC 90#define E1000_WUS_MAG E1000_WUFC_MAG 91#define E1000_WUS_EX E1000_WUFC_EX 92#define E1000_WUS_MC E1000_WUFC_MC 93#define E1000_WUS_BC E1000_WUFC_BC 94#define E1000_WUS_ARP E1000_WUFC_ARP 95#define E1000_WUS_IPV4 E1000_WUFC_IPV4 96#define E1000_WUS_IPV6 E1000_WUFC_IPV6 97#define E1000_WUS_FLX0 E1000_WUFC_FLX0 98#define E1000_WUS_FLX1 E1000_WUFC_FLX1 99#define E1000_WUS_FLX2 E1000_WUFC_FLX2 100#define E1000_WUS_FLX3 E1000_WUFC_FLX3 101#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS 102 103/* Wake Up Packet Length */ 104#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 105 106/* Four Flexible Filters are supported */ 107#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 108 109/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 110#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 111 112#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 113#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 114#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 115 116/* Extended Device Control */ 117#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 118#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 119#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 120#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 121#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 122#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 123#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 124#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 125#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 126#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 127#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 128#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 129#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 130#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 131#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 132#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 133#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 134#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 135#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 136#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 137#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 138#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 139#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 140#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 141#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 142#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 143#define E1000_CTRL_EXT_EIAME 0x01000000 144#define E1000_CTRL_EXT_IRCA 0x00000001 145#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 146#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 147#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 148#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 149#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 150#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */ 151#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 152#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 153#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 154#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 155#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 156#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 157#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 158#define E1000_I2CCMD_REG_ADDR_SHIFT 16 159#define E1000_I2CCMD_REG_ADDR 0x00FF0000 160#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 161#define E1000_I2CCMD_PHY_ADDR 0x07000000 162#define E1000_I2CCMD_OPCODE_READ 0x08000000 163#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 164#define E1000_I2CCMD_RESET 0x10000000 165#define E1000_I2CCMD_READY 0x20000000 166#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 167#define E1000_I2CCMD_ERROR 0x80000000 168#define E1000_MAX_SGMII_PHY_REG_ADDR 255 169#define E1000_I2CCMD_PHY_TIMEOUT 200 170 171/* Receive Decriptor bit definitions */ 172#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 173#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 174#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 175#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 176#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 177#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 178#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 179#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 180#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 181#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 182#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 183#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 184#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 185#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 186#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 187#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 188#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 189#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 190#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 191#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 192#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 193#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 194#define E1000_RXD_SPC_PRI_SHIFT 13 195#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 196#define E1000_RXD_SPC_CFI_SHIFT 12 197 198#define E1000_RXDEXT_STATERR_CE 0x01000000 199#define E1000_RXDEXT_STATERR_SE 0x02000000 200#define E1000_RXDEXT_STATERR_SEQ 0x04000000 201#define E1000_RXDEXT_STATERR_CXE 0x10000000 202#define E1000_RXDEXT_STATERR_TCPE 0x20000000 203#define E1000_RXDEXT_STATERR_IPE 0x40000000 204#define E1000_RXDEXT_STATERR_RXE 0x80000000 205 206/* mask to determine if packets should be dropped due to frame errors */ 207#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 208 E1000_RXD_ERR_CE | \ 209 E1000_RXD_ERR_SE | \ 210 E1000_RXD_ERR_SEQ | \ 211 E1000_RXD_ERR_CXE | \ 212 E1000_RXD_ERR_RXE) 213 214/* Same mask, but for extended and packet split descriptors */ 215#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 216 E1000_RXDEXT_STATERR_CE | \ 217 E1000_RXDEXT_STATERR_SE | \ 218 E1000_RXDEXT_STATERR_SEQ | \ 219 E1000_RXDEXT_STATERR_CXE | \ 220 E1000_RXDEXT_STATERR_RXE) 221 222#define E1000_MRQC_ENABLE_MASK 0x00000007 223#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 224#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 225#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 226#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 227#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 228#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 229#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 230#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 231#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 232 233#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 234#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 235 236/* Management Control */ 237#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 238#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 239#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 240#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 241#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 242#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 243#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 244#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 245#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 246#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 247 * Filtering */ 248#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 249#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 250#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 251#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 252#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 253#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 254#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 255 * filtering */ 256#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 257 * memory */ 258#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 259 * filtering */ 260#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 261#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 262#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 263#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 264#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 265#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 266#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 267#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 268 269#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 270#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 271 272/* Receive Control */ 273#define E1000_RCTL_RST 0x00000001 /* Software reset */ 274#define E1000_RCTL_EN 0x00000002 /* enable */ 275#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 276#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 277#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 278#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 279#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 280#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 281#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 282#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 283#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 284#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 285#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 286#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 287#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 288#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 289#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 290#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 291#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 292#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 293#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 294#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 295/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 296#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 297#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 298#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 299#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 300/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 301#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 302#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 303#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 304#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 305#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 306#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 307#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 308#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 309#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 310#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 311#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 312#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 313 314/* Use byte values for the following shift parameters 315 * Usage: 316 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 317 * E1000_PSRCTL_BSIZE0_MASK) | 318 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 319 * E1000_PSRCTL_BSIZE1_MASK) | 320 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 321 * E1000_PSRCTL_BSIZE2_MASK) | 322 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 323 * E1000_PSRCTL_BSIZE3_MASK)) 324 * where value0 = [128..16256], default=256 325 * value1 = [1024..64512], default=4096 326 * value2 = [0..64512], default=4096 327 * value3 = [0..64512], default=0 328 */ 329 330#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 331#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 332#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 333#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 334 335#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 336#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 337#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 338#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 339 340/* SWFW_SYNC Definitions */ 341#define E1000_SWFW_EEP_SM 0x1 342#define E1000_SWFW_PHY0_SM 0x2 343#define E1000_SWFW_PHY1_SM 0x4 344 345/* Device Control */ 346#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 347#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 348#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 349#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 350#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 351#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 352#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 353#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 354#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 355#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 356#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 357#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 358#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 359#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 360#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 361#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 362#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 363#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 364#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 365#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 366#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 367#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 368#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 369#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 370#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 371#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 372#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 373#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 374#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 375#define E1000_CTRL_RST 0x04000000 /* Global reset */ 376#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 377#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 378#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 379#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 380#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 381#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 382#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 383 384/* Bit definitions for the Management Data IO (MDIO) and Management Data 385 * Clock (MDC) pins in the Device Control Register. 386 */ 387#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 388#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 389#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 390#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 391#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 392#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 393#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 394#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 395 396#define E1000_CONNSW_ENRGSRC 0x4 397#define E1000_PCS_LCTL_FLV_LINK_UP 1 398#define E1000_PCS_LCTL_FSV_10 0 399#define E1000_PCS_LCTL_FSV_100 2 400#define E1000_PCS_LCTL_FSV_1000 4 401#define E1000_PCS_LCTL_FDV_FULL 8 402#define E1000_PCS_LCTL_FSD 0x10 403#define E1000_PCS_LCTL_FORCE_LINK 0x20 404#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 405#define E1000_PCS_LCTL_AN_ENABLE 0x10000 406#define E1000_PCS_LCTL_AN_RESTART 0x20000 407#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 408#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 409#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 410#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 411#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 412#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 413#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 414 415#define E1000_PCS_LSTS_LINK_OK 1 416#define E1000_PCS_LSTS_SPEED_10 0 417#define E1000_PCS_LSTS_SPEED_100 2 418#define E1000_PCS_LSTS_SPEED_1000 4 419#define E1000_PCS_LSTS_DUPLEX_FULL 8 420#define E1000_PCS_LSTS_SYNK_OK 0x10 421#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 422#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 423#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 424#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 425#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 426 427/* Device Status */ 428#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 429#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 430#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 431#define E1000_STATUS_FUNC_SHIFT 2 432#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 433#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 434#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 435#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 436#define E1000_STATUS_SPEED_MASK 0x000000C0 437#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 438#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 439#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 440#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 441#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 442#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 443#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 444#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 445#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 446#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 447#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 448#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 449#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 450#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 451#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 452#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 453#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 454#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 455#define E1000_STATUS_FUSE_8 0x04000000 456#define E1000_STATUS_FUSE_9 0x08000000 457#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 458#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 459 460/* Constants used to intrepret the masked PCI-X bus speed. */ 461#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 462#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 463#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 464 465#define SPEED_10 10 466#define SPEED_100 100 467#define SPEED_1000 1000 468#define HALF_DUPLEX 1 469#define FULL_DUPLEX 2 470 471#define PHY_FORCE_TIME 20 472 473#define ADVERTISE_10_HALF 0x0001 474#define ADVERTISE_10_FULL 0x0002 475#define ADVERTISE_100_HALF 0x0004 476#define ADVERTISE_100_FULL 0x0008 477#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 478#define ADVERTISE_1000_FULL 0x0020 479 480/* 1000/H is not supported, nor spec-compliant. */ 481#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 482 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 483 ADVERTISE_1000_FULL) 484#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 485 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 486#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 487#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 488#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 489 ADVERTISE_1000_FULL) 490#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 491 492#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 493 494/* LED Control */ 495#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 496#define E1000_LEDCTL_LED0_MODE_SHIFT 0 497#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 498#define E1000_LEDCTL_LED0_IVRT 0x00000040 499#define E1000_LEDCTL_LED0_BLINK 0x00000080 500#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 501#define E1000_LEDCTL_LED1_MODE_SHIFT 8 502#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 503#define E1000_LEDCTL_LED1_IVRT 0x00004000 504#define E1000_LEDCTL_LED1_BLINK 0x00008000 505#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 506#define E1000_LEDCTL_LED2_MODE_SHIFT 16 507#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 508#define E1000_LEDCTL_LED2_IVRT 0x00400000 509#define E1000_LEDCTL_LED2_BLINK 0x00800000 510#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 511#define E1000_LEDCTL_LED3_MODE_SHIFT 24 512#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 513#define E1000_LEDCTL_LED3_IVRT 0x40000000 514#define E1000_LEDCTL_LED3_BLINK 0x80000000 515 516#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 517#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 518#define E1000_LEDCTL_MODE_LINK_UP 0x2 519#define E1000_LEDCTL_MODE_ACTIVITY 0x3 520#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 521#define E1000_LEDCTL_MODE_LINK_10 0x5 522#define E1000_LEDCTL_MODE_LINK_100 0x6 523#define E1000_LEDCTL_MODE_LINK_1000 0x7 524#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 525#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 526#define E1000_LEDCTL_MODE_COLLISION 0xA 527#define E1000_LEDCTL_MODE_BUS_SPEED 0xB 528#define E1000_LEDCTL_MODE_BUS_SIZE 0xC 529#define E1000_LEDCTL_MODE_PAUSED 0xD 530#define E1000_LEDCTL_MODE_LED_ON 0xE 531#define E1000_LEDCTL_MODE_LED_OFF 0xF 532 533/* Transmit Descriptor bit definitions */ 534#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 535#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 536#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 537#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 538#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 539#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 540#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 541#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 542#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 543#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 544#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 545#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 546#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 547#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 548#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 549#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 550#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 551#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 552#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 553#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 554 555/* Transmit Control */ 556#define E1000_TCTL_RST 0x00000001 /* software reset */ 557#define E1000_TCTL_EN 0x00000002 /* enable tx */ 558#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 559#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 560#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 561#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 562#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 563#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 564#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 565#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 566#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 567 568/* Transmit Arbitration Count */ 569#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 570 571/* SerDes Control */ 572#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 573 574/* Receive Checksum Control */ 575#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 576#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 577#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 578#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 579#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 580#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 581#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 582 583/* Header split receive */ 584#define E1000_RFCTL_ISCSI_DIS 0x00000001 585#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 586#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 587#define E1000_RFCTL_NFSW_DIS 0x00000040 588#define E1000_RFCTL_NFSR_DIS 0x00000080 589#define E1000_RFCTL_NFS_VER_MASK 0x00000300 590#define E1000_RFCTL_NFS_VER_SHIFT 8 591#define E1000_RFCTL_IPV6_DIS 0x00000400 592#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 593#define E1000_RFCTL_ACK_DIS 0x00001000 594#define E1000_RFCTL_ACKD_DIS 0x00002000 595#define E1000_RFCTL_IPFRSP_DIS 0x00004000 596#define E1000_RFCTL_EXTEN 0x00008000 597#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 598#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 599 600/* Collision related configuration parameters */ 601#define E1000_COLLISION_THRESHOLD 15 602#define E1000_CT_SHIFT 4 603#define E1000_COLLISION_DISTANCE 63 604#define E1000_COLD_SHIFT 12 605 606/* Default values for the transmit IPG register */ 607#ifndef NO_82542_SUPPORT 608#define DEFAULT_82542_TIPG_IPGT 10 609#endif 610#define DEFAULT_82543_TIPG_IPGT_FIBER 9 611#define DEFAULT_82543_TIPG_IPGT_COPPER 8 612 613#define E1000_TIPG_IPGT_MASK 0x000003FF 614#define E1000_TIPG_IPGR1_MASK 0x000FFC00 615#define E1000_TIPG_IPGR2_MASK 0x3FF00000 616 617#ifndef NO_82542_SUPPORT 618#define DEFAULT_82542_TIPG_IPGR1 2 619#endif 620#define DEFAULT_82543_TIPG_IPGR1 8 621#define E1000_TIPG_IPGR1_SHIFT 10 622 623#ifndef NO_82542_SUPPORT 624#define DEFAULT_82542_TIPG_IPGR2 10 625#endif 626#define DEFAULT_82543_TIPG_IPGR2 6 627#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 628#define E1000_TIPG_IPGR2_SHIFT 20 629 630/* Ethertype field values */ 631#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 632 633#define ETHERNET_FCS_SIZE 4 634#define MAX_JUMBO_FRAME_SIZE 0x3F00 635 636/* Extended Configuration Control and Size */ 637#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 638#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 639#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 640#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 641#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 642#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 643#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 644 645#define E1000_PHY_CTRL_SPD_EN 0x00000001 646#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 647#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 648#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 649#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 650 651#define E1000_KABGTXD_BGSQLBIAS 0x00050000 652 653/* PBA constants */ 654#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 655#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 656#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 657#define E1000_PBA_20K 0x0014 658#define E1000_PBA_22K 0x0016 659#define E1000_PBA_24K 0x0018 660#define E1000_PBA_30K 0x001E 661#define E1000_PBA_32K 0x0020 662#define E1000_PBA_34K 0x0022 663#define E1000_PBA_38K 0x0026 664#define E1000_PBA_40K 0x0028 665#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 666 667#define E1000_PBS_16K E1000_PBA_16K 668#define E1000_PBS_24K E1000_PBA_24K 669 670#define IFS_MAX 80 671#define IFS_MIN 40 672#define IFS_RATIO 4 673#define IFS_STEP 10 674#define MIN_NUM_XMITS 1000 675 676/* SW Semaphore Register */ 677#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 678#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 679#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 680#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 681 682/* Interrupt Cause Read */ 683#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 684#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 685#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 686#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 687#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 688#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 689#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 690#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 691#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 692#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 693#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 694#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 695#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 696#define E1000_ICR_TXD_LOW 0x00008000 697#define E1000_ICR_SRPD 0x00010000 698#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 699#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 700#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 701#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 702#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 703#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 704#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 705#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 706#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 707#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 708#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 709#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 710#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 711#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 712 713/* Extended Interrupt Cause Read */ 714#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 715#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 716#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 717#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 718#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 719#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 720#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 721#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 722#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 723#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 724/* TCP Timer */ 725#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 726#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 727#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 728#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 729 730/* This defines the bits that are set in the Interrupt Mask 731 * Set/Read Register. Each bit is documented below: 732 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 733 * o RXSEQ = Receive Sequence Error 734 */ 735#define POLL_IMS_ENABLE_MASK ( \ 736 E1000_IMS_RXDMT0 | \ 737 E1000_IMS_RXSEQ) 738 739/* This defines the bits that are set in the Interrupt Mask 740 * Set/Read Register. Each bit is documented below: 741 * o RXT0 = Receiver Timer Interrupt (ring 0) 742 * o TXDW = Transmit Descriptor Written Back 743 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 744 * o RXSEQ = Receive Sequence Error 745 * o LSC = Link Status Change 746 */ 747#define IMS_ENABLE_MASK ( \ 748 E1000_IMS_RXT0 | \ 749 E1000_IMS_TXDW | \ 750 E1000_IMS_RXDMT0 | \ 751 E1000_IMS_RXSEQ | \ 752 E1000_IMS_LSC) 753 754/* Interrupt Mask Set */ 755#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 756#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 757#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 758#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 759#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 760#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 761#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 762#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 763#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 764#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 765#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 766#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 767#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 768#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 769#define E1000_IMS_SRPD E1000_ICR_SRPD 770#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 771#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 772#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 773#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 774#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 775#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 776#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 777#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 778#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 779#define E1000_IMS_DSW E1000_ICR_DSW 780#define E1000_IMS_PHYINT E1000_ICR_PHYINT 781#define E1000_IMS_EPRST E1000_ICR_EPRST 782 783/* Extended Interrupt Mask Set */ 784#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 785#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 786#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 787#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 788#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 789#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 790#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 791#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 792#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 793#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 794 795/* Interrupt Cause Set */ 796#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 797#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 798#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 799#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 800#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 801#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 802#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 803#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 804#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 805#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 806#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 807#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 808#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 809#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 810#define E1000_ICS_SRPD E1000_ICR_SRPD 811#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 812#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 813#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 814#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 815#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 816#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 817#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 818#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 819#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 820#define E1000_ICS_DSW E1000_ICR_DSW 821#define E1000_ICS_PHYINT E1000_ICR_PHYINT 822#define E1000_ICS_EPRST E1000_ICR_EPRST 823 824/* Extended Interrupt Cause Set */ 825#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 826#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 827#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 828#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 829#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 830#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 831#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 832#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 833#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 834#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 835 836/* Transmit Descriptor Control */ 837#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 838#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 839#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 840#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 841#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 842#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 843#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 844#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 845 still to be processed. */ 846 847/* Flow Control Constants */ 848#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 849#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 850#define FLOW_CONTROL_TYPE 0x8808 851 852/* 802.1q VLAN Packet Size */ 853#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 854#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 855 856/* Receive Address */ 857/* Number of high/low register pairs in the RAR. The RAR (Receive Address 858 * Registers) holds the directed and multicast addresses that we monitor. 859 * Technically, we have 16 spots. However, we reserve one of these spots 860 * (RAR[15]) for our directed address used by controllers with 861 * manageability enabled, allowing us room for 15 multicast addresses. 862 */ 863#define E1000_RAR_ENTRIES 15 864#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 865 866/* Error Codes */ 867#define E1000_SUCCESS 0 868#define E1000_ERR_NVM 1 869#define E1000_ERR_PHY 2 870#define E1000_ERR_CONFIG 3 871#define E1000_ERR_PARAM 4 872#define E1000_ERR_MAC_INIT 5 873#define E1000_ERR_PHY_TYPE 6 874#define E1000_ERR_RESET 9 875#define E1000_ERR_MASTER_REQUESTS_PENDING 10 876#define E1000_ERR_HOST_INTERFACE_COMMAND 11 877#define E1000_BLK_PHY_RESET 12 878#define E1000_ERR_SWFW_SYNC 13 879#define E1000_NOT_IMPLEMENTED 14 880 881/* Loop limit on how long we wait for auto-negotiation to complete */ 882#define FIBER_LINK_UP_LIMIT 50 883#define COPPER_LINK_UP_LIMIT 10 884#define PHY_AUTO_NEG_LIMIT 45 885#define PHY_FORCE_LIMIT 20 886/* Number of 100 microseconds we wait for PCI Express master disable */ 887#define MASTER_DISABLE_TIMEOUT 800 888/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 889#define PHY_CFG_TIMEOUT 100 890/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 891#define MDIO_OWNERSHIP_TIMEOUT 10 892/* Number of milliseconds for NVM auto read done after MAC reset. */ 893#define AUTO_READ_DONE_TIMEOUT 10 894 895/* Flow Control */ 896#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 897#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 898#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 899#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 900 901/* Transmit Configuration Word */ 902#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 903#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 904#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 905#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 906#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 907#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 908#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 909#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 910#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 911#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 912 913/* Receive Configuration Word */ 914#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 915#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 916#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 917#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 918#define E1000_RXCW_C 0x20000000 /* Receive config */ 919#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 920#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 921 922/* PCI Express Control */ 923#define E1000_GCR_RXD_NO_SNOOP 0x00000001 924#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 925#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 926#define E1000_GCR_TXD_NO_SNOOP 0x00000008 927#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 928#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 929 930#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 931 E1000_GCR_RXDSCW_NO_SNOOP | \ 932 E1000_GCR_RXDSCR_NO_SNOOP | \ 933 E1000_GCR_TXD_NO_SNOOP | \ 934 E1000_GCR_TXDSCW_NO_SNOOP | \ 935 E1000_GCR_TXDSCR_NO_SNOOP) 936 937/* PHY Control Register */ 938#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 939#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 940#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 941#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 942#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 943#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 944#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 945#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 946#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 947#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 948#define MII_CR_SPEED_1000 0x0040 949#define MII_CR_SPEED_100 0x2000 950#define MII_CR_SPEED_10 0x0000 951 952/* PHY Status Register */ 953#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 954#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 955#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 956#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 957#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 958#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 959#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 960#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 961#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 962#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 963#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 964#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 965#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 966#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 967#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 968 969/* Autoneg Advertisement Register */ 970#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 971#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 972#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 973#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 974#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 975#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 976#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 977#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 978#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 979#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 980 981/* Link Partner Ability Register (Base Page) */ 982#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 983#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 984#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 985#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 986#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 987#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 988#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 989#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 990#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 991#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 992#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 993 994/* Autoneg Expansion Register */ 995#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 996#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 997#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 998#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 999#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 1000 1001/* 1000BASE-T Control Register */ 1002#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1003#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1004#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1005#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1006 /* 0=DTE device */ 1007#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1008 /* 0=Configure PHY as Slave */ 1009#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1010 /* 0=Automatic Master/Slave config */ 1011#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1012#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1013#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1014#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1015#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1016 1017/* 1000BASE-T Status Register */ 1018#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1019#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1020#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1021#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1022#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1023#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1024#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 1025#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1026 1027#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1028 1029/* PHY 1000 MII Register/Bit Definitions */ 1030/* PHY Registers defined by IEEE */ 1031#define PHY_CONTROL 0x00 /* Control Register */ 1032#define PHY_STATUS 0x01 /* Status Regiser */ 1033#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1034#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1035#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1036#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1037#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1038#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 1039#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1040#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1041#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1042#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1043 1044/* NVM Control */ 1045#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 1046#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1047#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1048#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1049#define E1000_EECD_FWE_MASK 0x00000030 1050#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1051#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1052#define E1000_EECD_FWE_SHIFT 4 1053#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1054#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1055#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1056#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1057#define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type 1058 * (0-small, 1-large) */ 1059#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1060#ifndef E1000_NVM_GRANT_ATTEMPTS 1061#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1062#endif 1063#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1064#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1065#define E1000_EECD_SIZE_EX_SHIFT 11 1066#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1067#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1068#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1069#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1070#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1071#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1072#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1073#define E1000_EECD_SECVAL_SHIFT 22 1074 1075#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1076#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1077#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 1078#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1079#define E1000_NVM_RW_REG_START 1 /* Start operation */ 1080#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1081#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1082#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1083#define E1000_FLASH_UPDATES 2000 1084 1085/* NVM Word Offsets */ 1086#define NVM_COMPAT 0x0003 1087#define NVM_ID_LED_SETTINGS 0x0004 1088#define NVM_VERSION 0x0005 1089#define NVM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 1090#define NVM_PHY_CLASS_WORD 0x0007 1091#define NVM_INIT_CONTROL1_REG 0x000A 1092#define NVM_INIT_CONTROL2_REG 0x000F 1093#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1094#define NVM_INIT_CONTROL3_PORT_B 0x0014 1095#define NVM_INIT_3GIO_3 0x001A 1096#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1097#define NVM_INIT_CONTROL3_PORT_A 0x0024 1098#define NVM_CFG 0x0012 1099#define NVM_FLASH_VERSION 0x0032 1100#define NVM_CHECKSUM_REG 0x003F 1101 1102#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 1103#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 1104 1105/* Mask bits for fields in Word 0x0f of the NVM */ 1106#define NVM_WORD0F_PAUSE_MASK 0x3000 1107#define NVM_WORD0F_PAUSE 0x1000 1108#define NVM_WORD0F_ASM_DIR 0x2000 1109#define NVM_WORD0F_ANE 0x0800 1110#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1111#define NVM_WORD0F_LPLU 0x0001 1112 1113/* Mask bits for fields in Word 0x1a of the NVM */ 1114#define NVM_WORD1A_ASPM_MASK 0x000C 1115 1116/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1117#define NVM_SUM 0xBABA 1118 1119#define NVM_MAC_ADDR_OFFSET 0 1120#define NVM_PBA_OFFSET_0 8 1121#define NVM_PBA_OFFSET_1 9 1122#define NVM_RESERVED_WORD 0xFFFF 1123#define NVM_PHY_CLASS_A 0x8000 1124#define NVM_SERDES_AMPLITUDE_MASK 0x000F 1125#define NVM_SIZE_MASK 0x1C00 1126#define NVM_SIZE_SHIFT 10 1127#define NVM_WORD_SIZE_BASE_SHIFT 6 1128#define NVM_SWDPIO_EXT_SHIFT 4 1129 1130/* NVM Commands - Microwire */ 1131#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1132#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1133#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1134#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1135#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erast/write disable */ 1136 1137/* NVM Commands - SPI */ 1138#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1139#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1140#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1141#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1142#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1143#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ 1144#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1145#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ 1146 1147/* SPI NVM Status Register */ 1148#define NVM_STATUS_RDY_SPI 0x01 1149#define NVM_STATUS_WEN_SPI 0x02 1150#define NVM_STATUS_BP0_SPI 0x04 1151#define NVM_STATUS_BP1_SPI 0x08 1152#define NVM_STATUS_WPEN_SPI 0x80 1153 1154/* Word definitions for ID LED Settings */ 1155#define ID_LED_RESERVED_0000 0x0000 1156#define ID_LED_RESERVED_FFFF 0xFFFF 1157#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1158 (ID_LED_OFF1_OFF2 << 8) | \ 1159 (ID_LED_DEF1_DEF2 << 4) | \ 1160 (ID_LED_DEF1_DEF2)) 1161#define ID_LED_DEF1_DEF2 0x1 1162#define ID_LED_DEF1_ON2 0x2 1163#define ID_LED_DEF1_OFF2 0x3 1164#define ID_LED_ON1_DEF2 0x4 1165#define ID_LED_ON1_ON2 0x5 1166#define ID_LED_ON1_OFF2 0x6 1167#define ID_LED_OFF1_DEF2 0x7 1168#define ID_LED_OFF1_ON2 0x8 1169#define ID_LED_OFF1_OFF2 0x9 1170 1171#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1172#define IGP_ACTIVITY_LED_ENABLE 0x0300 1173#define IGP_LED3_MODE 0x07000000 1174 1175/* PCI/PCI-X/PCI-EX Config space */ 1176#define PCIX_COMMAND_REGISTER 0xE6 1177#define PCIX_STATUS_REGISTER_LO 0xE8 1178#define PCIX_STATUS_REGISTER_HI 0xEA 1179#define PCI_HEADER_TYPE_REGISTER 0x0E 1180#define PCIE_LINK_STATUS 0x12 1181 1182#define PCIX_COMMAND_MMRBC_MASK 0x000C 1183#define PCIX_COMMAND_MMRBC_SHIFT 0x2 1184#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1185#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1186#define PCIX_STATUS_HI_MMRBC_4K 0x3 1187#define PCIX_STATUS_HI_MMRBC_2K 0x2 1188#define PCIX_STATUS_LO_FUNC_MASK 0x7 1189#define PCI_HEADER_TYPE_MULTIFUNC 0x80 1190#define PCIE_LINK_WIDTH_MASK 0x3F0 1191#define PCIE_LINK_WIDTH_SHIFT 4 1192 1193#ifndef ETH_ADDR_LEN 1194#define ETH_ADDR_LEN 6 1195#endif 1196 1197#define PHY_REVISION_MASK 0xFFFFFFF0 1198#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1199#define MAX_PHY_MULTI_PAGE_REG 0xF 1200 1201/* Bit definitions for valid PHY IDs. */ 1202/* I = Integrated 1203 * E = External 1204 */ 1205#define M88E1000_E_PHY_ID 0x01410C50 1206#define M88E1000_I_PHY_ID 0x01410C30 1207#define M88E1011_I_PHY_ID 0x01410C20 1208#define IGP01E1000_I_PHY_ID 0x02A80380 1209#define M88E1011_I_REV_4 0x04 1210#define M88E1111_I_PHY_ID 0x01410CC0 1211#define GG82563_E_PHY_ID 0x01410CA0 1212#define IGP03E1000_E_PHY_ID 0x02A80390 1213#define IFE_E_PHY_ID 0x02A80330 1214#define IFE_PLUS_E_PHY_ID 0x02A80320 1215#define IFE_C_E_PHY_ID 0x02A80310 1216#define M88_VENDOR 0x0141 1217 1218/* M88E1000 Specific Registers */ 1219#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1220#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1221#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1222#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1223#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1224#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1225 1226#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1227#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 1228#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1229#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1230#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1231 1232/* M88E1000 PHY Specific Control Register */ 1233#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1234#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 1235#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1236#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 1237 * 0=CLK125 toggling 1238 */ 1239#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1240 /* Manual MDI configuration */ 1241#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1242#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 1243 * 100BASE-TX/10BASE-T: 1244 * MDI Mode 1245 */ 1246#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 1247 * all speeds. 1248 */ 1249#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 1250 /* 1=Enable Extended 10BASE-T distance 1251 * (Lower 10BASE-T RX Threshold) 1252 * 0=Normal 10BASE-T RX Threshold */ 1253#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1254 /* 1=5-Bit interface in 100BASE-TX 1255 * 0=MII interface in 100BASE-TX */ 1256#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1257#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1258#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 1259 1260/* M88E1000 PHY Specific Status Register */ 1261#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1262#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1263#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1264#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1265#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 1266 * 3=110-140M;4=>140M */ 1267#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1268#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1269#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1270#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1271#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1272#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1273#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1274#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1275 1276#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1277 1278/* M88E1000 Extended PHY Specific Control Register */ 1279#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1280#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 1281 * Will assert lost lock and bring 1282 * link down if idle not seen 1283 * within 1ms in 1000BASE-T 1284 */ 1285/* Number of times we will attempt to autonegotiate before downshifting if we 1286 * are the master */ 1287#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1288#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1289#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1290#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1291#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1292/* Number of times we will attempt to autonegotiate before downshifting if we 1293 * are the slave */ 1294#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1295#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1296#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1297#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1298#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1299#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1300#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1301#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1302 1303/* M88EC018 Rev 2 specific DownShift settings */ 1304#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1305#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1306#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1307#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1308#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1309#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1310#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1311#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1312#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1313 1314/* Bits... 1315 * 15-5: page 1316 * 4-0: register offset 1317 */ 1318#define GG82563_PAGE_SHIFT 5 1319#define GG82563_REG(page, reg) \ 1320 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1321#define GG82563_MIN_ALT_REG 30 1322 1323/* GG82563 Specific Registers */ 1324#define GG82563_PHY_SPEC_CTRL \ 1325 GG82563_REG(0, 16) /* PHY Specific Control */ 1326#define GG82563_PHY_SPEC_STATUS \ 1327 GG82563_REG(0, 17) /* PHY Specific Status */ 1328#define GG82563_PHY_INT_ENABLE \ 1329 GG82563_REG(0, 18) /* Interrupt Enable */ 1330#define GG82563_PHY_SPEC_STATUS_2 \ 1331 GG82563_REG(0, 19) /* PHY Specific Status 2 */ 1332#define GG82563_PHY_RX_ERR_CNTR \ 1333 GG82563_REG(0, 21) /* Receive Error Counter */ 1334#define GG82563_PHY_PAGE_SELECT \ 1335 GG82563_REG(0, 22) /* Page Select */ 1336#define GG82563_PHY_SPEC_CTRL_2 \ 1337 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 1338#define GG82563_PHY_PAGE_SELECT_ALT \ 1339 GG82563_REG(0, 29) /* Alternate Page Select */ 1340#define GG82563_PHY_TEST_CLK_CTRL \ 1341 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 1342 1343#define GG82563_PHY_MAC_SPEC_CTRL \ 1344 GG82563_REG(2, 21) /* MAC Specific Control Register */ 1345#define GG82563_PHY_MAC_SPEC_CTRL_2 \ 1346 GG82563_REG(2, 26) /* MAC Specific Control 2 */ 1347 1348#define GG82563_PHY_DSP_DISTANCE \ 1349 GG82563_REG(5, 26) /* DSP Distance */ 1350 1351/* Page 193 - Port Control Registers */ 1352#define GG82563_PHY_KMRN_MODE_CTRL \ 1353 GG82563_REG(193, 16) /* Kumeran Mode Control */ 1354#define GG82563_PHY_PORT_RESET \ 1355 GG82563_REG(193, 17) /* Port Reset */ 1356#define GG82563_PHY_REVISION_ID \ 1357 GG82563_REG(193, 18) /* Revision ID */ 1358#define GG82563_PHY_DEVICE_ID \ 1359 GG82563_REG(193, 19) /* Device ID */ 1360#define GG82563_PHY_PWR_MGMT_CTRL \ 1361 GG82563_REG(193, 20) /* Power Management Control */ 1362#define GG82563_PHY_RATE_ADAPT_CTRL \ 1363 GG82563_REG(193, 25) /* Rate Adaptation Control */ 1364 1365/* Page 194 - KMRN Registers */ 1366#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 1367 GG82563_REG(194, 16) /* FIFO's Control/Status */ 1368#define GG82563_PHY_KMRN_CTRL \ 1369 GG82563_REG(194, 17) /* Control */ 1370#define GG82563_PHY_INBAND_CTRL \ 1371 GG82563_REG(194, 18) /* Inband Control */ 1372#define GG82563_PHY_KMRN_DIAGNOSTIC \ 1373 GG82563_REG(194, 19) /* Diagnostic */ 1374#define GG82563_PHY_ACK_TIMEOUTS \ 1375 GG82563_REG(194, 20) /* Acknowledge Timeouts */ 1376#define GG82563_PHY_ADV_ABILITY \ 1377 GG82563_REG(194, 21) /* Advertised Ability */ 1378#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 1379 GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 1380#define GG82563_PHY_ADV_NEXT_PAGE \ 1381 GG82563_REG(194, 24) /* Advertised Next Page */ 1382#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 1383 GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 1384#define GG82563_PHY_KMRN_MISC \ 1385 GG82563_REG(194, 26) /* Misc. */ 1386 1387/* MDI Control */ 1388#define E1000_MDIC_DATA_MASK 0x0000FFFF 1389#define E1000_MDIC_REG_MASK 0x001F0000 1390#define E1000_MDIC_REG_SHIFT 16 1391#define E1000_MDIC_PHY_MASK 0x03E00000 1392#define E1000_MDIC_PHY_SHIFT 21 1393#define E1000_MDIC_OP_WRITE 0x04000000 1394#define E1000_MDIC_OP_READ 0x08000000 1395#define E1000_MDIC_READY 0x10000000 1396#define E1000_MDIC_INT_EN 0x20000000 1397#define E1000_MDIC_ERROR 0x40000000 1398 1399/* SerDes Control */ 1400#define E1000_GEN_CTL_READY 0x80000000 1401#define E1000_GEN_CTL_ADDRESS_SHIFT 8 1402#define E1000_GEN_POLL_TIMEOUT 640 1403#endif 1404