e1000_82575.h revision 200243
1176667Sjfv/****************************************************************************** 2176667Sjfv 3190872Sjfv Copyright (c) 2001-2009, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82575.h 200243 2009-12-08 01:07:44Z jfv $*/ 34176667Sjfv 35176667Sjfv#ifndef _E1000_82575_H_ 36176667Sjfv#define _E1000_82575_H_ 37176667Sjfv 38181027Sjfv#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 39181027Sjfv (ID_LED_DEF1_DEF2 << 8) | \ 40181027Sjfv (ID_LED_DEF1_DEF2 << 4) | \ 41181027Sjfv (ID_LED_OFF1_ON2)) 42176667Sjfv/* 43176667Sjfv * Receive Address Register Count 44176667Sjfv * Number of high/low register pairs in the RAR. The RAR (Receive Address 45176667Sjfv * Registers) holds the directed and multicast addresses that we monitor. 46176667Sjfv * These entries are also used for MAC-based filtering. 47176667Sjfv */ 48181027Sjfv/* 49181027Sjfv * For 82576, there are an additional set of RARs that begin at an offset 50181027Sjfv * separate from the first set of RARs. 51181027Sjfv */ 52176667Sjfv#define E1000_RAR_ENTRIES_82575 16 53181027Sjfv#define E1000_RAR_ENTRIES_82576 24 54200243Sjfv#define E1000_RAR_ENTRIES_82580 24 55200243Sjfv#define E1000_SW_SYNCH_MB 0x00000100 56200243Sjfv#define E1000_STAT_DEV_RST_SET 0x00100000 57200243Sjfv#define E1000_CTRL_DEV_RST 0x20000000 58176667Sjfv 59176667Sjfv#ifdef E1000_BIT_FIELDS 60176667Sjfvstruct e1000_adv_data_desc { 61200243Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 62176667Sjfv union { 63176667Sjfv u32 data; 64176667Sjfv struct { 65176667Sjfv u32 datalen :16; /* Data buffer length */ 66176667Sjfv u32 rsvd :4; 67176667Sjfv u32 dtyp :4; /* Descriptor type */ 68176667Sjfv u32 dcmd :8; /* Descriptor command */ 69176667Sjfv } config; 70176667Sjfv } lower; 71176667Sjfv union { 72176667Sjfv u32 data; 73176667Sjfv struct { 74176667Sjfv u32 status :4; /* Descriptor status */ 75176667Sjfv u32 idx :4; 76176667Sjfv u32 popts :6; /* Packet Options */ 77176667Sjfv u32 paylen :18; /* Payload length */ 78176667Sjfv } options; 79176667Sjfv } upper; 80176667Sjfv}; 81176667Sjfv 82176667Sjfv#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 83176667Sjfv#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 84176667Sjfv#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 85176667Sjfv#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 86176667Sjfv#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 87176667Sjfv#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 88176667Sjfv#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 89176667Sjfv#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 90176667Sjfv#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 91176667Sjfv#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 92176667Sjfv#define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 93176667Sjfv#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 94176667Sjfv#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 95176667Sjfv/* Extended Device Control */ 96176667Sjfv#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 97176667Sjfv 98176667Sjfvstruct e1000_adv_context_desc { 99176667Sjfv union { 100176667Sjfv u32 ip_config; 101176667Sjfv struct { 102176667Sjfv u32 iplen :9; 103176667Sjfv u32 maclen :7; 104176667Sjfv u32 vlan_tag :16; 105176667Sjfv } fields; 106176667Sjfv } ip_setup; 107176667Sjfv u32 seq_num; 108176667Sjfv union { 109176667Sjfv u64 l4_config; 110176667Sjfv struct { 111176667Sjfv u32 mkrloc :9; 112176667Sjfv u32 tucmd :11; 113176667Sjfv u32 dtyp :4; 114176667Sjfv u32 adv :8; 115176667Sjfv u32 rsvd :4; 116176667Sjfv u32 idx :4; 117176667Sjfv u32 l4len :8; 118176667Sjfv u32 mss :16; 119176667Sjfv } fields; 120176667Sjfv } l4_setup; 121176667Sjfv}; 122176667Sjfv#endif 123176667Sjfv 124176667Sjfv/* SRRCTL bit definitions */ 125176667Sjfv#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 126176667Sjfv#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 127176667Sjfv#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 128176667Sjfv#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 129176667Sjfv#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 130176667Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 131176667Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 132176667Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 133176667Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 134176667Sjfv#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 135200243Sjfv#define E1000_SRRCTL_TIMESTAMP 0x40000000 136190872Sjfv#define E1000_SRRCTL_DROP_EN 0x80000000 137176667Sjfv 138176667Sjfv#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 139176667Sjfv#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 140176667Sjfv 141176667Sjfv#define E1000_TX_HEAD_WB_ENABLE 0x1 142176667Sjfv#define E1000_TX_SEQNUM_WB_ENABLE 0x2 143176667Sjfv 144176667Sjfv#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 145181027Sjfv#define E1000_MRQC_ENABLE_VMDQ 0x00000003 146190872Sjfv#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 147176667Sjfv#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 148176667Sjfv#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 149176667Sjfv#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 150200243Sjfv#define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 151176667Sjfv 152181027Sjfv#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 153181027Sjfv#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) 154181027Sjfv#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 155181027Sjfv#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 156181027Sjfv#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 157181027Sjfv 158176667Sjfv#define E1000_EICR_TX_QUEUE ( \ 159176667Sjfv E1000_EICR_TX_QUEUE0 | \ 160176667Sjfv E1000_EICR_TX_QUEUE1 | \ 161176667Sjfv E1000_EICR_TX_QUEUE2 | \ 162176667Sjfv E1000_EICR_TX_QUEUE3) 163176667Sjfv 164176667Sjfv#define E1000_EICR_RX_QUEUE ( \ 165176667Sjfv E1000_EICR_RX_QUEUE0 | \ 166176667Sjfv E1000_EICR_RX_QUEUE1 | \ 167176667Sjfv E1000_EICR_RX_QUEUE2 | \ 168176667Sjfv E1000_EICR_RX_QUEUE3) 169176667Sjfv 170176667Sjfv#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 171176667Sjfv#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 172176667Sjfv 173176667Sjfv#define EIMS_ENABLE_MASK ( \ 174176667Sjfv E1000_EIMS_RX_QUEUE | \ 175176667Sjfv E1000_EIMS_TX_QUEUE | \ 176176667Sjfv E1000_EIMS_TCP_TIMER | \ 177176667Sjfv E1000_EIMS_OTHER) 178176667Sjfv 179176667Sjfv/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 180176667Sjfv#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 181176667Sjfv#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 182176667Sjfv#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 183176667Sjfv#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 184176667Sjfv#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 185176667Sjfv#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 186176667Sjfv#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 187176667Sjfv#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 188176667Sjfv#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 189176667Sjfv#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 190176667Sjfv 191176667Sjfv/* Receive Descriptor - Advanced */ 192176667Sjfvunion e1000_adv_rx_desc { 193176667Sjfv struct { 194200243Sjfv __le64 pkt_addr; /* Packet buffer address */ 195200243Sjfv __le64 hdr_addr; /* Header buffer address */ 196176667Sjfv } read; 197176667Sjfv struct { 198176667Sjfv struct { 199176667Sjfv union { 200200243Sjfv __le32 data; 201176667Sjfv struct { 202200243Sjfv __le16 pkt_info; /*RSS type, Pkt type*/ 203200243Sjfv __le16 hdr_info; /* Split Header, 204200243Sjfv * header buffer len*/ 205176667Sjfv } hs_rss; 206176667Sjfv } lo_dword; 207176667Sjfv union { 208200243Sjfv __le32 rss; /* RSS Hash */ 209176667Sjfv struct { 210200243Sjfv __le16 ip_id; /* IP id */ 211200243Sjfv __le16 csum; /* Packet Checksum */ 212176667Sjfv } csum_ip; 213176667Sjfv } hi_dword; 214176667Sjfv } lower; 215176667Sjfv struct { 216200243Sjfv __le32 status_error; /* ext status/error */ 217200243Sjfv __le16 length; /* Packet length */ 218200243Sjfv __le16 vlan; /* VLAN tag */ 219176667Sjfv } upper; 220176667Sjfv } wb; /* writeback */ 221176667Sjfv}; 222176667Sjfv 223194865Sjfv#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 224176667Sjfv#define E1000_RXDADV_RSSTYPE_SHIFT 12 225176667Sjfv#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 226176667Sjfv#define E1000_RXDADV_HDRBUFLEN_SHIFT 5 227176667Sjfv#define E1000_RXDADV_SPLITHEADER_EN 0x00001000 228176667Sjfv#define E1000_RXDADV_SPH 0x8000 229200243Sjfv#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 230200243Sjfv#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 231181027Sjfv#define E1000_RXDADV_ERR_HBO 0x00800000 232176667Sjfv 233176667Sjfv/* RSS Hash results */ 234176667Sjfv#define E1000_RXDADV_RSSTYPE_NONE 0x00000000 235176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 236176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 237176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 238176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 239176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 240176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 241176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 242176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 243176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 244176667Sjfv 245176667Sjfv/* RSS Packet Types as indicated in the receive descriptor */ 246176667Sjfv#define E1000_RXDADV_PKTTYPE_NONE 0x00000000 247176667Sjfv#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 248176667Sjfv#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 249176667Sjfv#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 250176667Sjfv#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 251176667Sjfv#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 252176667Sjfv#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 253176667Sjfv#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 254176667Sjfv#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 255176667Sjfv 256181027Sjfv#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 257181027Sjfv#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 258181027Sjfv#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 259181027Sjfv#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 260181027Sjfv#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 261181027Sjfv#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 262181027Sjfv 263181027Sjfv/* LinkSec results */ 264181027Sjfv/* Security Processing bit Indication */ 265181027Sjfv#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 266181027Sjfv#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 267181027Sjfv#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 268181027Sjfv#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 269181027Sjfv#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 270181027Sjfv 271181027Sjfv#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 272181027Sjfv#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 273181027Sjfv#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 274181027Sjfv#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 275181027Sjfv#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 276181027Sjfv 277176667Sjfv/* Transmit Descriptor - Advanced */ 278176667Sjfvunion e1000_adv_tx_desc { 279176667Sjfv struct { 280200243Sjfv __le64 buffer_addr; /* Address of descriptor's data buf */ 281200243Sjfv __le32 cmd_type_len; 282200243Sjfv __le32 olinfo_status; 283176667Sjfv } read; 284176667Sjfv struct { 285200243Sjfv __le64 rsvd; /* Reserved */ 286200243Sjfv __le32 nxtseq_seed; 287200243Sjfv __le32 status; 288176667Sjfv } wb; 289176667Sjfv}; 290176667Sjfv 291176667Sjfv/* Adv Transmit Descriptor Config Masks */ 292176667Sjfv#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 293176667Sjfv#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 294176667Sjfv#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 295176667Sjfv#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 296176667Sjfv#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 297176667Sjfv#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 298176667Sjfv#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 299176667Sjfv#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 300176667Sjfv#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 301181027Sjfv#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */ 302176667Sjfv#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 303176667Sjfv#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ 304176667Sjfv#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 305176667Sjfv#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 306176667Sjfv#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 307176667Sjfv#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 308176667Sjfv#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ 309176667Sjfv#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 310176667Sjfv#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 311176667Sjfv 312176667Sjfv/* Context descriptors */ 313176667Sjfvstruct e1000_adv_tx_context_desc { 314200243Sjfv __le32 vlan_macip_lens; 315200243Sjfv __le32 seqnum_seed; 316200243Sjfv __le32 type_tucmd_mlhl; 317200243Sjfv __le32 mss_l4len_idx; 318176667Sjfv}; 319176667Sjfv 320176667Sjfv#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 321176667Sjfv#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 322176667Sjfv#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 323176667Sjfv#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 324176667Sjfv#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 325176667Sjfv#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 326190872Sjfv#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 327176667Sjfv#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 328176667Sjfv/* IPSec Encrypt Enable for ESP */ 329176667Sjfv#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 330176667Sjfv#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ 331176667Sjfv#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 332176667Sjfv#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 333176667Sjfv/* Adv ctxt IPSec SA IDX mask */ 334176667Sjfv#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 335176667Sjfv/* Adv ctxt IPSec ESP len mask */ 336176667Sjfv#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 337176667Sjfv 338176667Sjfv/* Additional Transmit Descriptor Control definitions */ 339176667Sjfv#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 340176667Sjfv#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 341176667Sjfv/* Tx Queue Arbitration Priority 0=low, 1=high */ 342176667Sjfv#define E1000_TXDCTL_PRIORITY 0x08000000 343176667Sjfv 344176667Sjfv/* Additional Receive Descriptor Control definitions */ 345176667Sjfv#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 346176667Sjfv#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 347176667Sjfv 348176667Sjfv/* Direct Cache Access (DCA) definitions */ 349176667Sjfv#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 350176667Sjfv#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 351176667Sjfv 352176667Sjfv#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 353176667Sjfv#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 354176667Sjfv 355176667Sjfv#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 356176667Sjfv#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 357176667Sjfv#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 358176667Sjfv#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 359176667Sjfv 360176667Sjfv#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 361176667Sjfv#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 362176667Sjfv#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 363176667Sjfv 364181027Sjfv#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 365181027Sjfv#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 366185353Sjfv#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 367185353Sjfv#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 368176667Sjfv 369181027Sjfv/* Additional interrupt register bit definitions */ 370181027Sjfv#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 371181027Sjfv#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 372181027Sjfv#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 373176667Sjfv 374181027Sjfv/* ETQF register bit definitions */ 375181027Sjfv#define E1000_ETQF_FILTER_ENABLE (1 << 26) 376181027Sjfv#define E1000_ETQF_IMM_INT (1 << 29) 377185353Sjfv#define E1000_ETQF_1588 (1 << 30) 378185353Sjfv#define E1000_ETQF_QUEUE_ENABLE (1 << 31) 379181027Sjfv/* 380181027Sjfv * ETQF filter list: one static filter per filter consumer. This is 381181027Sjfv * to avoid filter collisions later. Add new filters 382181027Sjfv * here!! 383181027Sjfv * 384181027Sjfv * Current filters: 385181027Sjfv * EAPOL 802.1x (0x888e): Filter 0 386181027Sjfv */ 387181027Sjfv#define E1000_ETQF_FILTER_EAPOL 0 388181027Sjfv 389200243Sjfv#define E1000_FTQF_VF_BP 0x00008000 390200243Sjfv#define E1000_FTQF_1588_TIME_STAMP 0x08000000 391200243Sjfv#define E1000_FTQF_MASK 0xF0000000 392200243Sjfv#define E1000_FTQF_MASK_PROTO_BP 0x10000000 393200243Sjfv#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 394200243Sjfv#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 395200243Sjfv#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 396200243Sjfv 397181027Sjfv#define E1000_NVM_APME_82575 0x0400 398181027Sjfv#define MAX_NUM_VFS 8 399181027Sjfv 400181027Sjfv#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ 401181027Sjfv#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ 402181027Sjfv#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 403190872Sjfv#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 404190872Sjfv#define E1000_DTXSWC_LLE_SHIFT 16 405181027Sjfv#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 406181027Sjfv 407181027Sjfv/* Easy defines for setting default pool, would normally be left a zero */ 408181027Sjfv#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 409181027Sjfv#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 410181027Sjfv 411181027Sjfv/* Other useful VMD_CTL register defines */ 412181027Sjfv#define E1000_VT_CTL_IGNORE_MAC (1 << 28) 413181027Sjfv#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 414181027Sjfv#define E1000_VT_CTL_VM_REPL_EN (1 << 30) 415181027Sjfv 416181027Sjfv/* Per VM Offload register setup */ 417190872Sjfv#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 418181027Sjfv#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 419190872Sjfv#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 420181027Sjfv#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 421190872Sjfv#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 422190872Sjfv#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 423181027Sjfv#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 424181027Sjfv#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 425181027Sjfv#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 426190872Sjfv#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 427181027Sjfv 428190872Sjfv#define E1000_VLVF_ARRAY_SIZE 32 429190872Sjfv#define E1000_VLVF_VLANID_MASK 0x00000FFF 430190872Sjfv#define E1000_VLVF_POOLSEL_SHIFT 12 431190872Sjfv#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 432190872Sjfv#define E1000_VLVF_LVLAN 0x00100000 433190872Sjfv#define E1000_VLVF_VLANID_ENABLE 0x80000000 434181027Sjfv 435200243Sjfv#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 436200243Sjfv#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 437200243Sjfv 438190872Sjfv#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 439181027Sjfv 440190872Sjfv#define E1000_IOVCTL 0x05BBC 441190872Sjfv#define E1000_IOVCTL_REUSE_VFQ 0x00000001 442181027Sjfv 443194865Sjfv#define E1000_RPLOLR_STRVLAN 0x40000000 444194865Sjfv#define E1000_RPLOLR_STRCRC 0x80000000 445194865Sjfv 446200243Sjfv#define E1000_DTXCTL_8023LL 0x0004 447200243Sjfv#define E1000_DTXCTL_VLAN_ADDED 0x0008 448200243Sjfv#define E1000_DTXCTL_OOS_ENABLE 0x0010 449200243Sjfv#define E1000_DTXCTL_MDP_EN 0x0020 450200243Sjfv#define E1000_DTXCTL_SPOOF_INT 0x0040 451200243Sjfv 452185353Sjfv#define ALL_QUEUES 0xFFFF 453185353Sjfv 454200243Sjfv/* RX packet buffer size defines */ 455200243Sjfv#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 456194865Sjfvvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 457194865Sjfvvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 458200243Sjfvu16 e1000_rxpbs_adjust_82580(u32 data); 459200243Sjfvs32 e1000_erfuse_check_82580(struct e1000_hw *); 460190872Sjfv#endif /* _E1000_82575_H_ */ 461