1176667Sjfv/****************************************************************************** 2176667Sjfv 3248292Sjfv Copyright (c) 2001-2013, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD$*/ 34176667Sjfv 35176667Sjfv#ifndef _E1000_82575_H_ 36176667Sjfv#define _E1000_82575_H_ 37176667Sjfv 38235527Sjfv#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 39235527Sjfv (ID_LED_DEF1_DEF2 << 8) | \ 40235527Sjfv (ID_LED_DEF1_DEF2 << 4) | \ 41235527Sjfv (ID_LED_OFF1_ON2)) 42176667Sjfv/* 43176667Sjfv * Receive Address Register Count 44176667Sjfv * Number of high/low register pairs in the RAR. The RAR (Receive Address 45176667Sjfv * Registers) holds the directed and multicast addresses that we monitor. 46176667Sjfv * These entries are also used for MAC-based filtering. 47176667Sjfv */ 48181027Sjfv/* 49181027Sjfv * For 82576, there are an additional set of RARs that begin at an offset 50181027Sjfv * separate from the first set of RARs. 51181027Sjfv */ 52235527Sjfv#define E1000_RAR_ENTRIES_82575 16 53235527Sjfv#define E1000_RAR_ENTRIES_82576 24 54235527Sjfv#define E1000_RAR_ENTRIES_82580 24 55235527Sjfv#define E1000_RAR_ENTRIES_I350 32 56235527Sjfv#define E1000_SW_SYNCH_MB 0x00000100 57235527Sjfv#define E1000_STAT_DEV_RST_SET 0x00100000 58235527Sjfv#define E1000_CTRL_DEV_RST 0x20000000 59176667Sjfv 60176667Sjfv#ifdef E1000_BIT_FIELDS 61176667Sjfvstruct e1000_adv_data_desc { 62200243Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 63176667Sjfv union { 64176667Sjfv u32 data; 65176667Sjfv struct { 66235527Sjfv u32 datalen:16; /* Data buffer length */ 67235527Sjfv u32 rsvd:4; 68235527Sjfv u32 dtyp:4; /* Descriptor type */ 69235527Sjfv u32 dcmd:8; /* Descriptor command */ 70176667Sjfv } config; 71176667Sjfv } lower; 72176667Sjfv union { 73176667Sjfv u32 data; 74176667Sjfv struct { 75235527Sjfv u32 status:4; /* Descriptor status */ 76235527Sjfv u32 idx:4; 77235527Sjfv u32 popts:6; /* Packet Options */ 78235527Sjfv u32 paylen:18; /* Payload length */ 79176667Sjfv } options; 80176667Sjfv } upper; 81176667Sjfv}; 82176667Sjfv 83235527Sjfv#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 84235527Sjfv#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 85235527Sjfv#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 86235527Sjfv#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 87235527Sjfv#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 88235527Sjfv#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 89235527Sjfv#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 90235527Sjfv#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 91235527Sjfv#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 92235527Sjfv#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 93235527Sjfv#define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 94235527Sjfv#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 95235527Sjfv#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 96176667Sjfv/* Extended Device Control */ 97235527Sjfv#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 98176667Sjfv 99176667Sjfvstruct e1000_adv_context_desc { 100176667Sjfv union { 101176667Sjfv u32 ip_config; 102176667Sjfv struct { 103235527Sjfv u32 iplen:9; 104235527Sjfv u32 maclen:7; 105235527Sjfv u32 vlan_tag:16; 106176667Sjfv } fields; 107176667Sjfv } ip_setup; 108176667Sjfv u32 seq_num; 109176667Sjfv union { 110176667Sjfv u64 l4_config; 111176667Sjfv struct { 112235527Sjfv u32 mkrloc:9; 113235527Sjfv u32 tucmd:11; 114235527Sjfv u32 dtyp:4; 115235527Sjfv u32 adv:8; 116235527Sjfv u32 rsvd:4; 117235527Sjfv u32 idx:4; 118235527Sjfv u32 l4len:8; 119235527Sjfv u32 mss:16; 120176667Sjfv } fields; 121176667Sjfv } l4_setup; 122176667Sjfv}; 123176667Sjfv#endif 124176667Sjfv 125176667Sjfv/* SRRCTL bit definitions */ 126235527Sjfv#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 127235527Sjfv#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 128235527Sjfv#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 129235527Sjfv#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 130235527Sjfv#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 131235527Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 132235527Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 133235527Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 134176667Sjfv#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 135235527Sjfv#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 136235527Sjfv#define E1000_SRRCTL_TIMESTAMP 0x40000000 137235527Sjfv#define E1000_SRRCTL_DROP_EN 0x80000000 138176667Sjfv 139235527Sjfv#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 140235527Sjfv#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 141176667Sjfv 142235527Sjfv#define E1000_TX_HEAD_WB_ENABLE 0x1 143235527Sjfv#define E1000_TX_SEQNUM_WB_ENABLE 0x2 144176667Sjfv 145235527Sjfv#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 146235527Sjfv#define E1000_MRQC_ENABLE_VMDQ 0x00000003 147235527Sjfv#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 148235527Sjfv#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 149235527Sjfv#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 150235527Sjfv#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 151235527Sjfv#define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 152176667Sjfv 153235527Sjfv#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 154235527Sjfv#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ 155235527Sjfv E1000_VMRCTL_MIRROR_PORT_SHIFT) 156235527Sjfv#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 157235527Sjfv#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 158235527Sjfv#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 159181027Sjfv 160176667Sjfv#define E1000_EICR_TX_QUEUE ( \ 161235527Sjfv E1000_EICR_TX_QUEUE0 | \ 162235527Sjfv E1000_EICR_TX_QUEUE1 | \ 163235527Sjfv E1000_EICR_TX_QUEUE2 | \ 164235527Sjfv E1000_EICR_TX_QUEUE3) 165176667Sjfv 166176667Sjfv#define E1000_EICR_RX_QUEUE ( \ 167235527Sjfv E1000_EICR_RX_QUEUE0 | \ 168235527Sjfv E1000_EICR_RX_QUEUE1 | \ 169235527Sjfv E1000_EICR_RX_QUEUE2 | \ 170235527Sjfv E1000_EICR_RX_QUEUE3) 171176667Sjfv 172235527Sjfv#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 173235527Sjfv#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 174176667Sjfv 175176667Sjfv#define EIMS_ENABLE_MASK ( \ 176235527Sjfv E1000_EIMS_RX_QUEUE | \ 177235527Sjfv E1000_EIMS_TX_QUEUE | \ 178235527Sjfv E1000_EIMS_TCP_TIMER | \ 179235527Sjfv E1000_EIMS_OTHER) 180176667Sjfv 181176667Sjfv/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 182235527Sjfv#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 183235527Sjfv#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 184235527Sjfv#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 185235527Sjfv#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 186235527Sjfv#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 187235527Sjfv#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 188235527Sjfv#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 189235527Sjfv#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 190235527Sjfv#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 191235527Sjfv#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 192176667Sjfv 193176667Sjfv/* Receive Descriptor - Advanced */ 194176667Sjfvunion e1000_adv_rx_desc { 195176667Sjfv struct { 196235527Sjfv __le64 pkt_addr; /* Packet buffer address */ 197235527Sjfv __le64 hdr_addr; /* Header buffer address */ 198176667Sjfv } read; 199176667Sjfv struct { 200176667Sjfv struct { 201176667Sjfv union { 202200243Sjfv __le32 data; 203176667Sjfv struct { 204200243Sjfv __le16 pkt_info; /*RSS type, Pkt type*/ 205218530Sjfv /* Split Header, header buffer len */ 206218530Sjfv __le16 hdr_info; 207176667Sjfv } hs_rss; 208176667Sjfv } lo_dword; 209176667Sjfv union { 210235527Sjfv __le32 rss; /* RSS Hash */ 211176667Sjfv struct { 212235527Sjfv __le16 ip_id; /* IP id */ 213235527Sjfv __le16 csum; /* Packet Checksum */ 214176667Sjfv } csum_ip; 215176667Sjfv } hi_dword; 216176667Sjfv } lower; 217176667Sjfv struct { 218235527Sjfv __le32 status_error; /* ext status/error */ 219235527Sjfv __le16 length; /* Packet length */ 220235527Sjfv __le16 vlan; /* VLAN tag */ 221176667Sjfv } upper; 222176667Sjfv } wb; /* writeback */ 223176667Sjfv}; 224176667Sjfv 225235527Sjfv#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 226235527Sjfv#define E1000_RXDADV_RSSTYPE_SHIFT 12 227235527Sjfv#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 228235527Sjfv#define E1000_RXDADV_HDRBUFLEN_SHIFT 5 229235527Sjfv#define E1000_RXDADV_SPLITHEADER_EN 0x00001000 230235527Sjfv#define E1000_RXDADV_SPH 0x8000 231235527Sjfv#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 232235527Sjfv#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 233235527Sjfv#define E1000_RXDADV_ERR_HBO 0x00800000 234176667Sjfv 235176667Sjfv/* RSS Hash results */ 236235527Sjfv#define E1000_RXDADV_RSSTYPE_NONE 0x00000000 237235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 238235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 239235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 240235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 241235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 242176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 243235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 244235527Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 245176667Sjfv#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 246176667Sjfv 247176667Sjfv/* RSS Packet Types as indicated in the receive descriptor */ 248235527Sjfv#define E1000_RXDADV_PKTTYPE_NONE 0x00000000 249235527Sjfv#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 250235527Sjfv#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 251235527Sjfv#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 252235527Sjfv#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 253235527Sjfv#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 254235527Sjfv#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 255235527Sjfv#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 256235527Sjfv#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 257176667Sjfv 258235527Sjfv#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 259235527Sjfv#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 260235527Sjfv#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 261235527Sjfv#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 262235527Sjfv#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 263235527Sjfv#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 264181027Sjfv 265181027Sjfv/* LinkSec results */ 266181027Sjfv/* Security Processing bit Indication */ 267235527Sjfv#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 268235527Sjfv#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 269235527Sjfv#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 270235527Sjfv#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 271235527Sjfv#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 272181027Sjfv 273235527Sjfv#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 274235527Sjfv#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 275235527Sjfv#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 276235527Sjfv#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 277235527Sjfv#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 278181027Sjfv 279176667Sjfv/* Transmit Descriptor - Advanced */ 280176667Sjfvunion e1000_adv_tx_desc { 281176667Sjfv struct { 282200243Sjfv __le64 buffer_addr; /* Address of descriptor's data buf */ 283200243Sjfv __le32 cmd_type_len; 284200243Sjfv __le32 olinfo_status; 285176667Sjfv } read; 286176667Sjfv struct { 287200243Sjfv __le64 rsvd; /* Reserved */ 288200243Sjfv __le32 nxtseq_seed; 289200243Sjfv __le32 status; 290176667Sjfv } wb; 291176667Sjfv}; 292176667Sjfv 293176667Sjfv/* Adv Transmit Descriptor Config Masks */ 294235527Sjfv#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 295235527Sjfv#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 296235527Sjfv#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 297235527Sjfv#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 298235527Sjfv#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 299235527Sjfv#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 300235527Sjfv#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 301235527Sjfv#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 302235527Sjfv#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 303235527Sjfv#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 304235527Sjfv#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 305235527Sjfv#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 306235527Sjfv#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 307235527Sjfv#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 308235527Sjfv#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 309235527Sjfv#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 310235527Sjfv/* 1st & Last TSO-full iSCSI PDU*/ 311235527Sjfv#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 312235527Sjfv#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 313235527Sjfv#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 314176667Sjfv 315176667Sjfv/* Context descriptors */ 316176667Sjfvstruct e1000_adv_tx_context_desc { 317200243Sjfv __le32 vlan_macip_lens; 318200243Sjfv __le32 seqnum_seed; 319200243Sjfv __le32 type_tucmd_mlhl; 320200243Sjfv __le32 mss_l4len_idx; 321176667Sjfv}; 322176667Sjfv 323235527Sjfv#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 324235527Sjfv#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 325235527Sjfv#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 326235527Sjfv#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 327235527Sjfv#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 328235527Sjfv#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 329235527Sjfv#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 330235527Sjfv#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 331176667Sjfv/* IPSec Encrypt Enable for ESP */ 332235527Sjfv#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 333235527Sjfv/* Req requires Markers and CRC */ 334235527Sjfv#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 335235527Sjfv#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 336235527Sjfv#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 337176667Sjfv/* Adv ctxt IPSec SA IDX mask */ 338235527Sjfv#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 339176667Sjfv/* Adv ctxt IPSec ESP len mask */ 340235527Sjfv#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 341176667Sjfv 342176667Sjfv/* Additional Transmit Descriptor Control definitions */ 343235527Sjfv#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 344235527Sjfv#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ 345176667Sjfv/* Tx Queue Arbitration Priority 0=low, 1=high */ 346235527Sjfv#define E1000_TXDCTL_PRIORITY 0x08000000 347176667Sjfv 348176667Sjfv/* Additional Receive Descriptor Control definitions */ 349235527Sjfv#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 350235527Sjfv#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ 351176667Sjfv 352176667Sjfv/* Direct Cache Access (DCA) definitions */ 353235527Sjfv#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 354235527Sjfv#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 355176667Sjfv 356235527Sjfv#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 357235527Sjfv#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 358176667Sjfv 359235527Sjfv#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 360235527Sjfv#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 361235527Sjfv#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ 362235527Sjfv#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ 363248292Sjfv#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ 364176667Sjfv 365235527Sjfv#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 366235527Sjfv#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 367248292Sjfv#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 368235527Sjfv#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 369248292Sjfv#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 370176667Sjfv 371235527Sjfv#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 372235527Sjfv#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 373235527Sjfv#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 374235527Sjfv#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 375176667Sjfv 376181027Sjfv/* Additional interrupt register bit definitions */ 377235527Sjfv#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 378235527Sjfv#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 379235527Sjfv#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 380176667Sjfv 381181027Sjfv/* ETQF register bit definitions */ 382235527Sjfv#define E1000_ETQF_FILTER_ENABLE (1 << 26) 383235527Sjfv#define E1000_ETQF_IMM_INT (1 << 29) 384235527Sjfv#define E1000_ETQF_1588 (1 << 30) 385235527Sjfv#define E1000_ETQF_QUEUE_ENABLE (1 << 31) 386181027Sjfv/* 387181027Sjfv * ETQF filter list: one static filter per filter consumer. This is 388181027Sjfv * to avoid filter collisions later. Add new filters 389181027Sjfv * here!! 390181027Sjfv * 391181027Sjfv * Current filters: 392181027Sjfv * EAPOL 802.1x (0x888e): Filter 0 393181027Sjfv */ 394235527Sjfv#define E1000_ETQF_FILTER_EAPOL 0 395181027Sjfv 396235527Sjfv#define E1000_FTQF_VF_BP 0x00008000 397235527Sjfv#define E1000_FTQF_1588_TIME_STAMP 0x08000000 398235527Sjfv#define E1000_FTQF_MASK 0xF0000000 399235527Sjfv#define E1000_FTQF_MASK_PROTO_BP 0x10000000 400235527Sjfv#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 401235527Sjfv#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 402235527Sjfv#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 403200243Sjfv 404235527Sjfv#define E1000_NVM_APME_82575 0x0400 405235527Sjfv#define MAX_NUM_VFS 7 406181027Sjfv 407235527Sjfv#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ 408235527Sjfv#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ 409235527Sjfv#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 410235527Sjfv#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 411235527Sjfv#define E1000_DTXSWC_LLE_SHIFT 16 412235527Sjfv#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 413181027Sjfv 414181027Sjfv/* Easy defines for setting default pool, would normally be left a zero */ 415235527Sjfv#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 416235527Sjfv#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 417181027Sjfv 418181027Sjfv/* Other useful VMD_CTL register defines */ 419235527Sjfv#define E1000_VT_CTL_IGNORE_MAC (1 << 28) 420235527Sjfv#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 421235527Sjfv#define E1000_VT_CTL_VM_REPL_EN (1 << 30) 422181027Sjfv 423181027Sjfv/* Per VM Offload register setup */ 424235527Sjfv#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 425235527Sjfv#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 426235527Sjfv#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 427235527Sjfv#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 428235527Sjfv#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 429235527Sjfv#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 430235527Sjfv#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 431235527Sjfv#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 432235527Sjfv#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 433235527Sjfv#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 434181027Sjfv 435235527Sjfv#define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ 436235527Sjfv#define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ 437235527Sjfv#define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ 438235527Sjfv#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 439235527Sjfv#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 440205869Sjfv 441235527Sjfv#define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ 442235527Sjfv#define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ 443218530Sjfv 444235527Sjfv#define E1000_VLVF_ARRAY_SIZE 32 445235527Sjfv#define E1000_VLVF_VLANID_MASK 0x00000FFF 446235527Sjfv#define E1000_VLVF_POOLSEL_SHIFT 12 447235527Sjfv#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 448235527Sjfv#define E1000_VLVF_LVLAN 0x00100000 449235527Sjfv#define E1000_VLVF_VLANID_ENABLE 0x80000000 450181027Sjfv 451235527Sjfv#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 452235527Sjfv#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 453200243Sjfv 454235527Sjfv#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 455181027Sjfv 456235527Sjfv#define E1000_IOVCTL 0x05BBC 457235527Sjfv#define E1000_IOVCTL_REUSE_VFQ 0x00000001 458181027Sjfv 459235527Sjfv#define E1000_RPLOLR_STRVLAN 0x40000000 460235527Sjfv#define E1000_RPLOLR_STRCRC 0x80000000 461194865Sjfv 462235527Sjfv#define E1000_TCTL_EXT_COLD 0x000FFC00 463235527Sjfv#define E1000_TCTL_EXT_COLD_SHIFT 10 464203049Sjfv 465235527Sjfv#define E1000_DTXCTL_8023LL 0x0004 466235527Sjfv#define E1000_DTXCTL_VLAN_ADDED 0x0008 467235527Sjfv#define E1000_DTXCTL_OOS_ENABLE 0x0010 468235527Sjfv#define E1000_DTXCTL_MDP_EN 0x0020 469235527Sjfv#define E1000_DTXCTL_SPOOF_INT 0x0040 470200243Sjfv 471235527Sjfv#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 472185353Sjfv 473235527Sjfv#define ALL_QUEUES 0xFFFF 474235527Sjfv 475218530Sjfv/* Rx packet buffer size defines */ 476235527Sjfv#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 477194865Sjfvvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 478213234Sjfvvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); 479194865Sjfvvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 480219753Sjfvs32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 481219753Sjfv 482209616Sjfvenum e1000_promisc_type { 483209616Sjfv e1000_promisc_disabled = 0, /* all promisc modes disabled */ 484209616Sjfv e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 485209616Sjfv e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 486209616Sjfv e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 487209616Sjfv e1000_num_promisc_types 488209616Sjfv}; 489209616Sjfv 490209616Sjfvvoid e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 491209616Sjfvvoid e1000_rlpml_set_vf(struct e1000_hw *, u16); 492209616Sjfvs32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type); 493200243Sjfvu16 e1000_rxpbs_adjust_82580(u32 data); 494218530Sjfvs32 e1000_set_eee_i350(struct e1000_hw *); 495235527Sjfv 496235527Sjfv/* I2C SDA and SCL timing parameters for standard mode */ 497235527Sjfv#define E1000_I2C_T_HD_STA 4 498235527Sjfv#define E1000_I2C_T_LOW 5 499235527Sjfv#define E1000_I2C_T_HIGH 4 500235527Sjfv#define E1000_I2C_T_SU_STA 5 501235527Sjfv#define E1000_I2C_T_HD_DATA 5 502235527Sjfv#define E1000_I2C_T_SU_DATA 1 503235527Sjfv#define E1000_I2C_T_RISE 1 504235527Sjfv#define E1000_I2C_T_FALL 1 505235527Sjfv#define E1000_I2C_T_SU_STO 4 506235527Sjfv#define E1000_I2C_T_BUF 5 507235527Sjfv 508235527Sjfvs32 e1000_set_i2c_bb(struct e1000_hw *hw); 509235527Sjfvs32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 510235527Sjfv u8 dev_addr, u8 *data); 511235527Sjfvs32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 512235527Sjfv u8 dev_addr, u8 data); 513235527Sjfvvoid e1000_i2c_bus_clear(struct e1000_hw *hw); 514190872Sjfv#endif /* _E1000_82575_H_ */ 515