e1000_82575.c revision 218909
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 218909 2011-02-21 09:01:34Z brucec $*/ 34 35/* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82575GB Gigabit Network Connection 40 * 82576 Gigabit Network Connection 41 * 82576 Quad Port Gigabit Mezzanine Adapter 42 */ 43 44#include "e1000_api.h" 45 46static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 48static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50static void e1000_release_phy_82575(struct e1000_hw *hw); 51static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 52static void e1000_release_nvm_82575(struct e1000_hw *hw); 53static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56 u16 *duplex); 57static s32 e1000_init_hw_82575(struct e1000_hw *hw); 58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 60 u16 *data); 61static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 62static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 64 u32 offset, u16 *data); 65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66 u32 offset, u16 data); 67static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 68 bool active); 69static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 70 bool active); 71static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 72 bool active); 73static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 74static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 75static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 76static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 77 u32 offset, u16 data); 78static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 79static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 80static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 81 u16 *speed, u16 *duplex); 82static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 83static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 84static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 85static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 86static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 87static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 88static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 89static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 90static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 91static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 92static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 93static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 94static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 95static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 96 u16 offset); 97static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 98 u16 offset); 99static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 100static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 101 102static const u16 e1000_82580_rxpbs_table[] = 103 { 36, 72, 144, 1, 2, 4, 8, 16, 104 35, 70, 140 }; 105#define E1000_82580_RXPBS_TABLE_SIZE \ 106 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 107 108 109/** 110 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 111 * @hw: pointer to the HW structure 112 * 113 * Called to determine if the I2C pins are being used for I2C or as an 114 * external MDIO interface since the two options are mutually exclusive. 115 **/ 116static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 117{ 118 u32 reg = 0; 119 bool ext_mdio = FALSE; 120 121 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 122 123 switch (hw->mac.type) { 124 case e1000_82575: 125 case e1000_82576: 126 reg = E1000_READ_REG(hw, E1000_MDIC); 127 ext_mdio = !!(reg & E1000_MDIC_DEST); 128 break; 129 case e1000_82580: 130 case e1000_i350: 131 reg = E1000_READ_REG(hw, E1000_MDICNFG); 132 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 133 break; 134 default: 135 break; 136 } 137 return ext_mdio; 138} 139 140/** 141 * e1000_init_phy_params_82575 - Init PHY func ptrs. 142 * @hw: pointer to the HW structure 143 **/ 144static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 145{ 146 struct e1000_phy_info *phy = &hw->phy; 147 s32 ret_val = E1000_SUCCESS; 148 u32 ctrl_ext; 149 150 DEBUGFUNC("e1000_init_phy_params_82575"); 151 152 if (hw->phy.media_type != e1000_media_type_copper) { 153 phy->type = e1000_phy_none; 154 goto out; 155 } 156 157 phy->ops.power_up = e1000_power_up_phy_copper; 158 phy->ops.power_down = e1000_power_down_phy_copper_82575; 159 160 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 161 phy->reset_delay_us = 100; 162 163 phy->ops.acquire = e1000_acquire_phy_82575; 164 phy->ops.check_reset_block = e1000_check_reset_block_generic; 165 phy->ops.commit = e1000_phy_sw_reset_generic; 166 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 167 phy->ops.release = e1000_release_phy_82575; 168 169 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 170 171 if (e1000_sgmii_active_82575(hw)) { 172 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 173 ctrl_ext |= E1000_CTRL_I2C_ENA; 174 } else { 175 phy->ops.reset = e1000_phy_hw_reset_generic; 176 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 177 } 178 179 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 180 e1000_reset_mdicnfg_82580(hw); 181 182 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 183 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 184 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 185 } else if (hw->mac.type >= e1000_82580) { 186 phy->ops.read_reg = e1000_read_phy_reg_82580; 187 phy->ops.write_reg = e1000_write_phy_reg_82580; 188 } else { 189 phy->ops.read_reg = e1000_read_phy_reg_igp; 190 phy->ops.write_reg = e1000_write_phy_reg_igp; 191 } 192 193 /* Set phy->phy_addr and phy->id. */ 194 ret_val = e1000_get_phy_id_82575(hw); 195 196 /* Verify phy id and set remaining function pointers */ 197 switch (phy->id) { 198 case I347AT4_E_PHY_ID: 199 case M88E1112_E_PHY_ID: 200 case M88E1111_I_PHY_ID: 201 phy->type = e1000_phy_m88; 202 phy->ops.check_polarity = e1000_check_polarity_m88; 203 phy->ops.get_info = e1000_get_phy_info_m88; 204 if (phy->id == I347AT4_E_PHY_ID || 205 phy->id == M88E1112_E_PHY_ID) 206 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 207 else 208 phy->ops.get_cable_length = e1000_get_cable_length_m88; 209 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 210 break; 211 case IGP03E1000_E_PHY_ID: 212 case IGP04E1000_E_PHY_ID: 213 phy->type = e1000_phy_igp_3; 214 phy->ops.check_polarity = e1000_check_polarity_igp; 215 phy->ops.get_info = e1000_get_phy_info_igp; 216 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 217 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 218 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 219 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 220 break; 221 case I82580_I_PHY_ID: 222 case I350_I_PHY_ID: 223 phy->type = e1000_phy_82580; 224 phy->ops.check_polarity = e1000_check_polarity_82577; 225 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; 226 phy->ops.get_cable_length = e1000_get_cable_length_82577; 227 phy->ops.get_info = e1000_get_phy_info_82577; 228 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 229 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 230 break; 231 default: 232 ret_val = -E1000_ERR_PHY; 233 goto out; 234 } 235 236out: 237 return ret_val; 238} 239 240/** 241 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 242 * @hw: pointer to the HW structure 243 **/ 244static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 245{ 246 struct e1000_nvm_info *nvm = &hw->nvm; 247 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 248 u16 size; 249 250 DEBUGFUNC("e1000_init_nvm_params_82575"); 251 252 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 253 E1000_EECD_SIZE_EX_SHIFT); 254 /* 255 * Added to a constant, "size" becomes the left-shift value 256 * for setting word_size. 257 */ 258 size += NVM_WORD_SIZE_BASE_SHIFT; 259 260 nvm->word_size = 1 << size; 261 262 nvm->opcode_bits = 8; 263 nvm->delay_usec = 1; 264 switch (nvm->override) { 265 case e1000_nvm_override_spi_large: 266 nvm->page_size = 32; 267 nvm->address_bits = 16; 268 break; 269 case e1000_nvm_override_spi_small: 270 nvm->page_size = 8; 271 nvm->address_bits = 8; 272 break; 273 default: 274 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 275 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 276 break; 277 } 278 279 nvm->type = e1000_nvm_eeprom_spi; 280 281 if (nvm->word_size == (1 << 15)) { 282 nvm->page_size = 128; 283 } 284 285 286 /* Function Pointers */ 287 nvm->ops.acquire = e1000_acquire_nvm_82575; 288 if (nvm->word_size < (1 << 15)) { 289 nvm->ops.read = e1000_read_nvm_eerd; 290 } else { 291 nvm->ops.read = e1000_read_nvm_spi; 292 } 293 nvm->ops.release = e1000_release_nvm_82575; 294 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 295 switch (hw->mac.type) { 296 case e1000_82580: 297 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 298 nvm->ops.update = e1000_update_nvm_checksum_82580; 299 break; 300 case e1000_i350: 301 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 302 nvm->ops.update = e1000_update_nvm_checksum_i350; 303 break; 304 default: 305 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 306 nvm->ops.update = e1000_update_nvm_checksum_generic; 307 } 308 nvm->ops.write = e1000_write_nvm_spi; 309 310 return E1000_SUCCESS; 311} 312 313/** 314 * e1000_init_mac_params_82575 - Init MAC func ptrs. 315 * @hw: pointer to the HW structure 316 **/ 317static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 318{ 319 struct e1000_mac_info *mac = &hw->mac; 320 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 321 u32 ctrl_ext = 0; 322 323 DEBUGFUNC("e1000_init_mac_params_82575"); 324 325 /* Set media type */ 326 /* 327 * The 82575 uses bits 22:23 for link mode. The mode can be changed 328 * based on the EEPROM. We cannot rely upon device ID. There 329 * is no distinguishable difference between fiber and internal 330 * SerDes mode on the 82575. There can be an external PHY attached 331 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 332 */ 333 hw->phy.media_type = e1000_media_type_copper; 334 dev_spec->sgmii_active = FALSE; 335 336 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 337 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 338 case E1000_CTRL_EXT_LINK_MODE_SGMII: 339 dev_spec->sgmii_active = TRUE; 340 break; 341 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 342 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 343 hw->phy.media_type = e1000_media_type_internal_serdes; 344 break; 345 default: 346 break; 347 } 348 349 /* Set mta register count */ 350 mac->mta_reg_count = 128; 351 /* Set uta register count */ 352 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 353 /* Set rar entry count */ 354 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 355 if (mac->type == e1000_82576) 356 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 357 if (mac->type == e1000_82580) 358 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 359 if (mac->type == e1000_i350) { 360 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 361 /* Enable EEE default settings for i350 */ 362 dev_spec->eee_disable = FALSE; 363 } 364 365 /* Set if part includes ASF firmware */ 366 mac->asf_firmware_present = TRUE; 367 /* FWSM register */ 368 mac->has_fwsm = TRUE; 369 /* ARC supported; valid only if manageability features are enabled. */ 370 mac->arc_subsystem_valid = 371 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 372 ? TRUE : FALSE; 373 374 /* Function pointers */ 375 376 /* bus type/speed/width */ 377 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 378 /* reset */ 379 if (mac->type >= e1000_82580) 380 mac->ops.reset_hw = e1000_reset_hw_82580; 381 else 382 mac->ops.reset_hw = e1000_reset_hw_82575; 383 /* hw initialization */ 384 mac->ops.init_hw = e1000_init_hw_82575; 385 /* link setup */ 386 mac->ops.setup_link = e1000_setup_link_generic; 387 /* physical interface link setup */ 388 mac->ops.setup_physical_interface = 389 (hw->phy.media_type == e1000_media_type_copper) 390 ? e1000_setup_copper_link_82575 391 : e1000_setup_serdes_link_82575; 392 /* physical interface shutdown */ 393 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 394 /* physical interface power up */ 395 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 396 /* check for link */ 397 mac->ops.check_for_link = e1000_check_for_link_82575; 398 /* receive address register setting */ 399 mac->ops.rar_set = e1000_rar_set_generic; 400 /* read mac address */ 401 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 402 /* configure collision distance */ 403 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 404 /* multicast address update */ 405 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 406 /* writing VFTA */ 407 mac->ops.write_vfta = e1000_write_vfta_generic; 408 /* clearing VFTA */ 409 mac->ops.clear_vfta = e1000_clear_vfta_generic; 410 /* ID LED init */ 411 mac->ops.id_led_init = e1000_id_led_init_generic; 412 /* blink LED */ 413 mac->ops.blink_led = e1000_blink_led_generic; 414 /* setup LED */ 415 mac->ops.setup_led = e1000_setup_led_generic; 416 /* cleanup LED */ 417 mac->ops.cleanup_led = e1000_cleanup_led_generic; 418 /* turn on/off LED */ 419 mac->ops.led_on = e1000_led_on_generic; 420 mac->ops.led_off = e1000_led_off_generic; 421 /* clear hardware counters */ 422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 423 /* link info */ 424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 425 426 /* set lan id for port to determine which phy lock to use */ 427 hw->mac.ops.set_lan_id(hw); 428 429 return E1000_SUCCESS; 430} 431 432/** 433 * e1000_init_function_pointers_82575 - Init func ptrs. 434 * @hw: pointer to the HW structure 435 * 436 * Called to initialize all function pointers and parameters. 437 **/ 438void e1000_init_function_pointers_82575(struct e1000_hw *hw) 439{ 440 DEBUGFUNC("e1000_init_function_pointers_82575"); 441 442 hw->mac.ops.init_params = e1000_init_mac_params_82575; 443 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 444 hw->phy.ops.init_params = e1000_init_phy_params_82575; 445 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 446} 447 448/** 449 * e1000_acquire_phy_82575 - Acquire rights to access PHY 450 * @hw: pointer to the HW structure 451 * 452 * Acquire access rights to the correct PHY. 453 **/ 454static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 455{ 456 u16 mask = E1000_SWFW_PHY0_SM; 457 458 DEBUGFUNC("e1000_acquire_phy_82575"); 459 460 if (hw->bus.func == E1000_FUNC_1) 461 mask = E1000_SWFW_PHY1_SM; 462 else if (hw->bus.func == E1000_FUNC_2) 463 mask = E1000_SWFW_PHY2_SM; 464 else if (hw->bus.func == E1000_FUNC_3) 465 mask = E1000_SWFW_PHY3_SM; 466 467 return e1000_acquire_swfw_sync_82575(hw, mask); 468} 469 470/** 471 * e1000_release_phy_82575 - Release rights to access PHY 472 * @hw: pointer to the HW structure 473 * 474 * A wrapper to release access rights to the correct PHY. 475 **/ 476static void e1000_release_phy_82575(struct e1000_hw *hw) 477{ 478 u16 mask = E1000_SWFW_PHY0_SM; 479 480 DEBUGFUNC("e1000_release_phy_82575"); 481 482 if (hw->bus.func == E1000_FUNC_1) 483 mask = E1000_SWFW_PHY1_SM; 484 else if (hw->bus.func == E1000_FUNC_2) 485 mask = E1000_SWFW_PHY2_SM; 486 else if (hw->bus.func == E1000_FUNC_3) 487 mask = E1000_SWFW_PHY3_SM; 488 489 e1000_release_swfw_sync_82575(hw, mask); 490} 491 492/** 493 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 494 * @hw: pointer to the HW structure 495 * @offset: register offset to be read 496 * @data: pointer to the read data 497 * 498 * Reads the PHY register at offset using the serial gigabit media independent 499 * interface and stores the retrieved information in data. 500 **/ 501static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 502 u16 *data) 503{ 504 s32 ret_val = -E1000_ERR_PARAM; 505 506 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 507 508 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 509 DEBUGOUT1("PHY Address %u is out of range\n", offset); 510 goto out; 511 } 512 513 ret_val = hw->phy.ops.acquire(hw); 514 if (ret_val) 515 goto out; 516 517 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 518 519 hw->phy.ops.release(hw); 520 521out: 522 return ret_val; 523} 524 525/** 526 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 527 * @hw: pointer to the HW structure 528 * @offset: register offset to write to 529 * @data: data to write at register offset 530 * 531 * Writes the data to PHY register at the offset using the serial gigabit 532 * media independent interface. 533 **/ 534static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 535 u16 data) 536{ 537 s32 ret_val = -E1000_ERR_PARAM; 538 539 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 540 541 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 542 DEBUGOUT1("PHY Address %d is out of range\n", offset); 543 goto out; 544 } 545 546 ret_val = hw->phy.ops.acquire(hw); 547 if (ret_val) 548 goto out; 549 550 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 551 552 hw->phy.ops.release(hw); 553 554out: 555 return ret_val; 556} 557 558/** 559 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 560 * @hw: pointer to the HW structure 561 * 562 * Retrieves the PHY address and ID for both PHY's which do and do not use 563 * sgmi interface. 564 **/ 565static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 566{ 567 struct e1000_phy_info *phy = &hw->phy; 568 s32 ret_val = E1000_SUCCESS; 569 u16 phy_id; 570 u32 ctrl_ext; 571 u32 mdic; 572 573 DEBUGFUNC("e1000_get_phy_id_82575"); 574 575 /* 576 * For SGMII PHYs, we try the list of possible addresses until 577 * we find one that works. For non-SGMII PHYs 578 * (e.g. integrated copper PHYs), an address of 1 should 579 * work. The result of this function should mean phy->phy_addr 580 * and phy->id are set correctly. 581 */ 582 if (!e1000_sgmii_active_82575(hw)) { 583 phy->addr = 1; 584 ret_val = e1000_get_phy_id(hw); 585 goto out; 586 } 587 588 if (e1000_sgmii_uses_mdio_82575(hw)) { 589 switch (hw->mac.type) { 590 case e1000_82575: 591 case e1000_82576: 592 mdic = E1000_READ_REG(hw, E1000_MDIC); 593 mdic &= E1000_MDIC_PHY_MASK; 594 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 595 break; 596 case e1000_82580: 597 case e1000_i350: 598 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 599 mdic &= E1000_MDICNFG_PHY_MASK; 600 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 601 break; 602 default: 603 ret_val = -E1000_ERR_PHY; 604 goto out; 605 break; 606 } 607 ret_val = e1000_get_phy_id(hw); 608 goto out; 609 } 610 611 /* Power on sgmii phy if it is disabled */ 612 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 613 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 614 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 615 E1000_WRITE_FLUSH(hw); 616 msec_delay(300); 617 618 /* 619 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 620 * Therefore, we need to test 1-7 621 */ 622 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 623 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 624 if (ret_val == E1000_SUCCESS) { 625 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 626 phy_id, 627 phy->addr); 628 /* 629 * At the time of this writing, The M88 part is 630 * the only supported SGMII PHY product. 631 */ 632 if (phy_id == M88_VENDOR) 633 break; 634 } else { 635 DEBUGOUT1("PHY address %u was unreadable\n", 636 phy->addr); 637 } 638 } 639 640 /* A valid PHY type couldn't be found. */ 641 if (phy->addr == 8) { 642 phy->addr = 0; 643 ret_val = -E1000_ERR_PHY; 644 } else { 645 ret_val = e1000_get_phy_id(hw); 646 } 647 648 /* restore previous sfp cage power state */ 649 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 650 651out: 652 return ret_val; 653} 654 655/** 656 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 657 * @hw: pointer to the HW structure 658 * 659 * Resets the PHY using the serial gigabit media independent interface. 660 **/ 661static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 662{ 663 s32 ret_val = E1000_SUCCESS; 664 665 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 666 667 /* 668 * This isn't a TRUE "hard" reset, but is the only reset 669 * available to us at this time. 670 */ 671 672 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 673 674 if (!(hw->phy.ops.write_reg)) 675 goto out; 676 677 /* 678 * SFP documentation requires the following to configure the SPF module 679 * to work on SGMII. No further documentation is given. 680 */ 681 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 682 if (ret_val) 683 goto out; 684 685 ret_val = hw->phy.ops.commit(hw); 686 687out: 688 return ret_val; 689} 690 691/** 692 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 693 * @hw: pointer to the HW structure 694 * @active: TRUE to enable LPLU, FALSE to disable 695 * 696 * Sets the LPLU D0 state according to the active flag. When 697 * activating LPLU this function also disables smart speed 698 * and vice versa. LPLU will not be activated unless the 699 * device autonegotiation advertisement meets standards of 700 * either 10 or 10/100 or 10/100/1000 at all duplexes. 701 * This is a function pointer entry point only called by 702 * PHY setup routines. 703 **/ 704static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 705{ 706 struct e1000_phy_info *phy = &hw->phy; 707 s32 ret_val = E1000_SUCCESS; 708 u16 data; 709 710 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 711 712 if (!(hw->phy.ops.read_reg)) 713 goto out; 714 715 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 716 if (ret_val) 717 goto out; 718 719 if (active) { 720 data |= IGP02E1000_PM_D0_LPLU; 721 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 722 data); 723 if (ret_val) 724 goto out; 725 726 /* When LPLU is enabled, we should disable SmartSpeed */ 727 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 728 &data); 729 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 730 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 731 data); 732 if (ret_val) 733 goto out; 734 } else { 735 data &= ~IGP02E1000_PM_D0_LPLU; 736 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 737 data); 738 /* 739 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 740 * during Dx states where the power conservation is most 741 * important. During driver activity we should enable 742 * SmartSpeed, so performance is maintained. 743 */ 744 if (phy->smart_speed == e1000_smart_speed_on) { 745 ret_val = phy->ops.read_reg(hw, 746 IGP01E1000_PHY_PORT_CONFIG, 747 &data); 748 if (ret_val) 749 goto out; 750 751 data |= IGP01E1000_PSCFR_SMART_SPEED; 752 ret_val = phy->ops.write_reg(hw, 753 IGP01E1000_PHY_PORT_CONFIG, 754 data); 755 if (ret_val) 756 goto out; 757 } else if (phy->smart_speed == e1000_smart_speed_off) { 758 ret_val = phy->ops.read_reg(hw, 759 IGP01E1000_PHY_PORT_CONFIG, 760 &data); 761 if (ret_val) 762 goto out; 763 764 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 765 ret_val = phy->ops.write_reg(hw, 766 IGP01E1000_PHY_PORT_CONFIG, 767 data); 768 if (ret_val) 769 goto out; 770 } 771 } 772 773out: 774 return ret_val; 775} 776 777/** 778 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 779 * @hw: pointer to the HW structure 780 * @active: TRUE to enable LPLU, FALSE to disable 781 * 782 * Sets the LPLU D0 state according to the active flag. When 783 * activating LPLU this function also disables smart speed 784 * and vice versa. LPLU will not be activated unless the 785 * device autonegotiation advertisement meets standards of 786 * either 10 or 10/100 or 10/100/1000 at all duplexes. 787 * This is a function pointer entry point only called by 788 * PHY setup routines. 789 **/ 790static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 791{ 792 struct e1000_phy_info *phy = &hw->phy; 793 s32 ret_val = E1000_SUCCESS; 794 u16 data; 795 796 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 797 798 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 799 800 if (active) { 801 data |= E1000_82580_PM_D0_LPLU; 802 803 /* When LPLU is enabled, we should disable SmartSpeed */ 804 data &= ~E1000_82580_PM_SPD; 805 } else { 806 data &= ~E1000_82580_PM_D0_LPLU; 807 808 /* 809 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 810 * during Dx states where the power conservation is most 811 * important. During driver activity we should enable 812 * SmartSpeed, so performance is maintained. 813 */ 814 if (phy->smart_speed == e1000_smart_speed_on) { 815 data |= E1000_82580_PM_SPD; 816 } else if (phy->smart_speed == e1000_smart_speed_off) { 817 data &= ~E1000_82580_PM_SPD; 818 } 819 } 820 821 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 822 return ret_val; 823} 824 825/** 826 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 827 * @hw: pointer to the HW structure 828 * @active: boolean used to enable/disable lplu 829 * 830 * Success returns 0, Failure returns 1 831 * 832 * The low power link up (lplu) state is set to the power management level D3 833 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 834 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 835 * is used during Dx states where the power conservation is most important. 836 * During driver activity, SmartSpeed should be enabled so performance is 837 * maintained. 838 **/ 839s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 840{ 841 struct e1000_phy_info *phy = &hw->phy; 842 s32 ret_val = E1000_SUCCESS; 843 u16 data; 844 845 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 846 847 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 848 849 if (!active) { 850 data &= ~E1000_82580_PM_D3_LPLU; 851 /* 852 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 853 * during Dx states where the power conservation is most 854 * important. During driver activity we should enable 855 * SmartSpeed, so performance is maintained. 856 */ 857 if (phy->smart_speed == e1000_smart_speed_on) { 858 data |= E1000_82580_PM_SPD; 859 } else if (phy->smart_speed == e1000_smart_speed_off) { 860 data &= ~E1000_82580_PM_SPD; 861 } 862 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 863 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 864 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 865 data |= E1000_82580_PM_D3_LPLU; 866 /* When LPLU is enabled, we should disable SmartSpeed */ 867 data &= ~E1000_82580_PM_SPD; 868 } 869 870 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 871 return ret_val; 872} 873 874/** 875 * e1000_acquire_nvm_82575 - Request for access to EEPROM 876 * @hw: pointer to the HW structure 877 * 878 * Acquire the necessary semaphores for exclusive access to the EEPROM. 879 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 880 * Return successful if access grant bit set, else clear the request for 881 * EEPROM access and return -E1000_ERR_NVM (-1). 882 **/ 883static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 884{ 885 s32 ret_val; 886 887 DEBUGFUNC("e1000_acquire_nvm_82575"); 888 889 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 890 if (ret_val) 891 goto out; 892 893 ret_val = e1000_acquire_nvm_generic(hw); 894 895 if (ret_val) 896 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 897 898out: 899 return ret_val; 900} 901 902/** 903 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 904 * @hw: pointer to the HW structure 905 * 906 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 907 * then release the semaphores acquired. 908 **/ 909static void e1000_release_nvm_82575(struct e1000_hw *hw) 910{ 911 DEBUGFUNC("e1000_release_nvm_82575"); 912 913 e1000_release_nvm_generic(hw); 914 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 915} 916 917/** 918 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 919 * @hw: pointer to the HW structure 920 * @mask: specifies which semaphore to acquire 921 * 922 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 923 * will also specify which port we're acquiring the lock for. 924 **/ 925static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 926{ 927 u32 swfw_sync; 928 u32 swmask = mask; 929 u32 fwmask = mask << 16; 930 s32 ret_val = E1000_SUCCESS; 931 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 932 933 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 934 935 while (i < timeout) { 936 if (e1000_get_hw_semaphore_generic(hw)) { 937 ret_val = -E1000_ERR_SWFW_SYNC; 938 goto out; 939 } 940 941 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 942 if (!(swfw_sync & (fwmask | swmask))) 943 break; 944 945 /* 946 * Firmware currently using resource (fwmask) 947 * or other software thread using resource (swmask) 948 */ 949 e1000_put_hw_semaphore_generic(hw); 950 msec_delay_irq(5); 951 i++; 952 } 953 954 if (i == timeout) { 955 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 956 ret_val = -E1000_ERR_SWFW_SYNC; 957 goto out; 958 } 959 960 swfw_sync |= swmask; 961 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 962 963 e1000_put_hw_semaphore_generic(hw); 964 965out: 966 return ret_val; 967} 968 969/** 970 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 971 * @hw: pointer to the HW structure 972 * @mask: specifies which semaphore to acquire 973 * 974 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 975 * will also specify which port we're releasing the lock for. 976 **/ 977static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 978{ 979 u32 swfw_sync; 980 981 DEBUGFUNC("e1000_release_swfw_sync_82575"); 982 983 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 984 /* Empty */ 985 986 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 987 swfw_sync &= ~mask; 988 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 989 990 e1000_put_hw_semaphore_generic(hw); 991} 992 993/** 994 * e1000_get_cfg_done_82575 - Read config done bit 995 * @hw: pointer to the HW structure 996 * 997 * Read the management control register for the config done bit for 998 * completion status. NOTE: silicon which is EEPROM-less will fail trying 999 * to read the config done bit, so an error is *ONLY* logged and returns 1000 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1001 * would not be able to be reset or change link. 1002 **/ 1003static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1004{ 1005 s32 timeout = PHY_CFG_TIMEOUT; 1006 s32 ret_val = E1000_SUCCESS; 1007 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1008 1009 DEBUGFUNC("e1000_get_cfg_done_82575"); 1010 1011 if (hw->bus.func == E1000_FUNC_1) 1012 mask = E1000_NVM_CFG_DONE_PORT_1; 1013 else if (hw->bus.func == E1000_FUNC_2) 1014 mask = E1000_NVM_CFG_DONE_PORT_2; 1015 else if (hw->bus.func == E1000_FUNC_3) 1016 mask = E1000_NVM_CFG_DONE_PORT_3; 1017 while (timeout) { 1018 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1019 break; 1020 msec_delay(1); 1021 timeout--; 1022 } 1023 if (!timeout) 1024 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1025 1026 /* If EEPROM is not marked present, init the PHY manually */ 1027 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 1028 (hw->phy.type == e1000_phy_igp_3)) 1029 e1000_phy_init_script_igp3(hw); 1030 1031 return ret_val; 1032} 1033 1034/** 1035 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1036 * @hw: pointer to the HW structure 1037 * @speed: stores the current speed 1038 * @duplex: stores the current duplex 1039 * 1040 * This is a wrapper function, if using the serial gigabit media independent 1041 * interface, use PCS to retrieve the link speed and duplex information. 1042 * Otherwise, use the generic function to get the link speed and duplex info. 1043 **/ 1044static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1045 u16 *duplex) 1046{ 1047 s32 ret_val; 1048 1049 DEBUGFUNC("e1000_get_link_up_info_82575"); 1050 1051 if (hw->phy.media_type != e1000_media_type_copper) 1052 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1053 duplex); 1054 else 1055 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1056 duplex); 1057 1058 return ret_val; 1059} 1060 1061/** 1062 * e1000_check_for_link_82575 - Check for link 1063 * @hw: pointer to the HW structure 1064 * 1065 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1066 * use the generic interface for determining link. 1067 **/ 1068static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1069{ 1070 s32 ret_val; 1071 u16 speed, duplex; 1072 1073 DEBUGFUNC("e1000_check_for_link_82575"); 1074 1075 if (hw->phy.media_type != e1000_media_type_copper) { 1076 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1077 &duplex); 1078 /* 1079 * Use this flag to determine if link needs to be checked or 1080 * not. If we have link clear the flag so that we do not 1081 * continue to check for link. 1082 */ 1083 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1084 } else { 1085 ret_val = e1000_check_for_copper_link_generic(hw); 1086 } 1087 1088 return ret_val; 1089} 1090 1091/** 1092 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1093 * @hw: pointer to the HW structure 1094 **/ 1095static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1096{ 1097 u32 reg; 1098 1099 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1100 1101 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1102 !e1000_sgmii_active_82575(hw)) 1103 return; 1104 1105 /* Enable PCS to turn on link */ 1106 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1107 reg |= E1000_PCS_CFG_PCS_EN; 1108 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1109 1110 /* Power up the laser */ 1111 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1112 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1113 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1114 1115 /* flush the write to verify completion */ 1116 E1000_WRITE_FLUSH(hw); 1117 msec_delay(1); 1118} 1119 1120/** 1121 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1122 * @hw: pointer to the HW structure 1123 * @speed: stores the current speed 1124 * @duplex: stores the current duplex 1125 * 1126 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1127 * duplex, then store the values in the pointers provided. 1128 **/ 1129static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1130 u16 *speed, u16 *duplex) 1131{ 1132 struct e1000_mac_info *mac = &hw->mac; 1133 u32 pcs; 1134 1135 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1136 1137 /* Set up defaults for the return values of this function */ 1138 mac->serdes_has_link = FALSE; 1139 *speed = 0; 1140 *duplex = 0; 1141 1142 /* 1143 * Read the PCS Status register for link state. For non-copper mode, 1144 * the status register is not accurate. The PCS status register is 1145 * used instead. 1146 */ 1147 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1148 1149 /* 1150 * The link up bit determines when link is up on autoneg. The sync ok 1151 * gets set once both sides sync up and agree upon link. Stable link 1152 * can be determined by checking for both link up and link sync ok 1153 */ 1154 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1155 mac->serdes_has_link = TRUE; 1156 1157 /* Detect and store PCS speed */ 1158 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 1159 *speed = SPEED_1000; 1160 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 1161 *speed = SPEED_100; 1162 } else { 1163 *speed = SPEED_10; 1164 } 1165 1166 /* Detect and store PCS duplex */ 1167 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 1168 *duplex = FULL_DUPLEX; 1169 } else { 1170 *duplex = HALF_DUPLEX; 1171 } 1172 } 1173 1174 return E1000_SUCCESS; 1175} 1176 1177/** 1178 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1179 * @hw: pointer to the HW structure 1180 * 1181 * In the case of serdes shut down sfp and PCS on driver unload 1182 * when management pass thru is not enabled. 1183 **/ 1184void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1185{ 1186 u32 reg; 1187 1188 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1189 1190 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1191 !e1000_sgmii_active_82575(hw)) 1192 return; 1193 1194 if (!e1000_enable_mng_pass_thru(hw)) { 1195 /* Disable PCS to turn off link */ 1196 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1197 reg &= ~E1000_PCS_CFG_PCS_EN; 1198 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1199 1200 /* shutdown the laser */ 1201 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1202 reg |= E1000_CTRL_EXT_SDP3_DATA; 1203 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1204 1205 /* flush the write to verify completion */ 1206 E1000_WRITE_FLUSH(hw); 1207 msec_delay(1); 1208 } 1209 1210 return; 1211} 1212 1213/** 1214 * e1000_reset_hw_82575 - Reset hardware 1215 * @hw: pointer to the HW structure 1216 * 1217 * This resets the hardware into a known state. 1218 **/ 1219static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1220{ 1221 u32 ctrl; 1222 s32 ret_val; 1223 1224 DEBUGFUNC("e1000_reset_hw_82575"); 1225 1226 /* 1227 * Prevent the PCI-E bus from sticking if there is no TLP connection 1228 * on the last TLP read/write transaction when MAC is reset. 1229 */ 1230 ret_val = e1000_disable_pcie_master_generic(hw); 1231 if (ret_val) { 1232 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1233 } 1234 1235 /* set the completion timeout for interface */ 1236 ret_val = e1000_set_pcie_completion_timeout(hw); 1237 if (ret_val) { 1238 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1239 } 1240 1241 DEBUGOUT("Masking off all interrupts\n"); 1242 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1243 1244 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1245 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1246 E1000_WRITE_FLUSH(hw); 1247 1248 msec_delay(10); 1249 1250 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1251 1252 DEBUGOUT("Issuing a global reset to MAC\n"); 1253 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1254 1255 ret_val = e1000_get_auto_rd_done_generic(hw); 1256 if (ret_val) { 1257 /* 1258 * When auto config read does not complete, do not 1259 * return with an error. This can happen in situations 1260 * where there is no eeprom and prevents getting link. 1261 */ 1262 DEBUGOUT("Auto Read Done did not complete\n"); 1263 } 1264 1265 /* If EEPROM is not present, run manual init scripts */ 1266 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1267 e1000_reset_init_script_82575(hw); 1268 1269 /* Clear any pending interrupt events. */ 1270 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1271 E1000_READ_REG(hw, E1000_ICR); 1272 1273 /* Install any alternate MAC address into RAR0 */ 1274 ret_val = e1000_check_alt_mac_addr_generic(hw); 1275 1276 return ret_val; 1277} 1278 1279/** 1280 * e1000_init_hw_82575 - Initialize hardware 1281 * @hw: pointer to the HW structure 1282 * 1283 * This inits the hardware readying it for operation. 1284 **/ 1285static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1286{ 1287 struct e1000_mac_info *mac = &hw->mac; 1288 s32 ret_val; 1289 u16 i, rar_count = mac->rar_entry_count; 1290 1291 DEBUGFUNC("e1000_init_hw_82575"); 1292 1293 /* Initialize identification LED */ 1294 ret_val = mac->ops.id_led_init(hw); 1295 if (ret_val) { 1296 DEBUGOUT("Error initializing identification LED\n"); 1297 /* This is not fatal and we should not stop init due to this */ 1298 } 1299 1300 /* Disabling VLAN filtering */ 1301 DEBUGOUT("Initializing the IEEE VLAN\n"); 1302 mac->ops.clear_vfta(hw); 1303 1304 /* Setup the receive address */ 1305 e1000_init_rx_addrs_generic(hw, rar_count); 1306 1307 /* Zero out the Multicast HASH table */ 1308 DEBUGOUT("Zeroing the MTA\n"); 1309 for (i = 0; i < mac->mta_reg_count; i++) 1310 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1311 1312 /* Zero out the Unicast HASH table */ 1313 DEBUGOUT("Zeroing the UTA\n"); 1314 for (i = 0; i < mac->uta_reg_count; i++) 1315 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1316 1317 /* Setup link and flow control */ 1318 ret_val = mac->ops.setup_link(hw); 1319 1320 /* 1321 * Clear all of the statistics registers (clear on read). It is 1322 * important that we do this after we have tried to establish link 1323 * because the symbol error count will increment wildly if there 1324 * is no link. 1325 */ 1326 e1000_clear_hw_cntrs_82575(hw); 1327 1328 return ret_val; 1329} 1330 1331/** 1332 * e1000_setup_copper_link_82575 - Configure copper link settings 1333 * @hw: pointer to the HW structure 1334 * 1335 * Configures the link for auto-neg or forced speed and duplex. Then we check 1336 * for link, once link is established calls to configure collision distance 1337 * and flow control are called. 1338 **/ 1339static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1340{ 1341 u32 ctrl; 1342 s32 ret_val; 1343 1344 DEBUGFUNC("e1000_setup_copper_link_82575"); 1345 1346 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1347 ctrl |= E1000_CTRL_SLU; 1348 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1349 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1350 1351 ret_val = e1000_setup_serdes_link_82575(hw); 1352 if (ret_val) 1353 goto out; 1354 1355 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1356 /* allow time for SFP cage time to power up phy */ 1357 msec_delay(300); 1358 1359 ret_val = hw->phy.ops.reset(hw); 1360 if (ret_val) { 1361 DEBUGOUT("Error resetting the PHY.\n"); 1362 goto out; 1363 } 1364 } 1365 switch (hw->phy.type) { 1366 case e1000_phy_m88: 1367 if (hw->phy.id == I347AT4_E_PHY_ID || 1368 hw->phy.id == M88E1112_E_PHY_ID) 1369 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1370 else 1371 ret_val = e1000_copper_link_setup_m88(hw); 1372 break; 1373 case e1000_phy_igp_3: 1374 ret_val = e1000_copper_link_setup_igp(hw); 1375 break; 1376 case e1000_phy_82580: 1377 ret_val = e1000_copper_link_setup_82577(hw); 1378 break; 1379 default: 1380 ret_val = -E1000_ERR_PHY; 1381 break; 1382 } 1383 1384 if (ret_val) 1385 goto out; 1386 1387 ret_val = e1000_setup_copper_link_generic(hw); 1388out: 1389 return ret_val; 1390} 1391 1392/** 1393 * e1000_setup_serdes_link_82575 - Setup link for serdes 1394 * @hw: pointer to the HW structure 1395 * 1396 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1397 * used on copper connections where the serialized gigabit media independent 1398 * interface (sgmii), or serdes fiber is being used. Configures the link 1399 * for auto-negotiation or forces speed/duplex. 1400 **/ 1401static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1402{ 1403 u32 ctrl_ext, ctrl_reg, reg; 1404 bool pcs_autoneg; 1405 1406 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1407 1408 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1409 !e1000_sgmii_active_82575(hw)) 1410 return E1000_SUCCESS; 1411 1412 /* 1413 * On the 82575, SerDes loopback mode persists until it is 1414 * explicitly turned off or a power cycle is performed. A read to 1415 * the register does not indicate its status. Therefore, we ensure 1416 * loopback mode is disabled during initialization. 1417 */ 1418 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1419 1420 /* power on the sfp cage if present */ 1421 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1422 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1423 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1424 1425 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1426 ctrl_reg |= E1000_CTRL_SLU; 1427 1428 /* set both sw defined pins on 82575/82576*/ 1429 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1430 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1431 1432 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1433 1434 /* default pcs_autoneg to the same setting as mac autoneg */ 1435 pcs_autoneg = hw->mac.autoneg; 1436 1437 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1438 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1439 /* sgmii mode lets the phy handle forcing speed/duplex */ 1440 pcs_autoneg = TRUE; 1441 /* autoneg time out should be disabled for SGMII mode */ 1442 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1443 break; 1444 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1445 /* disable PCS autoneg and support parallel detect only */ 1446 pcs_autoneg = FALSE; 1447 /* fall through to default case */ 1448 default: 1449 /* 1450 * non-SGMII modes only supports a speed of 1000/Full for the 1451 * link so it is best to just force the MAC and let the pcs 1452 * link either autoneg or be forced to 1000/Full 1453 */ 1454 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1455 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1456 1457 /* set speed of 1000/Full if speed/duplex is forced */ 1458 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1459 break; 1460 } 1461 1462 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1463 1464 /* 1465 * New SerDes mode allows for forcing speed or autonegotiating speed 1466 * at 1gb. Autoneg should be default set by most drivers. This is the 1467 * mode that will be compatible with older link partners and switches. 1468 * However, both are supported by the hardware and some drivers/tools. 1469 */ 1470 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1471 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1472 1473 /* 1474 * We force flow control to prevent the CTRL register values from being 1475 * overwritten by the autonegotiated flow control values 1476 */ 1477 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1478 1479 if (pcs_autoneg) { 1480 /* Set PCS register for autoneg */ 1481 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1482 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1483 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1484 } else { 1485 /* Set PCS register for forced link */ 1486 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1487 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1488 } 1489 1490 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1491 1492 if (!e1000_sgmii_active_82575(hw)) 1493 e1000_force_mac_fc_generic(hw); 1494 1495 return E1000_SUCCESS; 1496} 1497 1498/** 1499 * e1000_valid_led_default_82575 - Verify a valid default LED config 1500 * @hw: pointer to the HW structure 1501 * @data: pointer to the NVM (EEPROM) 1502 * 1503 * Read the EEPROM for the current default LED configuration. If the 1504 * LED configuration is not valid, set to a valid LED configuration. 1505 **/ 1506static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1507{ 1508 s32 ret_val; 1509 1510 DEBUGFUNC("e1000_valid_led_default_82575"); 1511 1512 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1513 if (ret_val) { 1514 DEBUGOUT("NVM Read Error\n"); 1515 goto out; 1516 } 1517 1518 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1519 switch(hw->phy.media_type) { 1520 case e1000_media_type_internal_serdes: 1521 *data = ID_LED_DEFAULT_82575_SERDES; 1522 break; 1523 case e1000_media_type_copper: 1524 default: 1525 *data = ID_LED_DEFAULT; 1526 break; 1527 } 1528 } 1529out: 1530 return ret_val; 1531} 1532 1533/** 1534 * e1000_sgmii_active_82575 - Return sgmii state 1535 * @hw: pointer to the HW structure 1536 * 1537 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1538 * which can be enabled for use in the embedded applications. Simply 1539 * return the current state of the sgmii interface. 1540 **/ 1541static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1542{ 1543 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1544 return dev_spec->sgmii_active; 1545} 1546 1547/** 1548 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1549 * @hw: pointer to the HW structure 1550 * 1551 * Inits recommended HW defaults after a reset when there is no EEPROM 1552 * detected. This is only for the 82575. 1553 **/ 1554static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1555{ 1556 DEBUGFUNC("e1000_reset_init_script_82575"); 1557 1558 if (hw->mac.type == e1000_82575) { 1559 DEBUGOUT("Running reset init script for 82575\n"); 1560 /* SerDes configuration via SERDESCTRL */ 1561 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1562 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1563 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1564 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1565 1566 /* CCM configuration via CCMCTL register */ 1567 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1568 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1569 1570 /* PCIe lanes configuration */ 1571 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1572 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1573 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1574 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1575 1576 /* PCIe PLL Configuration */ 1577 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1578 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1579 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1580 } 1581 1582 return E1000_SUCCESS; 1583} 1584 1585/** 1586 * e1000_read_mac_addr_82575 - Read device MAC address 1587 * @hw: pointer to the HW structure 1588 **/ 1589static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1590{ 1591 s32 ret_val = E1000_SUCCESS; 1592 1593 DEBUGFUNC("e1000_read_mac_addr_82575"); 1594 1595 /* 1596 * If there's an alternate MAC address place it in RAR0 1597 * so that it will override the Si installed default perm 1598 * address. 1599 */ 1600 ret_val = e1000_check_alt_mac_addr_generic(hw); 1601 if (ret_val) 1602 goto out; 1603 1604 ret_val = e1000_read_mac_addr_generic(hw); 1605 1606out: 1607 return ret_val; 1608} 1609 1610/** 1611 * e1000_config_collision_dist_82575 - Configure collision distance 1612 * @hw: pointer to the HW structure 1613 * 1614 * Configures the collision distance to the default value and is used 1615 * during link setup. 1616 **/ 1617static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1618{ 1619 u32 tctl_ext; 1620 1621 DEBUGFUNC("e1000_config_collision_dist_82575"); 1622 1623 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1624 1625 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1626 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1627 1628 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1629 E1000_WRITE_FLUSH(hw); 1630} 1631 1632/** 1633 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1634 * @hw: pointer to the HW structure 1635 * 1636 * In the case of a PHY power down to save power, or to turn off link during a 1637 * driver unload, or wake on lan is not enabled, remove the link. 1638 **/ 1639static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1640{ 1641 struct e1000_phy_info *phy = &hw->phy; 1642 1643 if (!(phy->ops.check_reset_block)) 1644 return; 1645 1646 /* If the management interface is not enabled, then power down */ 1647 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1648 e1000_power_down_phy_copper(hw); 1649 1650 return; 1651} 1652 1653/** 1654 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1655 * @hw: pointer to the HW structure 1656 * 1657 * Clears the hardware counters by reading the counter registers. 1658 **/ 1659static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1660{ 1661 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1662 1663 e1000_clear_hw_cntrs_base_generic(hw); 1664 1665 E1000_READ_REG(hw, E1000_PRC64); 1666 E1000_READ_REG(hw, E1000_PRC127); 1667 E1000_READ_REG(hw, E1000_PRC255); 1668 E1000_READ_REG(hw, E1000_PRC511); 1669 E1000_READ_REG(hw, E1000_PRC1023); 1670 E1000_READ_REG(hw, E1000_PRC1522); 1671 E1000_READ_REG(hw, E1000_PTC64); 1672 E1000_READ_REG(hw, E1000_PTC127); 1673 E1000_READ_REG(hw, E1000_PTC255); 1674 E1000_READ_REG(hw, E1000_PTC511); 1675 E1000_READ_REG(hw, E1000_PTC1023); 1676 E1000_READ_REG(hw, E1000_PTC1522); 1677 1678 E1000_READ_REG(hw, E1000_ALGNERRC); 1679 E1000_READ_REG(hw, E1000_RXERRC); 1680 E1000_READ_REG(hw, E1000_TNCRS); 1681 E1000_READ_REG(hw, E1000_CEXTERR); 1682 E1000_READ_REG(hw, E1000_TSCTC); 1683 E1000_READ_REG(hw, E1000_TSCTFC); 1684 1685 E1000_READ_REG(hw, E1000_MGTPRC); 1686 E1000_READ_REG(hw, E1000_MGTPDC); 1687 E1000_READ_REG(hw, E1000_MGTPTC); 1688 1689 E1000_READ_REG(hw, E1000_IAC); 1690 E1000_READ_REG(hw, E1000_ICRXOC); 1691 1692 E1000_READ_REG(hw, E1000_ICRXPTC); 1693 E1000_READ_REG(hw, E1000_ICRXATC); 1694 E1000_READ_REG(hw, E1000_ICTXPTC); 1695 E1000_READ_REG(hw, E1000_ICTXATC); 1696 E1000_READ_REG(hw, E1000_ICTXQEC); 1697 E1000_READ_REG(hw, E1000_ICTXQMTC); 1698 E1000_READ_REG(hw, E1000_ICRXDMTC); 1699 1700 E1000_READ_REG(hw, E1000_CBTMPC); 1701 E1000_READ_REG(hw, E1000_HTDPMC); 1702 E1000_READ_REG(hw, E1000_CBRMPC); 1703 E1000_READ_REG(hw, E1000_RPTHC); 1704 E1000_READ_REG(hw, E1000_HGPTC); 1705 E1000_READ_REG(hw, E1000_HTCBDPC); 1706 E1000_READ_REG(hw, E1000_HGORCL); 1707 E1000_READ_REG(hw, E1000_HGORCH); 1708 E1000_READ_REG(hw, E1000_HGOTCL); 1709 E1000_READ_REG(hw, E1000_HGOTCH); 1710 E1000_READ_REG(hw, E1000_LENERRS); 1711 1712 /* This register should not be read in copper configurations */ 1713 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1714 e1000_sgmii_active_82575(hw)) 1715 E1000_READ_REG(hw, E1000_SCVPC); 1716} 1717 1718/** 1719 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 1720 * @hw: pointer to the HW structure 1721 * 1722 * After rx enable if managability is enabled then there is likely some 1723 * bad data at the start of the fifo and possibly in the DMA fifo. This 1724 * function clears the fifos and flushes any packets that came in as rx was 1725 * being enabled. 1726 **/ 1727void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1728{ 1729 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1730 int i, ms_wait; 1731 1732 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1733 if (hw->mac.type != e1000_82575 || 1734 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1735 return; 1736 1737 /* Disable all Rx queues */ 1738 for (i = 0; i < 4; i++) { 1739 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1740 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1741 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1742 } 1743 /* Poll all queues to verify they have shut down */ 1744 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1745 msec_delay(1); 1746 rx_enabled = 0; 1747 for (i = 0; i < 4; i++) 1748 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1749 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1750 break; 1751 } 1752 1753 if (ms_wait == 10) 1754 DEBUGOUT("Queue disable timed out after 10ms\n"); 1755 1756 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1757 * incoming packets are rejected. Set enable and wait 2ms so that 1758 * any packet that was coming in as RCTL.EN was set is flushed 1759 */ 1760 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1761 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1762 1763 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1764 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1765 1766 rctl = E1000_READ_REG(hw, E1000_RCTL); 1767 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1768 temp_rctl |= E1000_RCTL_LPE; 1769 1770 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1771 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1772 E1000_WRITE_FLUSH(hw); 1773 msec_delay(2); 1774 1775 /* Enable Rx queues that were previously enabled and restore our 1776 * previous state 1777 */ 1778 for (i = 0; i < 4; i++) 1779 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1780 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1781 E1000_WRITE_FLUSH(hw); 1782 1783 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1784 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1785 1786 /* Flush receive errors generated by workaround */ 1787 E1000_READ_REG(hw, E1000_ROC); 1788 E1000_READ_REG(hw, E1000_RNBC); 1789 E1000_READ_REG(hw, E1000_MPC); 1790} 1791 1792/** 1793 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1794 * @hw: pointer to the HW structure 1795 * 1796 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1797 * however the hardware default for these parts is 500us to 1ms which is less 1798 * than the 10ms recommended by the pci-e spec. To address this we need to 1799 * increase the value to either 10ms to 200ms for capability version 1 config, 1800 * or 16ms to 55ms for version 2. 1801 **/ 1802static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1803{ 1804 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1805 s32 ret_val = E1000_SUCCESS; 1806 u16 pcie_devctl2; 1807 1808 /* only take action if timeout value is defaulted to 0 */ 1809 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1810 goto out; 1811 1812 /* 1813 * if capababilities version is type 1 we can write the 1814 * timeout of 10ms to 200ms through the GCR register 1815 */ 1816 if (!(gcr & E1000_GCR_CAP_VER2)) { 1817 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1818 goto out; 1819 } 1820 1821 /* 1822 * for version 2 capabilities we need to write the config space 1823 * directly in order to set the completion timeout value for 1824 * 16ms to 55ms 1825 */ 1826 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1827 &pcie_devctl2); 1828 if (ret_val) 1829 goto out; 1830 1831 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1832 1833 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1834 &pcie_devctl2); 1835out: 1836 /* disable completion timeout resend */ 1837 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1838 1839 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1840 return ret_val; 1841} 1842 1843 1844/** 1845 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 1846 * @hw: pointer to the hardware struct 1847 * @enable: state to enter, either enabled or disabled 1848 * @pf: Physical Function pool - do not set anti-spoofing for the PF 1849 * 1850 * enables/disables L2 switch anti-spoofing functionality. 1851 **/ 1852void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 1853{ 1854 u32 dtxswc; 1855 1856 switch (hw->mac.type) { 1857 case e1000_82576: 1858 case e1000_i350: 1859 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1860 if (enable) { 1861 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 1862 E1000_DTXSWC_VLAN_SPOOF_MASK); 1863 /* The PF can spoof - it has to in order to 1864 * support emulation mode NICs */ 1865 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 1866 } else { 1867 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 1868 E1000_DTXSWC_VLAN_SPOOF_MASK); 1869 } 1870 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1871 break; 1872 default: 1873 break; 1874 } 1875} 1876 1877/** 1878 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1879 * @hw: pointer to the hardware struct 1880 * @enable: state to enter, either enabled or disabled 1881 * 1882 * enables/disables L2 switch loopback functionality. 1883 **/ 1884void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1885{ 1886 u32 dtxswc; 1887 1888 switch (hw->mac.type) { 1889 case e1000_82576: 1890 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1891 if (enable) 1892 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1893 else 1894 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1895 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1896 break; 1897 case e1000_i350: 1898 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 1899 if (enable) 1900 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1901 else 1902 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1903 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 1904 break; 1905 default: 1906 /* Currently no other hardware supports loopback */ 1907 break; 1908 } 1909 1910 1911} 1912 1913/** 1914 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1915 * @hw: pointer to the hardware struct 1916 * @enable: state to enter, either enabled or disabled 1917 * 1918 * enables/disables replication of packets across multiple pools. 1919 **/ 1920void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1921{ 1922 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 1923 1924 if (enable) 1925 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1926 else 1927 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1928 1929 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 1930} 1931 1932/** 1933 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 1934 * @hw: pointer to the HW structure 1935 * @offset: register offset to be read 1936 * @data: pointer to the read data 1937 * 1938 * Reads the MDI control register in the PHY at offset and stores the 1939 * information read to data. 1940 **/ 1941static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1942{ 1943 s32 ret_val; 1944 1945 DEBUGFUNC("e1000_read_phy_reg_82580"); 1946 1947 ret_val = hw->phy.ops.acquire(hw); 1948 if (ret_val) 1949 goto out; 1950 1951 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 1952 1953 hw->phy.ops.release(hw); 1954 1955out: 1956 return ret_val; 1957} 1958 1959/** 1960 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 1961 * @hw: pointer to the HW structure 1962 * @offset: register offset to write to 1963 * @data: data to write to register at offset 1964 * 1965 * Writes data to MDI control register in the PHY at offset. 1966 **/ 1967static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1968{ 1969 s32 ret_val; 1970 1971 DEBUGFUNC("e1000_write_phy_reg_82580"); 1972 1973 ret_val = hw->phy.ops.acquire(hw); 1974 if (ret_val) 1975 goto out; 1976 1977 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 1978 1979 hw->phy.ops.release(hw); 1980 1981out: 1982 return ret_val; 1983} 1984 1985/** 1986 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 1987 * @hw: pointer to the HW structure 1988 * 1989 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 1990 * the values found in the EEPROM. This addresses an issue in which these 1991 * bits are not restored from EEPROM after reset. 1992 **/ 1993static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 1994{ 1995 s32 ret_val = E1000_SUCCESS; 1996 u32 mdicnfg; 1997 u16 nvm_data = 0; 1998 1999 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2000 2001 if (hw->mac.type != e1000_82580) 2002 goto out; 2003 if (!e1000_sgmii_active_82575(hw)) 2004 goto out; 2005 2006 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2007 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2008 &nvm_data); 2009 if (ret_val) { 2010 DEBUGOUT("NVM Read Error\n"); 2011 goto out; 2012 } 2013 2014 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2015 if (nvm_data & NVM_WORD24_EXT_MDIO) 2016 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2017 if (nvm_data & NVM_WORD24_COM_MDIO) 2018 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2019 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2020out: 2021 return ret_val; 2022} 2023 2024/** 2025 * e1000_reset_hw_82580 - Reset hardware 2026 * @hw: pointer to the HW structure 2027 * 2028 * This resets function or entire device (all ports, etc.) 2029 * to a known state. 2030 **/ 2031static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2032{ 2033 s32 ret_val = E1000_SUCCESS; 2034 /* BH SW mailbox bit in SW_FW_SYNC */ 2035 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2036 u32 ctrl; 2037 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2038 2039 DEBUGFUNC("e1000_reset_hw_82580"); 2040 2041 hw->dev_spec._82575.global_device_reset = FALSE; 2042 2043 /* Get current control state. */ 2044 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2045 2046 /* 2047 * Prevent the PCI-E bus from sticking if there is no TLP connection 2048 * on the last TLP read/write transaction when MAC is reset. 2049 */ 2050 ret_val = e1000_disable_pcie_master_generic(hw); 2051 if (ret_val) 2052 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2053 2054 DEBUGOUT("Masking off all interrupts\n"); 2055 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2056 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2057 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2058 E1000_WRITE_FLUSH(hw); 2059 2060 msec_delay(10); 2061 2062 /* Determine whether or not a global dev reset is requested */ 2063 if (global_device_reset && 2064 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 2065 global_device_reset = FALSE; 2066 2067 if (global_device_reset && 2068 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2069 ctrl |= E1000_CTRL_DEV_RST; 2070 else 2071 ctrl |= E1000_CTRL_RST; 2072 2073 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2074 2075 /* Add delay to insure DEV_RST has time to complete */ 2076 if (global_device_reset) 2077 msec_delay(5); 2078 2079 ret_val = e1000_get_auto_rd_done_generic(hw); 2080 if (ret_val) { 2081 /* 2082 * When auto config read does not complete, do not 2083 * return with an error. This can happen in situations 2084 * where there is no eeprom and prevents getting link. 2085 */ 2086 DEBUGOUT("Auto Read Done did not complete\n"); 2087 } 2088 2089 /* If EEPROM is not present, run manual init scripts */ 2090 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 2091 e1000_reset_init_script_82575(hw); 2092 2093 /* clear global device reset status bit */ 2094 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2095 2096 /* Clear any pending interrupt events. */ 2097 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2098 E1000_READ_REG(hw, E1000_ICR); 2099 2100 ret_val = e1000_reset_mdicnfg_82580(hw); 2101 if (ret_val) 2102 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2103 2104 /* Install any alternate MAC address into RAR0 */ 2105 ret_val = e1000_check_alt_mac_addr_generic(hw); 2106 2107 /* Release semaphore */ 2108 if (global_device_reset) 2109 e1000_release_swfw_sync_82575(hw, swmbsw_mask); 2110 2111 return ret_val; 2112} 2113 2114/** 2115 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2116 * @data: data received by reading RXPBS register 2117 * 2118 * The 82580 uses a table based approach for packet buffer allocation sizes. 2119 * This function converts the retrieved value into the correct table value 2120 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2121 * 0x0 36 72 144 1 2 4 8 16 2122 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2123 */ 2124u16 e1000_rxpbs_adjust_82580(u32 data) 2125{ 2126 u16 ret_val = 0; 2127 2128 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2129 ret_val = e1000_82580_rxpbs_table[data]; 2130 2131 return ret_val; 2132} 2133 2134/** 2135 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2136 * checksum 2137 * @hw: pointer to the HW structure 2138 * @offset: offset in words of the checksum protected region 2139 * 2140 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2141 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2142 **/ 2143s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2144{ 2145 s32 ret_val = E1000_SUCCESS; 2146 u16 checksum = 0; 2147 u16 i, nvm_data; 2148 2149 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2150 2151 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2152 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2153 if (ret_val) { 2154 DEBUGOUT("NVM Read Error\n"); 2155 goto out; 2156 } 2157 checksum += nvm_data; 2158 } 2159 2160 if (checksum != (u16) NVM_SUM) { 2161 DEBUGOUT("NVM Checksum Invalid\n"); 2162 ret_val = -E1000_ERR_NVM; 2163 goto out; 2164 } 2165 2166out: 2167 return ret_val; 2168} 2169 2170/** 2171 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2172 * checksum 2173 * @hw: pointer to the HW structure 2174 * @offset: offset in words of the checksum protected region 2175 * 2176 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2177 * up to the checksum. Then calculates the EEPROM checksum and writes the 2178 * value to the EEPROM. 2179 **/ 2180s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2181{ 2182 s32 ret_val; 2183 u16 checksum = 0; 2184 u16 i, nvm_data; 2185 2186 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2187 2188 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2189 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2190 if (ret_val) { 2191 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2192 goto out; 2193 } 2194 checksum += nvm_data; 2195 } 2196 checksum = (u16) NVM_SUM - checksum; 2197 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2198 &checksum); 2199 if (ret_val) 2200 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2201 2202out: 2203 return ret_val; 2204} 2205 2206/** 2207 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2208 * @hw: pointer to the HW structure 2209 * 2210 * Calculates the EEPROM section checksum by reading/adding each word of 2211 * the EEPROM and then verifies that the sum of the EEPROM is 2212 * equal to 0xBABA. 2213 **/ 2214static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2215{ 2216 s32 ret_val = E1000_SUCCESS; 2217 u16 eeprom_regions_count = 1; 2218 u16 j, nvm_data; 2219 u16 nvm_offset; 2220 2221 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2222 2223 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2224 if (ret_val) { 2225 DEBUGOUT("NVM Read Error\n"); 2226 goto out; 2227 } 2228 2229 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2230 /* if chekcsums compatibility bit is set validate checksums 2231 * for all 4 ports. */ 2232 eeprom_regions_count = 4; 2233 } 2234 2235 for (j = 0; j < eeprom_regions_count; j++) { 2236 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2237 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2238 nvm_offset); 2239 if (ret_val != E1000_SUCCESS) 2240 goto out; 2241 } 2242 2243out: 2244 return ret_val; 2245} 2246 2247/** 2248 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2249 * @hw: pointer to the HW structure 2250 * 2251 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2252 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2253 * checksum and writes the value to the EEPROM. 2254 **/ 2255static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2256{ 2257 s32 ret_val; 2258 u16 j, nvm_data; 2259 u16 nvm_offset; 2260 2261 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2262 2263 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2264 if (ret_val) { 2265 DEBUGOUT("NVM Read Error while updating checksum" 2266 " compatibility bit.\n"); 2267 goto out; 2268 } 2269 2270 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2271 /* set compatibility bit to validate checksums appropriately */ 2272 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2273 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2274 &nvm_data); 2275 if (ret_val) { 2276 DEBUGOUT("NVM Write Error while updating checksum" 2277 " compatibility bit.\n"); 2278 goto out; 2279 } 2280 } 2281 2282 for (j = 0; j < 4; j++) { 2283 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2284 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2285 if (ret_val) { 2286 goto out; 2287 } 2288 } 2289 2290out: 2291 return ret_val; 2292} 2293 2294/** 2295 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2296 * @hw: pointer to the HW structure 2297 * 2298 * Calculates the EEPROM section checksum by reading/adding each word of 2299 * the EEPROM and then verifies that the sum of the EEPROM is 2300 * equal to 0xBABA. 2301 **/ 2302static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2303{ 2304 s32 ret_val = E1000_SUCCESS; 2305 u16 j; 2306 u16 nvm_offset; 2307 2308 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2309 2310 for (j = 0; j < 4; j++) { 2311 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2312 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2313 nvm_offset); 2314 if (ret_val != E1000_SUCCESS) 2315 goto out; 2316 } 2317 2318out: 2319 return ret_val; 2320} 2321 2322/** 2323 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2324 * @hw: pointer to the HW structure 2325 * 2326 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2327 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2328 * checksum and writes the value to the EEPROM. 2329 **/ 2330static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2331{ 2332 s32 ret_val = E1000_SUCCESS; 2333 u16 j; 2334 u16 nvm_offset; 2335 2336 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2337 2338 for (j = 0; j < 4; j++) { 2339 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2340 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2341 if (ret_val != E1000_SUCCESS) 2342 goto out; 2343 } 2344 2345out: 2346 return ret_val; 2347} 2348 2349/** 2350 * e1000_set_eee_i350 - Enable/disable EEE support 2351 * @hw: pointer to the HW structure 2352 * 2353 * Enable/disable EEE based on setting in dev_spec structure. 2354 * 2355 **/ 2356s32 e1000_set_eee_i350(struct e1000_hw *hw) 2357{ 2358 s32 ret_val = E1000_SUCCESS; 2359 u32 ipcnfg, eeer, ctrl_ext; 2360 2361 DEBUGFUNC("e1000_set_eee_i350"); 2362 2363 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2364 if ((hw->mac.type != e1000_i350) || 2365 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK)) 2366 goto out; 2367 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2368 eeer = E1000_READ_REG(hw, E1000_EEER); 2369 2370 /* enable or disable per user setting */ 2371 if (!(hw->dev_spec._82575.eee_disable)) { 2372 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | 2373 E1000_IPCNFG_EEE_100M_AN); 2374 eeer |= (E1000_EEER_TX_LPI_EN | 2375 E1000_EEER_RX_LPI_EN | 2376 E1000_EEER_LPI_FC); 2377 2378 } else { 2379 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2380 E1000_IPCNFG_EEE_100M_AN); 2381 eeer &= ~(E1000_EEER_TX_LPI_EN | 2382 E1000_EEER_RX_LPI_EN | 2383 E1000_EEER_LPI_FC); 2384 } 2385 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2386 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2387 E1000_READ_REG(hw, E1000_IPCNFG); 2388 E1000_READ_REG(hw, E1000_EEER); 2389out: 2390 2391 return ret_val; 2392} 2393