e1000_82575.c revision 194865
133965Sjdp/****************************************************************************** 278828Sobrien 3130561Sobrien Copyright (c) 2001-2009, Intel Corporation 438889Sjdp All rights reserved. 533965Sjdp 633965Sjdp Redistribution and use in source and binary forms, with or without 733965Sjdp modification, are permitted provided that the following conditions are met: 833965Sjdp 933965Sjdp 1. Redistributions of source code must retain the above copyright notice, 1033965Sjdp this list of conditions and the following disclaimer. 1133965Sjdp 1233965Sjdp 2. Redistributions in binary form must reproduce the above copyright 1333965Sjdp notice, this list of conditions and the following disclaimer in the 1433965Sjdp documentation and/or other materials provided with the distribution. 1533965Sjdp 1633965Sjdp 3. Neither the name of the Intel Corporation nor the names of its 1733965Sjdp contributors may be used to endorse or promote products derived from 1833965Sjdp this software without specific prior written permission. 1933965Sjdp 2033965Sjdp THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2133965Sjdp AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2233965Sjdp IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2333965Sjdp ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2433965Sjdp LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2533965Sjdp CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2633965Sjdp SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2733965Sjdp INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2877298Sobrien CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2933965Sjdp ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3033965Sjdp POSSIBILITY OF SUCH DAMAGE. 3133965Sjdp 3233965Sjdp******************************************************************************/ 3333965Sjdp/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 194865 2009-06-24 17:41:29Z jfv $*/ 3433965Sjdp 3533965Sjdp/* 3633965Sjdp * 82575EB Gigabit Network Connection 3733965Sjdp * 82575EB Gigabit Backplane Connection 3833965Sjdp * 82575GB Gigabit Network Connection 3933965Sjdp * 82575GB Gigabit Network Connection 4033965Sjdp * 82576 Gigabit Network Connection 4133965Sjdp * 82576 Quad Port Gigabit Mezzanine Adapter 4233965Sjdp */ 4333965Sjdp 4433965Sjdp#include "e1000_api.h" 4533965Sjdp 4677298Sobrienstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 4733965Sjdpstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 4833965Sjdpstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 4977298Sobrienstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 5033965Sjdpstatic void e1000_release_phy_82575(struct e1000_hw *hw); 5133965Sjdpstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 5233965Sjdpstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 5333965Sjdpstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 5433965Sjdpstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 5533965Sjdpstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 5633965Sjdp u16 *duplex); 5733965Sjdpstatic s32 e1000_init_hw_82575(struct e1000_hw *hw); 5833965Sjdpstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 5933965Sjdpstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 6033965Sjdp u16 *data); 6133965Sjdpstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 6233965Sjdpstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 6333965Sjdp bool active); 6433965Sjdpstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 6577298Sobrienstatic s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 6633965Sjdpstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 6733965Sjdpstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 6833965Sjdp u32 offset, u16 data); 6933965Sjdpstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 7033965Sjdpstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 7133965Sjdpstatic s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 7233965Sjdpstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 7333965Sjdp u16 *speed, u16 *duplex); 7433965Sjdpstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 7533965Sjdpstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 7633965Sjdpstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 7733965Sjdpstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 7833965Sjdpstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 7933965Sjdpstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 8033965Sjdpvoid e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 8133965Sjdpstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 8233965Sjdp 8333965Sjdp/** 8433965Sjdp * e1000_init_phy_params_82575 - Init PHY func ptrs. 8533965Sjdp * @hw: pointer to the HW structure 8633965Sjdp **/ 8733965Sjdpstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 8833965Sjdp{ 8933965Sjdp struct e1000_phy_info *phy = &hw->phy; 9033965Sjdp s32 ret_val = E1000_SUCCESS; 9133965Sjdp 9233965Sjdp DEBUGFUNC("e1000_init_phy_params_82575"); 9333965Sjdp 9433965Sjdp if (hw->phy.media_type != e1000_media_type_copper) { 9533965Sjdp phy->type = e1000_phy_none; 9633965Sjdp goto out; 9733965Sjdp } else { 9833965Sjdp phy->ops.power_up = e1000_power_up_phy_copper; 9933965Sjdp phy->ops.power_down = e1000_power_down_phy_copper_82575; 10033965Sjdp } 10133965Sjdp 10233965Sjdp phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 10333965Sjdp phy->reset_delay_us = 100; 10477298Sobrien 10533965Sjdp phy->ops.acquire = e1000_acquire_phy_82575; 10633965Sjdp phy->ops.check_reset_block = e1000_check_reset_block_generic; 10733965Sjdp phy->ops.commit = e1000_phy_sw_reset_generic; 10833965Sjdp phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 10933965Sjdp phy->ops.release = e1000_release_phy_82575; 11033965Sjdp 11189857Sobrien if (e1000_sgmii_active_82575(hw)) { 11233965Sjdp phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 11333965Sjdp phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 11433965Sjdp phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 11533965Sjdp } else { 11633965Sjdp phy->ops.reset = e1000_phy_hw_reset_generic; 117130561Sobrien phy->ops.read_reg = e1000_read_phy_reg_igp; 118130561Sobrien phy->ops.write_reg = e1000_write_phy_reg_igp; 119130561Sobrien } 120130561Sobrien 12133965Sjdp /* Set phy->phy_addr and phy->id. */ 12233965Sjdp ret_val = e1000_get_phy_id_82575(hw); 123130561Sobrien 12433965Sjdp /* Verify phy id and set remaining function pointers */ 125130561Sobrien switch (phy->id) { 126130561Sobrien case M88E1111_I_PHY_ID: 127130561Sobrien phy->type = e1000_phy_m88; 128130561Sobrien phy->ops.check_polarity = e1000_check_polarity_m88; 129130561Sobrien phy->ops.get_info = e1000_get_phy_info_m88; 130130561Sobrien phy->ops.get_cable_length = e1000_get_cable_length_m88; 13133965Sjdp phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 132130561Sobrien break; 13333965Sjdp case IGP03E1000_E_PHY_ID: 134130561Sobrien case IGP04E1000_E_PHY_ID: 135130561Sobrien phy->type = e1000_phy_igp_3; 136130561Sobrien phy->ops.check_polarity = e1000_check_polarity_igp; 137130561Sobrien phy->ops.get_info = e1000_get_phy_info_igp; 138130561Sobrien phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 139130561Sobrien phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 14033965Sjdp phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 141130561Sobrien phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 14233965Sjdp break; 14377298Sobrien default: 14433965Sjdp ret_val = -E1000_ERR_PHY; 14589857Sobrien goto out; 14633965Sjdp } 14733965Sjdp 14833965Sjdpout: 14933965Sjdp return ret_val; 15033965Sjdp} 15133965Sjdp 15233965Sjdp/** 15333965Sjdp * e1000_init_nvm_params_82575 - Init NVM func ptrs. 15433965Sjdp * @hw: pointer to the HW structure 15577298Sobrien **/ 15633965Sjdpstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 15733965Sjdp{ 15833965Sjdp struct e1000_nvm_info *nvm = &hw->nvm; 15933965Sjdp u32 eecd = E1000_READ_REG(hw, E1000_EECD); 160130561Sobrien u16 size; 16133965Sjdp 162104834Sobrien DEBUGFUNC("e1000_init_nvm_params_82575"); 16333965Sjdp 164130561Sobrien nvm->opcode_bits = 8; 16533965Sjdp nvm->delay_usec = 1; 16633965Sjdp switch (nvm->override) { 16733965Sjdp case e1000_nvm_override_spi_large: 16833965Sjdp nvm->page_size = 32; 16994536Sobrien nvm->address_bits = 16; 17033965Sjdp break; 17133965Sjdp case e1000_nvm_override_spi_small: 17277298Sobrien nvm->page_size = 8; 17377298Sobrien nvm->address_bits = 8; 17477298Sobrien break; 17594536Sobrien default: 17677298Sobrien nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 17777298Sobrien nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 17877298Sobrien break; 17977298Sobrien } 18077298Sobrien 18177298Sobrien nvm->type = e1000_nvm_eeprom_spi; 18277298Sobrien 183130561Sobrien size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 18477298Sobrien E1000_EECD_SIZE_EX_SHIFT); 18533965Sjdp 18633965Sjdp /* 18733965Sjdp * Added to a constant, "size" becomes the left-shift value 18833965Sjdp * for setting word_size. 18933965Sjdp */ 19033965Sjdp size += NVM_WORD_SIZE_BASE_SHIFT; 19133965Sjdp 19233965Sjdp /* EEPROM access above 16k is unsupported */ 19333965Sjdp if (size > 14) 19433965Sjdp size = 14; 19533965Sjdp nvm->word_size = 1 << size; 19633965Sjdp 19733965Sjdp /* Function Pointers */ 19833965Sjdp nvm->ops.acquire = e1000_acquire_nvm_82575; 19933965Sjdp nvm->ops.read = e1000_read_nvm_eerd; 20033965Sjdp nvm->ops.release = e1000_release_nvm_82575; 20133965Sjdp nvm->ops.update = e1000_update_nvm_checksum_generic; 20233965Sjdp nvm->ops.valid_led_default = e1000_valid_led_default_82575; 20333965Sjdp nvm->ops.validate = e1000_validate_nvm_checksum_generic; 20433965Sjdp nvm->ops.write = e1000_write_nvm_spi; 20533965Sjdp 20633965Sjdp return E1000_SUCCESS; 20733965Sjdp} 20833965Sjdp 20933965Sjdp/** 21033965Sjdp * e1000_init_mac_params_82575 - Init MAC func ptrs. 21133965Sjdp * @hw: pointer to the HW structure 21233965Sjdp **/ 21333965Sjdpstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 21433965Sjdp{ 21533965Sjdp struct e1000_mac_info *mac = &hw->mac; 21633965Sjdp struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 21733965Sjdp u32 ctrl_ext = 0; 21833965Sjdp 21933965Sjdp DEBUGFUNC("e1000_init_mac_params_82575"); 22033965Sjdp 22133965Sjdp /* Set media type */ 222130561Sobrien /* 223130561Sobrien * The 82575 uses bits 22:23 for link mode. The mode can be changed 224130561Sobrien * based on the EEPROM. We cannot rely upon device ID. There 225130561Sobrien * is no distinguishable difference between fiber and internal 22633965Sjdp * SerDes mode on the 82575. There can be an external PHY attached 22733965Sjdp * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 22833965Sjdp */ 229130561Sobrien hw->phy.media_type = e1000_media_type_copper; 23033965Sjdp dev_spec->sgmii_active = FALSE; 23133965Sjdp 23233965Sjdp ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 233104834Sobrien if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 234104834Sobrien E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 235104834Sobrien hw->phy.media_type = e1000_media_type_internal_serdes; 23633965Sjdp ctrl_ext |= E1000_CTRL_I2C_ENA; 23733965Sjdp } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 238104834Sobrien dev_spec->sgmii_active = TRUE; 239104834Sobrien ctrl_ext |= E1000_CTRL_I2C_ENA; 240104834Sobrien } else { 241130561Sobrien ctrl_ext &= ~E1000_CTRL_I2C_ENA; 242130561Sobrien } 243104834Sobrien E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 244104834Sobrien 245104834Sobrien /* Set mta register count */ 246104834Sobrien mac->mta_reg_count = 128; 247104834Sobrien /* Set rar entry count */ 248104834Sobrien mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 249104834Sobrien if (mac->type == e1000_82576) 25033965Sjdp mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 251130561Sobrien /* Set if part includes ASF firmware */ 25233965Sjdp mac->asf_firmware_present = TRUE; 25333965Sjdp /* Set if manageability features are enabled. */ 25433965Sjdp mac->arc_subsystem_valid = 25533965Sjdp (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 25633965Sjdp ? TRUE : FALSE; 25733965Sjdp 25833965Sjdp /* Function pointers */ 25933965Sjdp 260130561Sobrien /* bus type/speed/width */ 26133965Sjdp mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 26233965Sjdp /* reset */ 26333965Sjdp mac->ops.reset_hw = e1000_reset_hw_82575; 26489857Sobrien /* hw initialization */ 26533965Sjdp mac->ops.init_hw = e1000_init_hw_82575; 26633965Sjdp /* link setup */ 267130561Sobrien mac->ops.setup_link = e1000_setup_link_generic; 26833965Sjdp /* physical interface link setup */ 26933965Sjdp mac->ops.setup_physical_interface = 27033965Sjdp (hw->phy.media_type == e1000_media_type_copper) 27133965Sjdp ? e1000_setup_copper_link_82575 27233965Sjdp : e1000_setup_fiber_serdes_link_82575; 27333965Sjdp /* physical interface shutdown */ 27433965Sjdp mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; 27533965Sjdp /* check for link */ 27633965Sjdp mac->ops.check_for_link = e1000_check_for_link_82575; 27733965Sjdp /* receive address register setting */ 27833965Sjdp mac->ops.rar_set = e1000_rar_set_generic; 27933965Sjdp /* read mac address */ 28033965Sjdp mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 28133965Sjdp /* multicast address update */ 28233965Sjdp mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 283130561Sobrien /* writing VFTA */ 28433965Sjdp mac->ops.write_vfta = e1000_write_vfta_generic; 28533965Sjdp /* clearing VFTA */ 28633965Sjdp mac->ops.clear_vfta = e1000_clear_vfta_generic; 28733965Sjdp /* setting MTA */ 28833965Sjdp mac->ops.mta_set = e1000_mta_set_generic; 28933965Sjdp /* ID LED init */ 29033965Sjdp mac->ops.id_led_init = e1000_id_led_init_generic; 29133965Sjdp /* blink LED */ 29233965Sjdp mac->ops.blink_led = e1000_blink_led_generic; 29333965Sjdp /* setup LED */ 29489857Sobrien mac->ops.setup_led = e1000_setup_led_generic; 29533965Sjdp /* cleanup LED */ 29633965Sjdp mac->ops.cleanup_led = e1000_cleanup_led_generic; 29733965Sjdp /* turn on/off LED */ 29833965Sjdp mac->ops.led_on = e1000_led_on_generic; 29933965Sjdp mac->ops.led_off = e1000_led_off_generic; 30033965Sjdp /* clear hardware counters */ 30133965Sjdp mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 30260484Sobrien /* link info */ 30389857Sobrien mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 30433965Sjdp 30533965Sjdp return E1000_SUCCESS; 30633965Sjdp} 30733965Sjdp 30833965Sjdp/** 30933965Sjdp * e1000_init_function_pointers_82575 - Init func ptrs. 310130561Sobrien * @hw: pointer to the HW structure 31133965Sjdp * 31233965Sjdp * Called to initialize all function pointers and parameters. 31333965Sjdp **/ 31433965Sjdpvoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 31533965Sjdp{ 31633965Sjdp DEBUGFUNC("e1000_init_function_pointers_82575"); 31789857Sobrien 31833965Sjdp hw->mac.ops.init_params = e1000_init_mac_params_82575; 31989857Sobrien hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 32033965Sjdp hw->phy.ops.init_params = e1000_init_phy_params_82575; 321130561Sobrien} 32233965Sjdp 32333965Sjdp/** 32433965Sjdp * e1000_acquire_phy_82575 - Acquire rights to access PHY 32533965Sjdp * @hw: pointer to the HW structure 32633965Sjdp * 32733965Sjdp * Acquire access rights to the correct PHY. 32833965Sjdp **/ 32933965Sjdpstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 33033965Sjdp{ 33133965Sjdp u16 mask = E1000_SWFW_PHY0_SM; 33233965Sjdp 33333965Sjdp DEBUGFUNC("e1000_acquire_phy_82575"); 33433965Sjdp 335130561Sobrien if (hw->bus.func == E1000_FUNC_1) 33633965Sjdp mask = E1000_SWFW_PHY1_SM; 33733965Sjdp 33833965Sjdp return e1000_acquire_swfw_sync_82575(hw, mask); 33933965Sjdp} 34033965Sjdp 341130561Sobrien/** 34233965Sjdp * e1000_release_phy_82575 - Release rights to access PHY 34333965Sjdp * @hw: pointer to the HW structure 34433965Sjdp * 34533965Sjdp * A wrapper to release access rights to the correct PHY. 34633965Sjdp **/ 347130561Sobrienstatic void e1000_release_phy_82575(struct e1000_hw *hw) 34833965Sjdp{ 34933965Sjdp u16 mask = E1000_SWFW_PHY0_SM; 35033965Sjdp 35133965Sjdp DEBUGFUNC("e1000_release_phy_82575"); 35233965Sjdp 35333965Sjdp if (hw->bus.func == E1000_FUNC_1) 35433965Sjdp mask = E1000_SWFW_PHY1_SM; 35533965Sjdp 35633965Sjdp e1000_release_swfw_sync_82575(hw, mask); 35733965Sjdp} 35833965Sjdp 359130561Sobrien/** 36033965Sjdp * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 36133965Sjdp * @hw: pointer to the HW structure 36233965Sjdp * @offset: register offset to be read 36333965Sjdp * @data: pointer to the read data 36433965Sjdp * 36533965Sjdp * Reads the PHY register at offset using the serial gigabit media independent 36633965Sjdp * interface and stores the retrieved information in data. 36733965Sjdp **/ 36833965Sjdpstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 36933965Sjdp u16 *data) 37033965Sjdp{ 37133965Sjdp struct e1000_phy_info *phy = &hw->phy; 37233965Sjdp u32 i, i2ccmd = 0; 37333965Sjdp 37433965Sjdp DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 37533965Sjdp 37633965Sjdp if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 37733965Sjdp DEBUGOUT1("PHY Address %u is out of range\n", offset); 37833965Sjdp return -E1000_ERR_PARAM; 37933965Sjdp } 38033965Sjdp 38133965Sjdp /* 38233965Sjdp * Set up Op-code, Phy Address, and register address in the I2CCMD 38333965Sjdp * register. The MAC will take care of interfacing with the 38433965Sjdp * PHY to retrieve the desired data. 38533965Sjdp */ 38633965Sjdp i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 38733965Sjdp (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 38833965Sjdp (E1000_I2CCMD_OPCODE_READ)); 38933965Sjdp 39033965Sjdp E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 39133965Sjdp 39233965Sjdp /* Poll the ready bit to see if the I2C read completed */ 39333965Sjdp for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 39489857Sobrien usec_delay(50); 39533965Sjdp i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 39633965Sjdp if (i2ccmd & E1000_I2CCMD_READY) 39733965Sjdp break; 39833965Sjdp } 39933965Sjdp if (!(i2ccmd & E1000_I2CCMD_READY)) { 40033965Sjdp DEBUGOUT("I2CCMD Read did not complete\n"); 40133965Sjdp return -E1000_ERR_PHY; 40233965Sjdp } 40360484Sobrien if (i2ccmd & E1000_I2CCMD_ERROR) { 40433965Sjdp DEBUGOUT("I2CCMD Error bit set\n"); 40533965Sjdp return -E1000_ERR_PHY; 40633965Sjdp } 40733965Sjdp 40833965Sjdp /* Need to byte-swap the 16-bit value. */ 40933965Sjdp *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 41033965Sjdp 41133965Sjdp return E1000_SUCCESS; 41233965Sjdp} 41333965Sjdp 41433965Sjdp/** 41533965Sjdp * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 41633965Sjdp * @hw: pointer to the HW structure 41733965Sjdp * @offset: register offset to write to 41833965Sjdp * @data: data to write at register offset 41933965Sjdp * 42033965Sjdp * Writes the data to PHY register at the offset using the serial gigabit 42189857Sobrien * media independent interface. 42233965Sjdp **/ 42389857Sobrienstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 42433965Sjdp u16 data) 42533965Sjdp{ 42633965Sjdp struct e1000_phy_info *phy = &hw->phy; 42733965Sjdp u32 i, i2ccmd = 0; 42833965Sjdp u16 phy_data_swapped; 42933965Sjdp 43033965Sjdp DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 43133965Sjdp 43233965Sjdp if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 43333965Sjdp DEBUGOUT1("PHY Address %d is out of range\n", offset); 43433965Sjdp return -E1000_ERR_PARAM; 43533965Sjdp } 43633965Sjdp 43733965Sjdp /* Swap the data bytes for the I2C interface */ 43833965Sjdp phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 43933965Sjdp 44033965Sjdp /* 44133965Sjdp * Set up Op-code, Phy Address, and register address in the I2CCMD 44233965Sjdp * register. The MAC will take care of interfacing with the 44333965Sjdp * PHY to retrieve the desired data. 44433965Sjdp */ 44589857Sobrien i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 44633965Sjdp (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 44733965Sjdp E1000_I2CCMD_OPCODE_WRITE | 44833965Sjdp phy_data_swapped); 44933965Sjdp 45033965Sjdp E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 45133965Sjdp 45233965Sjdp /* Poll the ready bit to see if the I2C read completed */ 45333965Sjdp for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 45433965Sjdp usec_delay(50); 45533965Sjdp i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 45633965Sjdp if (i2ccmd & E1000_I2CCMD_READY) 45733965Sjdp break; 45833965Sjdp } 45933965Sjdp if (!(i2ccmd & E1000_I2CCMD_READY)) { 46033965Sjdp DEBUGOUT("I2CCMD Write did not complete\n"); 46133965Sjdp return -E1000_ERR_PHY; 46233965Sjdp } 46333965Sjdp if (i2ccmd & E1000_I2CCMD_ERROR) { 46433965Sjdp DEBUGOUT("I2CCMD Error bit set\n"); 46533965Sjdp return -E1000_ERR_PHY; 46633965Sjdp } 46733965Sjdp 46833965Sjdp return E1000_SUCCESS; 46933965Sjdp} 47033965Sjdp 47133965Sjdp/** 47233965Sjdp * e1000_get_phy_id_82575 - Retrieve PHY addr and id 47333965Sjdp * @hw: pointer to the HW structure 47433965Sjdp * 47533965Sjdp * Retrieves the PHY address and ID for both PHY's which do and do not use 47633965Sjdp * sgmi interface. 47733965Sjdp **/ 47833965Sjdpstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 47933965Sjdp{ 48033965Sjdp struct e1000_phy_info *phy = &hw->phy; 48133965Sjdp s32 ret_val = E1000_SUCCESS; 48233965Sjdp u16 phy_id; 48377298Sobrien 48477298Sobrien DEBUGFUNC("e1000_get_phy_id_82575"); 48533965Sjdp 48660484Sobrien /* 48760484Sobrien * For SGMII PHYs, we try the list of possible addresses until 48860484Sobrien * we find one that works. For non-SGMII PHYs 48933965Sjdp * (e.g. integrated copper PHYs), an address of 1 should 49033965Sjdp * work. The result of this function should mean phy->phy_addr 49133965Sjdp * and phy->id are set correctly. 49233965Sjdp */ 49333965Sjdp if (!(e1000_sgmii_active_82575(hw))) { 49433965Sjdp phy->addr = 1; 49577298Sobrien ret_val = e1000_get_phy_id(hw); 49633965Sjdp goto out; 49733965Sjdp } 49833965Sjdp 49933965Sjdp /* 50033965Sjdp * The address field in the I2CCMD register is 3 bits and 0 is invalid. 50133965Sjdp * Therefore, we need to test 1-7 50233965Sjdp */ 50333965Sjdp for (phy->addr = 1; phy->addr < 8; phy->addr++) { 50433965Sjdp ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 50533965Sjdp if (ret_val == E1000_SUCCESS) { 50633965Sjdp DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 50733965Sjdp phy_id, 50889857Sobrien phy->addr); 50933965Sjdp /* 51033965Sjdp * At the time of this writing, The M88 part is 51133965Sjdp * the only supported SGMII PHY product. 51233965Sjdp */ 51333965Sjdp if (phy_id == M88_VENDOR) 51433965Sjdp break; 51533965Sjdp } else { 51633965Sjdp DEBUGOUT1("PHY address %u was unreadable\n", 51733965Sjdp phy->addr); 51833965Sjdp } 51933965Sjdp } 52033965Sjdp 52133965Sjdp /* A valid PHY type couldn't be found. */ 52233965Sjdp if (phy->addr == 8) { 52333965Sjdp phy->addr = 0; 52433965Sjdp ret_val = -E1000_ERR_PHY; 52533965Sjdp goto out; 52689857Sobrien } 52733965Sjdp 52833965Sjdp ret_val = e1000_get_phy_id(hw); 52933965Sjdp 53033965Sjdpout: 53133965Sjdp return ret_val; 53289857Sobrien} 53333965Sjdp 53433965Sjdp/** 53533965Sjdp * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 53633965Sjdp * @hw: pointer to the HW structure 53733965Sjdp * 53833965Sjdp * Resets the PHY using the serial gigabit media independent interface. 53933965Sjdp **/ 54033965Sjdpstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 54133965Sjdp{ 54233965Sjdp s32 ret_val = E1000_SUCCESS; 54333965Sjdp 54433965Sjdp DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 545130561Sobrien 54633965Sjdp /* 54733965Sjdp * This isn't a TRUE "hard" reset, but is the only reset 54833965Sjdp * available to us at this time. 54933965Sjdp */ 55033965Sjdp 55133965Sjdp DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 55233965Sjdp 55333965Sjdp if (!(hw->phy.ops.write_reg)) 55433965Sjdp goto out; 55533965Sjdp 55633965Sjdp /* 55733965Sjdp * SFP documentation requires the following to configure the SPF module 55833965Sjdp * to work on SGMII. No further documentation is given. 55933965Sjdp */ 56033965Sjdp ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 56133965Sjdp if (ret_val) 56233965Sjdp goto out; 56333965Sjdp 56433965Sjdp ret_val = hw->phy.ops.commit(hw); 56533965Sjdp 56633965Sjdpout: 56733965Sjdp return ret_val; 56833965Sjdp} 56933965Sjdp 570130561Sobrien/** 57133965Sjdp * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 57233965Sjdp * @hw: pointer to the HW structure 57333965Sjdp * @active: TRUE to enable LPLU, FALSE to disable 57433965Sjdp * 57533965Sjdp * Sets the LPLU D0 state according to the active flag. When 57633965Sjdp * activating LPLU this function also disables smart speed 57789857Sobrien * and vice versa. LPLU will not be activated unless the 57833965Sjdp * device autonegotiation advertisement meets standards of 57933965Sjdp * either 10 or 10/100 or 10/100/1000 at all duplexes. 58089857Sobrien * This is a function pointer entry point only called by 58189857Sobrien * PHY setup routines. 58233965Sjdp **/ 58333965Sjdpstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 58433965Sjdp{ 58533965Sjdp struct e1000_phy_info *phy = &hw->phy; 58633965Sjdp s32 ret_val = E1000_SUCCESS; 58733965Sjdp u16 data; 58833965Sjdp 58933965Sjdp DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 59033965Sjdp 59133965Sjdp if (!(hw->phy.ops.read_reg)) 59233965Sjdp goto out; 59333965Sjdp 59433965Sjdp ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 59533965Sjdp if (ret_val) 59633965Sjdp goto out; 59733965Sjdp 59833965Sjdp if (active) { 59933965Sjdp data |= IGP02E1000_PM_D0_LPLU; 60033965Sjdp ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 60133965Sjdp data); 60233965Sjdp if (ret_val) 60333965Sjdp goto out; 60433965Sjdp 60533965Sjdp /* When LPLU is enabled, we should disable SmartSpeed */ 60633965Sjdp ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 60733965Sjdp &data); 60833965Sjdp data &= ~IGP01E1000_PSCFR_SMART_SPEED; 60933965Sjdp ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 61033965Sjdp data); 61133965Sjdp if (ret_val) 61233965Sjdp goto out; 61333965Sjdp } else { 61433965Sjdp data &= ~IGP02E1000_PM_D0_LPLU; 615130561Sobrien ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 61633965Sjdp data); 61733965Sjdp /* 61833965Sjdp * LPLU and SmartSpeed are mutually exclusive. LPLU is used 61933965Sjdp * during Dx states where the power conservation is most 62033965Sjdp * important. During driver activity we should enable 62133965Sjdp * SmartSpeed, so performance is maintained. 62233965Sjdp */ 62333965Sjdp if (phy->smart_speed == e1000_smart_speed_on) { 62433965Sjdp ret_val = phy->ops.read_reg(hw, 62533965Sjdp IGP01E1000_PHY_PORT_CONFIG, 62633965Sjdp &data); 62733965Sjdp if (ret_val) 628130561Sobrien goto out; 62933965Sjdp 63033965Sjdp data |= IGP01E1000_PSCFR_SMART_SPEED; 63133965Sjdp ret_val = phy->ops.write_reg(hw, 63233965Sjdp IGP01E1000_PHY_PORT_CONFIG, 63333965Sjdp data); 63433965Sjdp if (ret_val) 635130561Sobrien goto out; 63633965Sjdp } else if (phy->smart_speed == e1000_smart_speed_off) { 63733965Sjdp ret_val = phy->ops.read_reg(hw, 63833965Sjdp IGP01E1000_PHY_PORT_CONFIG, 63933965Sjdp &data); 64033965Sjdp if (ret_val) 64133965Sjdp goto out; 64233965Sjdp 64333965Sjdp data &= ~IGP01E1000_PSCFR_SMART_SPEED; 644104834Sobrien ret_val = phy->ops.write_reg(hw, 64533965Sjdp IGP01E1000_PHY_PORT_CONFIG, 64633965Sjdp data); 64733965Sjdp if (ret_val) 64833965Sjdp goto out; 64933965Sjdp } 65089857Sobrien } 65133965Sjdp 65233965Sjdpout: 65333965Sjdp return ret_val; 65433965Sjdp} 65533965Sjdp 65633965Sjdp/** 65733965Sjdp * e1000_acquire_nvm_82575 - Request for access to EEPROM 65833965Sjdp * @hw: pointer to the HW structure 659104834Sobrien * 660104834Sobrien * Acquire the necessary semaphores for exclusive access to the EEPROM. 661104834Sobrien * Set the EEPROM access request bit and wait for EEPROM access grant bit. 662104834Sobrien * Return successful if access grant bit set, else clear the request for 663104834Sobrien * EEPROM access and return -E1000_ERR_NVM (-1). 664104834Sobrien **/ 665104834Sobrienstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 666104834Sobrien{ 66733965Sjdp s32 ret_val; 66860484Sobrien 66960484Sobrien DEBUGFUNC("e1000_acquire_nvm_82575"); 67060484Sobrien 67133965Sjdp ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 67233965Sjdp if (ret_val) 67333965Sjdp goto out; 67433965Sjdp 67533965Sjdp ret_val = e1000_acquire_nvm_generic(hw); 67633965Sjdp 67733965Sjdp if (ret_val) 67833965Sjdp e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 67933965Sjdp 680104834Sobrienout: 68133965Sjdp return ret_val; 68233965Sjdp} 68333965Sjdp 68433965Sjdp/** 68533965Sjdp * e1000_release_nvm_82575 - Release exclusive access to EEPROM 68689857Sobrien * @hw: pointer to the HW structure 68733965Sjdp * 68833965Sjdp * Stop any current commands to the EEPROM and clear the EEPROM request bit, 68933965Sjdp * then release the semaphores acquired. 69033965Sjdp **/ 69133965Sjdpstatic void e1000_release_nvm_82575(struct e1000_hw *hw) 69233965Sjdp{ 69333965Sjdp DEBUGFUNC("e1000_release_nvm_82575"); 69433965Sjdp 695104834Sobrien e1000_release_nvm_generic(hw); 696104834Sobrien e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 697104834Sobrien} 698104834Sobrien 699104834Sobrien/** 700104834Sobrien * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 701104834Sobrien * @hw: pointer to the HW structure 702104834Sobrien * @mask: specifies which semaphore to acquire 70333965Sjdp * 70460484Sobrien * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 70560484Sobrien * will also specify which port we're acquiring the lock for. 70660484Sobrien **/ 70733965Sjdpstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 70833965Sjdp{ 70933965Sjdp u32 swfw_sync; 71033965Sjdp u32 swmask = mask; 71133965Sjdp u32 fwmask = mask << 16; 712130561Sobrien s32 ret_val = E1000_SUCCESS; 71333965Sjdp s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 71433965Sjdp 71533965Sjdp DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 71633965Sjdp 71733965Sjdp while (i < timeout) { 71833965Sjdp if (e1000_get_hw_semaphore_generic(hw)) { 71933965Sjdp ret_val = -E1000_ERR_SWFW_SYNC; 720130561Sobrien goto out; 72133965Sjdp } 72233965Sjdp 72333965Sjdp swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 72433965Sjdp if (!(swfw_sync & (fwmask | swmask))) 72533965Sjdp break; 72633965Sjdp 72733965Sjdp /* 72833965Sjdp * Firmware currently using resource (fwmask) 72933965Sjdp * or other software thread using resource (swmask) 73033965Sjdp */ 73133965Sjdp e1000_put_hw_semaphore_generic(hw); 73233965Sjdp msec_delay_irq(5); 73333965Sjdp i++; 73433965Sjdp } 73533965Sjdp 73633965Sjdp if (i == timeout) { 73733965Sjdp DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 738130561Sobrien ret_val = -E1000_ERR_SWFW_SYNC; 73933965Sjdp goto out; 74033965Sjdp } 74189857Sobrien 74233965Sjdp swfw_sync |= swmask; 74333965Sjdp E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 74433965Sjdp 74533965Sjdp e1000_put_hw_semaphore_generic(hw); 74633965Sjdp 74733965Sjdpout: 74833965Sjdp return ret_val; 74933965Sjdp} 75033965Sjdp 75133965Sjdp/** 75289857Sobrien * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 75333965Sjdp * @hw: pointer to the HW structure 75433965Sjdp * @mask: specifies which semaphore to acquire 75533965Sjdp * 75633965Sjdp * Release the SW/FW semaphore used to access the PHY or NVM. The mask 75733965Sjdp * will also specify which port we're releasing the lock for. 75889857Sobrien **/ 75933965Sjdpstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 76033965Sjdp{ 76133965Sjdp u32 swfw_sync; 76233965Sjdp 76333965Sjdp DEBUGFUNC("e1000_release_swfw_sync_82575"); 76433965Sjdp 76533965Sjdp while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 76633965Sjdp /* Empty */ 76733965Sjdp 76833965Sjdp swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 769130561Sobrien swfw_sync &= ~mask; 77033965Sjdp E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 77133965Sjdp 77233965Sjdp e1000_put_hw_semaphore_generic(hw); 77333965Sjdp} 77433965Sjdp 77533965Sjdp/** 77633965Sjdp * e1000_get_cfg_done_82575 - Read config done bit 77733965Sjdp * @hw: pointer to the HW structure 77833965Sjdp * 77933965Sjdp * Read the management control register for the config done bit for 78033965Sjdp * completion status. NOTE: silicon which is EEPROM-less will fail trying 78133965Sjdp * to read the config done bit, so an error is *ONLY* logged and returns 78233965Sjdp * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 78333965Sjdp * would not be able to be reset or change link. 78433965Sjdp **/ 78533965Sjdpstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 78633965Sjdp{ 78733965Sjdp s32 timeout = PHY_CFG_TIMEOUT; 78833965Sjdp s32 ret_val = E1000_SUCCESS; 78933965Sjdp u32 mask = E1000_NVM_CFG_DONE_PORT_0; 79033965Sjdp 79133965Sjdp DEBUGFUNC("e1000_get_cfg_done_82575"); 79233965Sjdp 79333965Sjdp if (hw->bus.func == E1000_FUNC_1) 794130561Sobrien mask = E1000_NVM_CFG_DONE_PORT_1; 79533965Sjdp while (timeout) { 79633965Sjdp if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 79733965Sjdp break; 79833965Sjdp msec_delay(1); 79933965Sjdp timeout--; 80033965Sjdp } 80133965Sjdp if (!timeout) { 80233965Sjdp DEBUGOUT("MNG configuration cycle has not completed.\n"); 80333965Sjdp } 80433965Sjdp 80533965Sjdp /* If EEPROM is not marked present, init the PHY manually */ 80633965Sjdp if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 80733965Sjdp (hw->phy.type == e1000_phy_igp_3)) { 80833965Sjdp e1000_phy_init_script_igp3(hw); 80933965Sjdp } 81033965Sjdp 81133965Sjdp return ret_val; 81233965Sjdp} 81333965Sjdp 81433965Sjdp/** 81533965Sjdp * e1000_get_link_up_info_82575 - Get link speed/duplex info 81633965Sjdp * @hw: pointer to the HW structure 81733965Sjdp * @speed: stores the current speed 81833965Sjdp * @duplex: stores the current duplex 819130561Sobrien * 82033965Sjdp * This is a wrapper function, if using the serial gigabit media independent 82133965Sjdp * interface, use PCS to retrieve the link speed and duplex information. 82233965Sjdp * Otherwise, use the generic function to get the link speed and duplex info. 82333965Sjdp **/ 824130561Sobrienstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 82533965Sjdp u16 *duplex) 82633965Sjdp{ 82733965Sjdp s32 ret_val; 82833965Sjdp 829130561Sobrien DEBUGFUNC("e1000_get_link_up_info_82575"); 83033965Sjdp 83133965Sjdp if (hw->phy.media_type != e1000_media_type_copper || 83233965Sjdp e1000_sgmii_active_82575(hw)) { 83333965Sjdp ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 83433965Sjdp duplex); 83533965Sjdp } else { 83633965Sjdp ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 83733965Sjdp duplex); 83833965Sjdp } 83933965Sjdp 84089857Sobrien return ret_val; 841130561Sobrien} 84233965Sjdp 84333965Sjdp/** 844130561Sobrien * e1000_check_for_link_82575 - Check for link 84533965Sjdp * @hw: pointer to the HW structure 84633965Sjdp * 84733965Sjdp * If sgmii is enabled, then use the pcs register to determine link, otherwise 84833965Sjdp * use the generic interface for determining link. 84933965Sjdp **/ 850130561Sobrienstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 85133965Sjdp{ 85233965Sjdp s32 ret_val; 85333965Sjdp u16 speed, duplex; 85433965Sjdp 855130561Sobrien DEBUGFUNC("e1000_check_for_link_82575"); 85633965Sjdp 85733965Sjdp /* SGMII link check is done through the PCS register. */ 85833965Sjdp if ((hw->phy.media_type != e1000_media_type_copper) || 85933965Sjdp (e1000_sgmii_active_82575(hw))) { 86033965Sjdp ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 86133965Sjdp &duplex); 86233965Sjdp /* 86333965Sjdp * Use this flag to determine if link needs to be checked or 864130561Sobrien * not. If we have link clear the flag so that we do not 86533965Sjdp * continue to check for link. 86633965Sjdp */ 86733965Sjdp hw->mac.get_link_status = !hw->mac.serdes_has_link; 86833965Sjdp } else { 86977298Sobrien ret_val = e1000_check_for_copper_link_generic(hw); 87033965Sjdp } 871130561Sobrien 87233965Sjdp return ret_val; 87333965Sjdp} 87433965Sjdp 875130561Sobrien/** 87633965Sjdp * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 87733965Sjdp * @hw: pointer to the HW structure 87833965Sjdp * @speed: stores the current speed 87933965Sjdp * @duplex: stores the current duplex 88033965Sjdp * 88133965Sjdp * Using the physical coding sub-layer (PCS), retrieve the current speed and 88233965Sjdp * duplex, then store the values in the pointers provided. 88389857Sobrien **/ 88433965Sjdpstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 885130561Sobrien u16 *speed, u16 *duplex) 88633965Sjdp{ 88733965Sjdp struct e1000_mac_info *mac = &hw->mac; 88833965Sjdp u32 pcs; 88933965Sjdp 89033965Sjdp DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 89189857Sobrien 89289857Sobrien /* Set up defaults for the return values of this function */ 89389857Sobrien mac->serdes_has_link = FALSE; 89433965Sjdp *speed = 0; 895130561Sobrien *duplex = 0; 89633965Sjdp 89733965Sjdp /* 898130561Sobrien * Read the PCS Status register for link state. For non-copper mode, 89977298Sobrien * the status register is not accurate. The PCS status register is 90077298Sobrien * used instead. 90177298Sobrien */ 90277298Sobrien pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 90377298Sobrien 90433965Sjdp /* 90560484Sobrien * The link up bit determines when link is up on autoneg. The sync ok 90677298Sobrien * gets set once both sides sync up and agree upon link. Stable link 90733965Sjdp * can be determined by checking for both link up and link sync ok 90877298Sobrien */ 90933965Sjdp if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 91033965Sjdp mac->serdes_has_link = TRUE; 91133965Sjdp 91233965Sjdp /* Detect and store PCS speed */ 91333965Sjdp if (pcs & E1000_PCS_LSTS_SPEED_1000) { 91433965Sjdp *speed = SPEED_1000; 915130561Sobrien } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 91633965Sjdp *speed = SPEED_100; 91733965Sjdp } else { 91833965Sjdp *speed = SPEED_10; 91933965Sjdp } 92033965Sjdp 92133965Sjdp /* Detect and store PCS duplex */ 92233965Sjdp if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 92333965Sjdp *duplex = FULL_DUPLEX; 92433965Sjdp } else { 92533965Sjdp *duplex = HALF_DUPLEX; 92633965Sjdp } 92733965Sjdp } 92833965Sjdp 92933965Sjdp return E1000_SUCCESS; 93033965Sjdp} 93133965Sjdp 93233965Sjdp/** 93333965Sjdp * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down 93433965Sjdp * @hw: pointer to the HW structure 93533965Sjdp * 93633965Sjdp * In the case of fiber serdes shut down optics and PCS on driver unload 937130561Sobrien * when management pass thru is not enabled. 93833965Sjdp **/ 93933965Sjdpvoid e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) 94033965Sjdp{ 94133965Sjdp u32 reg; 94277298Sobrien u16 eeprom_data = 0; 94377298Sobrien 944130561Sobrien if (hw->phy.media_type != e1000_media_type_internal_serdes) 94533965Sjdp return; 94633965Sjdp 94789857Sobrien if (hw->bus.func == E1000_FUNC_0) 94833965Sjdp hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 94933965Sjdp else if (hw->bus.func == E1000_FUNC_1) 95033965Sjdp hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 95133965Sjdp 95294536Sobrien /* 95333965Sjdp * If APM is not enabled in the EEPROM and management interface is 95489857Sobrien * not enabled, then power down. 95533965Sjdp */ 95633965Sjdp if (!(eeprom_data & E1000_NVM_APME_82575) && 95733965Sjdp !e1000_enable_mng_pass_thru(hw)) { 95833965Sjdp /* Disable PCS to turn off link */ 95933965Sjdp reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 96033965Sjdp reg &= ~E1000_PCS_CFG_PCS_EN; 96133965Sjdp E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 96233965Sjdp 96377298Sobrien /* shutdown the laser */ 96433965Sjdp reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 96533965Sjdp reg |= E1000_CTRL_EXT_SDP7_DATA; 96633965Sjdp E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 96733965Sjdp 96833965Sjdp /* flush the write to verfiy completion */ 96933965Sjdp E1000_WRITE_FLUSH(hw); 97033965Sjdp msec_delay(1); 97133965Sjdp } 97233965Sjdp 97333965Sjdp return; 97433965Sjdp} 97533965Sjdp 97633965Sjdp/** 97733965Sjdp * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 97833965Sjdp * @hw: pointer to the HW structure 97933965Sjdp * @enable: state to enter, either enabled or disabled 98033965Sjdp * 98133965Sjdp * enables/disables L2 switch loopback functionality 98233965Sjdp **/ 98333965Sjdpvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 98433965Sjdp{ 98533965Sjdp u32 reg; 98633965Sjdp 98733965Sjdp reg = E1000_READ_REG(hw, E1000_DTXSWC); 98833965Sjdp if (enable) 98933965Sjdp reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 99033965Sjdp else 99177298Sobrien reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN); 99233965Sjdp E1000_WRITE_REG(hw, E1000_DTXSWC, reg); 99333965Sjdp} 99433965Sjdp 99533965Sjdp/** 99633965Sjdp * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 99733965Sjdp * @hw: pointer to the HW structure 99833965Sjdp * @enable: state to enter, either enabled or disabled 99933965Sjdp * 100033965Sjdp * enables/disables replication of packets across multiple pools 100189857Sobrien **/ 1002130561Sobrienvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1003130561Sobrien{ 100433965Sjdp u32 reg; 100533965Sjdp 1006130561Sobrien reg = E1000_READ_REG(hw, E1000_VT_CTL); 100733965Sjdp if (enable) 100833965Sjdp reg |= E1000_VT_CTL_VM_REPL_EN; 100933965Sjdp else 101094536Sobrien reg &= ~(E1000_VT_CTL_VM_REPL_EN); 101133965Sjdp 1012130561Sobrien E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 101394536Sobrien} 101494536Sobrien 101577298Sobrien/** 101694536Sobrien * e1000_reset_hw_82575 - Reset hardware 101794536Sobrien * @hw: pointer to the HW structure 101833965Sjdp * 101933965Sjdp * This resets the hardware into a known state. 1020130561Sobrien **/ 102133965Sjdpstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 102233965Sjdp{ 102333965Sjdp u32 ctrl, icr; 102433965Sjdp s32 ret_val; 102533965Sjdp 102660484Sobrien DEBUGFUNC("e1000_reset_hw_82575"); 102733965Sjdp 102833965Sjdp /* 102994536Sobrien * Prevent the PCI-E bus from sticking if there is no TLP connection 103094536Sobrien * on the last TLP read/write transaction when MAC is reset. 103194536Sobrien */ 103294536Sobrien ret_val = e1000_disable_pcie_master_generic(hw); 103394536Sobrien if (ret_val) { 103494536Sobrien DEBUGOUT("PCI-E Master disable polling has failed.\n"); 103594536Sobrien } 103694536Sobrien 103794536Sobrien /* set the completion timeout for interface */ 103894536Sobrien ret_val = e1000_set_pcie_completion_timeout(hw); 103994536Sobrien if (ret_val) { 104060484Sobrien DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 104133965Sjdp } 104233965Sjdp 104360484Sobrien DEBUGOUT("Masking off all interrupts\n"); 104433965Sjdp E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 104577298Sobrien 104677298Sobrien E1000_WRITE_REG(hw, E1000_RCTL, 0); 104733965Sjdp E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 104860484Sobrien E1000_WRITE_FLUSH(hw); 104933965Sjdp 105033965Sjdp msec_delay(10); 105133965Sjdp 105233965Sjdp ctrl = E1000_READ_REG(hw, E1000_CTRL); 105333965Sjdp 105460484Sobrien DEBUGOUT("Issuing a global reset to MAC\n"); 1055130561Sobrien E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 105633965Sjdp 105760484Sobrien ret_val = e1000_get_auto_rd_done_generic(hw); 105860484Sobrien if (ret_val) { 105933965Sjdp /* 106033965Sjdp * When auto config read does not complete, do not 1061130561Sobrien * return with an error. This can happen in situations 106233965Sjdp * where there is no eeprom and prevents getting link. 106333965Sjdp */ 1064130561Sobrien DEBUGOUT("Auto Read Done did not complete\n"); 106533965Sjdp } 106633965Sjdp 106733965Sjdp /* If EEPROM is not present, run manual init scripts */ 106833965Sjdp if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 106933965Sjdp e1000_reset_init_script_82575(hw); 107094536Sobrien 107133965Sjdp /* Clear any pending interrupt events. */ 107233965Sjdp E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1073130561Sobrien icr = E1000_READ_REG(hw, E1000_ICR); 107433965Sjdp 107533965Sjdp /* Install any alternate MAC address into RAR0 */ 107633965Sjdp ret_val = e1000_check_alt_mac_addr_generic(hw); 107777298Sobrien 107833965Sjdp return ret_val; 107933965Sjdp} 108033965Sjdp 108133965Sjdp/** 108233965Sjdp * e1000_init_hw_82575 - Initialize hardware 108389857Sobrien * @hw: pointer to the HW structure 108433965Sjdp * 108594536Sobrien * This inits the hardware readying it for operation. 108694536Sobrien **/ 108794536Sobrienstatic s32 e1000_init_hw_82575(struct e1000_hw *hw) 108894536Sobrien{ 1089130561Sobrien struct e1000_mac_info *mac = &hw->mac; 109033965Sjdp s32 ret_val; 109133965Sjdp u16 i, rar_count = mac->rar_entry_count; 109233965Sjdp 109333965Sjdp DEBUGFUNC("e1000_init_hw_82575"); 109460484Sobrien 109560484Sobrien /* Initialize identification LED */ 109633965Sjdp ret_val = mac->ops.id_led_init(hw); 109777298Sobrien if (ret_val) { 1098130561Sobrien DEBUGOUT("Error initializing identification LED\n"); 109933965Sjdp /* This is not fatal and we should not stop init due to this */ 110094536Sobrien } 110194536Sobrien 110294536Sobrien /* Disabling VLAN filtering */ 1103130561Sobrien DEBUGOUT("Initializing the IEEE VLAN\n"); 110494536Sobrien mac->ops.clear_vfta(hw); 1105130561Sobrien 110694536Sobrien /* Setup the receive address */ 110794536Sobrien e1000_init_rx_addrs_generic(hw, rar_count); 1108130561Sobrien 110933965Sjdp /* Zero out the Multicast HASH table */ 111033965Sjdp DEBUGOUT("Zeroing the MTA\n"); 111194536Sobrien for (i = 0; i < mac->mta_reg_count; i++) 111294536Sobrien E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 111394536Sobrien 1114130561Sobrien /* Setup link and flow control */ 111594536Sobrien ret_val = mac->ops.setup_link(hw); 1116130561Sobrien 111794536Sobrien /* 1118130561Sobrien * Clear all of the statistics registers (clear on read). It is 111933965Sjdp * important that we do this after we have tried to establish link 112033965Sjdp * because the symbol error count will increment wildly if there 112194536Sobrien * is no link. 1122130561Sobrien */ 112333965Sjdp e1000_clear_hw_cntrs_82575(hw); 112433965Sjdp 1125130561Sobrien return ret_val; 112633965Sjdp} 112733965Sjdp 1128130561Sobrien/** 112933965Sjdp * e1000_setup_copper_link_82575 - Configure copper link settings 113033965Sjdp * @hw: pointer to the HW structure 113133965Sjdp * 113233965Sjdp * Configures the link for auto-neg or forced speed and duplex. Then we check 113333965Sjdp * for link, once link is established calls to configure collision distance 113433965Sjdp * and flow control are called. 113533965Sjdp **/ 113633965Sjdpstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 113733965Sjdp{ 113833965Sjdp u32 ctrl; 1139130561Sobrien s32 ret_val; 114033965Sjdp bool link; 114133965Sjdp 114233965Sjdp DEBUGFUNC("e1000_setup_copper_link_82575"); 1143130561Sobrien 114433965Sjdp ctrl = E1000_READ_REG(hw, E1000_CTRL); 114577298Sobrien ctrl |= E1000_CTRL_SLU; 114633965Sjdp ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 114733965Sjdp E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 114833965Sjdp 114933965Sjdp switch (hw->phy.type) { 115033965Sjdp case e1000_phy_m88: 1151130561Sobrien ret_val = e1000_copper_link_setup_m88(hw); 115233965Sjdp break; 115333965Sjdp case e1000_phy_igp_3: 115433965Sjdp ret_val = e1000_copper_link_setup_igp(hw); 115533965Sjdp break; 115633965Sjdp default: 1157130561Sobrien ret_val = -E1000_ERR_PHY; 115833965Sjdp break; 115933965Sjdp } 116033965Sjdp 116133965Sjdp if (ret_val) 116233965Sjdp goto out; 116333965Sjdp 1164130561Sobrien if (hw->mac.autoneg) { 116533965Sjdp /* 116633965Sjdp * Setup autoneg and flow control advertisement 116733965Sjdp * and perform autonegotiation. 116833965Sjdp */ 116933965Sjdp ret_val = e1000_copper_link_autoneg(hw); 117033965Sjdp if (ret_val) 117133965Sjdp goto out; 117233965Sjdp } else { 117360484Sobrien /* 1174130561Sobrien * PHY will be set to 10H, 10F, 100H or 100F 117533965Sjdp * depending on user settings. 117633965Sjdp */ 117733965Sjdp DEBUGOUT("Forcing Speed and Duplex\n"); 117833965Sjdp ret_val = hw->phy.ops.force_speed_duplex(hw); 117933965Sjdp if (ret_val) { 118033965Sjdp DEBUGOUT("Error Forcing Speed and Duplex\n"); 118133965Sjdp goto out; 118233965Sjdp } 118333965Sjdp } 118433965Sjdp 118533965Sjdp ret_val = e1000_configure_pcs_link_82575(hw); 118633965Sjdp if (ret_val) 118733965Sjdp goto out; 118833965Sjdp 118933965Sjdp /* 119033965Sjdp * Check link status. Wait up to 100 microseconds for link to become 1191130561Sobrien * valid. 119233965Sjdp */ 119333965Sjdp ret_val = e1000_phy_has_link_generic(hw, 119433965Sjdp COPPER_LINK_UP_LIMIT, 119589857Sobrien 10, 119633965Sjdp &link); 119733965Sjdp if (ret_val) 119833965Sjdp goto out; 119933965Sjdp 120033965Sjdp if (link) { 120133965Sjdp DEBUGOUT("Valid link established!!!\n"); 120233965Sjdp /* Config the MAC and PHY after link is up */ 120333965Sjdp e1000_config_collision_dist_generic(hw); 120433965Sjdp ret_val = e1000_config_fc_after_link_up_generic(hw); 120533965Sjdp } else { 120633965Sjdp DEBUGOUT("Unable to establish link!!!\n"); 1207130561Sobrien } 120833965Sjdp 120933965Sjdpout: 121033965Sjdp return ret_val; 121133965Sjdp} 121233965Sjdp 121333965Sjdp/** 121433965Sjdp * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 121533965Sjdp * @hw: pointer to the HW structure 121633965Sjdp * 121733965Sjdp * Configures speed and duplex for fiber and serdes links. 121833965Sjdp **/ 121933965Sjdpstatic s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 122033965Sjdp{ 122133965Sjdp u32 reg; 122277298Sobrien 122333965Sjdp DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 122433965Sjdp 122533965Sjdp /* 122633965Sjdp * On the 82575, SerDes loopback mode persists until it is 122733965Sjdp * explicitly turned off or a power cycle is performed. A read to 122833965Sjdp * the register does not indicate its status. Therefore, we ensure 122933965Sjdp * loopback mode is disabled during initialization. 123033965Sjdp */ 123133965Sjdp E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 123260484Sobrien 123333965Sjdp /* Force link up, set 1gb */ 123433965Sjdp reg = E1000_READ_REG(hw, E1000_CTRL); 123533965Sjdp reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD; 123633965Sjdp if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 123733965Sjdp /* set both sw defined pins */ 123833965Sjdp reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 123933965Sjdp } 124089857Sobrien E1000_WRITE_REG(hw, E1000_CTRL, reg); 124189857Sobrien /* Power on phy for 82576 fiber adapters */ 124233965Sjdp if (hw->mac.type == e1000_82576) { 124333965Sjdp reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 124433965Sjdp reg &= ~E1000_CTRL_EXT_SDP7_DATA; 124533965Sjdp E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 124633965Sjdp } 124733965Sjdp 124833965Sjdp /* Set switch control to serdes energy detect */ 124933965Sjdp reg = E1000_READ_REG(hw, E1000_CONNSW); 125033965Sjdp reg |= E1000_CONNSW_ENRGSRC; 125133965Sjdp E1000_WRITE_REG(hw, E1000_CONNSW, reg); 125233965Sjdp 125389857Sobrien /* 125433965Sjdp * New SerDes mode allows for forcing speed or autonegotiating speed 125533965Sjdp * at 1gb. Autoneg should be default set by most drivers. This is the 125633965Sjdp * mode that will be compatible with older link partners and switches. 125733965Sjdp * However, both are supported by the hardware and some drivers/tools. 125833965Sjdp */ 125933965Sjdp reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 126033965Sjdp 126133965Sjdp reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 126233965Sjdp E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 126333965Sjdp 126433965Sjdp if (hw->mac.autoneg) { 126533965Sjdp /* Set PCS register for autoneg */ 126633965Sjdp reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 126733965Sjdp E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 126889857Sobrien E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 126933965Sjdp E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 127033965Sjdp DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 127133965Sjdp } else { 127233965Sjdp /* Set PCS register for forced speed */ 127333965Sjdp reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 127433965Sjdp E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 127533965Sjdp E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 127633965Sjdp E1000_PCS_LCTL_FSD | /* Force Speed */ 127733965Sjdp E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 127833965Sjdp DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 127933965Sjdp } 128033965Sjdp 128133965Sjdp if (hw->mac.type == e1000_82576) { 128233965Sjdp reg |= E1000_PCS_LCTL_FORCE_FCTRL; 128333965Sjdp e1000_force_mac_fc_generic(hw); 128433965Sjdp } 128560484Sobrien 128689857Sobrien E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1287104834Sobrien 128833965Sjdp return E1000_SUCCESS; 1289104834Sobrien} 129033965Sjdp 1291104834Sobrien/** 129233965Sjdp * e1000_valid_led_default_82575 - Verify a valid default LED config 129333965Sjdp * @hw: pointer to the HW structure 129433965Sjdp * @data: pointer to the NVM (EEPROM) 129533965Sjdp * 129633965Sjdp * Read the EEPROM for the current default LED configuration. If the 129733965Sjdp * LED configuration is not valid, set to a valid LED configuration. 129833965Sjdp **/ 129933965Sjdpstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 130033965Sjdp{ 130133965Sjdp s32 ret_val; 130233965Sjdp 130333965Sjdp DEBUGFUNC("e1000_valid_led_default_82575"); 130433965Sjdp 130533965Sjdp ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 130633965Sjdp if (ret_val) { 130733965Sjdp DEBUGOUT("NVM Read Error\n"); 130833965Sjdp goto out; 130933965Sjdp } 131033965Sjdp 131133965Sjdp if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 131233965Sjdp switch(hw->phy.media_type) { 131333965Sjdp case e1000_media_type_internal_serdes: 131433965Sjdp *data = ID_LED_DEFAULT_82575_SERDES; 131533965Sjdp break; 131633965Sjdp case e1000_media_type_copper: 131733965Sjdp default: 131833965Sjdp *data = ID_LED_DEFAULT; 131933965Sjdp break; 132033965Sjdp } 132133965Sjdp } 132233965Sjdpout: 132333965Sjdp return ret_val; 132433965Sjdp} 132533965Sjdp 132633965Sjdp/** 132733965Sjdp * e1000_configure_pcs_link_82575 - Configure PCS link 132833965Sjdp * @hw: pointer to the HW structure 132933965Sjdp * 133033965Sjdp * Configure the physical coding sub-layer (PCS) link. The PCS link is 133133965Sjdp * only used on copper connections where the serialized gigabit media 133233965Sjdp * independent interface (sgmii) is being used. Configures the link 133333965Sjdp * for auto-negotiation or forces speed/duplex. 133433965Sjdp **/ 133533965Sjdpstatic s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 133633965Sjdp{ 133733965Sjdp struct e1000_mac_info *mac = &hw->mac; 133833965Sjdp u32 reg = 0; 133933965Sjdp 134033965Sjdp DEBUGFUNC("e1000_configure_pcs_link_82575"); 134133965Sjdp 134233965Sjdp if (hw->phy.media_type != e1000_media_type_copper || 134333965Sjdp !(e1000_sgmii_active_82575(hw))) 134433965Sjdp goto out; 134560484Sobrien 134677298Sobrien /* For SGMII, we need to issue a PCS autoneg restart */ 134733965Sjdp reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 134833965Sjdp 134933965Sjdp /* AN time out should be disabled for SGMII mode */ 135033965Sjdp reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 135133965Sjdp 135233965Sjdp if (mac->autoneg) { 135333965Sjdp /* Make sure forced speed and force link are not set */ 135433965Sjdp reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 135533965Sjdp 135633965Sjdp /* 135733965Sjdp * The PHY should be setup prior to calling this function. 135833965Sjdp * All we need to do is restart autoneg and enable autoneg. 135933965Sjdp */ 136033965Sjdp reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 136133965Sjdp } else { 136233965Sjdp /* Set PCS register for forced speed */ 136333965Sjdp 136433965Sjdp /* Turn off bits for full duplex, speed, and autoneg */ 136533965Sjdp reg &= ~(E1000_PCS_LCTL_FSV_1000 | 136633965Sjdp E1000_PCS_LCTL_FSV_100 | 136733965Sjdp E1000_PCS_LCTL_FDV_FULL | 136833965Sjdp E1000_PCS_LCTL_AN_ENABLE); 136933965Sjdp 137033965Sjdp /* Check for duplex first */ 137133965Sjdp if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 137233965Sjdp reg |= E1000_PCS_LCTL_FDV_FULL; 137333965Sjdp 137433965Sjdp /* Now set speed */ 137533965Sjdp if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 137633965Sjdp reg |= E1000_PCS_LCTL_FSV_100; 137733965Sjdp 137833965Sjdp /* Force speed and force link */ 137933965Sjdp reg |= E1000_PCS_LCTL_FSD | 138033965Sjdp E1000_PCS_LCTL_FORCE_LINK | 138133965Sjdp E1000_PCS_LCTL_FLV_LINK_UP; 138233965Sjdp 138333965Sjdp DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 138433965Sjdp reg); 138533965Sjdp } 138633965Sjdp E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 138733965Sjdp 138833965Sjdpout: 138933965Sjdp return E1000_SUCCESS; 139033965Sjdp} 139133965Sjdp 139233965Sjdp/** 139333965Sjdp * e1000_sgmii_active_82575 - Return sgmii state 139433965Sjdp * @hw: pointer to the HW structure 139533965Sjdp * 139633965Sjdp * 82575 silicon has a serialized gigabit media independent interface (sgmii) 139733965Sjdp * which can be enabled for use in the embedded applications. Simply 139833965Sjdp * return the current state of the sgmii interface. 139933965Sjdp **/ 140060484Sobrienstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw) 140177298Sobrien{ 140233965Sjdp struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 140333965Sjdp return dev_spec->sgmii_active; 1404} 1405 1406/** 1407 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1408 * @hw: pointer to the HW structure 1409 * 1410 * Inits recommended HW defaults after a reset when there is no EEPROM 1411 * detected. This is only for the 82575. 1412 **/ 1413static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1414{ 1415 DEBUGFUNC("e1000_reset_init_script_82575"); 1416 1417 if (hw->mac.type == e1000_82575) { 1418 DEBUGOUT("Running reset init script for 82575\n"); 1419 /* SerDes configuration via SERDESCTRL */ 1420 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1421 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1422 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1423 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1424 1425 /* CCM configuration via CCMCTL register */ 1426 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1427 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1428 1429 /* PCIe lanes configuration */ 1430 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1431 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1432 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1433 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1434 1435 /* PCIe PLL Configuration */ 1436 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1437 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1438 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1439 } 1440 1441 return E1000_SUCCESS; 1442} 1443 1444/** 1445 * e1000_read_mac_addr_82575 - Read device MAC address 1446 * @hw: pointer to the HW structure 1447 **/ 1448static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1449{ 1450 s32 ret_val = E1000_SUCCESS; 1451 1452 DEBUGFUNC("e1000_read_mac_addr_82575"); 1453 1454 /* 1455 * If there's an alternate MAC address place it in RAR0 1456 * so that it will override the Si installed default perm 1457 * address. 1458 */ 1459 ret_val = e1000_check_alt_mac_addr_generic(hw); 1460 if (ret_val) 1461 goto out; 1462 1463 ret_val = e1000_read_mac_addr_generic(hw); 1464 1465out: 1466 return ret_val; 1467} 1468 1469/** 1470 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1471 * @hw: pointer to the HW structure 1472 * 1473 * In the case of a PHY power down to save power, or to turn off link during a 1474 * driver unload, or wake on lan is not enabled, remove the link. 1475 **/ 1476static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1477{ 1478 struct e1000_phy_info *phy = &hw->phy; 1479 struct e1000_mac_info *mac = &hw->mac; 1480 1481 if (!(phy->ops.check_reset_block)) 1482 return; 1483 1484 /* If the management interface is not enabled, then power down */ 1485 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1486 e1000_power_down_phy_copper(hw); 1487 1488 return; 1489} 1490 1491/** 1492 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1493 * @hw: pointer to the HW structure 1494 * 1495 * Clears the hardware counters by reading the counter registers. 1496 **/ 1497static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1498{ 1499 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1500 1501 e1000_clear_hw_cntrs_base_generic(hw); 1502 1503 E1000_READ_REG(hw, E1000_PRC64); 1504 E1000_READ_REG(hw, E1000_PRC127); 1505 E1000_READ_REG(hw, E1000_PRC255); 1506 E1000_READ_REG(hw, E1000_PRC511); 1507 E1000_READ_REG(hw, E1000_PRC1023); 1508 E1000_READ_REG(hw, E1000_PRC1522); 1509 E1000_READ_REG(hw, E1000_PTC64); 1510 E1000_READ_REG(hw, E1000_PTC127); 1511 E1000_READ_REG(hw, E1000_PTC255); 1512 E1000_READ_REG(hw, E1000_PTC511); 1513 E1000_READ_REG(hw, E1000_PTC1023); 1514 E1000_READ_REG(hw, E1000_PTC1522); 1515 1516 E1000_READ_REG(hw, E1000_ALGNERRC); 1517 E1000_READ_REG(hw, E1000_RXERRC); 1518 E1000_READ_REG(hw, E1000_TNCRS); 1519 E1000_READ_REG(hw, E1000_CEXTERR); 1520 E1000_READ_REG(hw, E1000_TSCTC); 1521 E1000_READ_REG(hw, E1000_TSCTFC); 1522 1523 E1000_READ_REG(hw, E1000_MGTPRC); 1524 E1000_READ_REG(hw, E1000_MGTPDC); 1525 E1000_READ_REG(hw, E1000_MGTPTC); 1526 1527 E1000_READ_REG(hw, E1000_IAC); 1528 E1000_READ_REG(hw, E1000_ICRXOC); 1529 1530 E1000_READ_REG(hw, E1000_ICRXPTC); 1531 E1000_READ_REG(hw, E1000_ICRXATC); 1532 E1000_READ_REG(hw, E1000_ICTXPTC); 1533 E1000_READ_REG(hw, E1000_ICTXATC); 1534 E1000_READ_REG(hw, E1000_ICTXQEC); 1535 E1000_READ_REG(hw, E1000_ICTXQMTC); 1536 E1000_READ_REG(hw, E1000_ICRXDMTC); 1537 1538 E1000_READ_REG(hw, E1000_CBTMPC); 1539 E1000_READ_REG(hw, E1000_HTDPMC); 1540 E1000_READ_REG(hw, E1000_CBRMPC); 1541 E1000_READ_REG(hw, E1000_RPTHC); 1542 E1000_READ_REG(hw, E1000_HGPTC); 1543 E1000_READ_REG(hw, E1000_HTCBDPC); 1544 E1000_READ_REG(hw, E1000_HGORCL); 1545 E1000_READ_REG(hw, E1000_HGORCH); 1546 E1000_READ_REG(hw, E1000_HGOTCL); 1547 E1000_READ_REG(hw, E1000_HGOTCH); 1548 E1000_READ_REG(hw, E1000_LENERRS); 1549 1550 /* This register should not be read in copper configurations */ 1551 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1552 E1000_READ_REG(hw, E1000_SCVPC); 1553} 1554 1555/** 1556 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1557 * @hw: pointer to the HW structure 1558 * 1559 * After rx enable if managability is enabled then there is likely some 1560 * bad data at the start of the fifo and possibly in the DMA fifo. This 1561 * function clears the fifos and flushes any packets that came in as rx was 1562 * being enabled. 1563 **/ 1564void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1565{ 1566 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1567 int i, ms_wait; 1568 1569 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1570 if (hw->mac.type != e1000_82575 || 1571 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1572 return; 1573 1574 /* Disable all RX queues */ 1575 for (i = 0; i < 4; i++) { 1576 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1577 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1578 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1579 } 1580 /* Poll all queues to verify they have shut down */ 1581 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1582 msec_delay(1); 1583 rx_enabled = 0; 1584 for (i = 0; i < 4; i++) 1585 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1586 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1587 break; 1588 } 1589 1590 if (ms_wait == 10) 1591 DEBUGOUT("Queue disable timed out after 10ms\n"); 1592 1593 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1594 * incoming packets are rejected. Set enable and wait 2ms so that 1595 * any packet that was coming in as RCTL.EN was set is flushed 1596 */ 1597 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1598 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1599 1600 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1601 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1602 1603 rctl = E1000_READ_REG(hw, E1000_RCTL); 1604 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1605 temp_rctl |= E1000_RCTL_LPE; 1606 1607 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1608 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1609 E1000_WRITE_FLUSH(hw); 1610 msec_delay(2); 1611 1612 /* Enable RX queues that were previously enabled and restore our 1613 * previous state 1614 */ 1615 for (i = 0; i < 4; i++) 1616 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1617 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1618 E1000_WRITE_FLUSH(hw); 1619 1620 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1621 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1622 1623 /* Flush receive errors generated by workaround */ 1624 E1000_READ_REG(hw, E1000_ROC); 1625 E1000_READ_REG(hw, E1000_RNBC); 1626 E1000_READ_REG(hw, E1000_MPC); 1627} 1628 1629/** 1630 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1631 * @hw: pointer to the HW structure 1632 * 1633 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1634 * however the hardware default for these parts is 500us to 1ms which is less 1635 * than the 10ms recommended by the pci-e spec. To address this we need to 1636 * increase the value to either 10ms to 200ms for capability version 1 config, 1637 * or 16ms to 55ms for version 2. 1638 **/ 1639static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1640{ 1641 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1642 s32 ret_val = E1000_SUCCESS; 1643 u16 pcie_devctl2; 1644 1645 /* only take action if timeout value is defaulted to 0 */ 1646 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1647 goto out; 1648 1649 /* 1650 * if capababilities version is type 1 we can write the 1651 * timeout of 10ms to 200ms through the GCR register 1652 */ 1653 if (!(gcr & E1000_GCR_CAP_VER2)) { 1654 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1655 goto out; 1656 } 1657 1658 /* 1659 * for version 2 capabilities we need to write the config space 1660 * directly in order to set the completion timeout value for 1661 * 16ms to 55ms 1662 */ 1663 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1664 &pcie_devctl2); 1665 if (ret_val) 1666 goto out; 1667 1668 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1669 1670 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1671 &pcie_devctl2); 1672out: 1673 /* disable completion timeout resend */ 1674 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1675 1676 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1677 return ret_val; 1678} 1679 1680