e1000_82575.c revision 190872
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 190872 2009-04-10 00:05:46Z jfv $*/ 34 35/* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82575GB Gigabit Network Connection 40 * 82576 Gigabit Network Connection 41 */ 42 43#include "e1000_api.h" 44 45static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 46static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 47static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 48static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 49static void e1000_release_phy_82575(struct e1000_hw *hw); 50static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 51static void e1000_release_nvm_82575(struct e1000_hw *hw); 52static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 53static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 54static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 55 u16 *duplex); 56static s32 e1000_init_hw_82575(struct e1000_hw *hw); 57static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 58static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 59 u16 *data); 60static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 61static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 62 bool active); 63static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 64static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 65static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 66static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 67 u32 offset, u16 data); 68static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 69static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 70static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 71static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 72 u16 *speed, u16 *duplex); 73static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 74static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 75static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 76static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 77static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 78static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 79void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 80 81/** 82 * e1000_init_phy_params_82575 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 86{ 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82575"); 91 92 if (hw->phy.media_type != e1000_media_type_copper) { 93 phy->type = e1000_phy_none; 94 goto out; 95 } else { 96 phy->ops.power_up = e1000_power_up_phy_copper; 97 phy->ops.power_down = e1000_power_down_phy_copper_82575; 98 } 99 100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 101 phy->reset_delay_us = 100; 102 103 phy->ops.acquire = e1000_acquire_phy_82575; 104 phy->ops.check_reset_block = e1000_check_reset_block_generic; 105 phy->ops.commit = e1000_phy_sw_reset_generic; 106 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 107 phy->ops.release = e1000_release_phy_82575; 108 109 if (e1000_sgmii_active_82575(hw)) { 110 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 111 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 112 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 113 } else { 114 phy->ops.reset = e1000_phy_hw_reset_generic; 115 phy->ops.read_reg = e1000_read_phy_reg_igp; 116 phy->ops.write_reg = e1000_write_phy_reg_igp; 117 } 118 119 /* Set phy->phy_addr and phy->id. */ 120 ret_val = e1000_get_phy_id_82575(hw); 121 122 /* Verify phy id and set remaining function pointers */ 123 switch (phy->id) { 124 case M88E1111_I_PHY_ID: 125 phy->type = e1000_phy_m88; 126 phy->ops.check_polarity = e1000_check_polarity_m88; 127 phy->ops.get_info = e1000_get_phy_info_m88; 128 phy->ops.get_cable_length = e1000_get_cable_length_m88; 129 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 130 break; 131 case IGP03E1000_E_PHY_ID: 132 case IGP04E1000_E_PHY_ID: 133 phy->type = e1000_phy_igp_3; 134 phy->ops.check_polarity = e1000_check_polarity_igp; 135 phy->ops.get_info = e1000_get_phy_info_igp; 136 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 138 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 139 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 140 break; 141 default: 142 ret_val = -E1000_ERR_PHY; 143 goto out; 144 } 145 146out: 147 return ret_val; 148} 149 150/** 151 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 152 * @hw: pointer to the HW structure 153 **/ 154static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 155{ 156 struct e1000_nvm_info *nvm = &hw->nvm; 157 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 158 u16 size; 159 160 DEBUGFUNC("e1000_init_nvm_params_82575"); 161 162 nvm->opcode_bits = 8; 163 nvm->delay_usec = 1; 164 switch (nvm->override) { 165 case e1000_nvm_override_spi_large: 166 nvm->page_size = 32; 167 nvm->address_bits = 16; 168 break; 169 case e1000_nvm_override_spi_small: 170 nvm->page_size = 8; 171 nvm->address_bits = 8; 172 break; 173 default: 174 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 175 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 176 break; 177 } 178 179 nvm->type = e1000_nvm_eeprom_spi; 180 181 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 182 E1000_EECD_SIZE_EX_SHIFT); 183 184 /* 185 * Added to a constant, "size" becomes the left-shift value 186 * for setting word_size. 187 */ 188 size += NVM_WORD_SIZE_BASE_SHIFT; 189 190 /* EEPROM access above 16k is unsupported */ 191 if (size > 14) 192 size = 14; 193 nvm->word_size = 1 << size; 194 195 /* Function Pointers */ 196 nvm->ops.acquire = e1000_acquire_nvm_82575; 197 nvm->ops.read = e1000_read_nvm_eerd; 198 nvm->ops.release = e1000_release_nvm_82575; 199 nvm->ops.update = e1000_update_nvm_checksum_generic; 200 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 201 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 202 nvm->ops.write = e1000_write_nvm_spi; 203 204 return E1000_SUCCESS; 205} 206 207/** 208 * e1000_init_mac_params_82575 - Init MAC func ptrs. 209 * @hw: pointer to the HW structure 210 **/ 211static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 212{ 213 struct e1000_mac_info *mac = &hw->mac; 214 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 215 u32 ctrl_ext = 0; 216 217 DEBUGFUNC("e1000_init_mac_params_82575"); 218 219 /* Set media type */ 220 /* 221 * The 82575 uses bits 22:23 for link mode. The mode can be changed 222 * based on the EEPROM. We cannot rely upon device ID. There 223 * is no distinguishable difference between fiber and internal 224 * SerDes mode on the 82575. There can be an external PHY attached 225 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 226 */ 227 hw->phy.media_type = e1000_media_type_copper; 228 dev_spec->sgmii_active = FALSE; 229 230 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 231 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 232 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 233 hw->phy.media_type = e1000_media_type_internal_serdes; 234 ctrl_ext |= E1000_CTRL_I2C_ENA; 235 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 236 dev_spec->sgmii_active = TRUE; 237 ctrl_ext |= E1000_CTRL_I2C_ENA; 238 } else { 239 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 240 } 241 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 242 243 /* Set mta register count */ 244 mac->mta_reg_count = 128; 245 /* Set rar entry count */ 246 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 247 if (mac->type == e1000_82576) 248 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 249 /* Set if part includes ASF firmware */ 250 mac->asf_firmware_present = TRUE; 251 /* Set if manageability features are enabled. */ 252 mac->arc_subsystem_valid = 253 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 254 ? TRUE : FALSE; 255 256 /* Function pointers */ 257 258 /* bus type/speed/width */ 259 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 260 /* reset */ 261 mac->ops.reset_hw = e1000_reset_hw_82575; 262 /* hw initialization */ 263 mac->ops.init_hw = e1000_init_hw_82575; 264 /* link setup */ 265 mac->ops.setup_link = e1000_setup_link_generic; 266 /* physical interface link setup */ 267 mac->ops.setup_physical_interface = 268 (hw->phy.media_type == e1000_media_type_copper) 269 ? e1000_setup_copper_link_82575 270 : e1000_setup_fiber_serdes_link_82575; 271 /* physical interface shutdown */ 272 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; 273 /* check for link */ 274 mac->ops.check_for_link = e1000_check_for_link_82575; 275 /* receive address register setting */ 276 mac->ops.rar_set = e1000_rar_set_generic; 277 /* read mac address */ 278 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 279 /* multicast address update */ 280 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 281 /* writing VFTA */ 282 mac->ops.write_vfta = e1000_write_vfta_generic; 283 /* clearing VFTA */ 284 mac->ops.clear_vfta = e1000_clear_vfta_generic; 285 /* setting MTA */ 286 mac->ops.mta_set = e1000_mta_set_generic; 287 /* ID LED init */ 288 mac->ops.id_led_init = e1000_id_led_init_generic; 289 /* blink LED */ 290 mac->ops.blink_led = e1000_blink_led_generic; 291 /* setup LED */ 292 mac->ops.setup_led = e1000_setup_led_generic; 293 /* cleanup LED */ 294 mac->ops.cleanup_led = e1000_cleanup_led_generic; 295 /* turn on/off LED */ 296 mac->ops.led_on = e1000_led_on_generic; 297 mac->ops.led_off = e1000_led_off_generic; 298 /* clear hardware counters */ 299 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 300 /* link info */ 301 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 302 303 return E1000_SUCCESS; 304} 305 306/** 307 * e1000_init_function_pointers_82575 - Init func ptrs. 308 * @hw: pointer to the HW structure 309 * 310 * Called to initialize all function pointers and parameters. 311 **/ 312void e1000_init_function_pointers_82575(struct e1000_hw *hw) 313{ 314 DEBUGFUNC("e1000_init_function_pointers_82575"); 315 316 hw->mac.ops.init_params = e1000_init_mac_params_82575; 317 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 318 hw->phy.ops.init_params = e1000_init_phy_params_82575; 319} 320 321/** 322 * e1000_acquire_phy_82575 - Acquire rights to access PHY 323 * @hw: pointer to the HW structure 324 * 325 * Acquire access rights to the correct PHY. 326 **/ 327static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 328{ 329 u16 mask; 330 331 DEBUGFUNC("e1000_acquire_phy_82575"); 332 333 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 334 335 return e1000_acquire_swfw_sync_82575(hw, mask); 336} 337 338/** 339 * e1000_release_phy_82575 - Release rights to access PHY 340 * @hw: pointer to the HW structure 341 * 342 * A wrapper to release access rights to the correct PHY. 343 **/ 344static void e1000_release_phy_82575(struct e1000_hw *hw) 345{ 346 u16 mask; 347 348 DEBUGFUNC("e1000_release_phy_82575"); 349 350 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 351 e1000_release_swfw_sync_82575(hw, mask); 352} 353 354/** 355 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 356 * @hw: pointer to the HW structure 357 * @offset: register offset to be read 358 * @data: pointer to the read data 359 * 360 * Reads the PHY register at offset using the serial gigabit media independent 361 * interface and stores the retrieved information in data. 362 **/ 363static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 364 u16 *data) 365{ 366 struct e1000_phy_info *phy = &hw->phy; 367 u32 i, i2ccmd = 0; 368 369 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 370 371 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 372 DEBUGOUT1("PHY Address %u is out of range\n", offset); 373 return -E1000_ERR_PARAM; 374 } 375 376 /* 377 * Set up Op-code, Phy Address, and register address in the I2CCMD 378 * register. The MAC will take care of interfacing with the 379 * PHY to retrieve the desired data. 380 */ 381 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 382 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 383 (E1000_I2CCMD_OPCODE_READ)); 384 385 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 386 387 /* Poll the ready bit to see if the I2C read completed */ 388 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 389 usec_delay(50); 390 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 391 if (i2ccmd & E1000_I2CCMD_READY) 392 break; 393 } 394 if (!(i2ccmd & E1000_I2CCMD_READY)) { 395 DEBUGOUT("I2CCMD Read did not complete\n"); 396 return -E1000_ERR_PHY; 397 } 398 if (i2ccmd & E1000_I2CCMD_ERROR) { 399 DEBUGOUT("I2CCMD Error bit set\n"); 400 return -E1000_ERR_PHY; 401 } 402 403 /* Need to byte-swap the 16-bit value. */ 404 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 405 406 return E1000_SUCCESS; 407} 408 409/** 410 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 411 * @hw: pointer to the HW structure 412 * @offset: register offset to write to 413 * @data: data to write at register offset 414 * 415 * Writes the data to PHY register at the offset using the serial gigabit 416 * media independent interface. 417 **/ 418static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 419 u16 data) 420{ 421 struct e1000_phy_info *phy = &hw->phy; 422 u32 i, i2ccmd = 0; 423 u16 phy_data_swapped; 424 425 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 426 427 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 428 DEBUGOUT1("PHY Address %d is out of range\n", offset); 429 return -E1000_ERR_PARAM; 430 } 431 432 /* Swap the data bytes for the I2C interface */ 433 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 434 435 /* 436 * Set up Op-code, Phy Address, and register address in the I2CCMD 437 * register. The MAC will take care of interfacing with the 438 * PHY to retrieve the desired data. 439 */ 440 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 441 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 442 E1000_I2CCMD_OPCODE_WRITE | 443 phy_data_swapped); 444 445 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 446 447 /* Poll the ready bit to see if the I2C read completed */ 448 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 449 usec_delay(50); 450 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 451 if (i2ccmd & E1000_I2CCMD_READY) 452 break; 453 } 454 if (!(i2ccmd & E1000_I2CCMD_READY)) { 455 DEBUGOUT("I2CCMD Write did not complete\n"); 456 return -E1000_ERR_PHY; 457 } 458 if (i2ccmd & E1000_I2CCMD_ERROR) { 459 DEBUGOUT("I2CCMD Error bit set\n"); 460 return -E1000_ERR_PHY; 461 } 462 463 return E1000_SUCCESS; 464} 465 466/** 467 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 468 * @hw: pointer to the HW structure 469 * 470 * Retrieves the PHY address and ID for both PHY's which do and do not use 471 * sgmi interface. 472 **/ 473static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 474{ 475 struct e1000_phy_info *phy = &hw->phy; 476 s32 ret_val = E1000_SUCCESS; 477 u16 phy_id; 478 479 DEBUGFUNC("e1000_get_phy_id_82575"); 480 481 /* 482 * For SGMII PHYs, we try the list of possible addresses until 483 * we find one that works. For non-SGMII PHYs 484 * (e.g. integrated copper PHYs), an address of 1 should 485 * work. The result of this function should mean phy->phy_addr 486 * and phy->id are set correctly. 487 */ 488 if (!(e1000_sgmii_active_82575(hw))) { 489 phy->addr = 1; 490 ret_val = e1000_get_phy_id(hw); 491 goto out; 492 } 493 494 /* 495 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 496 * Therefore, we need to test 1-7 497 */ 498 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 499 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 500 if (ret_val == E1000_SUCCESS) { 501 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 502 phy_id, 503 phy->addr); 504 /* 505 * At the time of this writing, The M88 part is 506 * the only supported SGMII PHY product. 507 */ 508 if (phy_id == M88_VENDOR) 509 break; 510 } else { 511 DEBUGOUT1("PHY address %u was unreadable\n", 512 phy->addr); 513 } 514 } 515 516 /* A valid PHY type couldn't be found. */ 517 if (phy->addr == 8) { 518 phy->addr = 0; 519 ret_val = -E1000_ERR_PHY; 520 goto out; 521 } 522 523 ret_val = e1000_get_phy_id(hw); 524 525out: 526 return ret_val; 527} 528 529/** 530 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 531 * @hw: pointer to the HW structure 532 * 533 * Resets the PHY using the serial gigabit media independent interface. 534 **/ 535static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 536{ 537 s32 ret_val = E1000_SUCCESS; 538 539 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 540 541 /* 542 * This isn't a TRUE "hard" reset, but is the only reset 543 * available to us at this time. 544 */ 545 546 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 547 548 if (!(hw->phy.ops.write_reg)) 549 goto out; 550 551 /* 552 * SFP documentation requires the following to configure the SPF module 553 * to work on SGMII. No further documentation is given. 554 */ 555 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 556 if (ret_val) 557 goto out; 558 559 ret_val = hw->phy.ops.commit(hw); 560 561out: 562 return ret_val; 563} 564 565/** 566 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 567 * @hw: pointer to the HW structure 568 * @active: TRUE to enable LPLU, FALSE to disable 569 * 570 * Sets the LPLU D0 state according to the active flag. When 571 * activating LPLU this function also disables smart speed 572 * and vice versa. LPLU will not be activated unless the 573 * device autonegotiation advertisement meets standards of 574 * either 10 or 10/100 or 10/100/1000 at all duplexes. 575 * This is a function pointer entry point only called by 576 * PHY setup routines. 577 **/ 578static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 579{ 580 struct e1000_phy_info *phy = &hw->phy; 581 s32 ret_val = E1000_SUCCESS; 582 u16 data; 583 584 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 585 586 if (!(hw->phy.ops.read_reg)) 587 goto out; 588 589 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 590 if (ret_val) 591 goto out; 592 593 if (active) { 594 data |= IGP02E1000_PM_D0_LPLU; 595 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 596 data); 597 if (ret_val) 598 goto out; 599 600 /* When LPLU is enabled, we should disable SmartSpeed */ 601 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 602 &data); 603 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 604 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 605 data); 606 if (ret_val) 607 goto out; 608 } else { 609 data &= ~IGP02E1000_PM_D0_LPLU; 610 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 611 data); 612 /* 613 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 614 * during Dx states where the power conservation is most 615 * important. During driver activity we should enable 616 * SmartSpeed, so performance is maintained. 617 */ 618 if (phy->smart_speed == e1000_smart_speed_on) { 619 ret_val = phy->ops.read_reg(hw, 620 IGP01E1000_PHY_PORT_CONFIG, 621 &data); 622 if (ret_val) 623 goto out; 624 625 data |= IGP01E1000_PSCFR_SMART_SPEED; 626 ret_val = phy->ops.write_reg(hw, 627 IGP01E1000_PHY_PORT_CONFIG, 628 data); 629 if (ret_val) 630 goto out; 631 } else if (phy->smart_speed == e1000_smart_speed_off) { 632 ret_val = phy->ops.read_reg(hw, 633 IGP01E1000_PHY_PORT_CONFIG, 634 &data); 635 if (ret_val) 636 goto out; 637 638 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 639 ret_val = phy->ops.write_reg(hw, 640 IGP01E1000_PHY_PORT_CONFIG, 641 data); 642 if (ret_val) 643 goto out; 644 } 645 } 646 647out: 648 return ret_val; 649} 650 651/** 652 * e1000_acquire_nvm_82575 - Request for access to EEPROM 653 * @hw: pointer to the HW structure 654 * 655 * Acquire the necessary semaphores for exclusive access to the EEPROM. 656 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 657 * Return successful if access grant bit set, else clear the request for 658 * EEPROM access and return -E1000_ERR_NVM (-1). 659 **/ 660static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 661{ 662 s32 ret_val; 663 664 DEBUGFUNC("e1000_acquire_nvm_82575"); 665 666 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 667 if (ret_val) 668 goto out; 669 670 ret_val = e1000_acquire_nvm_generic(hw); 671 672 if (ret_val) 673 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 674 675out: 676 return ret_val; 677} 678 679/** 680 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 681 * @hw: pointer to the HW structure 682 * 683 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 684 * then release the semaphores acquired. 685 **/ 686static void e1000_release_nvm_82575(struct e1000_hw *hw) 687{ 688 DEBUGFUNC("e1000_release_nvm_82575"); 689 690 e1000_release_nvm_generic(hw); 691 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 692} 693 694/** 695 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 696 * @hw: pointer to the HW structure 697 * @mask: specifies which semaphore to acquire 698 * 699 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 700 * will also specify which port we're acquiring the lock for. 701 **/ 702static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 703{ 704 u32 swfw_sync; 705 u32 swmask = mask; 706 u32 fwmask = mask << 16; 707 s32 ret_val = E1000_SUCCESS; 708 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 709 710 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 711 712 while (i < timeout) { 713 if (e1000_get_hw_semaphore_generic(hw)) { 714 ret_val = -E1000_ERR_SWFW_SYNC; 715 goto out; 716 } 717 718 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 719 if (!(swfw_sync & (fwmask | swmask))) 720 break; 721 722 /* 723 * Firmware currently using resource (fwmask) 724 * or other software thread using resource (swmask) 725 */ 726 e1000_put_hw_semaphore_generic(hw); 727 msec_delay_irq(5); 728 i++; 729 } 730 731 if (i == timeout) { 732 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 733 ret_val = -E1000_ERR_SWFW_SYNC; 734 goto out; 735 } 736 737 swfw_sync |= swmask; 738 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 739 740 e1000_put_hw_semaphore_generic(hw); 741 742out: 743 return ret_val; 744} 745 746/** 747 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 748 * @hw: pointer to the HW structure 749 * @mask: specifies which semaphore to acquire 750 * 751 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 752 * will also specify which port we're releasing the lock for. 753 **/ 754static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 755{ 756 u32 swfw_sync; 757 758 DEBUGFUNC("e1000_release_swfw_sync_82575"); 759 760 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 761 /* Empty */ 762 763 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 764 swfw_sync &= ~mask; 765 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 766 767 e1000_put_hw_semaphore_generic(hw); 768} 769 770/** 771 * e1000_get_cfg_done_82575 - Read config done bit 772 * @hw: pointer to the HW structure 773 * 774 * Read the management control register for the config done bit for 775 * completion status. NOTE: silicon which is EEPROM-less will fail trying 776 * to read the config done bit, so an error is *ONLY* logged and returns 777 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 778 * would not be able to be reset or change link. 779 **/ 780static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 781{ 782 s32 timeout = PHY_CFG_TIMEOUT; 783 s32 ret_val = E1000_SUCCESS; 784 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 785 786 DEBUGFUNC("e1000_get_cfg_done_82575"); 787 788 if (hw->bus.func == 1) 789 mask = E1000_NVM_CFG_DONE_PORT_1; 790 791 while (timeout) { 792 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 793 break; 794 msec_delay(1); 795 timeout--; 796 } 797 if (!timeout) { 798 DEBUGOUT("MNG configuration cycle has not completed.\n"); 799 } 800 801 /* If EEPROM is not marked present, init the PHY manually */ 802 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 803 (hw->phy.type == e1000_phy_igp_3)) { 804 e1000_phy_init_script_igp3(hw); 805 } 806 807 return ret_val; 808} 809 810/** 811 * e1000_get_link_up_info_82575 - Get link speed/duplex info 812 * @hw: pointer to the HW structure 813 * @speed: stores the current speed 814 * @duplex: stores the current duplex 815 * 816 * This is a wrapper function, if using the serial gigabit media independent 817 * interface, use PCS to retrieve the link speed and duplex information. 818 * Otherwise, use the generic function to get the link speed and duplex info. 819 **/ 820static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 821 u16 *duplex) 822{ 823 s32 ret_val; 824 825 DEBUGFUNC("e1000_get_link_up_info_82575"); 826 827 if (hw->phy.media_type != e1000_media_type_copper || 828 e1000_sgmii_active_82575(hw)) { 829 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 830 duplex); 831 } else { 832 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 833 duplex); 834 } 835 836 return ret_val; 837} 838 839/** 840 * e1000_check_for_link_82575 - Check for link 841 * @hw: pointer to the HW structure 842 * 843 * If sgmii is enabled, then use the pcs register to determine link, otherwise 844 * use the generic interface for determining link. 845 **/ 846static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 847{ 848 s32 ret_val; 849 u16 speed, duplex; 850 851 DEBUGFUNC("e1000_check_for_link_82575"); 852 853 /* SGMII link check is done through the PCS register. */ 854 if ((hw->phy.media_type != e1000_media_type_copper) || 855 (e1000_sgmii_active_82575(hw))) { 856 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 857 &duplex); 858 /* 859 * Use this flag to determine if link needs to be checked or 860 * not. If we have link clear the flag so that we do not 861 * continue to check for link. 862 */ 863 hw->mac.get_link_status = !hw->mac.serdes_has_link; 864 } else { 865 ret_val = e1000_check_for_copper_link_generic(hw); 866 } 867 868 return ret_val; 869} 870 871/** 872 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 873 * @hw: pointer to the HW structure 874 * @speed: stores the current speed 875 * @duplex: stores the current duplex 876 * 877 * Using the physical coding sub-layer (PCS), retrieve the current speed and 878 * duplex, then store the values in the pointers provided. 879 **/ 880static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 881 u16 *speed, u16 *duplex) 882{ 883 struct e1000_mac_info *mac = &hw->mac; 884 u32 pcs; 885 886 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 887 888 /* Set up defaults for the return values of this function */ 889 mac->serdes_has_link = FALSE; 890 *speed = 0; 891 *duplex = 0; 892 893 /* 894 * Read the PCS Status register for link state. For non-copper mode, 895 * the status register is not accurate. The PCS status register is 896 * used instead. 897 */ 898 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 899 900 /* 901 * The link up bit determines when link is up on autoneg. The sync ok 902 * gets set once both sides sync up and agree upon link. Stable link 903 * can be determined by checking for both link up and link sync ok 904 */ 905 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 906 mac->serdes_has_link = TRUE; 907 908 /* Detect and store PCS speed */ 909 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 910 *speed = SPEED_1000; 911 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 912 *speed = SPEED_100; 913 } else { 914 *speed = SPEED_10; 915 } 916 917 /* Detect and store PCS duplex */ 918 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 919 *duplex = FULL_DUPLEX; 920 } else { 921 *duplex = HALF_DUPLEX; 922 } 923 } 924 925 return E1000_SUCCESS; 926} 927 928/** 929 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down 930 * @hw: pointer to the HW structure 931 * 932 * In the case of fiber serdes shut down optics and PCS on driver unload 933 * when management pass thru is not enabled. 934 **/ 935void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) 936{ 937 u32 reg; 938 u16 eeprom_data = 0; 939 940 if (hw->mac.type != e1000_82576 || 941 (hw->phy.media_type != e1000_media_type_fiber && 942 hw->phy.media_type != e1000_media_type_internal_serdes)) 943 return; 944 945 if (hw->bus.func == 0) 946 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 947 948 /* 949 * If APM is not enabled in the EEPROM and management interface is 950 * not enabled, then power down. 951 */ 952 if (!(eeprom_data & E1000_NVM_APME_82575) && 953 !e1000_enable_mng_pass_thru(hw)) { 954 /* Disable PCS to turn off link */ 955 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 956 reg &= ~E1000_PCS_CFG_PCS_EN; 957 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 958 959 /* shutdown the laser */ 960 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 961 reg |= E1000_CTRL_EXT_SDP7_DATA; 962 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 963 964 /* flush the write to verfiy completion */ 965 E1000_WRITE_FLUSH(hw); 966 msec_delay(1); 967 } 968 969 return; 970} 971 972/** 973 * e1000_vmdq_loopback_enable_pf- Enables VM to VM queue loopback replication 974 * @hw: pointer to the HW structure 975 **/ 976void e1000_vmdq_loopback_enable_pf(struct e1000_hw *hw) 977{ 978 u32 reg; 979 980 reg = E1000_READ_REG(hw, E1000_DTXSWC); 981 reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 982 E1000_WRITE_REG(hw, E1000_DTXSWC, reg); 983} 984 985/** 986 * e1000_vmdq_loopback_disable_pf - Disable VM to VM queue loopbk replication 987 * @hw: pointer to the HW structure 988 **/ 989void e1000_vmdq_loopback_disable_pf(struct e1000_hw *hw) 990{ 991 u32 reg; 992 993 reg = E1000_READ_REG(hw, E1000_DTXSWC); 994 reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN); 995 E1000_WRITE_REG(hw, E1000_DTXSWC, reg); 996} 997 998/** 999 * e1000_vmdq_replication_enable_pf - Enable replication of brdcst & multicst 1000 * @hw: pointer to the HW structure 1001 * 1002 * Enables replication of broadcast and multicast packets from the network 1003 * to VM's which have their respective broadcast and multicast accept 1004 * bits set in the VM Offload Register. This gives the PF driver per 1005 * VM granularity control over which VM's get replicated broadcast traffic. 1006 **/ 1007void e1000_vmdq_replication_enable_pf(struct e1000_hw *hw, u32 enables) 1008{ 1009 u32 reg; 1010 u32 i; 1011 1012 for (i = 0; i < MAX_NUM_VFS; i++) { 1013 if (enables & (1 << i)) { 1014 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1015 reg |= (E1000_VMOLR_AUPE | 1016 E1000_VMOLR_BAM | 1017 E1000_VMOLR_MPME); 1018 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1019 } 1020 } 1021 1022 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1023 reg |= E1000_VT_CTL_VM_REPL_EN; 1024 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1025} 1026 1027/** 1028 * e1000_vmdq_replication_disable_pf - Disable replication of brdcst & multicst 1029 * @hw: pointer to the HW structure 1030 * 1031 * Disables replication of broadcast and multicast packets to the VM's. 1032 **/ 1033void e1000_vmdq_replication_disable_pf(struct e1000_hw *hw) 1034{ 1035 u32 reg; 1036 1037 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1038 reg &= ~(E1000_VT_CTL_VM_REPL_EN); 1039 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1040} 1041 1042/** 1043 * e1000_vmdq_enable_replication_mode_pf - Enables replication mode in the device 1044 * @hw: pointer to the HW structure 1045 **/ 1046void e1000_vmdq_enable_replication_mode_pf(struct e1000_hw *hw) 1047{ 1048 u32 reg; 1049 1050 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1051 reg |= E1000_VT_CTL_VM_REPL_EN; 1052 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1053} 1054 1055/** 1056 * e1000_vmdq_broadcast_replication_enable_pf - Enable replication of brdcst 1057 * @hw: pointer to the HW structure 1058 * @enables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1059 * 1060 * Enables replication of broadcast packets from the network 1061 * to VM's which have their respective broadcast accept 1062 * bits set in the VM Offload Register. This gives the PF driver per 1063 * VM granularity control over which VM's get replicated broadcast traffic. 1064 **/ 1065void e1000_vmdq_broadcast_replication_enable_pf(struct e1000_hw *hw, 1066 u32 enables) 1067{ 1068 u32 reg; 1069 u32 i; 1070 1071 for (i = 0; i < MAX_NUM_VFS; i++) { 1072 if ((enables == ALL_QUEUES) || (enables & (1 << i))) { 1073 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1074 reg |= E1000_VMOLR_BAM; 1075 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1076 } 1077 } 1078} 1079 1080/** 1081 * e1000_vmdq_broadcast_replication_disable_pf - Disable replication 1082 * of broadcast packets 1083 * @hw: pointer to the HW structure 1084 * @disables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1085 * 1086 * Disables replication of broadcast packets for specific pools. 1087 * If bam/mpe is disabled on all pools then replication mode is 1088 * turned off. 1089 **/ 1090void e1000_vmdq_broadcast_replication_disable_pf(struct e1000_hw *hw, 1091 u32 disables) 1092{ 1093 u32 reg; 1094 u32 i; 1095 u32 oneenabled = 0; 1096 1097 for (i = 0; i < MAX_NUM_VFS; i++) { 1098 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1099 if ((disables == ALL_QUEUES) || (disables & (1 << i))) { 1100 reg &= ~(E1000_VMOLR_BAM); 1101 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1102 } 1103 if (!oneenabled && (reg & (E1000_VMOLR_AUPE | 1104 E1000_VMOLR_BAM | 1105 E1000_VMOLR_MPME))) 1106 oneenabled = 1; 1107 } 1108 if (!oneenabled) { 1109 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1110 reg &= ~(E1000_VT_CTL_VM_REPL_EN); 1111 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1112 } 1113} 1114 1115/** 1116 * e1000_vmdq_multicast_promiscuous_enable_pf - Enable promiscuous reception 1117 * @hw: pointer to the HW structure 1118 * @enables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1119 * 1120 * Enables promiscuous reception of multicast packets from the network 1121 * to VM's which have their respective multicast promiscuous mode enable 1122 * bits set in the VM Offload Register. This gives the PF driver per 1123 * VM granularity control over which VM's get all multicast traffic. 1124 **/ 1125void e1000_vmdq_multicast_promiscuous_enable_pf(struct e1000_hw *hw, 1126 u32 enables) 1127{ 1128 u32 reg; 1129 u32 i; 1130 1131 for (i = 0; i < MAX_NUM_VFS; i++) { 1132 if ((enables == ALL_QUEUES) || (enables & (1 << i))) { 1133 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1134 reg |= E1000_VMOLR_MPME; 1135 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1136 } 1137 } 1138} 1139 1140/** 1141 * e1000_vmdq_multicast_promiscuous_disable_pf - Disable promiscuous 1142 * reception of multicast packets 1143 * @hw: pointer to the HW structure 1144 * @disables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1145 * 1146 * Disables promiscuous reception of multicast packets for specific pools. 1147 * If bam/mpe is disabled on all pools then replication mode is 1148 * turned off. 1149 **/ 1150void e1000_vmdq_multicast_promiscuous_disable_pf(struct e1000_hw *hw, 1151 u32 disables) 1152{ 1153 u32 reg; 1154 u32 i; 1155 u32 oneenabled = 0; 1156 1157 for (i = 0; i < MAX_NUM_VFS; i++) { 1158 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1159 if ((disables == ALL_QUEUES) || (disables & (1 << i))) { 1160 reg &= ~(E1000_VMOLR_MPME); 1161 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1162 } 1163 if (!oneenabled && (reg & (E1000_VMOLR_AUPE | 1164 E1000_VMOLR_BAM | 1165 E1000_VMOLR_MPME))) 1166 oneenabled = 1; 1167 } 1168 if (!oneenabled) { 1169 reg = E1000_READ_REG(hw, E1000_VT_CTL); 1170 reg &= ~(E1000_VT_CTL_VM_REPL_EN); 1171 E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1172 } 1173} 1174 1175/** 1176 * e1000_vmdq_aupe_enable_pf - Enable acceptance of untagged packets 1177 * @hw: pointer to the HW structure 1178 * @enables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1179 * 1180 * Enables acceptance of packets from the network which do not have 1181 * a VLAN tag but match the exact MAC filter of a given VM. 1182 **/ 1183void e1000_vmdq_aupe_enable_pf(struct e1000_hw *hw, u32 enables) 1184{ 1185 u32 reg; 1186 u32 i; 1187 1188 for (i = 0; i < MAX_NUM_VFS; i++) { 1189 if ((enables == ALL_QUEUES) || (enables & (1 << i))) { 1190 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1191 reg |= E1000_VMOLR_AUPE; 1192 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1193 } 1194 } 1195} 1196 1197/** 1198 * e1000_vmdq_aupe_disable_pf - Disable acceptance of untagged packets 1199 * @hw: pointer to the HW structure 1200 * @disables: PoolSet Bit - if set to ALL_QUEUES, apply to all pools. 1201 * 1202 * Disables acceptance of packets from the network which do not have 1203 * a VLAN tag but match the exact MAC filter of a given VM. 1204 **/ 1205void e1000_vmdq_aupe_disable_pf(struct e1000_hw *hw, u32 disables) 1206{ 1207 u32 reg; 1208 u32 i; 1209 1210 for (i = 0; i < MAX_NUM_VFS; i++) { 1211 if ((disables == ALL_QUEUES) || (disables & (1 << i))) { 1212 reg = E1000_READ_REG(hw, E1000_VMOLR(i)); 1213 reg &= ~E1000_VMOLR_AUPE; 1214 E1000_WRITE_REG(hw, E1000_VMOLR(i), reg); 1215 } 1216 } 1217} 1218 1219/** 1220 * e1000_reset_hw_82575 - Reset hardware 1221 * @hw: pointer to the HW structure 1222 * 1223 * This resets the hardware into a known state. 1224 **/ 1225static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1226{ 1227 u32 ctrl, icr; 1228 s32 ret_val; 1229 1230 DEBUGFUNC("e1000_reset_hw_82575"); 1231 1232 /* 1233 * Prevent the PCI-E bus from sticking if there is no TLP connection 1234 * on the last TLP read/write transaction when MAC is reset. 1235 */ 1236 ret_val = e1000_disable_pcie_master_generic(hw); 1237 if (ret_val) { 1238 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1239 } 1240 1241 DEBUGOUT("Masking off all interrupts\n"); 1242 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1243 1244 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1245 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1246 E1000_WRITE_FLUSH(hw); 1247 1248 msec_delay(10); 1249 1250 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1251 1252 DEBUGOUT("Issuing a global reset to MAC\n"); 1253 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1254 1255 ret_val = e1000_get_auto_rd_done_generic(hw); 1256 if (ret_val) { 1257 /* 1258 * When auto config read does not complete, do not 1259 * return with an error. This can happen in situations 1260 * where there is no eeprom and prevents getting link. 1261 */ 1262 DEBUGOUT("Auto Read Done did not complete\n"); 1263 } 1264 1265 /* If EEPROM is not present, run manual init scripts */ 1266 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1267 e1000_reset_init_script_82575(hw); 1268 1269 /* Clear any pending interrupt events. */ 1270 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1271 icr = E1000_READ_REG(hw, E1000_ICR); 1272 1273 /* Install any alternate MAC address into RAR0 */ 1274 ret_val = e1000_check_alt_mac_addr_generic(hw); 1275 1276 return ret_val; 1277} 1278 1279/** 1280 * e1000_init_hw_82575 - Initialize hardware 1281 * @hw: pointer to the HW structure 1282 * 1283 * This inits the hardware readying it for operation. 1284 **/ 1285static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1286{ 1287 struct e1000_mac_info *mac = &hw->mac; 1288 s32 ret_val; 1289 u16 i, rar_count = mac->rar_entry_count; 1290 1291 DEBUGFUNC("e1000_init_hw_82575"); 1292 1293 /* Initialize identification LED */ 1294 ret_val = mac->ops.id_led_init(hw); 1295 if (ret_val) { 1296 DEBUGOUT("Error initializing identification LED\n"); 1297 /* This is not fatal and we should not stop init due to this */ 1298 } 1299 1300 /* Disabling VLAN filtering */ 1301 DEBUGOUT("Initializing the IEEE VLAN\n"); 1302 mac->ops.clear_vfta(hw); 1303 1304 /* Setup the receive address */ 1305 e1000_init_rx_addrs_generic(hw, rar_count); 1306 1307 /* Zero out the Multicast HASH table */ 1308 DEBUGOUT("Zeroing the MTA\n"); 1309 for (i = 0; i < mac->mta_reg_count; i++) 1310 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1311 1312 /* Setup link and flow control */ 1313 ret_val = mac->ops.setup_link(hw); 1314 1315 /* 1316 * Clear all of the statistics registers (clear on read). It is 1317 * important that we do this after we have tried to establish link 1318 * because the symbol error count will increment wildly if there 1319 * is no link. 1320 */ 1321 e1000_clear_hw_cntrs_82575(hw); 1322 1323 return ret_val; 1324} 1325 1326/** 1327 * e1000_setup_copper_link_82575 - Configure copper link settings 1328 * @hw: pointer to the HW structure 1329 * 1330 * Configures the link for auto-neg or forced speed and duplex. Then we check 1331 * for link, once link is established calls to configure collision distance 1332 * and flow control are called. 1333 **/ 1334static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1335{ 1336 u32 ctrl, led_ctrl; 1337 s32 ret_val; 1338 bool link; 1339 1340 DEBUGFUNC("e1000_setup_copper_link_82575"); 1341 1342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1343 ctrl |= E1000_CTRL_SLU; 1344 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1345 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1346 1347 switch (hw->phy.type) { 1348 case e1000_phy_m88: 1349 ret_val = e1000_copper_link_setup_m88(hw); 1350 break; 1351 case e1000_phy_igp_3: 1352 ret_val = e1000_copper_link_setup_igp(hw); 1353 /* Setup activity LED */ 1354 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1355 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1356 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1357 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1358 break; 1359 default: 1360 ret_val = -E1000_ERR_PHY; 1361 break; 1362 } 1363 1364 if (ret_val) 1365 goto out; 1366 1367 if (hw->mac.autoneg) { 1368 /* 1369 * Setup autoneg and flow control advertisement 1370 * and perform autonegotiation. 1371 */ 1372 ret_val = e1000_copper_link_autoneg(hw); 1373 if (ret_val) 1374 goto out; 1375 } else { 1376 /* 1377 * PHY will be set to 10H, 10F, 100H or 100F 1378 * depending on user settings. 1379 */ 1380 DEBUGOUT("Forcing Speed and Duplex\n"); 1381 ret_val = hw->phy.ops.force_speed_duplex(hw); 1382 if (ret_val) { 1383 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1384 goto out; 1385 } 1386 } 1387 1388 ret_val = e1000_configure_pcs_link_82575(hw); 1389 if (ret_val) 1390 goto out; 1391 1392 /* 1393 * Check link status. Wait up to 100 microseconds for link to become 1394 * valid. 1395 */ 1396 ret_val = e1000_phy_has_link_generic(hw, 1397 COPPER_LINK_UP_LIMIT, 1398 10, 1399 &link); 1400 if (ret_val) 1401 goto out; 1402 1403 if (link) { 1404 DEBUGOUT("Valid link established!!!\n"); 1405 /* Config the MAC and PHY after link is up */ 1406 e1000_config_collision_dist_generic(hw); 1407 ret_val = e1000_config_fc_after_link_up_generic(hw); 1408 } else { 1409 DEBUGOUT("Unable to establish link!!!\n"); 1410 } 1411 1412out: 1413 return ret_val; 1414} 1415 1416/** 1417 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1418 * @hw: pointer to the HW structure 1419 * 1420 * Configures speed and duplex for fiber and serdes links. 1421 **/ 1422static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 1423{ 1424 u32 reg; 1425 1426 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 1427 1428 /* 1429 * On the 82575, SerDes loopback mode persists until it is 1430 * explicitly turned off or a power cycle is performed. A read to 1431 * the register does not indicate its status. Therefore, we ensure 1432 * loopback mode is disabled during initialization. 1433 */ 1434 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1435 1436 /* Force link up, set 1gb, set both sw defined pins */ 1437 reg = E1000_READ_REG(hw, E1000_CTRL); 1438 reg |= E1000_CTRL_SLU | 1439 E1000_CTRL_SPD_1000 | 1440 E1000_CTRL_FRCSPD | 1441 E1000_CTRL_SWDPIN0 | 1442 E1000_CTRL_SWDPIN1; 1443 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1444 1445 /* Power on phy for 82576 fiber adapters */ 1446 if (hw->mac.type == e1000_82576) { 1447 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1448 reg &= ~E1000_CTRL_EXT_SDP7_DATA; 1449 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1450 } 1451 1452 /* Set switch control to serdes energy detect */ 1453 reg = E1000_READ_REG(hw, E1000_CONNSW); 1454 reg |= E1000_CONNSW_ENRGSRC; 1455 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1456 1457 /* 1458 * New SerDes mode allows for forcing speed or autonegotiating speed 1459 * at 1gb. Autoneg should be default set by most drivers. This is the 1460 * mode that will be compatible with older link partners and switches. 1461 * However, both are supported by the hardware and some drivers/tools. 1462 */ 1463 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1464 1465 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1466 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1467 1468 if (hw->mac.autoneg) { 1469 /* Set PCS register for autoneg */ 1470 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1471 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1472 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1473 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1474 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1475 } else { 1476 /* Set PCS register for forced speed */ 1477 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1478 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1479 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1480 E1000_PCS_LCTL_FSD | /* Force Speed */ 1481 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1482 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1483 } 1484 1485 if (hw->mac.type == e1000_82576) { 1486 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1487 e1000_force_mac_fc_generic(hw); 1488 } 1489 1490 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1491 1492 return E1000_SUCCESS; 1493} 1494 1495/** 1496 * e1000_valid_led_default_82575 - Verify a valid default LED config 1497 * @hw: pointer to the HW structure 1498 * @data: pointer to the NVM (EEPROM) 1499 * 1500 * Read the EEPROM for the current default LED configuration. If the 1501 * LED configuration is not valid, set to a valid LED configuration. 1502 **/ 1503static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1504{ 1505 s32 ret_val; 1506 1507 DEBUGFUNC("e1000_valid_led_default_82575"); 1508 1509 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1510 if (ret_val) { 1511 DEBUGOUT("NVM Read Error\n"); 1512 goto out; 1513 } 1514 1515 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1516 switch(hw->phy.media_type) { 1517 case e1000_media_type_fiber: 1518 case e1000_media_type_internal_serdes: 1519 *data = ID_LED_DEFAULT_82575_SERDES; 1520 break; 1521 case e1000_media_type_copper: 1522 default: 1523 *data = ID_LED_DEFAULT; 1524 break; 1525 } 1526 } 1527out: 1528 return ret_val; 1529} 1530 1531/** 1532 * e1000_configure_pcs_link_82575 - Configure PCS link 1533 * @hw: pointer to the HW structure 1534 * 1535 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1536 * only used on copper connections where the serialized gigabit media 1537 * independent interface (sgmii) is being used. Configures the link 1538 * for auto-negotiation or forces speed/duplex. 1539 **/ 1540static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 1541{ 1542 struct e1000_mac_info *mac = &hw->mac; 1543 u32 reg = 0; 1544 1545 DEBUGFUNC("e1000_configure_pcs_link_82575"); 1546 1547 if (hw->phy.media_type != e1000_media_type_copper || 1548 !(e1000_sgmii_active_82575(hw))) 1549 goto out; 1550 1551 /* For SGMII, we need to issue a PCS autoneg restart */ 1552 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1553 1554 /* AN time out should be disabled for SGMII mode */ 1555 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1556 1557 if (mac->autoneg) { 1558 /* Make sure forced speed and force link are not set */ 1559 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1560 1561 /* 1562 * The PHY should be setup prior to calling this function. 1563 * All we need to do is restart autoneg and enable autoneg. 1564 */ 1565 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1566 } else { 1567 /* Set PCS register for forced speed */ 1568 1569 /* Turn off bits for full duplex, speed, and autoneg */ 1570 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1571 E1000_PCS_LCTL_FSV_100 | 1572 E1000_PCS_LCTL_FDV_FULL | 1573 E1000_PCS_LCTL_AN_ENABLE); 1574 1575 /* Check for duplex first */ 1576 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1577 reg |= E1000_PCS_LCTL_FDV_FULL; 1578 1579 /* Now set speed */ 1580 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 1581 reg |= E1000_PCS_LCTL_FSV_100; 1582 1583 /* Force speed and force link */ 1584 reg |= E1000_PCS_LCTL_FSD | 1585 E1000_PCS_LCTL_FORCE_LINK | 1586 E1000_PCS_LCTL_FLV_LINK_UP; 1587 1588 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 1589 reg); 1590 } 1591 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1592 1593out: 1594 return E1000_SUCCESS; 1595} 1596 1597/** 1598 * e1000_sgmii_active_82575 - Return sgmii state 1599 * @hw: pointer to the HW structure 1600 * 1601 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1602 * which can be enabled for use in the embedded applications. Simply 1603 * return the current state of the sgmii interface. 1604 **/ 1605static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1606{ 1607 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1608 1609 DEBUGFUNC("e1000_sgmii_active_82575"); 1610 1611 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576) 1612 return FALSE; 1613 1614 return dev_spec->sgmii_active; 1615} 1616 1617/** 1618 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1619 * @hw: pointer to the HW structure 1620 * 1621 * Inits recommended HW defaults after a reset when there is no EEPROM 1622 * detected. This is only for the 82575. 1623 **/ 1624static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1625{ 1626 DEBUGFUNC("e1000_reset_init_script_82575"); 1627 1628 if (hw->mac.type == e1000_82575) { 1629 DEBUGOUT("Running reset init script for 82575\n"); 1630 /* SerDes configuration via SERDESCTRL */ 1631 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1632 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1633 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1634 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1635 1636 /* CCM configuration via CCMCTL register */ 1637 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1638 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1639 1640 /* PCIe lanes configuration */ 1641 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1642 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1643 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1644 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1645 1646 /* PCIe PLL Configuration */ 1647 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1648 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1649 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1650 } 1651 1652 return E1000_SUCCESS; 1653} 1654 1655/** 1656 * e1000_read_mac_addr_82575 - Read device MAC address 1657 * @hw: pointer to the HW structure 1658 **/ 1659static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1660{ 1661 s32 ret_val = E1000_SUCCESS; 1662 1663 DEBUGFUNC("e1000_read_mac_addr_82575"); 1664 1665 /* 1666 * If there's an alternate MAC address place it in RAR0 1667 * so that it will override the Si installed default perm 1668 * address. 1669 */ 1670 ret_val = e1000_check_alt_mac_addr_generic(hw); 1671 if (ret_val) 1672 goto out; 1673 1674 ret_val = e1000_read_mac_addr_generic(hw); 1675 1676out: 1677 return ret_val; 1678} 1679 1680/** 1681 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1682 * @hw: pointer to the HW structure 1683 * 1684 * In the case of a PHY power down to save power, or to turn off link during a 1685 * driver unload, or wake on lan is not enabled, remove the link. 1686 **/ 1687static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1688{ 1689 struct e1000_phy_info *phy = &hw->phy; 1690 struct e1000_mac_info *mac = &hw->mac; 1691 1692 if (!(phy->ops.check_reset_block)) 1693 return; 1694 1695 /* If the management interface is not enabled, then power down */ 1696 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1697 e1000_power_down_phy_copper(hw); 1698 1699 return; 1700} 1701 1702/** 1703 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1704 * @hw: pointer to the HW structure 1705 * 1706 * Clears the hardware counters by reading the counter registers. 1707 **/ 1708static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1709{ 1710 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1711 1712 e1000_clear_hw_cntrs_base_generic(hw); 1713 1714 E1000_READ_REG(hw, E1000_PRC64); 1715 E1000_READ_REG(hw, E1000_PRC127); 1716 E1000_READ_REG(hw, E1000_PRC255); 1717 E1000_READ_REG(hw, E1000_PRC511); 1718 E1000_READ_REG(hw, E1000_PRC1023); 1719 E1000_READ_REG(hw, E1000_PRC1522); 1720 E1000_READ_REG(hw, E1000_PTC64); 1721 E1000_READ_REG(hw, E1000_PTC127); 1722 E1000_READ_REG(hw, E1000_PTC255); 1723 E1000_READ_REG(hw, E1000_PTC511); 1724 E1000_READ_REG(hw, E1000_PTC1023); 1725 E1000_READ_REG(hw, E1000_PTC1522); 1726 1727 E1000_READ_REG(hw, E1000_ALGNERRC); 1728 E1000_READ_REG(hw, E1000_RXERRC); 1729 E1000_READ_REG(hw, E1000_TNCRS); 1730 E1000_READ_REG(hw, E1000_CEXTERR); 1731 E1000_READ_REG(hw, E1000_TSCTC); 1732 E1000_READ_REG(hw, E1000_TSCTFC); 1733 1734 E1000_READ_REG(hw, E1000_MGTPRC); 1735 E1000_READ_REG(hw, E1000_MGTPDC); 1736 E1000_READ_REG(hw, E1000_MGTPTC); 1737 1738 E1000_READ_REG(hw, E1000_IAC); 1739 E1000_READ_REG(hw, E1000_ICRXOC); 1740 1741 E1000_READ_REG(hw, E1000_ICRXPTC); 1742 E1000_READ_REG(hw, E1000_ICRXATC); 1743 E1000_READ_REG(hw, E1000_ICTXPTC); 1744 E1000_READ_REG(hw, E1000_ICTXATC); 1745 E1000_READ_REG(hw, E1000_ICTXQEC); 1746 E1000_READ_REG(hw, E1000_ICTXQMTC); 1747 E1000_READ_REG(hw, E1000_ICRXDMTC); 1748 1749 E1000_READ_REG(hw, E1000_CBTMPC); 1750 E1000_READ_REG(hw, E1000_HTDPMC); 1751 E1000_READ_REG(hw, E1000_CBRMPC); 1752 E1000_READ_REG(hw, E1000_RPTHC); 1753 E1000_READ_REG(hw, E1000_HGPTC); 1754 E1000_READ_REG(hw, E1000_HTCBDPC); 1755 E1000_READ_REG(hw, E1000_HGORCL); 1756 E1000_READ_REG(hw, E1000_HGORCH); 1757 E1000_READ_REG(hw, E1000_HGOTCL); 1758 E1000_READ_REG(hw, E1000_HGOTCH); 1759 E1000_READ_REG(hw, E1000_LENERRS); 1760 1761 /* This register should not be read in copper configurations */ 1762 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1763 E1000_READ_REG(hw, E1000_SCVPC); 1764} 1765/** 1766 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1767 * @hw: pointer to the HW structure 1768 * 1769 * After rx enable if managability is enabled then there is likely some 1770 * bad data at the start of the fifo and possibly in the DMA fifo. This 1771 * function clears the fifos and flushes any packets that came in as rx was 1772 * being enabled. 1773 **/ 1774void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1775{ 1776 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1777 int i, ms_wait; 1778 1779 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1780 if (hw->mac.type != e1000_82575 || 1781 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1782 return; 1783 1784 /* Disable all RX queues */ 1785 for (i = 0; i < 4; i++) { 1786 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1787 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1788 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1789 } 1790 /* Poll all queues to verify they have shut down */ 1791 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1792 msec_delay(1); 1793 rx_enabled = 0; 1794 for (i = 0; i < 4; i++) 1795 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1796 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1797 break; 1798 } 1799 1800 if (ms_wait == 10) 1801 DEBUGOUT("Queue disable timed out after 10ms\n"); 1802 1803 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1804 * incoming packets are rejected. Set enable and wait 2ms so that 1805 * any packet that was coming in as RCTL.EN was set is flushed 1806 */ 1807 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1808 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1809 1810 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1811 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1812 1813 rctl = E1000_READ_REG(hw, E1000_RCTL); 1814 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1815 temp_rctl |= E1000_RCTL_LPE; 1816 1817 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1818 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1819 E1000_WRITE_FLUSH(hw); 1820 msec_delay(2); 1821 1822 /* Enable RX queues that were previously enabled and restore our 1823 * previous state 1824 */ 1825 for (i = 0; i < 4; i++) 1826 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1827 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1828 E1000_WRITE_FLUSH(hw); 1829 1830 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1831 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1832 1833 /* Flush receive errors generated by workaround */ 1834 E1000_READ_REG(hw, E1000_ROC); 1835 E1000_READ_REG(hw, E1000_RNBC); 1836 E1000_READ_REG(hw, E1000_MPC); 1837} 1838 1839