e1000_82543.c revision 176667
1169240Sjfv/******************************************************************************* 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32169240Sjfv*******************************************************************************/ 33173788Sjfv/* $FreeBSD: head/sys/dev/em/e1000_82543.c 176667 2008-02-29 21:50:11Z jfv $ */ 34169240Sjfv 35169240Sjfv 36169240Sjfv/* e1000_82543 37169240Sjfv * e1000_82544 38169240Sjfv */ 39169240Sjfv 40169589Sjfv#include "e1000_api.h" 41169240Sjfv#include "e1000_82543.h" 42169240Sjfv 43173788SjfvSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 44173788SjfvSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 45173788SjfvSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 46173788SjfvSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 47173788Sjfv u16 *data); 48173788SjfvSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 49173788Sjfv u16 data); 50173788SjfvSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 51173788SjfvSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 52173788SjfvSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 53173788SjfvSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 54173788SjfvSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 55173788SjfvSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 56173788SjfvSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 57173788SjfvSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 58173788SjfvSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 59173788SjfvSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 60173788SjfvSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 61173788SjfvSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 62173788Sjfv u32 value); 63173788SjfvSTATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 64173788SjfvSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 65173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 66173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 67173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 68173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 69173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 71173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 72173788Sjfv u16 count); 73173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 74173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 75169240Sjfv 76169240Sjfvstruct e1000_dev_spec_82543 { 77169240Sjfv u32 tbi_compatibility; 78173788Sjfv bool dma_fairness; 79173788Sjfv bool init_phy_disabled; 80169240Sjfv}; 81169240Sjfv 82169240Sjfv/** 83169240Sjfv * e1000_init_phy_params_82543 - Init PHY func ptrs. 84169589Sjfv * @hw: pointer to the HW structure 85169240Sjfv * 86169240Sjfv * This is a function pointer entry point called by the api module. 87169240Sjfv **/ 88173788SjfvSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 89169240Sjfv{ 90169240Sjfv struct e1000_phy_info *phy = &hw->phy; 91169240Sjfv struct e1000_functions *func = &hw->func; 92169240Sjfv s32 ret_val = E1000_SUCCESS; 93169240Sjfv 94169240Sjfv DEBUGFUNC("e1000_init_phy_params_82543"); 95169240Sjfv 96173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 97169240Sjfv phy->type = e1000_phy_none; 98169240Sjfv goto out; 99173788Sjfv } else { 100173788Sjfv func->power_up_phy = e1000_power_up_phy_copper; 101173788Sjfv func->power_down_phy = e1000_power_down_phy_copper; 102169240Sjfv } 103169240Sjfv 104169240Sjfv phy->addr = 1; 105169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106169240Sjfv phy->reset_delay_us = 10000; 107169240Sjfv phy->type = e1000_phy_m88; 108169240Sjfv 109169240Sjfv /* Function Pointers */ 110169240Sjfv func->check_polarity = e1000_check_polarity_m88; 111169240Sjfv func->commit_phy = e1000_phy_sw_reset_generic; 112169240Sjfv func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 113169240Sjfv func->get_cable_length = e1000_get_cable_length_m88; 114169240Sjfv func->get_cfg_done = e1000_get_cfg_done_generic; 115169240Sjfv func->read_phy_reg = (hw->mac.type == e1000_82543) 116169240Sjfv ? e1000_read_phy_reg_82543 117169240Sjfv : e1000_read_phy_reg_m88; 118169240Sjfv func->reset_phy = (hw->mac.type == e1000_82543) 119169240Sjfv ? e1000_phy_hw_reset_82543 120169240Sjfv : e1000_phy_hw_reset_generic; 121169240Sjfv func->write_phy_reg = (hw->mac.type == e1000_82543) 122169240Sjfv ? e1000_write_phy_reg_82543 123169240Sjfv : e1000_write_phy_reg_m88; 124169240Sjfv func->get_phy_info = e1000_get_phy_info_m88; 125169240Sjfv 126173788Sjfv /* 127173788Sjfv * The external PHY of the 82543 can be in a funky state. 128169240Sjfv * Resetting helps us read the PHY registers for acquiring 129169240Sjfv * the PHY ID. 130169240Sjfv */ 131169240Sjfv if (!e1000_init_phy_disabled_82543(hw)) { 132169240Sjfv ret_val = e1000_phy_hw_reset(hw); 133169240Sjfv if (ret_val) { 134169240Sjfv DEBUGOUT("Resetting PHY during init failed.\n"); 135169240Sjfv goto out; 136169240Sjfv } 137169240Sjfv msec_delay(20); 138169240Sjfv } 139169240Sjfv 140169240Sjfv ret_val = e1000_get_phy_id(hw); 141169240Sjfv if (ret_val) 142169240Sjfv goto out; 143169240Sjfv 144169240Sjfv /* Verify phy id */ 145169240Sjfv switch (hw->mac.type) { 146169240Sjfv case e1000_82543: 147169240Sjfv if (phy->id != M88E1000_E_PHY_ID) { 148169240Sjfv ret_val = -E1000_ERR_PHY; 149169240Sjfv goto out; 150169240Sjfv } 151169240Sjfv break; 152169240Sjfv case e1000_82544: 153169240Sjfv if (phy->id != M88E1000_I_PHY_ID) { 154169240Sjfv ret_val = -E1000_ERR_PHY; 155169240Sjfv goto out; 156169240Sjfv } 157169240Sjfv break; 158169240Sjfv default: 159169240Sjfv ret_val = -E1000_ERR_PHY; 160169240Sjfv goto out; 161169240Sjfv break; 162169240Sjfv } 163169240Sjfv 164169240Sjfvout: 165169240Sjfv return ret_val; 166169240Sjfv} 167169240Sjfv 168169240Sjfv/** 169169240Sjfv * e1000_init_nvm_params_82543 - Init NVM func ptrs. 170169589Sjfv * @hw: pointer to the HW structure 171169240Sjfv * 172169240Sjfv * This is a function pointer entry point called by the api module. 173169240Sjfv **/ 174173788SjfvSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 175169240Sjfv{ 176169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 177169240Sjfv struct e1000_functions *func = &hw->func; 178169240Sjfv 179169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82543"); 180169240Sjfv 181169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 182169240Sjfv nvm->word_size = 64; 183169240Sjfv nvm->delay_usec = 50; 184169240Sjfv nvm->address_bits = 6; 185169240Sjfv nvm->opcode_bits = 3; 186169240Sjfv 187169240Sjfv /* Function Pointers */ 188169240Sjfv func->read_nvm = e1000_read_nvm_microwire; 189169240Sjfv func->update_nvm = e1000_update_nvm_checksum_generic; 190169240Sjfv func->valid_led_default = e1000_valid_led_default_generic; 191169240Sjfv func->validate_nvm = e1000_validate_nvm_checksum_generic; 192169240Sjfv func->write_nvm = e1000_write_nvm_microwire; 193169240Sjfv 194169240Sjfv return E1000_SUCCESS; 195169240Sjfv} 196169240Sjfv 197169240Sjfv/** 198169240Sjfv * e1000_init_mac_params_82543 - Init MAC func ptrs. 199169589Sjfv * @hw: pointer to the HW structure 200169240Sjfv * 201169240Sjfv * This is a function pointer entry point called by the api module. 202169240Sjfv **/ 203173788SjfvSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 204169240Sjfv{ 205169240Sjfv struct e1000_mac_info *mac = &hw->mac; 206169240Sjfv struct e1000_functions *func = &hw->func; 207169240Sjfv s32 ret_val; 208169240Sjfv 209169240Sjfv DEBUGFUNC("e1000_init_mac_params_82543"); 210169240Sjfv 211169240Sjfv /* Set media type */ 212169240Sjfv switch (hw->device_id) { 213169240Sjfv case E1000_DEV_ID_82543GC_FIBER: 214169240Sjfv case E1000_DEV_ID_82544EI_FIBER: 215173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 216169240Sjfv break; 217169240Sjfv default: 218173788Sjfv hw->phy.media_type = e1000_media_type_copper; 219169240Sjfv break; 220169240Sjfv } 221169240Sjfv 222169240Sjfv /* Set mta register count */ 223169240Sjfv mac->mta_reg_count = 128; 224169240Sjfv /* Set rar entry count */ 225169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 226169240Sjfv 227169240Sjfv /* Function pointers */ 228169240Sjfv 229169240Sjfv /* bus type/speed/width */ 230169240Sjfv func->get_bus_info = e1000_get_bus_info_pci_generic; 231169240Sjfv /* reset */ 232169240Sjfv func->reset_hw = e1000_reset_hw_82543; 233169240Sjfv /* hw initialization */ 234169240Sjfv func->init_hw = e1000_init_hw_82543; 235169240Sjfv /* link setup */ 236169240Sjfv func->setup_link = e1000_setup_link_82543; 237169240Sjfv /* physical interface setup */ 238169240Sjfv func->setup_physical_interface = 239173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 240169240Sjfv ? e1000_setup_copper_link_82543 241169240Sjfv : e1000_setup_fiber_link_82543; 242169240Sjfv /* check for link */ 243169240Sjfv func->check_for_link = 244173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 245169240Sjfv ? e1000_check_for_copper_link_82543 246169240Sjfv : e1000_check_for_fiber_link_82543; 247169240Sjfv /* link info */ 248169240Sjfv func->get_link_up_info = 249173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 250169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 251169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 252169240Sjfv /* multicast address update */ 253173788Sjfv func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 254169240Sjfv /* writing VFTA */ 255169240Sjfv func->write_vfta = e1000_write_vfta_82543; 256169240Sjfv /* clearing VFTA */ 257169240Sjfv func->clear_vfta = e1000_clear_vfta_generic; 258169240Sjfv /* setting MTA */ 259169240Sjfv func->mta_set = e1000_mta_set_82543; 260169240Sjfv /* turn on/off LED */ 261169240Sjfv func->led_on = e1000_led_on_82543; 262169240Sjfv func->led_off = e1000_led_off_82543; 263169240Sjfv /* remove device */ 264169240Sjfv func->remove_device = e1000_remove_device_generic; 265169240Sjfv /* clear hardware counters */ 266169240Sjfv func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 267169240Sjfv 268169240Sjfv hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 269169240Sjfv 270169240Sjfv /* Device-specific structure allocation */ 271169240Sjfv ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 272169240Sjfv if (ret_val) 273169240Sjfv goto out; 274169240Sjfv 275169240Sjfv /* Set tbi compatibility */ 276169240Sjfv if ((hw->mac.type != e1000_82543) || 277173788Sjfv (hw->phy.media_type == e1000_media_type_fiber)) 278169240Sjfv e1000_set_tbi_compatibility_82543(hw, FALSE); 279169240Sjfv 280169240Sjfvout: 281169240Sjfv return ret_val; 282169240Sjfv} 283169240Sjfv 284169240Sjfv/** 285169240Sjfv * e1000_init_function_pointers_82543 - Init func ptrs. 286169589Sjfv * @hw: pointer to the HW structure 287169240Sjfv * 288169240Sjfv * The only function explicitly called by the api module to initialize 289169240Sjfv * all function pointers and parameters. 290169240Sjfv **/ 291173788Sjfvvoid e1000_init_function_pointers_82543(struct e1000_hw *hw) 292169240Sjfv{ 293169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82543"); 294169240Sjfv 295169240Sjfv hw->func.init_mac_params = e1000_init_mac_params_82543; 296169240Sjfv hw->func.init_nvm_params = e1000_init_nvm_params_82543; 297169240Sjfv hw->func.init_phy_params = e1000_init_phy_params_82543; 298169240Sjfv} 299169240Sjfv 300169240Sjfv/** 301169240Sjfv * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 302169589Sjfv * @hw: pointer to the HW structure 303169240Sjfv * 304176667Sjfv * Returns the current status of 10-bit Interface (TBI) compatibility 305169240Sjfv * (enabled/disabled). 306169240Sjfv **/ 307173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 308169240Sjfv{ 309169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 310173788Sjfv bool state = FALSE; 311169240Sjfv 312169240Sjfv DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 313169240Sjfv 314169240Sjfv if (hw->mac.type != e1000_82543) { 315169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 316169240Sjfv goto out; 317169240Sjfv } 318169240Sjfv 319169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 320169240Sjfv 321173788Sjfv if (!dev_spec) { 322169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 323169240Sjfv goto out; 324169240Sjfv } 325169240Sjfv 326169240Sjfv state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 327169240Sjfv ? TRUE : FALSE; 328169240Sjfv 329169240Sjfvout: 330169240Sjfv return state; 331169240Sjfv} 332169240Sjfv 333169240Sjfv/** 334169240Sjfv * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 335169589Sjfv * @hw: pointer to the HW structure 336169589Sjfv * @state: enable/disable TBI compatibility 337169240Sjfv * 338169240Sjfv * Enables or disabled 10-bit Interface (TBI) compatibility. 339169240Sjfv **/ 340173788Sjfvvoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 341169240Sjfv{ 342169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 343169240Sjfv 344169240Sjfv DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 345169240Sjfv 346169240Sjfv if (hw->mac.type != e1000_82543) { 347169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 348169240Sjfv goto out; 349169240Sjfv } 350169240Sjfv 351169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 352169240Sjfv 353173788Sjfv if (!dev_spec) { 354169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 355169240Sjfv goto out; 356169240Sjfv } 357169240Sjfv 358169240Sjfv if (state) 359169240Sjfv dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 360169240Sjfv else 361169240Sjfv dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 362169240Sjfv 363169240Sjfvout: 364169240Sjfv return; 365169240Sjfv} 366169240Sjfv 367169240Sjfv/** 368169240Sjfv * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 369169589Sjfv * @hw: pointer to the HW structure 370169240Sjfv * 371176667Sjfv * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 372169240Sjfv * (enabled/disabled). 373169240Sjfv **/ 374173788Sjfvbool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 375169240Sjfv{ 376169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 377173788Sjfv bool state = FALSE; 378169240Sjfv 379169240Sjfv DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 380169240Sjfv 381169240Sjfv if (hw->mac.type != e1000_82543) { 382169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 383169240Sjfv goto out; 384169240Sjfv } 385169240Sjfv 386169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 387169240Sjfv 388173788Sjfv if (!dev_spec) { 389169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 390169240Sjfv goto out; 391169240Sjfv } 392169240Sjfv 393169240Sjfv state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 394169240Sjfv ? TRUE : FALSE; 395169240Sjfv 396169240Sjfvout: 397169240Sjfv return state; 398169240Sjfv} 399169240Sjfv 400169240Sjfv/** 401169240Sjfv * e1000_set_tbi_sbp_82543 - Set TBI SBP 402169589Sjfv * @hw: pointer to the HW structure 403169589Sjfv * @state: enable/disable TBI store bad packet 404169240Sjfv * 405169240Sjfv * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 406169240Sjfv **/ 407173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 408169240Sjfv{ 409169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 410169240Sjfv 411169240Sjfv DEBUGFUNC("e1000_set_tbi_sbp_82543"); 412169240Sjfv 413169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 414169240Sjfv 415169240Sjfv if (state && e1000_tbi_compatibility_enabled_82543(hw)) 416169240Sjfv dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 417169240Sjfv else 418169240Sjfv dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 419169240Sjfv 420169240Sjfv return; 421169240Sjfv} 422169240Sjfv 423169240Sjfv/** 424169240Sjfv * e1000_init_phy_disabled_82543 - Returns init PHY status 425169589Sjfv * @hw: pointer to the HW structure 426169240Sjfv * 427169240Sjfv * Returns the current status of whether PHY initialization is disabled. 428169240Sjfv * True if PHY initialization is disabled else false. 429169240Sjfv **/ 430173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 431169240Sjfv{ 432169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 433173788Sjfv bool ret_val; 434169240Sjfv 435169240Sjfv DEBUGFUNC("e1000_init_phy_disabled_82543"); 436169240Sjfv 437169240Sjfv if (hw->mac.type != e1000_82543) { 438169240Sjfv ret_val = FALSE; 439169240Sjfv goto out; 440169240Sjfv } 441169240Sjfv 442169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 443169240Sjfv 444173788Sjfv if (!dev_spec) { 445169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 446169240Sjfv ret_val = FALSE; 447169240Sjfv goto out; 448169240Sjfv } 449169240Sjfv 450169240Sjfv ret_val = dev_spec->init_phy_disabled; 451169240Sjfv 452169240Sjfvout: 453169240Sjfv return ret_val; 454169240Sjfv} 455169240Sjfv 456169240Sjfv/** 457169240Sjfv * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 458169589Sjfv * @hw: pointer to the HW structure 459169589Sjfv * @stats: Struct containing statistic register values 460169589Sjfv * @frame_len: The length of the frame in question 461169589Sjfv * @mac_addr: The Ethernet destination address of the frame in question 462173788Sjfv * @max_frame_size: The maximum frame size 463169240Sjfv * 464169240Sjfv * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 465169240Sjfv **/ 466173788Sjfvvoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 467173788Sjfv struct e1000_hw_stats *stats, u32 frame_len, 468173788Sjfv u8 *mac_addr, u32 max_frame_size) 469169240Sjfv{ 470173788Sjfv if (!(e1000_tbi_sbp_enabled_82543(hw))) 471169240Sjfv goto out; 472169240Sjfv 473169240Sjfv /* First adjust the frame length. */ 474169240Sjfv frame_len--; 475173788Sjfv /* 476173788Sjfv * We need to adjust the statistics counters, since the hardware 477169240Sjfv * counters overcount this packet as a CRC error and undercount 478169240Sjfv * the packet as a good packet 479169240Sjfv */ 480169240Sjfv /* This packet should not be counted as a CRC error. */ 481169240Sjfv stats->crcerrs--; 482169240Sjfv /* This packet does count as a Good Packet Received. */ 483169240Sjfv stats->gprc++; 484169240Sjfv 485169240Sjfv /* Adjust the Good Octets received counters */ 486173788Sjfv stats->gorc += frame_len; 487173788Sjfv 488173788Sjfv /* 489173788Sjfv * Is this a broadcast or multicast? Check broadcast first, 490169240Sjfv * since the test for a multicast frame will test positive on 491169240Sjfv * a broadcast frame. 492169240Sjfv */ 493169240Sjfv if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 494169240Sjfv /* Broadcast packet */ 495169240Sjfv stats->bprc++; 496169240Sjfv else if (*mac_addr & 0x01) 497169240Sjfv /* Multicast packet */ 498169240Sjfv stats->mprc++; 499169240Sjfv 500173788Sjfv /* 501173788Sjfv * In this case, the hardware has overcounted the number of 502169240Sjfv * oversize frames. 503169240Sjfv */ 504173788Sjfv if ((frame_len == max_frame_size) && (stats->roc > 0)) 505169240Sjfv stats->roc--; 506169240Sjfv 507173788Sjfv /* 508173788Sjfv * Adjust the bin counters when the extra byte put the frame in the 509169240Sjfv * wrong bin. Remember that the frame_len was adjusted above. 510169240Sjfv */ 511169240Sjfv if (frame_len == 64) { 512169240Sjfv stats->prc64++; 513169240Sjfv stats->prc127--; 514169240Sjfv } else if (frame_len == 127) { 515169240Sjfv stats->prc127++; 516169240Sjfv stats->prc255--; 517169240Sjfv } else if (frame_len == 255) { 518169240Sjfv stats->prc255++; 519169240Sjfv stats->prc511--; 520169240Sjfv } else if (frame_len == 511) { 521169240Sjfv stats->prc511++; 522169240Sjfv stats->prc1023--; 523169240Sjfv } else if (frame_len == 1023) { 524169240Sjfv stats->prc1023++; 525169240Sjfv stats->prc1522--; 526169240Sjfv } else if (frame_len == 1522) { 527169240Sjfv stats->prc1522++; 528169240Sjfv } 529169240Sjfv 530169240Sjfvout: 531169240Sjfv return; 532169240Sjfv} 533169240Sjfv 534169240Sjfv/** 535169240Sjfv * e1000_read_phy_reg_82543 - Read PHY register 536169589Sjfv * @hw: pointer to the HW structure 537169589Sjfv * @offset: register offset to be read 538169589Sjfv * @data: pointer to the read data 539169240Sjfv * 540169240Sjfv * Reads the PHY at offset and stores the information read to data. 541169240Sjfv **/ 542173788SjfvSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 543169240Sjfv{ 544169240Sjfv u32 mdic; 545169240Sjfv s32 ret_val = E1000_SUCCESS; 546169240Sjfv 547169240Sjfv DEBUGFUNC("e1000_read_phy_reg_82543"); 548169240Sjfv 549169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 550169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 551169240Sjfv ret_val = -E1000_ERR_PARAM; 552169240Sjfv goto out; 553169240Sjfv } 554169240Sjfv 555173788Sjfv /* 556173788Sjfv * We must first send a preamble through the MDIO pin to signal the 557169240Sjfv * beginning of an MII instruction. This is done by sending 32 558169240Sjfv * consecutive "1" bits. 559169240Sjfv */ 560169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 561169240Sjfv 562173788Sjfv /* 563173788Sjfv * Now combine the next few fields that are required for a read 564169240Sjfv * operation. We use this method instead of calling the 565169240Sjfv * e1000_shift_out_mdi_bits routine five different times. The format 566169240Sjfv * of an MII read instruction consists of a shift out of 14 bits and 567169240Sjfv * is defined as follows: 568169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Offset> 569169240Sjfv * followed by a shift in of 18 bits. This first two bits shifted in 570169240Sjfv * are TurnAround bits used to avoid contention on the MDIO pin when a 571169240Sjfv * READ operation is performed. These two bits are thrown away 572169240Sjfv * followed by a shift in of 16 bits which contains the desired data. 573169240Sjfv */ 574169240Sjfv mdic = (offset | (hw->phy.addr << 5) | 575169240Sjfv (PHY_OP_READ << 10) | (PHY_SOF << 12)); 576169240Sjfv 577169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 578169240Sjfv 579173788Sjfv /* 580173788Sjfv * Now that we've shifted out the read command to the MII, we need to 581169240Sjfv * "shift in" the 16-bit value (18 total bits) of the requested PHY 582169240Sjfv * register address. 583169240Sjfv */ 584169240Sjfv *data = e1000_shift_in_mdi_bits_82543(hw); 585169240Sjfv 586169240Sjfvout: 587169240Sjfv return ret_val; 588169240Sjfv} 589169240Sjfv 590169240Sjfv/** 591169240Sjfv * e1000_write_phy_reg_82543 - Write PHY register 592169589Sjfv * @hw: pointer to the HW structure 593169589Sjfv * @offset: register offset to be written 594169589Sjfv * @data: pointer to the data to be written at offset 595169240Sjfv * 596169240Sjfv * Writes data to the PHY at offset. 597169240Sjfv **/ 598173788SjfvSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 599169240Sjfv{ 600169240Sjfv u32 mdic; 601169240Sjfv s32 ret_val = E1000_SUCCESS; 602169240Sjfv 603169240Sjfv DEBUGFUNC("e1000_write_phy_reg_82543"); 604169240Sjfv 605169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 606169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 607169240Sjfv ret_val = -E1000_ERR_PARAM; 608169240Sjfv goto out; 609169240Sjfv } 610169240Sjfv 611173788Sjfv /* 612173788Sjfv * We'll need to use the SW defined pins to shift the write command 613169240Sjfv * out to the PHY. We first send a preamble to the PHY to signal the 614169240Sjfv * beginning of the MII instruction. This is done by sending 32 615169240Sjfv * consecutive "1" bits. 616169240Sjfv */ 617169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 618169240Sjfv 619173788Sjfv /* 620173788Sjfv * Now combine the remaining required fields that will indicate a 621169240Sjfv * write operation. We use this method instead of calling the 622169240Sjfv * e1000_shift_out_mdi_bits routine for each field in the command. The 623169240Sjfv * format of a MII write instruction is as follows: 624169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 625169240Sjfv */ 626169240Sjfv mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 627169240Sjfv (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 628169240Sjfv mdic <<= 16; 629169240Sjfv mdic |= (u32) data; 630169240Sjfv 631169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 632169240Sjfv 633169240Sjfvout: 634169240Sjfv return ret_val; 635169240Sjfv} 636169240Sjfv 637169240Sjfv/** 638169240Sjfv * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 639169589Sjfv * @hw: pointer to the HW structure 640169589Sjfv * @ctrl: pointer to the control register 641169240Sjfv * 642169240Sjfv * Raise the management data input clock by setting the MDC bit in the control 643169240Sjfv * register. 644169240Sjfv **/ 645173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 646169240Sjfv{ 647173788Sjfv /* 648173788Sjfv * Raise the clock input to the Management Data Clock (by setting the 649169240Sjfv * MDC bit), and then delay a sufficient amount of time. 650169240Sjfv */ 651169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 652169240Sjfv E1000_WRITE_FLUSH(hw); 653169240Sjfv usec_delay(10); 654169240Sjfv} 655169240Sjfv 656169240Sjfv/** 657169240Sjfv * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 658169589Sjfv * @hw: pointer to the HW structure 659169589Sjfv * @ctrl: pointer to the control register 660169240Sjfv * 661176667Sjfv * Lower the management data input clock by clearing the MDC bit in the 662176667Sjfv * control register. 663169240Sjfv **/ 664173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 665169240Sjfv{ 666173788Sjfv /* 667173788Sjfv * Lower the clock input to the Management Data Clock (by clearing the 668169240Sjfv * MDC bit), and then delay a sufficient amount of time. 669169240Sjfv */ 670169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 671169240Sjfv E1000_WRITE_FLUSH(hw); 672169240Sjfv usec_delay(10); 673169240Sjfv} 674169240Sjfv 675169240Sjfv/** 676169240Sjfv * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 677169589Sjfv * @hw: pointer to the HW structure 678169589Sjfv * @data: data to send to the PHY 679169589Sjfv * @count: number of bits to shift out 680169240Sjfv * 681169240Sjfv * We need to shift 'count' bits out to the PHY. So, the value in the 682169240Sjfv * "data" parameter will be shifted out to the PHY one bit at a time. 683169240Sjfv * In order to do this, "data" must be broken down into bits. 684169240Sjfv **/ 685173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 686173788Sjfv u16 count) 687169240Sjfv{ 688169240Sjfv u32 ctrl, mask; 689169240Sjfv 690173788Sjfv /* 691173788Sjfv * We need to shift "count" number of bits out to the PHY. So, the 692169240Sjfv * value in the "data" parameter will be shifted out to the PHY one 693169240Sjfv * bit at a time. In order to do this, "data" must be broken down 694169240Sjfv * into bits. 695169240Sjfv */ 696169240Sjfv mask = 0x01; 697169240Sjfv mask <<= (count -1); 698169240Sjfv 699169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 700169240Sjfv 701169240Sjfv /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 702169240Sjfv ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 703169240Sjfv 704169240Sjfv while (mask) { 705173788Sjfv /* 706173788Sjfv * A "1" is shifted out to the PHY by setting the MDIO bit to 707169240Sjfv * "1" and then raising and lowering the Management Data Clock. 708169240Sjfv * A "0" is shifted out to the PHY by setting the MDIO bit to 709169240Sjfv * "0" and then raising and lowering the clock. 710169240Sjfv */ 711169240Sjfv if (data & mask) ctrl |= E1000_CTRL_MDIO; 712169240Sjfv else ctrl &= ~E1000_CTRL_MDIO; 713169240Sjfv 714169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 715169240Sjfv E1000_WRITE_FLUSH(hw); 716169240Sjfv 717169240Sjfv usec_delay(10); 718169240Sjfv 719169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 720169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 721169240Sjfv 722169240Sjfv mask >>= 1; 723169240Sjfv } 724169240Sjfv} 725169240Sjfv 726169240Sjfv/** 727169240Sjfv * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 728169589Sjfv * @hw: pointer to the HW structure 729169240Sjfv * 730169240Sjfv * In order to read a register from the PHY, we need to shift 18 bits 731169240Sjfv * in from the PHY. Bits are "shifted in" by raising the clock input to 732169240Sjfv * the PHY (setting the MDC bit), and then reading the value of the data out 733169240Sjfv * MDIO bit. 734169240Sjfv **/ 735173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 736169240Sjfv{ 737169240Sjfv u32 ctrl; 738169240Sjfv u16 data = 0; 739169240Sjfv u8 i; 740169240Sjfv 741173788Sjfv /* 742173788Sjfv * In order to read a register from the PHY, we need to shift in a 743169240Sjfv * total of 18 bits from the PHY. The first two bit (turnaround) 744169240Sjfv * times are used to avoid contention on the MDIO pin when a read 745169240Sjfv * operation is performed. These two bits are ignored by us and 746169240Sjfv * thrown away. Bits are "shifted in" by raising the input to the 747169240Sjfv * Management Data Clock (setting the MDC bit) and then reading the 748169240Sjfv * value of the MDIO bit. 749169240Sjfv */ 750169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 751169240Sjfv 752173788Sjfv /* 753173788Sjfv * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 754169240Sjfv * input. 755169240Sjfv */ 756169240Sjfv ctrl &= ~E1000_CTRL_MDIO_DIR; 757169240Sjfv ctrl &= ~E1000_CTRL_MDIO; 758169240Sjfv 759169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 760169240Sjfv E1000_WRITE_FLUSH(hw); 761169240Sjfv 762173788Sjfv /* 763173788Sjfv * Raise and lower the clock before reading in the data. This accounts 764169240Sjfv * for the turnaround bits. The first clock occurred when we clocked 765169240Sjfv * out the last bit of the Register Address. 766169240Sjfv */ 767169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 768169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 769169240Sjfv 770169240Sjfv for (data = 0, i = 0; i < 16; i++) { 771169240Sjfv data <<= 1; 772169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 773169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 774169240Sjfv /* Check to see if we shifted in a "1". */ 775169240Sjfv if (ctrl & E1000_CTRL_MDIO) 776169240Sjfv data |= 1; 777169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 778169240Sjfv } 779169240Sjfv 780169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 781169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 782169240Sjfv 783169240Sjfv return data; 784169240Sjfv} 785169240Sjfv 786169240Sjfv/** 787169240Sjfv * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 788169589Sjfv * @hw: pointer to the HW structure 789169240Sjfv * 790169240Sjfv * Calls the function to force speed and duplex for the m88 PHY, and 791169240Sjfv * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 792169240Sjfv * then call the function for polarity reversal workaround. 793169240Sjfv **/ 794173788SjfvSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 795169240Sjfv{ 796169240Sjfv s32 ret_val; 797169240Sjfv 798169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 799169240Sjfv 800169240Sjfv ret_val = e1000_phy_force_speed_duplex_m88(hw); 801169240Sjfv if (ret_val) 802169240Sjfv goto out; 803169240Sjfv 804169240Sjfv if (!hw->mac.autoneg && 805169240Sjfv (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 806169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 807169240Sjfv 808169240Sjfvout: 809169240Sjfv return ret_val; 810169240Sjfv} 811169240Sjfv 812169240Sjfv/** 813169240Sjfv * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 814169589Sjfv * @hw: pointer to the HW structure 815169240Sjfv * 816169240Sjfv * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 817176667Sjfv * inadvertently. To workaround the issue, we disable the transmitter on 818169240Sjfv * the PHY until we have established the link partner's link parameters. 819169240Sjfv **/ 820173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 821169240Sjfv{ 822169240Sjfv s32 ret_val; 823169240Sjfv u16 mii_status_reg; 824169240Sjfv u16 i; 825173788Sjfv bool link; 826169240Sjfv 827169240Sjfv /* Polarity reversal workaround for forced 10F/10H links. */ 828169240Sjfv 829169240Sjfv /* Disable the transmitter on the PHY */ 830169240Sjfv 831169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 832169240Sjfv if (ret_val) 833169240Sjfv goto out; 834169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 835169240Sjfv if (ret_val) 836169240Sjfv goto out; 837169240Sjfv 838169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 839169240Sjfv if (ret_val) 840169240Sjfv goto out; 841169240Sjfv 842173788Sjfv /* 843173788Sjfv * This loop will early-out if the NO link condition has been met. 844169240Sjfv * In other words, DO NOT use e1000_phy_has_link_generic() here. 845169240Sjfv */ 846169240Sjfv for (i = PHY_FORCE_TIME; i > 0; i--) { 847173788Sjfv /* 848173788Sjfv * Read the MII Status Register and wait for Link Status bit 849169240Sjfv * to be clear. 850169240Sjfv */ 851169240Sjfv 852169240Sjfv ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 853169240Sjfv if (ret_val) 854169240Sjfv goto out; 855169240Sjfv 856169240Sjfv ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 857169240Sjfv if (ret_val) 858169240Sjfv goto out; 859169240Sjfv 860169240Sjfv if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 861169240Sjfv break; 862169240Sjfv msec_delay_irq(100); 863169240Sjfv } 864169240Sjfv 865169240Sjfv /* Recommended delay time after link has been lost */ 866169240Sjfv msec_delay_irq(1000); 867169240Sjfv 868169240Sjfv /* Now we will re-enable the transmitter on the PHY */ 869169240Sjfv 870169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 871169240Sjfv if (ret_val) 872169240Sjfv goto out; 873169240Sjfv msec_delay_irq(50); 874169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 875169240Sjfv if (ret_val) 876169240Sjfv goto out; 877169240Sjfv msec_delay_irq(50); 878169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 879169240Sjfv if (ret_val) 880169240Sjfv goto out; 881169240Sjfv msec_delay_irq(50); 882169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 883169240Sjfv if (ret_val) 884169240Sjfv goto out; 885169240Sjfv 886169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 887169240Sjfv if (ret_val) 888169240Sjfv goto out; 889169240Sjfv 890173788Sjfv /* 891173788Sjfv * Read the MII Status Register and wait for Link Status bit 892169240Sjfv * to be set. 893169240Sjfv */ 894169240Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 895169240Sjfv if (ret_val) 896169240Sjfv goto out; 897169240Sjfv 898169240Sjfvout: 899169240Sjfv return ret_val; 900169240Sjfv} 901169240Sjfv 902169240Sjfv/** 903169240Sjfv * e1000_phy_hw_reset_82543 - PHY hardware reset 904169589Sjfv * @hw: pointer to the HW structure 905169240Sjfv * 906169240Sjfv * Sets the PHY_RESET_DIR bit in the extended device control register 907169240Sjfv * to put the PHY into a reset and waits for completion. Once the reset 908169240Sjfv * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 909169240Sjfv * of reset. This is a function pointer entry point called by the api module. 910169240Sjfv **/ 911173788SjfvSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 912169240Sjfv{ 913169240Sjfv struct e1000_functions *func = &hw->func; 914169240Sjfv u32 ctrl_ext; 915169240Sjfv s32 ret_val; 916169240Sjfv 917169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_82543"); 918169240Sjfv 919173788Sjfv /* 920173788Sjfv * Read the Extended Device Control Register, assert the PHY_RESET_DIR 921169240Sjfv * bit to put the PHY into reset... 922169240Sjfv */ 923169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 924169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 925169240Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 926169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 927169240Sjfv E1000_WRITE_FLUSH(hw); 928169240Sjfv 929169240Sjfv msec_delay(10); 930169240Sjfv 931169240Sjfv /* ...then take it out of reset. */ 932169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 933169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 934169240Sjfv E1000_WRITE_FLUSH(hw); 935169240Sjfv 936169240Sjfv usec_delay(150); 937169240Sjfv 938169240Sjfv ret_val = func->get_cfg_done(hw); 939169240Sjfv 940169240Sjfv return ret_val; 941169240Sjfv} 942169240Sjfv 943169240Sjfv/** 944169240Sjfv * e1000_reset_hw_82543 - Reset hardware 945169589Sjfv * @hw: pointer to the HW structure 946169240Sjfv * 947169240Sjfv * This resets the hardware into a known state. This is a 948169240Sjfv * function pointer entry point called by the api module. 949169240Sjfv **/ 950173788SjfvSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw) 951169240Sjfv{ 952169240Sjfv u32 ctrl, icr; 953169240Sjfv s32 ret_val = E1000_SUCCESS; 954169240Sjfv 955169240Sjfv DEBUGFUNC("e1000_reset_hw_82543"); 956169240Sjfv 957169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 958169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 959169240Sjfv 960169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 961169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 962169240Sjfv E1000_WRITE_FLUSH(hw); 963169240Sjfv 964169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 965169240Sjfv 966173788Sjfv /* 967173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 968169240Sjfv * resetting the device 969169240Sjfv */ 970169240Sjfv msec_delay(10); 971169240Sjfv 972169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 973169240Sjfv 974169240Sjfv DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 975169240Sjfv if (hw->mac.type == e1000_82543) { 976169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 977169240Sjfv } else { 978173788Sjfv /* 979173788Sjfv * The 82544 can't ACK the 64-bit write when issuing the 980169240Sjfv * reset, so use IO-mapping as a workaround. 981169240Sjfv */ 982169240Sjfv E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 983169240Sjfv } 984169240Sjfv 985173788Sjfv /* 986173788Sjfv * After MAC reset, force reload of NVM to restore power-on 987169240Sjfv * settings to device. 988169240Sjfv */ 989169240Sjfv e1000_reload_nvm(hw); 990169240Sjfv msec_delay(2); 991169240Sjfv 992169240Sjfv /* Masking off and clearing any pending interrupts */ 993169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 994169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 995169240Sjfv 996169240Sjfv return ret_val; 997169240Sjfv} 998169240Sjfv 999169240Sjfv/** 1000169240Sjfv * e1000_init_hw_82543 - Initialize hardware 1001169589Sjfv * @hw: pointer to the HW structure 1002169240Sjfv * 1003169240Sjfv * This inits the hardware readying it for operation. 1004169240Sjfv **/ 1005173788SjfvSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw) 1006169240Sjfv{ 1007169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1008169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 1009169240Sjfv u32 ctrl; 1010169240Sjfv s32 ret_val; 1011169240Sjfv u16 i; 1012169240Sjfv 1013169240Sjfv DEBUGFUNC("e1000_init_hw_82543"); 1014169240Sjfv 1015169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1016169240Sjfv 1017173788Sjfv if (!dev_spec) { 1018169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1019169240Sjfv ret_val = -E1000_ERR_CONFIG; 1020169240Sjfv goto out; 1021169240Sjfv } 1022169240Sjfv 1023169240Sjfv /* Disabling VLAN filtering */ 1024169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 1025169240Sjfv e1000_clear_vfta(hw); 1026169240Sjfv 1027169240Sjfv /* Setup the receive address. */ 1028169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1029169240Sjfv 1030169240Sjfv /* Zero out the Multicast HASH table */ 1031169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 1032169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) { 1033169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1034169240Sjfv E1000_WRITE_FLUSH(hw); 1035169240Sjfv } 1036169240Sjfv 1037173788Sjfv /* 1038173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 1039169240Sjfv * determines if the adapter gives priority to receives, or if it 1040169240Sjfv * gives equal priority to transmits and receives. 1041169240Sjfv */ 1042169240Sjfv if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1043169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1044169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1045169240Sjfv } 1046169240Sjfv 1047169240Sjfv e1000_pcix_mmrbc_workaround_generic(hw); 1048169240Sjfv 1049169240Sjfv /* Setup link and flow control */ 1050169240Sjfv ret_val = e1000_setup_link(hw); 1051169240Sjfv 1052173788Sjfv /* 1053173788Sjfv * Clear all of the statistics registers (clear on read). It is 1054169240Sjfv * important that we do this after we have tried to establish link 1055169240Sjfv * because the symbol error count will increment wildly if there 1056169240Sjfv * is no link. 1057169240Sjfv */ 1058169240Sjfv e1000_clear_hw_cntrs_82543(hw); 1059169240Sjfv 1060169240Sjfvout: 1061169240Sjfv return ret_val; 1062169240Sjfv} 1063169240Sjfv 1064169240Sjfv/** 1065169240Sjfv * e1000_setup_link_82543 - Setup flow control and link settings 1066169589Sjfv * @hw: pointer to the HW structure 1067169240Sjfv * 1068169240Sjfv * Read the EEPROM to determine the initial polarity value and write the 1069169240Sjfv * extended device control register with the information before calling 1070169240Sjfv * the generic setup link function, which does the following: 1071169240Sjfv * Determines which flow control settings to use, then configures flow 1072169240Sjfv * control. Calls the appropriate media-specific link configuration 1073169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1074169240Sjfv * should be established. Assumes the hardware has previously been reset 1075169240Sjfv * and the transmitter and receiver are not enabled. 1076169240Sjfv **/ 1077173788SjfvSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw) 1078169240Sjfv{ 1079169240Sjfv u32 ctrl_ext; 1080169240Sjfv s32 ret_val; 1081169240Sjfv u16 data; 1082169240Sjfv 1083169240Sjfv DEBUGFUNC("e1000_setup_link_82543"); 1084169240Sjfv 1085173788Sjfv /* 1086173788Sjfv * Take the 4 bits from NVM word 0xF that determine the initial 1087169240Sjfv * polarity value for the SW controlled pins, and setup the 1088169240Sjfv * Extended Device Control reg with that info. 1089169240Sjfv * This is needed because one of the SW controlled pins is used for 1090169240Sjfv * signal detection. So this should be done before phy setup. 1091169240Sjfv */ 1092169240Sjfv if (hw->mac.type == e1000_82543) { 1093169240Sjfv ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1094169240Sjfv if (ret_val) { 1095169240Sjfv DEBUGOUT("NVM Read Error\n"); 1096169240Sjfv ret_val = -E1000_ERR_NVM; 1097169240Sjfv goto out; 1098169240Sjfv } 1099169240Sjfv ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1100169240Sjfv NVM_SWDPIO_EXT_SHIFT); 1101169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1102169240Sjfv } 1103169240Sjfv 1104169240Sjfv ret_val = e1000_setup_link_generic(hw); 1105169240Sjfv 1106169240Sjfvout: 1107169240Sjfv return ret_val; 1108169240Sjfv} 1109169240Sjfv 1110169240Sjfv/** 1111169240Sjfv * e1000_setup_copper_link_82543 - Configure copper link settings 1112169589Sjfv * @hw: pointer to the HW structure 1113169240Sjfv * 1114169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1115169240Sjfv * for link, once link is established calls to configure collision distance 1116169240Sjfv * and flow control are called. 1117169240Sjfv **/ 1118173788SjfvSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1119169240Sjfv{ 1120169240Sjfv u32 ctrl; 1121169240Sjfv s32 ret_val; 1122173788Sjfv bool link; 1123169240Sjfv 1124169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82543"); 1125169240Sjfv 1126169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1127173788Sjfv /* 1128173788Sjfv * With 82543, we need to force speed and duplex on the MAC 1129169240Sjfv * equal to what the PHY speed and duplex configuration is. 1130169240Sjfv * In addition, we need to perform a hardware reset on the 1131169240Sjfv * PHY to take it out of reset. 1132169240Sjfv */ 1133169240Sjfv if (hw->mac.type == e1000_82543) { 1134169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1135169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1136169240Sjfv ret_val = e1000_phy_hw_reset(hw); 1137169240Sjfv if (ret_val) 1138169240Sjfv goto out; 1139169240Sjfv hw->phy.reset_disable = FALSE; 1140169240Sjfv } else { 1141169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1142169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1143169240Sjfv } 1144169240Sjfv 1145169240Sjfv /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1146169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1147169240Sjfv if (ret_val) 1148169240Sjfv goto out; 1149169240Sjfv 1150169240Sjfv if (hw->mac.autoneg) { 1151173788Sjfv /* 1152173788Sjfv * Setup autoneg and flow control advertisement and perform 1153173788Sjfv * autonegotiation. 1154173788Sjfv */ 1155169240Sjfv ret_val = e1000_copper_link_autoneg(hw); 1156169240Sjfv if (ret_val) 1157169240Sjfv goto out; 1158169240Sjfv } else { 1159173788Sjfv /* 1160173788Sjfv * PHY will be set to 10H, 10F, 100H or 100F 1161173788Sjfv * depending on user settings. 1162173788Sjfv */ 1163169240Sjfv DEBUGOUT("Forcing Speed and Duplex\n"); 1164169240Sjfv ret_val = e1000_phy_force_speed_duplex_82543(hw); 1165169240Sjfv if (ret_val) { 1166169240Sjfv DEBUGOUT("Error Forcing Speed and Duplex\n"); 1167169240Sjfv goto out; 1168169240Sjfv } 1169169240Sjfv } 1170169240Sjfv 1171173788Sjfv /* 1172173788Sjfv * Check link status. Wait up to 100 microseconds for link to become 1173169240Sjfv * valid. 1174169240Sjfv */ 1175169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1176169240Sjfv COPPER_LINK_UP_LIMIT, 1177169240Sjfv 10, 1178169240Sjfv &link); 1179169240Sjfv if (ret_val) 1180169240Sjfv goto out; 1181169240Sjfv 1182169240Sjfv 1183169240Sjfv if (link) { 1184169240Sjfv DEBUGOUT("Valid link established!!!\n"); 1185169240Sjfv /* Config the MAC and PHY after link is up */ 1186173788Sjfv if (hw->mac.type == e1000_82544) { 1187169240Sjfv e1000_config_collision_dist_generic(hw); 1188173788Sjfv } else { 1189169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1190169240Sjfv if (ret_val) 1191169240Sjfv goto out; 1192169240Sjfv } 1193169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1194169240Sjfv } else { 1195169240Sjfv DEBUGOUT("Unable to establish link!!!\n"); 1196169240Sjfv } 1197169240Sjfv 1198169240Sjfvout: 1199169240Sjfv return ret_val; 1200169240Sjfv} 1201169240Sjfv 1202169240Sjfv/** 1203169240Sjfv * e1000_setup_fiber_link_82543 - Setup link for fiber 1204169589Sjfv * @hw: pointer to the HW structure 1205169240Sjfv * 1206169240Sjfv * Configures collision distance and flow control for fiber links. Upon 1207169240Sjfv * successful setup, poll for link. 1208169240Sjfv **/ 1209173788SjfvSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1210169240Sjfv{ 1211169240Sjfv u32 ctrl; 1212169240Sjfv s32 ret_val; 1213169240Sjfv 1214169240Sjfv DEBUGFUNC("e1000_setup_fiber_link_82543"); 1215169240Sjfv 1216169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1217169240Sjfv 1218169240Sjfv /* Take the link out of reset */ 1219169240Sjfv ctrl &= ~E1000_CTRL_LRST; 1220169240Sjfv 1221169240Sjfv e1000_config_collision_dist_generic(hw); 1222169240Sjfv 1223169240Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1224169240Sjfv if (ret_val) 1225169240Sjfv goto out; 1226169240Sjfv 1227169240Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1228169240Sjfv 1229169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1230169240Sjfv E1000_WRITE_FLUSH(hw); 1231169240Sjfv msec_delay(1); 1232169240Sjfv 1233173788Sjfv /* 1234176667Sjfv * For these adapters, the SW definable pin 1 is cleared when the 1235169240Sjfv * optics detect a signal. If we have a signal, then poll for a 1236169240Sjfv * "Link-Up" indication. 1237169240Sjfv */ 1238169240Sjfv if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1239169240Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1240169240Sjfv } else { 1241169240Sjfv DEBUGOUT("No signal detected\n"); 1242169240Sjfv } 1243169240Sjfv 1244169240Sjfvout: 1245169240Sjfv return ret_val; 1246169240Sjfv} 1247169240Sjfv 1248169240Sjfv/** 1249169240Sjfv * e1000_check_for_copper_link_82543 - Check for link (Copper) 1250169589Sjfv * @hw: pointer to the HW structure 1251169240Sjfv * 1252169240Sjfv * Checks the phy for link, if link exists, do the following: 1253169240Sjfv * - check for downshift 1254169240Sjfv * - do polarity workaround (if necessary) 1255169240Sjfv * - configure collision distance 1256169240Sjfv * - configure flow control after link up 1257169240Sjfv * - configure tbi compatibility 1258169240Sjfv **/ 1259173788SjfvSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1260169240Sjfv{ 1261169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1262169240Sjfv u32 icr, rctl; 1263169240Sjfv s32 ret_val; 1264169240Sjfv u16 speed, duplex; 1265173788Sjfv bool link; 1266169240Sjfv 1267169240Sjfv DEBUGFUNC("e1000_check_for_copper_link_82543"); 1268169240Sjfv 1269169240Sjfv if (!mac->get_link_status) { 1270169240Sjfv ret_val = E1000_SUCCESS; 1271169240Sjfv goto out; 1272169240Sjfv } 1273169240Sjfv 1274169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1275169240Sjfv if (ret_val) 1276169240Sjfv goto out; 1277169240Sjfv 1278169240Sjfv if (!link) 1279169240Sjfv goto out; /* No link detected */ 1280169240Sjfv 1281169240Sjfv mac->get_link_status = FALSE; 1282169240Sjfv 1283169240Sjfv e1000_check_downshift_generic(hw); 1284169240Sjfv 1285173788Sjfv /* 1286173788Sjfv * If we are forcing speed/duplex, then we can return since 1287169240Sjfv * we have already determined whether we have link or not. 1288169240Sjfv */ 1289169240Sjfv if (!mac->autoneg) { 1290173788Sjfv /* 1291173788Sjfv * If speed and duplex are forced to 10H or 10F, then we will 1292169240Sjfv * implement the polarity reversal workaround. We disable 1293169240Sjfv * interrupts first, and upon returning, place the devices 1294169240Sjfv * interrupt state to its previous value except for the link 1295169240Sjfv * status change interrupt which will happened due to the 1296169240Sjfv * execution of this workaround. 1297169240Sjfv */ 1298169240Sjfv if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1299169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1300169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 1301169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1302169240Sjfv E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1303169240Sjfv E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1304169240Sjfv } 1305169240Sjfv 1306169240Sjfv ret_val = -E1000_ERR_CONFIG; 1307169240Sjfv goto out; 1308169240Sjfv } 1309169240Sjfv 1310173788Sjfv /* 1311173788Sjfv * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1312169240Sjfv * have Si on board that is 82544 or newer, Auto 1313169240Sjfv * Speed Detection takes care of MAC speed/duplex 1314169240Sjfv * configuration. So we only need to configure Collision 1315169240Sjfv * Distance in the MAC. Otherwise, we need to force 1316169240Sjfv * speed/duplex on the MAC to the current PHY speed/duplex 1317169240Sjfv * settings. 1318169240Sjfv */ 1319169240Sjfv if (mac->type == e1000_82544) 1320169240Sjfv e1000_config_collision_dist_generic(hw); 1321169240Sjfv else { 1322169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1323169240Sjfv if (ret_val) { 1324169240Sjfv DEBUGOUT("Error configuring MAC to PHY settings\n"); 1325169240Sjfv goto out; 1326169240Sjfv } 1327169240Sjfv } 1328169240Sjfv 1329173788Sjfv /* 1330173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 1331169240Sjfv * First, we need to restore the desired flow control 1332169240Sjfv * settings because we may have had to re-autoneg with a 1333169240Sjfv * different link partner. 1334169240Sjfv */ 1335169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1336169240Sjfv if (ret_val) { 1337169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1338169240Sjfv } 1339169240Sjfv 1340173788Sjfv /* 1341173788Sjfv * At this point we know that we are on copper and we have 1342169240Sjfv * auto-negotiated link. These are conditions for checking the link 1343169240Sjfv * partner capability register. We use the link speed to determine if 1344169240Sjfv * TBI compatibility needs to be turned on or off. If the link is not 1345169240Sjfv * at gigabit speed, then TBI compatibility is not needed. If we are 1346169240Sjfv * at gigabit speed, we turn on TBI compatibility. 1347169240Sjfv */ 1348169240Sjfv if (e1000_tbi_compatibility_enabled_82543(hw)) { 1349169240Sjfv ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1350169240Sjfv if (ret_val) { 1351169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1352169240Sjfv return ret_val; 1353169240Sjfv } 1354169240Sjfv if (speed != SPEED_1000) { 1355173788Sjfv /* 1356173788Sjfv * If link speed is not set to gigabit speed, 1357169240Sjfv * we do not need to enable TBI compatibility. 1358169240Sjfv */ 1359169240Sjfv if (e1000_tbi_sbp_enabled_82543(hw)) { 1360173788Sjfv /* 1361173788Sjfv * If we previously were in the mode, 1362169240Sjfv * turn it off. 1363169240Sjfv */ 1364169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 1365169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1366169240Sjfv rctl &= ~E1000_RCTL_SBP; 1367169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1368169240Sjfv } 1369169240Sjfv } else { 1370173788Sjfv /* 1371173788Sjfv * If TBI compatibility is was previously off, 1372169240Sjfv * turn it on. For compatibility with a TBI link 1373169240Sjfv * partner, we will store bad packets. Some 1374169240Sjfv * frames have an additional byte on the end and 1375169240Sjfv * will look like CRC errors to to the hardware. 1376169240Sjfv */ 1377169240Sjfv if (!e1000_tbi_sbp_enabled_82543(hw)) { 1378169240Sjfv e1000_set_tbi_sbp_82543(hw, TRUE); 1379169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1380169240Sjfv rctl |= E1000_RCTL_SBP; 1381169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1382169240Sjfv } 1383169240Sjfv } 1384169240Sjfv } 1385169240Sjfvout: 1386169240Sjfv return ret_val; 1387169240Sjfv} 1388169240Sjfv 1389169240Sjfv/** 1390169240Sjfv * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1391169589Sjfv * @hw: pointer to the HW structure 1392169240Sjfv * 1393169240Sjfv * Checks for link up on the hardware. If link is not up and we have 1394169240Sjfv * a signal, then we need to force link up. 1395169240Sjfv **/ 1396173788SjfvSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1397169240Sjfv{ 1398169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1399169240Sjfv u32 rxcw, ctrl, status; 1400169240Sjfv s32 ret_val = E1000_SUCCESS; 1401169240Sjfv 1402169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1403169240Sjfv 1404169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1405173788Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1406173788Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1407169240Sjfv 1408173788Sjfv /* 1409173788Sjfv * If we don't have link (auto-negotiation failed or link partner 1410169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 1411169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 1412169240Sjfv * are receiving idles or data), we need to force link up. We also 1413169240Sjfv * need to give auto-negotiation time to complete, in case the cable 1414169240Sjfv * was just plugged in. The autoneg_failed flag does this. 1415169240Sjfv */ 1416169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1417169240Sjfv if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1418169240Sjfv (!(status & E1000_STATUS_LU)) && 1419169240Sjfv (!(rxcw & E1000_RXCW_C))) { 1420169240Sjfv if (mac->autoneg_failed == 0) { 1421169240Sjfv mac->autoneg_failed = 1; 1422169240Sjfv ret_val = 0; 1423169240Sjfv goto out; 1424169240Sjfv } 1425169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1426169240Sjfv 1427169240Sjfv /* Disable auto-negotiation in the TXCW register */ 1428169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1429169240Sjfv 1430169240Sjfv /* Force link-up and also force full-duplex. */ 1431169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1432169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1433169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1434169240Sjfv 1435169240Sjfv /* Configure Flow Control after forcing link up. */ 1436169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1437169240Sjfv if (ret_val) { 1438169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1439169240Sjfv goto out; 1440169240Sjfv } 1441169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1442173788Sjfv /* 1443173788Sjfv * If we are forcing link and we are receiving /C/ ordered 1444169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 1445169240Sjfv * and disable forced link in the Device Control register 1446169240Sjfv * in an attempt to auto-negotiate with our link partner. 1447169240Sjfv */ 1448169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1449169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1450169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1451169240Sjfv 1452169240Sjfv mac->serdes_has_link = TRUE; 1453169240Sjfv } 1454169240Sjfv 1455169240Sjfvout: 1456169240Sjfv return ret_val; 1457169240Sjfv} 1458169240Sjfv 1459169240Sjfv/** 1460169240Sjfv * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1461169589Sjfv * @hw: pointer to the HW structure 1462169240Sjfv * 1463169240Sjfv * For the 82543 silicon, we need to set the MAC to match the settings 1464169240Sjfv * of the PHY, even if the PHY is auto-negotiating. 1465169240Sjfv **/ 1466173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1467169240Sjfv{ 1468169240Sjfv u32 ctrl; 1469169240Sjfv s32 ret_val; 1470169240Sjfv u16 phy_data; 1471169240Sjfv 1472169240Sjfv DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1473169240Sjfv 1474169240Sjfv /* Set the bits to force speed and duplex */ 1475169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1476169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1477169240Sjfv ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1478169240Sjfv 1479173788Sjfv /* 1480173788Sjfv * Set up duplex in the Device Control and Transmit Control 1481169240Sjfv * registers depending on negotiated values. 1482169240Sjfv */ 1483169240Sjfv ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1484169240Sjfv if (ret_val) 1485169240Sjfv goto out; 1486169240Sjfv 1487169240Sjfv ctrl &= ~E1000_CTRL_FD; 1488169240Sjfv if (phy_data & M88E1000_PSSR_DPLX) 1489169240Sjfv ctrl |= E1000_CTRL_FD; 1490169240Sjfv 1491169240Sjfv e1000_config_collision_dist_generic(hw); 1492169240Sjfv 1493173788Sjfv /* 1494173788Sjfv * Set up speed in the Device Control register depending on 1495169240Sjfv * negotiated values. 1496169240Sjfv */ 1497169240Sjfv if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1498169240Sjfv ctrl |= E1000_CTRL_SPD_1000; 1499169240Sjfv else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1500169240Sjfv ctrl |= E1000_CTRL_SPD_100; 1501169240Sjfv 1502169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1503169240Sjfv 1504169240Sjfvout: 1505169240Sjfv return ret_val; 1506169240Sjfv} 1507169240Sjfv 1508169240Sjfv/** 1509169240Sjfv * e1000_write_vfta_82543 - Write value to VLAN filter table 1510169589Sjfv * @hw: pointer to the HW structure 1511169589Sjfv * @offset: the 32-bit offset in which to write the value to. 1512169589Sjfv * @value: the 32-bit value to write at location offset. 1513169240Sjfv * 1514169240Sjfv * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1515169240Sjfv * table. 1516169240Sjfv **/ 1517173788SjfvSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1518169240Sjfv{ 1519169240Sjfv u32 temp; 1520169240Sjfv 1521169240Sjfv DEBUGFUNC("e1000_write_vfta_82543"); 1522169240Sjfv 1523169240Sjfv if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1524169240Sjfv temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1525169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1526169240Sjfv E1000_WRITE_FLUSH(hw); 1527169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1528169240Sjfv E1000_WRITE_FLUSH(hw); 1529173788Sjfv } else { 1530169240Sjfv e1000_write_vfta_generic(hw, offset, value); 1531173788Sjfv } 1532169240Sjfv} 1533169240Sjfv 1534169240Sjfv/** 1535169240Sjfv * e1000_mta_set_82543 - Set multicast filter table address 1536169589Sjfv * @hw: pointer to the HW structure 1537169589Sjfv * @hash_value: determines the MTA register and bit to set 1538169240Sjfv * 1539169240Sjfv * The multicast table address is a register array of 32-bit registers. 1540169240Sjfv * The hash_value is used to determine what register the bit is in, the 1541169240Sjfv * current value is read, the new bit is OR'd in and the new value is 1542169240Sjfv * written back into the register. 1543169240Sjfv **/ 1544173788SjfvSTATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1545169240Sjfv{ 1546169240Sjfv u32 hash_bit, hash_reg, mta, temp; 1547169240Sjfv 1548169240Sjfv DEBUGFUNC("e1000_mta_set_82543"); 1549169240Sjfv 1550169240Sjfv hash_reg = (hash_value >> 5); 1551169240Sjfv 1552173788Sjfv /* 1553173788Sjfv * If we are on an 82544 and we are trying to write an odd offset 1554169240Sjfv * in the MTA, save off the previous entry before writing and 1555169240Sjfv * restore the old value after writing. 1556169240Sjfv */ 1557169240Sjfv if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1558169240Sjfv hash_reg &= (hw->mac.mta_reg_count - 1); 1559169240Sjfv hash_bit = hash_value & 0x1F; 1560169240Sjfv mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1561169240Sjfv mta |= (1 << hash_bit); 1562169240Sjfv temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1563169240Sjfv 1564169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1565169240Sjfv E1000_WRITE_FLUSH(hw); 1566169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1567169240Sjfv E1000_WRITE_FLUSH(hw); 1568173788Sjfv } else { 1569169240Sjfv e1000_mta_set_generic(hw, hash_value); 1570173788Sjfv } 1571169240Sjfv} 1572169240Sjfv 1573169240Sjfv/** 1574169240Sjfv * e1000_led_on_82543 - Turn on SW controllable LED 1575169589Sjfv * @hw: pointer to the HW structure 1576169240Sjfv * 1577169240Sjfv * Turns the SW defined LED on. This is a function pointer entry point 1578169240Sjfv * called by the api module. 1579169240Sjfv **/ 1580173788SjfvSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw) 1581169240Sjfv{ 1582169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1583169240Sjfv 1584169240Sjfv DEBUGFUNC("e1000_led_on_82543"); 1585169240Sjfv 1586169240Sjfv if (hw->mac.type == e1000_82544 && 1587173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1588176667Sjfv /* Clear SW-definable Pin 0 to turn on the LED */ 1589169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1590169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1591169240Sjfv } else { 1592169240Sjfv /* Fiber 82544 and all 82543 use this method */ 1593169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1594169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1595169240Sjfv } 1596169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1597169240Sjfv 1598169240Sjfv return E1000_SUCCESS; 1599169240Sjfv} 1600169240Sjfv 1601169240Sjfv/** 1602169240Sjfv * e1000_led_off_82543 - Turn off SW controllable LED 1603169589Sjfv * @hw: pointer to the HW structure 1604169240Sjfv * 1605169240Sjfv * Turns the SW defined LED off. This is a function pointer entry point 1606169240Sjfv * called by the api module. 1607169240Sjfv **/ 1608173788SjfvSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw) 1609169240Sjfv{ 1610169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1611169240Sjfv 1612169240Sjfv DEBUGFUNC("e1000_led_off_82543"); 1613169240Sjfv 1614169240Sjfv if (hw->mac.type == e1000_82544 && 1615173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1616176667Sjfv /* Set SW-definable Pin 0 to turn off the LED */ 1617169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1618169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1619169240Sjfv } else { 1620169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1621169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1622169240Sjfv } 1623169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1624169240Sjfv 1625169240Sjfv return E1000_SUCCESS; 1626169240Sjfv} 1627169240Sjfv 1628169240Sjfv/** 1629169240Sjfv * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1630169589Sjfv * @hw: pointer to the HW structure 1631169240Sjfv * 1632169240Sjfv * Clears the hardware counters by reading the counter registers. 1633169240Sjfv **/ 1634173788SjfvSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1635169240Sjfv{ 1636169240Sjfv volatile u32 temp; 1637169240Sjfv 1638169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1639169240Sjfv 1640169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1641169240Sjfv 1642169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC64); 1643169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC127); 1644169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC255); 1645169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC511); 1646169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1023); 1647169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1522); 1648169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC64); 1649169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC127); 1650169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC255); 1651169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC511); 1652169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1023); 1653169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1522); 1654169240Sjfv 1655169240Sjfv temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1656169240Sjfv temp = E1000_READ_REG(hw, E1000_RXERRC); 1657169240Sjfv temp = E1000_READ_REG(hw, E1000_TNCRS); 1658169240Sjfv temp = E1000_READ_REG(hw, E1000_CEXTERR); 1659169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTC); 1660169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTFC); 1661169240Sjfv} 1662