e1000_82543.c revision 173788
1169240Sjfv/******************************************************************************* 2169240Sjfv 3169240Sjfv Copyright (c) 2001-2007, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32169240Sjfv*******************************************************************************/ 33173788Sjfv/* $FreeBSD: head/sys/dev/em/e1000_82543.c 173788 2007-11-20 21:41:22Z jfv $ */ 34169240Sjfv 35169240Sjfv 36169240Sjfv/* e1000_82543 37169240Sjfv * e1000_82544 38169240Sjfv */ 39169240Sjfv 40169589Sjfv#include "e1000_api.h" 41169240Sjfv#include "e1000_82543.h" 42169240Sjfv 43169240Sjfvvoid e1000_init_function_pointers_82543(struct e1000_hw *hw); 44169240Sjfv 45173788SjfvSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 46173788SjfvSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 47173788SjfvSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 48173788SjfvSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 49173788Sjfv u16 *data); 50173788SjfvSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 51173788Sjfv u16 data); 52173788SjfvSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 53173788SjfvSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 54173788SjfvSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 55173788SjfvSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 56173788SjfvSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 57173788SjfvSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 58173788SjfvSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 59173788SjfvSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 60173788SjfvSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 61173788SjfvSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 62173788SjfvSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 63173788SjfvSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 64173788Sjfv u32 value); 65173788SjfvSTATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 66173788SjfvSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74173788Sjfv u16 count); 75173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 77169240Sjfv 78169240Sjfvstruct e1000_dev_spec_82543 { 79169240Sjfv u32 tbi_compatibility; 80173788Sjfv bool dma_fairness; 81173788Sjfv bool init_phy_disabled; 82169240Sjfv}; 83169240Sjfv 84169240Sjfv/** 85169240Sjfv * e1000_init_phy_params_82543 - Init PHY func ptrs. 86169589Sjfv * @hw: pointer to the HW structure 87169240Sjfv * 88169240Sjfv * This is a function pointer entry point called by the api module. 89169240Sjfv **/ 90173788SjfvSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 91169240Sjfv{ 92169240Sjfv struct e1000_phy_info *phy = &hw->phy; 93169240Sjfv struct e1000_functions *func = &hw->func; 94169240Sjfv s32 ret_val = E1000_SUCCESS; 95169240Sjfv 96169240Sjfv DEBUGFUNC("e1000_init_phy_params_82543"); 97169240Sjfv 98173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 99169240Sjfv phy->type = e1000_phy_none; 100169240Sjfv goto out; 101173788Sjfv } else { 102173788Sjfv func->power_up_phy = e1000_power_up_phy_copper; 103173788Sjfv func->power_down_phy = e1000_power_down_phy_copper; 104169240Sjfv } 105169240Sjfv 106169240Sjfv phy->addr = 1; 107169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108169240Sjfv phy->reset_delay_us = 10000; 109169240Sjfv phy->type = e1000_phy_m88; 110169240Sjfv 111169240Sjfv /* Function Pointers */ 112169240Sjfv func->check_polarity = e1000_check_polarity_m88; 113169240Sjfv func->commit_phy = e1000_phy_sw_reset_generic; 114169240Sjfv func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 115169240Sjfv func->get_cable_length = e1000_get_cable_length_m88; 116169240Sjfv func->get_cfg_done = e1000_get_cfg_done_generic; 117169240Sjfv func->read_phy_reg = (hw->mac.type == e1000_82543) 118169240Sjfv ? e1000_read_phy_reg_82543 119169240Sjfv : e1000_read_phy_reg_m88; 120169240Sjfv func->reset_phy = (hw->mac.type == e1000_82543) 121169240Sjfv ? e1000_phy_hw_reset_82543 122169240Sjfv : e1000_phy_hw_reset_generic; 123169240Sjfv func->write_phy_reg = (hw->mac.type == e1000_82543) 124169240Sjfv ? e1000_write_phy_reg_82543 125169240Sjfv : e1000_write_phy_reg_m88; 126169240Sjfv func->get_phy_info = e1000_get_phy_info_m88; 127169240Sjfv 128173788Sjfv /* 129173788Sjfv * The external PHY of the 82543 can be in a funky state. 130169240Sjfv * Resetting helps us read the PHY registers for acquiring 131169240Sjfv * the PHY ID. 132169240Sjfv */ 133169240Sjfv if (!e1000_init_phy_disabled_82543(hw)) { 134169240Sjfv ret_val = e1000_phy_hw_reset(hw); 135169240Sjfv if (ret_val) { 136169240Sjfv DEBUGOUT("Resetting PHY during init failed.\n"); 137169240Sjfv goto out; 138169240Sjfv } 139169240Sjfv msec_delay(20); 140169240Sjfv } 141169240Sjfv 142169240Sjfv ret_val = e1000_get_phy_id(hw); 143169240Sjfv if (ret_val) 144169240Sjfv goto out; 145169240Sjfv 146169240Sjfv /* Verify phy id */ 147169240Sjfv switch (hw->mac.type) { 148169240Sjfv case e1000_82543: 149169240Sjfv if (phy->id != M88E1000_E_PHY_ID) { 150169240Sjfv ret_val = -E1000_ERR_PHY; 151169240Sjfv goto out; 152169240Sjfv } 153169240Sjfv break; 154169240Sjfv case e1000_82544: 155169240Sjfv if (phy->id != M88E1000_I_PHY_ID) { 156169240Sjfv ret_val = -E1000_ERR_PHY; 157169240Sjfv goto out; 158169240Sjfv } 159169240Sjfv break; 160169240Sjfv default: 161169240Sjfv ret_val = -E1000_ERR_PHY; 162169240Sjfv goto out; 163169240Sjfv break; 164169240Sjfv } 165169240Sjfv 166169240Sjfvout: 167169240Sjfv return ret_val; 168169240Sjfv} 169169240Sjfv 170169240Sjfv/** 171169240Sjfv * e1000_init_nvm_params_82543 - Init NVM func ptrs. 172169589Sjfv * @hw: pointer to the HW structure 173169240Sjfv * 174169240Sjfv * This is a function pointer entry point called by the api module. 175169240Sjfv **/ 176173788SjfvSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 177169240Sjfv{ 178169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 179169240Sjfv struct e1000_functions *func = &hw->func; 180169240Sjfv 181169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82543"); 182169240Sjfv 183169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 184169240Sjfv nvm->word_size = 64; 185169240Sjfv nvm->delay_usec = 50; 186169240Sjfv nvm->address_bits = 6; 187169240Sjfv nvm->opcode_bits = 3; 188169240Sjfv 189169240Sjfv /* Function Pointers */ 190169240Sjfv func->read_nvm = e1000_read_nvm_microwire; 191169240Sjfv func->update_nvm = e1000_update_nvm_checksum_generic; 192169240Sjfv func->valid_led_default = e1000_valid_led_default_generic; 193169240Sjfv func->validate_nvm = e1000_validate_nvm_checksum_generic; 194169240Sjfv func->write_nvm = e1000_write_nvm_microwire; 195169240Sjfv 196169240Sjfv return E1000_SUCCESS; 197169240Sjfv} 198169240Sjfv 199169240Sjfv/** 200169240Sjfv * e1000_init_mac_params_82543 - Init MAC func ptrs. 201169589Sjfv * @hw: pointer to the HW structure 202169240Sjfv * 203169240Sjfv * This is a function pointer entry point called by the api module. 204169240Sjfv **/ 205173788SjfvSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 206169240Sjfv{ 207169240Sjfv struct e1000_mac_info *mac = &hw->mac; 208169240Sjfv struct e1000_functions *func = &hw->func; 209169240Sjfv s32 ret_val; 210169240Sjfv 211169240Sjfv DEBUGFUNC("e1000_init_mac_params_82543"); 212169240Sjfv 213169240Sjfv /* Set media type */ 214169240Sjfv switch (hw->device_id) { 215169240Sjfv case E1000_DEV_ID_82543GC_FIBER: 216169240Sjfv case E1000_DEV_ID_82544EI_FIBER: 217173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 218169240Sjfv break; 219169240Sjfv default: 220173788Sjfv hw->phy.media_type = e1000_media_type_copper; 221169240Sjfv break; 222169240Sjfv } 223169240Sjfv 224169240Sjfv /* Set mta register count */ 225169240Sjfv mac->mta_reg_count = 128; 226169240Sjfv /* Set rar entry count */ 227169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 228169240Sjfv 229169240Sjfv /* Function pointers */ 230169240Sjfv 231169240Sjfv /* bus type/speed/width */ 232169240Sjfv func->get_bus_info = e1000_get_bus_info_pci_generic; 233169240Sjfv /* reset */ 234169240Sjfv func->reset_hw = e1000_reset_hw_82543; 235169240Sjfv /* hw initialization */ 236169240Sjfv func->init_hw = e1000_init_hw_82543; 237169240Sjfv /* link setup */ 238169240Sjfv func->setup_link = e1000_setup_link_82543; 239169240Sjfv /* physical interface setup */ 240169240Sjfv func->setup_physical_interface = 241173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 242169240Sjfv ? e1000_setup_copper_link_82543 243169240Sjfv : e1000_setup_fiber_link_82543; 244169240Sjfv /* check for link */ 245169240Sjfv func->check_for_link = 246173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 247169240Sjfv ? e1000_check_for_copper_link_82543 248169240Sjfv : e1000_check_for_fiber_link_82543; 249169240Sjfv /* link info */ 250169240Sjfv func->get_link_up_info = 251173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 252169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 253169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 254169240Sjfv /* multicast address update */ 255173788Sjfv func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 256169240Sjfv /* writing VFTA */ 257169240Sjfv func->write_vfta = e1000_write_vfta_82543; 258169240Sjfv /* clearing VFTA */ 259169240Sjfv func->clear_vfta = e1000_clear_vfta_generic; 260169240Sjfv /* setting MTA */ 261169240Sjfv func->mta_set = e1000_mta_set_82543; 262169240Sjfv /* turn on/off LED */ 263169240Sjfv func->led_on = e1000_led_on_82543; 264169240Sjfv func->led_off = e1000_led_off_82543; 265169240Sjfv /* remove device */ 266169240Sjfv func->remove_device = e1000_remove_device_generic; 267169240Sjfv /* clear hardware counters */ 268169240Sjfv func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 269169240Sjfv 270169240Sjfv hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 271169240Sjfv 272169240Sjfv /* Device-specific structure allocation */ 273169240Sjfv ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 274169240Sjfv if (ret_val) 275169240Sjfv goto out; 276169240Sjfv 277169240Sjfv /* Set tbi compatibility */ 278169240Sjfv if ((hw->mac.type != e1000_82543) || 279173788Sjfv (hw->phy.media_type == e1000_media_type_fiber)) 280169240Sjfv e1000_set_tbi_compatibility_82543(hw, FALSE); 281169240Sjfv 282169240Sjfvout: 283169240Sjfv return ret_val; 284169240Sjfv} 285169240Sjfv 286169240Sjfv/** 287169240Sjfv * e1000_init_function_pointers_82543 - Init func ptrs. 288169589Sjfv * @hw: pointer to the HW structure 289169240Sjfv * 290169240Sjfv * The only function explicitly called by the api module to initialize 291169240Sjfv * all function pointers and parameters. 292169240Sjfv **/ 293173788Sjfvvoid e1000_init_function_pointers_82543(struct e1000_hw *hw) 294169240Sjfv{ 295169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82543"); 296169240Sjfv 297169240Sjfv hw->func.init_mac_params = e1000_init_mac_params_82543; 298169240Sjfv hw->func.init_nvm_params = e1000_init_nvm_params_82543; 299169240Sjfv hw->func.init_phy_params = e1000_init_phy_params_82543; 300169240Sjfv} 301169240Sjfv 302169240Sjfv/** 303169240Sjfv * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 304169589Sjfv * @hw: pointer to the HW structure 305169240Sjfv * 306169240Sjfv * Returns the curent status of 10-bit Interface (TBI) compatibility 307169240Sjfv * (enabled/disabled). 308169240Sjfv **/ 309173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 310169240Sjfv{ 311169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 312173788Sjfv bool state = FALSE; 313169240Sjfv 314169240Sjfv DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 315169240Sjfv 316169240Sjfv if (hw->mac.type != e1000_82543) { 317169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 318169240Sjfv goto out; 319169240Sjfv } 320169240Sjfv 321169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 322169240Sjfv 323173788Sjfv if (!dev_spec) { 324169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 325169240Sjfv goto out; 326169240Sjfv } 327169240Sjfv 328169240Sjfv state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 329169240Sjfv ? TRUE : FALSE; 330169240Sjfv 331169240Sjfvout: 332169240Sjfv return state; 333169240Sjfv} 334169240Sjfv 335169240Sjfv/** 336169240Sjfv * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 337169589Sjfv * @hw: pointer to the HW structure 338169589Sjfv * @state: enable/disable TBI compatibility 339169240Sjfv * 340169240Sjfv * Enables or disabled 10-bit Interface (TBI) compatibility. 341169240Sjfv **/ 342173788Sjfvvoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 343169240Sjfv{ 344169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 345169240Sjfv 346169240Sjfv DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 347169240Sjfv 348169240Sjfv if (hw->mac.type != e1000_82543) { 349169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 350169240Sjfv goto out; 351169240Sjfv } 352169240Sjfv 353169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 354169240Sjfv 355173788Sjfv if (!dev_spec) { 356169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 357169240Sjfv goto out; 358169240Sjfv } 359169240Sjfv 360169240Sjfv if (state) 361169240Sjfv dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 362169240Sjfv else 363169240Sjfv dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 364169240Sjfv 365169240Sjfvout: 366169240Sjfv return; 367169240Sjfv} 368169240Sjfv 369169240Sjfv/** 370169240Sjfv * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 371169589Sjfv * @hw: pointer to the HW structure 372169240Sjfv * 373169240Sjfv * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) 374169240Sjfv * (enabled/disabled). 375169240Sjfv **/ 376173788Sjfvbool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 377169240Sjfv{ 378169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 379173788Sjfv bool state = FALSE; 380169240Sjfv 381169240Sjfv DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 382169240Sjfv 383169240Sjfv if (hw->mac.type != e1000_82543) { 384169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 385169240Sjfv goto out; 386169240Sjfv } 387169240Sjfv 388169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 389169240Sjfv 390173788Sjfv if (!dev_spec) { 391169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 392169240Sjfv goto out; 393169240Sjfv } 394169240Sjfv 395169240Sjfv state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 396169240Sjfv ? TRUE : FALSE; 397169240Sjfv 398169240Sjfvout: 399169240Sjfv return state; 400169240Sjfv} 401169240Sjfv 402169240Sjfv/** 403169240Sjfv * e1000_set_tbi_sbp_82543 - Set TBI SBP 404169589Sjfv * @hw: pointer to the HW structure 405169589Sjfv * @state: enable/disable TBI store bad packet 406169240Sjfv * 407169240Sjfv * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 408169240Sjfv **/ 409173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 410169240Sjfv{ 411169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 412169240Sjfv 413169240Sjfv DEBUGFUNC("e1000_set_tbi_sbp_82543"); 414169240Sjfv 415169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 416169240Sjfv 417169240Sjfv if (state && e1000_tbi_compatibility_enabled_82543(hw)) 418169240Sjfv dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 419169240Sjfv else 420169240Sjfv dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 421169240Sjfv 422169240Sjfv return; 423169240Sjfv} 424169240Sjfv 425169240Sjfv/** 426169240Sjfv * e1000_init_phy_disabled_82543 - Returns init PHY status 427169589Sjfv * @hw: pointer to the HW structure 428169240Sjfv * 429169240Sjfv * Returns the current status of whether PHY initialization is disabled. 430169240Sjfv * True if PHY initialization is disabled else false. 431169240Sjfv **/ 432173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 433169240Sjfv{ 434169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 435173788Sjfv bool ret_val; 436169240Sjfv 437169240Sjfv DEBUGFUNC("e1000_init_phy_disabled_82543"); 438169240Sjfv 439169240Sjfv if (hw->mac.type != e1000_82543) { 440169240Sjfv ret_val = FALSE; 441169240Sjfv goto out; 442169240Sjfv } 443169240Sjfv 444169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 445169240Sjfv 446173788Sjfv if (!dev_spec) { 447169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 448169240Sjfv ret_val = FALSE; 449169240Sjfv goto out; 450169240Sjfv } 451169240Sjfv 452169240Sjfv ret_val = dev_spec->init_phy_disabled; 453169240Sjfv 454169240Sjfvout: 455169240Sjfv return ret_val; 456169240Sjfv} 457169240Sjfv 458169240Sjfv/** 459169240Sjfv * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 460169589Sjfv * @hw: pointer to the HW structure 461169589Sjfv * @stats: Struct containing statistic register values 462169589Sjfv * @frame_len: The length of the frame in question 463169589Sjfv * @mac_addr: The Ethernet destination address of the frame in question 464173788Sjfv * @max_frame_size: The maximum frame size 465169240Sjfv * 466169240Sjfv * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 467169240Sjfv **/ 468173788Sjfvvoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 469173788Sjfv struct e1000_hw_stats *stats, u32 frame_len, 470173788Sjfv u8 *mac_addr, u32 max_frame_size) 471169240Sjfv{ 472173788Sjfv if (!(e1000_tbi_sbp_enabled_82543(hw))) 473169240Sjfv goto out; 474169240Sjfv 475169240Sjfv /* First adjust the frame length. */ 476169240Sjfv frame_len--; 477173788Sjfv /* 478173788Sjfv * We need to adjust the statistics counters, since the hardware 479169240Sjfv * counters overcount this packet as a CRC error and undercount 480169240Sjfv * the packet as a good packet 481169240Sjfv */ 482169240Sjfv /* This packet should not be counted as a CRC error. */ 483169240Sjfv stats->crcerrs--; 484169240Sjfv /* This packet does count as a Good Packet Received. */ 485169240Sjfv stats->gprc++; 486169240Sjfv 487169240Sjfv /* Adjust the Good Octets received counters */ 488173788Sjfv stats->gorc += frame_len; 489173788Sjfv 490173788Sjfv /* 491173788Sjfv * Is this a broadcast or multicast? Check broadcast first, 492169240Sjfv * since the test for a multicast frame will test positive on 493169240Sjfv * a broadcast frame. 494169240Sjfv */ 495169240Sjfv if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 496169240Sjfv /* Broadcast packet */ 497169240Sjfv stats->bprc++; 498169240Sjfv else if (*mac_addr & 0x01) 499169240Sjfv /* Multicast packet */ 500169240Sjfv stats->mprc++; 501169240Sjfv 502173788Sjfv /* 503173788Sjfv * In this case, the hardware has overcounted the number of 504169240Sjfv * oversize frames. 505169240Sjfv */ 506173788Sjfv if ((frame_len == max_frame_size) && (stats->roc > 0)) 507169240Sjfv stats->roc--; 508169240Sjfv 509173788Sjfv /* 510173788Sjfv * Adjust the bin counters when the extra byte put the frame in the 511169240Sjfv * wrong bin. Remember that the frame_len was adjusted above. 512169240Sjfv */ 513169240Sjfv if (frame_len == 64) { 514169240Sjfv stats->prc64++; 515169240Sjfv stats->prc127--; 516169240Sjfv } else if (frame_len == 127) { 517169240Sjfv stats->prc127++; 518169240Sjfv stats->prc255--; 519169240Sjfv } else if (frame_len == 255) { 520169240Sjfv stats->prc255++; 521169240Sjfv stats->prc511--; 522169240Sjfv } else if (frame_len == 511) { 523169240Sjfv stats->prc511++; 524169240Sjfv stats->prc1023--; 525169240Sjfv } else if (frame_len == 1023) { 526169240Sjfv stats->prc1023++; 527169240Sjfv stats->prc1522--; 528169240Sjfv } else if (frame_len == 1522) { 529169240Sjfv stats->prc1522++; 530169240Sjfv } 531169240Sjfv 532169240Sjfvout: 533169240Sjfv return; 534169240Sjfv} 535169240Sjfv 536169240Sjfv/** 537169240Sjfv * e1000_read_phy_reg_82543 - Read PHY register 538169589Sjfv * @hw: pointer to the HW structure 539169589Sjfv * @offset: register offset to be read 540169589Sjfv * @data: pointer to the read data 541169240Sjfv * 542169240Sjfv * Reads the PHY at offset and stores the information read to data. 543169240Sjfv **/ 544173788SjfvSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 545169240Sjfv{ 546169240Sjfv u32 mdic; 547169240Sjfv s32 ret_val = E1000_SUCCESS; 548169240Sjfv 549169240Sjfv DEBUGFUNC("e1000_read_phy_reg_82543"); 550169240Sjfv 551169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 552169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 553169240Sjfv ret_val = -E1000_ERR_PARAM; 554169240Sjfv goto out; 555169240Sjfv } 556169240Sjfv 557173788Sjfv /* 558173788Sjfv * We must first send a preamble through the MDIO pin to signal the 559169240Sjfv * beginning of an MII instruction. This is done by sending 32 560169240Sjfv * consecutive "1" bits. 561169240Sjfv */ 562169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 563169240Sjfv 564173788Sjfv /* 565173788Sjfv * Now combine the next few fields that are required for a read 566169240Sjfv * operation. We use this method instead of calling the 567169240Sjfv * e1000_shift_out_mdi_bits routine five different times. The format 568169240Sjfv * of an MII read instruction consists of a shift out of 14 bits and 569169240Sjfv * is defined as follows: 570169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Offset> 571169240Sjfv * followed by a shift in of 18 bits. This first two bits shifted in 572169240Sjfv * are TurnAround bits used to avoid contention on the MDIO pin when a 573169240Sjfv * READ operation is performed. These two bits are thrown away 574169240Sjfv * followed by a shift in of 16 bits which contains the desired data. 575169240Sjfv */ 576169240Sjfv mdic = (offset | (hw->phy.addr << 5) | 577169240Sjfv (PHY_OP_READ << 10) | (PHY_SOF << 12)); 578169240Sjfv 579169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 580169240Sjfv 581173788Sjfv /* 582173788Sjfv * Now that we've shifted out the read command to the MII, we need to 583169240Sjfv * "shift in" the 16-bit value (18 total bits) of the requested PHY 584169240Sjfv * register address. 585169240Sjfv */ 586169240Sjfv *data = e1000_shift_in_mdi_bits_82543(hw); 587169240Sjfv 588169240Sjfvout: 589169240Sjfv return ret_val; 590169240Sjfv} 591169240Sjfv 592169240Sjfv/** 593169240Sjfv * e1000_write_phy_reg_82543 - Write PHY register 594169589Sjfv * @hw: pointer to the HW structure 595169589Sjfv * @offset: register offset to be written 596169589Sjfv * @data: pointer to the data to be written at offset 597169240Sjfv * 598169240Sjfv * Writes data to the PHY at offset. 599169240Sjfv **/ 600173788SjfvSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 601169240Sjfv{ 602169240Sjfv u32 mdic; 603169240Sjfv s32 ret_val = E1000_SUCCESS; 604169240Sjfv 605169240Sjfv DEBUGFUNC("e1000_write_phy_reg_82543"); 606169240Sjfv 607169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 608169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 609169240Sjfv ret_val = -E1000_ERR_PARAM; 610169240Sjfv goto out; 611169240Sjfv } 612169240Sjfv 613173788Sjfv /* 614173788Sjfv * We'll need to use the SW defined pins to shift the write command 615169240Sjfv * out to the PHY. We first send a preamble to the PHY to signal the 616169240Sjfv * beginning of the MII instruction. This is done by sending 32 617169240Sjfv * consecutive "1" bits. 618169240Sjfv */ 619169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 620169240Sjfv 621173788Sjfv /* 622173788Sjfv * Now combine the remaining required fields that will indicate a 623169240Sjfv * write operation. We use this method instead of calling the 624169240Sjfv * e1000_shift_out_mdi_bits routine for each field in the command. The 625169240Sjfv * format of a MII write instruction is as follows: 626169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 627169240Sjfv */ 628169240Sjfv mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 629169240Sjfv (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 630169240Sjfv mdic <<= 16; 631169240Sjfv mdic |= (u32) data; 632169240Sjfv 633169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 634169240Sjfv 635169240Sjfvout: 636169240Sjfv return ret_val; 637169240Sjfv} 638169240Sjfv 639169240Sjfv/** 640169240Sjfv * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 641169589Sjfv * @hw: pointer to the HW structure 642169589Sjfv * @ctrl: pointer to the control register 643169240Sjfv * 644169240Sjfv * Raise the management data input clock by setting the MDC bit in the control 645169240Sjfv * register. 646169240Sjfv **/ 647173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 648169240Sjfv{ 649173788Sjfv /* 650173788Sjfv * Raise the clock input to the Management Data Clock (by setting the 651169240Sjfv * MDC bit), and then delay a sufficient amount of time. 652169240Sjfv */ 653169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 654169240Sjfv E1000_WRITE_FLUSH(hw); 655169240Sjfv usec_delay(10); 656169240Sjfv} 657169240Sjfv 658169240Sjfv/** 659169240Sjfv * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 660169589Sjfv * @hw: pointer to the HW structure 661169589Sjfv * @ctrl: pointer to the control register 662169240Sjfv * 663169240Sjfv * Lower the management data input clock by clearing the MDC bit in the control 664169240Sjfv * register. 665169240Sjfv **/ 666173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 667169240Sjfv{ 668173788Sjfv /* 669173788Sjfv * Lower the clock input to the Management Data Clock (by clearing the 670169240Sjfv * MDC bit), and then delay a sufficient amount of time. 671169240Sjfv */ 672169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 673169240Sjfv E1000_WRITE_FLUSH(hw); 674169240Sjfv usec_delay(10); 675169240Sjfv} 676169240Sjfv 677169240Sjfv/** 678169240Sjfv * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 679169589Sjfv * @hw: pointer to the HW structure 680169589Sjfv * @data: data to send to the PHY 681169589Sjfv * @count: number of bits to shift out 682169240Sjfv * 683169240Sjfv * We need to shift 'count' bits out to the PHY. So, the value in the 684169240Sjfv * "data" parameter will be shifted out to the PHY one bit at a time. 685169240Sjfv * In order to do this, "data" must be broken down into bits. 686169240Sjfv **/ 687173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 688173788Sjfv u16 count) 689169240Sjfv{ 690169240Sjfv u32 ctrl, mask; 691169240Sjfv 692173788Sjfv /* 693173788Sjfv * We need to shift "count" number of bits out to the PHY. So, the 694169240Sjfv * value in the "data" parameter will be shifted out to the PHY one 695169240Sjfv * bit at a time. In order to do this, "data" must be broken down 696169240Sjfv * into bits. 697169240Sjfv */ 698169240Sjfv mask = 0x01; 699169240Sjfv mask <<= (count -1); 700169240Sjfv 701169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 702169240Sjfv 703169240Sjfv /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 704169240Sjfv ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 705169240Sjfv 706169240Sjfv while (mask) { 707173788Sjfv /* 708173788Sjfv * A "1" is shifted out to the PHY by setting the MDIO bit to 709169240Sjfv * "1" and then raising and lowering the Management Data Clock. 710169240Sjfv * A "0" is shifted out to the PHY by setting the MDIO bit to 711169240Sjfv * "0" and then raising and lowering the clock. 712169240Sjfv */ 713169240Sjfv if (data & mask) ctrl |= E1000_CTRL_MDIO; 714169240Sjfv else ctrl &= ~E1000_CTRL_MDIO; 715169240Sjfv 716169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 717169240Sjfv E1000_WRITE_FLUSH(hw); 718169240Sjfv 719169240Sjfv usec_delay(10); 720169240Sjfv 721169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 722169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 723169240Sjfv 724169240Sjfv mask >>= 1; 725169240Sjfv } 726169240Sjfv} 727169240Sjfv 728169240Sjfv/** 729169240Sjfv * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 730169589Sjfv * @hw: pointer to the HW structure 731169240Sjfv * 732169240Sjfv * In order to read a register from the PHY, we need to shift 18 bits 733169240Sjfv * in from the PHY. Bits are "shifted in" by raising the clock input to 734169240Sjfv * the PHY (setting the MDC bit), and then reading the value of the data out 735169240Sjfv * MDIO bit. 736169240Sjfv **/ 737173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 738169240Sjfv{ 739169240Sjfv u32 ctrl; 740169240Sjfv u16 data = 0; 741169240Sjfv u8 i; 742169240Sjfv 743173788Sjfv /* 744173788Sjfv * In order to read a register from the PHY, we need to shift in a 745169240Sjfv * total of 18 bits from the PHY. The first two bit (turnaround) 746169240Sjfv * times are used to avoid contention on the MDIO pin when a read 747169240Sjfv * operation is performed. These two bits are ignored by us and 748169240Sjfv * thrown away. Bits are "shifted in" by raising the input to the 749169240Sjfv * Management Data Clock (setting the MDC bit) and then reading the 750169240Sjfv * value of the MDIO bit. 751169240Sjfv */ 752169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 753169240Sjfv 754173788Sjfv /* 755173788Sjfv * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 756169240Sjfv * input. 757169240Sjfv */ 758169240Sjfv ctrl &= ~E1000_CTRL_MDIO_DIR; 759169240Sjfv ctrl &= ~E1000_CTRL_MDIO; 760169240Sjfv 761169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 762169240Sjfv E1000_WRITE_FLUSH(hw); 763169240Sjfv 764173788Sjfv /* 765173788Sjfv * Raise and lower the clock before reading in the data. This accounts 766169240Sjfv * for the turnaround bits. The first clock occurred when we clocked 767169240Sjfv * out the last bit of the Register Address. 768169240Sjfv */ 769169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 770169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 771169240Sjfv 772169240Sjfv for (data = 0, i = 0; i < 16; i++) { 773169240Sjfv data <<= 1; 774169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 775169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 776169240Sjfv /* Check to see if we shifted in a "1". */ 777169240Sjfv if (ctrl & E1000_CTRL_MDIO) 778169240Sjfv data |= 1; 779169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 780169240Sjfv } 781169240Sjfv 782169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 783169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 784169240Sjfv 785169240Sjfv return data; 786169240Sjfv} 787169240Sjfv 788169240Sjfv/** 789169240Sjfv * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 790169589Sjfv * @hw: pointer to the HW structure 791169240Sjfv * 792169240Sjfv * Calls the function to force speed and duplex for the m88 PHY, and 793169240Sjfv * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 794169240Sjfv * then call the function for polarity reversal workaround. 795169240Sjfv **/ 796173788SjfvSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 797169240Sjfv{ 798169240Sjfv s32 ret_val; 799169240Sjfv 800169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 801169240Sjfv 802169240Sjfv ret_val = e1000_phy_force_speed_duplex_m88(hw); 803169240Sjfv if (ret_val) 804169240Sjfv goto out; 805169240Sjfv 806169240Sjfv if (!hw->mac.autoneg && 807169240Sjfv (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 808169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 809169240Sjfv 810169240Sjfvout: 811169240Sjfv return ret_val; 812169240Sjfv} 813169240Sjfv 814169240Sjfv/** 815169240Sjfv * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 816169589Sjfv * @hw: pointer to the HW structure 817169240Sjfv * 818169240Sjfv * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 819169240Sjfv * inadvertantly. To workaround the issue, we disable the transmitter on 820169240Sjfv * the PHY until we have established the link partner's link parameters. 821169240Sjfv **/ 822173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 823169240Sjfv{ 824169240Sjfv s32 ret_val; 825169240Sjfv u16 mii_status_reg; 826169240Sjfv u16 i; 827173788Sjfv bool link; 828169240Sjfv 829169240Sjfv /* Polarity reversal workaround for forced 10F/10H links. */ 830169240Sjfv 831169240Sjfv /* Disable the transmitter on the PHY */ 832169240Sjfv 833169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 834169240Sjfv if (ret_val) 835169240Sjfv goto out; 836169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 837169240Sjfv if (ret_val) 838169240Sjfv goto out; 839169240Sjfv 840169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 841169240Sjfv if (ret_val) 842169240Sjfv goto out; 843169240Sjfv 844173788Sjfv /* 845173788Sjfv * This loop will early-out if the NO link condition has been met. 846169240Sjfv * In other words, DO NOT use e1000_phy_has_link_generic() here. 847169240Sjfv */ 848169240Sjfv for (i = PHY_FORCE_TIME; i > 0; i--) { 849173788Sjfv /* 850173788Sjfv * Read the MII Status Register and wait for Link Status bit 851169240Sjfv * to be clear. 852169240Sjfv */ 853169240Sjfv 854169240Sjfv ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 855169240Sjfv if (ret_val) 856169240Sjfv goto out; 857169240Sjfv 858169240Sjfv ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 859169240Sjfv if (ret_val) 860169240Sjfv goto out; 861169240Sjfv 862169240Sjfv if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 863169240Sjfv break; 864169240Sjfv msec_delay_irq(100); 865169240Sjfv } 866169240Sjfv 867169240Sjfv /* Recommended delay time after link has been lost */ 868169240Sjfv msec_delay_irq(1000); 869169240Sjfv 870169240Sjfv /* Now we will re-enable the transmitter on the PHY */ 871169240Sjfv 872169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 873169240Sjfv if (ret_val) 874169240Sjfv goto out; 875169240Sjfv msec_delay_irq(50); 876169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 877169240Sjfv if (ret_val) 878169240Sjfv goto out; 879169240Sjfv msec_delay_irq(50); 880169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 881169240Sjfv if (ret_val) 882169240Sjfv goto out; 883169240Sjfv msec_delay_irq(50); 884169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 885169240Sjfv if (ret_val) 886169240Sjfv goto out; 887169240Sjfv 888169240Sjfv ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 889169240Sjfv if (ret_val) 890169240Sjfv goto out; 891169240Sjfv 892173788Sjfv /* 893173788Sjfv * Read the MII Status Register and wait for Link Status bit 894169240Sjfv * to be set. 895169240Sjfv */ 896169240Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 897169240Sjfv if (ret_val) 898169240Sjfv goto out; 899169240Sjfv 900169240Sjfvout: 901169240Sjfv return ret_val; 902169240Sjfv} 903169240Sjfv 904169240Sjfv/** 905169240Sjfv * e1000_phy_hw_reset_82543 - PHY hardware reset 906169589Sjfv * @hw: pointer to the HW structure 907169240Sjfv * 908169240Sjfv * Sets the PHY_RESET_DIR bit in the extended device control register 909169240Sjfv * to put the PHY into a reset and waits for completion. Once the reset 910169240Sjfv * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 911169240Sjfv * of reset. This is a function pointer entry point called by the api module. 912169240Sjfv **/ 913173788SjfvSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 914169240Sjfv{ 915169240Sjfv struct e1000_functions *func = &hw->func; 916169240Sjfv u32 ctrl_ext; 917169240Sjfv s32 ret_val; 918169240Sjfv 919169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_82543"); 920169240Sjfv 921173788Sjfv /* 922173788Sjfv * Read the Extended Device Control Register, assert the PHY_RESET_DIR 923169240Sjfv * bit to put the PHY into reset... 924169240Sjfv */ 925169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 926169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 927169240Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 928169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 929169240Sjfv E1000_WRITE_FLUSH(hw); 930169240Sjfv 931169240Sjfv msec_delay(10); 932169240Sjfv 933169240Sjfv /* ...then take it out of reset. */ 934169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 935169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 936169240Sjfv E1000_WRITE_FLUSH(hw); 937169240Sjfv 938169240Sjfv usec_delay(150); 939169240Sjfv 940169240Sjfv ret_val = func->get_cfg_done(hw); 941169240Sjfv 942169240Sjfv return ret_val; 943169240Sjfv} 944169240Sjfv 945169240Sjfv/** 946169240Sjfv * e1000_reset_hw_82543 - Reset hardware 947169589Sjfv * @hw: pointer to the HW structure 948169240Sjfv * 949169240Sjfv * This resets the hardware into a known state. This is a 950169240Sjfv * function pointer entry point called by the api module. 951169240Sjfv **/ 952173788SjfvSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw) 953169240Sjfv{ 954169240Sjfv u32 ctrl, icr; 955169240Sjfv s32 ret_val = E1000_SUCCESS; 956169240Sjfv 957169240Sjfv DEBUGFUNC("e1000_reset_hw_82543"); 958169240Sjfv 959169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 960169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 961169240Sjfv 962169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 963169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 964169240Sjfv E1000_WRITE_FLUSH(hw); 965169240Sjfv 966169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 967169240Sjfv 968173788Sjfv /* 969173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 970169240Sjfv * resetting the device 971169240Sjfv */ 972169240Sjfv msec_delay(10); 973169240Sjfv 974169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 975169240Sjfv 976169240Sjfv DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 977169240Sjfv if (hw->mac.type == e1000_82543) { 978169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 979169240Sjfv } else { 980173788Sjfv /* 981173788Sjfv * The 82544 can't ACK the 64-bit write when issuing the 982169240Sjfv * reset, so use IO-mapping as a workaround. 983169240Sjfv */ 984169240Sjfv E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 985169240Sjfv } 986169240Sjfv 987173788Sjfv /* 988173788Sjfv * After MAC reset, force reload of NVM to restore power-on 989169240Sjfv * settings to device. 990169240Sjfv */ 991169240Sjfv e1000_reload_nvm(hw); 992169240Sjfv msec_delay(2); 993169240Sjfv 994169240Sjfv /* Masking off and clearing any pending interrupts */ 995169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 996169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 997169240Sjfv 998169240Sjfv return ret_val; 999169240Sjfv} 1000169240Sjfv 1001169240Sjfv/** 1002169240Sjfv * e1000_init_hw_82543 - Initialize hardware 1003169589Sjfv * @hw: pointer to the HW structure 1004169240Sjfv * 1005169240Sjfv * This inits the hardware readying it for operation. 1006169240Sjfv **/ 1007173788SjfvSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw) 1008169240Sjfv{ 1009169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1010169240Sjfv struct e1000_dev_spec_82543 *dev_spec; 1011169240Sjfv u32 ctrl; 1012169240Sjfv s32 ret_val; 1013169240Sjfv u16 i; 1014169240Sjfv 1015169240Sjfv DEBUGFUNC("e1000_init_hw_82543"); 1016169240Sjfv 1017169240Sjfv dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1018169240Sjfv 1019173788Sjfv if (!dev_spec) { 1020169240Sjfv DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1021169240Sjfv ret_val = -E1000_ERR_CONFIG; 1022169240Sjfv goto out; 1023169240Sjfv } 1024169240Sjfv 1025169240Sjfv /* Disabling VLAN filtering */ 1026169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 1027169240Sjfv e1000_clear_vfta(hw); 1028169240Sjfv 1029169240Sjfv /* Setup the receive address. */ 1030169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1031169240Sjfv 1032169240Sjfv /* Zero out the Multicast HASH table */ 1033169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 1034169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) { 1035169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1036169240Sjfv E1000_WRITE_FLUSH(hw); 1037169240Sjfv } 1038169240Sjfv 1039173788Sjfv /* 1040173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 1041169240Sjfv * determines if the adapter gives priority to receives, or if it 1042169240Sjfv * gives equal priority to transmits and receives. 1043169240Sjfv */ 1044169240Sjfv if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1045169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1046169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1047169240Sjfv } 1048169240Sjfv 1049169240Sjfv e1000_pcix_mmrbc_workaround_generic(hw); 1050169240Sjfv 1051169240Sjfv /* Setup link and flow control */ 1052169240Sjfv ret_val = e1000_setup_link(hw); 1053169240Sjfv 1054173788Sjfv /* 1055173788Sjfv * Clear all of the statistics registers (clear on read). It is 1056169240Sjfv * important that we do this after we have tried to establish link 1057169240Sjfv * because the symbol error count will increment wildly if there 1058169240Sjfv * is no link. 1059169240Sjfv */ 1060169240Sjfv e1000_clear_hw_cntrs_82543(hw); 1061169240Sjfv 1062169240Sjfvout: 1063169240Sjfv return ret_val; 1064169240Sjfv} 1065169240Sjfv 1066169240Sjfv/** 1067169240Sjfv * e1000_setup_link_82543 - Setup flow control and link settings 1068169589Sjfv * @hw: pointer to the HW structure 1069169240Sjfv * 1070169240Sjfv * Read the EEPROM to determine the initial polarity value and write the 1071169240Sjfv * extended device control register with the information before calling 1072169240Sjfv * the generic setup link function, which does the following: 1073169240Sjfv * Determines which flow control settings to use, then configures flow 1074169240Sjfv * control. Calls the appropriate media-specific link configuration 1075169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1076169240Sjfv * should be established. Assumes the hardware has previously been reset 1077169240Sjfv * and the transmitter and receiver are not enabled. 1078169240Sjfv **/ 1079173788SjfvSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw) 1080169240Sjfv{ 1081169240Sjfv u32 ctrl_ext; 1082169240Sjfv s32 ret_val; 1083169240Sjfv u16 data; 1084169240Sjfv 1085169240Sjfv DEBUGFUNC("e1000_setup_link_82543"); 1086169240Sjfv 1087173788Sjfv /* 1088173788Sjfv * Take the 4 bits from NVM word 0xF that determine the initial 1089169240Sjfv * polarity value for the SW controlled pins, and setup the 1090169240Sjfv * Extended Device Control reg with that info. 1091169240Sjfv * This is needed because one of the SW controlled pins is used for 1092169240Sjfv * signal detection. So this should be done before phy setup. 1093169240Sjfv */ 1094169240Sjfv if (hw->mac.type == e1000_82543) { 1095169240Sjfv ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1096169240Sjfv if (ret_val) { 1097169240Sjfv DEBUGOUT("NVM Read Error\n"); 1098169240Sjfv ret_val = -E1000_ERR_NVM; 1099169240Sjfv goto out; 1100169240Sjfv } 1101169240Sjfv ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1102169240Sjfv NVM_SWDPIO_EXT_SHIFT); 1103169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1104169240Sjfv } 1105169240Sjfv 1106169240Sjfv ret_val = e1000_setup_link_generic(hw); 1107169240Sjfv 1108169240Sjfvout: 1109169240Sjfv return ret_val; 1110169240Sjfv} 1111169240Sjfv 1112169240Sjfv/** 1113169240Sjfv * e1000_setup_copper_link_82543 - Configure copper link settings 1114169589Sjfv * @hw: pointer to the HW structure 1115169240Sjfv * 1116169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1117169240Sjfv * for link, once link is established calls to configure collision distance 1118169240Sjfv * and flow control are called. 1119169240Sjfv **/ 1120173788SjfvSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1121169240Sjfv{ 1122169240Sjfv u32 ctrl; 1123169240Sjfv s32 ret_val; 1124173788Sjfv bool link; 1125169240Sjfv 1126169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82543"); 1127169240Sjfv 1128169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1129173788Sjfv /* 1130173788Sjfv * With 82543, we need to force speed and duplex on the MAC 1131169240Sjfv * equal to what the PHY speed and duplex configuration is. 1132169240Sjfv * In addition, we need to perform a hardware reset on the 1133169240Sjfv * PHY to take it out of reset. 1134169240Sjfv */ 1135169240Sjfv if (hw->mac.type == e1000_82543) { 1136169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1137169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1138169240Sjfv ret_val = e1000_phy_hw_reset(hw); 1139169240Sjfv if (ret_val) 1140169240Sjfv goto out; 1141169240Sjfv hw->phy.reset_disable = FALSE; 1142169240Sjfv } else { 1143169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1144169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1145169240Sjfv } 1146169240Sjfv 1147169240Sjfv /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1148169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1149169240Sjfv if (ret_val) 1150169240Sjfv goto out; 1151169240Sjfv 1152169240Sjfv if (hw->mac.autoneg) { 1153173788Sjfv /* 1154173788Sjfv * Setup autoneg and flow control advertisement and perform 1155173788Sjfv * autonegotiation. 1156173788Sjfv */ 1157169240Sjfv ret_val = e1000_copper_link_autoneg(hw); 1158169240Sjfv if (ret_val) 1159169240Sjfv goto out; 1160169240Sjfv } else { 1161173788Sjfv /* 1162173788Sjfv * PHY will be set to 10H, 10F, 100H or 100F 1163173788Sjfv * depending on user settings. 1164173788Sjfv */ 1165169240Sjfv DEBUGOUT("Forcing Speed and Duplex\n"); 1166169240Sjfv ret_val = e1000_phy_force_speed_duplex_82543(hw); 1167169240Sjfv if (ret_val) { 1168169240Sjfv DEBUGOUT("Error Forcing Speed and Duplex\n"); 1169169240Sjfv goto out; 1170169240Sjfv } 1171169240Sjfv } 1172169240Sjfv 1173173788Sjfv /* 1174173788Sjfv * Check link status. Wait up to 100 microseconds for link to become 1175169240Sjfv * valid. 1176169240Sjfv */ 1177169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1178169240Sjfv COPPER_LINK_UP_LIMIT, 1179169240Sjfv 10, 1180169240Sjfv &link); 1181169240Sjfv if (ret_val) 1182169240Sjfv goto out; 1183169240Sjfv 1184169240Sjfv 1185169240Sjfv if (link) { 1186169240Sjfv DEBUGOUT("Valid link established!!!\n"); 1187169240Sjfv /* Config the MAC and PHY after link is up */ 1188173788Sjfv if (hw->mac.type == e1000_82544) { 1189169240Sjfv e1000_config_collision_dist_generic(hw); 1190173788Sjfv } else { 1191169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1192169240Sjfv if (ret_val) 1193169240Sjfv goto out; 1194169240Sjfv } 1195169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1196169240Sjfv } else { 1197169240Sjfv DEBUGOUT("Unable to establish link!!!\n"); 1198169240Sjfv } 1199169240Sjfv 1200169240Sjfvout: 1201169240Sjfv return ret_val; 1202169240Sjfv} 1203169240Sjfv 1204169240Sjfv/** 1205169240Sjfv * e1000_setup_fiber_link_82543 - Setup link for fiber 1206169589Sjfv * @hw: pointer to the HW structure 1207169240Sjfv * 1208169240Sjfv * Configures collision distance and flow control for fiber links. Upon 1209169240Sjfv * successful setup, poll for link. 1210169240Sjfv **/ 1211173788SjfvSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1212169240Sjfv{ 1213169240Sjfv u32 ctrl; 1214169240Sjfv s32 ret_val; 1215169240Sjfv 1216169240Sjfv DEBUGFUNC("e1000_setup_fiber_link_82543"); 1217169240Sjfv 1218169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1219169240Sjfv 1220169240Sjfv /* Take the link out of reset */ 1221169240Sjfv ctrl &= ~E1000_CTRL_LRST; 1222169240Sjfv 1223169240Sjfv e1000_config_collision_dist_generic(hw); 1224169240Sjfv 1225169240Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1226169240Sjfv if (ret_val) 1227169240Sjfv goto out; 1228169240Sjfv 1229169240Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1230169240Sjfv 1231169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1232169240Sjfv E1000_WRITE_FLUSH(hw); 1233169240Sjfv msec_delay(1); 1234169240Sjfv 1235173788Sjfv /* 1236173788Sjfv * For these adapters, the SW defineable pin 1 is cleared when the 1237169240Sjfv * optics detect a signal. If we have a signal, then poll for a 1238169240Sjfv * "Link-Up" indication. 1239169240Sjfv */ 1240169240Sjfv if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1241169240Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1242169240Sjfv } else { 1243169240Sjfv DEBUGOUT("No signal detected\n"); 1244169240Sjfv } 1245169240Sjfv 1246169240Sjfvout: 1247169240Sjfv return ret_val; 1248169240Sjfv} 1249169240Sjfv 1250169240Sjfv/** 1251169240Sjfv * e1000_check_for_copper_link_82543 - Check for link (Copper) 1252169589Sjfv * @hw: pointer to the HW structure 1253169240Sjfv * 1254169240Sjfv * Checks the phy for link, if link exists, do the following: 1255169240Sjfv * - check for downshift 1256169240Sjfv * - do polarity workaround (if necessary) 1257169240Sjfv * - configure collision distance 1258169240Sjfv * - configure flow control after link up 1259169240Sjfv * - configure tbi compatibility 1260169240Sjfv **/ 1261173788SjfvSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1262169240Sjfv{ 1263169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1264169240Sjfv u32 icr, rctl; 1265169240Sjfv s32 ret_val; 1266169240Sjfv u16 speed, duplex; 1267173788Sjfv bool link; 1268169240Sjfv 1269169240Sjfv DEBUGFUNC("e1000_check_for_copper_link_82543"); 1270169240Sjfv 1271169240Sjfv if (!mac->get_link_status) { 1272169240Sjfv ret_val = E1000_SUCCESS; 1273169240Sjfv goto out; 1274169240Sjfv } 1275169240Sjfv 1276169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1277169240Sjfv if (ret_val) 1278169240Sjfv goto out; 1279169240Sjfv 1280169240Sjfv if (!link) 1281169240Sjfv goto out; /* No link detected */ 1282169240Sjfv 1283169240Sjfv mac->get_link_status = FALSE; 1284169240Sjfv 1285169240Sjfv e1000_check_downshift_generic(hw); 1286169240Sjfv 1287173788Sjfv /* 1288173788Sjfv * If we are forcing speed/duplex, then we can return since 1289169240Sjfv * we have already determined whether we have link or not. 1290169240Sjfv */ 1291169240Sjfv if (!mac->autoneg) { 1292173788Sjfv /* 1293173788Sjfv * If speed and duplex are forced to 10H or 10F, then we will 1294169240Sjfv * implement the polarity reversal workaround. We disable 1295169240Sjfv * interrupts first, and upon returning, place the devices 1296169240Sjfv * interrupt state to its previous value except for the link 1297169240Sjfv * status change interrupt which will happened due to the 1298169240Sjfv * execution of this workaround. 1299169240Sjfv */ 1300169240Sjfv if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1301169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1302169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 1303169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1304169240Sjfv E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1305169240Sjfv E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1306169240Sjfv } 1307169240Sjfv 1308169240Sjfv ret_val = -E1000_ERR_CONFIG; 1309169240Sjfv goto out; 1310169240Sjfv } 1311169240Sjfv 1312173788Sjfv /* 1313173788Sjfv * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1314169240Sjfv * have Si on board that is 82544 or newer, Auto 1315169240Sjfv * Speed Detection takes care of MAC speed/duplex 1316169240Sjfv * configuration. So we only need to configure Collision 1317169240Sjfv * Distance in the MAC. Otherwise, we need to force 1318169240Sjfv * speed/duplex on the MAC to the current PHY speed/duplex 1319169240Sjfv * settings. 1320169240Sjfv */ 1321169240Sjfv if (mac->type == e1000_82544) 1322169240Sjfv e1000_config_collision_dist_generic(hw); 1323169240Sjfv else { 1324169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1325169240Sjfv if (ret_val) { 1326169240Sjfv DEBUGOUT("Error configuring MAC to PHY settings\n"); 1327169240Sjfv goto out; 1328169240Sjfv } 1329169240Sjfv } 1330169240Sjfv 1331173788Sjfv /* 1332173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 1333169240Sjfv * First, we need to restore the desired flow control 1334169240Sjfv * settings because we may have had to re-autoneg with a 1335169240Sjfv * different link partner. 1336169240Sjfv */ 1337169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1338169240Sjfv if (ret_val) { 1339169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1340169240Sjfv } 1341169240Sjfv 1342173788Sjfv /* 1343173788Sjfv * At this point we know that we are on copper and we have 1344169240Sjfv * auto-negotiated link. These are conditions for checking the link 1345169240Sjfv * partner capability register. We use the link speed to determine if 1346169240Sjfv * TBI compatibility needs to be turned on or off. If the link is not 1347169240Sjfv * at gigabit speed, then TBI compatibility is not needed. If we are 1348169240Sjfv * at gigabit speed, we turn on TBI compatibility. 1349169240Sjfv */ 1350169240Sjfv if (e1000_tbi_compatibility_enabled_82543(hw)) { 1351169240Sjfv ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1352169240Sjfv if (ret_val) { 1353169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1354169240Sjfv return ret_val; 1355169240Sjfv } 1356169240Sjfv if (speed != SPEED_1000) { 1357173788Sjfv /* 1358173788Sjfv * If link speed is not set to gigabit speed, 1359169240Sjfv * we do not need to enable TBI compatibility. 1360169240Sjfv */ 1361169240Sjfv if (e1000_tbi_sbp_enabled_82543(hw)) { 1362173788Sjfv /* 1363173788Sjfv * If we previously were in the mode, 1364169240Sjfv * turn it off. 1365169240Sjfv */ 1366169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 1367169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1368169240Sjfv rctl &= ~E1000_RCTL_SBP; 1369169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1370169240Sjfv } 1371169240Sjfv } else { 1372173788Sjfv /* 1373173788Sjfv * If TBI compatibility is was previously off, 1374169240Sjfv * turn it on. For compatibility with a TBI link 1375169240Sjfv * partner, we will store bad packets. Some 1376169240Sjfv * frames have an additional byte on the end and 1377169240Sjfv * will look like CRC errors to to the hardware. 1378169240Sjfv */ 1379169240Sjfv if (!e1000_tbi_sbp_enabled_82543(hw)) { 1380169240Sjfv e1000_set_tbi_sbp_82543(hw, TRUE); 1381169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1382169240Sjfv rctl |= E1000_RCTL_SBP; 1383169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1384169240Sjfv } 1385169240Sjfv } 1386169240Sjfv } 1387169240Sjfvout: 1388169240Sjfv return ret_val; 1389169240Sjfv} 1390169240Sjfv 1391169240Sjfv/** 1392169240Sjfv * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1393169589Sjfv * @hw: pointer to the HW structure 1394169240Sjfv * 1395169240Sjfv * Checks for link up on the hardware. If link is not up and we have 1396169240Sjfv * a signal, then we need to force link up. 1397169240Sjfv **/ 1398173788SjfvSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1399169240Sjfv{ 1400169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1401169240Sjfv u32 rxcw, ctrl, status; 1402169240Sjfv s32 ret_val = E1000_SUCCESS; 1403169240Sjfv 1404169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1405169240Sjfv 1406169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1407173788Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1408173788Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1409169240Sjfv 1410173788Sjfv /* 1411173788Sjfv * If we don't have link (auto-negotiation failed or link partner 1412169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 1413169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 1414169240Sjfv * are receiving idles or data), we need to force link up. We also 1415169240Sjfv * need to give auto-negotiation time to complete, in case the cable 1416169240Sjfv * was just plugged in. The autoneg_failed flag does this. 1417169240Sjfv */ 1418169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1419169240Sjfv if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1420169240Sjfv (!(status & E1000_STATUS_LU)) && 1421169240Sjfv (!(rxcw & E1000_RXCW_C))) { 1422169240Sjfv if (mac->autoneg_failed == 0) { 1423169240Sjfv mac->autoneg_failed = 1; 1424169240Sjfv ret_val = 0; 1425169240Sjfv goto out; 1426169240Sjfv } 1427169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1428169240Sjfv 1429169240Sjfv /* Disable auto-negotiation in the TXCW register */ 1430169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1431169240Sjfv 1432169240Sjfv /* Force link-up and also force full-duplex. */ 1433169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1434169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1435169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1436169240Sjfv 1437169240Sjfv /* Configure Flow Control after forcing link up. */ 1438169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1439169240Sjfv if (ret_val) { 1440169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1441169240Sjfv goto out; 1442169240Sjfv } 1443169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1444173788Sjfv /* 1445173788Sjfv * If we are forcing link and we are receiving /C/ ordered 1446169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 1447169240Sjfv * and disable forced link in the Device Control register 1448169240Sjfv * in an attempt to auto-negotiate with our link partner. 1449169240Sjfv */ 1450169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1451169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1452169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1453169240Sjfv 1454169240Sjfv mac->serdes_has_link = TRUE; 1455169240Sjfv } 1456169240Sjfv 1457169240Sjfvout: 1458169240Sjfv return ret_val; 1459169240Sjfv} 1460169240Sjfv 1461169240Sjfv/** 1462169240Sjfv * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1463169589Sjfv * @hw: pointer to the HW structure 1464169240Sjfv * 1465169240Sjfv * For the 82543 silicon, we need to set the MAC to match the settings 1466169240Sjfv * of the PHY, even if the PHY is auto-negotiating. 1467169240Sjfv **/ 1468173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1469169240Sjfv{ 1470169240Sjfv u32 ctrl; 1471169240Sjfv s32 ret_val; 1472169240Sjfv u16 phy_data; 1473169240Sjfv 1474169240Sjfv DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1475169240Sjfv 1476169240Sjfv /* Set the bits to force speed and duplex */ 1477169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1478169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1479169240Sjfv ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1480169240Sjfv 1481173788Sjfv /* 1482173788Sjfv * Set up duplex in the Device Control and Transmit Control 1483169240Sjfv * registers depending on negotiated values. 1484169240Sjfv */ 1485169240Sjfv ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1486169240Sjfv if (ret_val) 1487169240Sjfv goto out; 1488169240Sjfv 1489169240Sjfv ctrl &= ~E1000_CTRL_FD; 1490169240Sjfv if (phy_data & M88E1000_PSSR_DPLX) 1491169240Sjfv ctrl |= E1000_CTRL_FD; 1492169240Sjfv 1493169240Sjfv e1000_config_collision_dist_generic(hw); 1494169240Sjfv 1495173788Sjfv /* 1496173788Sjfv * Set up speed in the Device Control register depending on 1497169240Sjfv * negotiated values. 1498169240Sjfv */ 1499169240Sjfv if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1500169240Sjfv ctrl |= E1000_CTRL_SPD_1000; 1501169240Sjfv else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1502169240Sjfv ctrl |= E1000_CTRL_SPD_100; 1503169240Sjfv 1504169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1505169240Sjfv 1506169240Sjfvout: 1507169240Sjfv return ret_val; 1508169240Sjfv} 1509169240Sjfv 1510169240Sjfv/** 1511169240Sjfv * e1000_write_vfta_82543 - Write value to VLAN filter table 1512169589Sjfv * @hw: pointer to the HW structure 1513169589Sjfv * @offset: the 32-bit offset in which to write the value to. 1514169589Sjfv * @value: the 32-bit value to write at location offset. 1515169240Sjfv * 1516169240Sjfv * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1517169240Sjfv * table. 1518169240Sjfv **/ 1519173788SjfvSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1520169240Sjfv{ 1521169240Sjfv u32 temp; 1522169240Sjfv 1523169240Sjfv DEBUGFUNC("e1000_write_vfta_82543"); 1524169240Sjfv 1525169240Sjfv if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1526169240Sjfv temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1527169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1528169240Sjfv E1000_WRITE_FLUSH(hw); 1529169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1530169240Sjfv E1000_WRITE_FLUSH(hw); 1531173788Sjfv } else { 1532169240Sjfv e1000_write_vfta_generic(hw, offset, value); 1533173788Sjfv } 1534169240Sjfv} 1535169240Sjfv 1536169240Sjfv/** 1537169240Sjfv * e1000_mta_set_82543 - Set multicast filter table address 1538169589Sjfv * @hw: pointer to the HW structure 1539169589Sjfv * @hash_value: determines the MTA register and bit to set 1540169240Sjfv * 1541169240Sjfv * The multicast table address is a register array of 32-bit registers. 1542169240Sjfv * The hash_value is used to determine what register the bit is in, the 1543169240Sjfv * current value is read, the new bit is OR'd in and the new value is 1544169240Sjfv * written back into the register. 1545169240Sjfv **/ 1546173788SjfvSTATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1547169240Sjfv{ 1548169240Sjfv u32 hash_bit, hash_reg, mta, temp; 1549169240Sjfv 1550169240Sjfv DEBUGFUNC("e1000_mta_set_82543"); 1551169240Sjfv 1552169240Sjfv hash_reg = (hash_value >> 5); 1553169240Sjfv 1554173788Sjfv /* 1555173788Sjfv * If we are on an 82544 and we are trying to write an odd offset 1556169240Sjfv * in the MTA, save off the previous entry before writing and 1557169240Sjfv * restore the old value after writing. 1558169240Sjfv */ 1559169240Sjfv if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1560169240Sjfv hash_reg &= (hw->mac.mta_reg_count - 1); 1561169240Sjfv hash_bit = hash_value & 0x1F; 1562169240Sjfv mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1563169240Sjfv mta |= (1 << hash_bit); 1564169240Sjfv temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1565169240Sjfv 1566169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1567169240Sjfv E1000_WRITE_FLUSH(hw); 1568169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1569169240Sjfv E1000_WRITE_FLUSH(hw); 1570173788Sjfv } else { 1571169240Sjfv e1000_mta_set_generic(hw, hash_value); 1572173788Sjfv } 1573169240Sjfv} 1574169240Sjfv 1575169240Sjfv/** 1576169240Sjfv * e1000_led_on_82543 - Turn on SW controllable LED 1577169589Sjfv * @hw: pointer to the HW structure 1578169240Sjfv * 1579169240Sjfv * Turns the SW defined LED on. This is a function pointer entry point 1580169240Sjfv * called by the api module. 1581169240Sjfv **/ 1582173788SjfvSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw) 1583169240Sjfv{ 1584169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1585169240Sjfv 1586169240Sjfv DEBUGFUNC("e1000_led_on_82543"); 1587169240Sjfv 1588169240Sjfv if (hw->mac.type == e1000_82544 && 1589173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1590169240Sjfv /* Clear SW-defineable Pin 0 to turn on the LED */ 1591169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1592169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1593169240Sjfv } else { 1594169240Sjfv /* Fiber 82544 and all 82543 use this method */ 1595169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1596169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1597169240Sjfv } 1598169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1599169240Sjfv 1600169240Sjfv return E1000_SUCCESS; 1601169240Sjfv} 1602169240Sjfv 1603169240Sjfv/** 1604169240Sjfv * e1000_led_off_82543 - Turn off SW controllable LED 1605169589Sjfv * @hw: pointer to the HW structure 1606169240Sjfv * 1607169240Sjfv * Turns the SW defined LED off. This is a function pointer entry point 1608169240Sjfv * called by the api module. 1609169240Sjfv **/ 1610173788SjfvSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw) 1611169240Sjfv{ 1612169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1613169240Sjfv 1614169240Sjfv DEBUGFUNC("e1000_led_off_82543"); 1615169240Sjfv 1616169240Sjfv if (hw->mac.type == e1000_82544 && 1617173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1618169240Sjfv /* Set SW-defineable Pin 0 to turn off the LED */ 1619169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1620169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1621169240Sjfv } else { 1622169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1623169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1624169240Sjfv } 1625169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1626169240Sjfv 1627169240Sjfv return E1000_SUCCESS; 1628169240Sjfv} 1629169240Sjfv 1630169240Sjfv/** 1631169240Sjfv * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1632169589Sjfv * @hw: pointer to the HW structure 1633169240Sjfv * 1634169240Sjfv * Clears the hardware counters by reading the counter registers. 1635169240Sjfv **/ 1636173788SjfvSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1637169240Sjfv{ 1638169240Sjfv volatile u32 temp; 1639169240Sjfv 1640169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1641169240Sjfv 1642169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1643169240Sjfv 1644169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC64); 1645169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC127); 1646169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC255); 1647169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC511); 1648169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1023); 1649169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1522); 1650169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC64); 1651169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC127); 1652169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC255); 1653169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC511); 1654169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1023); 1655169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1522); 1656169240Sjfv 1657169240Sjfv temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1658169240Sjfv temp = E1000_READ_REG(hw, E1000_RXERRC); 1659169240Sjfv temp = E1000_READ_REG(hw, E1000_TNCRS); 1660169240Sjfv temp = E1000_READ_REG(hw, E1000_CEXTERR); 1661169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTC); 1662169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTFC); 1663169240Sjfv} 1664