1177867Sjfv/****************************************************************************** 2169240Sjfv 3235527Sjfv Copyright (c) 2001-2011, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82543GC Gigabit Ethernet Controller (Fiber) 37185353Sjfv * 82543GC Gigabit Ethernet Controller (Copper) 38185353Sjfv * 82544EI Gigabit Ethernet Controller (Copper) 39185353Sjfv * 82544EI Gigabit Ethernet Controller (Fiber) 40185353Sjfv * 82544GC Gigabit Ethernet Controller (Copper) 41185353Sjfv * 82544GC Gigabit Ethernet Controller (LOM) 42169240Sjfv */ 43169240Sjfv 44169589Sjfv#include "e1000_api.h" 45169240Sjfv 46177867Sjfvstatic s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50173788Sjfv u16 *data); 51177867Sjfvstatic s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52173788Sjfv u16 data); 53177867Sjfvstatic s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54177867Sjfvstatic s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55177867Sjfvstatic s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_init_hw_82543(struct e1000_hw *hw); 57177867Sjfvstatic s32 e1000_setup_link_82543(struct e1000_hw *hw); 58177867Sjfvstatic s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59177867Sjfvstatic s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60177867Sjfvstatic s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61177867Sjfvstatic s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62177867Sjfvstatic s32 e1000_led_on_82543(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_led_off_82543(struct e1000_hw *hw); 64177867Sjfvstatic void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65173788Sjfv u32 value); 66177867Sjfvstatic void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74173788Sjfv u16 count); 75173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 77200528Sjfvstatic s32 e1000_read_mac_addr_82543(struct e1000_hw *hw); 78169240Sjfv 79200528Sjfv 80169240Sjfv/** 81169240Sjfv * e1000_init_phy_params_82543 - Init PHY func ptrs. 82169589Sjfv * @hw: pointer to the HW structure 83169240Sjfv **/ 84177867Sjfvstatic s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 85169240Sjfv{ 86169240Sjfv struct e1000_phy_info *phy = &hw->phy; 87169240Sjfv s32 ret_val = E1000_SUCCESS; 88169240Sjfv 89169240Sjfv DEBUGFUNC("e1000_init_phy_params_82543"); 90169240Sjfv 91173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 92169240Sjfv phy->type = e1000_phy_none; 93169240Sjfv goto out; 94173788Sjfv } else { 95177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 96177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper; 97169240Sjfv } 98169240Sjfv 99169240Sjfv phy->addr = 1; 100169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 101169240Sjfv phy->reset_delay_us = 10000; 102169240Sjfv phy->type = e1000_phy_m88; 103169240Sjfv 104169240Sjfv /* Function Pointers */ 105177867Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 106177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 107177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 108177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 109177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 110177867Sjfv phy->ops.read_reg = (hw->mac.type == e1000_82543) 111169240Sjfv ? e1000_read_phy_reg_82543 112169240Sjfv : e1000_read_phy_reg_m88; 113177867Sjfv phy->ops.reset = (hw->mac.type == e1000_82543) 114169240Sjfv ? e1000_phy_hw_reset_82543 115169240Sjfv : e1000_phy_hw_reset_generic; 116177867Sjfv phy->ops.write_reg = (hw->mac.type == e1000_82543) 117169240Sjfv ? e1000_write_phy_reg_82543 118169240Sjfv : e1000_write_phy_reg_m88; 119177867Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 120169240Sjfv 121173788Sjfv /* 122173788Sjfv * The external PHY of the 82543 can be in a funky state. 123169240Sjfv * Resetting helps us read the PHY registers for acquiring 124169240Sjfv * the PHY ID. 125169240Sjfv */ 126169240Sjfv if (!e1000_init_phy_disabled_82543(hw)) { 127177867Sjfv ret_val = phy->ops.reset(hw); 128169240Sjfv if (ret_val) { 129169240Sjfv DEBUGOUT("Resetting PHY during init failed.\n"); 130169240Sjfv goto out; 131169240Sjfv } 132169240Sjfv msec_delay(20); 133169240Sjfv } 134169240Sjfv 135169240Sjfv ret_val = e1000_get_phy_id(hw); 136169240Sjfv if (ret_val) 137169240Sjfv goto out; 138169240Sjfv 139169240Sjfv /* Verify phy id */ 140169240Sjfv switch (hw->mac.type) { 141169240Sjfv case e1000_82543: 142169240Sjfv if (phy->id != M88E1000_E_PHY_ID) { 143169240Sjfv ret_val = -E1000_ERR_PHY; 144169240Sjfv goto out; 145169240Sjfv } 146169240Sjfv break; 147169240Sjfv case e1000_82544: 148169240Sjfv if (phy->id != M88E1000_I_PHY_ID) { 149169240Sjfv ret_val = -E1000_ERR_PHY; 150169240Sjfv goto out; 151169240Sjfv } 152169240Sjfv break; 153169240Sjfv default: 154169240Sjfv ret_val = -E1000_ERR_PHY; 155169240Sjfv goto out; 156169240Sjfv break; 157169240Sjfv } 158169240Sjfv 159169240Sjfvout: 160169240Sjfv return ret_val; 161169240Sjfv} 162169240Sjfv 163169240Sjfv/** 164169240Sjfv * e1000_init_nvm_params_82543 - Init NVM func ptrs. 165169589Sjfv * @hw: pointer to the HW structure 166169240Sjfv **/ 167177867Sjfvstatic s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 168169240Sjfv{ 169169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 170169240Sjfv 171169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82543"); 172169240Sjfv 173169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 174169240Sjfv nvm->word_size = 64; 175169240Sjfv nvm->delay_usec = 50; 176169240Sjfv nvm->address_bits = 6; 177169240Sjfv nvm->opcode_bits = 3; 178169240Sjfv 179169240Sjfv /* Function Pointers */ 180177867Sjfv nvm->ops.read = e1000_read_nvm_microwire; 181177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 182177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_generic; 183177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 184177867Sjfv nvm->ops.write = e1000_write_nvm_microwire; 185169240Sjfv 186169240Sjfv return E1000_SUCCESS; 187169240Sjfv} 188169240Sjfv 189169240Sjfv/** 190169240Sjfv * e1000_init_mac_params_82543 - Init MAC func ptrs. 191169589Sjfv * @hw: pointer to the HW structure 192169240Sjfv **/ 193177867Sjfvstatic s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 194169240Sjfv{ 195169240Sjfv struct e1000_mac_info *mac = &hw->mac; 196169240Sjfv 197169240Sjfv DEBUGFUNC("e1000_init_mac_params_82543"); 198169240Sjfv 199169240Sjfv /* Set media type */ 200169240Sjfv switch (hw->device_id) { 201169240Sjfv case E1000_DEV_ID_82543GC_FIBER: 202169240Sjfv case E1000_DEV_ID_82544EI_FIBER: 203173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 204169240Sjfv break; 205169240Sjfv default: 206173788Sjfv hw->phy.media_type = e1000_media_type_copper; 207169240Sjfv break; 208169240Sjfv } 209169240Sjfv 210169240Sjfv /* Set mta register count */ 211169240Sjfv mac->mta_reg_count = 128; 212169240Sjfv /* Set rar entry count */ 213169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 214169240Sjfv 215169240Sjfv /* Function pointers */ 216169240Sjfv 217169240Sjfv /* bus type/speed/width */ 218177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 219185353Sjfv /* function id */ 220185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 221169240Sjfv /* reset */ 222177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82543; 223169240Sjfv /* hw initialization */ 224177867Sjfv mac->ops.init_hw = e1000_init_hw_82543; 225169240Sjfv /* link setup */ 226177867Sjfv mac->ops.setup_link = e1000_setup_link_82543; 227169240Sjfv /* physical interface setup */ 228177867Sjfv mac->ops.setup_physical_interface = 229173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 230169240Sjfv ? e1000_setup_copper_link_82543 231169240Sjfv : e1000_setup_fiber_link_82543; 232169240Sjfv /* check for link */ 233177867Sjfv mac->ops.check_for_link = 234173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 235169240Sjfv ? e1000_check_for_copper_link_82543 236169240Sjfv : e1000_check_for_fiber_link_82543; 237169240Sjfv /* link info */ 238177867Sjfv mac->ops.get_link_up_info = 239173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 240169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 241169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 242169240Sjfv /* multicast address update */ 243177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 244169240Sjfv /* writing VFTA */ 245177867Sjfv mac->ops.write_vfta = e1000_write_vfta_82543; 246169240Sjfv /* clearing VFTA */ 247177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 248200528Sjfv /* read mac address */ 249200528Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82543; 250169240Sjfv /* turn on/off LED */ 251177867Sjfv mac->ops.led_on = e1000_led_on_82543; 252177867Sjfv mac->ops.led_off = e1000_led_off_82543; 253169240Sjfv /* clear hardware counters */ 254177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 255169240Sjfv 256169240Sjfv /* Set tbi compatibility */ 257169240Sjfv if ((hw->mac.type != e1000_82543) || 258173788Sjfv (hw->phy.media_type == e1000_media_type_fiber)) 259169240Sjfv e1000_set_tbi_compatibility_82543(hw, FALSE); 260169240Sjfv 261185353Sjfv return E1000_SUCCESS; 262169240Sjfv} 263169240Sjfv 264169240Sjfv/** 265169240Sjfv * e1000_init_function_pointers_82543 - Init func ptrs. 266169589Sjfv * @hw: pointer to the HW structure 267169240Sjfv * 268185353Sjfv * Called to initialize all function pointers and parameters. 269169240Sjfv **/ 270173788Sjfvvoid e1000_init_function_pointers_82543(struct e1000_hw *hw) 271169240Sjfv{ 272169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82543"); 273169240Sjfv 274177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82543; 275177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 276177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82543; 277169240Sjfv} 278169240Sjfv 279169240Sjfv/** 280169240Sjfv * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 281169589Sjfv * @hw: pointer to the HW structure 282169240Sjfv * 283176667Sjfv * Returns the current status of 10-bit Interface (TBI) compatibility 284169240Sjfv * (enabled/disabled). 285169240Sjfv **/ 286173788Sjfvstatic bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 287169240Sjfv{ 288185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 289173788Sjfv bool state = FALSE; 290169240Sjfv 291169240Sjfv DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 292169240Sjfv 293169240Sjfv if (hw->mac.type != e1000_82543) { 294169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 295169240Sjfv goto out; 296169240Sjfv } 297169240Sjfv 298169240Sjfv state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 299169240Sjfv ? TRUE : FALSE; 300169240Sjfv 301169240Sjfvout: 302169240Sjfv return state; 303169240Sjfv} 304169240Sjfv 305169240Sjfv/** 306169240Sjfv * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 307169589Sjfv * @hw: pointer to the HW structure 308169589Sjfv * @state: enable/disable TBI compatibility 309169240Sjfv * 310169240Sjfv * Enables or disabled 10-bit Interface (TBI) compatibility. 311169240Sjfv **/ 312173788Sjfvvoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 313169240Sjfv{ 314185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 315169240Sjfv 316169240Sjfv DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 317169240Sjfv 318169240Sjfv if (hw->mac.type != e1000_82543) { 319169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 320169240Sjfv goto out; 321169240Sjfv } 322169240Sjfv 323169240Sjfv if (state) 324169240Sjfv dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 325169240Sjfv else 326169240Sjfv dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 327169240Sjfv 328169240Sjfvout: 329169240Sjfv return; 330169240Sjfv} 331169240Sjfv 332169240Sjfv/** 333169240Sjfv * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 334169589Sjfv * @hw: pointer to the HW structure 335169240Sjfv * 336176667Sjfv * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 337169240Sjfv * (enabled/disabled). 338169240Sjfv **/ 339173788Sjfvbool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 340169240Sjfv{ 341185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 342173788Sjfv bool state = FALSE; 343169240Sjfv 344169240Sjfv DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 345169240Sjfv 346169240Sjfv if (hw->mac.type != e1000_82543) { 347169240Sjfv DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 348169240Sjfv goto out; 349169240Sjfv } 350169240Sjfv 351169240Sjfv state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 352169240Sjfv ? TRUE : FALSE; 353169240Sjfv 354169240Sjfvout: 355169240Sjfv return state; 356169240Sjfv} 357169240Sjfv 358169240Sjfv/** 359169240Sjfv * e1000_set_tbi_sbp_82543 - Set TBI SBP 360169589Sjfv * @hw: pointer to the HW structure 361169589Sjfv * @state: enable/disable TBI store bad packet 362169240Sjfv * 363169240Sjfv * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 364169240Sjfv **/ 365173788Sjfvstatic void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 366169240Sjfv{ 367185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 368169240Sjfv 369169240Sjfv DEBUGFUNC("e1000_set_tbi_sbp_82543"); 370169240Sjfv 371169240Sjfv if (state && e1000_tbi_compatibility_enabled_82543(hw)) 372169240Sjfv dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 373169240Sjfv else 374169240Sjfv dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 375169240Sjfv 376169240Sjfv return; 377169240Sjfv} 378169240Sjfv 379169240Sjfv/** 380169240Sjfv * e1000_init_phy_disabled_82543 - Returns init PHY status 381169589Sjfv * @hw: pointer to the HW structure 382169240Sjfv * 383169240Sjfv * Returns the current status of whether PHY initialization is disabled. 384177867Sjfv * True if PHY initialization is disabled else FALSE. 385169240Sjfv **/ 386173788Sjfvstatic bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 387169240Sjfv{ 388185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 389173788Sjfv bool ret_val; 390169240Sjfv 391169240Sjfv DEBUGFUNC("e1000_init_phy_disabled_82543"); 392169240Sjfv 393169240Sjfv if (hw->mac.type != e1000_82543) { 394169240Sjfv ret_val = FALSE; 395169240Sjfv goto out; 396169240Sjfv } 397169240Sjfv 398169240Sjfv ret_val = dev_spec->init_phy_disabled; 399169240Sjfv 400169240Sjfvout: 401169240Sjfv return ret_val; 402169240Sjfv} 403169240Sjfv 404169240Sjfv/** 405169240Sjfv * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 406169589Sjfv * @hw: pointer to the HW structure 407169589Sjfv * @stats: Struct containing statistic register values 408169589Sjfv * @frame_len: The length of the frame in question 409169589Sjfv * @mac_addr: The Ethernet destination address of the frame in question 410173788Sjfv * @max_frame_size: The maximum frame size 411169240Sjfv * 412169240Sjfv * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 413169240Sjfv **/ 414173788Sjfvvoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 415173788Sjfv struct e1000_hw_stats *stats, u32 frame_len, 416173788Sjfv u8 *mac_addr, u32 max_frame_size) 417169240Sjfv{ 418173788Sjfv if (!(e1000_tbi_sbp_enabled_82543(hw))) 419169240Sjfv goto out; 420169240Sjfv 421169240Sjfv /* First adjust the frame length. */ 422169240Sjfv frame_len--; 423173788Sjfv /* 424173788Sjfv * We need to adjust the statistics counters, since the hardware 425169240Sjfv * counters overcount this packet as a CRC error and undercount 426169240Sjfv * the packet as a good packet 427169240Sjfv */ 428169240Sjfv /* This packet should not be counted as a CRC error. */ 429169240Sjfv stats->crcerrs--; 430169240Sjfv /* This packet does count as a Good Packet Received. */ 431169240Sjfv stats->gprc++; 432169240Sjfv 433169240Sjfv /* Adjust the Good Octets received counters */ 434173788Sjfv stats->gorc += frame_len; 435173788Sjfv 436173788Sjfv /* 437173788Sjfv * Is this a broadcast or multicast? Check broadcast first, 438169240Sjfv * since the test for a multicast frame will test positive on 439169240Sjfv * a broadcast frame. 440169240Sjfv */ 441169240Sjfv if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 442169240Sjfv /* Broadcast packet */ 443169240Sjfv stats->bprc++; 444169240Sjfv else if (*mac_addr & 0x01) 445169240Sjfv /* Multicast packet */ 446169240Sjfv stats->mprc++; 447169240Sjfv 448173788Sjfv /* 449173788Sjfv * In this case, the hardware has overcounted the number of 450169240Sjfv * oversize frames. 451169240Sjfv */ 452173788Sjfv if ((frame_len == max_frame_size) && (stats->roc > 0)) 453169240Sjfv stats->roc--; 454169240Sjfv 455173788Sjfv /* 456173788Sjfv * Adjust the bin counters when the extra byte put the frame in the 457169240Sjfv * wrong bin. Remember that the frame_len was adjusted above. 458169240Sjfv */ 459169240Sjfv if (frame_len == 64) { 460169240Sjfv stats->prc64++; 461169240Sjfv stats->prc127--; 462169240Sjfv } else if (frame_len == 127) { 463169240Sjfv stats->prc127++; 464169240Sjfv stats->prc255--; 465169240Sjfv } else if (frame_len == 255) { 466169240Sjfv stats->prc255++; 467169240Sjfv stats->prc511--; 468169240Sjfv } else if (frame_len == 511) { 469169240Sjfv stats->prc511++; 470169240Sjfv stats->prc1023--; 471169240Sjfv } else if (frame_len == 1023) { 472169240Sjfv stats->prc1023++; 473169240Sjfv stats->prc1522--; 474169240Sjfv } else if (frame_len == 1522) { 475169240Sjfv stats->prc1522++; 476169240Sjfv } 477169240Sjfv 478169240Sjfvout: 479169240Sjfv return; 480169240Sjfv} 481169240Sjfv 482169240Sjfv/** 483169240Sjfv * e1000_read_phy_reg_82543 - Read PHY register 484169589Sjfv * @hw: pointer to the HW structure 485169589Sjfv * @offset: register offset to be read 486169589Sjfv * @data: pointer to the read data 487169240Sjfv * 488169240Sjfv * Reads the PHY at offset and stores the information read to data. 489169240Sjfv **/ 490177867Sjfvstatic s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 491169240Sjfv{ 492169240Sjfv u32 mdic; 493169240Sjfv s32 ret_val = E1000_SUCCESS; 494169240Sjfv 495169240Sjfv DEBUGFUNC("e1000_read_phy_reg_82543"); 496169240Sjfv 497169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 498169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 499169240Sjfv ret_val = -E1000_ERR_PARAM; 500169240Sjfv goto out; 501169240Sjfv } 502169240Sjfv 503173788Sjfv /* 504173788Sjfv * We must first send a preamble through the MDIO pin to signal the 505169240Sjfv * beginning of an MII instruction. This is done by sending 32 506169240Sjfv * consecutive "1" bits. 507169240Sjfv */ 508169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 509169240Sjfv 510173788Sjfv /* 511173788Sjfv * Now combine the next few fields that are required for a read 512169240Sjfv * operation. We use this method instead of calling the 513169240Sjfv * e1000_shift_out_mdi_bits routine five different times. The format 514169240Sjfv * of an MII read instruction consists of a shift out of 14 bits and 515169240Sjfv * is defined as follows: 516169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Offset> 517169240Sjfv * followed by a shift in of 18 bits. This first two bits shifted in 518169240Sjfv * are TurnAround bits used to avoid contention on the MDIO pin when a 519169240Sjfv * READ operation is performed. These two bits are thrown away 520169240Sjfv * followed by a shift in of 16 bits which contains the desired data. 521169240Sjfv */ 522169240Sjfv mdic = (offset | (hw->phy.addr << 5) | 523169240Sjfv (PHY_OP_READ << 10) | (PHY_SOF << 12)); 524169240Sjfv 525169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 526169240Sjfv 527173788Sjfv /* 528173788Sjfv * Now that we've shifted out the read command to the MII, we need to 529169240Sjfv * "shift in" the 16-bit value (18 total bits) of the requested PHY 530169240Sjfv * register address. 531169240Sjfv */ 532169240Sjfv *data = e1000_shift_in_mdi_bits_82543(hw); 533169240Sjfv 534169240Sjfvout: 535169240Sjfv return ret_val; 536169240Sjfv} 537169240Sjfv 538169240Sjfv/** 539169240Sjfv * e1000_write_phy_reg_82543 - Write PHY register 540169589Sjfv * @hw: pointer to the HW structure 541169589Sjfv * @offset: register offset to be written 542169589Sjfv * @data: pointer to the data to be written at offset 543169240Sjfv * 544169240Sjfv * Writes data to the PHY at offset. 545169240Sjfv **/ 546177867Sjfvstatic s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 547169240Sjfv{ 548169240Sjfv u32 mdic; 549169240Sjfv s32 ret_val = E1000_SUCCESS; 550169240Sjfv 551169240Sjfv DEBUGFUNC("e1000_write_phy_reg_82543"); 552169240Sjfv 553169240Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 554169240Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 555169240Sjfv ret_val = -E1000_ERR_PARAM; 556169240Sjfv goto out; 557169240Sjfv } 558169240Sjfv 559173788Sjfv /* 560173788Sjfv * We'll need to use the SW defined pins to shift the write command 561169240Sjfv * out to the PHY. We first send a preamble to the PHY to signal the 562169240Sjfv * beginning of the MII instruction. This is done by sending 32 563169240Sjfv * consecutive "1" bits. 564169240Sjfv */ 565169240Sjfv e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 566169240Sjfv 567173788Sjfv /* 568173788Sjfv * Now combine the remaining required fields that will indicate a 569169240Sjfv * write operation. We use this method instead of calling the 570169240Sjfv * e1000_shift_out_mdi_bits routine for each field in the command. The 571169240Sjfv * format of a MII write instruction is as follows: 572169240Sjfv * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 573169240Sjfv */ 574169240Sjfv mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 575169240Sjfv (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 576169240Sjfv mdic <<= 16; 577169240Sjfv mdic |= (u32) data; 578169240Sjfv 579169240Sjfv e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 580169240Sjfv 581169240Sjfvout: 582169240Sjfv return ret_val; 583169240Sjfv} 584169240Sjfv 585169240Sjfv/** 586169240Sjfv * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 587169589Sjfv * @hw: pointer to the HW structure 588169589Sjfv * @ctrl: pointer to the control register 589169240Sjfv * 590169240Sjfv * Raise the management data input clock by setting the MDC bit in the control 591169240Sjfv * register. 592169240Sjfv **/ 593173788Sjfvstatic void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 594169240Sjfv{ 595173788Sjfv /* 596173788Sjfv * Raise the clock input to the Management Data Clock (by setting the 597169240Sjfv * MDC bit), and then delay a sufficient amount of time. 598169240Sjfv */ 599169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 600169240Sjfv E1000_WRITE_FLUSH(hw); 601169240Sjfv usec_delay(10); 602169240Sjfv} 603169240Sjfv 604169240Sjfv/** 605169240Sjfv * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 606169589Sjfv * @hw: pointer to the HW structure 607169589Sjfv * @ctrl: pointer to the control register 608169240Sjfv * 609176667Sjfv * Lower the management data input clock by clearing the MDC bit in the 610176667Sjfv * control register. 611169240Sjfv **/ 612173788Sjfvstatic void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 613169240Sjfv{ 614173788Sjfv /* 615173788Sjfv * Lower the clock input to the Management Data Clock (by clearing the 616169240Sjfv * MDC bit), and then delay a sufficient amount of time. 617169240Sjfv */ 618169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 619169240Sjfv E1000_WRITE_FLUSH(hw); 620169240Sjfv usec_delay(10); 621169240Sjfv} 622169240Sjfv 623169240Sjfv/** 624169240Sjfv * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 625169589Sjfv * @hw: pointer to the HW structure 626169589Sjfv * @data: data to send to the PHY 627169589Sjfv * @count: number of bits to shift out 628169240Sjfv * 629169240Sjfv * We need to shift 'count' bits out to the PHY. So, the value in the 630169240Sjfv * "data" parameter will be shifted out to the PHY one bit at a time. 631169240Sjfv * In order to do this, "data" must be broken down into bits. 632169240Sjfv **/ 633173788Sjfvstatic void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 634173788Sjfv u16 count) 635169240Sjfv{ 636169240Sjfv u32 ctrl, mask; 637169240Sjfv 638173788Sjfv /* 639173788Sjfv * We need to shift "count" number of bits out to the PHY. So, the 640169240Sjfv * value in the "data" parameter will be shifted out to the PHY one 641169240Sjfv * bit at a time. In order to do this, "data" must be broken down 642169240Sjfv * into bits. 643169240Sjfv */ 644169240Sjfv mask = 0x01; 645169240Sjfv mask <<= (count -1); 646169240Sjfv 647169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 648169240Sjfv 649169240Sjfv /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 650169240Sjfv ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 651169240Sjfv 652169240Sjfv while (mask) { 653173788Sjfv /* 654173788Sjfv * A "1" is shifted out to the PHY by setting the MDIO bit to 655169240Sjfv * "1" and then raising and lowering the Management Data Clock. 656169240Sjfv * A "0" is shifted out to the PHY by setting the MDIO bit to 657169240Sjfv * "0" and then raising and lowering the clock. 658169240Sjfv */ 659169240Sjfv if (data & mask) ctrl |= E1000_CTRL_MDIO; 660169240Sjfv else ctrl &= ~E1000_CTRL_MDIO; 661169240Sjfv 662169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 663169240Sjfv E1000_WRITE_FLUSH(hw); 664169240Sjfv 665169240Sjfv usec_delay(10); 666169240Sjfv 667169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 668169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 669169240Sjfv 670169240Sjfv mask >>= 1; 671169240Sjfv } 672169240Sjfv} 673169240Sjfv 674169240Sjfv/** 675169240Sjfv * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 676169589Sjfv * @hw: pointer to the HW structure 677169240Sjfv * 678169240Sjfv * In order to read a register from the PHY, we need to shift 18 bits 679169240Sjfv * in from the PHY. Bits are "shifted in" by raising the clock input to 680169240Sjfv * the PHY (setting the MDC bit), and then reading the value of the data out 681169240Sjfv * MDIO bit. 682169240Sjfv **/ 683173788Sjfvstatic u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 684169240Sjfv{ 685169240Sjfv u32 ctrl; 686169240Sjfv u16 data = 0; 687169240Sjfv u8 i; 688169240Sjfv 689173788Sjfv /* 690173788Sjfv * In order to read a register from the PHY, we need to shift in a 691169240Sjfv * total of 18 bits from the PHY. The first two bit (turnaround) 692169240Sjfv * times are used to avoid contention on the MDIO pin when a read 693169240Sjfv * operation is performed. These two bits are ignored by us and 694169240Sjfv * thrown away. Bits are "shifted in" by raising the input to the 695169240Sjfv * Management Data Clock (setting the MDC bit) and then reading the 696169240Sjfv * value of the MDIO bit. 697169240Sjfv */ 698169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 699169240Sjfv 700173788Sjfv /* 701173788Sjfv * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 702169240Sjfv * input. 703169240Sjfv */ 704169240Sjfv ctrl &= ~E1000_CTRL_MDIO_DIR; 705169240Sjfv ctrl &= ~E1000_CTRL_MDIO; 706169240Sjfv 707169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 708169240Sjfv E1000_WRITE_FLUSH(hw); 709169240Sjfv 710173788Sjfv /* 711173788Sjfv * Raise and lower the clock before reading in the data. This accounts 712169240Sjfv * for the turnaround bits. The first clock occurred when we clocked 713169240Sjfv * out the last bit of the Register Address. 714169240Sjfv */ 715169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 716169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 717169240Sjfv 718169240Sjfv for (data = 0, i = 0; i < 16; i++) { 719169240Sjfv data <<= 1; 720169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 721169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 722169240Sjfv /* Check to see if we shifted in a "1". */ 723169240Sjfv if (ctrl & E1000_CTRL_MDIO) 724169240Sjfv data |= 1; 725169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 726169240Sjfv } 727169240Sjfv 728169240Sjfv e1000_raise_mdi_clk_82543(hw, &ctrl); 729169240Sjfv e1000_lower_mdi_clk_82543(hw, &ctrl); 730169240Sjfv 731169240Sjfv return data; 732169240Sjfv} 733169240Sjfv 734169240Sjfv/** 735169240Sjfv * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 736169589Sjfv * @hw: pointer to the HW structure 737169240Sjfv * 738169240Sjfv * Calls the function to force speed and duplex for the m88 PHY, and 739169240Sjfv * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 740169240Sjfv * then call the function for polarity reversal workaround. 741169240Sjfv **/ 742177867Sjfvstatic s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 743169240Sjfv{ 744169240Sjfv s32 ret_val; 745169240Sjfv 746169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 747169240Sjfv 748169240Sjfv ret_val = e1000_phy_force_speed_duplex_m88(hw); 749169240Sjfv if (ret_val) 750169240Sjfv goto out; 751169240Sjfv 752169240Sjfv if (!hw->mac.autoneg && 753169240Sjfv (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 754169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 755169240Sjfv 756169240Sjfvout: 757169240Sjfv return ret_val; 758169240Sjfv} 759169240Sjfv 760169240Sjfv/** 761169240Sjfv * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 762169589Sjfv * @hw: pointer to the HW structure 763169240Sjfv * 764169240Sjfv * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 765176667Sjfv * inadvertently. To workaround the issue, we disable the transmitter on 766169240Sjfv * the PHY until we have established the link partner's link parameters. 767169240Sjfv **/ 768173788Sjfvstatic s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 769169240Sjfv{ 770177867Sjfv s32 ret_val = E1000_SUCCESS; 771169240Sjfv u16 mii_status_reg; 772169240Sjfv u16 i; 773173788Sjfv bool link; 774169240Sjfv 775177867Sjfv if (!(hw->phy.ops.write_reg)) 776177867Sjfv goto out; 777177867Sjfv 778169240Sjfv /* Polarity reversal workaround for forced 10F/10H links. */ 779169240Sjfv 780169240Sjfv /* Disable the transmitter on the PHY */ 781169240Sjfv 782177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 783169240Sjfv if (ret_val) 784169240Sjfv goto out; 785177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 786169240Sjfv if (ret_val) 787169240Sjfv goto out; 788169240Sjfv 789177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 790169240Sjfv if (ret_val) 791169240Sjfv goto out; 792169240Sjfv 793173788Sjfv /* 794173788Sjfv * This loop will early-out if the NO link condition has been met. 795169240Sjfv * In other words, DO NOT use e1000_phy_has_link_generic() here. 796169240Sjfv */ 797169240Sjfv for (i = PHY_FORCE_TIME; i > 0; i--) { 798173788Sjfv /* 799173788Sjfv * Read the MII Status Register and wait for Link Status bit 800169240Sjfv * to be clear. 801169240Sjfv */ 802169240Sjfv 803177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 804169240Sjfv if (ret_val) 805169240Sjfv goto out; 806169240Sjfv 807177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 808169240Sjfv if (ret_val) 809169240Sjfv goto out; 810169240Sjfv 811169240Sjfv if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 812169240Sjfv break; 813169240Sjfv msec_delay_irq(100); 814169240Sjfv } 815169240Sjfv 816169240Sjfv /* Recommended delay time after link has been lost */ 817169240Sjfv msec_delay_irq(1000); 818169240Sjfv 819169240Sjfv /* Now we will re-enable the transmitter on the PHY */ 820169240Sjfv 821177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 822169240Sjfv if (ret_val) 823169240Sjfv goto out; 824169240Sjfv msec_delay_irq(50); 825177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 826169240Sjfv if (ret_val) 827169240Sjfv goto out; 828169240Sjfv msec_delay_irq(50); 829177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 830169240Sjfv if (ret_val) 831169240Sjfv goto out; 832169240Sjfv msec_delay_irq(50); 833177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 834169240Sjfv if (ret_val) 835169240Sjfv goto out; 836169240Sjfv 837177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 838169240Sjfv if (ret_val) 839169240Sjfv goto out; 840169240Sjfv 841173788Sjfv /* 842173788Sjfv * Read the MII Status Register and wait for Link Status bit 843169240Sjfv * to be set. 844169240Sjfv */ 845169240Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 846169240Sjfv if (ret_val) 847169240Sjfv goto out; 848169240Sjfv 849169240Sjfvout: 850169240Sjfv return ret_val; 851169240Sjfv} 852169240Sjfv 853169240Sjfv/** 854169240Sjfv * e1000_phy_hw_reset_82543 - PHY hardware reset 855169589Sjfv * @hw: pointer to the HW structure 856169240Sjfv * 857169240Sjfv * Sets the PHY_RESET_DIR bit in the extended device control register 858169240Sjfv * to put the PHY into a reset and waits for completion. Once the reset 859169240Sjfv * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 860185353Sjfv * of reset. 861169240Sjfv **/ 862177867Sjfvstatic s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 863169240Sjfv{ 864169240Sjfv u32 ctrl_ext; 865169240Sjfv s32 ret_val; 866169240Sjfv 867169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_82543"); 868169240Sjfv 869173788Sjfv /* 870173788Sjfv * Read the Extended Device Control Register, assert the PHY_RESET_DIR 871169240Sjfv * bit to put the PHY into reset... 872169240Sjfv */ 873169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 874169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 875169240Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 876169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 877169240Sjfv E1000_WRITE_FLUSH(hw); 878169240Sjfv 879169240Sjfv msec_delay(10); 880169240Sjfv 881169240Sjfv /* ...then take it out of reset. */ 882169240Sjfv ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 883169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 884169240Sjfv E1000_WRITE_FLUSH(hw); 885169240Sjfv 886169240Sjfv usec_delay(150); 887169240Sjfv 888177867Sjfv if (!(hw->phy.ops.get_cfg_done)) 889177867Sjfv return E1000_SUCCESS; 890169240Sjfv 891177867Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 892177867Sjfv 893169240Sjfv return ret_val; 894169240Sjfv} 895169240Sjfv 896169240Sjfv/** 897169240Sjfv * e1000_reset_hw_82543 - Reset hardware 898169589Sjfv * @hw: pointer to the HW structure 899169240Sjfv * 900185353Sjfv * This resets the hardware into a known state. 901169240Sjfv **/ 902177867Sjfvstatic s32 e1000_reset_hw_82543(struct e1000_hw *hw) 903169240Sjfv{ 904235527Sjfv u32 ctrl, icr; 905169240Sjfv s32 ret_val = E1000_SUCCESS; 906169240Sjfv 907169240Sjfv DEBUGFUNC("e1000_reset_hw_82543"); 908169240Sjfv 909169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 910169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 911169240Sjfv 912169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 913169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 914169240Sjfv E1000_WRITE_FLUSH(hw); 915169240Sjfv 916169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 917169240Sjfv 918173788Sjfv /* 919173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 920169240Sjfv * resetting the device 921169240Sjfv */ 922169240Sjfv msec_delay(10); 923169240Sjfv 924169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 925169240Sjfv 926169240Sjfv DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 927169240Sjfv if (hw->mac.type == e1000_82543) { 928169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 929169240Sjfv } else { 930173788Sjfv /* 931173788Sjfv * The 82544 can't ACK the 64-bit write when issuing the 932169240Sjfv * reset, so use IO-mapping as a workaround. 933169240Sjfv */ 934169240Sjfv E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 935169240Sjfv } 936169240Sjfv 937173788Sjfv /* 938173788Sjfv * After MAC reset, force reload of NVM to restore power-on 939169240Sjfv * settings to device. 940169240Sjfv */ 941177867Sjfv hw->nvm.ops.reload(hw); 942169240Sjfv msec_delay(2); 943169240Sjfv 944169240Sjfv /* Masking off and clearing any pending interrupts */ 945169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 946235527Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 947169240Sjfv 948169240Sjfv return ret_val; 949169240Sjfv} 950169240Sjfv 951169240Sjfv/** 952169240Sjfv * e1000_init_hw_82543 - Initialize hardware 953169589Sjfv * @hw: pointer to the HW structure 954169240Sjfv * 955169240Sjfv * This inits the hardware readying it for operation. 956169240Sjfv **/ 957177867Sjfvstatic s32 e1000_init_hw_82543(struct e1000_hw *hw) 958169240Sjfv{ 959169240Sjfv struct e1000_mac_info *mac = &hw->mac; 960185353Sjfv struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 961169240Sjfv u32 ctrl; 962169240Sjfv s32 ret_val; 963169240Sjfv u16 i; 964169240Sjfv 965169240Sjfv DEBUGFUNC("e1000_init_hw_82543"); 966169240Sjfv 967169240Sjfv /* Disabling VLAN filtering */ 968169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 969177867Sjfv mac->ops.clear_vfta(hw); 970169240Sjfv 971169240Sjfv /* Setup the receive address. */ 972169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 973169240Sjfv 974169240Sjfv /* Zero out the Multicast HASH table */ 975169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 976169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) { 977169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 978169240Sjfv E1000_WRITE_FLUSH(hw); 979169240Sjfv } 980169240Sjfv 981173788Sjfv /* 982173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 983169240Sjfv * determines if the adapter gives priority to receives, or if it 984169240Sjfv * gives equal priority to transmits and receives. 985169240Sjfv */ 986169240Sjfv if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 987169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 988169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 989169240Sjfv } 990169240Sjfv 991169240Sjfv e1000_pcix_mmrbc_workaround_generic(hw); 992169240Sjfv 993169240Sjfv /* Setup link and flow control */ 994177867Sjfv ret_val = mac->ops.setup_link(hw); 995169240Sjfv 996173788Sjfv /* 997173788Sjfv * Clear all of the statistics registers (clear on read). It is 998169240Sjfv * important that we do this after we have tried to establish link 999169240Sjfv * because the symbol error count will increment wildly if there 1000169240Sjfv * is no link. 1001169240Sjfv */ 1002169240Sjfv e1000_clear_hw_cntrs_82543(hw); 1003169240Sjfv 1004169240Sjfv return ret_val; 1005169240Sjfv} 1006169240Sjfv 1007169240Sjfv/** 1008169240Sjfv * e1000_setup_link_82543 - Setup flow control and link settings 1009169589Sjfv * @hw: pointer to the HW structure 1010169240Sjfv * 1011169240Sjfv * Read the EEPROM to determine the initial polarity value and write the 1012169240Sjfv * extended device control register with the information before calling 1013169240Sjfv * the generic setup link function, which does the following: 1014169240Sjfv * Determines which flow control settings to use, then configures flow 1015169240Sjfv * control. Calls the appropriate media-specific link configuration 1016169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1017169240Sjfv * should be established. Assumes the hardware has previously been reset 1018169240Sjfv * and the transmitter and receiver are not enabled. 1019169240Sjfv **/ 1020177867Sjfvstatic s32 e1000_setup_link_82543(struct e1000_hw *hw) 1021169240Sjfv{ 1022169240Sjfv u32 ctrl_ext; 1023169240Sjfv s32 ret_val; 1024169240Sjfv u16 data; 1025169240Sjfv 1026169240Sjfv DEBUGFUNC("e1000_setup_link_82543"); 1027169240Sjfv 1028173788Sjfv /* 1029173788Sjfv * Take the 4 bits from NVM word 0xF that determine the initial 1030169240Sjfv * polarity value for the SW controlled pins, and setup the 1031169240Sjfv * Extended Device Control reg with that info. 1032169240Sjfv * This is needed because one of the SW controlled pins is used for 1033169240Sjfv * signal detection. So this should be done before phy setup. 1034169240Sjfv */ 1035169240Sjfv if (hw->mac.type == e1000_82543) { 1036177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1037169240Sjfv if (ret_val) { 1038169240Sjfv DEBUGOUT("NVM Read Error\n"); 1039169240Sjfv ret_val = -E1000_ERR_NVM; 1040169240Sjfv goto out; 1041169240Sjfv } 1042169240Sjfv ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1043169240Sjfv NVM_SWDPIO_EXT_SHIFT); 1044169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1045169240Sjfv } 1046169240Sjfv 1047169240Sjfv ret_val = e1000_setup_link_generic(hw); 1048169240Sjfv 1049169240Sjfvout: 1050169240Sjfv return ret_val; 1051169240Sjfv} 1052169240Sjfv 1053169240Sjfv/** 1054169240Sjfv * e1000_setup_copper_link_82543 - Configure copper link settings 1055169589Sjfv * @hw: pointer to the HW structure 1056169240Sjfv * 1057169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1058169240Sjfv * for link, once link is established calls to configure collision distance 1059169240Sjfv * and flow control are called. 1060169240Sjfv **/ 1061177867Sjfvstatic s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1062169240Sjfv{ 1063169240Sjfv u32 ctrl; 1064169240Sjfv s32 ret_val; 1065173788Sjfv bool link; 1066169240Sjfv 1067169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82543"); 1068169240Sjfv 1069169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1070173788Sjfv /* 1071173788Sjfv * With 82543, we need to force speed and duplex on the MAC 1072169240Sjfv * equal to what the PHY speed and duplex configuration is. 1073169240Sjfv * In addition, we need to perform a hardware reset on the 1074169240Sjfv * PHY to take it out of reset. 1075169240Sjfv */ 1076169240Sjfv if (hw->mac.type == e1000_82543) { 1077169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1078169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1079177867Sjfv ret_val = hw->phy.ops.reset(hw); 1080169240Sjfv if (ret_val) 1081169240Sjfv goto out; 1082169240Sjfv } else { 1083169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1084169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1085169240Sjfv } 1086169240Sjfv 1087169240Sjfv /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1088169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1089169240Sjfv if (ret_val) 1090169240Sjfv goto out; 1091169240Sjfv 1092169240Sjfv if (hw->mac.autoneg) { 1093173788Sjfv /* 1094173788Sjfv * Setup autoneg and flow control advertisement and perform 1095173788Sjfv * autonegotiation. 1096173788Sjfv */ 1097169240Sjfv ret_val = e1000_copper_link_autoneg(hw); 1098169240Sjfv if (ret_val) 1099169240Sjfv goto out; 1100169240Sjfv } else { 1101173788Sjfv /* 1102173788Sjfv * PHY will be set to 10H, 10F, 100H or 100F 1103173788Sjfv * depending on user settings. 1104173788Sjfv */ 1105169240Sjfv DEBUGOUT("Forcing Speed and Duplex\n"); 1106169240Sjfv ret_val = e1000_phy_force_speed_duplex_82543(hw); 1107169240Sjfv if (ret_val) { 1108169240Sjfv DEBUGOUT("Error Forcing Speed and Duplex\n"); 1109169240Sjfv goto out; 1110169240Sjfv } 1111169240Sjfv } 1112169240Sjfv 1113173788Sjfv /* 1114173788Sjfv * Check link status. Wait up to 100 microseconds for link to become 1115169240Sjfv * valid. 1116169240Sjfv */ 1117169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1118169240Sjfv COPPER_LINK_UP_LIMIT, 1119169240Sjfv 10, 1120169240Sjfv &link); 1121169240Sjfv if (ret_val) 1122169240Sjfv goto out; 1123169240Sjfv 1124169240Sjfv 1125169240Sjfv if (link) { 1126169240Sjfv DEBUGOUT("Valid link established!!!\n"); 1127169240Sjfv /* Config the MAC and PHY after link is up */ 1128173788Sjfv if (hw->mac.type == e1000_82544) { 1129238262Sjfv hw->mac.ops.config_collision_dist(hw); 1130173788Sjfv } else { 1131169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1132169240Sjfv if (ret_val) 1133169240Sjfv goto out; 1134169240Sjfv } 1135169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1136169240Sjfv } else { 1137169240Sjfv DEBUGOUT("Unable to establish link!!!\n"); 1138169240Sjfv } 1139169240Sjfv 1140169240Sjfvout: 1141169240Sjfv return ret_val; 1142169240Sjfv} 1143169240Sjfv 1144169240Sjfv/** 1145169240Sjfv * e1000_setup_fiber_link_82543 - Setup link for fiber 1146169589Sjfv * @hw: pointer to the HW structure 1147169240Sjfv * 1148169240Sjfv * Configures collision distance and flow control for fiber links. Upon 1149169240Sjfv * successful setup, poll for link. 1150169240Sjfv **/ 1151177867Sjfvstatic s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1152169240Sjfv{ 1153169240Sjfv u32 ctrl; 1154169240Sjfv s32 ret_val; 1155169240Sjfv 1156169240Sjfv DEBUGFUNC("e1000_setup_fiber_link_82543"); 1157169240Sjfv 1158169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1159169240Sjfv 1160169240Sjfv /* Take the link out of reset */ 1161169240Sjfv ctrl &= ~E1000_CTRL_LRST; 1162169240Sjfv 1163238262Sjfv hw->mac.ops.config_collision_dist(hw); 1164169240Sjfv 1165169240Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1166169240Sjfv if (ret_val) 1167169240Sjfv goto out; 1168169240Sjfv 1169169240Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1170169240Sjfv 1171169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1172169240Sjfv E1000_WRITE_FLUSH(hw); 1173169240Sjfv msec_delay(1); 1174169240Sjfv 1175173788Sjfv /* 1176176667Sjfv * For these adapters, the SW definable pin 1 is cleared when the 1177169240Sjfv * optics detect a signal. If we have a signal, then poll for a 1178169240Sjfv * "Link-Up" indication. 1179169240Sjfv */ 1180169240Sjfv if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1181169240Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1182169240Sjfv } else { 1183169240Sjfv DEBUGOUT("No signal detected\n"); 1184169240Sjfv } 1185169240Sjfv 1186169240Sjfvout: 1187169240Sjfv return ret_val; 1188169240Sjfv} 1189169240Sjfv 1190169240Sjfv/** 1191169240Sjfv * e1000_check_for_copper_link_82543 - Check for link (Copper) 1192169589Sjfv * @hw: pointer to the HW structure 1193169240Sjfv * 1194169240Sjfv * Checks the phy for link, if link exists, do the following: 1195169240Sjfv * - check for downshift 1196169240Sjfv * - do polarity workaround (if necessary) 1197169240Sjfv * - configure collision distance 1198169240Sjfv * - configure flow control after link up 1199169240Sjfv * - configure tbi compatibility 1200169240Sjfv **/ 1201177867Sjfvstatic s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1202169240Sjfv{ 1203169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1204169240Sjfv u32 icr, rctl; 1205169240Sjfv s32 ret_val; 1206169240Sjfv u16 speed, duplex; 1207173788Sjfv bool link; 1208169240Sjfv 1209169240Sjfv DEBUGFUNC("e1000_check_for_copper_link_82543"); 1210169240Sjfv 1211169240Sjfv if (!mac->get_link_status) { 1212169240Sjfv ret_val = E1000_SUCCESS; 1213169240Sjfv goto out; 1214169240Sjfv } 1215169240Sjfv 1216169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1217169240Sjfv if (ret_val) 1218169240Sjfv goto out; 1219169240Sjfv 1220169240Sjfv if (!link) 1221169240Sjfv goto out; /* No link detected */ 1222169240Sjfv 1223169240Sjfv mac->get_link_status = FALSE; 1224169240Sjfv 1225169240Sjfv e1000_check_downshift_generic(hw); 1226169240Sjfv 1227173788Sjfv /* 1228173788Sjfv * If we are forcing speed/duplex, then we can return since 1229169240Sjfv * we have already determined whether we have link or not. 1230169240Sjfv */ 1231169240Sjfv if (!mac->autoneg) { 1232173788Sjfv /* 1233173788Sjfv * If speed and duplex are forced to 10H or 10F, then we will 1234169240Sjfv * implement the polarity reversal workaround. We disable 1235169240Sjfv * interrupts first, and upon returning, place the devices 1236169240Sjfv * interrupt state to its previous value except for the link 1237169240Sjfv * status change interrupt which will happened due to the 1238169240Sjfv * execution of this workaround. 1239169240Sjfv */ 1240169240Sjfv if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1241169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1242169240Sjfv ret_val = e1000_polarity_reversal_workaround_82543(hw); 1243169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1244169240Sjfv E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1245169240Sjfv E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1246169240Sjfv } 1247169240Sjfv 1248169240Sjfv ret_val = -E1000_ERR_CONFIG; 1249169240Sjfv goto out; 1250169240Sjfv } 1251169240Sjfv 1252173788Sjfv /* 1253173788Sjfv * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1254169240Sjfv * have Si on board that is 82544 or newer, Auto 1255169240Sjfv * Speed Detection takes care of MAC speed/duplex 1256169240Sjfv * configuration. So we only need to configure Collision 1257169240Sjfv * Distance in the MAC. Otherwise, we need to force 1258169240Sjfv * speed/duplex on the MAC to the current PHY speed/duplex 1259169240Sjfv * settings. 1260169240Sjfv */ 1261169240Sjfv if (mac->type == e1000_82544) 1262238262Sjfv hw->mac.ops.config_collision_dist(hw); 1263169240Sjfv else { 1264169240Sjfv ret_val = e1000_config_mac_to_phy_82543(hw); 1265169240Sjfv if (ret_val) { 1266169240Sjfv DEBUGOUT("Error configuring MAC to PHY settings\n"); 1267169240Sjfv goto out; 1268169240Sjfv } 1269169240Sjfv } 1270169240Sjfv 1271173788Sjfv /* 1272173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 1273169240Sjfv * First, we need to restore the desired flow control 1274169240Sjfv * settings because we may have had to re-autoneg with a 1275169240Sjfv * different link partner. 1276169240Sjfv */ 1277169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1278169240Sjfv if (ret_val) { 1279169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1280169240Sjfv } 1281169240Sjfv 1282173788Sjfv /* 1283173788Sjfv * At this point we know that we are on copper and we have 1284169240Sjfv * auto-negotiated link. These are conditions for checking the link 1285169240Sjfv * partner capability register. We use the link speed to determine if 1286169240Sjfv * TBI compatibility needs to be turned on or off. If the link is not 1287169240Sjfv * at gigabit speed, then TBI compatibility is not needed. If we are 1288169240Sjfv * at gigabit speed, we turn on TBI compatibility. 1289169240Sjfv */ 1290169240Sjfv if (e1000_tbi_compatibility_enabled_82543(hw)) { 1291177867Sjfv ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1292169240Sjfv if (ret_val) { 1293169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1294169240Sjfv return ret_val; 1295169240Sjfv } 1296169240Sjfv if (speed != SPEED_1000) { 1297173788Sjfv /* 1298173788Sjfv * If link speed is not set to gigabit speed, 1299169240Sjfv * we do not need to enable TBI compatibility. 1300169240Sjfv */ 1301169240Sjfv if (e1000_tbi_sbp_enabled_82543(hw)) { 1302173788Sjfv /* 1303173788Sjfv * If we previously were in the mode, 1304169240Sjfv * turn it off. 1305169240Sjfv */ 1306169240Sjfv e1000_set_tbi_sbp_82543(hw, FALSE); 1307169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1308169240Sjfv rctl &= ~E1000_RCTL_SBP; 1309169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1310169240Sjfv } 1311169240Sjfv } else { 1312173788Sjfv /* 1313173788Sjfv * If TBI compatibility is was previously off, 1314169240Sjfv * turn it on. For compatibility with a TBI link 1315169240Sjfv * partner, we will store bad packets. Some 1316169240Sjfv * frames have an additional byte on the end and 1317169240Sjfv * will look like CRC errors to to the hardware. 1318169240Sjfv */ 1319169240Sjfv if (!e1000_tbi_sbp_enabled_82543(hw)) { 1320169240Sjfv e1000_set_tbi_sbp_82543(hw, TRUE); 1321169240Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1322169240Sjfv rctl |= E1000_RCTL_SBP; 1323169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1324169240Sjfv } 1325169240Sjfv } 1326169240Sjfv } 1327169240Sjfvout: 1328169240Sjfv return ret_val; 1329169240Sjfv} 1330169240Sjfv 1331169240Sjfv/** 1332169240Sjfv * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1333169589Sjfv * @hw: pointer to the HW structure 1334169240Sjfv * 1335169240Sjfv * Checks for link up on the hardware. If link is not up and we have 1336169240Sjfv * a signal, then we need to force link up. 1337169240Sjfv **/ 1338177867Sjfvstatic s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1339169240Sjfv{ 1340169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1341169240Sjfv u32 rxcw, ctrl, status; 1342169240Sjfv s32 ret_val = E1000_SUCCESS; 1343169240Sjfv 1344169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1345169240Sjfv 1346169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1347173788Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1348173788Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1349169240Sjfv 1350173788Sjfv /* 1351173788Sjfv * If we don't have link (auto-negotiation failed or link partner 1352169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 1353169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 1354169240Sjfv * are receiving idles or data), we need to force link up. We also 1355169240Sjfv * need to give auto-negotiation time to complete, in case the cable 1356169240Sjfv * was just plugged in. The autoneg_failed flag does this. 1357169240Sjfv */ 1358169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1359169240Sjfv if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1360169240Sjfv (!(status & E1000_STATUS_LU)) && 1361169240Sjfv (!(rxcw & E1000_RXCW_C))) { 1362169240Sjfv if (mac->autoneg_failed == 0) { 1363169240Sjfv mac->autoneg_failed = 1; 1364169240Sjfv ret_val = 0; 1365169240Sjfv goto out; 1366169240Sjfv } 1367169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1368169240Sjfv 1369169240Sjfv /* Disable auto-negotiation in the TXCW register */ 1370169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1371169240Sjfv 1372169240Sjfv /* Force link-up and also force full-duplex. */ 1373169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1374169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1375169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1376169240Sjfv 1377169240Sjfv /* Configure Flow Control after forcing link up. */ 1378169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1379169240Sjfv if (ret_val) { 1380169240Sjfv DEBUGOUT("Error configuring flow control\n"); 1381169240Sjfv goto out; 1382169240Sjfv } 1383169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1384173788Sjfv /* 1385173788Sjfv * If we are forcing link and we are receiving /C/ ordered 1386169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 1387169240Sjfv * and disable forced link in the Device Control register 1388169240Sjfv * in an attempt to auto-negotiate with our link partner. 1389169240Sjfv */ 1390169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1391169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1392169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1393169240Sjfv 1394169240Sjfv mac->serdes_has_link = TRUE; 1395169240Sjfv } 1396169240Sjfv 1397169240Sjfvout: 1398169240Sjfv return ret_val; 1399169240Sjfv} 1400169240Sjfv 1401169240Sjfv/** 1402169240Sjfv * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1403169589Sjfv * @hw: pointer to the HW structure 1404169240Sjfv * 1405169240Sjfv * For the 82543 silicon, we need to set the MAC to match the settings 1406169240Sjfv * of the PHY, even if the PHY is auto-negotiating. 1407169240Sjfv **/ 1408173788Sjfvstatic s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1409169240Sjfv{ 1410169240Sjfv u32 ctrl; 1411177867Sjfv s32 ret_val = E1000_SUCCESS; 1412169240Sjfv u16 phy_data; 1413169240Sjfv 1414169240Sjfv DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1415169240Sjfv 1416177867Sjfv if (!(hw->phy.ops.read_reg)) 1417177867Sjfv goto out; 1418177867Sjfv 1419169240Sjfv /* Set the bits to force speed and duplex */ 1420169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1421169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1422169240Sjfv ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1423169240Sjfv 1424173788Sjfv /* 1425173788Sjfv * Set up duplex in the Device Control and Transmit Control 1426169240Sjfv * registers depending on negotiated values. 1427169240Sjfv */ 1428177867Sjfv ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1429169240Sjfv if (ret_val) 1430169240Sjfv goto out; 1431169240Sjfv 1432169240Sjfv ctrl &= ~E1000_CTRL_FD; 1433169240Sjfv if (phy_data & M88E1000_PSSR_DPLX) 1434169240Sjfv ctrl |= E1000_CTRL_FD; 1435169240Sjfv 1436238262Sjfv hw->mac.ops.config_collision_dist(hw); 1437169240Sjfv 1438173788Sjfv /* 1439173788Sjfv * Set up speed in the Device Control register depending on 1440169240Sjfv * negotiated values. 1441169240Sjfv */ 1442169240Sjfv if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1443169240Sjfv ctrl |= E1000_CTRL_SPD_1000; 1444169240Sjfv else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1445169240Sjfv ctrl |= E1000_CTRL_SPD_100; 1446169240Sjfv 1447169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1448169240Sjfv 1449169240Sjfvout: 1450169240Sjfv return ret_val; 1451169240Sjfv} 1452169240Sjfv 1453169240Sjfv/** 1454169240Sjfv * e1000_write_vfta_82543 - Write value to VLAN filter table 1455169589Sjfv * @hw: pointer to the HW structure 1456169589Sjfv * @offset: the 32-bit offset in which to write the value to. 1457169589Sjfv * @value: the 32-bit value to write at location offset. 1458169240Sjfv * 1459169240Sjfv * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1460169240Sjfv * table. 1461169240Sjfv **/ 1462177867Sjfvstatic void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1463169240Sjfv{ 1464169240Sjfv u32 temp; 1465169240Sjfv 1466169240Sjfv DEBUGFUNC("e1000_write_vfta_82543"); 1467169240Sjfv 1468169240Sjfv if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1469169240Sjfv temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1470169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1471169240Sjfv E1000_WRITE_FLUSH(hw); 1472169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1473169240Sjfv E1000_WRITE_FLUSH(hw); 1474173788Sjfv } else { 1475169240Sjfv e1000_write_vfta_generic(hw, offset, value); 1476173788Sjfv } 1477169240Sjfv} 1478169240Sjfv 1479169240Sjfv/** 1480169240Sjfv * e1000_led_on_82543 - Turn on SW controllable LED 1481169589Sjfv * @hw: pointer to the HW structure 1482169240Sjfv * 1483185353Sjfv * Turns the SW defined LED on. 1484169240Sjfv **/ 1485177867Sjfvstatic s32 e1000_led_on_82543(struct e1000_hw *hw) 1486169240Sjfv{ 1487169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1488169240Sjfv 1489169240Sjfv DEBUGFUNC("e1000_led_on_82543"); 1490169240Sjfv 1491169240Sjfv if (hw->mac.type == e1000_82544 && 1492173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1493176667Sjfv /* Clear SW-definable Pin 0 to turn on the LED */ 1494169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1495169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1496169240Sjfv } else { 1497169240Sjfv /* Fiber 82544 and all 82543 use this method */ 1498169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1499169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1500169240Sjfv } 1501169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1502169240Sjfv 1503169240Sjfv return E1000_SUCCESS; 1504169240Sjfv} 1505169240Sjfv 1506169240Sjfv/** 1507169240Sjfv * e1000_led_off_82543 - Turn off SW controllable LED 1508169589Sjfv * @hw: pointer to the HW structure 1509169240Sjfv * 1510185353Sjfv * Turns the SW defined LED off. 1511169240Sjfv **/ 1512177867Sjfvstatic s32 e1000_led_off_82543(struct e1000_hw *hw) 1513169240Sjfv{ 1514169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1515169240Sjfv 1516169240Sjfv DEBUGFUNC("e1000_led_off_82543"); 1517169240Sjfv 1518169240Sjfv if (hw->mac.type == e1000_82544 && 1519173788Sjfv hw->phy.media_type == e1000_media_type_copper) { 1520176667Sjfv /* Set SW-definable Pin 0 to turn off the LED */ 1521169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1522169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1523169240Sjfv } else { 1524169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1525169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1526169240Sjfv } 1527169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1528169240Sjfv 1529169240Sjfv return E1000_SUCCESS; 1530169240Sjfv} 1531169240Sjfv 1532169240Sjfv/** 1533169240Sjfv * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1534169589Sjfv * @hw: pointer to the HW structure 1535169240Sjfv * 1536169240Sjfv * Clears the hardware counters by reading the counter registers. 1537169240Sjfv **/ 1538177867Sjfvstatic void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1539169240Sjfv{ 1540169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1541169240Sjfv 1542169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1543169240Sjfv 1544185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1545185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1546185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1547185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1548185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1549185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1550185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1551185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1552185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1553185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1554185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1555185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 1556169240Sjfv 1557185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 1558185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 1559185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 1560185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 1561185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 1562185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 1563169240Sjfv} 1564200528Sjfv 1565200528Sjfv/** 1566200528Sjfv * e1000_read_mac_addr_82543 - Read device MAC address 1567200528Sjfv * @hw: pointer to the HW structure 1568200528Sjfv * 1569200528Sjfv * Reads the device MAC address from the EEPROM and stores the value. 1570200528Sjfv * Since devices with two ports use the same EEPROM, we increment the 1571200528Sjfv * last bit in the MAC address for the second port. 1572200528Sjfv * 1573200528Sjfv **/ 1574200528Sjfvs32 e1000_read_mac_addr_82543(struct e1000_hw *hw) 1575200528Sjfv{ 1576200528Sjfv s32 ret_val = E1000_SUCCESS; 1577200528Sjfv u16 offset, nvm_data, i; 1578200528Sjfv 1579200528Sjfv DEBUGFUNC("e1000_read_mac_addr"); 1580200528Sjfv 1581200528Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1582200528Sjfv offset = i >> 1; 1583200528Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1584200528Sjfv if (ret_val) { 1585200528Sjfv DEBUGOUT("NVM Read Error\n"); 1586200528Sjfv goto out; 1587200528Sjfv } 1588200528Sjfv hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1589200528Sjfv hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1590200528Sjfv } 1591200528Sjfv 1592200528Sjfv /* Flip last bit of mac address if we're on second port */ 1593200528Sjfv if (hw->bus.func == E1000_FUNC_1) 1594200528Sjfv hw->mac.perm_addr[5] ^= 1; 1595200528Sjfv 1596200528Sjfv for (i = 0; i < ETH_ADDR_LEN; i++) 1597200528Sjfv hw->mac.addr[i] = hw->mac.perm_addr[i]; 1598200528Sjfv 1599200528Sjfvout: 1600200528Sjfv return ret_val; 1601200528Sjfv} 1602