e1000_82541.c revision 194865
1235783Skib/****************************************************************************** 2235783Skib 3235783Skib Copyright (c) 2001-2009, Intel Corporation 4235783Skib All rights reserved. 5235783Skib 6235783Skib Redistribution and use in source and binary forms, with or without 7235783Skib modification, are permitted provided that the following conditions are met: 8235783Skib 9235783Skib 1. Redistributions of source code must retain the above copyright notice, 10235783Skib this list of conditions and the following disclaimer. 11235783Skib 12235783Skib 2. Redistributions in binary form must reproduce the above copyright 13235783Skib notice, this list of conditions and the following disclaimer in the 14235783Skib documentation and/or other materials provided with the distribution. 15235783Skib 16235783Skib 3. Neither the name of the Intel Corporation nor the names of its 17235783Skib contributors may be used to endorse or promote products derived from 18235783Skib this software without specific prior written permission. 19235783Skib 20235783Skib THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21235783Skib AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22235783Skib IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23235783Skib ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24235783Skib LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25235783Skib CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26235783Skib SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27235783Skib INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28235783Skib CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29235783Skib ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30235783Skib POSSIBILITY OF SUCH DAMAGE. 31235783Skib 32235783Skib******************************************************************************/ 33235783Skib/*$FreeBSD: head/sys/dev/e1000/e1000_82541.c 194865 2009-06-24 17:41:29Z jfv $*/ 34235783Skib 35235783Skib/* 36235783Skib * 82541EI Gigabit Ethernet Controller 37235783Skib * 82541ER Gigabit Ethernet Controller 38235783Skib * 82541GI Gigabit Ethernet Controller 39235783Skib * 82541PI Gigabit Ethernet Controller 40235783Skib * 82547EI Gigabit Ethernet Controller 41235783Skib * 82547GI Gigabit Ethernet Controller 42235783Skib */ 43235783Skib 44235783Skib#include "e1000_api.h" 45235783Skib 46235783Skibstatic s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47235783Skibstatic s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48235783Skibstatic s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49235783Skibstatic s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50235783Skibstatic s32 e1000_init_hw_82541(struct e1000_hw *hw); 51235783Skibstatic s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52235783Skib u16 *duplex); 53235783Skibstatic s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54235783Skibstatic s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55235783Skibstatic s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56235783Skibstatic s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57235783Skibstatic s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58235783Skib bool active); 59235783Skibstatic s32 e1000_setup_led_82541(struct e1000_hw *hw); 60235783Skibstatic s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61235783Skibstatic void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62235783Skibstatic s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 63235783Skib bool link_up); 64235783Skibstatic s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 65235783Skibstatic void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 66235783Skib 67235783Skibstatic const u16 e1000_igp_cable_length_table[] = 68235783Skib { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 69235783Skib 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 70235783Skib 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 71235783Skib 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 72235783Skib 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 73235783Skib 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 74235783Skib 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 75235783Skib 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 76235783Skib#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 77235783Skib (sizeof(e1000_igp_cable_length_table) / \ 78235783Skib sizeof(e1000_igp_cable_length_table[0])) 79235783Skib 80235783Skib/** 81235783Skib * e1000_init_phy_params_82541 - Init PHY func ptrs. 82235783Skib * @hw: pointer to the HW structure 83235783Skib **/ 84235783Skibstatic s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 85235783Skib{ 86235783Skib struct e1000_phy_info *phy = &hw->phy; 87235783Skib s32 ret_val = E1000_SUCCESS; 88235783Skib 89235783Skib DEBUGFUNC("e1000_init_phy_params_82541"); 90235783Skib 91235783Skib phy->addr = 1; 92235783Skib phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 93235783Skib phy->reset_delay_us = 10000; 94235783Skib phy->type = e1000_phy_igp; 95235783Skib 96235783Skib /* Function Pointers */ 97235783Skib phy->ops.check_polarity = e1000_check_polarity_igp; 98235783Skib phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 99235783Skib phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 100235783Skib phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 101235783Skib phy->ops.get_info = e1000_get_phy_info_igp; 102235783Skib phy->ops.read_reg = e1000_read_phy_reg_igp; 103235783Skib phy->ops.reset = e1000_phy_hw_reset_82541; 104235783Skib phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 105235783Skib phy->ops.write_reg = e1000_write_phy_reg_igp; 106235783Skib phy->ops.power_up = e1000_power_up_phy_copper; 107235783Skib phy->ops.power_down = e1000_power_down_phy_copper_82541; 108235783Skib 109235783Skib ret_val = e1000_get_phy_id(hw); 110235783Skib if (ret_val) 111235783Skib goto out; 112235783Skib 113235783Skib /* Verify phy id */ 114235783Skib if (phy->id != IGP01E1000_I_PHY_ID) { 115235783Skib ret_val = -E1000_ERR_PHY; 116235783Skib goto out; 117235783Skib } 118235783Skib 119235783Skibout: 120235783Skib return ret_val; 121235783Skib} 122235783Skib 123235783Skib/** 124235783Skib * e1000_init_nvm_params_82541 - Init NVM func ptrs. 125235783Skib * @hw: pointer to the HW structure 126235783Skib **/ 127235783Skibstatic s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 128235783Skib{ 129235783Skib struct e1000_nvm_info *nvm = &hw->nvm; 130235783Skib s32 ret_val = E1000_SUCCESS; 131235783Skib u32 eecd = E1000_READ_REG(hw, E1000_EECD); 132235783Skib u16 size; 133235783Skib 134235783Skib DEBUGFUNC("e1000_init_nvm_params_82541"); 135235783Skib 136235783Skib switch (nvm->override) { 137235783Skib case e1000_nvm_override_spi_large: 138235783Skib nvm->type = e1000_nvm_eeprom_spi; 139235783Skib eecd |= E1000_EECD_ADDR_BITS; 140235783Skib break; 141235783Skib case e1000_nvm_override_spi_small: 142235783Skib nvm->type = e1000_nvm_eeprom_spi; 143235783Skib eecd &= ~E1000_EECD_ADDR_BITS; 144235783Skib break; 145235783Skib case e1000_nvm_override_microwire_large: 146235783Skib nvm->type = e1000_nvm_eeprom_microwire; 147235783Skib eecd |= E1000_EECD_SIZE; 148235783Skib break; 149235783Skib case e1000_nvm_override_microwire_small: 150235783Skib nvm->type = e1000_nvm_eeprom_microwire; 151235783Skib eecd &= ~E1000_EECD_SIZE; 152235783Skib break; 153235783Skib default: 154235783Skib nvm->type = eecd & E1000_EECD_TYPE 155235783Skib ? e1000_nvm_eeprom_spi 156235783Skib : e1000_nvm_eeprom_microwire; 157235783Skib break; 158235783Skib } 159235783Skib 160235783Skib if (nvm->type == e1000_nvm_eeprom_spi) { 161235783Skib nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 162235783Skib ? 16 : 8; 163235783Skib nvm->delay_usec = 1; 164235783Skib nvm->opcode_bits = 8; 165235783Skib nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 166235783Skib ? 32 : 8; 167235783Skib 168235783Skib /* Function Pointers */ 169235783Skib nvm->ops.acquire = e1000_acquire_nvm_generic; 170235783Skib nvm->ops.read = e1000_read_nvm_spi; 171235783Skib nvm->ops.release = e1000_release_nvm_generic; 172235783Skib nvm->ops.update = e1000_update_nvm_checksum_generic; 173235783Skib nvm->ops.valid_led_default = e1000_valid_led_default_generic; 174235783Skib nvm->ops.validate = e1000_validate_nvm_checksum_generic; 175235783Skib nvm->ops.write = e1000_write_nvm_spi; 176235783Skib 177235783Skib /* 178235783Skib * nvm->word_size must be discovered after the pointers 179235783Skib * are set so we can verify the size from the nvm image 180235783Skib * itself. Temporarily set it to a dummy value so the 181235783Skib * read will work. 182235783Skib */ 183235783Skib nvm->word_size = 64; 184235783Skib ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 185235783Skib if (ret_val) 186235783Skib goto out; 187235783Skib size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 188235783Skib /* 189235783Skib * if size != 0, it can be added to a constant and become 190235783Skib * the left-shift value to set the word_size. Otherwise, 191235783Skib * word_size stays at 64. 192235783Skib */ 193235783Skib if (size) { 194235783Skib size += NVM_WORD_SIZE_BASE_SHIFT_82541; 195255013Sjkim nvm->word_size = 1 << size; 196235783Skib } 197235783Skib } else { 198235783Skib nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 199235783Skib ? 8 : 6; 200235783Skib nvm->delay_usec = 50; 201235783Skib nvm->opcode_bits = 3; 202235783Skib nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 203235783Skib ? 256 : 64; 204235783Skib 205235783Skib /* Function Pointers */ 206235783Skib nvm->ops.acquire = e1000_acquire_nvm_generic; 207235783Skib nvm->ops.read = e1000_read_nvm_microwire; 208235783Skib nvm->ops.release = e1000_release_nvm_generic; 209235783Skib nvm->ops.update = e1000_update_nvm_checksum_generic; 210235783Skib nvm->ops.valid_led_default = e1000_valid_led_default_generic; 211235783Skib nvm->ops.validate = e1000_validate_nvm_checksum_generic; 212235783Skib nvm->ops.write = e1000_write_nvm_microwire; 213235783Skib } 214235783Skib 215235783Skibout: 216235783Skib return ret_val; 217235783Skib} 218235783Skib 219235783Skib/** 220235783Skib * e1000_init_mac_params_82541 - Init MAC func ptrs. 221235783Skib * @hw: pointer to the HW structure 222235783Skib **/ 223235783Skibstatic s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 224235783Skib{ 225235783Skib struct e1000_mac_info *mac = &hw->mac; 226235783Skib 227235783Skib DEBUGFUNC("e1000_init_mac_params_82541"); 228235783Skib 229235783Skib /* Set media type */ 230235783Skib hw->phy.media_type = e1000_media_type_copper; 231235783Skib /* Set mta register count */ 232235783Skib mac->mta_reg_count = 128; 233235783Skib /* Set rar entry count */ 234235783Skib mac->rar_entry_count = E1000_RAR_ENTRIES; 235235783Skib /* Set if part includes ASF firmware */ 236235783Skib mac->asf_firmware_present = TRUE; 237235783Skib 238235783Skib /* Function Pointers */ 239235783Skib 240235783Skib /* bus type/speed/width */ 241235783Skib mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 242235783Skib /* function id */ 243235783Skib mac->ops.set_lan_id = e1000_set_lan_id_single_port; 244235783Skib /* reset */ 245235783Skib mac->ops.reset_hw = e1000_reset_hw_82541; 246235783Skib /* hw initialization */ 247235783Skib mac->ops.init_hw = e1000_init_hw_82541; 248235783Skib /* link setup */ 249235783Skib mac->ops.setup_link = e1000_setup_link_generic; 250235783Skib /* physical interface link setup */ 251235783Skib mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 252235783Skib /* check for link */ 253235783Skib mac->ops.check_for_link = e1000_check_for_link_82541; 254235783Skib /* link info */ 255235783Skib mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 256235783Skib /* multicast address update */ 257235783Skib mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 258235783Skib /* writing VFTA */ 259235783Skib mac->ops.write_vfta = e1000_write_vfta_generic; 260235783Skib /* clearing VFTA */ 261235783Skib mac->ops.clear_vfta = e1000_clear_vfta_generic; 262235783Skib /* setting MTA */ 263235783Skib mac->ops.mta_set = e1000_mta_set_generic; 264235783Skib /* ID LED init */ 265235783Skib mac->ops.id_led_init = e1000_id_led_init_generic; 266280369Skib /* setup LED */ 267280369Skib mac->ops.setup_led = e1000_setup_led_82541; 268280369Skib /* cleanup LED */ 269280369Skib mac->ops.cleanup_led = e1000_cleanup_led_82541; 270280369Skib /* turn on/off LED */ 271280369Skib mac->ops.led_on = e1000_led_on_generic; 272235783Skib mac->ops.led_off = e1000_led_off_generic; 273235783Skib /* clear hardware counters */ 274235783Skib mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 275235783Skib 276235783Skib return E1000_SUCCESS; 277235783Skib} 278235783Skib 279280369Skib/** 280235783Skib * e1000_init_function_pointers_82541 - Init func ptrs. 281235783Skib * @hw: pointer to the HW structure 282235783Skib * 283235783Skib * Called to initialize all function pointers and parameters. 284235783Skib **/ 285235783Skibvoid e1000_init_function_pointers_82541(struct e1000_hw *hw) 286235783Skib{ 287235783Skib DEBUGFUNC("e1000_init_function_pointers_82541"); 288280369Skib 289280369Skib hw->mac.ops.init_params = e1000_init_mac_params_82541; 290235783Skib hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 291235783Skib hw->phy.ops.init_params = e1000_init_phy_params_82541; 292235783Skib} 293235783Skib 294235783Skib/** 295235783Skib * e1000_reset_hw_82541 - Reset hardware 296235783Skib * @hw: pointer to the HW structure 297235783Skib * 298235783Skib * This resets the hardware into a known state. 299235783Skib **/ 300235783Skibstatic s32 e1000_reset_hw_82541(struct e1000_hw *hw) 301235783Skib{ 302235783Skib u32 ledctl, ctrl, icr, manc; 303235783Skib 304235783Skib DEBUGFUNC("e1000_reset_hw_82541"); 305235783Skib 306235783Skib DEBUGOUT("Masking off all interrupts\n"); 307235783Skib E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 308235783Skib 309235783Skib E1000_WRITE_REG(hw, E1000_RCTL, 0); 310235783Skib E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 311235783Skib E1000_WRITE_FLUSH(hw); 312235783Skib 313235783Skib /* 314235783Skib * Delay to allow any outstanding PCI transactions to complete 315235783Skib * before resetting the device. 316235783Skib */ 317235783Skib msec_delay(10); 318235783Skib 319235783Skib ctrl = E1000_READ_REG(hw, E1000_CTRL); 320235783Skib 321235783Skib /* Must reset the Phy before resetting the MAC */ 322235783Skib if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 323235783Skib E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 324235783Skib msec_delay(5); 325235783Skib } 326235783Skib 327235783Skib DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 328235783Skib switch (hw->mac.type) { 329235783Skib case e1000_82541: 330235783Skib case e1000_82541_rev_2: 331235783Skib /* 332235783Skib * These controllers can't ack the 64-bit write when 333235783Skib * issuing the reset, so we use IO-mapping as a 334235783Skib * workaround to issue the reset. 335235783Skib */ 336235783Skib E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 337235783Skib break; 338235783Skib default: 339235783Skib E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 340235783Skib break; 341235783Skib } 342235783Skib 343235783Skib /* Wait for NVM reload */ 344235783Skib msec_delay(20); 345235783Skib 346235783Skib /* Disable HW ARPs on ASF enabled adapters */ 347235783Skib manc = E1000_READ_REG(hw, E1000_MANC); 348235783Skib manc &= ~E1000_MANC_ARP_EN; 349235783Skib E1000_WRITE_REG(hw, E1000_MANC, manc); 350235783Skib 351235783Skib if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 352235783Skib e1000_phy_init_script_82541(hw); 353235783Skib 354235783Skib /* Configure activity LED after Phy reset */ 355235783Skib ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 356235783Skib ledctl &= IGP_ACTIVITY_LED_MASK; 357235783Skib ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 358235783Skib E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 359235783Skib } 360235783Skib 361235783Skib /* Once again, mask the interrupts */ 362235783Skib DEBUGOUT("Masking off all interrupts\n"); 363235783Skib E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 364235783Skib 365235783Skib /* Clear any pending interrupt events. */ 366235783Skib icr = E1000_READ_REG(hw, E1000_ICR); 367235783Skib 368235783Skib return E1000_SUCCESS; 369235783Skib} 370235783Skib 371235783Skib/** 372235783Skib * e1000_init_hw_82541 - Initialize hardware 373235783Skib * @hw: pointer to the HW structure 374235783Skib * 375280369Skib * This inits the hardware readying it for operation. 376280369Skib **/ 377280369Skibstatic s32 e1000_init_hw_82541(struct e1000_hw *hw) 378280369Skib{ 379235783Skib struct e1000_mac_info *mac = &hw->mac; 380280369Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 381235783Skib u32 i, txdctl; 382235783Skib s32 ret_val; 383235783Skib 384235783Skib DEBUGFUNC("e1000_init_hw_82541"); 385280369Skib 386280369Skib /* Initialize identification LED */ 387280369Skib ret_val = mac->ops.id_led_init(hw); 388280369Skib if (ret_val) { 389235783Skib DEBUGOUT("Error initializing identification LED\n"); 390235783Skib /* This is not fatal and we should not stop init due to this */ 391235783Skib } 392235783Skib 393235783Skib /* Storing the Speed Power Down value for later use */ 394235783Skib ret_val = hw->phy.ops.read_reg(hw, 395235783Skib IGP01E1000_GMII_FIFO, 396235783Skib &dev_spec->spd_default); 397235783Skib if (ret_val) 398235783Skib goto out; 399235783Skib 400280369Skib /* Disabling VLAN filtering */ 401235783Skib DEBUGOUT("Initializing the IEEE VLAN\n"); 402235783Skib mac->ops.clear_vfta(hw); 403235783Skib 404280369Skib /* Setup the receive address. */ 405280369Skib e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 406280369Skib 407280369Skib /* Zero out the Multicast HASH table */ 408235783Skib DEBUGOUT("Zeroing the MTA\n"); 409235783Skib for (i = 0; i < mac->mta_reg_count; i++) { 410235783Skib E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 411235783Skib /* 412235783Skib * Avoid back to back register writes by adding the register 413235783Skib * read (flush). This is to protect against some strange 414235783Skib * bridge configurations that may issue Memory Write Block 415235783Skib * (MWB) to our register space. 416235783Skib */ 417235783Skib E1000_WRITE_FLUSH(hw); 418235783Skib } 419235783Skib 420235783Skib /* Setup link and flow control */ 421280369Skib ret_val = mac->ops.setup_link(hw); 422280369Skib 423280369Skib txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 424280369Skib txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 425280369Skib E1000_TXDCTL_FULL_TX_DESC_WB; 426280369Skib E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 427280369Skib 428280369Skib /* 429280369Skib * Clear all of the statistics registers (clear on read). It is 430280369Skib * important that we do this after we have tried to establish link 431235783Skib * because the symbol error count will increment wildly if there 432235783Skib * is no link. 433235783Skib */ 434235783Skib e1000_clear_hw_cntrs_82541(hw); 435235783Skib 436235783Skibout: 437235783Skib return ret_val; 438235783Skib} 439235783Skib 440235783Skib/** 441280369Skib * e1000_get_link_up_info_82541 - Report speed and duplex 442280369Skib * @hw: pointer to the HW structure 443235783Skib * @speed: pointer to speed buffer 444235783Skib * @duplex: pointer to duplex buffer 445280369Skib * 446235783Skib * Retrieve the current speed and duplex configuration. 447235783Skib **/ 448280369Skibstatic s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 449280369Skib u16 *duplex) 450280369Skib{ 451280369Skib struct e1000_phy_info *phy = &hw->phy; 452280369Skib s32 ret_val; 453280369Skib u16 data; 454280369Skib 455235783Skib DEBUGFUNC("e1000_get_link_up_info_82541"); 456280369Skib 457235783Skib ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 458235783Skib if (ret_val) 459235783Skib goto out; 460280369Skib 461280369Skib if (!phy->speed_downgraded) 462280369Skib goto out; 463280369Skib 464280369Skib /* 465280369Skib * IGP01 PHY may advertise full duplex operation after speed 466280369Skib * downgrade even if it is operating at half duplex. 467280369Skib * Here we set the duplex settings to match the duplex in the 468280369Skib * link partner's capabilities. 469280369Skib */ 470280369Skib ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 471280369Skib if (ret_val) 472280369Skib goto out; 473280369Skib 474280369Skib if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 475280369Skib *duplex = HALF_DUPLEX; 476280369Skib } else { 477235783Skib ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 478280369Skib if (ret_val) 479235783Skib goto out; 480235783Skib 481235783Skib if (*speed == SPEED_100) { 482235783Skib if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 483235783Skib *duplex = HALF_DUPLEX; 484235783Skib } else if (*speed == SPEED_10) { 485235783Skib if (!(data & NWAY_LPAR_10T_FD_CAPS)) 486235783Skib *duplex = HALF_DUPLEX; 487235783Skib } 488235783Skib } 489235783Skib 490235783Skibout: 491235783Skib return ret_val; 492235783Skib} 493235783Skib 494235783Skib/** 495235783Skib * e1000_phy_hw_reset_82541 - PHY hardware reset 496235783Skib * @hw: pointer to the HW structure 497235783Skib * 498235783Skib * Verify the reset block is not blocking us from resetting. Acquire 499235783Skib * semaphore (if necessary) and read/set/write the device control reset 500235783Skib * bit in the PHY. Wait the appropriate delay time for the device to 501235783Skib * reset and release the semaphore (if necessary). 502235783Skib **/ 503235783Skibstatic s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 504235783Skib{ 505235783Skib s32 ret_val; 506235783Skib u32 ledctl; 507235783Skib 508235783Skib DEBUGFUNC("e1000_phy_hw_reset_82541"); 509235783Skib 510235783Skib ret_val = e1000_phy_hw_reset_generic(hw); 511235783Skib if (ret_val) 512235783Skib goto out; 513235783Skib 514235783Skib e1000_phy_init_script_82541(hw); 515235783Skib 516235783Skib if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 517235783Skib /* Configure activity LED after PHY reset */ 518235783Skib ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 519235783Skib ledctl &= IGP_ACTIVITY_LED_MASK; 520235783Skib ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 521235783Skib E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 522235783Skib } 523235783Skib 524235783Skibout: 525235783Skib return ret_val; 526235783Skib} 527235783Skib 528235783Skib/** 529235783Skib * e1000_setup_copper_link_82541 - Configure copper link settings 530235783Skib * @hw: pointer to the HW structure 531235783Skib * 532235783Skib * Calls the appropriate function to configure the link for auto-neg or forced 533280369Skib * speed and duplex. Then we check for link, once link is established calls 534280369Skib * to configure collision distance and flow control are called. If link is 535280369Skib * not established, we return -E1000_ERR_PHY (-2). 536280369Skib **/ 537280369Skibstatic s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 538280369Skib{ 539280369Skib struct e1000_phy_info *phy = &hw->phy; 540235783Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 541235783Skib s32 ret_val; 542235783Skib u32 ctrl, ledctl; 543235783Skib 544235783Skib DEBUGFUNC("e1000_setup_copper_link_82541"); 545235783Skib 546235783Skib ctrl = E1000_READ_REG(hw, E1000_CTRL); 547235783Skib ctrl |= E1000_CTRL_SLU; 548235783Skib ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 549235783Skib E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 550235783Skib 551235783Skib hw->phy.reset_disable = FALSE; 552280369Skib 553235783Skib /* Earlier revs of the IGP phy require us to force MDI. */ 554235783Skib if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 555235783Skib dev_spec->dsp_config = e1000_dsp_config_disabled; 556235783Skib phy->mdix = 1; 557235783Skib } else { 558235783Skib dev_spec->dsp_config = e1000_dsp_config_enabled; 559235783Skib } 560280369Skib 561280369Skib ret_val = e1000_copper_link_setup_igp(hw); 562280369Skib if (ret_val) 563235783Skib goto out; 564280369Skib 565235783Skib if (hw->mac.autoneg) { 566280369Skib if (dev_spec->ffe_config == e1000_ffe_config_active) 567235783Skib dev_spec->ffe_config = e1000_ffe_config_enabled; 568235783Skib } 569235783Skib 570235783Skib /* Configure activity LED after Phy reset */ 571235783Skib ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 572235783Skib ledctl &= IGP_ACTIVITY_LED_MASK; 573235783Skib ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 574235783Skib E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 575235783Skib 576235783Skib ret_val = e1000_setup_copper_link_generic(hw); 577235783Skib 578235783Skibout: 579235783Skib return ret_val; 580235783Skib} 581235783Skib 582235783Skib/** 583235783Skib * e1000_check_for_link_82541 - Check/Store link connection 584235783Skib * @hw: pointer to the HW structure 585235783Skib * 586235783Skib * This checks the link condition of the adapter and stores the 587235783Skib * results in the hw->mac structure. 588235783Skib **/ 589235783Skibstatic s32 e1000_check_for_link_82541(struct e1000_hw *hw) 590235783Skib{ 591235783Skib struct e1000_mac_info *mac = &hw->mac; 592235783Skib s32 ret_val; 593235783Skib bool link; 594235783Skib 595235783Skib DEBUGFUNC("e1000_check_for_link_82541"); 596235783Skib 597235783Skib /* 598235783Skib * We only want to go out to the PHY registers to see if Auto-Neg 599235783Skib * has completed and/or if our link status has changed. The 600235783Skib * get_link_status flag is set upon receiving a Link Status 601235783Skib * Change or Rx Sequence Error interrupt. 602235783Skib */ 603235783Skib if (!mac->get_link_status) { 604235783Skib ret_val = E1000_SUCCESS; 605280369Skib goto out; 606235783Skib } 607235783Skib 608235783Skib /* 609235783Skib * First we want to see if the MII Status Register reports 610235783Skib * link. If so, then we want to get the current speed/duplex 611235783Skib * of the PHY. 612235783Skib */ 613235783Skib ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 614235783Skib if (ret_val) 615235783Skib goto out; 616235783Skib 617235783Skib if (!link) { 618235783Skib ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 619235783Skib goto out; /* No link detected */ 620235783Skib } 621235783Skib 622235783Skib mac->get_link_status = FALSE; 623235783Skib 624235783Skib /* 625235783Skib * Check if there was DownShift, must be checked 626235783Skib * immediately after link-up 627235783Skib */ 628235783Skib e1000_check_downshift_generic(hw); 629235783Skib 630235783Skib /* 631235783Skib * If we are forcing speed/duplex, then we simply return since 632235783Skib * we have already determined whether we have link or not. 633235783Skib */ 634235783Skib if (!mac->autoneg) { 635235783Skib ret_val = -E1000_ERR_CONFIG; 636235783Skib goto out; 637235783Skib } 638235783Skib 639235783Skib ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 640235783Skib 641235783Skib /* 642235783Skib * Auto-Neg is enabled. Auto Speed Detection takes care 643235783Skib * of MAC speed/duplex configuration. So we only need to 644235783Skib * configure Collision Distance in the MAC. 645235783Skib */ 646280369Skib e1000_config_collision_dist_generic(hw); 647235783Skib 648235783Skib /* 649235783Skib * Configure Flow Control now that Auto-Neg has completed. 650235783Skib * First, we need to restore the desired flow control 651235783Skib * settings because we may have had to re-autoneg with a 652235783Skib * different link partner. 653235783Skib */ 654235783Skib ret_val = e1000_config_fc_after_link_up_generic(hw); 655235783Skib if (ret_val) { 656235783Skib DEBUGOUT("Error configuring flow control\n"); 657235783Skib } 658235783Skib 659235783Skibout: 660235783Skib return ret_val; 661235783Skib} 662235783Skib 663235783Skib/** 664235783Skib * e1000_config_dsp_after_link_change_82541 - Config DSP after link 665235783Skib * @hw: pointer to the HW structure 666235783Skib * @link_up: boolean flag for link up status 667235783Skib * 668235783Skib * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 669235783Skib * at any other case. 670235783Skib * 671235783Skib * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 672235783Skib * gigabit link is achieved to improve link quality. 673235783Skib **/ 674235783Skibstatic s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 675235783Skib bool link_up) 676235783Skib{ 677235783Skib struct e1000_phy_info *phy = &hw->phy; 678235783Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 679235783Skib s32 ret_val; 680235783Skib u32 idle_errs = 0; 681235783Skib u16 phy_data, phy_saved_data, speed, duplex, i; 682235783Skib u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 683235783Skib u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 684235783Skib {IGP01E1000_PHY_AGC_PARAM_A, 685235783Skib IGP01E1000_PHY_AGC_PARAM_B, 686235783Skib IGP01E1000_PHY_AGC_PARAM_C, 687235783Skib IGP01E1000_PHY_AGC_PARAM_D}; 688235783Skib 689235783Skib DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 690235783Skib 691235783Skib if (link_up) { 692235783Skib ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 693235783Skib if (ret_val) { 694235783Skib DEBUGOUT("Error getting link speed and duplex\n"); 695235783Skib goto out; 696235783Skib } 697235783Skib 698235783Skib if (speed != SPEED_1000) { 699235783Skib ret_val = E1000_SUCCESS; 700235783Skib goto out; 701235783Skib } 702235783Skib 703235783Skib ret_val = phy->ops.get_cable_length(hw); 704235783Skib if (ret_val) 705235783Skib goto out; 706235783Skib 707235783Skib if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 708235783Skib phy->min_cable_length >= 50) { 709235783Skib 710235783Skib for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 711235783Skib ret_val = phy->ops.read_reg(hw, 712235783Skib dsp_reg_array[i], 713235783Skib &phy_data); 714235783Skib if (ret_val) 715235783Skib goto out; 716235783Skib 717235783Skib phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 718235783Skib 719235783Skib ret_val = phy->ops.write_reg(hw, 720235783Skib dsp_reg_array[i], 721235783Skib phy_data); 722235783Skib if (ret_val) 723235783Skib goto out; 724235783Skib } 725235783Skib dev_spec->dsp_config = e1000_dsp_config_activated; 726235783Skib } 727235783Skib 728235783Skib if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 729235783Skib (phy->min_cable_length >= 50)) { 730235783Skib ret_val = E1000_SUCCESS; 731235783Skib goto out; 732235783Skib } 733235783Skib 734235783Skib /* clear previous idle error counts */ 735235783Skib ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 736235783Skib if (ret_val) 737235783Skib goto out; 738235783Skib 739235783Skib for (i = 0; i < ffe_idle_err_timeout; i++) { 740235783Skib usec_delay(1000); 741235783Skib ret_val = phy->ops.read_reg(hw, 742235783Skib PHY_1000T_STATUS, 743235783Skib &phy_data); 744235783Skib if (ret_val) 745235783Skib goto out; 746235783Skib 747235783Skib idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 748235783Skib if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 749235783Skib dev_spec->ffe_config = e1000_ffe_config_active; 750235783Skib 751235783Skib ret_val = phy->ops.write_reg(hw, 752235783Skib IGP01E1000_PHY_DSP_FFE, 753235783Skib IGP01E1000_PHY_DSP_FFE_CM_CP); 754235783Skib if (ret_val) 755235783Skib goto out; 756235783Skib break; 757235783Skib } 758235783Skib 759235783Skib if (idle_errs) 760235783Skib ffe_idle_err_timeout = 761235783Skib FFE_IDLE_ERR_COUNT_TIMEOUT_100; 762235783Skib } 763235783Skib } else { 764235783Skib if (dev_spec->dsp_config == e1000_dsp_config_activated) { 765235783Skib /* 766235783Skib * Save off the current value of register 0x2F5B 767235783Skib * to be restored at the end of the routines. 768235783Skib */ 769235783Skib ret_val = phy->ops.read_reg(hw, 770235783Skib 0x2F5B, 771235783Skib &phy_saved_data); 772235783Skib if (ret_val) 773235783Skib goto out; 774235783Skib 775235783Skib /* Disable the PHY transmitter */ 776235783Skib ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 777235783Skib if (ret_val) 778235783Skib goto out; 779235783Skib 780235783Skib msec_delay_irq(20); 781235783Skib 782235783Skib ret_val = phy->ops.write_reg(hw, 783235783Skib 0x0000, 784235783Skib IGP01E1000_IEEE_FORCE_GIG); 785235783Skib if (ret_val) 786235783Skib goto out; 787235783Skib for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 788235783Skib ret_val = phy->ops.read_reg(hw, 789235783Skib dsp_reg_array[i], 790235783Skib &phy_data); 791235783Skib if (ret_val) 792235783Skib goto out; 793235783Skib 794235783Skib phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 795235783Skib phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 796235783Skib 797235783Skib ret_val = phy->ops.write_reg(hw, 798235783Skib dsp_reg_array[i], 799235783Skib phy_data); 800235783Skib if (ret_val) 801235783Skib goto out; 802235783Skib } 803235783Skib 804235783Skib ret_val = phy->ops.write_reg(hw, 805235783Skib 0x0000, 806235783Skib IGP01E1000_IEEE_RESTART_AUTONEG); 807235783Skib if (ret_val) 808235783Skib goto out; 809235783Skib 810235783Skib msec_delay_irq(20); 811235783Skib 812235783Skib /* Now enable the transmitter */ 813235783Skib ret_val = phy->ops.write_reg(hw, 814235783Skib 0x2F5B, 815235783Skib phy_saved_data); 816235783Skib if (ret_val) 817235783Skib goto out; 818235783Skib 819235783Skib dev_spec->dsp_config = e1000_dsp_config_enabled; 820235783Skib } 821235783Skib 822235783Skib if (dev_spec->ffe_config != e1000_ffe_config_active) { 823235783Skib ret_val = E1000_SUCCESS; 824235783Skib goto out; 825235783Skib } 826235783Skib 827235783Skib /* 828235783Skib * Save off the current value of register 0x2F5B 829235783Skib * to be restored at the end of the routines. 830235783Skib */ 831235783Skib ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 832235783Skib if (ret_val) 833235783Skib goto out; 834235783Skib 835235783Skib /* Disable the PHY transmitter */ 836235783Skib ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 837235783Skib if (ret_val) 838235783Skib goto out; 839235783Skib 840235783Skib msec_delay_irq(20); 841235783Skib 842235783Skib ret_val = phy->ops.write_reg(hw, 843235783Skib 0x0000, 844235783Skib IGP01E1000_IEEE_FORCE_GIG); 845235783Skib if (ret_val) 846235783Skib goto out; 847235783Skib 848235783Skib ret_val = phy->ops.write_reg(hw, 849235783Skib IGP01E1000_PHY_DSP_FFE, 850235783Skib IGP01E1000_PHY_DSP_FFE_DEFAULT); 851235783Skib if (ret_val) 852235783Skib goto out; 853235783Skib 854235783Skib ret_val = phy->ops.write_reg(hw, 855235783Skib 0x0000, 856235783Skib IGP01E1000_IEEE_RESTART_AUTONEG); 857235783Skib if (ret_val) 858235783Skib goto out; 859235783Skib 860235783Skib msec_delay_irq(20); 861235783Skib 862235783Skib /* Now enable the transmitter */ 863235783Skib ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 864235783Skib 865235783Skib if (ret_val) 866235783Skib goto out; 867235783Skib 868235783Skib dev_spec->ffe_config = e1000_ffe_config_enabled; 869235783Skib } 870235783Skib 871235783Skibout: 872235783Skib return ret_val; 873235783Skib} 874235783Skib 875235783Skib/** 876235783Skib * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 877235783Skib * @hw: pointer to the HW structure 878235783Skib * 879235783Skib * The automatic gain control (agc) normalizes the amplitude of the 880235783Skib * received signal, adjusting for the attenuation produced by the 881235783Skib * cable. By reading the AGC registers, which represent the 882235783Skib * combination of coarse and fine gain value, the value can be put 883235783Skib * into a lookup table to obtain the approximate cable length 884235783Skib * for each channel. 885235783Skib **/ 886235783Skibstatic s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 887235783Skib{ 888235783Skib struct e1000_phy_info *phy = &hw->phy; 889235783Skib s32 ret_val = E1000_SUCCESS; 890235783Skib u16 i, data; 891235783Skib u16 cur_agc_value, agc_value = 0; 892235783Skib u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 893235783Skib u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 894235783Skib {IGP01E1000_PHY_AGC_A, 895235783Skib IGP01E1000_PHY_AGC_B, 896235783Skib IGP01E1000_PHY_AGC_C, 897235783Skib IGP01E1000_PHY_AGC_D}; 898235783Skib 899235783Skib DEBUGFUNC("e1000_get_cable_length_igp_82541"); 900235783Skib 901235783Skib /* Read the AGC registers for all channels */ 902235783Skib for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 903235783Skib ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 904235783Skib if (ret_val) 905235783Skib goto out; 906235783Skib 907235783Skib cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 908235783Skib 909235783Skib /* Bounds checking */ 910235783Skib if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 911235783Skib (cur_agc_value == 0)) { 912235783Skib ret_val = -E1000_ERR_PHY; 913235783Skib goto out; 914235783Skib } 915235783Skib 916235783Skib agc_value += cur_agc_value; 917235783Skib 918235783Skib if (min_agc_value > cur_agc_value) 919235783Skib min_agc_value = cur_agc_value; 920235783Skib } 921235783Skib 922235783Skib /* Remove the minimal AGC result for length < 50m */ 923235783Skib if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 924235783Skib agc_value -= min_agc_value; 925235783Skib /* Average the three remaining channels for the length. */ 926280369Skib agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 927235783Skib } else { 928235783Skib /* Average the channels for the length. */ 929235783Skib agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 930235783Skib } 931235783Skib 932235783Skib phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 933235783Skib IGP01E1000_AGC_RANGE) 934235783Skib ? (e1000_igp_cable_length_table[agc_value] - 935235783Skib IGP01E1000_AGC_RANGE) 936235783Skib : 0; 937235783Skib phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 938235783Skib IGP01E1000_AGC_RANGE; 939235783Skib 940235783Skib phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 941235783Skib 942290454Sjhbout: 943235783Skib return ret_val; 944235783Skib} 945235783Skib 946235783Skib/** 947235783Skib * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 948235783Skib * @hw: pointer to the HW structure 949290454Sjhb * @active: boolean used to enable/disable lplu 950290454Sjhb * 951235783Skib * Success returns 0, Failure returns 1 952235783Skib * 953235783Skib * The low power link up (lplu) state is set to the power management level D3 954235783Skib * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 955235783Skib * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 956235783Skib * is used during Dx states where the power conservation is most important. 957235783Skib * During driver activity, SmartSpeed should be enabled so performance is 958235783Skib * maintained. 959235783Skib **/ 960235783Skibstatic s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 961235783Skib{ 962235783Skib struct e1000_phy_info *phy = &hw->phy; 963235783Skib s32 ret_val; 964235783Skib u16 data; 965235783Skib 966235783Skib DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 967235783Skib 968235783Skib switch (hw->mac.type) { 969235783Skib case e1000_82541_rev_2: 970235783Skib case e1000_82547_rev_2: 971235783Skib break; 972290454Sjhb default: 973290454Sjhb ret_val = e1000_set_d3_lplu_state_generic(hw, active); 974290454Sjhb goto out; 975290454Sjhb break; 976235783Skib } 977235783Skib 978235783Skib ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 979235783Skib if (ret_val) 980235783Skib goto out; 981235783Skib 982235783Skib if (!active) { 983235783Skib data &= ~IGP01E1000_GMII_FLEX_SPD; 984235783Skib ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 985235783Skib if (ret_val) 986235783Skib goto out; 987235783Skib 988235783Skib /* 989235783Skib * LPLU and SmartSpeed are mutually exclusive. LPLU is used 990235783Skib * during Dx states where the power conservation is most 991235783Skib * important. During driver activity we should enable 992235783Skib * SmartSpeed, so performance is maintained. 993235783Skib */ 994235783Skib if (phy->smart_speed == e1000_smart_speed_on) { 995235783Skib ret_val = phy->ops.read_reg(hw, 996235783Skib IGP01E1000_PHY_PORT_CONFIG, 997235783Skib &data); 998235783Skib if (ret_val) 999235783Skib goto out; 1000235783Skib 1001235783Skib data |= IGP01E1000_PSCFR_SMART_SPEED; 1002235783Skib ret_val = phy->ops.write_reg(hw, 1003235783Skib IGP01E1000_PHY_PORT_CONFIG, 1004235783Skib data); 1005235783Skib if (ret_val) 1006235783Skib goto out; 1007280369Skib } else if (phy->smart_speed == e1000_smart_speed_off) { 1008280369Skib ret_val = phy->ops.read_reg(hw, 1009235783Skib IGP01E1000_PHY_PORT_CONFIG, 1010235783Skib &data); 1011235783Skib if (ret_val) 1012235783Skib goto out; 1013280369Skib 1014280369Skib data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1015235783Skib ret_val = phy->ops.write_reg(hw, 1016235783Skib IGP01E1000_PHY_PORT_CONFIG, 1017235783Skib data); 1018235783Skib if (ret_val) 1019235783Skib goto out; 1020235783Skib } 1021235783Skib } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1022235783Skib (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1023235783Skib (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1024235783Skib data |= IGP01E1000_GMII_FLEX_SPD; 1025235783Skib ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1026235783Skib if (ret_val) 1027235783Skib goto out; 1028235783Skib 1029235783Skib /* When LPLU is enabled, we should disable SmartSpeed */ 1030235783Skib ret_val = phy->ops.read_reg(hw, 1031235783Skib IGP01E1000_PHY_PORT_CONFIG, 1032235783Skib &data); 1033235783Skib if (ret_val) 1034235783Skib goto out; 1035235783Skib 1036235783Skib data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1037235783Skib ret_val = phy->ops.write_reg(hw, 1038235783Skib IGP01E1000_PHY_PORT_CONFIG, 1039235783Skib data); 1040235783Skib } 1041235783Skib 1042235783Skibout: 1043235783Skib return ret_val; 1044235783Skib} 1045235783Skib 1046280369Skib/** 1047280369Skib * e1000_setup_led_82541 - Configures SW controllable LED 1048280369Skib * @hw: pointer to the HW structure 1049280369Skib * 1050235783Skib * This prepares the SW controllable LED for use and saves the current state 1051235783Skib * of the LED so it can be later restored. 1052235783Skib **/ 1053235783Skibstatic s32 e1000_setup_led_82541(struct e1000_hw *hw) 1054235783Skib{ 1055235783Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1056235783Skib s32 ret_val; 1057235783Skib 1058235783Skib DEBUGFUNC("e1000_setup_led_82541"); 1059235783Skib 1060235783Skib ret_val = hw->phy.ops.read_reg(hw, 1061235783Skib IGP01E1000_GMII_FIFO, 1062235783Skib &dev_spec->spd_default); 1063235783Skib if (ret_val) 1064235783Skib goto out; 1065235783Skib 1066236182Skib ret_val = hw->phy.ops.write_reg(hw, 1067236182Skib IGP01E1000_GMII_FIFO, 1068235783Skib (u16)(dev_spec->spd_default & 1069235783Skib ~IGP01E1000_GMII_SPD)); 1070235783Skib if (ret_val) 1071235783Skib goto out; 1072235783Skib 1073235783Skib E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1074235783Skib 1075235783Skibout: 1076235783Skib return ret_val; 1077235783Skib} 1078235783Skib 1079235783Skib/** 1080235783Skib * e1000_cleanup_led_82541 - Set LED config to default operation 1081236182Skib * @hw: pointer to the HW structure 1082235783Skib * 1083235783Skib * Remove the current LED configuration and set the LED configuration 1084235783Skib * to the default value, saved from the EEPROM. 1085235783Skib **/ 1086235783Skibstatic s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1087236183Skib{ 1088235783Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1089235783Skib s32 ret_val; 1090235783Skib 1091235783Skib DEBUGFUNC("e1000_cleanup_led_82541"); 1092235783Skib 1093235783Skib ret_val = hw->phy.ops.write_reg(hw, 1094235783Skib IGP01E1000_GMII_FIFO, 1095235783Skib dev_spec->spd_default); 1096235783Skib if (ret_val) 1097235783Skib goto out; 1098235783Skib 1099235783Skib E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1100235783Skib 1101235783Skibout: 1102235783Skib return ret_val; 1103235783Skib} 1104235783Skib 1105235783Skib/** 1106235783Skib * e1000_phy_init_script_82541 - Initialize GbE PHY 1107235783Skib * @hw: pointer to the HW structure 1108235783Skib * 1109235783Skib * Initializes the IGP PHY. 1110235783Skib **/ 1111235783Skibstatic s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1112235783Skib{ 1113235783Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1114235783Skib u32 ret_val; 1115235783Skib u16 phy_saved_data; 1116235783Skib 1117235783Skib DEBUGFUNC("e1000_phy_init_script_82541"); 1118235783Skib 1119235783Skib if (!dev_spec->phy_init_script) { 1120235783Skib ret_val = E1000_SUCCESS; 1121235783Skib goto out; 1122235783Skib } 1123235783Skib 1124235783Skib /* Delay after phy reset to enable NVM configuration to load */ 1125235783Skib msec_delay(20); 1126235783Skib 1127290454Sjhb /* 1128271816Sdumbbell * Save off the current value of register 0x2F5B to be restored at 1129235783Skib * the end of this routine. 1130235783Skib */ 1131235783Skib ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1132235783Skib 1133235783Skib /* Disabled the PHY transmitter */ 1134235783Skib hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1135235783Skib 1136235783Skib msec_delay(20); 1137235783Skib 1138235783Skib hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1139235783Skib 1140235783Skib msec_delay(5); 1141235783Skib 1142290454Sjhb switch (hw->mac.type) { 1143290454Sjhb case e1000_82541: 1144235783Skib case e1000_82547: 1145235783Skib hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1146235783Skib 1147235783Skib hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1148235783Skib 1149235783Skib hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1150235783Skib 1151235783Skib hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1152235783Skib 1153235783Skib hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1154271816Sdumbbell 1155271816Sdumbbell hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1156271816Sdumbbell 1157290454Sjhb hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1158290454Sjhb 1159271816Sdumbbell hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1160235783Skib 1161235783Skib hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1162235783Skib break; 1163271816Sdumbbell case e1000_82541_rev_2: 1164271816Sdumbbell case e1000_82547_rev_2: 1165271816Sdumbbell hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1166290454Sjhb break; 1167290454Sjhb default: 1168271816Sdumbbell break; 1169235783Skib } 1170235783Skib 1171235783Skib hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1172235783Skib 1173235783Skib msec_delay(20); 1174235783Skib 1175235783Skib /* Now enable the transmitter */ 1176280369Skib hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1177280369Skib 1178280369Skib if (hw->mac.type == e1000_82547) { 1179290454Sjhb u16 fused, fine, coarse; 1180290454Sjhb 1181280369Skib /* Move to analog registers page */ 1182235783Skib hw->phy.ops.read_reg(hw, 1183235783Skib IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1184235783Skib &fused); 1185235783Skib 1186235783Skib if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1187235783Skib hw->phy.ops.read_reg(hw, 1188235783Skib IGP01E1000_ANALOG_FUSE_STATUS, 1189235783Skib &fused); 1190235783Skib 1191235783Skib fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1192235783Skib coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1193235783Skib 1194235783Skib if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1195235783Skib coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1196235783Skib fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1197235783Skib } else if (coarse == 1198235783Skib IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1199235783Skib fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1200235783Skib 1201235783Skib fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1202235783Skib (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1203235783Skib (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1204235783Skib 1205235783Skib hw->phy.ops.write_reg(hw, 1206235783Skib IGP01E1000_ANALOG_FUSE_CONTROL, 1207235783Skib fused); 1208235783Skib hw->phy.ops.write_reg(hw, 1209235783Skib IGP01E1000_ANALOG_FUSE_BYPASS, 1210235783Skib IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1211235783Skib } 1212235783Skib } 1213235783Skib 1214235783Skibout: 1215235783Skib return ret_val; 1216235783Skib} 1217235783Skib 1218235783Skib/** 1219235783Skib * e1000_init_script_state_82541 - Enable/Disable PHY init script 1220235783Skib * @hw: pointer to the HW structure 1221235783Skib * @state: boolean value used to enable/disable PHY init script 1222235783Skib * 1223235783Skib * Allows the driver to enable/disable the PHY init script, if the PHY is an 1224235783Skib * IGP PHY. 1225235783Skib **/ 1226280369Skibvoid e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1227280369Skib{ 1228280369Skib struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1229280369Skib 1230280369Skib DEBUGFUNC("e1000_init_script_state_82541"); 1231280369Skib 1232235783Skib if (hw->phy.type != e1000_phy_igp) { 1233235783Skib DEBUGOUT("Initialization script not necessary.\n"); 1234235783Skib goto out; 1235235783Skib } 1236235783Skib 1237235783Skib dev_spec->phy_init_script = state; 1238235783Skib 1239235783Skibout: 1240235783Skib return; 1241235783Skib} 1242235783Skib 1243235783Skib/** 1244235783Skib * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1245235783Skib * @hw: pointer to the HW structure 1246235783Skib * 1247235783Skib * In the case of a PHY power down to save power, or to turn off link during a 1248235783Skib * driver unload, or wake on lan is not enabled, remove the link. 1249235783Skib **/ 1250235783Skibstatic void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1251282199Sdumbbell{ 1252235783Skib /* If the management interface is not enabled, then power down */ 1253282199Sdumbbell if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1254235783Skib e1000_power_down_phy_copper(hw); 1255235783Skib 1256235783Skib return; 1257235783Skib} 1258282199Sdumbbell 1259235783Skib/** 1260282199Sdumbbell * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1261235783Skib * @hw: pointer to the HW structure 1262235783Skib * 1263235783Skib * Clears the hardware counters by reading the counter registers. 1264235783Skib **/ 1265235783Skibstatic void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1266235783Skib{ 1267235783Skib DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1268235783Skib 1269235783Skib e1000_clear_hw_cntrs_base_generic(hw); 1270235783Skib 1271235783Skib E1000_READ_REG(hw, E1000_PRC64); 1272235783Skib E1000_READ_REG(hw, E1000_PRC127); 1273235783Skib E1000_READ_REG(hw, E1000_PRC255); 1274235783Skib E1000_READ_REG(hw, E1000_PRC511); 1275235783Skib E1000_READ_REG(hw, E1000_PRC1023); 1276235783Skib E1000_READ_REG(hw, E1000_PRC1522); 1277235783Skib E1000_READ_REG(hw, E1000_PTC64); 1278235783Skib E1000_READ_REG(hw, E1000_PTC127); 1279235783Skib E1000_READ_REG(hw, E1000_PTC255); 1280235783Skib E1000_READ_REG(hw, E1000_PTC511); 1281235783Skib E1000_READ_REG(hw, E1000_PTC1023); 1282235783Skib E1000_READ_REG(hw, E1000_PTC1522); 1283235783Skib 1284235783Skib E1000_READ_REG(hw, E1000_ALGNERRC); 1285235783Skib E1000_READ_REG(hw, E1000_RXERRC); 1286235783Skib E1000_READ_REG(hw, E1000_TNCRS); 1287235783Skib E1000_READ_REG(hw, E1000_CEXTERR); 1288235783Skib E1000_READ_REG(hw, E1000_TSCTC); 1289235783Skib E1000_READ_REG(hw, E1000_TSCTFC); 1290235783Skib 1291235783Skib E1000_READ_REG(hw, E1000_MGTPRC); 1292235783Skib E1000_READ_REG(hw, E1000_MGTPDC); 1293235783Skib E1000_READ_REG(hw, E1000_MGTPTC); 1294235783Skib} 1295235783Skib