e1000_82541.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_82541.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36/* e1000_82541 37 * e1000_82547 38 * e1000_82541_rev_2 39 * e1000_82547_rev_2 40 */ 41 42#include "e1000_api.h" 43#include "e1000_82541.h" 44 45STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 48STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw); 49STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw); 50STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 51 u16 *duplex); 52STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 53STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 54STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw); 55STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 56STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 57 bool active); 58STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw); 59STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 60STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 61static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 62 bool link_up); 63static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 64STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 65 66static const u16 e1000_igp_cable_length_table[] = 67 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 68 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 69 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 70 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 71 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 72 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 73 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 74 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 75#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 76 (sizeof(e1000_igp_cable_length_table) / \ 77 sizeof(e1000_igp_cable_length_table[0])) 78 79struct e1000_dev_spec_82541 { 80 e1000_dsp_config dsp_config; 81 e1000_ffe_config ffe_config; 82 u16 spd_default; 83 bool phy_init_script; 84}; 85 86/** 87 * e1000_init_phy_params_82541 - Init PHY func ptrs. 88 * @hw: pointer to the HW structure 89 * 90 * This is a function pointer entry point called by the api module. 91 **/ 92STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_82541"); 99 100 phy->addr = 1; 101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 102 phy->reset_delay_us = 10000; 103 phy->type = e1000_phy_igp; 104 105 /* Function Pointers */ 106 func->check_polarity = e1000_check_polarity_igp; 107 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 108 func->get_cable_length = e1000_get_cable_length_igp_82541; 109 func->get_cfg_done = e1000_get_cfg_done_generic; 110 func->get_phy_info = e1000_get_phy_info_igp; 111 func->read_phy_reg = e1000_read_phy_reg_igp; 112 func->reset_phy = e1000_phy_hw_reset_82541; 113 func->set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 114 func->write_phy_reg = e1000_write_phy_reg_igp; 115 func->power_up_phy = e1000_power_up_phy_copper; 116 func->power_down_phy = e1000_power_down_phy_copper_82541; 117 118 ret_val = e1000_get_phy_id(hw); 119 if (ret_val) 120 goto out; 121 122 /* Verify phy id */ 123 if (phy->id != IGP01E1000_I_PHY_ID) { 124 ret_val = -E1000_ERR_PHY; 125 goto out; 126 } 127 128out: 129 return ret_val; 130} 131 132/** 133 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 134 * @hw: pointer to the HW structure 135 * 136 * This is a function pointer entry point called by the api module. 137 **/ 138STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 139{ 140 struct e1000_nvm_info *nvm = &hw->nvm; 141 struct e1000_functions *func = &hw->func; 142 s32 ret_val = E1000_SUCCESS; 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144 u16 size; 145 146 DEBUGFUNC("e1000_init_nvm_params_82541"); 147 148 switch (nvm->override) { 149 case e1000_nvm_override_spi_large: 150 nvm->type = e1000_nvm_eeprom_spi; 151 eecd |= E1000_EECD_ADDR_BITS; 152 break; 153 case e1000_nvm_override_spi_small: 154 nvm->type = e1000_nvm_eeprom_spi; 155 eecd &= ~E1000_EECD_ADDR_BITS; 156 break; 157 case e1000_nvm_override_microwire_large: 158 nvm->type = e1000_nvm_eeprom_microwire; 159 eecd |= E1000_EECD_SIZE; 160 break; 161 case e1000_nvm_override_microwire_small: 162 nvm->type = e1000_nvm_eeprom_microwire; 163 eecd &= ~E1000_EECD_SIZE; 164 break; 165 default: 166 nvm->type = eecd & E1000_EECD_TYPE 167 ? e1000_nvm_eeprom_spi 168 : e1000_nvm_eeprom_microwire; 169 break; 170 } 171 172 if (nvm->type == e1000_nvm_eeprom_spi) { 173 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 174 ? 16 : 8; 175 nvm->delay_usec = 1; 176 nvm->opcode_bits = 8; 177 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 178 ? 32 : 8; 179 180 /* Function Pointers */ 181 func->acquire_nvm = e1000_acquire_nvm_generic; 182 func->read_nvm = e1000_read_nvm_spi; 183 func->release_nvm = e1000_release_nvm_generic; 184 func->update_nvm = e1000_update_nvm_checksum_generic; 185 func->valid_led_default = e1000_valid_led_default_generic; 186 func->validate_nvm = e1000_validate_nvm_checksum_generic; 187 func->write_nvm = e1000_write_nvm_spi; 188 189 /* 190 * nvm->word_size must be discovered after the pointers 191 * are set so we can verify the size from the nvm image 192 * itself. Temporarily set it to a dummy value so the 193 * read will work. 194 */ 195 nvm->word_size = 64; 196 ret_val = e1000_read_nvm(hw, NVM_CFG, 1, &size); 197 if (ret_val) 198 goto out; 199 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 200 /* 201 * if size != 0, it can be added to a constant and become 202 * the left-shift value to set the word_size. Otherwise, 203 * word_size stays at 64. 204 */ 205 if (size) { 206 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 207 nvm->word_size = 1 << size; 208 } 209 } else { 210 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 211 ? 8 : 6; 212 nvm->delay_usec = 50; 213 nvm->opcode_bits = 3; 214 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 215 ? 256 : 64; 216 217 /* Function Pointers */ 218 func->acquire_nvm = e1000_acquire_nvm_generic; 219 func->read_nvm = e1000_read_nvm_microwire; 220 func->release_nvm = e1000_release_nvm_generic; 221 func->update_nvm = e1000_update_nvm_checksum_generic; 222 func->valid_led_default = e1000_valid_led_default_generic; 223 func->validate_nvm = e1000_validate_nvm_checksum_generic; 224 func->write_nvm = e1000_write_nvm_microwire; 225 } 226 227out: 228 return ret_val; 229} 230 231/** 232 * e1000_init_mac_params_82541 - Init MAC func ptrs. 233 * @hw: pointer to the HW structure 234 * 235 * This is a function pointer entry point called by the api module. 236 **/ 237STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 238{ 239 struct e1000_mac_info *mac = &hw->mac; 240 struct e1000_functions *func = &hw->func; 241 s32 ret_val; 242 243 DEBUGFUNC("e1000_init_mac_params_82541"); 244 245 /* Set media type */ 246 hw->phy.media_type = e1000_media_type_copper; 247 /* Set mta register count */ 248 mac->mta_reg_count = 128; 249 /* Set rar entry count */ 250 mac->rar_entry_count = E1000_RAR_ENTRIES; 251 /* Set if part includes ASF firmware */ 252 mac->asf_firmware_present = TRUE; 253 254 /* Function Pointers */ 255 256 /* bus type/speed/width */ 257 func->get_bus_info = e1000_get_bus_info_pci_generic; 258 /* reset */ 259 func->reset_hw = e1000_reset_hw_82541; 260 /* hw initialization */ 261 func->init_hw = e1000_init_hw_82541; 262 /* link setup */ 263 func->setup_link = e1000_setup_link_generic; 264 /* physical interface link setup */ 265 func->setup_physical_interface = e1000_setup_copper_link_82541; 266 /* check for link */ 267 func->check_for_link = e1000_check_for_link_82541; 268 /* link info */ 269 func->get_link_up_info = e1000_get_link_up_info_82541; 270 /* multicast address update */ 271 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 272 /* writing VFTA */ 273 func->write_vfta = e1000_write_vfta_generic; 274 /* clearing VFTA */ 275 func->clear_vfta = e1000_clear_vfta_generic; 276 /* setting MTA */ 277 func->mta_set = e1000_mta_set_generic; 278 /* setup LED */ 279 func->setup_led = e1000_setup_led_82541; 280 /* cleanup LED */ 281 func->cleanup_led = e1000_cleanup_led_82541; 282 /* turn on/off LED */ 283 func->led_on = e1000_led_on_generic; 284 func->led_off = e1000_led_off_generic; 285 /* remove device */ 286 func->remove_device = e1000_remove_device_generic; 287 /* clear hardware counters */ 288 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 289 290 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82541); 291 292 /* Device-specific structure allocation */ 293 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 294 295 return ret_val; 296} 297 298/** 299 * e1000_init_function_pointers_82541 - Init func ptrs. 300 * @hw: pointer to the HW structure 301 * 302 * The only function explicitly called by the api module to initialize 303 * all function pointers and parameters. 304 **/ 305void e1000_init_function_pointers_82541(struct e1000_hw *hw) 306{ 307 DEBUGFUNC("e1000_init_function_pointers_82541"); 308 309 hw->func.init_mac_params = e1000_init_mac_params_82541; 310 hw->func.init_nvm_params = e1000_init_nvm_params_82541; 311 hw->func.init_phy_params = e1000_init_phy_params_82541; 312} 313 314/** 315 * e1000_reset_hw_82541 - Reset hardware 316 * @hw: pointer to the HW structure 317 * 318 * This resets the hardware into a known state. This is a 319 * function pointer entry point called by the api module. 320 **/ 321STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw) 322{ 323 u32 ledctl, ctrl, icr, manc; 324 325 DEBUGFUNC("e1000_reset_hw_82541"); 326 327 DEBUGOUT("Masking off all interrupts\n"); 328 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 329 330 E1000_WRITE_REG(hw, E1000_RCTL, 0); 331 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 332 E1000_WRITE_FLUSH(hw); 333 334 /* 335 * Delay to allow any outstanding PCI transactions to complete 336 * before resetting the device. 337 */ 338 msec_delay(10); 339 340 ctrl = E1000_READ_REG(hw, E1000_CTRL); 341 342 /* Must reset the Phy before resetting the MAC */ 343 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 344 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 345 msec_delay(5); 346 } 347 348 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 349 switch (hw->mac.type) { 350 case e1000_82541: 351 case e1000_82541_rev_2: 352 /* 353 * These controllers can't ack the 64-bit write when 354 * issuing the reset, so we use IO-mapping as a 355 * workaround to issue the reset. 356 */ 357 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 358 break; 359 default: 360 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 361 break; 362 } 363 364 /* Wait for NVM reload */ 365 msec_delay(20); 366 367 /* Disable HW ARPs on ASF enabled adapters */ 368 manc = E1000_READ_REG(hw, E1000_MANC); 369 manc &= ~E1000_MANC_ARP_EN; 370 E1000_WRITE_REG(hw, E1000_MANC, manc); 371 372 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 373 e1000_phy_init_script_82541(hw); 374 375 /* Configure activity LED after Phy reset */ 376 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 377 ledctl &= IGP_ACTIVITY_LED_MASK; 378 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 379 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 380 } 381 382 /* Once again, mask the interrupts */ 383 DEBUGOUT("Masking off all interrupts\n"); 384 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 385 386 /* Clear any pending interrupt events. */ 387 icr = E1000_READ_REG(hw, E1000_ICR); 388 389 return E1000_SUCCESS; 390} 391 392/** 393 * e1000_init_hw_82541 - Initialize hardware 394 * @hw: pointer to the HW structure 395 * 396 * This inits the hardware readying it for operation. This is a 397 * function pointer entry point called by the api module. 398 **/ 399STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw) 400{ 401 struct e1000_mac_info *mac = &hw->mac; 402 u32 i, txdctl; 403 s32 ret_val; 404 405 DEBUGFUNC("e1000_init_hw_82541"); 406 407 /* Initialize identification LED */ 408 ret_val = e1000_id_led_init_generic(hw); 409 if (ret_val) { 410 DEBUGOUT("Error initializing identification LED\n"); 411 /* This is not fatal and we should not stop init due to this */ 412 } 413 414 /* Disabling VLAN filtering */ 415 DEBUGOUT("Initializing the IEEE VLAN\n"); 416 e1000_clear_vfta(hw); 417 418 /* Setup the receive address. */ 419 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 420 421 /* Zero out the Multicast HASH table */ 422 DEBUGOUT("Zeroing the MTA\n"); 423 for (i = 0; i < mac->mta_reg_count; i++) { 424 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 425 /* 426 * Avoid back to back register writes by adding the register 427 * read (flush). This is to protect against some strange 428 * bridge configurations that may issue Memory Write Block 429 * (MWB) to our register space. 430 */ 431 E1000_WRITE_FLUSH(hw); 432 } 433 434 /* Setup link and flow control */ 435 ret_val = e1000_setup_link(hw); 436 437 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 438 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 439 E1000_TXDCTL_FULL_TX_DESC_WB; 440 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 441 442 /* 443 * Clear all of the statistics registers (clear on read). It is 444 * important that we do this after we have tried to establish link 445 * because the symbol error count will increment wildly if there 446 * is no link. 447 */ 448 e1000_clear_hw_cntrs_82541(hw); 449 450 return ret_val; 451} 452 453/** 454 * e1000_get_link_up_info_82541 - Report speed and duplex 455 * @hw: pointer to the HW structure 456 * @speed: pointer to speed buffer 457 * @duplex: pointer to duplex buffer 458 * 459 * Retrieve the current speed and duplex configuration. 460 * This is a function pointer entry point called by the api module. 461 **/ 462STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 463 u16 *duplex) 464{ 465 struct e1000_phy_info *phy = &hw->phy; 466 s32 ret_val; 467 u16 data; 468 469 DEBUGFUNC("e1000_get_link_up_info_82541"); 470 471 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 472 if (ret_val) 473 goto out; 474 475 if (!phy->speed_downgraded) 476 goto out; 477 478 /* 479 * IGP01 PHY may advertise full duplex operation after speed 480 * downgrade even if it is operating at half duplex. 481 * Here we set the duplex settings to match the duplex in the 482 * link partner's capabilities. 483 */ 484 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &data); 485 if (ret_val) 486 goto out; 487 488 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 489 *duplex = HALF_DUPLEX; 490 } else { 491 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &data); 492 if (ret_val) 493 goto out; 494 495 if (*speed == SPEED_100) { 496 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 497 *duplex = HALF_DUPLEX; 498 } else if (*speed == SPEED_10) { 499 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 500 *duplex = HALF_DUPLEX; 501 } 502 } 503 504out: 505 return ret_val; 506} 507 508/** 509 * e1000_phy_hw_reset_82541 - PHY hardware reset 510 * @hw: pointer to the HW structure 511 * 512 * Verify the reset block is not blocking us from resetting. Acquire 513 * semaphore (if necessary) and read/set/write the device control reset 514 * bit in the PHY. Wait the appropriate delay time for the device to 515 * reset and release the semaphore (if necessary). 516 * This is a function pointer entry point called by the api module. 517 **/ 518STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 519{ 520 s32 ret_val; 521 u32 ledctl; 522 523 DEBUGFUNC("e1000_phy_hw_reset_82541"); 524 525 ret_val = e1000_phy_hw_reset_generic(hw); 526 if (ret_val) 527 goto out; 528 529 e1000_phy_init_script_82541(hw); 530 531 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 532 /* Configure activity LED after PHY reset */ 533 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 534 ledctl &= IGP_ACTIVITY_LED_MASK; 535 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 536 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 537 } 538 539out: 540 return ret_val; 541} 542 543/** 544 * e1000_setup_copper_link_82541 - Configure copper link settings 545 * @hw: pointer to the HW structure 546 * 547 * Calls the appropriate function to configure the link for auto-neg or forced 548 * speed and duplex. Then we check for link, once link is established calls 549 * to configure collision distance and flow control are called. If link is 550 * not established, we return -E1000_ERR_PHY (-2). This is a function 551 * pointer entry point called by the api module. 552 **/ 553STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 554{ 555 struct e1000_phy_info *phy = &hw->phy; 556 struct e1000_dev_spec_82541 *dev_spec; 557 s32 ret_val; 558 u32 ctrl, ledctl; 559 560 DEBUGFUNC("e1000_setup_copper_link_82541"); 561 562 ctrl = E1000_READ_REG(hw, E1000_CTRL); 563 ctrl |= E1000_CTRL_SLU; 564 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 565 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 566 567 hw->phy.reset_disable = FALSE; 568 569 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 570 571 /* Earlier revs of the IGP phy require us to force MDI. */ 572 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 573 dev_spec->dsp_config = e1000_dsp_config_disabled; 574 phy->mdix = 1; 575 } else { 576 dev_spec->dsp_config = e1000_dsp_config_enabled; 577 } 578 579 ret_val = e1000_copper_link_setup_igp(hw); 580 if (ret_val) 581 goto out; 582 583 if (hw->mac.autoneg) { 584 if (dev_spec->ffe_config == e1000_ffe_config_active) 585 dev_spec->ffe_config = e1000_ffe_config_enabled; 586 } 587 588 /* Configure activity LED after Phy reset */ 589 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 590 ledctl &= IGP_ACTIVITY_LED_MASK; 591 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 592 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 593 594 ret_val = e1000_setup_copper_link_generic(hw); 595 596out: 597 return ret_val; 598} 599 600/** 601 * e1000_check_for_link_82541 - Check/Store link connection 602 * @hw: pointer to the HW structure 603 * 604 * This checks the link condition of the adapter and stores the 605 * results in the hw->mac structure. This is a function pointer entry 606 * point called by the api module. 607 **/ 608STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw) 609{ 610 struct e1000_mac_info *mac = &hw->mac; 611 s32 ret_val; 612 bool link; 613 614 DEBUGFUNC("e1000_check_for_link_82541"); 615 616 /* 617 * We only want to go out to the PHY registers to see if Auto-Neg 618 * has completed and/or if our link status has changed. The 619 * get_link_status flag is set upon receiving a Link Status 620 * Change or Rx Sequence Error interrupt. 621 */ 622 if (!mac->get_link_status) { 623 ret_val = E1000_SUCCESS; 624 goto out; 625 } 626 627 /* 628 * First we want to see if the MII Status Register reports 629 * link. If so, then we want to get the current speed/duplex 630 * of the PHY. 631 */ 632 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 633 if (ret_val) 634 goto out; 635 636 if (!link) { 637 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 638 goto out; /* No link detected */ 639 } 640 641 mac->get_link_status = FALSE; 642 643 /* 644 * Check if there was DownShift, must be checked 645 * immediately after link-up 646 */ 647 e1000_check_downshift_generic(hw); 648 649 /* 650 * If we are forcing speed/duplex, then we simply return since 651 * we have already determined whether we have link or not. 652 */ 653 if (!mac->autoneg) { 654 ret_val = -E1000_ERR_CONFIG; 655 goto out; 656 } 657 658 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 659 660 /* 661 * Auto-Neg is enabled. Auto Speed Detection takes care 662 * of MAC speed/duplex configuration. So we only need to 663 * configure Collision Distance in the MAC. 664 */ 665 e1000_config_collision_dist_generic(hw); 666 667 /* 668 * Configure Flow Control now that Auto-Neg has completed. 669 * First, we need to restore the desired flow control 670 * settings because we may have had to re-autoneg with a 671 * different link partner. 672 */ 673 ret_val = e1000_config_fc_after_link_up_generic(hw); 674 if (ret_val) { 675 DEBUGOUT("Error configuring flow control\n"); 676 } 677 678out: 679 return ret_val; 680} 681 682/** 683 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 684 * @hw: pointer to the HW structure 685 * @link_up: boolean flag for link up status 686 * 687 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 688 * at any other case. 689 * 690 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 691 * gigabit link is achieved to improve link quality. 692 * This is a function pointer entry point called by the api module. 693 **/ 694static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 695 bool link_up) 696{ 697 struct e1000_phy_info *phy = &hw->phy; 698 struct e1000_dev_spec_82541 *dev_spec; 699 s32 ret_val; 700 u32 idle_errs = 0; 701 u16 phy_data, phy_saved_data, speed, duplex, i; 702 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 703 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 704 {IGP01E1000_PHY_AGC_PARAM_A, 705 IGP01E1000_PHY_AGC_PARAM_B, 706 IGP01E1000_PHY_AGC_PARAM_C, 707 IGP01E1000_PHY_AGC_PARAM_D}; 708 709 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 710 711 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 712 713 if (link_up) { 714 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 715 if (ret_val) { 716 DEBUGOUT("Error getting link speed and duplex\n"); 717 goto out; 718 } 719 720 if (speed != SPEED_1000) { 721 ret_val = E1000_SUCCESS; 722 goto out; 723 } 724 725 ret_val = e1000_get_cable_length(hw); 726 if (ret_val) 727 goto out; 728 729 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 730 phy->min_cable_length >= 50) { 731 732 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 733 ret_val = e1000_read_phy_reg(hw, 734 dsp_reg_array[i], 735 &phy_data); 736 if (ret_val) 737 goto out; 738 739 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 740 741 ret_val = e1000_write_phy_reg(hw, 742 dsp_reg_array[i], 743 phy_data); 744 if (ret_val) 745 goto out; 746 } 747 dev_spec->dsp_config = e1000_dsp_config_activated; 748 } 749 750 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 751 (phy->min_cable_length >= 50)) { 752 ret_val = E1000_SUCCESS; 753 goto out; 754 } 755 756 /* clear previous idle error counts */ 757 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 758 if (ret_val) 759 goto out; 760 761 for (i = 0; i < ffe_idle_err_timeout; i++) { 762 usec_delay(1000); 763 ret_val = e1000_read_phy_reg(hw, 764 PHY_1000T_STATUS, 765 &phy_data); 766 if (ret_val) 767 goto out; 768 769 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 770 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 771 dev_spec->ffe_config = e1000_ffe_config_active; 772 773 ret_val = e1000_write_phy_reg(hw, 774 IGP01E1000_PHY_DSP_FFE, 775 IGP01E1000_PHY_DSP_FFE_CM_CP); 776 if (ret_val) 777 goto out; 778 break; 779 } 780 781 if (idle_errs) 782 ffe_idle_err_timeout = 783 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 784 } 785 } else { 786 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 787 /* 788 * Save off the current value of register 0x2F5B 789 * to be restored at the end of the routines. 790 */ 791 ret_val = e1000_read_phy_reg(hw, 792 0x2F5B, 793 &phy_saved_data); 794 if (ret_val) 795 goto out; 796 797 /* Disable the PHY transmitter */ 798 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 799 if (ret_val) 800 goto out; 801 802 msec_delay_irq(20); 803 804 ret_val = e1000_write_phy_reg(hw, 805 0x0000, 806 IGP01E1000_IEEE_FORCE_GIG); 807 if (ret_val) 808 goto out; 809 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 810 ret_val = e1000_read_phy_reg(hw, 811 dsp_reg_array[i], 812 &phy_data); 813 if (ret_val) 814 goto out; 815 816 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 817 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 818 819 ret_val = e1000_write_phy_reg(hw, 820 dsp_reg_array[i], 821 phy_data); 822 if (ret_val) 823 goto out; 824 } 825 826 ret_val = e1000_write_phy_reg(hw, 827 0x0000, 828 IGP01E1000_IEEE_RESTART_AUTONEG); 829 if (ret_val) 830 goto out; 831 832 msec_delay_irq(20); 833 834 /* Now enable the transmitter */ 835 ret_val = e1000_write_phy_reg(hw, 836 0x2F5B, 837 phy_saved_data); 838 if (ret_val) 839 goto out; 840 841 dev_spec->dsp_config = e1000_dsp_config_enabled; 842 } 843 844 if (dev_spec->ffe_config != e1000_ffe_config_active) { 845 ret_val = E1000_SUCCESS; 846 goto out; 847 } 848 849 /* 850 * Save off the current value of register 0x2F5B 851 * to be restored at the end of the routines. 852 */ 853 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 854 if (ret_val) 855 goto out; 856 857 /* Disable the PHY transmitter */ 858 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 859 if (ret_val) 860 goto out; 861 862 msec_delay_irq(20); 863 864 ret_val = e1000_write_phy_reg(hw, 865 0x0000, 866 IGP01E1000_IEEE_FORCE_GIG); 867 if (ret_val) 868 goto out; 869 870 ret_val = e1000_write_phy_reg(hw, 871 IGP01E1000_PHY_DSP_FFE, 872 IGP01E1000_PHY_DSP_FFE_DEFAULT); 873 if (ret_val) 874 goto out; 875 876 ret_val = e1000_write_phy_reg(hw, 877 0x0000, 878 IGP01E1000_IEEE_RESTART_AUTONEG); 879 if (ret_val) 880 goto out; 881 882 msec_delay_irq(20); 883 884 /* Now enable the transmitter */ 885 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 886 887 if (ret_val) 888 goto out; 889 890 dev_spec->ffe_config = e1000_ffe_config_enabled; 891 } 892 893out: 894 return ret_val; 895} 896 897/** 898 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 899 * @hw: pointer to the HW structure 900 * 901 * The automatic gain control (agc) normalizes the amplitude of the 902 * received signal, adjusting for the attenuation produced by the 903 * cable. By reading the AGC registers, which represent the 904 * combination of coarse and fine gain value, the value can be put 905 * into a lookup table to obtain the approximate cable length 906 * for each channel. This is a function pointer entry point called by the 907 * api module. 908 **/ 909STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 910{ 911 struct e1000_phy_info *phy = &hw->phy; 912 s32 ret_val = E1000_SUCCESS; 913 u16 i, data; 914 u16 cur_agc_value, agc_value = 0; 915 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 916 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 917 {IGP01E1000_PHY_AGC_A, 918 IGP01E1000_PHY_AGC_B, 919 IGP01E1000_PHY_AGC_C, 920 IGP01E1000_PHY_AGC_D}; 921 922 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 923 924 /* Read the AGC registers for all channels */ 925 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 926 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &data); 927 if (ret_val) 928 goto out; 929 930 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 931 932 /* Bounds checking */ 933 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 934 (cur_agc_value == 0)) { 935 ret_val = -E1000_ERR_PHY; 936 goto out; 937 } 938 939 agc_value += cur_agc_value; 940 941 if (min_agc_value > cur_agc_value) 942 min_agc_value = cur_agc_value; 943 } 944 945 /* Remove the minimal AGC result for length < 50m */ 946 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 947 agc_value -= min_agc_value; 948 /* Average the three remaining channels for the length. */ 949 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 950 } else { 951 /* Average the channels for the length. */ 952 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 953 } 954 955 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 956 IGP01E1000_AGC_RANGE) 957 ? (e1000_igp_cable_length_table[agc_value] - 958 IGP01E1000_AGC_RANGE) 959 : 0; 960 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 961 IGP01E1000_AGC_RANGE; 962 963 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 964 965out: 966 return ret_val; 967} 968 969/** 970 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 971 * @hw: pointer to the HW structure 972 * @active: boolean used to enable/disable lplu 973 * 974 * Success returns 0, Failure returns 1 975 * 976 * The low power link up (lplu) state is set to the power management level D3 977 * and SmartSpeed is disabled when active is true, else clear lplu for D3 978 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 979 * is used during Dx states where the power conservation is most important. 980 * During driver activity, SmartSpeed should be enabled so performance is 981 * maintained. This is a function pointer entry point called by the 982 * api module. 983 **/ 984STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 985{ 986 struct e1000_phy_info *phy = &hw->phy; 987 s32 ret_val; 988 u16 data; 989 990 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 991 992 switch (hw->mac.type) { 993 case e1000_82541_rev_2: 994 case e1000_82547_rev_2: 995 break; 996 default: 997 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 998 goto out; 999 break; 1000 } 1001 1002 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &data); 1003 if (ret_val) 1004 goto out; 1005 1006 if (!active) { 1007 data &= ~IGP01E1000_GMII_FLEX_SPD; 1008 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1009 if (ret_val) 1010 goto out; 1011 1012 /* 1013 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1014 * during Dx states where the power conservation is most 1015 * important. During driver activity we should enable 1016 * SmartSpeed, so performance is maintained. 1017 */ 1018 if (phy->smart_speed == e1000_smart_speed_on) { 1019 ret_val = e1000_read_phy_reg(hw, 1020 IGP01E1000_PHY_PORT_CONFIG, 1021 &data); 1022 if (ret_val) 1023 goto out; 1024 1025 data |= IGP01E1000_PSCFR_SMART_SPEED; 1026 ret_val = e1000_write_phy_reg(hw, 1027 IGP01E1000_PHY_PORT_CONFIG, 1028 data); 1029 if (ret_val) 1030 goto out; 1031 } else if (phy->smart_speed == e1000_smart_speed_off) { 1032 ret_val = e1000_read_phy_reg(hw, 1033 IGP01E1000_PHY_PORT_CONFIG, 1034 &data); 1035 if (ret_val) 1036 goto out; 1037 1038 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1039 ret_val = e1000_write_phy_reg(hw, 1040 IGP01E1000_PHY_PORT_CONFIG, 1041 data); 1042 if (ret_val) 1043 goto out; 1044 } 1045 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1046 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1047 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1048 data |= IGP01E1000_GMII_FLEX_SPD; 1049 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1050 if (ret_val) 1051 goto out; 1052 1053 /* When LPLU is enabled, we should disable SmartSpeed */ 1054 ret_val = e1000_read_phy_reg(hw, 1055 IGP01E1000_PHY_PORT_CONFIG, 1056 &data); 1057 if (ret_val) 1058 goto out; 1059 1060 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1061 ret_val = e1000_write_phy_reg(hw, 1062 IGP01E1000_PHY_PORT_CONFIG, 1063 data); 1064 } 1065 1066out: 1067 return ret_val; 1068} 1069 1070/** 1071 * e1000_setup_led_82541 - Configures SW controllable LED 1072 * @hw: pointer to the HW structure 1073 * 1074 * This prepares the SW controllable LED for use and saves the current state 1075 * of the LED so it can be later restored. This is a function pointer entry 1076 * point called by the api module. 1077 **/ 1078STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw) 1079{ 1080 struct e1000_dev_spec_82541 *dev_spec; 1081 s32 ret_val; 1082 1083 DEBUGFUNC("e1000_setup_led_82541"); 1084 1085 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1086 1087 ret_val = e1000_read_phy_reg(hw, 1088 IGP01E1000_GMII_FIFO, 1089 &dev_spec->spd_default); 1090 if (ret_val) 1091 goto out; 1092 1093 ret_val = e1000_write_phy_reg(hw, 1094 IGP01E1000_GMII_FIFO, 1095 (u16)(dev_spec->spd_default & 1096 ~IGP01E1000_GMII_SPD)); 1097 if (ret_val) 1098 goto out; 1099 1100 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1101 1102out: 1103 return ret_val; 1104} 1105 1106/** 1107 * e1000_cleanup_led_82541 - Set LED config to default operation 1108 * @hw: pointer to the HW structure 1109 * 1110 * Remove the current LED configuration and set the LED configuration 1111 * to the default value, saved from the EEPROM. This is a function pointer 1112 * entry point called by the api module. 1113 **/ 1114STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1115{ 1116 struct e1000_dev_spec_82541 *dev_spec; 1117 s32 ret_val; 1118 1119 DEBUGFUNC("e1000_cleanup_led_82541"); 1120 1121 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1122 1123 ret_val = e1000_write_phy_reg(hw, 1124 IGP01E1000_GMII_FIFO, 1125 dev_spec->spd_default); 1126 if (ret_val) 1127 goto out; 1128 1129 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1130 1131out: 1132 return ret_val; 1133} 1134 1135/** 1136 * e1000_phy_init_script_82541 - Initialize GbE PHY 1137 * @hw: pointer to the HW structure 1138 * 1139 * Initializes the IGP PHY. 1140 **/ 1141static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1142{ 1143 struct e1000_dev_spec_82541 *dev_spec; 1144 u32 ret_val; 1145 u16 phy_saved_data; 1146 1147 DEBUGFUNC("e1000_phy_init_script_82541"); 1148 1149 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1150 1151 if (!dev_spec->phy_init_script) { 1152 ret_val = E1000_SUCCESS; 1153 goto out; 1154 } 1155 1156 /* Delay after phy reset to enable NVM configuration to load */ 1157 msec_delay(20); 1158 1159 /* 1160 * Save off the current value of register 0x2F5B to be restored at 1161 * the end of this routine. 1162 */ 1163 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 1164 1165 /* Disabled the PHY transmitter */ 1166 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 1167 1168 msec_delay(20); 1169 1170 e1000_write_phy_reg(hw, 0x0000, 0x0140); 1171 1172 msec_delay(5); 1173 1174 switch (hw->mac.type) { 1175 case e1000_82541: 1176 case e1000_82547: 1177 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 1178 1179 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 1180 1181 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 1182 1183 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 1184 1185 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 1186 1187 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 1188 1189 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 1190 1191 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 1192 1193 e1000_write_phy_reg(hw, 0x2010, 0x0008); 1194 break; 1195 case e1000_82541_rev_2: 1196 case e1000_82547_rev_2: 1197 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 e1000_write_phy_reg(hw, 0x0000, 0x3300); 1204 1205 msec_delay(20); 1206 1207 /* Now enable the transmitter */ 1208 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 1209 1210 if (hw->mac.type == e1000_82547) { 1211 u16 fused, fine, coarse; 1212 1213 /* Move to analog registers page */ 1214 e1000_read_phy_reg(hw, 1215 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1216 &fused); 1217 1218 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1219 e1000_read_phy_reg(hw, 1220 IGP01E1000_ANALOG_FUSE_STATUS, 1221 &fused); 1222 1223 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1224 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1225 1226 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1227 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1228 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1229 } else if (coarse == 1230 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1231 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1232 1233 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1234 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1235 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1236 1237 e1000_write_phy_reg(hw, 1238 IGP01E1000_ANALOG_FUSE_CONTROL, 1239 fused); 1240 e1000_write_phy_reg(hw, 1241 IGP01E1000_ANALOG_FUSE_BYPASS, 1242 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1243 } 1244 } 1245 1246out: 1247 return ret_val; 1248} 1249 1250/** 1251 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1252 * @hw: pointer to the HW structure 1253 * @state: boolean value used to enable/disable PHY init script 1254 * 1255 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1256 * IGP PHY. This is a function pointer entry point called by the api module. 1257 **/ 1258void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1259{ 1260 struct e1000_dev_spec_82541 *dev_spec; 1261 1262 DEBUGFUNC("e1000_init_script_state_82541"); 1263 1264 if (hw->phy.type != e1000_phy_igp) { 1265 DEBUGOUT("Initialization script not necessary.\n"); 1266 goto out; 1267 } 1268 1269 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1270 1271 if (!dev_spec) { 1272 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1273 goto out; 1274 } 1275 1276 dev_spec->phy_init_script = state; 1277 1278out: 1279 return; 1280} 1281 1282/** 1283 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1284 * @hw: pointer to the HW structure 1285 * 1286 * In the case of a PHY power down to save power, or to turn off link during a 1287 * driver unload, or wake on lan is not enabled, remove the link. 1288 **/ 1289STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1290{ 1291 /* If the management interface is not enabled, then power down */ 1292 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1293 e1000_power_down_phy_copper(hw); 1294 1295 return; 1296} 1297 1298/** 1299 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1300 * @hw: pointer to the HW structure 1301 * 1302 * Clears the hardware counters by reading the counter registers. 1303 **/ 1304STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1305{ 1306 volatile u32 temp; 1307 1308 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1309 1310 e1000_clear_hw_cntrs_base_generic(hw); 1311 1312 temp = E1000_READ_REG(hw, E1000_PRC64); 1313 temp = E1000_READ_REG(hw, E1000_PRC127); 1314 temp = E1000_READ_REG(hw, E1000_PRC255); 1315 temp = E1000_READ_REG(hw, E1000_PRC511); 1316 temp = E1000_READ_REG(hw, E1000_PRC1023); 1317 temp = E1000_READ_REG(hw, E1000_PRC1522); 1318 temp = E1000_READ_REG(hw, E1000_PTC64); 1319 temp = E1000_READ_REG(hw, E1000_PTC127); 1320 temp = E1000_READ_REG(hw, E1000_PTC255); 1321 temp = E1000_READ_REG(hw, E1000_PTC511); 1322 temp = E1000_READ_REG(hw, E1000_PTC1023); 1323 temp = E1000_READ_REG(hw, E1000_PTC1522); 1324 1325 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1326 temp = E1000_READ_REG(hw, E1000_RXERRC); 1327 temp = E1000_READ_REG(hw, E1000_TNCRS); 1328 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1329 temp = E1000_READ_REG(hw, E1000_TSCTC); 1330 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1331 1332 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1333 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1334 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1335} 1336