e1000_82541.c revision 173788
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_82541.c 173788 2007-11-20 21:41:22Z jfv $ */ 34 35 36/* e1000_82541 37 * e1000_82547 38 * e1000_82541_rev_2 39 * e1000_82547_rev_2 40 */ 41 42#include "e1000_api.h" 43#include "e1000_82541.h" 44 45void e1000_init_function_pointers_82541(struct e1000_hw *hw); 46 47STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 48STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 49STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 50STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw); 51STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw); 52STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 53 u16 *duplex); 54STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 55STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 56STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw); 57STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 58STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 59 bool active); 60STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw); 61STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 62STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 63static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64 bool link_up); 65static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 67 68static const u16 e1000_igp_cable_length_table[] = 69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 77#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78 (sizeof(e1000_igp_cable_length_table) / \ 79 sizeof(e1000_igp_cable_length_table[0])) 80 81struct e1000_dev_spec_82541 { 82 e1000_dsp_config dsp_config; 83 e1000_ffe_config ffe_config; 84 u16 spd_default; 85 bool phy_init_script; 86}; 87 88/** 89 * e1000_init_phy_params_82541 - Init PHY func ptrs. 90 * @hw: pointer to the HW structure 91 * 92 * This is a function pointer entry point called by the api module. 93 **/ 94STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 95{ 96 struct e1000_phy_info *phy = &hw->phy; 97 struct e1000_functions *func = &hw->func; 98 s32 ret_val = E1000_SUCCESS; 99 100 DEBUGFUNC("e1000_init_phy_params_82541"); 101 102 phy->addr = 1; 103 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 104 phy->reset_delay_us = 10000; 105 phy->type = e1000_phy_igp; 106 107 /* Function Pointers */ 108 func->check_polarity = e1000_check_polarity_igp; 109 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 110 func->get_cable_length = e1000_get_cable_length_igp_82541; 111 func->get_cfg_done = e1000_get_cfg_done_generic; 112 func->get_phy_info = e1000_get_phy_info_igp; 113 func->read_phy_reg = e1000_read_phy_reg_igp; 114 func->reset_phy = e1000_phy_hw_reset_82541; 115 func->set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 116 func->write_phy_reg = e1000_write_phy_reg_igp; 117 func->power_up_phy = e1000_power_up_phy_copper; 118 func->power_down_phy = e1000_power_down_phy_copper_82541; 119 120 ret_val = e1000_get_phy_id(hw); 121 if (ret_val) 122 goto out; 123 124 /* Verify phy id */ 125 if (phy->id != IGP01E1000_I_PHY_ID) { 126 ret_val = -E1000_ERR_PHY; 127 goto out; 128 } 129 130out: 131 return ret_val; 132} 133 134/** 135 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 136 * @hw: pointer to the HW structure 137 * 138 * This is a function pointer entry point called by the api module. 139 **/ 140STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 141{ 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 struct e1000_functions *func = &hw->func; 144 s32 ret_val = E1000_SUCCESS; 145 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 146 u16 size; 147 148 DEBUGFUNC("e1000_init_nvm_params_82541"); 149 150 switch (nvm->override) { 151 case e1000_nvm_override_spi_large: 152 nvm->type = e1000_nvm_eeprom_spi; 153 eecd |= E1000_EECD_ADDR_BITS; 154 break; 155 case e1000_nvm_override_spi_small: 156 nvm->type = e1000_nvm_eeprom_spi; 157 eecd &= ~E1000_EECD_ADDR_BITS; 158 break; 159 case e1000_nvm_override_microwire_large: 160 nvm->type = e1000_nvm_eeprom_microwire; 161 eecd |= E1000_EECD_SIZE; 162 break; 163 case e1000_nvm_override_microwire_small: 164 nvm->type = e1000_nvm_eeprom_microwire; 165 eecd &= ~E1000_EECD_SIZE; 166 break; 167 default: 168 nvm->type = eecd & E1000_EECD_TYPE 169 ? e1000_nvm_eeprom_spi 170 : e1000_nvm_eeprom_microwire; 171 break; 172 } 173 174 if (nvm->type == e1000_nvm_eeprom_spi) { 175 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 176 ? 16 : 8; 177 nvm->delay_usec = 1; 178 nvm->opcode_bits = 8; 179 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 180 ? 32 : 8; 181 182 /* Function Pointers */ 183 func->acquire_nvm = e1000_acquire_nvm_generic; 184 func->read_nvm = e1000_read_nvm_spi; 185 func->release_nvm = e1000_release_nvm_generic; 186 func->update_nvm = e1000_update_nvm_checksum_generic; 187 func->valid_led_default = e1000_valid_led_default_generic; 188 func->validate_nvm = e1000_validate_nvm_checksum_generic; 189 func->write_nvm = e1000_write_nvm_spi; 190 191 /* 192 * nvm->word_size must be discovered after the pointers 193 * are set so we can verify the size from the nvm image 194 * itself. Temporarily set it to a dummy value so the 195 * read will work. 196 */ 197 nvm->word_size = 64; 198 ret_val = e1000_read_nvm(hw, NVM_CFG, 1, &size); 199 if (ret_val) 200 goto out; 201 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 202 /* 203 * if size != 0, it can be added to a constant and become 204 * the left-shift value to set the word_size. Otherwise, 205 * word_size stays at 64. 206 */ 207 if (size) { 208 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 209 nvm->word_size = 1 << size; 210 } 211 } else { 212 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 213 ? 8 : 6; 214 nvm->delay_usec = 50; 215 nvm->opcode_bits = 3; 216 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 217 ? 256 : 64; 218 219 /* Function Pointers */ 220 func->acquire_nvm = e1000_acquire_nvm_generic; 221 func->read_nvm = e1000_read_nvm_microwire; 222 func->release_nvm = e1000_release_nvm_generic; 223 func->update_nvm = e1000_update_nvm_checksum_generic; 224 func->valid_led_default = e1000_valid_led_default_generic; 225 func->validate_nvm = e1000_validate_nvm_checksum_generic; 226 func->write_nvm = e1000_write_nvm_microwire; 227 } 228 229out: 230 return ret_val; 231} 232 233/** 234 * e1000_init_mac_params_82541 - Init MAC func ptrs. 235 * @hw: pointer to the HW structure 236 * 237 * This is a function pointer entry point called by the api module. 238 **/ 239STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 240{ 241 struct e1000_mac_info *mac = &hw->mac; 242 struct e1000_functions *func = &hw->func; 243 s32 ret_val; 244 245 DEBUGFUNC("e1000_init_mac_params_82541"); 246 247 /* Set media type */ 248 hw->phy.media_type = e1000_media_type_copper; 249 /* Set mta register count */ 250 mac->mta_reg_count = 128; 251 /* Set rar entry count */ 252 mac->rar_entry_count = E1000_RAR_ENTRIES; 253 /* Set if part includes ASF firmware */ 254 mac->asf_firmware_present = TRUE; 255 256 /* Function Pointers */ 257 258 /* bus type/speed/width */ 259 func->get_bus_info = e1000_get_bus_info_pci_generic; 260 /* reset */ 261 func->reset_hw = e1000_reset_hw_82541; 262 /* hw initialization */ 263 func->init_hw = e1000_init_hw_82541; 264 /* link setup */ 265 func->setup_link = e1000_setup_link_generic; 266 /* physical interface link setup */ 267 func->setup_physical_interface = e1000_setup_copper_link_82541; 268 /* check for link */ 269 func->check_for_link = e1000_check_for_link_82541; 270 /* link info */ 271 func->get_link_up_info = e1000_get_link_up_info_82541; 272 /* multicast address update */ 273 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 274 /* writing VFTA */ 275 func->write_vfta = e1000_write_vfta_generic; 276 /* clearing VFTA */ 277 func->clear_vfta = e1000_clear_vfta_generic; 278 /* setting MTA */ 279 func->mta_set = e1000_mta_set_generic; 280 /* setup LED */ 281 func->setup_led = e1000_setup_led_82541; 282 /* cleanup LED */ 283 func->cleanup_led = e1000_cleanup_led_82541; 284 /* turn on/off LED */ 285 func->led_on = e1000_led_on_generic; 286 func->led_off = e1000_led_off_generic; 287 /* remove device */ 288 func->remove_device = e1000_remove_device_generic; 289 /* clear hardware counters */ 290 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 291 292 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82541); 293 294 /* Device-specific structure allocation */ 295 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 296 297 return ret_val; 298} 299 300/** 301 * e1000_init_function_pointers_82541 - Init func ptrs. 302 * @hw: pointer to the HW structure 303 * 304 * The only function explicitly called by the api module to initialize 305 * all function pointers and parameters. 306 **/ 307void e1000_init_function_pointers_82541(struct e1000_hw *hw) 308{ 309 DEBUGFUNC("e1000_init_function_pointers_82541"); 310 311 hw->func.init_mac_params = e1000_init_mac_params_82541; 312 hw->func.init_nvm_params = e1000_init_nvm_params_82541; 313 hw->func.init_phy_params = e1000_init_phy_params_82541; 314} 315 316/** 317 * e1000_reset_hw_82541 - Reset hardware 318 * @hw: pointer to the HW structure 319 * 320 * This resets the hardware into a known state. This is a 321 * function pointer entry point called by the api module. 322 **/ 323STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw) 324{ 325 u32 ledctl, ctrl, icr, manc; 326 327 DEBUGFUNC("e1000_reset_hw_82541"); 328 329 DEBUGOUT("Masking off all interrupts\n"); 330 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 331 332 E1000_WRITE_REG(hw, E1000_RCTL, 0); 333 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 334 E1000_WRITE_FLUSH(hw); 335 336 /* 337 * Delay to allow any outstanding PCI transactions to complete 338 * before resetting the device. 339 */ 340 msec_delay(10); 341 342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 343 344 /* Must reset the Phy before resetting the MAC */ 345 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 346 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 347 msec_delay(5); 348 } 349 350 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 351 switch (hw->mac.type) { 352 case e1000_82541: 353 case e1000_82541_rev_2: 354 /* 355 * These controllers can't ack the 64-bit write when 356 * issuing the reset, so we use IO-mapping as a 357 * workaround to issue the reset. 358 */ 359 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 360 break; 361 default: 362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 363 break; 364 } 365 366 /* Wait for NVM reload */ 367 msec_delay(20); 368 369 /* Disable HW ARPs on ASF enabled adapters */ 370 manc = E1000_READ_REG(hw, E1000_MANC); 371 manc &= ~E1000_MANC_ARP_EN; 372 E1000_WRITE_REG(hw, E1000_MANC, manc); 373 374 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 375 e1000_phy_init_script_82541(hw); 376 377 /* Configure activity LED after Phy reset */ 378 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 379 ledctl &= IGP_ACTIVITY_LED_MASK; 380 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 381 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 382 } 383 384 /* Once again, mask the interrupts */ 385 DEBUGOUT("Masking off all interrupts\n"); 386 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 387 388 /* Clear any pending interrupt events. */ 389 icr = E1000_READ_REG(hw, E1000_ICR); 390 391 return E1000_SUCCESS; 392} 393 394/** 395 * e1000_init_hw_82541 - Initialize hardware 396 * @hw: pointer to the HW structure 397 * 398 * This inits the hardware readying it for operation. This is a 399 * function pointer entry point called by the api module. 400 **/ 401STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw) 402{ 403 struct e1000_mac_info *mac = &hw->mac; 404 u32 i, txdctl; 405 s32 ret_val; 406 407 DEBUGFUNC("e1000_init_hw_82541"); 408 409 /* Initialize identification LED */ 410 ret_val = e1000_id_led_init_generic(hw); 411 if (ret_val) { 412 DEBUGOUT("Error initializing identification LED\n"); 413 /* This is not fatal and we should not stop init due to this */ 414 } 415 416 /* Disabling VLAN filtering */ 417 DEBUGOUT("Initializing the IEEE VLAN\n"); 418 e1000_clear_vfta(hw); 419 420 /* Setup the receive address. */ 421 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 422 423 /* Zero out the Multicast HASH table */ 424 DEBUGOUT("Zeroing the MTA\n"); 425 for (i = 0; i < mac->mta_reg_count; i++) { 426 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 427 /* 428 * Avoid back to back register writes by adding the register 429 * read (flush). This is to protect against some strange 430 * bridge configurations that may issue Memory Write Block 431 * (MWB) to our register space. 432 */ 433 E1000_WRITE_FLUSH(hw); 434 } 435 436 /* Setup link and flow control */ 437 ret_val = e1000_setup_link(hw); 438 439 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 440 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 441 E1000_TXDCTL_FULL_TX_DESC_WB; 442 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 443 444 /* 445 * Clear all of the statistics registers (clear on read). It is 446 * important that we do this after we have tried to establish link 447 * because the symbol error count will increment wildly if there 448 * is no link. 449 */ 450 e1000_clear_hw_cntrs_82541(hw); 451 452 return ret_val; 453} 454 455/** 456 * e1000_get_link_up_info_82541 - Report speed and duplex 457 * @hw: pointer to the HW structure 458 * @speed: pointer to speed buffer 459 * @duplex: pointer to duplex buffer 460 * 461 * Retrieve the current speed and duplex configuration. 462 * This is a function pointer entry point called by the api module. 463 **/ 464STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 465 u16 *duplex) 466{ 467 struct e1000_phy_info *phy = &hw->phy; 468 s32 ret_val; 469 u16 data; 470 471 DEBUGFUNC("e1000_get_link_up_info_82541"); 472 473 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 474 if (ret_val) 475 goto out; 476 477 if (!phy->speed_downgraded) 478 goto out; 479 480 /* 481 * IGP01 PHY may advertise full duplex operation after speed 482 * downgrade even if it is operating at half duplex. 483 * Here we set the duplex settings to match the duplex in the 484 * link partner's capabilities. 485 */ 486 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &data); 487 if (ret_val) 488 goto out; 489 490 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 491 *duplex = HALF_DUPLEX; 492 } else { 493 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &data); 494 if (ret_val) 495 goto out; 496 497 if (*speed == SPEED_100) { 498 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 499 *duplex = HALF_DUPLEX; 500 } else if (*speed == SPEED_10) { 501 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 502 *duplex = HALF_DUPLEX; 503 } 504 } 505 506out: 507 return ret_val; 508} 509 510/** 511 * e1000_phy_hw_reset_82541 - PHY hardware reset 512 * @hw: pointer to the HW structure 513 * 514 * Verify the reset block is not blocking us from resetting. Acquire 515 * semaphore (if necessary) and read/set/write the device control reset 516 * bit in the PHY. Wait the appropriate delay time for the device to 517 * reset and relase the semaphore (if necessary). 518 * This is a function pointer entry point called by the api module. 519 **/ 520STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 521{ 522 s32 ret_val; 523 u32 ledctl; 524 525 DEBUGFUNC("e1000_phy_hw_reset_82541"); 526 527 ret_val = e1000_phy_hw_reset_generic(hw); 528 if (ret_val) 529 goto out; 530 531 e1000_phy_init_script_82541(hw); 532 533 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 534 /* Configure activity LED after PHY reset */ 535 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 536 ledctl &= IGP_ACTIVITY_LED_MASK; 537 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 538 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 539 } 540 541out: 542 return ret_val; 543} 544 545/** 546 * e1000_setup_copper_link_82541 - Configure copper link settings 547 * @hw: pointer to the HW structure 548 * 549 * Calls the appropriate function to configure the link for auto-neg or forced 550 * speed and duplex. Then we check for link, once link is established calls 551 * to configure collision distance and flow control are called. If link is 552 * not established, we return -E1000_ERR_PHY (-2). This is a function 553 * pointer entry point called by the api module. 554 **/ 555STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 556{ 557 struct e1000_phy_info *phy = &hw->phy; 558 struct e1000_dev_spec_82541 *dev_spec; 559 s32 ret_val; 560 u32 ctrl, ledctl; 561 562 DEBUGFUNC("e1000_setup_copper_link_82541"); 563 564 ctrl = E1000_READ_REG(hw, E1000_CTRL); 565 ctrl |= E1000_CTRL_SLU; 566 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 567 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 568 569 hw->phy.reset_disable = FALSE; 570 571 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 572 573 /* Earlier revs of the IGP phy require us to force MDI. */ 574 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 575 dev_spec->dsp_config = e1000_dsp_config_disabled; 576 phy->mdix = 1; 577 } else { 578 dev_spec->dsp_config = e1000_dsp_config_enabled; 579 } 580 581 ret_val = e1000_copper_link_setup_igp(hw); 582 if (ret_val) 583 goto out; 584 585 if (hw->mac.autoneg) { 586 if (dev_spec->ffe_config == e1000_ffe_config_active) 587 dev_spec->ffe_config = e1000_ffe_config_enabled; 588 } 589 590 /* Configure activity LED after Phy reset */ 591 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 592 ledctl &= IGP_ACTIVITY_LED_MASK; 593 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 594 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 595 596 ret_val = e1000_setup_copper_link_generic(hw); 597 598out: 599 return ret_val; 600} 601 602/** 603 * e1000_check_for_link_82541 - Check/Store link connection 604 * @hw: pointer to the HW structure 605 * 606 * This checks the link condition of the adapter and stores the 607 * results in the hw->mac structure. This is a function pointer entry 608 * point called by the api module. 609 **/ 610STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw) 611{ 612 struct e1000_mac_info *mac = &hw->mac; 613 s32 ret_val; 614 bool link; 615 616 DEBUGFUNC("e1000_check_for_link_82541"); 617 618 /* 619 * We only want to go out to the PHY registers to see if Auto-Neg 620 * has completed and/or if our link status has changed. The 621 * get_link_status flag is set upon receiving a Link Status 622 * Change or Rx Sequence Error interrupt. 623 */ 624 if (!mac->get_link_status) { 625 ret_val = E1000_SUCCESS; 626 goto out; 627 } 628 629 /* 630 * First we want to see if the MII Status Register reports 631 * link. If so, then we want to get the current speed/duplex 632 * of the PHY. 633 */ 634 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 635 if (ret_val) 636 goto out; 637 638 if (!link) { 639 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 640 goto out; /* No link detected */ 641 } 642 643 mac->get_link_status = FALSE; 644 645 /* 646 * Check if there was DownShift, must be checked 647 * immediately after link-up 648 */ 649 e1000_check_downshift_generic(hw); 650 651 /* 652 * If we are forcing speed/duplex, then we simply return since 653 * we have already determined whether we have link or not. 654 */ 655 if (!mac->autoneg) { 656 ret_val = -E1000_ERR_CONFIG; 657 goto out; 658 } 659 660 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 661 662 /* 663 * Auto-Neg is enabled. Auto Speed Detection takes care 664 * of MAC speed/duplex configuration. So we only need to 665 * configure Collision Distance in the MAC. 666 */ 667 e1000_config_collision_dist_generic(hw); 668 669 /* 670 * Configure Flow Control now that Auto-Neg has completed. 671 * First, we need to restore the desired flow control 672 * settings because we may have had to re-autoneg with a 673 * different link partner. 674 */ 675 ret_val = e1000_config_fc_after_link_up_generic(hw); 676 if (ret_val) { 677 DEBUGOUT("Error configuring flow control\n"); 678 } 679 680out: 681 return ret_val; 682} 683 684/** 685 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 686 * @hw: pointer to the HW structure 687 * @link_up: boolean flag for link up status 688 * 689 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 690 * at any other case. 691 * 692 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 693 * gigabit link is achieved to improve link quality. 694 * This is a function pointer entry point called by the api module. 695 **/ 696static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 697 bool link_up) 698{ 699 struct e1000_phy_info *phy = &hw->phy; 700 struct e1000_dev_spec_82541 *dev_spec; 701 s32 ret_val; 702 u32 idle_errs = 0; 703 u16 phy_data, phy_saved_data, speed, duplex, i; 704 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 705 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 706 {IGP01E1000_PHY_AGC_PARAM_A, 707 IGP01E1000_PHY_AGC_PARAM_B, 708 IGP01E1000_PHY_AGC_PARAM_C, 709 IGP01E1000_PHY_AGC_PARAM_D}; 710 711 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 712 713 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 714 715 if (link_up) { 716 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 717 if (ret_val) { 718 DEBUGOUT("Error getting link speed and duplex\n"); 719 goto out; 720 } 721 722 if (speed != SPEED_1000) { 723 ret_val = E1000_SUCCESS; 724 goto out; 725 } 726 727 ret_val = e1000_get_cable_length(hw); 728 if (ret_val) 729 goto out; 730 731 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 732 phy->min_cable_length >= 50) { 733 734 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 735 ret_val = e1000_read_phy_reg(hw, 736 dsp_reg_array[i], 737 &phy_data); 738 if (ret_val) 739 goto out; 740 741 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 742 743 ret_val = e1000_write_phy_reg(hw, 744 dsp_reg_array[i], 745 phy_data); 746 if (ret_val) 747 goto out; 748 } 749 dev_spec->dsp_config = e1000_dsp_config_activated; 750 } 751 752 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 753 (phy->min_cable_length >= 50)) { 754 ret_val = E1000_SUCCESS; 755 goto out; 756 } 757 758 /* clear previous idle error counts */ 759 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 760 if (ret_val) 761 goto out; 762 763 for (i = 0; i < ffe_idle_err_timeout; i++) { 764 usec_delay(1000); 765 ret_val = e1000_read_phy_reg(hw, 766 PHY_1000T_STATUS, 767 &phy_data); 768 if (ret_val) 769 goto out; 770 771 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 772 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 773 dev_spec->ffe_config = e1000_ffe_config_active; 774 775 ret_val = e1000_write_phy_reg(hw, 776 IGP01E1000_PHY_DSP_FFE, 777 IGP01E1000_PHY_DSP_FFE_CM_CP); 778 if (ret_val) 779 goto out; 780 break; 781 } 782 783 if (idle_errs) 784 ffe_idle_err_timeout = 785 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 786 } 787 } else { 788 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 789 /* 790 * Save off the current value of register 0x2F5B 791 * to be restored at the end of the routines. 792 */ 793 ret_val = e1000_read_phy_reg(hw, 794 0x2F5B, 795 &phy_saved_data); 796 if (ret_val) 797 goto out; 798 799 /* Disable the PHY transmitter */ 800 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 801 if (ret_val) 802 goto out; 803 804 msec_delay_irq(20); 805 806 ret_val = e1000_write_phy_reg(hw, 807 0x0000, 808 IGP01E1000_IEEE_FORCE_GIG); 809 if (ret_val) 810 goto out; 811 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 812 ret_val = e1000_read_phy_reg(hw, 813 dsp_reg_array[i], 814 &phy_data); 815 if (ret_val) 816 goto out; 817 818 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 819 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 820 821 ret_val = e1000_write_phy_reg(hw, 822 dsp_reg_array[i], 823 phy_data); 824 if (ret_val) 825 goto out; 826 } 827 828 ret_val = e1000_write_phy_reg(hw, 829 0x0000, 830 IGP01E1000_IEEE_RESTART_AUTONEG); 831 if (ret_val) 832 goto out; 833 834 msec_delay_irq(20); 835 836 /* Now enable the transmitter */ 837 ret_val = e1000_write_phy_reg(hw, 838 0x2F5B, 839 phy_saved_data); 840 if (ret_val) 841 goto out; 842 843 dev_spec->dsp_config = e1000_dsp_config_enabled; 844 } 845 846 if (dev_spec->ffe_config != e1000_ffe_config_active) { 847 ret_val = E1000_SUCCESS; 848 goto out; 849 } 850 851 /* 852 * Save off the current value of register 0x2F5B 853 * to be restored at the end of the routines. 854 */ 855 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 856 if (ret_val) 857 goto out; 858 859 /* Disable the PHY transmitter */ 860 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 861 if (ret_val) 862 goto out; 863 864 msec_delay_irq(20); 865 866 ret_val = e1000_write_phy_reg(hw, 867 0x0000, 868 IGP01E1000_IEEE_FORCE_GIG); 869 if (ret_val) 870 goto out; 871 872 ret_val = e1000_write_phy_reg(hw, 873 IGP01E1000_PHY_DSP_FFE, 874 IGP01E1000_PHY_DSP_FFE_DEFAULT); 875 if (ret_val) 876 goto out; 877 878 ret_val = e1000_write_phy_reg(hw, 879 0x0000, 880 IGP01E1000_IEEE_RESTART_AUTONEG); 881 if (ret_val) 882 goto out; 883 884 msec_delay_irq(20); 885 886 /* Now enable the transmitter */ 887 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 888 889 if (ret_val) 890 goto out; 891 892 dev_spec->ffe_config = e1000_ffe_config_enabled; 893 } 894 895out: 896 return ret_val; 897} 898 899/** 900 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 901 * @hw: pointer to the HW structure 902 * 903 * The automatic gain control (agc) normalizes the amplitude of the 904 * received signal, adjusting for the attenuation produced by the 905 * cable. By reading the AGC registers, which reperesent the 906 * cobination of course and fine gain value, the value can be put 907 * into a lookup table to obtain the approximate cable length 908 * for each channel. This is a function pointer entry point called by the 909 * api module. 910 **/ 911STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 912{ 913 struct e1000_phy_info *phy = &hw->phy; 914 s32 ret_val = E1000_SUCCESS; 915 u16 i, data; 916 u16 cur_agc_value, agc_value = 0; 917 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 918 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 919 {IGP01E1000_PHY_AGC_A, 920 IGP01E1000_PHY_AGC_B, 921 IGP01E1000_PHY_AGC_C, 922 IGP01E1000_PHY_AGC_D}; 923 924 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 925 926 /* Read the AGC registers for all channels */ 927 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 928 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &data); 929 if (ret_val) 930 goto out; 931 932 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 933 934 /* Bounds checking */ 935 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 936 (cur_agc_value == 0)) { 937 ret_val = -E1000_ERR_PHY; 938 goto out; 939 } 940 941 agc_value += cur_agc_value; 942 943 if (min_agc_value > cur_agc_value) 944 min_agc_value = cur_agc_value; 945 } 946 947 /* Remove the minimal AGC result for length < 50m */ 948 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 949 agc_value -= min_agc_value; 950 /* Average the three remaining channels for the length. */ 951 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 952 } else { 953 /* Average the channels for the length. */ 954 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 955 } 956 957 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 958 IGP01E1000_AGC_RANGE) 959 ? (e1000_igp_cable_length_table[agc_value] - 960 IGP01E1000_AGC_RANGE) 961 : 0; 962 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 963 IGP01E1000_AGC_RANGE; 964 965 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 966 967out: 968 return ret_val; 969} 970 971/** 972 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 973 * @hw: pointer to the HW structure 974 * @active: boolean used to enable/disable lplu 975 * 976 * Success returns 0, Failure returns 1 977 * 978 * The low power link up (lplu) state is set to the power management level D3 979 * and SmartSpeed is disabled when active is true, else clear lplu for D3 980 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 981 * is used during Dx states where the power conservation is most important. 982 * During driver activity, SmartSpeed should be enabled so performance is 983 * maintained. This is a function pointer entry point called by the 984 * api module. 985 **/ 986STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 987{ 988 struct e1000_phy_info *phy = &hw->phy; 989 s32 ret_val; 990 u16 data; 991 992 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 993 994 switch (hw->mac.type) { 995 case e1000_82541_rev_2: 996 case e1000_82547_rev_2: 997 break; 998 default: 999 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 1000 goto out; 1001 break; 1002 } 1003 1004 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &data); 1005 if (ret_val) 1006 goto out; 1007 1008 if (!active) { 1009 data &= ~IGP01E1000_GMII_FLEX_SPD; 1010 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1011 if (ret_val) 1012 goto out; 1013 1014 /* 1015 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1016 * during Dx states where the power conservation is most 1017 * important. During driver activity we should enable 1018 * SmartSpeed, so performance is maintained. 1019 */ 1020 if (phy->smart_speed == e1000_smart_speed_on) { 1021 ret_val = e1000_read_phy_reg(hw, 1022 IGP01E1000_PHY_PORT_CONFIG, 1023 &data); 1024 if (ret_val) 1025 goto out; 1026 1027 data |= IGP01E1000_PSCFR_SMART_SPEED; 1028 ret_val = e1000_write_phy_reg(hw, 1029 IGP01E1000_PHY_PORT_CONFIG, 1030 data); 1031 if (ret_val) 1032 goto out; 1033 } else if (phy->smart_speed == e1000_smart_speed_off) { 1034 ret_val = e1000_read_phy_reg(hw, 1035 IGP01E1000_PHY_PORT_CONFIG, 1036 &data); 1037 if (ret_val) 1038 goto out; 1039 1040 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1041 ret_val = e1000_write_phy_reg(hw, 1042 IGP01E1000_PHY_PORT_CONFIG, 1043 data); 1044 if (ret_val) 1045 goto out; 1046 } 1047 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1048 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1049 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1050 data |= IGP01E1000_GMII_FLEX_SPD; 1051 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1052 if (ret_val) 1053 goto out; 1054 1055 /* When LPLU is enabled, we should disable SmartSpeed */ 1056 ret_val = e1000_read_phy_reg(hw, 1057 IGP01E1000_PHY_PORT_CONFIG, 1058 &data); 1059 if (ret_val) 1060 goto out; 1061 1062 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1063 ret_val = e1000_write_phy_reg(hw, 1064 IGP01E1000_PHY_PORT_CONFIG, 1065 data); 1066 } 1067 1068out: 1069 return ret_val; 1070} 1071 1072/** 1073 * e1000_setup_led_82541 - Configures SW controllable LED 1074 * @hw: pointer to the HW structure 1075 * 1076 * This prepares the SW controllable LED for use and saves the current state 1077 * of the LED so it can be later restored. This is a function pointer entry 1078 * point called by the api module. 1079 **/ 1080STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw) 1081{ 1082 struct e1000_dev_spec_82541 *dev_spec; 1083 s32 ret_val; 1084 1085 DEBUGFUNC("e1000_setup_led_82541"); 1086 1087 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1088 1089 ret_val = e1000_read_phy_reg(hw, 1090 IGP01E1000_GMII_FIFO, 1091 &dev_spec->spd_default); 1092 if (ret_val) 1093 goto out; 1094 1095 ret_val = e1000_write_phy_reg(hw, 1096 IGP01E1000_GMII_FIFO, 1097 (u16)(dev_spec->spd_default & 1098 ~IGP01E1000_GMII_SPD)); 1099 if (ret_val) 1100 goto out; 1101 1102 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1103 1104out: 1105 return ret_val; 1106} 1107 1108/** 1109 * e1000_cleanup_led_82541 - Set LED config to default operation 1110 * @hw: pointer to the HW structure 1111 * 1112 * Remove the current LED configuration and set the LED configuration 1113 * to the default value, saved from the EEPROM. This is a function pointer 1114 * entry point called by the api module. 1115 **/ 1116STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1117{ 1118 struct e1000_dev_spec_82541 *dev_spec; 1119 s32 ret_val; 1120 1121 DEBUGFUNC("e1000_cleanup_led_82541"); 1122 1123 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1124 1125 ret_val = e1000_write_phy_reg(hw, 1126 IGP01E1000_GMII_FIFO, 1127 dev_spec->spd_default); 1128 if (ret_val) 1129 goto out; 1130 1131 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1132 1133out: 1134 return ret_val; 1135} 1136 1137/** 1138 * e1000_phy_init_script_82541 - Initialize GbE PHY 1139 * @hw: pointer to the HW structure 1140 * 1141 * Initializes the IGP PHY. 1142 **/ 1143static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1144{ 1145 struct e1000_dev_spec_82541 *dev_spec; 1146 u32 ret_val; 1147 u16 phy_saved_data; 1148 1149 DEBUGFUNC("e1000_phy_init_script_82541"); 1150 1151 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1152 1153 if (!dev_spec->phy_init_script) { 1154 ret_val = E1000_SUCCESS; 1155 goto out; 1156 } 1157 1158 /* Delay after phy reset to enable NVM configuration to load */ 1159 msec_delay(20); 1160 1161 /* 1162 * Save off the current value of register 0x2F5B to be restored at 1163 * the end of this routine. 1164 */ 1165 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 1166 1167 /* Disabled the PHY transmitter */ 1168 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 1169 1170 msec_delay(20); 1171 1172 e1000_write_phy_reg(hw, 0x0000, 0x0140); 1173 1174 msec_delay(5); 1175 1176 switch (hw->mac.type) { 1177 case e1000_82541: 1178 case e1000_82547: 1179 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 1180 1181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 1182 1183 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 1184 1185 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 1186 1187 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 1188 1189 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 1190 1191 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 1192 1193 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 1194 1195 e1000_write_phy_reg(hw, 0x2010, 0x0008); 1196 break; 1197 case e1000_82541_rev_2: 1198 case e1000_82547_rev_2: 1199 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 1200 break; 1201 default: 1202 break; 1203 } 1204 1205 e1000_write_phy_reg(hw, 0x0000, 0x3300); 1206 1207 msec_delay(20); 1208 1209 /* Now enable the transmitter */ 1210 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 1211 1212 if (hw->mac.type == e1000_82547) { 1213 u16 fused, fine, coarse; 1214 1215 /* Move to analog registers page */ 1216 e1000_read_phy_reg(hw, 1217 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1218 &fused); 1219 1220 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1221 e1000_read_phy_reg(hw, 1222 IGP01E1000_ANALOG_FUSE_STATUS, 1223 &fused); 1224 1225 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1226 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1227 1228 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1229 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1230 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1231 } else if (coarse == 1232 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1233 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1234 1235 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1236 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1237 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1238 1239 e1000_write_phy_reg(hw, 1240 IGP01E1000_ANALOG_FUSE_CONTROL, 1241 fused); 1242 e1000_write_phy_reg(hw, 1243 IGP01E1000_ANALOG_FUSE_BYPASS, 1244 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1245 } 1246 } 1247 1248out: 1249 return ret_val; 1250} 1251 1252/** 1253 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1254 * @hw: pointer to the HW structure 1255 * @state: boolean value used to enable/disable PHY init script 1256 * 1257 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1258 * IGP PHY. This is a function pointer entry point called by the api module. 1259 **/ 1260void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1261{ 1262 struct e1000_dev_spec_82541 *dev_spec; 1263 1264 DEBUGFUNC("e1000_init_script_state_82541"); 1265 1266 if (hw->phy.type != e1000_phy_igp) { 1267 DEBUGOUT("Initialization script not necessary.\n"); 1268 goto out; 1269 } 1270 1271 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1272 1273 if (!dev_spec) { 1274 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1275 goto out; 1276 } 1277 1278 dev_spec->phy_init_script = state; 1279 1280out: 1281 return; 1282} 1283 1284/** 1285 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1286 * @hw: pointer to the HW structure 1287 * 1288 * In the case of a PHY power down to save power, or to turn off link during a 1289 * driver unload, or wake on lan is not enabled, remove the link. 1290 **/ 1291STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1292{ 1293 /* If the management interface is not enabled, then power down */ 1294 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1295 e1000_power_down_phy_copper(hw); 1296 1297 return; 1298} 1299 1300/** 1301 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1302 * @hw: pointer to the HW structure 1303 * 1304 * Clears the hardware counters by reading the counter registers. 1305 **/ 1306STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1307{ 1308 volatile u32 temp; 1309 1310 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1311 1312 e1000_clear_hw_cntrs_base_generic(hw); 1313 1314 temp = E1000_READ_REG(hw, E1000_PRC64); 1315 temp = E1000_READ_REG(hw, E1000_PRC127); 1316 temp = E1000_READ_REG(hw, E1000_PRC255); 1317 temp = E1000_READ_REG(hw, E1000_PRC511); 1318 temp = E1000_READ_REG(hw, E1000_PRC1023); 1319 temp = E1000_READ_REG(hw, E1000_PRC1522); 1320 temp = E1000_READ_REG(hw, E1000_PTC64); 1321 temp = E1000_READ_REG(hw, E1000_PTC127); 1322 temp = E1000_READ_REG(hw, E1000_PTC255); 1323 temp = E1000_READ_REG(hw, E1000_PTC511); 1324 temp = E1000_READ_REG(hw, E1000_PTC1023); 1325 temp = E1000_READ_REG(hw, E1000_PTC1522); 1326 1327 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1328 temp = E1000_READ_REG(hw, E1000_RXERRC); 1329 temp = E1000_READ_REG(hw, E1000_TNCRS); 1330 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1331 temp = E1000_READ_REG(hw, E1000_TSCTC); 1332 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1333 1334 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1335 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1336 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1337} 1338