e1000_82541.c revision 169589
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_82541.c 169589 2007-05-16 00:14:23Z jfv $*/ 34 35 36/* e1000_82541 37 * e1000_82547 38 * e1000_82541_rev_2 39 * e1000_82547_rev_2 40 */ 41 42#include "e1000_api.h" 43#include "e1000_82541.h" 44 45void e1000_init_function_pointers_82541(struct e1000_hw *hw); 46 47STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 48STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 49STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 50STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw); 51STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw); 52STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 53 u16 *duplex); 54STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 55STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 56STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw); 57STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 58STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 59 boolean_t active); 60STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw); 61STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 62STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 63static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64 boolean_t link_up); 65static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66 67static const 68u16 e1000_igp_cable_length_table[] = 69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 77#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78 (sizeof(e1000_igp_cable_length_table) / \ 79 sizeof(e1000_igp_cable_length_table[0])) 80 81struct e1000_dev_spec_82541 { 82 e1000_dsp_config dsp_config; 83 e1000_ffe_config ffe_config; 84 u16 spd_default; 85 boolean_t phy_init_script; 86}; 87 88/** 89 * e1000_init_phy_params_82541 - Init PHY func ptrs. 90 * @hw: pointer to the HW structure 91 * 92 * This is a function pointer entry point called by the api module. 93 **/ 94STATIC s32 95e1000_init_phy_params_82541(struct e1000_hw *hw) 96{ 97 struct e1000_phy_info *phy = &hw->phy; 98 struct e1000_functions *func = &hw->func; 99 s32 ret_val = E1000_SUCCESS; 100 101 DEBUGFUNC("e1000_init_phy_params_82541"); 102 103 phy->addr = 1; 104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105 phy->reset_delay_us = 10000; 106 phy->type = e1000_phy_igp; 107 108 /* Function Pointers */ 109 func->check_polarity = e1000_check_polarity_igp; 110 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 111 func->get_cable_length = e1000_get_cable_length_igp_82541; 112 func->get_cfg_done = e1000_get_cfg_done_generic; 113 func->get_phy_info = e1000_get_phy_info_igp; 114 func->read_phy_reg = e1000_read_phy_reg_igp; 115 func->reset_phy = e1000_phy_hw_reset_82541; 116 func->set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 117 func->write_phy_reg = e1000_write_phy_reg_igp; 118 119 ret_val = e1000_get_phy_id(hw); 120 if (ret_val) 121 goto out; 122 123 /* Verify phy id */ 124 if (phy->id != IGP01E1000_I_PHY_ID) { 125 ret_val = -E1000_ERR_PHY; 126 goto out; 127 } 128 129out: 130 return ret_val; 131} 132 133/** 134 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 135 * @hw: pointer to the HW structure 136 * 137 * This is a function pointer entry point called by the api module. 138 **/ 139STATIC s32 140e1000_init_nvm_params_82541(struct e1000_hw *hw) 141{ 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 struct e1000_functions *func = &hw->func; 144 s32 ret_val = E1000_SUCCESS; 145 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 146 u16 size; 147 148 DEBUGFUNC("e1000_init_nvm_params_82541"); 149 150 switch (nvm->override) { 151 case e1000_nvm_override_spi_large: 152 nvm->type = e1000_nvm_eeprom_spi; 153 eecd |= E1000_EECD_ADDR_BITS; 154 break; 155 case e1000_nvm_override_spi_small: 156 nvm->type = e1000_nvm_eeprom_spi; 157 eecd &= ~E1000_EECD_ADDR_BITS; 158 break; 159 case e1000_nvm_override_microwire_large: 160 nvm->type = e1000_nvm_eeprom_microwire; 161 eecd |= E1000_EECD_SIZE; 162 break; 163 case e1000_nvm_override_microwire_small: 164 nvm->type = e1000_nvm_eeprom_microwire; 165 eecd &= ~E1000_EECD_SIZE; 166 break; 167 default: 168 nvm->type = eecd & E1000_EECD_TYPE 169 ? e1000_nvm_eeprom_spi 170 : e1000_nvm_eeprom_microwire; 171 break; 172 } 173 174 if (nvm->type == e1000_nvm_eeprom_spi) { 175 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 176 ? 16 : 8; 177 nvm->delay_usec = 1; 178 nvm->opcode_bits = 8; 179 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 180 ? 32 : 8; 181 182 /* Function Pointers */ 183 func->acquire_nvm = e1000_acquire_nvm_generic; 184 func->read_nvm = e1000_read_nvm_spi; 185 func->release_nvm = e1000_release_nvm_generic; 186 func->update_nvm = e1000_update_nvm_checksum_generic; 187 func->valid_led_default = e1000_valid_led_default_generic; 188 func->validate_nvm = e1000_validate_nvm_checksum_generic; 189 func->write_nvm = e1000_write_nvm_spi; 190 191 /* nvm->word_size must be discovered after the pointers 192 * are set so we can verify the size from the nvm image 193 * itself. Temporarily set it to a dummy value so the 194 * read will work. 195 */ 196 nvm->word_size = 64; 197 ret_val = e1000_read_nvm(hw, NVM_CFG, 1, &size); 198 if (ret_val) 199 goto out; 200 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 201 /* if size != 0, it can be added to a constant and become 202 * the left-shift value to set the word_size. Otherwise, 203 * word_size stays at 64. 204 */ 205 if (size) { 206 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 207 nvm->word_size = 1 << size; 208 } 209 } else { 210 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 211 ? 8 : 6; 212 nvm->delay_usec = 50; 213 nvm->opcode_bits = 3; 214 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 215 ? 256 : 64; 216 217 /* Function Pointers */ 218 func->acquire_nvm = e1000_acquire_nvm_generic; 219 func->read_nvm = e1000_read_nvm_microwire; 220 func->release_nvm = e1000_release_nvm_generic; 221 func->update_nvm = e1000_update_nvm_checksum_generic; 222 func->valid_led_default = e1000_valid_led_default_generic; 223 func->validate_nvm = e1000_validate_nvm_checksum_generic; 224 func->write_nvm = e1000_write_nvm_microwire; 225 } 226 227out: 228 return ret_val; 229} 230 231/** 232 * e1000_init_mac_params_82541 - Init MAC func ptrs. 233 * @hw: pointer to the HW structure 234 * 235 * This is a function pointer entry point called by the api module. 236 **/ 237STATIC s32 238e1000_init_mac_params_82541(struct e1000_hw *hw) 239{ 240 struct e1000_mac_info *mac = &hw->mac; 241 struct e1000_functions *func = &hw->func; 242 s32 ret_val; 243 244 DEBUGFUNC("e1000_init_mac_params_82541"); 245 246 /* Set media type */ 247 hw->media_type = e1000_media_type_copper; 248 /* Set mta register count */ 249 mac->mta_reg_count = 128; 250 /* Set rar entry count */ 251 mac->rar_entry_count = E1000_RAR_ENTRIES; 252 /* Set if part includes ASF firmware */ 253 mac->asf_firmware_present = TRUE; 254 255 /* Function Pointers */ 256 257 /* bus type/speed/width */ 258 func->get_bus_info = e1000_get_bus_info_pci_generic; 259 /* reset */ 260 func->reset_hw = e1000_reset_hw_82541; 261 /* hw initialization */ 262 func->init_hw = e1000_init_hw_82541; 263 /* link setup */ 264 func->setup_link = e1000_setup_link_generic; 265 /* physical interface link setup */ 266 func->setup_physical_interface = e1000_setup_copper_link_82541; 267 /* check for link */ 268 func->check_for_link = e1000_check_for_link_82541; 269 /* link info */ 270 func->get_link_up_info = e1000_get_link_up_info_82541; 271 /* multicast address update */ 272 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 273 /* writing VFTA */ 274 func->write_vfta = e1000_write_vfta_generic; 275 /* clearing VFTA */ 276 func->clear_vfta = e1000_clear_vfta_generic; 277 /* setting MTA */ 278 func->mta_set = e1000_mta_set_generic; 279 /* setup LED */ 280 func->setup_led = e1000_setup_led_82541; 281 /* cleanup LED */ 282 func->cleanup_led = e1000_cleanup_led_82541; 283 /* turn on/off LED */ 284 func->led_on = e1000_led_on_generic; 285 func->led_off = e1000_led_off_generic; 286 /* remove device */ 287 func->remove_device = e1000_remove_device_generic; 288 /* clear hardware counters */ 289 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 290 291 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82541); 292 293 /* Device-specific structure allocation */ 294 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 295 296 return ret_val; 297} 298 299/** 300 * e1000_init_function_pointers_82541 - Init func ptrs. 301 * @hw: pointer to the HW structure 302 * 303 * The only function explicitly called by the api module to initialize 304 * all function pointers and parameters. 305 **/ 306void 307e1000_init_function_pointers_82541(struct e1000_hw *hw) 308{ 309 DEBUGFUNC("e1000_init_function_pointers_82541"); 310 311 hw->func.init_mac_params = e1000_init_mac_params_82541; 312 hw->func.init_nvm_params = e1000_init_nvm_params_82541; 313 hw->func.init_phy_params = e1000_init_phy_params_82541; 314} 315 316/** 317 * e1000_reset_hw_82541 - Reset hardware 318 * @hw: pointer to the HW structure 319 * 320 * This resets the hardware into a known state. This is a 321 * function pointer entry point called by the api module. 322 **/ 323STATIC s32 324e1000_reset_hw_82541(struct e1000_hw *hw) 325{ 326 u32 ledctl, ctrl, icr, manc; 327 328 DEBUGFUNC("e1000_reset_hw_82541"); 329 330 DEBUGOUT("Masking off all interrupts\n"); 331 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 332 333 E1000_WRITE_REG(hw, E1000_RCTL, 0); 334 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 335 E1000_WRITE_FLUSH(hw); 336 337 /* Delay to allow any outstanding PCI transactions to complete 338 * before resetting the device. 339 */ 340 msec_delay(10); 341 342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 343 344 /* Must reset the Phy before resetting the MAC */ 345 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 346 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 347 msec_delay(5); 348 } 349 350 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 351 switch (hw->mac.type) { 352 case e1000_82541: 353 case e1000_82541_rev_2: 354 /* These controllers can't ack the 64-bit write when 355 * issuing the reset, so we use IO-mapping as a 356 * workaround to issue the reset. 357 */ 358 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 359 break; 360 default: 361 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 362 break; 363 } 364 365 /* Wait for NVM reload */ 366 msec_delay(20); 367 368 /* Disable HW ARPs on ASF enabled adapters */ 369 manc = E1000_READ_REG(hw, E1000_MANC); 370 manc &= ~E1000_MANC_ARP_EN; 371 E1000_WRITE_REG(hw, E1000_MANC, manc); 372 373 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 374 e1000_phy_init_script_82541(hw); 375 376 /* Configure activity LED after Phy reset */ 377 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 378 ledctl &= IGP_ACTIVITY_LED_MASK; 379 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 380 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 381 } 382 383 /* Once again, mask the interrupts */ 384 DEBUGOUT("Masking off all interrupts\n"); 385 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 386 387 /* Clear any pending interrupt events. */ 388 icr = E1000_READ_REG(hw, E1000_ICR); 389 390 return E1000_SUCCESS; 391} 392 393/** 394 * e1000_init_hw_82541 - Initialize hardware 395 * @hw: pointer to the HW structure 396 * 397 * This inits the hardware readying it for operation. This is a 398 * function pointer entry point called by the api module. 399 **/ 400STATIC s32 401e1000_init_hw_82541(struct e1000_hw *hw) 402{ 403 struct e1000_mac_info *mac = &hw->mac; 404 u32 i, txdctl; 405 s32 ret_val; 406 407 DEBUGFUNC("e1000_init_hw_82541"); 408 409 /* Initialize identification LED */ 410 ret_val = e1000_id_led_init_generic(hw); 411 if (ret_val) { 412 DEBUGOUT("Error initializing identification LED\n"); 413 goto out; 414 } 415 416 /* Disabling VLAN filtering */ 417 DEBUGOUT("Initializing the IEEE VLAN\n"); 418 e1000_clear_vfta(hw); 419 420 /* Setup the receive address. */ 421 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 422 423 /* Zero out the Multicast HASH table */ 424 DEBUGOUT("Zeroing the MTA\n"); 425 for (i = 0; i < mac->mta_reg_count; i++) { 426 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 427 /* Avoid back to back register writes by adding the register 428 * read (flush). This is to protect against some strange 429 * bridge configurations that may issue Memory Write Block 430 * (MWB) to our register space. 431 */ 432 E1000_WRITE_FLUSH(hw); 433 } 434 435 /* Setup link and flow control */ 436 ret_val = e1000_setup_link(hw); 437 438 txdctl = E1000_READ_REG(hw, E1000_TXDCTL); 439 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 440 E1000_TXDCTL_FULL_TX_DESC_WB; 441 E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl); 442 443 /* Clear all of the statistics registers (clear on read). It is 444 * important that we do this after we have tried to establish link 445 * because the symbol error count will increment wildly if there 446 * is no link. 447 */ 448 e1000_clear_hw_cntrs_82541(hw); 449 450out: 451 return ret_val; 452} 453 454/** 455 * e1000_get_link_up_info_82541 - Report speed and duplex 456 * @hw: pointer to the HW structure 457 * @speed: pointer to speed buffer 458 * @duplex: pointer to duplex buffer 459 * 460 * Retrieve the current speed and duplex configuration. 461 * This is a function pointer entry point called by the api module. 462 **/ 463STATIC s32 464e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, u16 *duplex) 465{ 466 struct e1000_phy_info *phy = &hw->phy; 467 s32 ret_val; 468 u16 data; 469 470 DEBUGFUNC("e1000_get_link_up_info_82541"); 471 472 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 473 if (ret_val) 474 goto out; 475 476 if (!phy->speed_downgraded) 477 goto out; 478 479 /* IGP01 PHY may advertise full duplex operation after speed 480 * downgrade even if it is operating at half duplex. 481 * Here we set the duplex settings to match the duplex in the 482 * link partner's capabilities. 483 */ 484 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &data); 485 if (ret_val) 486 goto out; 487 488 if (!(data & NWAY_ER_LP_NWAY_CAPS)) 489 *duplex = HALF_DUPLEX; 490 else { 491 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &data); 492 if (ret_val) 493 goto out; 494 495 if (*speed == SPEED_100) { 496 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 497 *duplex = HALF_DUPLEX; 498 } else if (*speed == SPEED_10) { 499 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 500 *duplex = HALF_DUPLEX; 501 } 502 } 503 504out: 505 return ret_val; 506} 507 508/** 509 * e1000_phy_hw_reset_82541 - PHY hardware reset 510 * @hw: pointer to the HW structure 511 * 512 * Verify the reset block is not blocking us from resetting. Acquire 513 * semaphore (if necessary) and read/set/write the device control reset 514 * bit in the PHY. Wait the appropriate delay time for the device to 515 * reset and relase the semaphore (if necessary). 516 * This is a function pointer entry point called by the api module. 517 **/ 518STATIC s32 519e1000_phy_hw_reset_82541(struct e1000_hw *hw) 520{ 521 s32 ret_val; 522 u32 ledctl; 523 524 DEBUGFUNC("e1000_phy_hw_reset_82541"); 525 526 ret_val = e1000_phy_hw_reset_generic(hw); 527 if (ret_val) 528 goto out; 529 530 e1000_phy_init_script_82541(hw); 531 532 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 533 /* Configure activity LED after PHY reset */ 534 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 535 ledctl &= IGP_ACTIVITY_LED_MASK; 536 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 537 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 538 } 539 540out: 541 return ret_val; 542} 543 544/** 545 * e1000_setup_copper_link_82541 - Configure copper link settings 546 * @hw: pointer to the HW structure 547 * 548 * Calls the appropriate function to configure the link for auto-neg or forced 549 * speed and duplex. Then we check for link, once link is established calls 550 * to configure collision distance and flow control are called. If link is 551 * not established, we return -E1000_ERR_PHY (-2). This is a function 552 * pointer entry point called by the api module. 553 **/ 554STATIC s32 555e1000_setup_copper_link_82541(struct e1000_hw *hw) 556{ 557 struct e1000_phy_info *phy = &hw->phy; 558 struct e1000_dev_spec_82541 *dev_spec; 559 s32 ret_val; 560 u32 ctrl, ledctl; 561 562 DEBUGFUNC("e1000_setup_copper_link_82541"); 563 564 ctrl = E1000_READ_REG(hw, E1000_CTRL); 565 ctrl |= E1000_CTRL_SLU; 566 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 567 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 568 569 hw->phy.reset_disable = FALSE; 570 571 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 572 573 /* Earlier revs of the IGP phy require us to force MDI. */ 574 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 575 dev_spec->dsp_config = e1000_dsp_config_disabled; 576 phy->mdix = 1; 577 } else 578 dev_spec->dsp_config = e1000_dsp_config_enabled; 579 580 ret_val = e1000_copper_link_setup_igp(hw); 581 if (ret_val) 582 goto out; 583 584 if (hw->mac.autoneg) { 585 if (dev_spec->ffe_config == e1000_ffe_config_active) 586 dev_spec->ffe_config = e1000_ffe_config_enabled; 587 } 588 589 /* Configure activity LED after Phy reset */ 590 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 591 ledctl &= IGP_ACTIVITY_LED_MASK; 592 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 593 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 594 595 ret_val = e1000_setup_copper_link_generic(hw); 596 597out: 598 return ret_val; 599} 600 601/** 602 * e1000_check_for_link_82541 - Check/Store link connection 603 * @hw: pointer to the HW structure 604 * 605 * This checks the link condition of the adapter and stores the 606 * results in the hw->mac structure. This is a function pointer entry 607 * point called by the api module. 608 **/ 609STATIC s32 610e1000_check_for_link_82541(struct e1000_hw *hw) 611{ 612 struct e1000_mac_info *mac = &hw->mac; 613 s32 ret_val; 614 boolean_t link; 615 616 DEBUGFUNC("e1000_check_for_link_82541"); 617 618 /* We only want to go out to the PHY registers to see if Auto-Neg 619 * has completed and/or if our link status has changed. The 620 * get_link_status flag is set upon receiving a Link Status 621 * Change or Rx Sequence Error interrupt. 622 */ 623 if (!mac->get_link_status) { 624 ret_val = E1000_SUCCESS; 625 goto out; 626 } 627 628 /* First we want to see if the MII Status Register reports 629 * link. If so, then we want to get the current speed/duplex 630 * of the PHY. 631 */ 632 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 633 if (ret_val) 634 goto out; 635 636 if (!link) { 637 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 638 goto out; /* No link detected */ 639 } 640 641 mac->get_link_status = FALSE; 642 643 /* Check if there was DownShift, must be checked 644 * immediately after link-up */ 645 e1000_check_downshift_generic(hw); 646 647 /* If we are forcing speed/duplex, then we simply return since 648 * we have already determined whether we have link or not. 649 */ 650 if (!mac->autoneg) { 651 ret_val = -E1000_ERR_CONFIG; 652 goto out; 653 } 654 655 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 656 657 /* Auto-Neg is enabled. Auto Speed Detection takes care 658 * of MAC speed/duplex configuration. So we only need to 659 * configure Collision Distance in the MAC. 660 */ 661 e1000_config_collision_dist_generic(hw); 662 663 /* Configure Flow Control now that Auto-Neg has completed. 664 * First, we need to restore the desired flow control 665 * settings because we may have had to re-autoneg with a 666 * different link partner. 667 */ 668 ret_val = e1000_config_fc_after_link_up_generic(hw); 669 if (ret_val) { 670 DEBUGOUT("Error configuring flow control\n"); 671 } 672 673out: 674 return ret_val; 675} 676 677/** 678 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 679 * @hw: pointer to the HW structure 680 * @link_up: boolean flag for link up status 681 * 682 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 683 * at any other case. 684 * 685 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 686 * gigabit link is achieved to improve link quality. 687 * This is a function pointer entry point called by the api module. 688 **/ 689static s32 690e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, boolean_t link_up) 691{ 692 struct e1000_phy_info *phy = &hw->phy; 693 struct e1000_dev_spec_82541 *dev_spec; 694 s32 ret_val; 695 u32 idle_errs = 0; 696 u16 phy_data, phy_saved_data, speed, duplex, i; 697 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 698 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 699 {IGP01E1000_PHY_AGC_PARAM_A, 700 IGP01E1000_PHY_AGC_PARAM_B, 701 IGP01E1000_PHY_AGC_PARAM_C, 702 IGP01E1000_PHY_AGC_PARAM_D}; 703 704 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 705 706 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 707 708 if (link_up) { 709 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 710 if (ret_val) { 711 DEBUGOUT("Error getting link speed and duplex\n"); 712 goto out; 713 } 714 715 if (speed != SPEED_1000) { 716 ret_val = E1000_SUCCESS; 717 goto out; 718 } 719 720 ret_val = e1000_get_cable_length(hw); 721 if (ret_val) 722 goto out; 723 724 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 725 phy->min_cable_length >= 50) { 726 727 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 728 ret_val = e1000_read_phy_reg(hw, 729 dsp_reg_array[i], 730 &phy_data); 731 if (ret_val) 732 goto out; 733 734 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 735 736 ret_val = e1000_write_phy_reg(hw, 737 dsp_reg_array[i], 738 phy_data); 739 if (ret_val) 740 goto out; 741 } 742 dev_spec->dsp_config = e1000_dsp_config_activated; 743 } 744 745 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 746 (phy->min_cable_length >= 50)) { 747 ret_val = E1000_SUCCESS; 748 goto out; 749 } 750 751 /* clear previous idle error counts */ 752 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 753 if (ret_val) 754 goto out; 755 756 for (i = 0; i < ffe_idle_err_timeout; i++) { 757 usec_delay(1000); 758 ret_val = e1000_read_phy_reg(hw, 759 PHY_1000T_STATUS, 760 &phy_data); 761 if (ret_val) 762 goto out; 763 764 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 765 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 766 dev_spec->ffe_config = e1000_ffe_config_active; 767 768 ret_val = e1000_write_phy_reg(hw, 769 IGP01E1000_PHY_DSP_FFE, 770 IGP01E1000_PHY_DSP_FFE_CM_CP); 771 if (ret_val) 772 goto out; 773 break; 774 } 775 776 if (idle_errs) 777 ffe_idle_err_timeout = 778 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 779 } 780 } else { 781 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 782 /* Save off the current value of register 0x2F5B 783 * to be restored at the end of the routines. */ 784 ret_val = e1000_read_phy_reg(hw, 785 0x2F5B, 786 &phy_saved_data); 787 if (ret_val) 788 goto out; 789 790 /* Disable the PHY transmitter */ 791 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 792 if (ret_val) 793 goto out; 794 795 msec_delay_irq(20); 796 797 ret_val = e1000_write_phy_reg(hw, 798 0x0000, 799 IGP01E1000_IEEE_FORCE_GIG); 800 if (ret_val) 801 goto out; 802 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 803 ret_val = e1000_read_phy_reg(hw, 804 dsp_reg_array[i], 805 &phy_data); 806 if (ret_val) 807 goto out; 808 809 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 810 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 811 812 ret_val = e1000_write_phy_reg(hw, 813 dsp_reg_array[i], 814 phy_data); 815 if (ret_val) 816 goto out; 817 } 818 819 ret_val = e1000_write_phy_reg(hw, 820 0x0000, 821 IGP01E1000_IEEE_RESTART_AUTONEG); 822 if (ret_val) 823 goto out; 824 825 msec_delay_irq(20); 826 827 /* Now enable the transmitter */ 828 ret_val = e1000_write_phy_reg(hw, 829 0x2F5B, 830 phy_saved_data); 831 if (ret_val) 832 goto out; 833 834 dev_spec->dsp_config = e1000_dsp_config_enabled; 835 } 836 837 if (dev_spec->ffe_config != e1000_ffe_config_active) { 838 ret_val = E1000_SUCCESS; 839 goto out; 840 } 841 842 /* Save off the current value of register 0x2F5B 843 * to be restored at the end of the routines. */ 844 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 845 if (ret_val) 846 goto out; 847 848 /* Disable the PHY transmitter */ 849 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 850 if (ret_val) 851 goto out; 852 853 msec_delay_irq(20); 854 855 ret_val = e1000_write_phy_reg(hw, 856 0x0000, 857 IGP01E1000_IEEE_FORCE_GIG); 858 if (ret_val) 859 goto out; 860 861 ret_val = e1000_write_phy_reg(hw, 862 IGP01E1000_PHY_DSP_FFE, 863 IGP01E1000_PHY_DSP_FFE_DEFAULT); 864 if (ret_val) 865 goto out; 866 867 ret_val = e1000_write_phy_reg(hw, 868 0x0000, 869 IGP01E1000_IEEE_RESTART_AUTONEG); 870 if (ret_val) 871 goto out; 872 873 msec_delay_irq(20); 874 875 /* Now enable the transmitter */ 876 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 877 878 if (ret_val) 879 goto out; 880 881 dev_spec->ffe_config = e1000_ffe_config_enabled; 882 } 883 884out: 885 return ret_val; 886} 887 888/** 889 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 890 * @hw: pointer to the HW structure 891 * 892 * The automatic gain control (agc) normalizes the amplitude of the 893 * received signal, adjusting for the attenuation produced by the 894 * cable. By reading the AGC registers, which reperesent the 895 * cobination of course and fine gain value, the value can be put 896 * into a lookup table to obtain the approximate cable length 897 * for each channel. This is a function pointer entry point called by the 898 * api module. 899 **/ 900STATIC s32 901e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 902{ 903 struct e1000_phy_info *phy = &hw->phy; 904 s32 ret_val = E1000_SUCCESS; 905 u16 i, data; 906 u16 cur_agc_value, agc_value = 0; 907 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 908 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 909 {IGP01E1000_PHY_AGC_A, 910 IGP01E1000_PHY_AGC_B, 911 IGP01E1000_PHY_AGC_C, 912 IGP01E1000_PHY_AGC_D}; 913 914 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 915 916 /* Read the AGC registers for all channels */ 917 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 918 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &data); 919 if (ret_val) 920 goto out; 921 922 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 923 924 /* Bounds checking */ 925 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 926 (cur_agc_value == 0)) { 927 ret_val = -E1000_ERR_PHY; 928 goto out; 929 } 930 931 agc_value += cur_agc_value; 932 933 if (min_agc_value > cur_agc_value) 934 min_agc_value = cur_agc_value; 935 } 936 937 /* Remove the minimal AGC result for length < 50m */ 938 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 939 agc_value -= min_agc_value; 940 /* Average the three remaining channels for the length. */ 941 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 942 } else { 943 /* Average the channels for the length. */ 944 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 945 } 946 947 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 948 IGP01E1000_AGC_RANGE) 949 ? (e1000_igp_cable_length_table[agc_value] - 950 IGP01E1000_AGC_RANGE) 951 : 0; 952 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 953 IGP01E1000_AGC_RANGE; 954 955 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 956 957out: 958 return ret_val; 959} 960 961/** 962 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 963 * @hw: pointer to the HW structure 964 * @active: boolean used to enable/disable lplu 965 * 966 * Success returns 0, Failure returns 1 967 * 968 * The low power link up (lplu) state is set to the power management level D3 969 * and SmartSpeed is disabled when active is true, else clear lplu for D3 970 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 971 * is used during Dx states where the power conservation is most important. 972 * During driver activity, SmartSpeed should be enabled so performance is 973 * maintained. This is a function pointer entry point called by the 974 * api module. 975 **/ 976STATIC s32 977e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, boolean_t active) 978{ 979 struct e1000_phy_info *phy = &hw->phy; 980 s32 ret_val; 981 u16 data; 982 983 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 984 985 switch (hw->mac.type) { 986 case e1000_82541_rev_2: 987 case e1000_82547_rev_2: 988 break; 989 default: 990 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 991 goto out; 992 break; 993 } 994 995 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &data); 996 if (ret_val) 997 goto out; 998 999 if (!active) { 1000 data &= ~IGP01E1000_GMII_FLEX_SPD; 1001 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1002 if (ret_val) 1003 goto out; 1004 1005 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1006 * during Dx states where the power conservation is most 1007 * important. During driver activity we should enable 1008 * SmartSpeed, so performance is maintained. */ 1009 if (phy->smart_speed == e1000_smart_speed_on) { 1010 ret_val = e1000_read_phy_reg(hw, 1011 IGP01E1000_PHY_PORT_CONFIG, 1012 &data); 1013 if (ret_val) 1014 goto out; 1015 1016 data |= IGP01E1000_PSCFR_SMART_SPEED; 1017 ret_val = e1000_write_phy_reg(hw, 1018 IGP01E1000_PHY_PORT_CONFIG, 1019 data); 1020 if (ret_val) 1021 goto out; 1022 } else if (phy->smart_speed == e1000_smart_speed_off) { 1023 ret_val = e1000_read_phy_reg(hw, 1024 IGP01E1000_PHY_PORT_CONFIG, 1025 &data); 1026 if (ret_val) 1027 goto out; 1028 1029 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1030 ret_val = e1000_write_phy_reg(hw, 1031 IGP01E1000_PHY_PORT_CONFIG, 1032 data); 1033 if (ret_val) 1034 goto out; 1035 } 1036 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1037 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1038 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1039 data |= IGP01E1000_GMII_FLEX_SPD; 1040 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data); 1041 if (ret_val) 1042 goto out; 1043 1044 /* When LPLU is enabled, we should disable SmartSpeed */ 1045 ret_val = e1000_read_phy_reg(hw, 1046 IGP01E1000_PHY_PORT_CONFIG, 1047 &data); 1048 if (ret_val) 1049 goto out; 1050 1051 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1052 ret_val = e1000_write_phy_reg(hw, 1053 IGP01E1000_PHY_PORT_CONFIG, 1054 data); 1055 } 1056 1057out: 1058 return ret_val; 1059} 1060 1061/** 1062 * e1000_setup_led_82541 - Configures SW controllable LED 1063 * @hw: pointer to the HW structure 1064 * 1065 * This prepares the SW controllable LED for use and saves the current state 1066 * of the LED so it can be later restored. This is a function pointer entry 1067 * point called by the api module. 1068 **/ 1069STATIC s32 1070e1000_setup_led_82541(struct e1000_hw *hw) 1071{ 1072 struct e1000_dev_spec_82541 *dev_spec; 1073 s32 ret_val; 1074 1075 DEBUGFUNC("e1000_setup_led_82541"); 1076 1077 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1078 1079 ret_val = e1000_read_phy_reg(hw, 1080 IGP01E1000_GMII_FIFO, 1081 &dev_spec->spd_default); 1082 if (ret_val) 1083 goto out; 1084 1085 ret_val = e1000_write_phy_reg(hw, 1086 IGP01E1000_GMII_FIFO, 1087 (u16)(dev_spec->spd_default & 1088 ~IGP01E1000_GMII_SPD)); 1089 if (ret_val) 1090 goto out; 1091 1092 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1093 1094out: 1095 return ret_val; 1096} 1097 1098/** 1099 * e1000_cleanup_led_82541 - Set LED config to default operation 1100 * @hw: pointer to the HW structure 1101 * 1102 * Remove the current LED configuration and set the LED configuration 1103 * to the default value, saved from the EEPROM. This is a function pointer 1104 * entry point called by the api module. 1105 **/ 1106STATIC s32 1107e1000_cleanup_led_82541(struct e1000_hw *hw) 1108{ 1109 struct e1000_dev_spec_82541 *dev_spec; 1110 s32 ret_val; 1111 1112 DEBUGFUNC("e1000_cleanup_led_82541"); 1113 1114 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1115 1116 ret_val = e1000_write_phy_reg(hw, 1117 IGP01E1000_GMII_FIFO, 1118 dev_spec->spd_default); 1119 if (ret_val) 1120 goto out; 1121 1122 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1123 1124out: 1125 return ret_val; 1126} 1127 1128/** 1129 * e1000_phy_init_script_82541 - Initialize GbE PHY 1130 * @hw: pointer to the HW structure 1131 * 1132 * Initializes the IGP PHY. 1133 **/ 1134static s32 1135e1000_phy_init_script_82541(struct e1000_hw *hw) 1136{ 1137 struct e1000_dev_spec_82541 *dev_spec; 1138 u32 ret_val; 1139 u16 phy_saved_data; 1140 1141 DEBUGFUNC("e1000_phy_init_script_82541"); 1142 1143 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1144 1145 if (!dev_spec->phy_init_script) { 1146 ret_val = E1000_SUCCESS; 1147 goto out; 1148 } 1149 1150 /* Delay after phy reset to enable NVM configuration to load */ 1151 msec_delay(20); 1152 1153 /* Save off the current value of register 0x2F5B to be restored at 1154 * the end of this routine. */ 1155 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 1156 1157 /* Disabled the PHY transmitter */ 1158 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 1159 1160 msec_delay(20); 1161 1162 e1000_write_phy_reg(hw, 0x0000, 0x0140); 1163 1164 msec_delay(5); 1165 1166 switch (hw->mac.type) { 1167 case e1000_82541: 1168 case e1000_82547: 1169 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 1170 1171 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 1172 1173 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 1174 1175 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 1176 1177 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 1178 1179 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 1180 1181 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 1182 1183 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 1184 1185 e1000_write_phy_reg(hw, 0x2010, 0x0008); 1186 break; 1187 case e1000_82541_rev_2: 1188 case e1000_82547_rev_2: 1189 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 1190 break; 1191 default: 1192 break; 1193 } 1194 1195 e1000_write_phy_reg(hw, 0x0000, 0x3300); 1196 1197 msec_delay(20); 1198 1199 /* Now enable the transmitter */ 1200 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 1201 1202 if (hw->mac.type == e1000_82547) { 1203 u16 fused, fine, coarse; 1204 1205 /* Move to analog registers page */ 1206 e1000_read_phy_reg(hw, 1207 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1208 &fused); 1209 1210 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1211 e1000_read_phy_reg(hw, 1212 IGP01E1000_ANALOG_FUSE_STATUS, 1213 &fused); 1214 1215 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1216 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1217 1218 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1219 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1221 } else if (coarse == 1222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1224 1225 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1226 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1227 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1228 1229 e1000_write_phy_reg(hw, 1230 IGP01E1000_ANALOG_FUSE_CONTROL, 1231 fused); 1232 e1000_write_phy_reg(hw, 1233 IGP01E1000_ANALOG_FUSE_BYPASS, 1234 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1235 } 1236 } 1237 1238out: 1239 return ret_val; 1240} 1241 1242/** 1243 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1244 * @hw: pointer to the HW structure 1245 * @state: boolean value used to enable/disable PHY init script 1246 * 1247 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1248 * IGP PHY. This is a function pointer entry point called by the api module. 1249 **/ 1250void 1251e1000_init_script_state_82541(struct e1000_hw *hw, boolean_t state) 1252{ 1253 struct e1000_dev_spec_82541 *dev_spec; 1254 1255 DEBUGFUNC("e1000_init_script_state_82541"); 1256 1257 if (hw->phy.type != e1000_phy_igp) { 1258 DEBUGOUT("Initialization script not necessary.\n"); 1259 goto out; 1260 } 1261 1262 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec; 1263 1264 if (dev_spec == NULL) { 1265 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1266 goto out; 1267 } 1268 1269 dev_spec->phy_init_script = state; 1270 1271out: 1272 return; 1273} 1274 1275/** 1276 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1277 * @hw: pointer to the HW structure 1278 * 1279 * Clears the hardware counters by reading the counter registers. 1280 **/ 1281STATIC void 1282e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1283{ 1284 volatile u32 temp; 1285 1286 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1287 1288 e1000_clear_hw_cntrs_base_generic(hw); 1289 1290 temp = E1000_READ_REG(hw, E1000_PRC64); 1291 temp = E1000_READ_REG(hw, E1000_PRC127); 1292 temp = E1000_READ_REG(hw, E1000_PRC255); 1293 temp = E1000_READ_REG(hw, E1000_PRC511); 1294 temp = E1000_READ_REG(hw, E1000_PRC1023); 1295 temp = E1000_READ_REG(hw, E1000_PRC1522); 1296 temp = E1000_READ_REG(hw, E1000_PTC64); 1297 temp = E1000_READ_REG(hw, E1000_PTC127); 1298 temp = E1000_READ_REG(hw, E1000_PTC255); 1299 temp = E1000_READ_REG(hw, E1000_PTC511); 1300 temp = E1000_READ_REG(hw, E1000_PTC1023); 1301 temp = E1000_READ_REG(hw, E1000_PTC1522); 1302 1303 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1304 temp = E1000_READ_REG(hw, E1000_RXERRC); 1305 temp = E1000_READ_REG(hw, E1000_TNCRS); 1306 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1307 temp = E1000_READ_REG(hw, E1000_TSCTC); 1308 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1309 1310 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1311 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1312 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1313} 1314