1177867Sjfv/****************************************************************************** 2169240Sjfv 3235527Sjfv Copyright (c) 2001-2011, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82541EI Gigabit Ethernet Controller 37185353Sjfv * 82541ER Gigabit Ethernet Controller 38185353Sjfv * 82541GI Gigabit Ethernet Controller 39185353Sjfv * 82541PI Gigabit Ethernet Controller 40185353Sjfv * 82547EI Gigabit Ethernet Controller 41185353Sjfv * 82547GI Gigabit Ethernet Controller 42169240Sjfv */ 43169240Sjfv 44169589Sjfv#include "e1000_api.h" 45169240Sjfv 46177867Sjfvstatic s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50177867Sjfvstatic s32 e1000_init_hw_82541(struct e1000_hw *hw); 51177867Sjfvstatic s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52169240Sjfv u16 *duplex); 53177867Sjfvstatic s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54177867Sjfvstatic s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55177867Sjfvstatic s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57177867Sjfvstatic s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58173788Sjfv bool active); 59177867Sjfvstatic s32 e1000_setup_led_82541(struct e1000_hw *hw); 60177867Sjfvstatic s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61177867Sjfvstatic void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62200243Sjfvstatic s32 e1000_read_mac_addr_82541(struct e1000_hw *hw); 63169240Sjfvstatic s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64173788Sjfv bool link_up); 65169240Sjfvstatic s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66177867Sjfvstatic void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 67169240Sjfv 68173788Sjfvstatic const u16 e1000_igp_cable_length_table[] = 69169240Sjfv { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 70169240Sjfv 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 71169240Sjfv 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 72169240Sjfv 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 73169240Sjfv 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 74169240Sjfv 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 75169240Sjfv 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 76169240Sjfv 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 77169240Sjfv#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78169240Sjfv (sizeof(e1000_igp_cable_length_table) / \ 79169240Sjfv sizeof(e1000_igp_cable_length_table[0])) 80169240Sjfv 81169240Sjfv/** 82169240Sjfv * e1000_init_phy_params_82541 - Init PHY func ptrs. 83169589Sjfv * @hw: pointer to the HW structure 84169240Sjfv **/ 85177867Sjfvstatic s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 86169240Sjfv{ 87169240Sjfv struct e1000_phy_info *phy = &hw->phy; 88169240Sjfv s32 ret_val = E1000_SUCCESS; 89169240Sjfv 90169240Sjfv DEBUGFUNC("e1000_init_phy_params_82541"); 91169240Sjfv 92177867Sjfv phy->addr = 1; 93177867Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 94177867Sjfv phy->reset_delay_us = 10000; 95177867Sjfv phy->type = e1000_phy_igp; 96169240Sjfv 97169240Sjfv /* Function Pointers */ 98177867Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 99177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 100177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 101177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 102177867Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 103177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 104177867Sjfv phy->ops.reset = e1000_phy_hw_reset_82541; 105177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 106177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 107177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 108177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82541; 109169240Sjfv 110169240Sjfv ret_val = e1000_get_phy_id(hw); 111169240Sjfv if (ret_val) 112169240Sjfv goto out; 113169240Sjfv 114169240Sjfv /* Verify phy id */ 115169240Sjfv if (phy->id != IGP01E1000_I_PHY_ID) { 116169240Sjfv ret_val = -E1000_ERR_PHY; 117169240Sjfv goto out; 118169240Sjfv } 119169240Sjfv 120169240Sjfvout: 121169240Sjfv return ret_val; 122169240Sjfv} 123169240Sjfv 124169240Sjfv/** 125169240Sjfv * e1000_init_nvm_params_82541 - Init NVM func ptrs. 126169589Sjfv * @hw: pointer to the HW structure 127169240Sjfv **/ 128177867Sjfvstatic s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 129169240Sjfv{ 130169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 131169240Sjfv s32 ret_val = E1000_SUCCESS; 132169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 133169240Sjfv u16 size; 134169240Sjfv 135169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82541"); 136169240Sjfv 137169240Sjfv switch (nvm->override) { 138169240Sjfv case e1000_nvm_override_spi_large: 139169240Sjfv nvm->type = e1000_nvm_eeprom_spi; 140169240Sjfv eecd |= E1000_EECD_ADDR_BITS; 141169240Sjfv break; 142169240Sjfv case e1000_nvm_override_spi_small: 143169240Sjfv nvm->type = e1000_nvm_eeprom_spi; 144169240Sjfv eecd &= ~E1000_EECD_ADDR_BITS; 145169240Sjfv break; 146169240Sjfv case e1000_nvm_override_microwire_large: 147169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 148169240Sjfv eecd |= E1000_EECD_SIZE; 149169240Sjfv break; 150169240Sjfv case e1000_nvm_override_microwire_small: 151169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 152169240Sjfv eecd &= ~E1000_EECD_SIZE; 153169240Sjfv break; 154169240Sjfv default: 155169240Sjfv nvm->type = eecd & E1000_EECD_TYPE 156169240Sjfv ? e1000_nvm_eeprom_spi 157169240Sjfv : e1000_nvm_eeprom_microwire; 158169240Sjfv break; 159169240Sjfv } 160169240Sjfv 161169240Sjfv if (nvm->type == e1000_nvm_eeprom_spi) { 162169240Sjfv nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 163169240Sjfv ? 16 : 8; 164169240Sjfv nvm->delay_usec = 1; 165169240Sjfv nvm->opcode_bits = 8; 166169240Sjfv nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 167169240Sjfv ? 32 : 8; 168169240Sjfv 169169240Sjfv /* Function Pointers */ 170177867Sjfv nvm->ops.acquire = e1000_acquire_nvm_generic; 171177867Sjfv nvm->ops.read = e1000_read_nvm_spi; 172177867Sjfv nvm->ops.release = e1000_release_nvm_generic; 173177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 174177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_generic; 175177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 176177867Sjfv nvm->ops.write = e1000_write_nvm_spi; 177169240Sjfv 178173788Sjfv /* 179173788Sjfv * nvm->word_size must be discovered after the pointers 180169240Sjfv * are set so we can verify the size from the nvm image 181169240Sjfv * itself. Temporarily set it to a dummy value so the 182169240Sjfv * read will work. 183169240Sjfv */ 184169240Sjfv nvm->word_size = 64; 185177867Sjfv ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 186169240Sjfv if (ret_val) 187169240Sjfv goto out; 188169240Sjfv size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 189173788Sjfv /* 190173788Sjfv * if size != 0, it can be added to a constant and become 191169240Sjfv * the left-shift value to set the word_size. Otherwise, 192169240Sjfv * word_size stays at 64. 193169240Sjfv */ 194169240Sjfv if (size) { 195169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT_82541; 196169240Sjfv nvm->word_size = 1 << size; 197169240Sjfv } 198169240Sjfv } else { 199169240Sjfv nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 200169240Sjfv ? 8 : 6; 201169240Sjfv nvm->delay_usec = 50; 202169240Sjfv nvm->opcode_bits = 3; 203169240Sjfv nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 204169240Sjfv ? 256 : 64; 205169240Sjfv 206169240Sjfv /* Function Pointers */ 207177867Sjfv nvm->ops.acquire = e1000_acquire_nvm_generic; 208177867Sjfv nvm->ops.read = e1000_read_nvm_microwire; 209177867Sjfv nvm->ops.release = e1000_release_nvm_generic; 210177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 211177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_generic; 212177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 213177867Sjfv nvm->ops.write = e1000_write_nvm_microwire; 214169240Sjfv } 215169240Sjfv 216169240Sjfvout: 217169240Sjfv return ret_val; 218169240Sjfv} 219169240Sjfv 220169240Sjfv/** 221169240Sjfv * e1000_init_mac_params_82541 - Init MAC func ptrs. 222169589Sjfv * @hw: pointer to the HW structure 223169240Sjfv **/ 224177867Sjfvstatic s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 225169240Sjfv{ 226169240Sjfv struct e1000_mac_info *mac = &hw->mac; 227169240Sjfv 228169240Sjfv DEBUGFUNC("e1000_init_mac_params_82541"); 229169240Sjfv 230169240Sjfv /* Set media type */ 231173788Sjfv hw->phy.media_type = e1000_media_type_copper; 232169240Sjfv /* Set mta register count */ 233169240Sjfv mac->mta_reg_count = 128; 234169240Sjfv /* Set rar entry count */ 235169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 236169240Sjfv /* Set if part includes ASF firmware */ 237169240Sjfv mac->asf_firmware_present = TRUE; 238169240Sjfv 239169240Sjfv /* Function Pointers */ 240169240Sjfv 241169240Sjfv /* bus type/speed/width */ 242177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 243185353Sjfv /* function id */ 244185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 245169240Sjfv /* reset */ 246177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82541; 247169240Sjfv /* hw initialization */ 248177867Sjfv mac->ops.init_hw = e1000_init_hw_82541; 249169240Sjfv /* link setup */ 250177867Sjfv mac->ops.setup_link = e1000_setup_link_generic; 251169240Sjfv /* physical interface link setup */ 252177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 253169240Sjfv /* check for link */ 254177867Sjfv mac->ops.check_for_link = e1000_check_for_link_82541; 255169240Sjfv /* link info */ 256177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 257169240Sjfv /* multicast address update */ 258177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 259169240Sjfv /* writing VFTA */ 260177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 261169240Sjfv /* clearing VFTA */ 262177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 263200243Sjfv /* read mac address */ 264200243Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82541; 265190872Sjfv /* ID LED init */ 266190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 267169240Sjfv /* setup LED */ 268177867Sjfv mac->ops.setup_led = e1000_setup_led_82541; 269169240Sjfv /* cleanup LED */ 270177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_82541; 271169240Sjfv /* turn on/off LED */ 272177867Sjfv mac->ops.led_on = e1000_led_on_generic; 273177867Sjfv mac->ops.led_off = e1000_led_off_generic; 274169240Sjfv /* clear hardware counters */ 275177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 276169240Sjfv 277185353Sjfv return E1000_SUCCESS; 278169240Sjfv} 279169240Sjfv 280169240Sjfv/** 281169240Sjfv * e1000_init_function_pointers_82541 - Init func ptrs. 282169589Sjfv * @hw: pointer to the HW structure 283169240Sjfv * 284185353Sjfv * Called to initialize all function pointers and parameters. 285169240Sjfv **/ 286173788Sjfvvoid e1000_init_function_pointers_82541(struct e1000_hw *hw) 287169240Sjfv{ 288169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82541"); 289169240Sjfv 290177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82541; 291177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 292177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82541; 293169240Sjfv} 294169240Sjfv 295169240Sjfv/** 296169240Sjfv * e1000_reset_hw_82541 - Reset hardware 297169589Sjfv * @hw: pointer to the HW structure 298169240Sjfv * 299185353Sjfv * This resets the hardware into a known state. 300169240Sjfv **/ 301177867Sjfvstatic s32 e1000_reset_hw_82541(struct e1000_hw *hw) 302169240Sjfv{ 303235527Sjfv u32 ledctl, ctrl, icr, manc; 304169240Sjfv 305169240Sjfv DEBUGFUNC("e1000_reset_hw_82541"); 306169240Sjfv 307169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 308169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 309169240Sjfv 310169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 311169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 312169240Sjfv E1000_WRITE_FLUSH(hw); 313169240Sjfv 314173788Sjfv /* 315173788Sjfv * Delay to allow any outstanding PCI transactions to complete 316169240Sjfv * before resetting the device. 317169240Sjfv */ 318169240Sjfv msec_delay(10); 319169240Sjfv 320169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 321169240Sjfv 322169240Sjfv /* Must reset the Phy before resetting the MAC */ 323169240Sjfv if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 324169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 325169240Sjfv msec_delay(5); 326169240Sjfv } 327169240Sjfv 328169240Sjfv DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 329169240Sjfv switch (hw->mac.type) { 330169240Sjfv case e1000_82541: 331169240Sjfv case e1000_82541_rev_2: 332173788Sjfv /* 333173788Sjfv * These controllers can't ack the 64-bit write when 334169240Sjfv * issuing the reset, so we use IO-mapping as a 335169240Sjfv * workaround to issue the reset. 336169240Sjfv */ 337169240Sjfv E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 338169240Sjfv break; 339169240Sjfv default: 340169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 341169240Sjfv break; 342169240Sjfv } 343169240Sjfv 344169240Sjfv /* Wait for NVM reload */ 345169240Sjfv msec_delay(20); 346169240Sjfv 347169240Sjfv /* Disable HW ARPs on ASF enabled adapters */ 348169240Sjfv manc = E1000_READ_REG(hw, E1000_MANC); 349169240Sjfv manc &= ~E1000_MANC_ARP_EN; 350169240Sjfv E1000_WRITE_REG(hw, E1000_MANC, manc); 351169240Sjfv 352169240Sjfv if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 353169240Sjfv e1000_phy_init_script_82541(hw); 354169240Sjfv 355169240Sjfv /* Configure activity LED after Phy reset */ 356169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 357169240Sjfv ledctl &= IGP_ACTIVITY_LED_MASK; 358169240Sjfv ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 359169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 360169240Sjfv } 361169240Sjfv 362169240Sjfv /* Once again, mask the interrupts */ 363169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 364169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 365169240Sjfv 366169240Sjfv /* Clear any pending interrupt events. */ 367235527Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 368169240Sjfv 369169240Sjfv return E1000_SUCCESS; 370169240Sjfv} 371169240Sjfv 372169240Sjfv/** 373169240Sjfv * e1000_init_hw_82541 - Initialize hardware 374169589Sjfv * @hw: pointer to the HW structure 375169240Sjfv * 376185353Sjfv * This inits the hardware readying it for operation. 377169240Sjfv **/ 378177867Sjfvstatic s32 e1000_init_hw_82541(struct e1000_hw *hw) 379169240Sjfv{ 380169240Sjfv struct e1000_mac_info *mac = &hw->mac; 381194865Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 382169240Sjfv u32 i, txdctl; 383169240Sjfv s32 ret_val; 384169240Sjfv 385169240Sjfv DEBUGFUNC("e1000_init_hw_82541"); 386169240Sjfv 387169240Sjfv /* Initialize identification LED */ 388190872Sjfv ret_val = mac->ops.id_led_init(hw); 389169240Sjfv if (ret_val) { 390169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 391173788Sjfv /* This is not fatal and we should not stop init due to this */ 392169240Sjfv } 393235527Sjfv 394194865Sjfv /* Storing the Speed Power Down value for later use */ 395194865Sjfv ret_val = hw->phy.ops.read_reg(hw, 396194865Sjfv IGP01E1000_GMII_FIFO, 397194865Sjfv &dev_spec->spd_default); 398194865Sjfv if (ret_val) 399194865Sjfv goto out; 400169240Sjfv 401169240Sjfv /* Disabling VLAN filtering */ 402169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 403177867Sjfv mac->ops.clear_vfta(hw); 404169240Sjfv 405169240Sjfv /* Setup the receive address. */ 406169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 407169240Sjfv 408169240Sjfv /* Zero out the Multicast HASH table */ 409169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 410169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) { 411169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 412173788Sjfv /* 413173788Sjfv * Avoid back to back register writes by adding the register 414169240Sjfv * read (flush). This is to protect against some strange 415169240Sjfv * bridge configurations that may issue Memory Write Block 416169240Sjfv * (MWB) to our register space. 417169240Sjfv */ 418169240Sjfv E1000_WRITE_FLUSH(hw); 419169240Sjfv } 420169240Sjfv 421169240Sjfv /* Setup link and flow control */ 422177867Sjfv ret_val = mac->ops.setup_link(hw); 423169240Sjfv 424173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 425169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 426169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 427173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 428169240Sjfv 429173788Sjfv /* 430173788Sjfv * Clear all of the statistics registers (clear on read). It is 431169240Sjfv * important that we do this after we have tried to establish link 432169240Sjfv * because the symbol error count will increment wildly if there 433169240Sjfv * is no link. 434169240Sjfv */ 435169240Sjfv e1000_clear_hw_cntrs_82541(hw); 436169240Sjfv 437194865Sjfvout: 438169240Sjfv return ret_val; 439169240Sjfv} 440169240Sjfv 441169240Sjfv/** 442169240Sjfv * e1000_get_link_up_info_82541 - Report speed and duplex 443169589Sjfv * @hw: pointer to the HW structure 444169589Sjfv * @speed: pointer to speed buffer 445169589Sjfv * @duplex: pointer to duplex buffer 446169240Sjfv * 447169240Sjfv * Retrieve the current speed and duplex configuration. 448169240Sjfv **/ 449177867Sjfvstatic s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 450173788Sjfv u16 *duplex) 451169240Sjfv{ 452169240Sjfv struct e1000_phy_info *phy = &hw->phy; 453169240Sjfv s32 ret_val; 454169240Sjfv u16 data; 455169240Sjfv 456169240Sjfv DEBUGFUNC("e1000_get_link_up_info_82541"); 457169240Sjfv 458169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 459169240Sjfv if (ret_val) 460169240Sjfv goto out; 461169240Sjfv 462169240Sjfv if (!phy->speed_downgraded) 463169240Sjfv goto out; 464169240Sjfv 465173788Sjfv /* 466173788Sjfv * IGP01 PHY may advertise full duplex operation after speed 467169240Sjfv * downgrade even if it is operating at half duplex. 468169240Sjfv * Here we set the duplex settings to match the duplex in the 469169240Sjfv * link partner's capabilities. 470169240Sjfv */ 471177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 472169240Sjfv if (ret_val) 473169240Sjfv goto out; 474169240Sjfv 475173788Sjfv if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 476169240Sjfv *duplex = HALF_DUPLEX; 477173788Sjfv } else { 478177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 479169240Sjfv if (ret_val) 480169240Sjfv goto out; 481169240Sjfv 482169240Sjfv if (*speed == SPEED_100) { 483169240Sjfv if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 484169240Sjfv *duplex = HALF_DUPLEX; 485169240Sjfv } else if (*speed == SPEED_10) { 486169240Sjfv if (!(data & NWAY_LPAR_10T_FD_CAPS)) 487169240Sjfv *duplex = HALF_DUPLEX; 488169240Sjfv } 489169240Sjfv } 490169240Sjfv 491169240Sjfvout: 492169240Sjfv return ret_val; 493169240Sjfv} 494169240Sjfv 495169240Sjfv/** 496169240Sjfv * e1000_phy_hw_reset_82541 - PHY hardware reset 497169589Sjfv * @hw: pointer to the HW structure 498169240Sjfv * 499169240Sjfv * Verify the reset block is not blocking us from resetting. Acquire 500169240Sjfv * semaphore (if necessary) and read/set/write the device control reset 501169240Sjfv * bit in the PHY. Wait the appropriate delay time for the device to 502176667Sjfv * reset and release the semaphore (if necessary). 503169240Sjfv **/ 504177867Sjfvstatic s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 505169240Sjfv{ 506169240Sjfv s32 ret_val; 507169240Sjfv u32 ledctl; 508169240Sjfv 509169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_82541"); 510169240Sjfv 511169240Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 512169240Sjfv if (ret_val) 513169240Sjfv goto out; 514169240Sjfv 515169240Sjfv e1000_phy_init_script_82541(hw); 516169240Sjfv 517169240Sjfv if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 518169240Sjfv /* Configure activity LED after PHY reset */ 519169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 520169240Sjfv ledctl &= IGP_ACTIVITY_LED_MASK; 521169240Sjfv ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 522169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 523169240Sjfv } 524169240Sjfv 525169240Sjfvout: 526169240Sjfv return ret_val; 527169240Sjfv} 528169240Sjfv 529169240Sjfv/** 530169240Sjfv * e1000_setup_copper_link_82541 - Configure copper link settings 531169589Sjfv * @hw: pointer to the HW structure 532169240Sjfv * 533169240Sjfv * Calls the appropriate function to configure the link for auto-neg or forced 534169240Sjfv * speed and duplex. Then we check for link, once link is established calls 535169240Sjfv * to configure collision distance and flow control are called. If link is 536185353Sjfv * not established, we return -E1000_ERR_PHY (-2). 537169240Sjfv **/ 538177867Sjfvstatic s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 539169240Sjfv{ 540169240Sjfv struct e1000_phy_info *phy = &hw->phy; 541185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 542169240Sjfv s32 ret_val; 543169240Sjfv u32 ctrl, ledctl; 544169240Sjfv 545169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82541"); 546169240Sjfv 547169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 548169240Sjfv ctrl |= E1000_CTRL_SLU; 549169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 550169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 551169240Sjfv 552169240Sjfv /* Earlier revs of the IGP phy require us to force MDI. */ 553169240Sjfv if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 554169240Sjfv dev_spec->dsp_config = e1000_dsp_config_disabled; 555169240Sjfv phy->mdix = 1; 556173788Sjfv } else { 557169240Sjfv dev_spec->dsp_config = e1000_dsp_config_enabled; 558173788Sjfv } 559169240Sjfv 560169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 561169240Sjfv if (ret_val) 562169240Sjfv goto out; 563169240Sjfv 564169240Sjfv if (hw->mac.autoneg) { 565169240Sjfv if (dev_spec->ffe_config == e1000_ffe_config_active) 566169240Sjfv dev_spec->ffe_config = e1000_ffe_config_enabled; 567169240Sjfv } 568169240Sjfv 569169240Sjfv /* Configure activity LED after Phy reset */ 570169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 571169240Sjfv ledctl &= IGP_ACTIVITY_LED_MASK; 572169240Sjfv ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 573169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 574169240Sjfv 575169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 576169240Sjfv 577169240Sjfvout: 578169240Sjfv return ret_val; 579169240Sjfv} 580169240Sjfv 581169240Sjfv/** 582169240Sjfv * e1000_check_for_link_82541 - Check/Store link connection 583169589Sjfv * @hw: pointer to the HW structure 584169240Sjfv * 585169240Sjfv * This checks the link condition of the adapter and stores the 586185353Sjfv * results in the hw->mac structure. 587169240Sjfv **/ 588177867Sjfvstatic s32 e1000_check_for_link_82541(struct e1000_hw *hw) 589169240Sjfv{ 590169240Sjfv struct e1000_mac_info *mac = &hw->mac; 591169240Sjfv s32 ret_val; 592173788Sjfv bool link; 593169240Sjfv 594169240Sjfv DEBUGFUNC("e1000_check_for_link_82541"); 595169240Sjfv 596173788Sjfv /* 597173788Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 598169240Sjfv * has completed and/or if our link status has changed. The 599169240Sjfv * get_link_status flag is set upon receiving a Link Status 600169240Sjfv * Change or Rx Sequence Error interrupt. 601169240Sjfv */ 602169240Sjfv if (!mac->get_link_status) { 603169240Sjfv ret_val = E1000_SUCCESS; 604169240Sjfv goto out; 605169240Sjfv } 606169240Sjfv 607173788Sjfv /* 608173788Sjfv * First we want to see if the MII Status Register reports 609169240Sjfv * link. If so, then we want to get the current speed/duplex 610169240Sjfv * of the PHY. 611169240Sjfv */ 612169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 613169240Sjfv if (ret_val) 614169240Sjfv goto out; 615169240Sjfv 616169240Sjfv if (!link) { 617169240Sjfv ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 618169240Sjfv goto out; /* No link detected */ 619169240Sjfv } 620169240Sjfv 621169240Sjfv mac->get_link_status = FALSE; 622169240Sjfv 623173788Sjfv /* 624173788Sjfv * Check if there was DownShift, must be checked 625173788Sjfv * immediately after link-up 626173788Sjfv */ 627169240Sjfv e1000_check_downshift_generic(hw); 628169240Sjfv 629173788Sjfv /* 630173788Sjfv * If we are forcing speed/duplex, then we simply return since 631169240Sjfv * we have already determined whether we have link or not. 632169240Sjfv */ 633169240Sjfv if (!mac->autoneg) { 634169240Sjfv ret_val = -E1000_ERR_CONFIG; 635169240Sjfv goto out; 636169240Sjfv } 637169240Sjfv 638169240Sjfv ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 639169240Sjfv 640173788Sjfv /* 641173788Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 642169240Sjfv * of MAC speed/duplex configuration. So we only need to 643169240Sjfv * configure Collision Distance in the MAC. 644169240Sjfv */ 645238262Sjfv mac->ops.config_collision_dist(hw); 646169240Sjfv 647173788Sjfv /* 648173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 649169240Sjfv * First, we need to restore the desired flow control 650169240Sjfv * settings because we may have had to re-autoneg with a 651169240Sjfv * different link partner. 652169240Sjfv */ 653169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 654169240Sjfv if (ret_val) { 655169240Sjfv DEBUGOUT("Error configuring flow control\n"); 656169240Sjfv } 657169240Sjfv 658169240Sjfvout: 659169240Sjfv return ret_val; 660169240Sjfv} 661169240Sjfv 662169240Sjfv/** 663169240Sjfv * e1000_config_dsp_after_link_change_82541 - Config DSP after link 664169589Sjfv * @hw: pointer to the HW structure 665169589Sjfv * @link_up: boolean flag for link up status 666169240Sjfv * 667169240Sjfv * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 668169240Sjfv * at any other case. 669169240Sjfv * 670169240Sjfv * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 671169240Sjfv * gigabit link is achieved to improve link quality. 672169240Sjfv **/ 673173788Sjfvstatic s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 674173788Sjfv bool link_up) 675169240Sjfv{ 676169240Sjfv struct e1000_phy_info *phy = &hw->phy; 677185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 678169240Sjfv s32 ret_val; 679169240Sjfv u32 idle_errs = 0; 680169240Sjfv u16 phy_data, phy_saved_data, speed, duplex, i; 681169240Sjfv u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 682169240Sjfv u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 683169240Sjfv {IGP01E1000_PHY_AGC_PARAM_A, 684169240Sjfv IGP01E1000_PHY_AGC_PARAM_B, 685169240Sjfv IGP01E1000_PHY_AGC_PARAM_C, 686169240Sjfv IGP01E1000_PHY_AGC_PARAM_D}; 687169240Sjfv 688169240Sjfv DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 689169240Sjfv 690169240Sjfv if (link_up) { 691177867Sjfv ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 692169240Sjfv if (ret_val) { 693169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 694169240Sjfv goto out; 695169240Sjfv } 696169240Sjfv 697169240Sjfv if (speed != SPEED_1000) { 698169240Sjfv ret_val = E1000_SUCCESS; 699169240Sjfv goto out; 700169240Sjfv } 701169240Sjfv 702177867Sjfv ret_val = phy->ops.get_cable_length(hw); 703169240Sjfv if (ret_val) 704169240Sjfv goto out; 705169240Sjfv 706169240Sjfv if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 707169240Sjfv phy->min_cable_length >= 50) { 708169240Sjfv 709169240Sjfv for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 710177867Sjfv ret_val = phy->ops.read_reg(hw, 711169240Sjfv dsp_reg_array[i], 712169240Sjfv &phy_data); 713169240Sjfv if (ret_val) 714169240Sjfv goto out; 715169240Sjfv 716169240Sjfv phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 717169240Sjfv 718177867Sjfv ret_val = phy->ops.write_reg(hw, 719169240Sjfv dsp_reg_array[i], 720169240Sjfv phy_data); 721169240Sjfv if (ret_val) 722169240Sjfv goto out; 723169240Sjfv } 724169240Sjfv dev_spec->dsp_config = e1000_dsp_config_activated; 725169240Sjfv } 726169240Sjfv 727169240Sjfv if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 728169240Sjfv (phy->min_cable_length >= 50)) { 729169240Sjfv ret_val = E1000_SUCCESS; 730169240Sjfv goto out; 731169240Sjfv } 732169240Sjfv 733169240Sjfv /* clear previous idle error counts */ 734177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 735169240Sjfv if (ret_val) 736169240Sjfv goto out; 737169240Sjfv 738169240Sjfv for (i = 0; i < ffe_idle_err_timeout; i++) { 739169240Sjfv usec_delay(1000); 740177867Sjfv ret_val = phy->ops.read_reg(hw, 741169240Sjfv PHY_1000T_STATUS, 742169240Sjfv &phy_data); 743169240Sjfv if (ret_val) 744169240Sjfv goto out; 745169240Sjfv 746169240Sjfv idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 747169240Sjfv if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 748169240Sjfv dev_spec->ffe_config = e1000_ffe_config_active; 749169240Sjfv 750177867Sjfv ret_val = phy->ops.write_reg(hw, 751169240Sjfv IGP01E1000_PHY_DSP_FFE, 752169240Sjfv IGP01E1000_PHY_DSP_FFE_CM_CP); 753169240Sjfv if (ret_val) 754169240Sjfv goto out; 755169240Sjfv break; 756169240Sjfv } 757169240Sjfv 758169240Sjfv if (idle_errs) 759169240Sjfv ffe_idle_err_timeout = 760169240Sjfv FFE_IDLE_ERR_COUNT_TIMEOUT_100; 761169240Sjfv } 762169240Sjfv } else { 763169240Sjfv if (dev_spec->dsp_config == e1000_dsp_config_activated) { 764173788Sjfv /* 765173788Sjfv * Save off the current value of register 0x2F5B 766173788Sjfv * to be restored at the end of the routines. 767173788Sjfv */ 768177867Sjfv ret_val = phy->ops.read_reg(hw, 769169240Sjfv 0x2F5B, 770169240Sjfv &phy_saved_data); 771169240Sjfv if (ret_val) 772169240Sjfv goto out; 773169240Sjfv 774169240Sjfv /* Disable the PHY transmitter */ 775177867Sjfv ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 776169240Sjfv if (ret_val) 777169240Sjfv goto out; 778169240Sjfv 779169240Sjfv msec_delay_irq(20); 780169240Sjfv 781177867Sjfv ret_val = phy->ops.write_reg(hw, 782169240Sjfv 0x0000, 783169240Sjfv IGP01E1000_IEEE_FORCE_GIG); 784169240Sjfv if (ret_val) 785169240Sjfv goto out; 786169240Sjfv for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 787177867Sjfv ret_val = phy->ops.read_reg(hw, 788169240Sjfv dsp_reg_array[i], 789169240Sjfv &phy_data); 790169240Sjfv if (ret_val) 791169240Sjfv goto out; 792169240Sjfv 793169240Sjfv phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 794169240Sjfv phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 795169240Sjfv 796177867Sjfv ret_val = phy->ops.write_reg(hw, 797169240Sjfv dsp_reg_array[i], 798169240Sjfv phy_data); 799169240Sjfv if (ret_val) 800169240Sjfv goto out; 801169240Sjfv } 802169240Sjfv 803177867Sjfv ret_val = phy->ops.write_reg(hw, 804169240Sjfv 0x0000, 805169240Sjfv IGP01E1000_IEEE_RESTART_AUTONEG); 806169240Sjfv if (ret_val) 807169240Sjfv goto out; 808169240Sjfv 809169240Sjfv msec_delay_irq(20); 810169240Sjfv 811169240Sjfv /* Now enable the transmitter */ 812177867Sjfv ret_val = phy->ops.write_reg(hw, 813169240Sjfv 0x2F5B, 814169240Sjfv phy_saved_data); 815169240Sjfv if (ret_val) 816169240Sjfv goto out; 817169240Sjfv 818169240Sjfv dev_spec->dsp_config = e1000_dsp_config_enabled; 819169240Sjfv } 820169240Sjfv 821169240Sjfv if (dev_spec->ffe_config != e1000_ffe_config_active) { 822169240Sjfv ret_val = E1000_SUCCESS; 823169240Sjfv goto out; 824169240Sjfv } 825169240Sjfv 826173788Sjfv /* 827173788Sjfv * Save off the current value of register 0x2F5B 828173788Sjfv * to be restored at the end of the routines. 829173788Sjfv */ 830177867Sjfv ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 831169240Sjfv if (ret_val) 832169240Sjfv goto out; 833169240Sjfv 834169240Sjfv /* Disable the PHY transmitter */ 835177867Sjfv ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 836169240Sjfv if (ret_val) 837169240Sjfv goto out; 838169240Sjfv 839169240Sjfv msec_delay_irq(20); 840169240Sjfv 841177867Sjfv ret_val = phy->ops.write_reg(hw, 842169240Sjfv 0x0000, 843169240Sjfv IGP01E1000_IEEE_FORCE_GIG); 844169240Sjfv if (ret_val) 845169240Sjfv goto out; 846169240Sjfv 847177867Sjfv ret_val = phy->ops.write_reg(hw, 848169240Sjfv IGP01E1000_PHY_DSP_FFE, 849169240Sjfv IGP01E1000_PHY_DSP_FFE_DEFAULT); 850169240Sjfv if (ret_val) 851169240Sjfv goto out; 852169240Sjfv 853177867Sjfv ret_val = phy->ops.write_reg(hw, 854169240Sjfv 0x0000, 855169240Sjfv IGP01E1000_IEEE_RESTART_AUTONEG); 856169240Sjfv if (ret_val) 857169240Sjfv goto out; 858169240Sjfv 859169240Sjfv msec_delay_irq(20); 860169240Sjfv 861169240Sjfv /* Now enable the transmitter */ 862177867Sjfv ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 863169240Sjfv 864169240Sjfv if (ret_val) 865169240Sjfv goto out; 866169240Sjfv 867169240Sjfv dev_spec->ffe_config = e1000_ffe_config_enabled; 868169240Sjfv } 869169240Sjfv 870169240Sjfvout: 871169240Sjfv return ret_val; 872169240Sjfv} 873169240Sjfv 874169240Sjfv/** 875169240Sjfv * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 876169589Sjfv * @hw: pointer to the HW structure 877169240Sjfv * 878169240Sjfv * The automatic gain control (agc) normalizes the amplitude of the 879169240Sjfv * received signal, adjusting for the attenuation produced by the 880176667Sjfv * cable. By reading the AGC registers, which represent the 881176667Sjfv * combination of coarse and fine gain value, the value can be put 882169240Sjfv * into a lookup table to obtain the approximate cable length 883185353Sjfv * for each channel. 884169240Sjfv **/ 885177867Sjfvstatic s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 886169240Sjfv{ 887169240Sjfv struct e1000_phy_info *phy = &hw->phy; 888169240Sjfv s32 ret_val = E1000_SUCCESS; 889169240Sjfv u16 i, data; 890169240Sjfv u16 cur_agc_value, agc_value = 0; 891169240Sjfv u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 892169240Sjfv u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 893169240Sjfv {IGP01E1000_PHY_AGC_A, 894169240Sjfv IGP01E1000_PHY_AGC_B, 895169240Sjfv IGP01E1000_PHY_AGC_C, 896169240Sjfv IGP01E1000_PHY_AGC_D}; 897169240Sjfv 898169240Sjfv DEBUGFUNC("e1000_get_cable_length_igp_82541"); 899169240Sjfv 900169240Sjfv /* Read the AGC registers for all channels */ 901169240Sjfv for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 902177867Sjfv ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 903169240Sjfv if (ret_val) 904169240Sjfv goto out; 905169240Sjfv 906169240Sjfv cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 907169240Sjfv 908169240Sjfv /* Bounds checking */ 909169240Sjfv if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 910169240Sjfv (cur_agc_value == 0)) { 911169240Sjfv ret_val = -E1000_ERR_PHY; 912169240Sjfv goto out; 913169240Sjfv } 914169240Sjfv 915169240Sjfv agc_value += cur_agc_value; 916169240Sjfv 917169240Sjfv if (min_agc_value > cur_agc_value) 918169240Sjfv min_agc_value = cur_agc_value; 919169240Sjfv } 920169240Sjfv 921169240Sjfv /* Remove the minimal AGC result for length < 50m */ 922169240Sjfv if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 923169240Sjfv agc_value -= min_agc_value; 924169240Sjfv /* Average the three remaining channels for the length. */ 925169240Sjfv agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 926169240Sjfv } else { 927169240Sjfv /* Average the channels for the length. */ 928169240Sjfv agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 929169240Sjfv } 930169240Sjfv 931169240Sjfv phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 932169240Sjfv IGP01E1000_AGC_RANGE) 933169240Sjfv ? (e1000_igp_cable_length_table[agc_value] - 934169240Sjfv IGP01E1000_AGC_RANGE) 935169240Sjfv : 0; 936169240Sjfv phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 937169240Sjfv IGP01E1000_AGC_RANGE; 938169240Sjfv 939169240Sjfv phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 940169240Sjfv 941169240Sjfvout: 942169240Sjfv return ret_val; 943169240Sjfv} 944169240Sjfv 945169240Sjfv/** 946169240Sjfv * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 947169589Sjfv * @hw: pointer to the HW structure 948169589Sjfv * @active: boolean used to enable/disable lplu 949169240Sjfv * 950169240Sjfv * Success returns 0, Failure returns 1 951169240Sjfv * 952169240Sjfv * The low power link up (lplu) state is set to the power management level D3 953177867Sjfv * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 954169240Sjfv * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 955169240Sjfv * is used during Dx states where the power conservation is most important. 956169240Sjfv * During driver activity, SmartSpeed should be enabled so performance is 957185353Sjfv * maintained. 958169240Sjfv **/ 959177867Sjfvstatic s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 960169240Sjfv{ 961169240Sjfv struct e1000_phy_info *phy = &hw->phy; 962169240Sjfv s32 ret_val; 963169240Sjfv u16 data; 964169240Sjfv 965169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 966169240Sjfv 967169240Sjfv switch (hw->mac.type) { 968169240Sjfv case e1000_82541_rev_2: 969169240Sjfv case e1000_82547_rev_2: 970169240Sjfv break; 971169240Sjfv default: 972169240Sjfv ret_val = e1000_set_d3_lplu_state_generic(hw, active); 973169240Sjfv goto out; 974169240Sjfv break; 975169240Sjfv } 976169240Sjfv 977177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 978169240Sjfv if (ret_val) 979169240Sjfv goto out; 980169240Sjfv 981169240Sjfv if (!active) { 982169240Sjfv data &= ~IGP01E1000_GMII_FLEX_SPD; 983177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 984169240Sjfv if (ret_val) 985169240Sjfv goto out; 986169240Sjfv 987173788Sjfv /* 988173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 989169240Sjfv * during Dx states where the power conservation is most 990169240Sjfv * important. During driver activity we should enable 991173788Sjfv * SmartSpeed, so performance is maintained. 992173788Sjfv */ 993169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 994177867Sjfv ret_val = phy->ops.read_reg(hw, 995169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 996169240Sjfv &data); 997169240Sjfv if (ret_val) 998169240Sjfv goto out; 999169240Sjfv 1000169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1001177867Sjfv ret_val = phy->ops.write_reg(hw, 1002169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1003169240Sjfv data); 1004169240Sjfv if (ret_val) 1005169240Sjfv goto out; 1006169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1007177867Sjfv ret_val = phy->ops.read_reg(hw, 1008169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1009169240Sjfv &data); 1010169240Sjfv if (ret_val) 1011169240Sjfv goto out; 1012169240Sjfv 1013169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1014177867Sjfv ret_val = phy->ops.write_reg(hw, 1015169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1016169240Sjfv data); 1017169240Sjfv if (ret_val) 1018169240Sjfv goto out; 1019169240Sjfv } 1020169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1021169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1022169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1023169240Sjfv data |= IGP01E1000_GMII_FLEX_SPD; 1024177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1025169240Sjfv if (ret_val) 1026169240Sjfv goto out; 1027169240Sjfv 1028169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1029177867Sjfv ret_val = phy->ops.read_reg(hw, 1030169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1031169240Sjfv &data); 1032169240Sjfv if (ret_val) 1033169240Sjfv goto out; 1034169240Sjfv 1035169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1036177867Sjfv ret_val = phy->ops.write_reg(hw, 1037169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 1038169240Sjfv data); 1039169240Sjfv } 1040169240Sjfv 1041169240Sjfvout: 1042169240Sjfv return ret_val; 1043169240Sjfv} 1044169240Sjfv 1045169240Sjfv/** 1046169240Sjfv * e1000_setup_led_82541 - Configures SW controllable LED 1047169589Sjfv * @hw: pointer to the HW structure 1048169240Sjfv * 1049169240Sjfv * This prepares the SW controllable LED for use and saves the current state 1050185353Sjfv * of the LED so it can be later restored. 1051169240Sjfv **/ 1052177867Sjfvstatic s32 e1000_setup_led_82541(struct e1000_hw *hw) 1053169240Sjfv{ 1054185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1055169240Sjfv s32 ret_val; 1056169240Sjfv 1057169240Sjfv DEBUGFUNC("e1000_setup_led_82541"); 1058169240Sjfv 1059177867Sjfv ret_val = hw->phy.ops.read_reg(hw, 1060177867Sjfv IGP01E1000_GMII_FIFO, 1061177867Sjfv &dev_spec->spd_default); 1062169240Sjfv if (ret_val) 1063169240Sjfv goto out; 1064169240Sjfv 1065177867Sjfv ret_val = hw->phy.ops.write_reg(hw, 1066177867Sjfv IGP01E1000_GMII_FIFO, 1067177867Sjfv (u16)(dev_spec->spd_default & 1068169240Sjfv ~IGP01E1000_GMII_SPD)); 1069169240Sjfv if (ret_val) 1070169240Sjfv goto out; 1071169240Sjfv 1072169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1073169240Sjfv 1074169240Sjfvout: 1075169240Sjfv return ret_val; 1076169240Sjfv} 1077169240Sjfv 1078169240Sjfv/** 1079169240Sjfv * e1000_cleanup_led_82541 - Set LED config to default operation 1080169589Sjfv * @hw: pointer to the HW structure 1081169240Sjfv * 1082169240Sjfv * Remove the current LED configuration and set the LED configuration 1083185353Sjfv * to the default value, saved from the EEPROM. 1084169240Sjfv **/ 1085177867Sjfvstatic s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1086169240Sjfv{ 1087185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1088169240Sjfv s32 ret_val; 1089169240Sjfv 1090169240Sjfv DEBUGFUNC("e1000_cleanup_led_82541"); 1091169240Sjfv 1092177867Sjfv ret_val = hw->phy.ops.write_reg(hw, 1093177867Sjfv IGP01E1000_GMII_FIFO, 1094177867Sjfv dev_spec->spd_default); 1095169240Sjfv if (ret_val) 1096169240Sjfv goto out; 1097169240Sjfv 1098169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1099169240Sjfv 1100169240Sjfvout: 1101169240Sjfv return ret_val; 1102169240Sjfv} 1103169240Sjfv 1104169240Sjfv/** 1105169240Sjfv * e1000_phy_init_script_82541 - Initialize GbE PHY 1106169589Sjfv * @hw: pointer to the HW structure 1107169240Sjfv * 1108169240Sjfv * Initializes the IGP PHY. 1109169240Sjfv **/ 1110173788Sjfvstatic s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1111169240Sjfv{ 1112185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1113169240Sjfv u32 ret_val; 1114169240Sjfv u16 phy_saved_data; 1115169240Sjfv 1116169240Sjfv DEBUGFUNC("e1000_phy_init_script_82541"); 1117169240Sjfv 1118169240Sjfv if (!dev_spec->phy_init_script) { 1119169240Sjfv ret_val = E1000_SUCCESS; 1120169240Sjfv goto out; 1121169240Sjfv } 1122169240Sjfv 1123169240Sjfv /* Delay after phy reset to enable NVM configuration to load */ 1124169240Sjfv msec_delay(20); 1125169240Sjfv 1126173788Sjfv /* 1127173788Sjfv * Save off the current value of register 0x2F5B to be restored at 1128173788Sjfv * the end of this routine. 1129173788Sjfv */ 1130177867Sjfv ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1131169240Sjfv 1132169240Sjfv /* Disabled the PHY transmitter */ 1133177867Sjfv hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1134169240Sjfv 1135169240Sjfv msec_delay(20); 1136169240Sjfv 1137177867Sjfv hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1138169240Sjfv 1139169240Sjfv msec_delay(5); 1140169240Sjfv 1141169240Sjfv switch (hw->mac.type) { 1142169240Sjfv case e1000_82541: 1143169240Sjfv case e1000_82547: 1144177867Sjfv hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1145169240Sjfv 1146177867Sjfv hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1147169240Sjfv 1148177867Sjfv hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1149169240Sjfv 1150177867Sjfv hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1151169240Sjfv 1152177867Sjfv hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1153169240Sjfv 1154177867Sjfv hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1155169240Sjfv 1156177867Sjfv hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1157169240Sjfv 1158177867Sjfv hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1159169240Sjfv 1160177867Sjfv hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1161169240Sjfv break; 1162169240Sjfv case e1000_82541_rev_2: 1163169240Sjfv case e1000_82547_rev_2: 1164177867Sjfv hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1165169240Sjfv break; 1166169240Sjfv default: 1167169240Sjfv break; 1168169240Sjfv } 1169169240Sjfv 1170177867Sjfv hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1171169240Sjfv 1172169240Sjfv msec_delay(20); 1173169240Sjfv 1174169240Sjfv /* Now enable the transmitter */ 1175177867Sjfv hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1176169240Sjfv 1177169240Sjfv if (hw->mac.type == e1000_82547) { 1178169240Sjfv u16 fused, fine, coarse; 1179169240Sjfv 1180169240Sjfv /* Move to analog registers page */ 1181177867Sjfv hw->phy.ops.read_reg(hw, 1182169240Sjfv IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1183169240Sjfv &fused); 1184169240Sjfv 1185169240Sjfv if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1186177867Sjfv hw->phy.ops.read_reg(hw, 1187169240Sjfv IGP01E1000_ANALOG_FUSE_STATUS, 1188169240Sjfv &fused); 1189169240Sjfv 1190169240Sjfv fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1191169240Sjfv coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1192169240Sjfv 1193169240Sjfv if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1194169240Sjfv coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1195169240Sjfv fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1196169240Sjfv } else if (coarse == 1197169240Sjfv IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1198169240Sjfv fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1199169240Sjfv 1200169240Sjfv fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1201169240Sjfv (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1202169240Sjfv (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1203169240Sjfv 1204177867Sjfv hw->phy.ops.write_reg(hw, 1205169240Sjfv IGP01E1000_ANALOG_FUSE_CONTROL, 1206169240Sjfv fused); 1207177867Sjfv hw->phy.ops.write_reg(hw, 1208169240Sjfv IGP01E1000_ANALOG_FUSE_BYPASS, 1209169240Sjfv IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1210169240Sjfv } 1211169240Sjfv } 1212169240Sjfv 1213169240Sjfvout: 1214169240Sjfv return ret_val; 1215169240Sjfv} 1216169240Sjfv 1217169240Sjfv/** 1218169240Sjfv * e1000_init_script_state_82541 - Enable/Disable PHY init script 1219169589Sjfv * @hw: pointer to the HW structure 1220169589Sjfv * @state: boolean value used to enable/disable PHY init script 1221169240Sjfv * 1222169240Sjfv * Allows the driver to enable/disable the PHY init script, if the PHY is an 1223185353Sjfv * IGP PHY. 1224169240Sjfv **/ 1225173788Sjfvvoid e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1226169240Sjfv{ 1227185353Sjfv struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1228169240Sjfv 1229169240Sjfv DEBUGFUNC("e1000_init_script_state_82541"); 1230169240Sjfv 1231169240Sjfv if (hw->phy.type != e1000_phy_igp) { 1232169240Sjfv DEBUGOUT("Initialization script not necessary.\n"); 1233169240Sjfv goto out; 1234169240Sjfv } 1235169240Sjfv 1236169240Sjfv dev_spec->phy_init_script = state; 1237169240Sjfv 1238169240Sjfvout: 1239169240Sjfv return; 1240169240Sjfv} 1241169240Sjfv 1242169240Sjfv/** 1243173788Sjfv * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1244173788Sjfv * @hw: pointer to the HW structure 1245173788Sjfv * 1246173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1247173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1248173788Sjfv **/ 1249177867Sjfvstatic void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1250173788Sjfv{ 1251173788Sjfv /* If the management interface is not enabled, then power down */ 1252173788Sjfv if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1253173788Sjfv e1000_power_down_phy_copper(hw); 1254173788Sjfv 1255173788Sjfv return; 1256173788Sjfv} 1257173788Sjfv 1258173788Sjfv/** 1259169240Sjfv * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1260169589Sjfv * @hw: pointer to the HW structure 1261169240Sjfv * 1262169240Sjfv * Clears the hardware counters by reading the counter registers. 1263169240Sjfv **/ 1264177867Sjfvstatic void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1265169240Sjfv{ 1266169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1267169240Sjfv 1268169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1269169240Sjfv 1270185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1271185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1272185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1273185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1274185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1275185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1276185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1277185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1278185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1279185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1280185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1281185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 1282169240Sjfv 1283185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 1284185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 1285185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 1286185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 1287185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 1288185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 1289169240Sjfv 1290185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 1291185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 1292185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 1293169240Sjfv} 1294200243Sjfv 1295200243Sjfv/** 1296200243Sjfv * e1000_read_mac_addr_82541 - Read device MAC address 1297200243Sjfv * @hw: pointer to the HW structure 1298200243Sjfv * 1299200243Sjfv * Reads the device MAC address from the EEPROM and stores the value. 1300200243Sjfv **/ 1301200243Sjfvstatic s32 e1000_read_mac_addr_82541(struct e1000_hw *hw) 1302200243Sjfv{ 1303200243Sjfv s32 ret_val = E1000_SUCCESS; 1304200243Sjfv u16 offset, nvm_data, i; 1305200243Sjfv 1306200243Sjfv DEBUGFUNC("e1000_read_mac_addr"); 1307200243Sjfv 1308200243Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1309200243Sjfv offset = i >> 1; 1310200243Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1311200243Sjfv if (ret_val) { 1312200243Sjfv DEBUGOUT("NVM Read Error\n"); 1313200243Sjfv goto out; 1314200243Sjfv } 1315200243Sjfv hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1316200243Sjfv hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1317200243Sjfv } 1318200243Sjfv 1319200243Sjfv for (i = 0; i < ETH_ADDR_LEN; i++) 1320200243Sjfv hw->mac.addr[i] = hw->mac.perm_addr[i]; 1321200243Sjfv 1322200243Sjfvout: 1323200243Sjfv return ret_val; 1324200243Sjfv} 1325200243Sjfv 1326