1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2007-8 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice shall be included in 13254885Sdumbbell * all copies or substantial portions of the Software. 14254885Sdumbbell * 15254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 22254885Sdumbbell * 23254885Sdumbbell * Authors: Dave Airlie 24254885Sdumbbell * Alex Deucher 25254885Sdumbbell */ 26254885Sdumbbell 27254885Sdumbbell#include <sys/cdefs.h> 28254885Sdumbbell__FBSDID("$FreeBSD$"); 29254885Sdumbbell 30254885Sdumbbell#include <dev/drm2/drmP.h> 31254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 32254885Sdumbbell#include "radeon.h" 33254885Sdumbbell 34254885Sdumbbell#include "atom.h" 35254885Sdumbbell 36254885Sdumbbell#include <dev/drm2/drm_crtc_helper.h> 37254885Sdumbbell#include <dev/drm2/drm_edid.h> 38254885Sdumbbell 39254885Sdumbbellstatic void avivo_crtc_load_lut(struct drm_crtc *crtc) 40254885Sdumbbell{ 41254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42254885Sdumbbell struct drm_device *dev = crtc->dev; 43254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 44254885Sdumbbell int i; 45254885Sdumbbell 46254885Sdumbbell DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47254885Sdumbbell WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48254885Sdumbbell 49254885Sdumbbell WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50254885Sdumbbell WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51254885Sdumbbell WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52254885Sdumbbell 53254885Sdumbbell WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54254885Sdumbbell WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55254885Sdumbbell WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56254885Sdumbbell 57254885Sdumbbell WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58254885Sdumbbell WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59254885Sdumbbell WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60254885Sdumbbell 61254885Sdumbbell WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62254885Sdumbbell for (i = 0; i < 256; i++) { 63254885Sdumbbell WREG32(AVIVO_DC_LUT_30_COLOR, 64254885Sdumbbell (radeon_crtc->lut_r[i] << 20) | 65254885Sdumbbell (radeon_crtc->lut_g[i] << 10) | 66254885Sdumbbell (radeon_crtc->lut_b[i] << 0)); 67254885Sdumbbell } 68254885Sdumbbell 69254885Sdumbbell WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 70254885Sdumbbell} 71254885Sdumbbell 72254885Sdumbbellstatic void dce4_crtc_load_lut(struct drm_crtc *crtc) 73254885Sdumbbell{ 74254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 75254885Sdumbbell struct drm_device *dev = crtc->dev; 76254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 77254885Sdumbbell int i; 78254885Sdumbbell 79254885Sdumbbell DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 80254885Sdumbbell WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 81254885Sdumbbell 82254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 83254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 84254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 85254885Sdumbbell 86254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 87254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 88254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 89254885Sdumbbell 90254885Sdumbbell WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 91254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 92254885Sdumbbell 93254885Sdumbbell WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 94254885Sdumbbell for (i = 0; i < 256; i++) { 95254885Sdumbbell WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 96254885Sdumbbell (radeon_crtc->lut_r[i] << 20) | 97254885Sdumbbell (radeon_crtc->lut_g[i] << 10) | 98254885Sdumbbell (radeon_crtc->lut_b[i] << 0)); 99254885Sdumbbell } 100254885Sdumbbell} 101254885Sdumbbell 102254885Sdumbbellstatic void dce5_crtc_load_lut(struct drm_crtc *crtc) 103254885Sdumbbell{ 104254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 105254885Sdumbbell struct drm_device *dev = crtc->dev; 106254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 107254885Sdumbbell int i; 108254885Sdumbbell 109254885Sdumbbell DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 110254885Sdumbbell 111254885Sdumbbell WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 112254885Sdumbbell (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 113254885Sdumbbell NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 114254885Sdumbbell WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 115254885Sdumbbell NI_GRPH_PRESCALE_BYPASS); 116254885Sdumbbell WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 117254885Sdumbbell NI_OVL_PRESCALE_BYPASS); 118254885Sdumbbell WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 119254885Sdumbbell (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 120254885Sdumbbell NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 121254885Sdumbbell 122254885Sdumbbell WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 123254885Sdumbbell 124254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 125254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 126254885Sdumbbell WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 127254885Sdumbbell 128254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 129254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 130254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 131254885Sdumbbell 132254885Sdumbbell WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 133254885Sdumbbell WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 134254885Sdumbbell 135254885Sdumbbell WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 136254885Sdumbbell for (i = 0; i < 256; i++) { 137254885Sdumbbell WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 138254885Sdumbbell (radeon_crtc->lut_r[i] << 20) | 139254885Sdumbbell (radeon_crtc->lut_g[i] << 10) | 140254885Sdumbbell (radeon_crtc->lut_b[i] << 0)); 141254885Sdumbbell } 142254885Sdumbbell 143254885Sdumbbell WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 144254885Sdumbbell (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 145254885Sdumbbell NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146254885Sdumbbell NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147254885Sdumbbell NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 148254885Sdumbbell WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 149254885Sdumbbell (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 150254885Sdumbbell NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 151254885Sdumbbell WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 152254885Sdumbbell (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 153254885Sdumbbell NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 154254885Sdumbbell WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 155254885Sdumbbell (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 156254885Sdumbbell NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 157254885Sdumbbell /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 158254885Sdumbbell WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 159254885Sdumbbell 160254885Sdumbbell} 161254885Sdumbbell 162254885Sdumbbellstatic void legacy_crtc_load_lut(struct drm_crtc *crtc) 163254885Sdumbbell{ 164254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 165254885Sdumbbell struct drm_device *dev = crtc->dev; 166254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 167254885Sdumbbell int i; 168254885Sdumbbell uint32_t dac2_cntl; 169254885Sdumbbell 170254885Sdumbbell dac2_cntl = RREG32(RADEON_DAC_CNTL2); 171254885Sdumbbell if (radeon_crtc->crtc_id == 0) 172254885Sdumbbell dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 173254885Sdumbbell else 174254885Sdumbbell dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 175254885Sdumbbell WREG32(RADEON_DAC_CNTL2, dac2_cntl); 176254885Sdumbbell 177254885Sdumbbell WREG8(RADEON_PALETTE_INDEX, 0); 178254885Sdumbbell for (i = 0; i < 256; i++) { 179254885Sdumbbell WREG32(RADEON_PALETTE_30_DATA, 180254885Sdumbbell (radeon_crtc->lut_r[i] << 20) | 181254885Sdumbbell (radeon_crtc->lut_g[i] << 10) | 182254885Sdumbbell (radeon_crtc->lut_b[i] << 0)); 183254885Sdumbbell } 184254885Sdumbbell} 185254885Sdumbbell 186254885Sdumbbellvoid radeon_crtc_load_lut(struct drm_crtc *crtc) 187254885Sdumbbell{ 188254885Sdumbbell struct drm_device *dev = crtc->dev; 189254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 190254885Sdumbbell 191254885Sdumbbell if (!crtc->enabled) 192254885Sdumbbell return; 193254885Sdumbbell 194254885Sdumbbell if (ASIC_IS_DCE5(rdev)) 195254885Sdumbbell dce5_crtc_load_lut(crtc); 196254885Sdumbbell else if (ASIC_IS_DCE4(rdev)) 197254885Sdumbbell dce4_crtc_load_lut(crtc); 198254885Sdumbbell else if (ASIC_IS_AVIVO(rdev)) 199254885Sdumbbell avivo_crtc_load_lut(crtc); 200254885Sdumbbell else 201254885Sdumbbell legacy_crtc_load_lut(crtc); 202254885Sdumbbell} 203254885Sdumbbell 204254885Sdumbbell/** Sets the color ramps on behalf of fbcon */ 205254885Sdumbbellvoid radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 206254885Sdumbbell u16 blue, int regno) 207254885Sdumbbell{ 208254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 209254885Sdumbbell 210254885Sdumbbell radeon_crtc->lut_r[regno] = red >> 6; 211254885Sdumbbell radeon_crtc->lut_g[regno] = green >> 6; 212254885Sdumbbell radeon_crtc->lut_b[regno] = blue >> 6; 213254885Sdumbbell} 214254885Sdumbbell 215254885Sdumbbell/** Gets the color ramps on behalf of fbcon */ 216254885Sdumbbellvoid radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 217254885Sdumbbell u16 *blue, int regno) 218254885Sdumbbell{ 219254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 220254885Sdumbbell 221254885Sdumbbell *red = radeon_crtc->lut_r[regno] << 6; 222254885Sdumbbell *green = radeon_crtc->lut_g[regno] << 6; 223254885Sdumbbell *blue = radeon_crtc->lut_b[regno] << 6; 224254885Sdumbbell} 225254885Sdumbbell 226254885Sdumbbellstatic void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 227254885Sdumbbell u16 *blue, uint32_t start, uint32_t size) 228254885Sdumbbell{ 229254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 230254885Sdumbbell int end = (start + size > 256) ? 256 : start + size, i; 231254885Sdumbbell 232254885Sdumbbell /* userspace palettes are always correct as is */ 233254885Sdumbbell for (i = start; i < end; i++) { 234254885Sdumbbell radeon_crtc->lut_r[i] = red[i] >> 6; 235254885Sdumbbell radeon_crtc->lut_g[i] = green[i] >> 6; 236254885Sdumbbell radeon_crtc->lut_b[i] = blue[i] >> 6; 237254885Sdumbbell } 238254885Sdumbbell radeon_crtc_load_lut(crtc); 239254885Sdumbbell} 240254885Sdumbbell 241254885Sdumbbellstatic void radeon_crtc_destroy(struct drm_crtc *crtc) 242254885Sdumbbell{ 243254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 244254885Sdumbbell 245254885Sdumbbell drm_crtc_cleanup(crtc); 246254885Sdumbbell free(radeon_crtc, DRM_MEM_DRIVER); 247254885Sdumbbell} 248254885Sdumbbell 249254885Sdumbbell/* 250254885Sdumbbell * Handle unpin events outside the interrupt handler proper. 251254885Sdumbbell */ 252254885Sdumbbellstatic void radeon_unpin_work_func(void *arg, int pending) 253254885Sdumbbell{ 254254885Sdumbbell struct radeon_unpin_work *work = arg; 255254885Sdumbbell int r; 256254885Sdumbbell 257254885Sdumbbell /* unpin of the old buffer */ 258254885Sdumbbell r = radeon_bo_reserve(work->old_rbo, false); 259254885Sdumbbell if (likely(r == 0)) { 260254885Sdumbbell r = radeon_bo_unpin(work->old_rbo); 261254885Sdumbbell if (unlikely(r != 0)) { 262254885Sdumbbell DRM_ERROR("failed to unpin buffer after flip\n"); 263254885Sdumbbell } 264254885Sdumbbell radeon_bo_unreserve(work->old_rbo); 265254885Sdumbbell } else 266254885Sdumbbell DRM_ERROR("failed to reserve buffer after flip\n"); 267254885Sdumbbell 268254885Sdumbbell drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 269254885Sdumbbell free(work, DRM_MEM_DRIVER); 270254885Sdumbbell} 271254885Sdumbbell 272254885Sdumbbellvoid radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 273254885Sdumbbell{ 274254885Sdumbbell struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 275254885Sdumbbell struct radeon_unpin_work *work; 276254885Sdumbbell struct drm_pending_vblank_event *e; 277254885Sdumbbell struct timeval now; 278254885Sdumbbell unsigned long flags; 279254885Sdumbbell u32 update_pending; 280254885Sdumbbell int vpos, hpos; 281254885Sdumbbell 282254885Sdumbbell DRM_SPINLOCK_IRQSAVE(&rdev->ddev->event_lock, flags); 283254885Sdumbbell work = radeon_crtc->unpin_work; 284254885Sdumbbell if (work == NULL || 285254885Sdumbbell (work->fence && !radeon_fence_signaled(work->fence))) { 286254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags); 287254885Sdumbbell return; 288254885Sdumbbell } 289254885Sdumbbell /* New pageflip, or just completion of a previous one? */ 290254885Sdumbbell if (!radeon_crtc->deferred_flip_completion) { 291254885Sdumbbell /* do the flip (mmio) */ 292254885Sdumbbell update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); 293254885Sdumbbell } else { 294254885Sdumbbell /* This is just a completion of a flip queued in crtc 295254885Sdumbbell * at last invocation. Make sure we go directly to 296254885Sdumbbell * completion routine. 297254885Sdumbbell */ 298254885Sdumbbell update_pending = 0; 299254885Sdumbbell radeon_crtc->deferred_flip_completion = 0; 300254885Sdumbbell } 301254885Sdumbbell 302254885Sdumbbell /* Has the pageflip already completed in crtc, or is it certain 303254885Sdumbbell * to complete in this vblank? 304254885Sdumbbell */ 305254885Sdumbbell if (update_pending && 306254885Sdumbbell (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 307254885Sdumbbell &vpos, &hpos)) && 308254885Sdumbbell ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 309254885Sdumbbell (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 310254885Sdumbbell /* crtc didn't flip in this target vblank interval, 311254885Sdumbbell * but flip is pending in crtc. Based on the current 312254885Sdumbbell * scanout position we know that the current frame is 313254885Sdumbbell * (nearly) complete and the flip will (likely) 314254885Sdumbbell * complete before the start of the next frame. 315254885Sdumbbell */ 316254885Sdumbbell update_pending = 0; 317254885Sdumbbell } 318254885Sdumbbell if (update_pending) { 319254885Sdumbbell /* crtc didn't flip in this target vblank interval, 320254885Sdumbbell * but flip is pending in crtc. It will complete it 321254885Sdumbbell * in next vblank interval, so complete the flip at 322254885Sdumbbell * next vblank irq. 323254885Sdumbbell */ 324254885Sdumbbell radeon_crtc->deferred_flip_completion = 1; 325254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags); 326254885Sdumbbell return; 327254885Sdumbbell } 328254885Sdumbbell 329254885Sdumbbell /* Pageflip (will be) certainly completed in this vblank. Clean up. */ 330254885Sdumbbell radeon_crtc->unpin_work = NULL; 331254885Sdumbbell 332254885Sdumbbell /* wakeup userspace */ 333254885Sdumbbell if (work->event) { 334254885Sdumbbell e = work->event; 335254885Sdumbbell e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); 336254885Sdumbbell e->event.tv_sec = now.tv_sec; 337254885Sdumbbell e->event.tv_usec = now.tv_usec; 338254885Sdumbbell list_add_tail(&e->base.link, &e->base.file_priv->event_list); 339263170Sdumbbell drm_event_wakeup(&e->base); 340254885Sdumbbell } 341254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags); 342254885Sdumbbell 343254885Sdumbbell drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 344254885Sdumbbell radeon_fence_unref(&work->fence); 345254885Sdumbbell radeon_post_page_flip(work->rdev, work->crtc_id); 346254885Sdumbbell taskqueue_enqueue(rdev->tq, &work->work); 347254885Sdumbbell} 348254885Sdumbbell 349254885Sdumbbellstatic int radeon_crtc_page_flip(struct drm_crtc *crtc, 350254885Sdumbbell struct drm_framebuffer *fb, 351254885Sdumbbell struct drm_pending_vblank_event *event) 352254885Sdumbbell{ 353254885Sdumbbell struct drm_device *dev = crtc->dev; 354254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 355254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 356254885Sdumbbell struct radeon_framebuffer *old_radeon_fb; 357254885Sdumbbell struct radeon_framebuffer *new_radeon_fb; 358254885Sdumbbell struct drm_gem_object *obj; 359254885Sdumbbell struct radeon_bo *rbo; 360254885Sdumbbell struct radeon_unpin_work *work; 361254885Sdumbbell unsigned long flags; 362254885Sdumbbell u32 tiling_flags, pitch_pixels; 363254885Sdumbbell u64 base; 364254885Sdumbbell int r; 365254885Sdumbbell 366254885Sdumbbell work = malloc(sizeof *work, DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 367254885Sdumbbell if (work == NULL) 368254885Sdumbbell return -ENOMEM; 369254885Sdumbbell 370254885Sdumbbell work->event = event; 371254885Sdumbbell work->rdev = rdev; 372254885Sdumbbell work->crtc_id = radeon_crtc->crtc_id; 373254885Sdumbbell old_radeon_fb = to_radeon_framebuffer(crtc->fb); 374254885Sdumbbell new_radeon_fb = to_radeon_framebuffer(fb); 375254885Sdumbbell /* schedule unpin of the old buffer */ 376254885Sdumbbell obj = old_radeon_fb->obj; 377254885Sdumbbell /* take a reference to the old object */ 378254885Sdumbbell drm_gem_object_reference(obj); 379254885Sdumbbell rbo = gem_to_radeon_bo(obj); 380254885Sdumbbell work->old_rbo = rbo; 381254885Sdumbbell obj = new_radeon_fb->obj; 382254885Sdumbbell rbo = gem_to_radeon_bo(obj); 383254885Sdumbbell 384254885Sdumbbell mtx_lock(&rbo->tbo.bdev->fence_lock); 385254885Sdumbbell if (rbo->tbo.sync_obj) 386254885Sdumbbell work->fence = radeon_fence_ref(rbo->tbo.sync_obj); 387254885Sdumbbell mtx_unlock(&rbo->tbo.bdev->fence_lock); 388254885Sdumbbell 389254885Sdumbbell TASK_INIT(&work->work, 0, radeon_unpin_work_func, work); 390254885Sdumbbell 391254885Sdumbbell /* We borrow the event spin lock for protecting unpin_work */ 392254885Sdumbbell DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags); 393254885Sdumbbell if (radeon_crtc->unpin_work) { 394254885Sdumbbell DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 395254885Sdumbbell r = -EBUSY; 396254885Sdumbbell goto unlock_free; 397254885Sdumbbell } 398254885Sdumbbell radeon_crtc->unpin_work = work; 399254885Sdumbbell radeon_crtc->deferred_flip_completion = 0; 400254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags); 401254885Sdumbbell 402254885Sdumbbell /* pin the new buffer */ 403254885Sdumbbell DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", 404254885Sdumbbell work->old_rbo, rbo); 405254885Sdumbbell 406254885Sdumbbell r = radeon_bo_reserve(rbo, false); 407254885Sdumbbell if (unlikely(r != 0)) { 408254885Sdumbbell DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 409254885Sdumbbell goto pflip_cleanup; 410254885Sdumbbell } 411254885Sdumbbell /* Only 27 bit offset for legacy CRTC */ 412254885Sdumbbell r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 413254885Sdumbbell ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 414254885Sdumbbell if (unlikely(r != 0)) { 415254885Sdumbbell radeon_bo_unreserve(rbo); 416254885Sdumbbell r = -EINVAL; 417254885Sdumbbell DRM_ERROR("failed to pin new rbo buffer before flip\n"); 418254885Sdumbbell goto pflip_cleanup; 419254885Sdumbbell } 420254885Sdumbbell radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 421254885Sdumbbell radeon_bo_unreserve(rbo); 422254885Sdumbbell 423254885Sdumbbell if (!ASIC_IS_AVIVO(rdev)) { 424254885Sdumbbell /* crtc offset is from display base addr not FB location */ 425254885Sdumbbell base -= radeon_crtc->legacy_display_base_addr; 426254885Sdumbbell pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 427254885Sdumbbell 428254885Sdumbbell if (tiling_flags & RADEON_TILING_MACRO) { 429254885Sdumbbell if (ASIC_IS_R300(rdev)) { 430254885Sdumbbell base &= ~0x7ff; 431254885Sdumbbell } else { 432254885Sdumbbell int byteshift = fb->bits_per_pixel >> 4; 433254885Sdumbbell int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 434254885Sdumbbell base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 435254885Sdumbbell } 436254885Sdumbbell } else { 437254885Sdumbbell int offset = crtc->y * pitch_pixels + crtc->x; 438254885Sdumbbell switch (fb->bits_per_pixel) { 439254885Sdumbbell case 8: 440254885Sdumbbell default: 441254885Sdumbbell offset *= 1; 442254885Sdumbbell break; 443254885Sdumbbell case 15: 444254885Sdumbbell case 16: 445254885Sdumbbell offset *= 2; 446254885Sdumbbell break; 447254885Sdumbbell case 24: 448254885Sdumbbell offset *= 3; 449254885Sdumbbell break; 450254885Sdumbbell case 32: 451254885Sdumbbell offset *= 4; 452254885Sdumbbell break; 453254885Sdumbbell } 454254885Sdumbbell base += offset; 455254885Sdumbbell } 456254885Sdumbbell base &= ~7; 457254885Sdumbbell } 458254885Sdumbbell 459254885Sdumbbell DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags); 460254885Sdumbbell work->new_crtc_base = base; 461254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags); 462254885Sdumbbell 463254885Sdumbbell /* update crtc fb */ 464254885Sdumbbell crtc->fb = fb; 465254885Sdumbbell 466254885Sdumbbell r = drm_vblank_get(dev, radeon_crtc->crtc_id); 467254885Sdumbbell if (r) { 468254885Sdumbbell DRM_ERROR("failed to get vblank before flip\n"); 469254885Sdumbbell goto pflip_cleanup1; 470254885Sdumbbell } 471254885Sdumbbell 472254885Sdumbbell /* set the proper interrupt */ 473254885Sdumbbell radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); 474254885Sdumbbell 475254885Sdumbbell return 0; 476254885Sdumbbell 477254885Sdumbbellpflip_cleanup1: 478254885Sdumbbell if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { 479254885Sdumbbell DRM_ERROR("failed to reserve new rbo in error path\n"); 480254885Sdumbbell goto pflip_cleanup; 481254885Sdumbbell } 482254885Sdumbbell if (unlikely(radeon_bo_unpin(rbo) != 0)) { 483254885Sdumbbell DRM_ERROR("failed to unpin new rbo in error path\n"); 484254885Sdumbbell } 485254885Sdumbbell radeon_bo_unreserve(rbo); 486254885Sdumbbell 487254885Sdumbbellpflip_cleanup: 488254885Sdumbbell DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags); 489254885Sdumbbell radeon_crtc->unpin_work = NULL; 490254885Sdumbbellunlock_free: 491254885Sdumbbell DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags); 492254885Sdumbbell drm_gem_object_unreference_unlocked(old_radeon_fb->obj); 493254885Sdumbbell radeon_fence_unref(&work->fence); 494254885Sdumbbell free(work, DRM_MEM_DRIVER); 495254885Sdumbbell 496254885Sdumbbell return r; 497254885Sdumbbell} 498254885Sdumbbell 499254885Sdumbbellstatic const struct drm_crtc_funcs radeon_crtc_funcs = { 500254885Sdumbbell .cursor_set = radeon_crtc_cursor_set, 501254885Sdumbbell .cursor_move = radeon_crtc_cursor_move, 502254885Sdumbbell .gamma_set = radeon_crtc_gamma_set, 503254885Sdumbbell .set_config = drm_crtc_helper_set_config, 504254885Sdumbbell .destroy = radeon_crtc_destroy, 505254885Sdumbbell .page_flip = radeon_crtc_page_flip, 506254885Sdumbbell}; 507254885Sdumbbell 508254885Sdumbbellstatic void radeon_crtc_init(struct drm_device *dev, int index) 509254885Sdumbbell{ 510254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 511254885Sdumbbell struct radeon_crtc *radeon_crtc; 512254885Sdumbbell int i; 513254885Sdumbbell 514254885Sdumbbell radeon_crtc = malloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 515254885Sdumbbell if (radeon_crtc == NULL) 516254885Sdumbbell return; 517254885Sdumbbell 518254885Sdumbbell drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 519254885Sdumbbell 520254885Sdumbbell drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 521254885Sdumbbell radeon_crtc->crtc_id = index; 522254885Sdumbbell rdev->mode_info.crtcs[index] = radeon_crtc; 523254885Sdumbbell 524254885Sdumbbell#if 0 525254885Sdumbbell radeon_crtc->mode_set.crtc = &radeon_crtc->base; 526254885Sdumbbell radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 527254885Sdumbbell radeon_crtc->mode_set.num_connectors = 0; 528254885Sdumbbell#endif 529254885Sdumbbell 530254885Sdumbbell for (i = 0; i < 256; i++) { 531254885Sdumbbell radeon_crtc->lut_r[i] = i << 2; 532254885Sdumbbell radeon_crtc->lut_g[i] = i << 2; 533254885Sdumbbell radeon_crtc->lut_b[i] = i << 2; 534254885Sdumbbell } 535254885Sdumbbell 536254885Sdumbbell if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 537254885Sdumbbell radeon_atombios_init_crtc(dev, radeon_crtc); 538254885Sdumbbell else 539254885Sdumbbell radeon_legacy_init_crtc(dev, radeon_crtc); 540254885Sdumbbell} 541254885Sdumbbell 542254885Sdumbbellstatic const char *encoder_names[37] = { 543254885Sdumbbell "NONE", 544254885Sdumbbell "INTERNAL_LVDS", 545254885Sdumbbell "INTERNAL_TMDS1", 546254885Sdumbbell "INTERNAL_TMDS2", 547254885Sdumbbell "INTERNAL_DAC1", 548254885Sdumbbell "INTERNAL_DAC2", 549254885Sdumbbell "INTERNAL_SDVOA", 550254885Sdumbbell "INTERNAL_SDVOB", 551254885Sdumbbell "SI170B", 552254885Sdumbbell "CH7303", 553254885Sdumbbell "CH7301", 554254885Sdumbbell "INTERNAL_DVO1", 555254885Sdumbbell "EXTERNAL_SDVOA", 556254885Sdumbbell "EXTERNAL_SDVOB", 557254885Sdumbbell "TITFP513", 558254885Sdumbbell "INTERNAL_LVTM1", 559254885Sdumbbell "VT1623", 560254885Sdumbbell "HDMI_SI1930", 561254885Sdumbbell "HDMI_INTERNAL", 562254885Sdumbbell "INTERNAL_KLDSCP_TMDS1", 563254885Sdumbbell "INTERNAL_KLDSCP_DVO1", 564254885Sdumbbell "INTERNAL_KLDSCP_DAC1", 565254885Sdumbbell "INTERNAL_KLDSCP_DAC2", 566254885Sdumbbell "SI178", 567254885Sdumbbell "MVPU_FPGA", 568254885Sdumbbell "INTERNAL_DDI", 569254885Sdumbbell "VT1625", 570254885Sdumbbell "HDMI_SI1932", 571254885Sdumbbell "DP_AN9801", 572254885Sdumbbell "DP_DP501", 573254885Sdumbbell "INTERNAL_UNIPHY", 574254885Sdumbbell "INTERNAL_KLDSCP_LVTMA", 575254885Sdumbbell "INTERNAL_UNIPHY1", 576254885Sdumbbell "INTERNAL_UNIPHY2", 577254885Sdumbbell "NUTMEG", 578254885Sdumbbell "TRAVIS", 579254885Sdumbbell "INTERNAL_VCE" 580254885Sdumbbell}; 581254885Sdumbbell 582254885Sdumbbellstatic const char *hpd_names[6] = { 583254885Sdumbbell "HPD1", 584254885Sdumbbell "HPD2", 585254885Sdumbbell "HPD3", 586254885Sdumbbell "HPD4", 587254885Sdumbbell "HPD5", 588254885Sdumbbell "HPD6", 589254885Sdumbbell}; 590254885Sdumbbell 591254885Sdumbbellstatic void radeon_print_display_setup(struct drm_device *dev) 592254885Sdumbbell{ 593254885Sdumbbell struct drm_connector *connector; 594254885Sdumbbell struct radeon_connector *radeon_connector; 595254885Sdumbbell struct drm_encoder *encoder; 596254885Sdumbbell struct radeon_encoder *radeon_encoder; 597254885Sdumbbell uint32_t devices; 598254885Sdumbbell int i = 0; 599254885Sdumbbell 600254885Sdumbbell DRM_INFO("Radeon Display Connectors\n"); 601254885Sdumbbell list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 602254885Sdumbbell radeon_connector = to_radeon_connector(connector); 603254885Sdumbbell DRM_INFO("Connector %d:\n", i); 604254885Sdumbbell DRM_INFO(" %s\n", drm_get_connector_name(connector)); 605254885Sdumbbell if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 606254885Sdumbbell DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 607254885Sdumbbell if (radeon_connector->ddc_bus) { 608254885Sdumbbell DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 609254885Sdumbbell radeon_connector->ddc_bus->rec.mask_clk_reg, 610254885Sdumbbell radeon_connector->ddc_bus->rec.mask_data_reg, 611254885Sdumbbell radeon_connector->ddc_bus->rec.a_clk_reg, 612254885Sdumbbell radeon_connector->ddc_bus->rec.a_data_reg, 613254885Sdumbbell radeon_connector->ddc_bus->rec.en_clk_reg, 614254885Sdumbbell radeon_connector->ddc_bus->rec.en_data_reg, 615254885Sdumbbell radeon_connector->ddc_bus->rec.y_clk_reg, 616254885Sdumbbell radeon_connector->ddc_bus->rec.y_data_reg); 617254885Sdumbbell if (radeon_connector->router.ddc_valid) 618254885Sdumbbell DRM_INFO(" DDC Router 0x%x/0x%x\n", 619254885Sdumbbell radeon_connector->router.ddc_mux_control_pin, 620254885Sdumbbell radeon_connector->router.ddc_mux_state); 621254885Sdumbbell if (radeon_connector->router.cd_valid) 622254885Sdumbbell DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 623254885Sdumbbell radeon_connector->router.cd_mux_control_pin, 624254885Sdumbbell radeon_connector->router.cd_mux_state); 625254885Sdumbbell } else { 626254885Sdumbbell if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 627254885Sdumbbell connector->connector_type == DRM_MODE_CONNECTOR_DVII || 628254885Sdumbbell connector->connector_type == DRM_MODE_CONNECTOR_DVID || 629254885Sdumbbell connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 630254885Sdumbbell connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 631254885Sdumbbell connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 632254885Sdumbbell DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 633254885Sdumbbell } 634254885Sdumbbell DRM_INFO(" Encoders:\n"); 635254885Sdumbbell list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 636254885Sdumbbell radeon_encoder = to_radeon_encoder(encoder); 637254885Sdumbbell devices = radeon_encoder->devices & radeon_connector->devices; 638254885Sdumbbell if (devices) { 639254885Sdumbbell if (devices & ATOM_DEVICE_CRT1_SUPPORT) 640254885Sdumbbell DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 641254885Sdumbbell if (devices & ATOM_DEVICE_CRT2_SUPPORT) 642254885Sdumbbell DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 643254885Sdumbbell if (devices & ATOM_DEVICE_LCD1_SUPPORT) 644254885Sdumbbell DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 645254885Sdumbbell if (devices & ATOM_DEVICE_DFP1_SUPPORT) 646254885Sdumbbell DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 647254885Sdumbbell if (devices & ATOM_DEVICE_DFP2_SUPPORT) 648254885Sdumbbell DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 649254885Sdumbbell if (devices & ATOM_DEVICE_DFP3_SUPPORT) 650254885Sdumbbell DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 651254885Sdumbbell if (devices & ATOM_DEVICE_DFP4_SUPPORT) 652254885Sdumbbell DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 653254885Sdumbbell if (devices & ATOM_DEVICE_DFP5_SUPPORT) 654254885Sdumbbell DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 655254885Sdumbbell if (devices & ATOM_DEVICE_DFP6_SUPPORT) 656254885Sdumbbell DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 657254885Sdumbbell if (devices & ATOM_DEVICE_TV1_SUPPORT) 658254885Sdumbbell DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 659254885Sdumbbell if (devices & ATOM_DEVICE_CV_SUPPORT) 660254885Sdumbbell DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 661254885Sdumbbell } 662254885Sdumbbell } 663254885Sdumbbell i++; 664254885Sdumbbell } 665254885Sdumbbell} 666254885Sdumbbell 667254885Sdumbbellstatic bool radeon_setup_enc_conn(struct drm_device *dev) 668254885Sdumbbell{ 669254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 670254885Sdumbbell bool ret = false; 671254885Sdumbbell 672254885Sdumbbell if (rdev->bios) { 673254885Sdumbbell if (rdev->is_atom_bios) { 674254885Sdumbbell ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 675254885Sdumbbell if (ret == false) 676254885Sdumbbell ret = radeon_get_atom_connector_info_from_object_table(dev); 677254885Sdumbbell } else { 678254885Sdumbbell ret = radeon_get_legacy_connector_info_from_bios(dev); 679254885Sdumbbell if (ret == false) 680254885Sdumbbell ret = radeon_get_legacy_connector_info_from_table(dev); 681254885Sdumbbell } 682254885Sdumbbell } else { 683254885Sdumbbell if (!ASIC_IS_AVIVO(rdev)) 684254885Sdumbbell ret = radeon_get_legacy_connector_info_from_table(dev); 685254885Sdumbbell } 686254885Sdumbbell if (ret) { 687254885Sdumbbell radeon_setup_encoder_clones(dev); 688254885Sdumbbell radeon_print_display_setup(dev); 689254885Sdumbbell } 690254885Sdumbbell 691254885Sdumbbell return ret; 692254885Sdumbbell} 693254885Sdumbbell 694254885Sdumbbellint radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 695254885Sdumbbell{ 696254885Sdumbbell struct drm_device *dev = radeon_connector->base.dev; 697254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 698254885Sdumbbell int ret = 0; 699254885Sdumbbell 700254885Sdumbbell /* on hw with routers, select right port */ 701254885Sdumbbell if (radeon_connector->router.ddc_valid) 702254885Sdumbbell radeon_router_select_ddc_port(radeon_connector); 703254885Sdumbbell 704254885Sdumbbell if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 705254885Sdumbbell ENCODER_OBJECT_ID_NONE) { 706254885Sdumbbell struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 707254885Sdumbbell 708254885Sdumbbell if (dig->dp_i2c_bus) 709254885Sdumbbell radeon_connector->edid = drm_get_edid(&radeon_connector->base, 710254885Sdumbbell dig->dp_i2c_bus->adapter); 711254885Sdumbbell } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 712254885Sdumbbell (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 713254885Sdumbbell struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 714254885Sdumbbell 715254885Sdumbbell if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 716254885Sdumbbell dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 717254885Sdumbbell radeon_connector->edid = drm_get_edid(&radeon_connector->base, 718254885Sdumbbell dig->dp_i2c_bus->adapter); 719254885Sdumbbell else if (radeon_connector->ddc_bus && !radeon_connector->edid) 720254885Sdumbbell radeon_connector->edid = drm_get_edid(&radeon_connector->base, 721254885Sdumbbell radeon_connector->ddc_bus->adapter); 722254885Sdumbbell } else { 723254885Sdumbbell if (radeon_connector->ddc_bus && !radeon_connector->edid) 724254885Sdumbbell radeon_connector->edid = drm_get_edid(&radeon_connector->base, 725254885Sdumbbell radeon_connector->ddc_bus->adapter); 726254885Sdumbbell } 727254885Sdumbbell 728254885Sdumbbell if (!radeon_connector->edid) { 729254885Sdumbbell if (rdev->is_atom_bios) { 730254885Sdumbbell /* some laptops provide a hardcoded edid in rom for LCDs */ 731254885Sdumbbell if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || 732254885Sdumbbell (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) 733254885Sdumbbell radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 734254885Sdumbbell } else 735254885Sdumbbell /* some servers provide a hardcoded edid in rom for KVMs */ 736254885Sdumbbell radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 737254885Sdumbbell } 738254885Sdumbbell if (radeon_connector->edid) { 739254885Sdumbbell drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 740254885Sdumbbell ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 741254885Sdumbbell return ret; 742254885Sdumbbell } 743254885Sdumbbell drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 744254885Sdumbbell return 0; 745254885Sdumbbell} 746254885Sdumbbell 747254885Sdumbbell/* avivo */ 748254885Sdumbbellstatic void avivo_get_fb_div(struct radeon_pll *pll, 749254885Sdumbbell u32 target_clock, 750254885Sdumbbell u32 post_div, 751254885Sdumbbell u32 ref_div, 752254885Sdumbbell u32 *fb_div, 753254885Sdumbbell u32 *frac_fb_div) 754254885Sdumbbell{ 755254885Sdumbbell u32 tmp = post_div * ref_div; 756254885Sdumbbell 757254885Sdumbbell tmp *= target_clock; 758254885Sdumbbell *fb_div = tmp / pll->reference_freq; 759254885Sdumbbell *frac_fb_div = tmp % pll->reference_freq; 760254885Sdumbbell 761254885Sdumbbell if (*fb_div > pll->max_feedback_div) 762254885Sdumbbell *fb_div = pll->max_feedback_div; 763254885Sdumbbell else if (*fb_div < pll->min_feedback_div) 764254885Sdumbbell *fb_div = pll->min_feedback_div; 765254885Sdumbbell} 766254885Sdumbbell 767254885Sdumbbellstatic u32 avivo_get_post_div(struct radeon_pll *pll, 768254885Sdumbbell u32 target_clock) 769254885Sdumbbell{ 770254885Sdumbbell u32 vco, post_div, tmp; 771254885Sdumbbell 772254885Sdumbbell if (pll->flags & RADEON_PLL_USE_POST_DIV) 773254885Sdumbbell return pll->post_div; 774254885Sdumbbell 775254885Sdumbbell if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 776254885Sdumbbell if (pll->flags & RADEON_PLL_IS_LCD) 777254885Sdumbbell vco = pll->lcd_pll_out_min; 778254885Sdumbbell else 779254885Sdumbbell vco = pll->pll_out_min; 780254885Sdumbbell } else { 781254885Sdumbbell if (pll->flags & RADEON_PLL_IS_LCD) 782254885Sdumbbell vco = pll->lcd_pll_out_max; 783254885Sdumbbell else 784254885Sdumbbell vco = pll->pll_out_max; 785254885Sdumbbell } 786254885Sdumbbell 787254885Sdumbbell post_div = vco / target_clock; 788254885Sdumbbell tmp = vco % target_clock; 789254885Sdumbbell 790254885Sdumbbell if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 791254885Sdumbbell if (tmp) 792254885Sdumbbell post_div++; 793254885Sdumbbell } else { 794254885Sdumbbell if (!tmp) 795254885Sdumbbell post_div--; 796254885Sdumbbell } 797254885Sdumbbell 798254885Sdumbbell if (post_div > pll->max_post_div) 799254885Sdumbbell post_div = pll->max_post_div; 800254885Sdumbbell else if (post_div < pll->min_post_div) 801254885Sdumbbell post_div = pll->min_post_div; 802254885Sdumbbell 803254885Sdumbbell return post_div; 804254885Sdumbbell} 805254885Sdumbbell 806254885Sdumbbell#define MAX_TOLERANCE 10 807254885Sdumbbell 808254885Sdumbbellvoid radeon_compute_pll_avivo(struct radeon_pll *pll, 809254885Sdumbbell u32 freq, 810254885Sdumbbell u32 *dot_clock_p, 811254885Sdumbbell u32 *fb_div_p, 812254885Sdumbbell u32 *frac_fb_div_p, 813254885Sdumbbell u32 *ref_div_p, 814254885Sdumbbell u32 *post_div_p) 815254885Sdumbbell{ 816254885Sdumbbell u32 target_clock = freq / 10; 817254885Sdumbbell u32 post_div = avivo_get_post_div(pll, target_clock); 818254885Sdumbbell u32 ref_div = pll->min_ref_div; 819254885Sdumbbell u32 fb_div = 0, frac_fb_div = 0, tmp; 820254885Sdumbbell 821254885Sdumbbell if (pll->flags & RADEON_PLL_USE_REF_DIV) 822254885Sdumbbell ref_div = pll->reference_div; 823254885Sdumbbell 824254885Sdumbbell if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 825254885Sdumbbell avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); 826254885Sdumbbell frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; 827254885Sdumbbell if (frac_fb_div >= 5) { 828254885Sdumbbell frac_fb_div -= 5; 829254885Sdumbbell frac_fb_div = frac_fb_div / 10; 830254885Sdumbbell frac_fb_div++; 831254885Sdumbbell } 832254885Sdumbbell if (frac_fb_div >= 10) { 833254885Sdumbbell fb_div++; 834254885Sdumbbell frac_fb_div = 0; 835254885Sdumbbell } 836254885Sdumbbell } else { 837254885Sdumbbell while (ref_div <= pll->max_ref_div) { 838254885Sdumbbell avivo_get_fb_div(pll, target_clock, post_div, ref_div, 839254885Sdumbbell &fb_div, &frac_fb_div); 840254885Sdumbbell if (frac_fb_div >= (pll->reference_freq / 2)) 841254885Sdumbbell fb_div++; 842254885Sdumbbell frac_fb_div = 0; 843254885Sdumbbell tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); 844254885Sdumbbell tmp = (tmp * 10000) / target_clock; 845254885Sdumbbell 846254885Sdumbbell if (tmp > (10000 + MAX_TOLERANCE)) 847254885Sdumbbell ref_div++; 848254885Sdumbbell else if (tmp >= (10000 - MAX_TOLERANCE)) 849254885Sdumbbell break; 850254885Sdumbbell else 851254885Sdumbbell ref_div++; 852254885Sdumbbell } 853254885Sdumbbell } 854254885Sdumbbell 855254885Sdumbbell *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / 856254885Sdumbbell (ref_div * post_div * 10); 857254885Sdumbbell *fb_div_p = fb_div; 858254885Sdumbbell *frac_fb_div_p = frac_fb_div; 859254885Sdumbbell *ref_div_p = ref_div; 860254885Sdumbbell *post_div_p = post_div; 861254885Sdumbbell DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", 862254885Sdumbbell *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); 863254885Sdumbbell} 864254885Sdumbbell 865254885Sdumbbell/* pre-avivo */ 866254885Sdumbbellstatic inline uint32_t radeon_div(uint64_t n, uint32_t d) 867254885Sdumbbell{ 868254885Sdumbbell uint64_t mod; 869254885Sdumbbell 870254885Sdumbbell n += d / 2; 871254885Sdumbbell 872254885Sdumbbell mod = do_div(n, d); 873254885Sdumbbell return n; 874254885Sdumbbell} 875254885Sdumbbell 876254885Sdumbbellvoid radeon_compute_pll_legacy(struct radeon_pll *pll, 877254885Sdumbbell uint64_t freq, 878254885Sdumbbell uint32_t *dot_clock_p, 879254885Sdumbbell uint32_t *fb_div_p, 880254885Sdumbbell uint32_t *frac_fb_div_p, 881254885Sdumbbell uint32_t *ref_div_p, 882254885Sdumbbell uint32_t *post_div_p) 883254885Sdumbbell{ 884254885Sdumbbell uint32_t min_ref_div = pll->min_ref_div; 885254885Sdumbbell uint32_t max_ref_div = pll->max_ref_div; 886254885Sdumbbell uint32_t min_post_div = pll->min_post_div; 887254885Sdumbbell uint32_t max_post_div = pll->max_post_div; 888254885Sdumbbell uint32_t min_fractional_feed_div = 0; 889254885Sdumbbell uint32_t max_fractional_feed_div = 0; 890254885Sdumbbell uint32_t best_vco = pll->best_vco; 891254885Sdumbbell uint32_t best_post_div = 1; 892254885Sdumbbell uint32_t best_ref_div = 1; 893254885Sdumbbell uint32_t best_feedback_div = 1; 894254885Sdumbbell uint32_t best_frac_feedback_div = 0; 895254885Sdumbbell uint32_t best_freq = -1; 896254885Sdumbbell uint32_t best_error = 0xffffffff; 897254885Sdumbbell uint32_t best_vco_diff = 1; 898254885Sdumbbell uint32_t post_div; 899254885Sdumbbell u32 pll_out_min, pll_out_max; 900254885Sdumbbell 901254885Sdumbbell DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div); 902254885Sdumbbell freq = freq * 1000; 903254885Sdumbbell 904254885Sdumbbell if (pll->flags & RADEON_PLL_IS_LCD) { 905254885Sdumbbell pll_out_min = pll->lcd_pll_out_min; 906254885Sdumbbell pll_out_max = pll->lcd_pll_out_max; 907254885Sdumbbell } else { 908254885Sdumbbell pll_out_min = pll->pll_out_min; 909254885Sdumbbell pll_out_max = pll->pll_out_max; 910254885Sdumbbell } 911254885Sdumbbell 912254885Sdumbbell if (pll_out_min > 64800) 913254885Sdumbbell pll_out_min = 64800; 914254885Sdumbbell 915254885Sdumbbell if (pll->flags & RADEON_PLL_USE_REF_DIV) 916254885Sdumbbell min_ref_div = max_ref_div = pll->reference_div; 917254885Sdumbbell else { 918254885Sdumbbell while (min_ref_div < max_ref_div-1) { 919254885Sdumbbell uint32_t mid = (min_ref_div + max_ref_div) / 2; 920254885Sdumbbell uint32_t pll_in = pll->reference_freq / mid; 921254885Sdumbbell if (pll_in < pll->pll_in_min) 922254885Sdumbbell max_ref_div = mid; 923254885Sdumbbell else if (pll_in > pll->pll_in_max) 924254885Sdumbbell min_ref_div = mid; 925254885Sdumbbell else 926254885Sdumbbell break; 927254885Sdumbbell } 928254885Sdumbbell } 929254885Sdumbbell 930254885Sdumbbell if (pll->flags & RADEON_PLL_USE_POST_DIV) 931254885Sdumbbell min_post_div = max_post_div = pll->post_div; 932254885Sdumbbell 933254885Sdumbbell if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 934254885Sdumbbell min_fractional_feed_div = pll->min_frac_feedback_div; 935254885Sdumbbell max_fractional_feed_div = pll->max_frac_feedback_div; 936254885Sdumbbell } 937254885Sdumbbell 938254885Sdumbbell for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 939254885Sdumbbell uint32_t ref_div; 940254885Sdumbbell 941254885Sdumbbell if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 942254885Sdumbbell continue; 943254885Sdumbbell 944254885Sdumbbell /* legacy radeons only have a few post_divs */ 945254885Sdumbbell if (pll->flags & RADEON_PLL_LEGACY) { 946254885Sdumbbell if ((post_div == 5) || 947254885Sdumbbell (post_div == 7) || 948254885Sdumbbell (post_div == 9) || 949254885Sdumbbell (post_div == 10) || 950254885Sdumbbell (post_div == 11) || 951254885Sdumbbell (post_div == 13) || 952254885Sdumbbell (post_div == 14) || 953254885Sdumbbell (post_div == 15)) 954254885Sdumbbell continue; 955254885Sdumbbell } 956254885Sdumbbell 957254885Sdumbbell for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 958254885Sdumbbell uint32_t feedback_div, current_freq = 0, error, vco_diff; 959254885Sdumbbell uint32_t pll_in = pll->reference_freq / ref_div; 960254885Sdumbbell uint32_t min_feed_div = pll->min_feedback_div; 961254885Sdumbbell uint32_t max_feed_div = pll->max_feedback_div + 1; 962254885Sdumbbell 963254885Sdumbbell if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 964254885Sdumbbell continue; 965254885Sdumbbell 966254885Sdumbbell while (min_feed_div < max_feed_div) { 967254885Sdumbbell uint32_t vco; 968254885Sdumbbell uint32_t min_frac_feed_div = min_fractional_feed_div; 969254885Sdumbbell uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 970254885Sdumbbell uint32_t frac_feedback_div; 971254885Sdumbbell uint64_t tmp; 972254885Sdumbbell 973254885Sdumbbell feedback_div = (min_feed_div + max_feed_div) / 2; 974254885Sdumbbell 975254885Sdumbbell tmp = (uint64_t)pll->reference_freq * feedback_div; 976254885Sdumbbell vco = radeon_div(tmp, ref_div); 977254885Sdumbbell 978254885Sdumbbell if (vco < pll_out_min) { 979254885Sdumbbell min_feed_div = feedback_div + 1; 980254885Sdumbbell continue; 981254885Sdumbbell } else if (vco > pll_out_max) { 982254885Sdumbbell max_feed_div = feedback_div; 983254885Sdumbbell continue; 984254885Sdumbbell } 985254885Sdumbbell 986254885Sdumbbell while (min_frac_feed_div < max_frac_feed_div) { 987254885Sdumbbell frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 988254885Sdumbbell tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 989254885Sdumbbell tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 990254885Sdumbbell current_freq = radeon_div(tmp, ref_div * post_div); 991254885Sdumbbell 992254885Sdumbbell if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 993254885Sdumbbell if (freq < current_freq) 994254885Sdumbbell error = 0xffffffff; 995254885Sdumbbell else 996254885Sdumbbell error = freq - current_freq; 997254885Sdumbbell } else 998254885Sdumbbell error = abs(current_freq - freq); 999254885Sdumbbell vco_diff = abs(vco - best_vco); 1000254885Sdumbbell 1001254885Sdumbbell if ((best_vco == 0 && error < best_error) || 1002254885Sdumbbell (best_vco != 0 && 1003254885Sdumbbell ((best_error > 100 && error < best_error - 100) || 1004254885Sdumbbell (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1005254885Sdumbbell best_post_div = post_div; 1006254885Sdumbbell best_ref_div = ref_div; 1007254885Sdumbbell best_feedback_div = feedback_div; 1008254885Sdumbbell best_frac_feedback_div = frac_feedback_div; 1009254885Sdumbbell best_freq = current_freq; 1010254885Sdumbbell best_error = error; 1011254885Sdumbbell best_vco_diff = vco_diff; 1012254885Sdumbbell } else if (current_freq == freq) { 1013254885Sdumbbell if (best_freq == -1) { 1014254885Sdumbbell best_post_div = post_div; 1015254885Sdumbbell best_ref_div = ref_div; 1016254885Sdumbbell best_feedback_div = feedback_div; 1017254885Sdumbbell best_frac_feedback_div = frac_feedback_div; 1018254885Sdumbbell best_freq = current_freq; 1019254885Sdumbbell best_error = error; 1020254885Sdumbbell best_vco_diff = vco_diff; 1021254885Sdumbbell } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1022254885Sdumbbell ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1023254885Sdumbbell ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1024254885Sdumbbell ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1025254885Sdumbbell ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1026254885Sdumbbell ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1027254885Sdumbbell best_post_div = post_div; 1028254885Sdumbbell best_ref_div = ref_div; 1029254885Sdumbbell best_feedback_div = feedback_div; 1030254885Sdumbbell best_frac_feedback_div = frac_feedback_div; 1031254885Sdumbbell best_freq = current_freq; 1032254885Sdumbbell best_error = error; 1033254885Sdumbbell best_vco_diff = vco_diff; 1034254885Sdumbbell } 1035254885Sdumbbell } 1036254885Sdumbbell if (current_freq < freq) 1037254885Sdumbbell min_frac_feed_div = frac_feedback_div + 1; 1038254885Sdumbbell else 1039254885Sdumbbell max_frac_feed_div = frac_feedback_div; 1040254885Sdumbbell } 1041254885Sdumbbell if (current_freq < freq) 1042254885Sdumbbell min_feed_div = feedback_div + 1; 1043254885Sdumbbell else 1044254885Sdumbbell max_feed_div = feedback_div; 1045254885Sdumbbell } 1046254885Sdumbbell } 1047254885Sdumbbell } 1048254885Sdumbbell 1049254885Sdumbbell *dot_clock_p = best_freq / 10000; 1050254885Sdumbbell *fb_div_p = best_feedback_div; 1051254885Sdumbbell *frac_fb_div_p = best_frac_feedback_div; 1052254885Sdumbbell *ref_div_p = best_ref_div; 1053254885Sdumbbell *post_div_p = best_post_div; 1054254885Sdumbbell DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1055254885Sdumbbell (long long)freq, 1056254885Sdumbbell best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1057254885Sdumbbell best_ref_div, best_post_div); 1058254885Sdumbbell 1059254885Sdumbbell} 1060254885Sdumbbell 1061254885Sdumbbellstatic void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1062254885Sdumbbell{ 1063254885Sdumbbell struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1064254885Sdumbbell 1065254885Sdumbbell if (radeon_fb->obj) { 1066254885Sdumbbell drm_gem_object_unreference_unlocked(radeon_fb->obj); 1067254885Sdumbbell } 1068254885Sdumbbell drm_framebuffer_cleanup(fb); 1069254885Sdumbbell free(radeon_fb, DRM_MEM_DRIVER); 1070254885Sdumbbell} 1071254885Sdumbbell 1072254885Sdumbbellstatic int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1073254885Sdumbbell struct drm_file *file_priv, 1074254885Sdumbbell unsigned int *handle) 1075254885Sdumbbell{ 1076254885Sdumbbell struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1077254885Sdumbbell 1078254885Sdumbbell return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1079254885Sdumbbell} 1080254885Sdumbbell 1081254885Sdumbbellstatic const struct drm_framebuffer_funcs radeon_fb_funcs = { 1082254885Sdumbbell .destroy = radeon_user_framebuffer_destroy, 1083254885Sdumbbell .create_handle = radeon_user_framebuffer_create_handle, 1084254885Sdumbbell}; 1085254885Sdumbbell 1086254885Sdumbbellint 1087254885Sdumbbellradeon_framebuffer_init(struct drm_device *dev, 1088254885Sdumbbell struct radeon_framebuffer *rfb, 1089254885Sdumbbell struct drm_mode_fb_cmd2 *mode_cmd, 1090254885Sdumbbell struct drm_gem_object *obj) 1091254885Sdumbbell{ 1092254885Sdumbbell int ret; 1093254885Sdumbbell rfb->obj = obj; 1094254885Sdumbbell ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1095254885Sdumbbell if (ret) { 1096254885Sdumbbell rfb->obj = NULL; 1097254885Sdumbbell return ret; 1098254885Sdumbbell } 1099254885Sdumbbell drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1100254885Sdumbbell return 0; 1101254885Sdumbbell} 1102254885Sdumbbell 1103254885Sdumbbellstatic int 1104254885Sdumbbellradeon_user_framebuffer_create(struct drm_device *dev, 1105254885Sdumbbell struct drm_file *file_priv, 1106254885Sdumbbell struct drm_mode_fb_cmd2 *mode_cmd, 1107254885Sdumbbell struct drm_framebuffer **res) 1108254885Sdumbbell{ 1109254885Sdumbbell struct drm_gem_object *obj; 1110254885Sdumbbell struct radeon_framebuffer *radeon_fb; 1111254885Sdumbbell int ret; 1112254885Sdumbbell 1113254885Sdumbbell obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1114254885Sdumbbell if (obj == NULL) { 1115254885Sdumbbell dev_err(dev->device, "No GEM object associated to handle 0x%08X, " 1116254885Sdumbbell "can't create framebuffer\n", mode_cmd->handles[0]); 1117254885Sdumbbell return -ENOENT; 1118254885Sdumbbell } 1119254885Sdumbbell 1120254885Sdumbbell radeon_fb = malloc(sizeof(*radeon_fb), DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1121254885Sdumbbell if (radeon_fb == NULL) { 1122254885Sdumbbell drm_gem_object_unreference_unlocked(obj); 1123254885Sdumbbell return (-ENOMEM); 1124254885Sdumbbell } 1125254885Sdumbbell 1126254885Sdumbbell ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1127254885Sdumbbell if (ret) { 1128254885Sdumbbell free(radeon_fb, DRM_MEM_DRIVER); 1129254885Sdumbbell drm_gem_object_unreference_unlocked(obj); 1130254885Sdumbbell return ret; 1131254885Sdumbbell } 1132254885Sdumbbell 1133254885Sdumbbell *res = &radeon_fb->base; 1134254885Sdumbbell return 0; 1135254885Sdumbbell} 1136254885Sdumbbell 1137254885Sdumbbellstatic void radeon_output_poll_changed(struct drm_device *dev) 1138254885Sdumbbell{ 1139254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 1140254885Sdumbbell radeon_fb_output_poll_changed(rdev); 1141254885Sdumbbell} 1142254885Sdumbbell 1143254885Sdumbbellstatic const struct drm_mode_config_funcs radeon_mode_funcs = { 1144254885Sdumbbell .fb_create = radeon_user_framebuffer_create, 1145254885Sdumbbell .output_poll_changed = radeon_output_poll_changed 1146254885Sdumbbell}; 1147254885Sdumbbell 1148254885Sdumbbellstatic struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1149254885Sdumbbell{ { 0, "driver" }, 1150254885Sdumbbell { 1, "bios" }, 1151254885Sdumbbell}; 1152254885Sdumbbell 1153254885Sdumbbellstatic struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1154254885Sdumbbell{ { TV_STD_NTSC, "ntsc" }, 1155254885Sdumbbell { TV_STD_PAL, "pal" }, 1156254885Sdumbbell { TV_STD_PAL_M, "pal-m" }, 1157254885Sdumbbell { TV_STD_PAL_60, "pal-60" }, 1158254885Sdumbbell { TV_STD_NTSC_J, "ntsc-j" }, 1159254885Sdumbbell { TV_STD_SCART_PAL, "scart-pal" }, 1160254885Sdumbbell { TV_STD_PAL_CN, "pal-cn" }, 1161254885Sdumbbell { TV_STD_SECAM, "secam" }, 1162254885Sdumbbell}; 1163254885Sdumbbell 1164254885Sdumbbellstatic struct drm_prop_enum_list radeon_underscan_enum_list[] = 1165254885Sdumbbell{ { UNDERSCAN_OFF, "off" }, 1166254885Sdumbbell { UNDERSCAN_ON, "on" }, 1167254885Sdumbbell { UNDERSCAN_AUTO, "auto" }, 1168254885Sdumbbell}; 1169254885Sdumbbell 1170254885Sdumbbellstatic int radeon_modeset_create_props(struct radeon_device *rdev) 1171254885Sdumbbell{ 1172254885Sdumbbell int sz; 1173254885Sdumbbell 1174254885Sdumbbell if (rdev->is_atom_bios) { 1175254885Sdumbbell rdev->mode_info.coherent_mode_property = 1176254885Sdumbbell drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1177254885Sdumbbell if (!rdev->mode_info.coherent_mode_property) 1178254885Sdumbbell return -ENOMEM; 1179254885Sdumbbell } 1180254885Sdumbbell 1181254885Sdumbbell if (!ASIC_IS_AVIVO(rdev)) { 1182254885Sdumbbell sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list); 1183254885Sdumbbell rdev->mode_info.tmds_pll_property = 1184254885Sdumbbell drm_property_create_enum(rdev->ddev, 0, 1185254885Sdumbbell "tmds_pll", 1186254885Sdumbbell radeon_tmds_pll_enum_list, sz); 1187254885Sdumbbell } 1188254885Sdumbbell 1189254885Sdumbbell rdev->mode_info.load_detect_property = 1190254885Sdumbbell drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1191254885Sdumbbell if (!rdev->mode_info.load_detect_property) 1192254885Sdumbbell return -ENOMEM; 1193254885Sdumbbell 1194254885Sdumbbell drm_mode_create_scaling_mode_property(rdev->ddev); 1195254885Sdumbbell 1196254885Sdumbbell sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list); 1197254885Sdumbbell rdev->mode_info.tv_std_property = 1198254885Sdumbbell drm_property_create_enum(rdev->ddev, 0, 1199254885Sdumbbell "tv standard", 1200254885Sdumbbell radeon_tv_std_enum_list, sz); 1201254885Sdumbbell 1202254885Sdumbbell sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list); 1203254885Sdumbbell rdev->mode_info.underscan_property = 1204254885Sdumbbell drm_property_create_enum(rdev->ddev, 0, 1205254885Sdumbbell "underscan", 1206254885Sdumbbell radeon_underscan_enum_list, sz); 1207254885Sdumbbell 1208254885Sdumbbell rdev->mode_info.underscan_hborder_property = 1209254885Sdumbbell drm_property_create_range(rdev->ddev, 0, 1210254885Sdumbbell "underscan hborder", 0, 128); 1211254885Sdumbbell if (!rdev->mode_info.underscan_hborder_property) 1212254885Sdumbbell return -ENOMEM; 1213254885Sdumbbell 1214254885Sdumbbell rdev->mode_info.underscan_vborder_property = 1215254885Sdumbbell drm_property_create_range(rdev->ddev, 0, 1216254885Sdumbbell "underscan vborder", 0, 128); 1217254885Sdumbbell if (!rdev->mode_info.underscan_vborder_property) 1218254885Sdumbbell return -ENOMEM; 1219254885Sdumbbell 1220254885Sdumbbell return 0; 1221254885Sdumbbell} 1222254885Sdumbbell 1223254885Sdumbbellvoid radeon_update_display_priority(struct radeon_device *rdev) 1224254885Sdumbbell{ 1225254885Sdumbbell /* adjustment options for the display watermarks */ 1226254885Sdumbbell if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1227254885Sdumbbell /* set display priority to high for r3xx, rv515 chips 1228254885Sdumbbell * this avoids flickering due to underflow to the 1229254885Sdumbbell * display controllers during heavy acceleration. 1230254885Sdumbbell * Don't force high on rs4xx igp chips as it seems to 1231254885Sdumbbell * affect the sound card. See kernel bug 15982. 1232254885Sdumbbell */ 1233254885Sdumbbell if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1234254885Sdumbbell !(rdev->flags & RADEON_IS_IGP)) 1235254885Sdumbbell rdev->disp_priority = 2; 1236254885Sdumbbell else 1237254885Sdumbbell rdev->disp_priority = 0; 1238254885Sdumbbell } else 1239254885Sdumbbell rdev->disp_priority = radeon_disp_priority; 1240254885Sdumbbell 1241254885Sdumbbell} 1242254885Sdumbbell 1243254885Sdumbbell/* 1244254885Sdumbbell * Allocate hdmi structs and determine register offsets 1245254885Sdumbbell */ 1246254885Sdumbbellstatic void radeon_afmt_init(struct radeon_device *rdev) 1247254885Sdumbbell{ 1248254885Sdumbbell int i; 1249254885Sdumbbell 1250254885Sdumbbell for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1251254885Sdumbbell rdev->mode_info.afmt[i] = NULL; 1252254885Sdumbbell 1253254885Sdumbbell if (ASIC_IS_DCE6(rdev)) { 1254254885Sdumbbell /* todo */ 1255254885Sdumbbell } else if (ASIC_IS_DCE4(rdev)) { 1256254885Sdumbbell /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1257254885Sdumbbell /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1258254885Sdumbbell rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt), 1259254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1260254885Sdumbbell if (rdev->mode_info.afmt[0]) { 1261254885Sdumbbell rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1262254885Sdumbbell rdev->mode_info.afmt[0]->id = 0; 1263254885Sdumbbell } 1264254885Sdumbbell rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt), 1265254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1266254885Sdumbbell if (rdev->mode_info.afmt[1]) { 1267254885Sdumbbell rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1268254885Sdumbbell rdev->mode_info.afmt[1]->id = 1; 1269254885Sdumbbell } 1270254885Sdumbbell if (!ASIC_IS_DCE41(rdev)) { 1271254885Sdumbbell rdev->mode_info.afmt[2] = malloc(sizeof(struct radeon_afmt), 1272254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1273254885Sdumbbell if (rdev->mode_info.afmt[2]) { 1274254885Sdumbbell rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1275254885Sdumbbell rdev->mode_info.afmt[2]->id = 2; 1276254885Sdumbbell } 1277254885Sdumbbell rdev->mode_info.afmt[3] = malloc(sizeof(struct radeon_afmt), 1278254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1279254885Sdumbbell if (rdev->mode_info.afmt[3]) { 1280254885Sdumbbell rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1281254885Sdumbbell rdev->mode_info.afmt[3]->id = 3; 1282254885Sdumbbell } 1283254885Sdumbbell rdev->mode_info.afmt[4] = malloc(sizeof(struct radeon_afmt), 1284254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1285254885Sdumbbell if (rdev->mode_info.afmt[4]) { 1286254885Sdumbbell rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1287254885Sdumbbell rdev->mode_info.afmt[4]->id = 4; 1288254885Sdumbbell } 1289254885Sdumbbell rdev->mode_info.afmt[5] = malloc(sizeof(struct radeon_afmt), 1290254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1291254885Sdumbbell if (rdev->mode_info.afmt[5]) { 1292254885Sdumbbell rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1293254885Sdumbbell rdev->mode_info.afmt[5]->id = 5; 1294254885Sdumbbell } 1295254885Sdumbbell } 1296254885Sdumbbell } else if (ASIC_IS_DCE3(rdev)) { 1297254885Sdumbbell /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1298254885Sdumbbell rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt), 1299254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1300254885Sdumbbell if (rdev->mode_info.afmt[0]) { 1301254885Sdumbbell rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1302254885Sdumbbell rdev->mode_info.afmt[0]->id = 0; 1303254885Sdumbbell } 1304254885Sdumbbell rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt), 1305254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1306254885Sdumbbell if (rdev->mode_info.afmt[1]) { 1307254885Sdumbbell rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1308254885Sdumbbell rdev->mode_info.afmt[1]->id = 1; 1309254885Sdumbbell } 1310254885Sdumbbell } else if (ASIC_IS_DCE2(rdev)) { 1311254885Sdumbbell /* DCE2 has at least 1 routable audio block */ 1312254885Sdumbbell rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt), 1313254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1314254885Sdumbbell if (rdev->mode_info.afmt[0]) { 1315254885Sdumbbell rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1316254885Sdumbbell rdev->mode_info.afmt[0]->id = 0; 1317254885Sdumbbell } 1318254885Sdumbbell /* r6xx has 2 routable audio blocks */ 1319254885Sdumbbell if (rdev->family >= CHIP_R600) { 1320254885Sdumbbell rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt), 1321254885Sdumbbell DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1322254885Sdumbbell if (rdev->mode_info.afmt[1]) { 1323254885Sdumbbell rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1324254885Sdumbbell rdev->mode_info.afmt[1]->id = 1; 1325254885Sdumbbell } 1326254885Sdumbbell } 1327254885Sdumbbell } 1328254885Sdumbbell} 1329254885Sdumbbell 1330254885Sdumbbellstatic void radeon_afmt_fini(struct radeon_device *rdev) 1331254885Sdumbbell{ 1332254885Sdumbbell int i; 1333254885Sdumbbell 1334254885Sdumbbell for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1335254885Sdumbbell free(rdev->mode_info.afmt[i], DRM_MEM_DRIVER); 1336254885Sdumbbell rdev->mode_info.afmt[i] = NULL; 1337254885Sdumbbell } 1338254885Sdumbbell} 1339254885Sdumbbell 1340254885Sdumbbellint radeon_modeset_init(struct radeon_device *rdev) 1341254885Sdumbbell{ 1342254885Sdumbbell int i; 1343254885Sdumbbell int ret; 1344254885Sdumbbell 1345254885Sdumbbell drm_mode_config_init(rdev->ddev); 1346254885Sdumbbell rdev->mode_info.mode_config_initialized = true; 1347254885Sdumbbell 1348254885Sdumbbell rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1349254885Sdumbbell 1350254885Sdumbbell if (ASIC_IS_DCE5(rdev)) { 1351254885Sdumbbell rdev->ddev->mode_config.max_width = 16384; 1352254885Sdumbbell rdev->ddev->mode_config.max_height = 16384; 1353254885Sdumbbell } else if (ASIC_IS_AVIVO(rdev)) { 1354254885Sdumbbell rdev->ddev->mode_config.max_width = 8192; 1355254885Sdumbbell rdev->ddev->mode_config.max_height = 8192; 1356254885Sdumbbell } else { 1357254885Sdumbbell rdev->ddev->mode_config.max_width = 4096; 1358254885Sdumbbell rdev->ddev->mode_config.max_height = 4096; 1359254885Sdumbbell } 1360254885Sdumbbell 1361254885Sdumbbell rdev->ddev->mode_config.preferred_depth = 24; 1362254885Sdumbbell rdev->ddev->mode_config.prefer_shadow = 1; 1363254885Sdumbbell 1364254885Sdumbbell rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1365254885Sdumbbell 1366254885Sdumbbell ret = radeon_modeset_create_props(rdev); 1367254885Sdumbbell if (ret) { 1368254885Sdumbbell return ret; 1369254885Sdumbbell } 1370254885Sdumbbell 1371254885Sdumbbell /* init i2c buses */ 1372254885Sdumbbell radeon_i2c_init(rdev); 1373254885Sdumbbell 1374254885Sdumbbell /* check combios for a valid hardcoded EDID - Sun servers */ 1375254885Sdumbbell if (!rdev->is_atom_bios) { 1376254885Sdumbbell /* check for hardcoded EDID in BIOS */ 1377254885Sdumbbell radeon_combios_check_hardcoded_edid(rdev); 1378254885Sdumbbell } 1379254885Sdumbbell 1380254885Sdumbbell /* allocate crtcs */ 1381254885Sdumbbell for (i = 0; i < rdev->num_crtc; i++) { 1382254885Sdumbbell radeon_crtc_init(rdev->ddev, i); 1383254885Sdumbbell } 1384254885Sdumbbell 1385254885Sdumbbell /* okay we should have all the bios connectors */ 1386254885Sdumbbell ret = radeon_setup_enc_conn(rdev->ddev); 1387254885Sdumbbell if (!ret) { 1388254885Sdumbbell return ret; 1389254885Sdumbbell } 1390254885Sdumbbell 1391254885Sdumbbell /* init dig PHYs, disp eng pll */ 1392254885Sdumbbell if (rdev->is_atom_bios) { 1393254885Sdumbbell radeon_atom_encoder_init(rdev); 1394254885Sdumbbell radeon_atom_disp_eng_pll_init(rdev); 1395254885Sdumbbell } 1396254885Sdumbbell 1397254885Sdumbbell /* initialize hpd */ 1398254885Sdumbbell radeon_hpd_init(rdev); 1399254885Sdumbbell 1400254885Sdumbbell /* setup afmt */ 1401254885Sdumbbell radeon_afmt_init(rdev); 1402254885Sdumbbell 1403254885Sdumbbell /* Initialize power management */ 1404254885Sdumbbell radeon_pm_init(rdev); 1405254885Sdumbbell 1406254885Sdumbbell radeon_fbdev_init(rdev); 1407254885Sdumbbell drm_kms_helper_poll_init(rdev->ddev); 1408254885Sdumbbell 1409254885Sdumbbell return 0; 1410254885Sdumbbell} 1411254885Sdumbbell 1412254885Sdumbbellvoid radeon_modeset_fini(struct radeon_device *rdev) 1413254885Sdumbbell{ 1414254885Sdumbbell radeon_fbdev_fini(rdev); 1415254885Sdumbbell free(rdev->mode_info.bios_hardcoded_edid, DRM_MEM_KMS); 1416254885Sdumbbell radeon_pm_fini(rdev); 1417254885Sdumbbell 1418254885Sdumbbell if (rdev->mode_info.mode_config_initialized) { 1419254885Sdumbbell radeon_afmt_fini(rdev); 1420254885Sdumbbell drm_kms_helper_poll_fini(rdev->ddev); 1421254885Sdumbbell radeon_hpd_fini(rdev); 1422254885Sdumbbell DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1423254885Sdumbbell drm_mode_config_cleanup(rdev->ddev); 1424254885Sdumbbell DRM_LOCK(rdev->ddev); 1425254885Sdumbbell rdev->mode_info.mode_config_initialized = false; 1426254885Sdumbbell } 1427254885Sdumbbell /* free i2c buses */ 1428254885Sdumbbell radeon_i2c_fini(rdev); 1429254885Sdumbbell} 1430254885Sdumbbell 1431254885Sdumbbellstatic bool is_hdtv_mode(const struct drm_display_mode *mode) 1432254885Sdumbbell{ 1433254885Sdumbbell /* try and guess if this is a tv or a monitor */ 1434254885Sdumbbell if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1435254885Sdumbbell (mode->vdisplay == 576) || /* 576p */ 1436254885Sdumbbell (mode->vdisplay == 720) || /* 720p */ 1437254885Sdumbbell (mode->vdisplay == 1080)) /* 1080p */ 1438254885Sdumbbell return true; 1439254885Sdumbbell else 1440254885Sdumbbell return false; 1441254885Sdumbbell} 1442254885Sdumbbell 1443254885Sdumbbellbool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1444254885Sdumbbell const struct drm_display_mode *mode, 1445254885Sdumbbell struct drm_display_mode *adjusted_mode) 1446254885Sdumbbell{ 1447254885Sdumbbell struct drm_device *dev = crtc->dev; 1448254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 1449254885Sdumbbell struct drm_encoder *encoder; 1450254885Sdumbbell struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1451254885Sdumbbell struct radeon_encoder *radeon_encoder; 1452254885Sdumbbell struct drm_connector *connector; 1453254885Sdumbbell struct radeon_connector *radeon_connector; 1454254885Sdumbbell bool first = true; 1455254885Sdumbbell u32 src_v = 1, dst_v = 1; 1456254885Sdumbbell u32 src_h = 1, dst_h = 1; 1457254885Sdumbbell 1458254885Sdumbbell radeon_crtc->h_border = 0; 1459254885Sdumbbell radeon_crtc->v_border = 0; 1460254885Sdumbbell 1461254885Sdumbbell list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1462254885Sdumbbell if (encoder->crtc != crtc) 1463254885Sdumbbell continue; 1464254885Sdumbbell radeon_encoder = to_radeon_encoder(encoder); 1465254885Sdumbbell connector = radeon_get_connector_for_encoder(encoder); 1466254885Sdumbbell radeon_connector = to_radeon_connector(connector); 1467254885Sdumbbell 1468254885Sdumbbell if (first) { 1469254885Sdumbbell /* set scaling */ 1470254885Sdumbbell if (radeon_encoder->rmx_type == RMX_OFF) 1471254885Sdumbbell radeon_crtc->rmx_type = RMX_OFF; 1472254885Sdumbbell else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1473254885Sdumbbell mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1474254885Sdumbbell radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1475254885Sdumbbell else 1476254885Sdumbbell radeon_crtc->rmx_type = RMX_OFF; 1477254885Sdumbbell /* copy native mode */ 1478254885Sdumbbell memcpy(&radeon_crtc->native_mode, 1479254885Sdumbbell &radeon_encoder->native_mode, 1480254885Sdumbbell sizeof(struct drm_display_mode)); 1481254885Sdumbbell src_v = crtc->mode.vdisplay; 1482254885Sdumbbell dst_v = radeon_crtc->native_mode.vdisplay; 1483254885Sdumbbell src_h = crtc->mode.hdisplay; 1484254885Sdumbbell dst_h = radeon_crtc->native_mode.hdisplay; 1485254885Sdumbbell 1486254885Sdumbbell /* fix up for overscan on hdmi */ 1487254885Sdumbbell if (ASIC_IS_AVIVO(rdev) && 1488254885Sdumbbell (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1489254885Sdumbbell ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1490254885Sdumbbell ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1491254885Sdumbbell drm_detect_hdmi_monitor(radeon_connector->edid) && 1492254885Sdumbbell is_hdtv_mode(mode)))) { 1493254885Sdumbbell if (radeon_encoder->underscan_hborder != 0) 1494254885Sdumbbell radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1495254885Sdumbbell else 1496254885Sdumbbell radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1497254885Sdumbbell if (radeon_encoder->underscan_vborder != 0) 1498254885Sdumbbell radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1499254885Sdumbbell else 1500254885Sdumbbell radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1501254885Sdumbbell radeon_crtc->rmx_type = RMX_FULL; 1502254885Sdumbbell src_v = crtc->mode.vdisplay; 1503254885Sdumbbell dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1504254885Sdumbbell src_h = crtc->mode.hdisplay; 1505254885Sdumbbell dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1506254885Sdumbbell } 1507254885Sdumbbell first = false; 1508254885Sdumbbell } else { 1509254885Sdumbbell if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1510254885Sdumbbell /* WARNING: Right now this can't happen but 1511254885Sdumbbell * in the future we need to check that scaling 1512254885Sdumbbell * are consistent across different encoder 1513254885Sdumbbell * (ie all encoder can work with the same 1514254885Sdumbbell * scaling). 1515254885Sdumbbell */ 1516254885Sdumbbell DRM_ERROR("Scaling not consistent across encoder.\n"); 1517254885Sdumbbell return false; 1518254885Sdumbbell } 1519254885Sdumbbell } 1520254885Sdumbbell } 1521254885Sdumbbell if (radeon_crtc->rmx_type != RMX_OFF) { 1522254885Sdumbbell fixed20_12 a, b; 1523254885Sdumbbell a.full = dfixed_const(src_v); 1524254885Sdumbbell b.full = dfixed_const(dst_v); 1525254885Sdumbbell radeon_crtc->vsc.full = dfixed_div(a, b); 1526254885Sdumbbell a.full = dfixed_const(src_h); 1527254885Sdumbbell b.full = dfixed_const(dst_h); 1528254885Sdumbbell radeon_crtc->hsc.full = dfixed_div(a, b); 1529254885Sdumbbell } else { 1530254885Sdumbbell radeon_crtc->vsc.full = dfixed_const(1); 1531254885Sdumbbell radeon_crtc->hsc.full = dfixed_const(1); 1532254885Sdumbbell } 1533254885Sdumbbell return true; 1534254885Sdumbbell} 1535254885Sdumbbell 1536254885Sdumbbell/* 1537254885Sdumbbell * Retrieve current video scanout position of crtc on a given gpu. 1538254885Sdumbbell * 1539254885Sdumbbell * \param dev Device to query. 1540254885Sdumbbell * \param crtc Crtc to query. 1541254885Sdumbbell * \param *vpos Location where vertical scanout position should be stored. 1542254885Sdumbbell * \param *hpos Location where horizontal scanout position should go. 1543254885Sdumbbell * 1544254885Sdumbbell * Returns vpos as a positive number while in active scanout area. 1545254885Sdumbbell * Returns vpos as a negative number inside vblank, counting the number 1546254885Sdumbbell * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1547254885Sdumbbell * until start of active scanout / end of vblank." 1548254885Sdumbbell * 1549254885Sdumbbell * \return Flags, or'ed together as follows: 1550254885Sdumbbell * 1551254885Sdumbbell * DRM_SCANOUTPOS_VALID = Query successful. 1552254885Sdumbbell * DRM_SCANOUTPOS_INVBL = Inside vblank. 1553254885Sdumbbell * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1554254885Sdumbbell * this flag means that returned position may be offset by a constant but 1555254885Sdumbbell * unknown small number of scanlines wrt. real scanout position. 1556254885Sdumbbell * 1557254885Sdumbbell */ 1558254885Sdumbbellint radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) 1559254885Sdumbbell{ 1560254885Sdumbbell u32 stat_crtc = 0, vbl = 0, position = 0; 1561254885Sdumbbell int vbl_start, vbl_end, vtotal, ret = 0; 1562254885Sdumbbell bool in_vbl = true; 1563254885Sdumbbell 1564254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 1565254885Sdumbbell 1566254885Sdumbbell if (ASIC_IS_DCE4(rdev)) { 1567254885Sdumbbell if (crtc == 0) { 1568254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1569254885Sdumbbell EVERGREEN_CRTC0_REGISTER_OFFSET); 1570254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1571254885Sdumbbell EVERGREEN_CRTC0_REGISTER_OFFSET); 1572254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1573254885Sdumbbell } 1574254885Sdumbbell if (crtc == 1) { 1575254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1576254885Sdumbbell EVERGREEN_CRTC1_REGISTER_OFFSET); 1577254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1578254885Sdumbbell EVERGREEN_CRTC1_REGISTER_OFFSET); 1579254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1580254885Sdumbbell } 1581254885Sdumbbell if (crtc == 2) { 1582254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1583254885Sdumbbell EVERGREEN_CRTC2_REGISTER_OFFSET); 1584254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1585254885Sdumbbell EVERGREEN_CRTC2_REGISTER_OFFSET); 1586254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1587254885Sdumbbell } 1588254885Sdumbbell if (crtc == 3) { 1589254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1590254885Sdumbbell EVERGREEN_CRTC3_REGISTER_OFFSET); 1591254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1592254885Sdumbbell EVERGREEN_CRTC3_REGISTER_OFFSET); 1593254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1594254885Sdumbbell } 1595254885Sdumbbell if (crtc == 4) { 1596254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1597254885Sdumbbell EVERGREEN_CRTC4_REGISTER_OFFSET); 1598254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1599254885Sdumbbell EVERGREEN_CRTC4_REGISTER_OFFSET); 1600254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1601254885Sdumbbell } 1602254885Sdumbbell if (crtc == 5) { 1603254885Sdumbbell vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1604254885Sdumbbell EVERGREEN_CRTC5_REGISTER_OFFSET); 1605254885Sdumbbell position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1606254885Sdumbbell EVERGREEN_CRTC5_REGISTER_OFFSET); 1607254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1608254885Sdumbbell } 1609254885Sdumbbell } else if (ASIC_IS_AVIVO(rdev)) { 1610254885Sdumbbell if (crtc == 0) { 1611254885Sdumbbell vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1612254885Sdumbbell position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1613254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1614254885Sdumbbell } 1615254885Sdumbbell if (crtc == 1) { 1616254885Sdumbbell vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1617254885Sdumbbell position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1618254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1619254885Sdumbbell } 1620254885Sdumbbell } else { 1621254885Sdumbbell /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1622254885Sdumbbell if (crtc == 0) { 1623254885Sdumbbell /* Assume vbl_end == 0, get vbl_start from 1624254885Sdumbbell * upper 16 bits. 1625254885Sdumbbell */ 1626254885Sdumbbell vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1627254885Sdumbbell RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1628254885Sdumbbell /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1629254885Sdumbbell position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1630254885Sdumbbell stat_crtc = RREG32(RADEON_CRTC_STATUS); 1631254885Sdumbbell if (!(stat_crtc & 1)) 1632254885Sdumbbell in_vbl = false; 1633254885Sdumbbell 1634254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1635254885Sdumbbell } 1636254885Sdumbbell if (crtc == 1) { 1637254885Sdumbbell vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1638254885Sdumbbell RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1639254885Sdumbbell position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1640254885Sdumbbell stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1641254885Sdumbbell if (!(stat_crtc & 1)) 1642254885Sdumbbell in_vbl = false; 1643254885Sdumbbell 1644254885Sdumbbell ret |= DRM_SCANOUTPOS_VALID; 1645254885Sdumbbell } 1646254885Sdumbbell } 1647254885Sdumbbell 1648254885Sdumbbell /* Decode into vertical and horizontal scanout position. */ 1649254885Sdumbbell *vpos = position & 0x1fff; 1650254885Sdumbbell *hpos = (position >> 16) & 0x1fff; 1651254885Sdumbbell 1652254885Sdumbbell /* Valid vblank area boundaries from gpu retrieved? */ 1653254885Sdumbbell if (vbl > 0) { 1654254885Sdumbbell /* Yes: Decode. */ 1655254885Sdumbbell ret |= DRM_SCANOUTPOS_ACCURATE; 1656254885Sdumbbell vbl_start = vbl & 0x1fff; 1657254885Sdumbbell vbl_end = (vbl >> 16) & 0x1fff; 1658254885Sdumbbell } 1659254885Sdumbbell else { 1660254885Sdumbbell /* No: Fake something reasonable which gives at least ok results. */ 1661254885Sdumbbell vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1662254885Sdumbbell vbl_end = 0; 1663254885Sdumbbell } 1664254885Sdumbbell 1665254885Sdumbbell /* Test scanout position against vblank region. */ 1666254885Sdumbbell if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1667254885Sdumbbell in_vbl = false; 1668254885Sdumbbell 1669254885Sdumbbell /* Check if inside vblank area and apply corrective offsets: 1670254885Sdumbbell * vpos will then be >=0 in video scanout area, but negative 1671254885Sdumbbell * within vblank area, counting down the number of lines until 1672254885Sdumbbell * start of scanout. 1673254885Sdumbbell */ 1674254885Sdumbbell 1675254885Sdumbbell /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1676254885Sdumbbell if (in_vbl && (*vpos >= vbl_start)) { 1677254885Sdumbbell vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1678254885Sdumbbell *vpos = *vpos - vtotal; 1679254885Sdumbbell } 1680254885Sdumbbell 1681254885Sdumbbell /* Correct for shifted end of vbl at vbl_end. */ 1682254885Sdumbbell *vpos = *vpos - vbl_end; 1683254885Sdumbbell 1684254885Sdumbbell /* In vblank? */ 1685254885Sdumbbell if (in_vbl) 1686254885Sdumbbell ret |= DRM_SCANOUTPOS_INVBL; 1687254885Sdumbbell 1688254885Sdumbbell return ret; 1689254885Sdumbbell} 1690