1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#include <dev/drm2/drmP.h> 33254885Sdumbbell#include "radeon.h" 34254885Sdumbbell#include "radeon_asic.h" 35254885Sdumbbell#include "r600d.h" 36254885Sdumbbell#include "r600_reg_safe.h" 37254885Sdumbbell#include "r600_cp.h" 38254885Sdumbbell#include "r600_cs.h" 39254885Sdumbbell 40254885Sdumbbellstatic int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 41254885Sdumbbell struct radeon_cs_reloc **cs_reloc); 42254885Sdumbbellstatic int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 43254885Sdumbbell struct radeon_cs_reloc **cs_reloc); 44254885Sdumbbelltypedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 45254885Sdumbbellstatic next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 46254885Sdumbbell 47254885Sdumbbell 48254885Sdumbbellstruct r600_cs_track { 49254885Sdumbbell /* configuration we miror so that we use same code btw kms/ums */ 50254885Sdumbbell u32 group_size; 51254885Sdumbbell u32 nbanks; 52254885Sdumbbell u32 npipes; 53254885Sdumbbell /* value we track */ 54254885Sdumbbell u32 sq_config; 55254885Sdumbbell u32 log_nsamples; 56254885Sdumbbell u32 nsamples; 57254885Sdumbbell u32 cb_color_base_last[8]; 58254885Sdumbbell struct radeon_bo *cb_color_bo[8]; 59254885Sdumbbell u64 cb_color_bo_mc[8]; 60254885Sdumbbell u64 cb_color_bo_offset[8]; 61254885Sdumbbell struct radeon_bo *cb_color_frag_bo[8]; 62254885Sdumbbell u64 cb_color_frag_offset[8]; 63254885Sdumbbell struct radeon_bo *cb_color_tile_bo[8]; 64254885Sdumbbell u64 cb_color_tile_offset[8]; 65254885Sdumbbell u32 cb_color_mask[8]; 66254885Sdumbbell u32 cb_color_info[8]; 67254885Sdumbbell u32 cb_color_view[8]; 68254885Sdumbbell u32 cb_color_size_idx[8]; /* unused */ 69254885Sdumbbell u32 cb_target_mask; 70254885Sdumbbell u32 cb_shader_mask; /* unused */ 71254885Sdumbbell bool is_resolve; 72254885Sdumbbell u32 cb_color_size[8]; 73254885Sdumbbell u32 vgt_strmout_en; 74254885Sdumbbell u32 vgt_strmout_buffer_en; 75254885Sdumbbell struct radeon_bo *vgt_strmout_bo[4]; 76254885Sdumbbell u64 vgt_strmout_bo_mc[4]; /* unused */ 77254885Sdumbbell u32 vgt_strmout_bo_offset[4]; 78254885Sdumbbell u32 vgt_strmout_size[4]; 79254885Sdumbbell u32 db_depth_control; 80254885Sdumbbell u32 db_depth_info; 81254885Sdumbbell u32 db_depth_size_idx; 82254885Sdumbbell u32 db_depth_view; 83254885Sdumbbell u32 db_depth_size; 84254885Sdumbbell u32 db_offset; 85254885Sdumbbell struct radeon_bo *db_bo; 86254885Sdumbbell u64 db_bo_mc; 87254885Sdumbbell bool sx_misc_kill_all_prims; 88254885Sdumbbell bool cb_dirty; 89254885Sdumbbell bool db_dirty; 90254885Sdumbbell bool streamout_dirty; 91254885Sdumbbell struct radeon_bo *htile_bo; 92254885Sdumbbell u64 htile_offset; 93254885Sdumbbell u32 htile_surface; 94254885Sdumbbell}; 95254885Sdumbbell 96254885Sdumbbell#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } 97254885Sdumbbell#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } 98254885Sdumbbell#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 } 99254885Sdumbbell#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } 100254885Sdumbbell#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 } 101254885Sdumbbell#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } 102254885Sdumbbell#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } 103254885Sdumbbell#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } 104254885Sdumbbell 105254885Sdumbbellstruct gpu_formats { 106254885Sdumbbell unsigned blockwidth; 107254885Sdumbbell unsigned blockheight; 108254885Sdumbbell unsigned blocksize; 109254885Sdumbbell unsigned valid_color; 110254885Sdumbbell enum radeon_family min_family; 111254885Sdumbbell}; 112254885Sdumbbell 113254885Sdumbbellstatic const struct gpu_formats color_formats_table[] = { 114254885Sdumbbell /* 8 bit */ 115254885Sdumbbell FMT_8_BIT(V_038004_COLOR_8, 1), 116254885Sdumbbell FMT_8_BIT(V_038004_COLOR_4_4, 1), 117254885Sdumbbell FMT_8_BIT(V_038004_COLOR_3_3_2, 1), 118254885Sdumbbell FMT_8_BIT(V_038004_FMT_1, 0), 119254885Sdumbbell 120254885Sdumbbell /* 16-bit */ 121254885Sdumbbell FMT_16_BIT(V_038004_COLOR_16, 1), 122254885Sdumbbell FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), 123254885Sdumbbell FMT_16_BIT(V_038004_COLOR_8_8, 1), 124254885Sdumbbell FMT_16_BIT(V_038004_COLOR_5_6_5, 1), 125254885Sdumbbell FMT_16_BIT(V_038004_COLOR_6_5_5, 1), 126254885Sdumbbell FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), 127254885Sdumbbell FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), 128254885Sdumbbell FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), 129254885Sdumbbell 130254885Sdumbbell /* 24-bit */ 131254885Sdumbbell FMT_24_BIT(V_038004_FMT_8_8_8), 132254885Sdumbbell 133254885Sdumbbell /* 32-bit */ 134254885Sdumbbell FMT_32_BIT(V_038004_COLOR_32, 1), 135254885Sdumbbell FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), 136254885Sdumbbell FMT_32_BIT(V_038004_COLOR_16_16, 1), 137254885Sdumbbell FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), 138254885Sdumbbell FMT_32_BIT(V_038004_COLOR_8_24, 1), 139254885Sdumbbell FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), 140254885Sdumbbell FMT_32_BIT(V_038004_COLOR_24_8, 1), 141254885Sdumbbell FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), 142254885Sdumbbell FMT_32_BIT(V_038004_COLOR_10_11_11, 1), 143254885Sdumbbell FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), 144254885Sdumbbell FMT_32_BIT(V_038004_COLOR_11_11_10, 1), 145254885Sdumbbell FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), 146254885Sdumbbell FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), 147254885Sdumbbell FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), 148254885Sdumbbell FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), 149254885Sdumbbell FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), 150254885Sdumbbell FMT_32_BIT(V_038004_FMT_32_AS_8, 0), 151254885Sdumbbell FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), 152254885Sdumbbell 153254885Sdumbbell /* 48-bit */ 154254885Sdumbbell FMT_48_BIT(V_038004_FMT_16_16_16), 155254885Sdumbbell FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), 156254885Sdumbbell 157254885Sdumbbell /* 64-bit */ 158254885Sdumbbell FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), 159254885Sdumbbell FMT_64_BIT(V_038004_COLOR_32_32, 1), 160254885Sdumbbell FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), 161254885Sdumbbell FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), 162254885Sdumbbell FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), 163254885Sdumbbell 164254885Sdumbbell FMT_96_BIT(V_038004_FMT_32_32_32), 165254885Sdumbbell FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), 166254885Sdumbbell 167254885Sdumbbell /* 128-bit */ 168254885Sdumbbell FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), 169254885Sdumbbell FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), 170254885Sdumbbell 171254885Sdumbbell [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, 172254885Sdumbbell [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, 173254885Sdumbbell 174254885Sdumbbell /* block compressed formats */ 175254885Sdumbbell [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, 176254885Sdumbbell [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, 177254885Sdumbbell [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, 178254885Sdumbbell [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, 179254885Sdumbbell [V_038004_FMT_BC5] = { 4, 4, 16, 0}, 180254885Sdumbbell [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 181254885Sdumbbell [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 182254885Sdumbbell 183254885Sdumbbell /* The other Evergreen formats */ 184254885Sdumbbell [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, 185254885Sdumbbell}; 186254885Sdumbbell 187254885Sdumbbellbool r600_fmt_is_valid_color(u32 format) 188254885Sdumbbell{ 189254885Sdumbbell if (format >= DRM_ARRAY_SIZE(color_formats_table)) 190254885Sdumbbell return false; 191254885Sdumbbell 192254885Sdumbbell if (color_formats_table[format].valid_color) 193254885Sdumbbell return true; 194254885Sdumbbell 195254885Sdumbbell return false; 196254885Sdumbbell} 197254885Sdumbbell 198254885Sdumbbellbool r600_fmt_is_valid_texture(u32 format, enum radeon_family family) 199254885Sdumbbell{ 200254885Sdumbbell if (format >= DRM_ARRAY_SIZE(color_formats_table)) 201254885Sdumbbell return false; 202254885Sdumbbell 203254885Sdumbbell if (family < color_formats_table[format].min_family) 204254885Sdumbbell return false; 205254885Sdumbbell 206254885Sdumbbell if (color_formats_table[format].blockwidth > 0) 207254885Sdumbbell return true; 208254885Sdumbbell 209254885Sdumbbell return false; 210254885Sdumbbell} 211254885Sdumbbell 212254885Sdumbbellint r600_fmt_get_blocksize(u32 format) 213254885Sdumbbell{ 214254885Sdumbbell if (format >= DRM_ARRAY_SIZE(color_formats_table)) 215254885Sdumbbell return 0; 216254885Sdumbbell 217254885Sdumbbell return color_formats_table[format].blocksize; 218254885Sdumbbell} 219254885Sdumbbell 220254885Sdumbbellint r600_fmt_get_nblocksx(u32 format, u32 w) 221254885Sdumbbell{ 222254885Sdumbbell unsigned bw; 223254885Sdumbbell 224254885Sdumbbell if (format >= DRM_ARRAY_SIZE(color_formats_table)) 225254885Sdumbbell return 0; 226254885Sdumbbell 227254885Sdumbbell bw = color_formats_table[format].blockwidth; 228254885Sdumbbell if (bw == 0) 229254885Sdumbbell return 0; 230254885Sdumbbell 231254885Sdumbbell return (w + bw - 1) / bw; 232254885Sdumbbell} 233254885Sdumbbell 234254885Sdumbbellint r600_fmt_get_nblocksy(u32 format, u32 h) 235254885Sdumbbell{ 236254885Sdumbbell unsigned bh; 237254885Sdumbbell 238254885Sdumbbell if (format >= DRM_ARRAY_SIZE(color_formats_table)) 239254885Sdumbbell return 0; 240254885Sdumbbell 241254885Sdumbbell bh = color_formats_table[format].blockheight; 242254885Sdumbbell if (bh == 0) 243254885Sdumbbell return 0; 244254885Sdumbbell 245254885Sdumbbell return (h + bh - 1) / bh; 246254885Sdumbbell} 247254885Sdumbbell 248254885Sdumbbellstruct array_mode_checker { 249254885Sdumbbell int array_mode; 250254885Sdumbbell u32 group_size; 251254885Sdumbbell u32 nbanks; 252254885Sdumbbell u32 npipes; 253254885Sdumbbell u32 nsamples; 254254885Sdumbbell u32 blocksize; 255254885Sdumbbell}; 256254885Sdumbbell 257254885Sdumbbell/* returns alignment in pixels for pitch/height/depth and bytes for base */ 258254885Sdumbbellstatic int r600_get_array_mode_alignment(struct array_mode_checker *values, 259254885Sdumbbell u32 *pitch_align, 260254885Sdumbbell u32 *height_align, 261254885Sdumbbell u32 *depth_align, 262254885Sdumbbell u64 *base_align) 263254885Sdumbbell{ 264254885Sdumbbell u32 tile_width = 8; 265254885Sdumbbell u32 tile_height = 8; 266254885Sdumbbell u32 macro_tile_width = values->nbanks; 267254885Sdumbbell u32 macro_tile_height = values->npipes; 268254885Sdumbbell u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; 269254885Sdumbbell u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; 270254885Sdumbbell 271254885Sdumbbell switch (values->array_mode) { 272254885Sdumbbell case ARRAY_LINEAR_GENERAL: 273254885Sdumbbell /* technically tile_width/_height for pitch/height */ 274254885Sdumbbell *pitch_align = 1; /* tile_width */ 275254885Sdumbbell *height_align = 1; /* tile_height */ 276254885Sdumbbell *depth_align = 1; 277254885Sdumbbell *base_align = 1; 278254885Sdumbbell break; 279254885Sdumbbell case ARRAY_LINEAR_ALIGNED: 280254885Sdumbbell *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); 281254885Sdumbbell *height_align = 1; 282254885Sdumbbell *depth_align = 1; 283254885Sdumbbell *base_align = values->group_size; 284254885Sdumbbell break; 285254885Sdumbbell case ARRAY_1D_TILED_THIN1: 286254885Sdumbbell *pitch_align = max((u32)tile_width, 287254885Sdumbbell (u32)(values->group_size / 288254885Sdumbbell (tile_height * values->blocksize * values->nsamples))); 289254885Sdumbbell *height_align = tile_height; 290254885Sdumbbell *depth_align = 1; 291254885Sdumbbell *base_align = values->group_size; 292254885Sdumbbell break; 293254885Sdumbbell case ARRAY_2D_TILED_THIN1: 294254885Sdumbbell *pitch_align = max((u32)macro_tile_width * tile_width, 295254885Sdumbbell (u32)((values->group_size * values->nbanks) / 296254885Sdumbbell (values->blocksize * values->nsamples * tile_width))); 297254885Sdumbbell *height_align = macro_tile_height * tile_height; 298254885Sdumbbell *depth_align = 1; 299254885Sdumbbell *base_align = max(macro_tile_bytes, 300254885Sdumbbell (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); 301254885Sdumbbell break; 302254885Sdumbbell default: 303254885Sdumbbell return -EINVAL; 304254885Sdumbbell } 305254885Sdumbbell 306254885Sdumbbell return 0; 307254885Sdumbbell} 308254885Sdumbbell 309254885Sdumbbellstatic void r600_cs_track_init(struct r600_cs_track *track) 310254885Sdumbbell{ 311254885Sdumbbell int i; 312254885Sdumbbell 313254885Sdumbbell /* assume DX9 mode */ 314254885Sdumbbell track->sq_config = DX9_CONSTS; 315254885Sdumbbell for (i = 0; i < 8; i++) { 316254885Sdumbbell track->cb_color_base_last[i] = 0; 317254885Sdumbbell track->cb_color_size[i] = 0; 318254885Sdumbbell track->cb_color_size_idx[i] = 0; 319254885Sdumbbell track->cb_color_info[i] = 0; 320254885Sdumbbell track->cb_color_view[i] = 0xFFFFFFFF; 321254885Sdumbbell track->cb_color_bo[i] = NULL; 322254885Sdumbbell track->cb_color_bo_offset[i] = 0xFFFFFFFF; 323254885Sdumbbell track->cb_color_bo_mc[i] = 0xFFFFFFFF; 324254885Sdumbbell track->cb_color_frag_bo[i] = NULL; 325254885Sdumbbell track->cb_color_frag_offset[i] = 0xFFFFFFFF; 326254885Sdumbbell track->cb_color_tile_bo[i] = NULL; 327254885Sdumbbell track->cb_color_tile_offset[i] = 0xFFFFFFFF; 328254885Sdumbbell track->cb_color_mask[i] = 0xFFFFFFFF; 329254885Sdumbbell } 330254885Sdumbbell track->is_resolve = false; 331254885Sdumbbell track->nsamples = 16; 332254885Sdumbbell track->log_nsamples = 4; 333254885Sdumbbell track->cb_target_mask = 0xFFFFFFFF; 334254885Sdumbbell track->cb_shader_mask = 0xFFFFFFFF; 335254885Sdumbbell track->cb_dirty = true; 336254885Sdumbbell track->db_bo = NULL; 337254885Sdumbbell track->db_bo_mc = 0xFFFFFFFF; 338254885Sdumbbell /* assume the biggest format and that htile is enabled */ 339254885Sdumbbell track->db_depth_info = 7 | (1 << 25); 340254885Sdumbbell track->db_depth_view = 0xFFFFC000; 341254885Sdumbbell track->db_depth_size = 0xFFFFFFFF; 342254885Sdumbbell track->db_depth_size_idx = 0; 343254885Sdumbbell track->db_depth_control = 0xFFFFFFFF; 344254885Sdumbbell track->db_dirty = true; 345254885Sdumbbell track->htile_bo = NULL; 346254885Sdumbbell track->htile_offset = 0xFFFFFFFF; 347254885Sdumbbell track->htile_surface = 0; 348254885Sdumbbell 349254885Sdumbbell for (i = 0; i < 4; i++) { 350254885Sdumbbell track->vgt_strmout_size[i] = 0; 351254885Sdumbbell track->vgt_strmout_bo[i] = NULL; 352254885Sdumbbell track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 353254885Sdumbbell track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; 354254885Sdumbbell } 355254885Sdumbbell track->streamout_dirty = true; 356254885Sdumbbell track->sx_misc_kill_all_prims = false; 357254885Sdumbbell} 358254885Sdumbbell 359254885Sdumbbellstatic int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 360254885Sdumbbell{ 361254885Sdumbbell struct r600_cs_track *track = p->track; 362254885Sdumbbell u32 slice_tile_max, size, tmp; 363254885Sdumbbell u32 height, height_align, pitch, pitch_align, depth_align; 364254885Sdumbbell u64 base_offset, base_align; 365254885Sdumbbell struct array_mode_checker array_check; 366254885Sdumbbell volatile u32 *ib = p->ib.ptr; 367254885Sdumbbell unsigned array_mode; 368254885Sdumbbell u32 format; 369254885Sdumbbell /* When resolve is used, the second colorbuffer has always 1 sample. */ 370254885Sdumbbell unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; 371254885Sdumbbell 372254885Sdumbbell size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 373254885Sdumbbell format = G_0280A0_FORMAT(track->cb_color_info[i]); 374254885Sdumbbell if (!r600_fmt_is_valid_color(format)) { 375254885Sdumbbell dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 376254885Sdumbbell __func__, __LINE__, format, 377254885Sdumbbell i, track->cb_color_info[i]); 378254885Sdumbbell return -EINVAL; 379254885Sdumbbell } 380254885Sdumbbell /* pitch in pixels */ 381254885Sdumbbell pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; 382254885Sdumbbell slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; 383254885Sdumbbell slice_tile_max *= 64; 384254885Sdumbbell height = slice_tile_max / pitch; 385254885Sdumbbell if (height > 8192) 386254885Sdumbbell height = 8192; 387254885Sdumbbell array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); 388254885Sdumbbell 389254885Sdumbbell base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; 390254885Sdumbbell array_check.array_mode = array_mode; 391254885Sdumbbell array_check.group_size = track->group_size; 392254885Sdumbbell array_check.nbanks = track->nbanks; 393254885Sdumbbell array_check.npipes = track->npipes; 394254885Sdumbbell array_check.nsamples = nsamples; 395254885Sdumbbell array_check.blocksize = r600_fmt_get_blocksize(format); 396254885Sdumbbell if (r600_get_array_mode_alignment(&array_check, 397254885Sdumbbell &pitch_align, &height_align, &depth_align, &base_align)) { 398254885Sdumbbell dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 399254885Sdumbbell G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 400254885Sdumbbell track->cb_color_info[i]); 401254885Sdumbbell return -EINVAL; 402254885Sdumbbell } 403254885Sdumbbell switch (array_mode) { 404254885Sdumbbell case V_0280A0_ARRAY_LINEAR_GENERAL: 405254885Sdumbbell break; 406254885Sdumbbell case V_0280A0_ARRAY_LINEAR_ALIGNED: 407254885Sdumbbell break; 408254885Sdumbbell case V_0280A0_ARRAY_1D_TILED_THIN1: 409254885Sdumbbell /* avoid breaking userspace */ 410254885Sdumbbell if (height > 7) 411254885Sdumbbell height &= ~0x7; 412254885Sdumbbell break; 413254885Sdumbbell case V_0280A0_ARRAY_2D_TILED_THIN1: 414254885Sdumbbell break; 415254885Sdumbbell default: 416254885Sdumbbell dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 417254885Sdumbbell G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 418254885Sdumbbell track->cb_color_info[i]); 419254885Sdumbbell return -EINVAL; 420254885Sdumbbell } 421254885Sdumbbell 422254885Sdumbbell if (!IS_ALIGNED(pitch, pitch_align)) { 423254885Sdumbbell dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 424254885Sdumbbell __func__, __LINE__, pitch, pitch_align, array_mode); 425254885Sdumbbell return -EINVAL; 426254885Sdumbbell } 427254885Sdumbbell if (!IS_ALIGNED(height, height_align)) { 428254885Sdumbbell dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 429254885Sdumbbell __func__, __LINE__, height, height_align, array_mode); 430254885Sdumbbell return -EINVAL; 431254885Sdumbbell } 432254885Sdumbbell if (!IS_ALIGNED(base_offset, base_align)) { 433254885Sdumbbell dev_warn(p->dev, "%s offset[%d] 0x%jx 0x%jx, %d not aligned\n", __func__, i, 434254885Sdumbbell (uintmax_t)base_offset, (uintmax_t)base_align, array_mode); 435254885Sdumbbell return -EINVAL; 436254885Sdumbbell } 437254885Sdumbbell 438254885Sdumbbell /* check offset */ 439254885Sdumbbell tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * 440254885Sdumbbell r600_fmt_get_blocksize(format) * nsamples; 441254885Sdumbbell switch (array_mode) { 442254885Sdumbbell default: 443254885Sdumbbell case V_0280A0_ARRAY_LINEAR_GENERAL: 444254885Sdumbbell case V_0280A0_ARRAY_LINEAR_ALIGNED: 445254885Sdumbbell tmp += track->cb_color_view[i] & 0xFF; 446254885Sdumbbell break; 447254885Sdumbbell case V_0280A0_ARRAY_1D_TILED_THIN1: 448254885Sdumbbell case V_0280A0_ARRAY_2D_TILED_THIN1: 449254885Sdumbbell tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; 450254885Sdumbbell break; 451254885Sdumbbell } 452254885Sdumbbell if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 453254885Sdumbbell if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 454254885Sdumbbell /* the initial DDX does bad things with the CB size occasionally */ 455254885Sdumbbell /* it rounds up height too far for slice tile max but the BO is smaller */ 456254885Sdumbbell /* r600c,g also seem to flush at bad times in some apps resulting in 457254885Sdumbbell * bogus values here. So for linear just allow anything to avoid breaking 458254885Sdumbbell * broken userspace. 459254885Sdumbbell */ 460254885Sdumbbell } else { 461254885Sdumbbell dev_warn(p->dev, "%s offset[%d] %d %ju %d %lu too big (%d %d) (%d %d %d)\n", 462254885Sdumbbell __func__, i, array_mode, 463254885Sdumbbell (uintmax_t)track->cb_color_bo_offset[i], tmp, 464254885Sdumbbell radeon_bo_size(track->cb_color_bo[i]), 465254885Sdumbbell pitch, height, r600_fmt_get_nblocksx(format, pitch), 466254885Sdumbbell r600_fmt_get_nblocksy(format, height), 467254885Sdumbbell r600_fmt_get_blocksize(format)); 468254885Sdumbbell return -EINVAL; 469254885Sdumbbell } 470254885Sdumbbell } 471254885Sdumbbell /* limit max tile */ 472254885Sdumbbell tmp = (height * pitch) >> 6; 473254885Sdumbbell if (tmp < slice_tile_max) 474254885Sdumbbell slice_tile_max = tmp; 475254885Sdumbbell tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 476254885Sdumbbell S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 477254885Sdumbbell ib[track->cb_color_size_idx[i]] = tmp; 478254885Sdumbbell 479254885Sdumbbell /* FMASK/CMASK */ 480254885Sdumbbell switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { 481254885Sdumbbell case V_0280A0_TILE_DISABLE: 482254885Sdumbbell break; 483254885Sdumbbell case V_0280A0_FRAG_ENABLE: 484254885Sdumbbell if (track->nsamples > 1) { 485254885Sdumbbell uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); 486254885Sdumbbell /* the tile size is 8x8, but the size is in units of bits. 487254885Sdumbbell * for bytes, do just * 8. */ 488254885Sdumbbell uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); 489254885Sdumbbell 490254885Sdumbbell if (bytes + track->cb_color_frag_offset[i] > 491254885Sdumbbell radeon_bo_size(track->cb_color_frag_bo[i])) { 492254885Sdumbbell dev_warn(p->dev, "%s FMASK_TILE_MAX too large " 493254885Sdumbbell "(tile_max=%u, bytes=%u, offset=%ju, bo_size=%lu)\n", 494254885Sdumbbell __func__, tile_max, bytes, 495254885Sdumbbell (uintmax_t)track->cb_color_frag_offset[i], 496254885Sdumbbell radeon_bo_size(track->cb_color_frag_bo[i])); 497254885Sdumbbell return -EINVAL; 498254885Sdumbbell } 499254885Sdumbbell } 500254885Sdumbbell /* fall through */ 501254885Sdumbbell case V_0280A0_CLEAR_ENABLE: 502254885Sdumbbell { 503254885Sdumbbell uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); 504254885Sdumbbell /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. 505254885Sdumbbell * (128*128) / (8*8) / 2 = 128 bytes per block. */ 506254885Sdumbbell uint32_t bytes = (block_max + 1) * 128; 507254885Sdumbbell 508254885Sdumbbell if (bytes + track->cb_color_tile_offset[i] > 509254885Sdumbbell radeon_bo_size(track->cb_color_tile_bo[i])) { 510254885Sdumbbell dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " 511254885Sdumbbell "(block_max=%u, bytes=%u, offset=%ju, bo_size=%lu)\n", 512254885Sdumbbell __func__, block_max, bytes, 513254885Sdumbbell (uintmax_t)track->cb_color_tile_offset[i], 514254885Sdumbbell radeon_bo_size(track->cb_color_tile_bo[i])); 515254885Sdumbbell return -EINVAL; 516254885Sdumbbell } 517254885Sdumbbell break; 518254885Sdumbbell } 519254885Sdumbbell default: 520254885Sdumbbell dev_warn(p->dev, "%s invalid tile mode\n", __func__); 521254885Sdumbbell return -EINVAL; 522254885Sdumbbell } 523254885Sdumbbell return 0; 524254885Sdumbbell} 525254885Sdumbbell 526254885Sdumbbellstatic int r600_cs_track_validate_db(struct radeon_cs_parser *p) 527254885Sdumbbell{ 528254885Sdumbbell struct r600_cs_track *track = p->track; 529254885Sdumbbell u32 nviews, bpe, ntiles, size, slice_tile_max, tmp; 530254885Sdumbbell u32 height_align, pitch_align, depth_align; 531254885Sdumbbell u32 pitch = 8192; 532254885Sdumbbell u32 height = 8192; 533254885Sdumbbell u64 base_offset, base_align; 534254885Sdumbbell struct array_mode_checker array_check; 535254885Sdumbbell int array_mode; 536254885Sdumbbell volatile u32 *ib = p->ib.ptr; 537254885Sdumbbell 538254885Sdumbbell 539254885Sdumbbell if (track->db_bo == NULL) { 540254885Sdumbbell dev_warn(p->dev, "z/stencil with no depth buffer\n"); 541254885Sdumbbell return -EINVAL; 542254885Sdumbbell } 543254885Sdumbbell switch (G_028010_FORMAT(track->db_depth_info)) { 544254885Sdumbbell case V_028010_DEPTH_16: 545254885Sdumbbell bpe = 2; 546254885Sdumbbell break; 547254885Sdumbbell case V_028010_DEPTH_X8_24: 548254885Sdumbbell case V_028010_DEPTH_8_24: 549254885Sdumbbell case V_028010_DEPTH_X8_24_FLOAT: 550254885Sdumbbell case V_028010_DEPTH_8_24_FLOAT: 551254885Sdumbbell case V_028010_DEPTH_32_FLOAT: 552254885Sdumbbell bpe = 4; 553254885Sdumbbell break; 554254885Sdumbbell case V_028010_DEPTH_X24_8_32_FLOAT: 555254885Sdumbbell bpe = 8; 556254885Sdumbbell break; 557254885Sdumbbell default: 558254885Sdumbbell dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); 559254885Sdumbbell return -EINVAL; 560254885Sdumbbell } 561254885Sdumbbell if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 562254885Sdumbbell if (!track->db_depth_size_idx) { 563254885Sdumbbell dev_warn(p->dev, "z/stencil buffer size not set\n"); 564254885Sdumbbell return -EINVAL; 565254885Sdumbbell } 566254885Sdumbbell tmp = radeon_bo_size(track->db_bo) - track->db_offset; 567254885Sdumbbell tmp = (tmp / bpe) >> 6; 568254885Sdumbbell if (!tmp) { 569254885Sdumbbell dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", 570254885Sdumbbell track->db_depth_size, bpe, track->db_offset, 571254885Sdumbbell radeon_bo_size(track->db_bo)); 572254885Sdumbbell return -EINVAL; 573254885Sdumbbell } 574254885Sdumbbell ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 575254885Sdumbbell } else { 576254885Sdumbbell size = radeon_bo_size(track->db_bo); 577254885Sdumbbell /* pitch in pixels */ 578254885Sdumbbell pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; 579254885Sdumbbell slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 580254885Sdumbbell slice_tile_max *= 64; 581254885Sdumbbell height = slice_tile_max / pitch; 582254885Sdumbbell if (height > 8192) 583254885Sdumbbell height = 8192; 584254885Sdumbbell base_offset = track->db_bo_mc + track->db_offset; 585254885Sdumbbell array_mode = G_028010_ARRAY_MODE(track->db_depth_info); 586254885Sdumbbell array_check.array_mode = array_mode; 587254885Sdumbbell array_check.group_size = track->group_size; 588254885Sdumbbell array_check.nbanks = track->nbanks; 589254885Sdumbbell array_check.npipes = track->npipes; 590254885Sdumbbell array_check.nsamples = track->nsamples; 591254885Sdumbbell array_check.blocksize = bpe; 592254885Sdumbbell if (r600_get_array_mode_alignment(&array_check, 593254885Sdumbbell &pitch_align, &height_align, &depth_align, &base_align)) { 594254885Sdumbbell dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 595254885Sdumbbell G_028010_ARRAY_MODE(track->db_depth_info), 596254885Sdumbbell track->db_depth_info); 597254885Sdumbbell return -EINVAL; 598254885Sdumbbell } 599254885Sdumbbell switch (array_mode) { 600254885Sdumbbell case V_028010_ARRAY_1D_TILED_THIN1: 601254885Sdumbbell /* don't break userspace */ 602254885Sdumbbell height &= ~0x7; 603254885Sdumbbell break; 604254885Sdumbbell case V_028010_ARRAY_2D_TILED_THIN1: 605254885Sdumbbell break; 606254885Sdumbbell default: 607254885Sdumbbell dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 608254885Sdumbbell G_028010_ARRAY_MODE(track->db_depth_info), 609254885Sdumbbell track->db_depth_info); 610254885Sdumbbell return -EINVAL; 611254885Sdumbbell } 612254885Sdumbbell 613254885Sdumbbell if (!IS_ALIGNED(pitch, pitch_align)) { 614254885Sdumbbell dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 615254885Sdumbbell __func__, __LINE__, pitch, pitch_align, array_mode); 616254885Sdumbbell return -EINVAL; 617254885Sdumbbell } 618254885Sdumbbell if (!IS_ALIGNED(height, height_align)) { 619254885Sdumbbell dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 620254885Sdumbbell __func__, __LINE__, height, height_align, array_mode); 621254885Sdumbbell return -EINVAL; 622254885Sdumbbell } 623254885Sdumbbell if (!IS_ALIGNED(base_offset, base_align)) { 624254885Sdumbbell dev_warn(p->dev, "%s offset 0x%jx, 0x%jx, %d not aligned\n", __func__, 625254885Sdumbbell (uintmax_t)base_offset, (uintmax_t)base_align, array_mode); 626254885Sdumbbell return -EINVAL; 627254885Sdumbbell } 628254885Sdumbbell 629254885Sdumbbell ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 630254885Sdumbbell nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 631254885Sdumbbell tmp = ntiles * bpe * 64 * nviews * track->nsamples; 632254885Sdumbbell if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 633254885Sdumbbell dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 634254885Sdumbbell array_mode, 635254885Sdumbbell track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 636254885Sdumbbell radeon_bo_size(track->db_bo)); 637254885Sdumbbell return -EINVAL; 638254885Sdumbbell } 639254885Sdumbbell } 640254885Sdumbbell 641254885Sdumbbell /* hyperz */ 642254885Sdumbbell if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { 643254885Sdumbbell unsigned long size; 644254885Sdumbbell unsigned nbx, nby; 645254885Sdumbbell 646254885Sdumbbell if (track->htile_bo == NULL) { 647254885Sdumbbell dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 648254885Sdumbbell __func__, __LINE__, track->db_depth_info); 649254885Sdumbbell return -EINVAL; 650254885Sdumbbell } 651254885Sdumbbell if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 652254885Sdumbbell dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", 653254885Sdumbbell __func__, __LINE__, track->db_depth_size); 654254885Sdumbbell return -EINVAL; 655254885Sdumbbell } 656254885Sdumbbell 657254885Sdumbbell nbx = pitch; 658254885Sdumbbell nby = height; 659254885Sdumbbell if (G_028D24_LINEAR(track->htile_surface)) { 660254885Sdumbbell /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ 661254885Sdumbbell nbx = roundup2(nbx, 16 * 8); 662254885Sdumbbell /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ 663254885Sdumbbell nby = roundup(nby, track->npipes * 8); 664254885Sdumbbell } else { 665254885Sdumbbell /* always assume 8x8 htile */ 666254885Sdumbbell /* align is htile align * 8, htile align vary according to 667254885Sdumbbell * number of pipe and tile width and nby 668254885Sdumbbell */ 669254885Sdumbbell switch (track->npipes) { 670254885Sdumbbell case 8: 671254885Sdumbbell /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 672254885Sdumbbell nbx = roundup2(nbx, 64 * 8); 673254885Sdumbbell nby = roundup2(nby, 64 * 8); 674254885Sdumbbell break; 675254885Sdumbbell case 4: 676254885Sdumbbell /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 677254885Sdumbbell nbx = roundup2(nbx, 64 * 8); 678254885Sdumbbell nby = roundup2(nby, 32 * 8); 679254885Sdumbbell break; 680254885Sdumbbell case 2: 681254885Sdumbbell /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 682254885Sdumbbell nbx = roundup2(nbx, 32 * 8); 683254885Sdumbbell nby = roundup2(nby, 32 * 8); 684254885Sdumbbell break; 685254885Sdumbbell case 1: 686254885Sdumbbell /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 687254885Sdumbbell nbx = roundup2(nbx, 32 * 8); 688254885Sdumbbell nby = roundup2(nby, 16 * 8); 689254885Sdumbbell break; 690254885Sdumbbell default: 691254885Sdumbbell dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 692254885Sdumbbell __func__, __LINE__, track->npipes); 693254885Sdumbbell return -EINVAL; 694254885Sdumbbell } 695254885Sdumbbell } 696254885Sdumbbell /* compute number of htile */ 697254885Sdumbbell nbx = nbx >> 3; 698254885Sdumbbell nby = nby >> 3; 699254885Sdumbbell /* size must be aligned on npipes * 2K boundary */ 700254885Sdumbbell size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); 701254885Sdumbbell size += track->htile_offset; 702254885Sdumbbell 703254885Sdumbbell if (size > radeon_bo_size(track->htile_bo)) { 704254885Sdumbbell dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 705254885Sdumbbell __func__, __LINE__, radeon_bo_size(track->htile_bo), 706254885Sdumbbell size, nbx, nby); 707254885Sdumbbell return -EINVAL; 708254885Sdumbbell } 709254885Sdumbbell } 710254885Sdumbbell 711254885Sdumbbell track->db_dirty = false; 712254885Sdumbbell return 0; 713254885Sdumbbell} 714254885Sdumbbell 715254885Sdumbbellstatic int r600_cs_track_check(struct radeon_cs_parser *p) 716254885Sdumbbell{ 717254885Sdumbbell struct r600_cs_track *track = p->track; 718254885Sdumbbell u32 tmp; 719254885Sdumbbell int r, i; 720254885Sdumbbell 721254885Sdumbbell /* on legacy kernel we don't perform advanced check */ 722254885Sdumbbell if (p->rdev == NULL) 723254885Sdumbbell return 0; 724254885Sdumbbell 725254885Sdumbbell /* check streamout */ 726254885Sdumbbell if (track->streamout_dirty && track->vgt_strmout_en) { 727254885Sdumbbell for (i = 0; i < 4; i++) { 728254885Sdumbbell if (track->vgt_strmout_buffer_en & (1 << i)) { 729254885Sdumbbell if (track->vgt_strmout_bo[i]) { 730254885Sdumbbell u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 731254885Sdumbbell (u64)track->vgt_strmout_size[i]; 732254885Sdumbbell if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 733254885Sdumbbell DRM_ERROR("streamout %d bo too small: 0x%jx, 0x%lx\n", 734254885Sdumbbell i, (uintmax_t)offset, 735254885Sdumbbell radeon_bo_size(track->vgt_strmout_bo[i])); 736254885Sdumbbell return -EINVAL; 737254885Sdumbbell } 738254885Sdumbbell } else { 739254885Sdumbbell dev_warn(p->dev, "No buffer for streamout %d\n", i); 740254885Sdumbbell return -EINVAL; 741254885Sdumbbell } 742254885Sdumbbell } 743254885Sdumbbell } 744254885Sdumbbell track->streamout_dirty = false; 745254885Sdumbbell } 746254885Sdumbbell 747254885Sdumbbell if (track->sx_misc_kill_all_prims) 748254885Sdumbbell return 0; 749254885Sdumbbell 750254885Sdumbbell /* check that we have a cb for each enabled target, we don't check 751254885Sdumbbell * shader_mask because it seems mesa isn't always setting it :( 752254885Sdumbbell */ 753254885Sdumbbell if (track->cb_dirty) { 754254885Sdumbbell tmp = track->cb_target_mask; 755254885Sdumbbell 756254885Sdumbbell /* We must check both colorbuffers for RESOLVE. */ 757254885Sdumbbell if (track->is_resolve) { 758254885Sdumbbell tmp |= 0xff; 759254885Sdumbbell } 760254885Sdumbbell 761254885Sdumbbell for (i = 0; i < 8; i++) { 762254885Sdumbbell if ((tmp >> (i * 4)) & 0xF) { 763254885Sdumbbell /* at least one component is enabled */ 764254885Sdumbbell if (track->cb_color_bo[i] == NULL) { 765254885Sdumbbell dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 766254885Sdumbbell __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 767254885Sdumbbell return -EINVAL; 768254885Sdumbbell } 769254885Sdumbbell /* perform rewrite of CB_COLOR[0-7]_SIZE */ 770254885Sdumbbell r = r600_cs_track_validate_cb(p, i); 771254885Sdumbbell if (r) 772254885Sdumbbell return r; 773254885Sdumbbell } 774254885Sdumbbell } 775254885Sdumbbell track->cb_dirty = false; 776254885Sdumbbell } 777254885Sdumbbell 778254885Sdumbbell /* Check depth buffer */ 779254885Sdumbbell if (track->db_dirty && 780254885Sdumbbell G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && 781254885Sdumbbell (G_028800_STENCIL_ENABLE(track->db_depth_control) || 782254885Sdumbbell G_028800_Z_ENABLE(track->db_depth_control))) { 783254885Sdumbbell r = r600_cs_track_validate_db(p); 784254885Sdumbbell if (r) 785254885Sdumbbell return r; 786254885Sdumbbell } 787254885Sdumbbell 788254885Sdumbbell return 0; 789254885Sdumbbell} 790254885Sdumbbell 791254885Sdumbbell/** 792254885Sdumbbell * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 793254885Sdumbbell * @parser: parser structure holding parsing context. 794254885Sdumbbell * @pkt: where to store packet informations 795254885Sdumbbell * 796254885Sdumbbell * Assume that chunk_ib_index is properly set. Will return -EINVAL 797254885Sdumbbell * if packet is bigger than remaining ib size. or if packets is unknown. 798254885Sdumbbell **/ 799254885Sdumbbellstatic int r600_cs_packet_parse(struct radeon_cs_parser *p, 800254885Sdumbbell struct radeon_cs_packet *pkt, 801254885Sdumbbell unsigned idx) 802254885Sdumbbell{ 803254885Sdumbbell struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 804254885Sdumbbell uint32_t header; 805254885Sdumbbell 806254885Sdumbbell if (idx >= ib_chunk->length_dw) { 807254885Sdumbbell DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 808254885Sdumbbell idx, ib_chunk->length_dw); 809254885Sdumbbell return -EINVAL; 810254885Sdumbbell } 811254885Sdumbbell header = radeon_get_ib_value(p, idx); 812254885Sdumbbell pkt->idx = idx; 813254885Sdumbbell pkt->type = CP_PACKET_GET_TYPE(header); 814254885Sdumbbell pkt->count = CP_PACKET_GET_COUNT(header); 815254885Sdumbbell pkt->one_reg_wr = 0; 816254885Sdumbbell switch (pkt->type) { 817254885Sdumbbell case PACKET_TYPE0: 818254885Sdumbbell pkt->reg = CP_PACKET0_GET_REG(header); 819254885Sdumbbell break; 820254885Sdumbbell case PACKET_TYPE3: 821254885Sdumbbell pkt->opcode = CP_PACKET3_GET_OPCODE(header); 822254885Sdumbbell break; 823254885Sdumbbell case PACKET_TYPE2: 824254885Sdumbbell pkt->count = -1; 825254885Sdumbbell break; 826254885Sdumbbell default: 827254885Sdumbbell DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 828254885Sdumbbell return -EINVAL; 829254885Sdumbbell } 830254885Sdumbbell if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 831254885Sdumbbell DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 832254885Sdumbbell pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 833254885Sdumbbell return -EINVAL; 834254885Sdumbbell } 835254885Sdumbbell return 0; 836254885Sdumbbell} 837254885Sdumbbell 838254885Sdumbbell/** 839254885Sdumbbell * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 840254885Sdumbbell * @parser: parser structure holding parsing context. 841254885Sdumbbell * @data: pointer to relocation data 842254885Sdumbbell * @offset_start: starting offset 843254885Sdumbbell * @offset_mask: offset mask (to align start offset on) 844254885Sdumbbell * @reloc: reloc informations 845254885Sdumbbell * 846254885Sdumbbell * Check next packet is relocation packet3, do bo validation and compute 847254885Sdumbbell * GPU offset using the provided start. 848254885Sdumbbell **/ 849254885Sdumbbellstatic int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 850254885Sdumbbell struct radeon_cs_reloc **cs_reloc) 851254885Sdumbbell{ 852254885Sdumbbell struct radeon_cs_chunk *relocs_chunk; 853254885Sdumbbell struct radeon_cs_packet p3reloc; 854254885Sdumbbell unsigned idx; 855254885Sdumbbell int r; 856254885Sdumbbell 857254885Sdumbbell if (p->chunk_relocs_idx == -1) { 858254885Sdumbbell DRM_ERROR("No relocation chunk !\n"); 859254885Sdumbbell return -EINVAL; 860254885Sdumbbell } 861254885Sdumbbell *cs_reloc = NULL; 862254885Sdumbbell relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 863254885Sdumbbell r = r600_cs_packet_parse(p, &p3reloc, p->idx); 864254885Sdumbbell if (r) { 865254885Sdumbbell return r; 866254885Sdumbbell } 867254885Sdumbbell p->idx += p3reloc.count + 2; 868254885Sdumbbell if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 869254885Sdumbbell DRM_ERROR("No packet3 for relocation for packet at %d.\n", 870254885Sdumbbell p3reloc.idx); 871254885Sdumbbell return -EINVAL; 872254885Sdumbbell } 873254885Sdumbbell idx = radeon_get_ib_value(p, p3reloc.idx + 1); 874254885Sdumbbell if (idx >= relocs_chunk->length_dw) { 875254885Sdumbbell DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 876254885Sdumbbell idx, relocs_chunk->length_dw); 877254885Sdumbbell return -EINVAL; 878254885Sdumbbell } 879254885Sdumbbell /* FIXME: we assume reloc size is 4 dwords */ 880254885Sdumbbell *cs_reloc = p->relocs_ptr[(idx / 4)]; 881254885Sdumbbell return 0; 882254885Sdumbbell} 883254885Sdumbbell 884254885Sdumbbell/** 885254885Sdumbbell * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 886254885Sdumbbell * @parser: parser structure holding parsing context. 887254885Sdumbbell * @data: pointer to relocation data 888254885Sdumbbell * @offset_start: starting offset 889254885Sdumbbell * @offset_mask: offset mask (to align start offset on) 890254885Sdumbbell * @reloc: reloc informations 891254885Sdumbbell * 892254885Sdumbbell * Check next packet is relocation packet3, do bo validation and compute 893254885Sdumbbell * GPU offset using the provided start. 894254885Sdumbbell **/ 895254885Sdumbbellstatic int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 896254885Sdumbbell struct radeon_cs_reloc **cs_reloc) 897254885Sdumbbell{ 898254885Sdumbbell struct radeon_cs_chunk *relocs_chunk; 899254885Sdumbbell struct radeon_cs_packet p3reloc; 900254885Sdumbbell unsigned idx; 901254885Sdumbbell int r; 902254885Sdumbbell 903254885Sdumbbell if (p->chunk_relocs_idx == -1) { 904254885Sdumbbell DRM_ERROR("No relocation chunk !\n"); 905254885Sdumbbell return -EINVAL; 906254885Sdumbbell } 907254885Sdumbbell *cs_reloc = NULL; 908254885Sdumbbell relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 909254885Sdumbbell r = r600_cs_packet_parse(p, &p3reloc, p->idx); 910254885Sdumbbell if (r) { 911254885Sdumbbell return r; 912254885Sdumbbell } 913254885Sdumbbell p->idx += p3reloc.count + 2; 914254885Sdumbbell if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 915254885Sdumbbell DRM_ERROR("No packet3 for relocation for packet at %d.\n", 916254885Sdumbbell p3reloc.idx); 917254885Sdumbbell return -EINVAL; 918254885Sdumbbell } 919254885Sdumbbell idx = radeon_get_ib_value(p, p3reloc.idx + 1); 920254885Sdumbbell if (idx >= relocs_chunk->length_dw) { 921254885Sdumbbell DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 922254885Sdumbbell idx, relocs_chunk->length_dw); 923254885Sdumbbell return -EINVAL; 924254885Sdumbbell } 925254885Sdumbbell *cs_reloc = p->relocs; 926254885Sdumbbell (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; 927254885Sdumbbell (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 928254885Sdumbbell return 0; 929254885Sdumbbell} 930254885Sdumbbell 931254885Sdumbbell/** 932254885Sdumbbell * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc 933254885Sdumbbell * @parser: parser structure holding parsing context. 934254885Sdumbbell * 935254885Sdumbbell * Check next packet is relocation packet3, do bo validation and compute 936254885Sdumbbell * GPU offset using the provided start. 937254885Sdumbbell **/ 938254885Sdumbbellstatic int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 939254885Sdumbbell{ 940254885Sdumbbell struct radeon_cs_packet p3reloc; 941254885Sdumbbell int r; 942254885Sdumbbell 943254885Sdumbbell r = r600_cs_packet_parse(p, &p3reloc, p->idx); 944254885Sdumbbell if (r) { 945254885Sdumbbell return 0; 946254885Sdumbbell } 947254885Sdumbbell if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 948254885Sdumbbell return 0; 949254885Sdumbbell } 950254885Sdumbbell return 1; 951254885Sdumbbell} 952254885Sdumbbell 953254885Sdumbbell/** 954254885Sdumbbell * r600_cs_packet_next_vline() - parse userspace VLINE packet 955254885Sdumbbell * @parser: parser structure holding parsing context. 956254885Sdumbbell * 957254885Sdumbbell * Userspace sends a special sequence for VLINE waits. 958254885Sdumbbell * PACKET0 - VLINE_START_END + value 959254885Sdumbbell * PACKET3 - WAIT_REG_MEM poll vline status reg 960254885Sdumbbell * RELOC (P3) - crtc_id in reloc. 961254885Sdumbbell * 962254885Sdumbbell * This function parses this and relocates the VLINE START END 963254885Sdumbbell * and WAIT_REG_MEM packets to the correct crtc. 964254885Sdumbbell * It also detects a switched off crtc and nulls out the 965254885Sdumbbell * wait in that case. 966254885Sdumbbell */ 967254885Sdumbbellstatic int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) 968254885Sdumbbell{ 969254885Sdumbbell struct drm_mode_object *obj; 970254885Sdumbbell struct drm_crtc *crtc; 971254885Sdumbbell struct radeon_crtc *radeon_crtc; 972254885Sdumbbell struct radeon_cs_packet p3reloc, wait_reg_mem; 973254885Sdumbbell int crtc_id; 974254885Sdumbbell int r; 975254885Sdumbbell uint32_t header, h_idx, reg, wait_reg_mem_info; 976254885Sdumbbell volatile uint32_t *ib; 977254885Sdumbbell 978254885Sdumbbell ib = p->ib.ptr; 979254885Sdumbbell 980254885Sdumbbell /* parse the WAIT_REG_MEM */ 981254885Sdumbbell r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx); 982254885Sdumbbell if (r) 983254885Sdumbbell return r; 984254885Sdumbbell 985254885Sdumbbell /* check its a WAIT_REG_MEM */ 986254885Sdumbbell if (wait_reg_mem.type != PACKET_TYPE3 || 987254885Sdumbbell wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 988254885Sdumbbell DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 989254885Sdumbbell return -EINVAL; 990254885Sdumbbell } 991254885Sdumbbell 992254885Sdumbbell wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 993254885Sdumbbell /* bit 4 is reg (0) or mem (1) */ 994254885Sdumbbell if (wait_reg_mem_info & 0x10) { 995254885Sdumbbell DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 996254885Sdumbbell return -EINVAL; 997254885Sdumbbell } 998254885Sdumbbell /* waiting for value to be equal */ 999254885Sdumbbell if ((wait_reg_mem_info & 0x7) != 0x3) { 1000254885Sdumbbell DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 1001254885Sdumbbell return -EINVAL; 1002254885Sdumbbell } 1003254885Sdumbbell if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { 1004254885Sdumbbell DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 1005254885Sdumbbell return -EINVAL; 1006254885Sdumbbell } 1007254885Sdumbbell 1008254885Sdumbbell if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { 1009254885Sdumbbell DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 1010254885Sdumbbell return -EINVAL; 1011254885Sdumbbell } 1012254885Sdumbbell 1013254885Sdumbbell /* jump over the NOP */ 1014254885Sdumbbell r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); 1015254885Sdumbbell if (r) 1016254885Sdumbbell return r; 1017254885Sdumbbell 1018254885Sdumbbell h_idx = p->idx - 2; 1019254885Sdumbbell p->idx += wait_reg_mem.count + 2; 1020254885Sdumbbell p->idx += p3reloc.count + 2; 1021254885Sdumbbell 1022254885Sdumbbell header = radeon_get_ib_value(p, h_idx); 1023254885Sdumbbell crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 1024254885Sdumbbell reg = CP_PACKET0_GET_REG(header); 1025254885Sdumbbell 1026254885Sdumbbell obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1027254885Sdumbbell if (!obj) { 1028254885Sdumbbell DRM_ERROR("cannot find crtc %d\n", crtc_id); 1029254885Sdumbbell return -EINVAL; 1030254885Sdumbbell } 1031254885Sdumbbell crtc = obj_to_crtc(obj); 1032254885Sdumbbell radeon_crtc = to_radeon_crtc(crtc); 1033254885Sdumbbell crtc_id = radeon_crtc->crtc_id; 1034254885Sdumbbell 1035254885Sdumbbell if (!crtc->enabled) { 1036254885Sdumbbell /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 1037254885Sdumbbell ib[h_idx + 2] = PACKET2(0); 1038254885Sdumbbell ib[h_idx + 3] = PACKET2(0); 1039254885Sdumbbell ib[h_idx + 4] = PACKET2(0); 1040254885Sdumbbell ib[h_idx + 5] = PACKET2(0); 1041254885Sdumbbell ib[h_idx + 6] = PACKET2(0); 1042254885Sdumbbell ib[h_idx + 7] = PACKET2(0); 1043254885Sdumbbell ib[h_idx + 8] = PACKET2(0); 1044254885Sdumbbell } else if (crtc_id == 1) { 1045254885Sdumbbell switch (reg) { 1046254885Sdumbbell case AVIVO_D1MODE_VLINE_START_END: 1047254885Sdumbbell header &= ~R600_CP_PACKET0_REG_MASK; 1048254885Sdumbbell header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1049254885Sdumbbell break; 1050254885Sdumbbell default: 1051254885Sdumbbell DRM_ERROR("unknown crtc reloc\n"); 1052254885Sdumbbell return -EINVAL; 1053254885Sdumbbell } 1054254885Sdumbbell ib[h_idx] = header; 1055254885Sdumbbell ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; 1056254885Sdumbbell } 1057254885Sdumbbell 1058254885Sdumbbell return 0; 1059254885Sdumbbell} 1060254885Sdumbbell 1061254885Sdumbbellstatic int r600_packet0_check(struct radeon_cs_parser *p, 1062254885Sdumbbell struct radeon_cs_packet *pkt, 1063254885Sdumbbell unsigned idx, unsigned reg) 1064254885Sdumbbell{ 1065254885Sdumbbell int r; 1066254885Sdumbbell 1067254885Sdumbbell switch (reg) { 1068254885Sdumbbell case AVIVO_D1MODE_VLINE_START_END: 1069254885Sdumbbell r = r600_cs_packet_parse_vline(p); 1070254885Sdumbbell if (r) { 1071254885Sdumbbell DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1072254885Sdumbbell idx, reg); 1073254885Sdumbbell return r; 1074254885Sdumbbell } 1075254885Sdumbbell break; 1076254885Sdumbbell default: 1077254885Sdumbbell DRM_ERROR("Forbidden register 0x%04X in cs at %d\n", 1078254885Sdumbbell reg, idx); 1079254885Sdumbbell return -EINVAL; 1080254885Sdumbbell } 1081254885Sdumbbell return 0; 1082254885Sdumbbell} 1083254885Sdumbbell 1084254885Sdumbbellstatic int r600_cs_parse_packet0(struct radeon_cs_parser *p, 1085254885Sdumbbell struct radeon_cs_packet *pkt) 1086254885Sdumbbell{ 1087254885Sdumbbell unsigned reg, i; 1088254885Sdumbbell unsigned idx; 1089254885Sdumbbell int r; 1090254885Sdumbbell 1091254885Sdumbbell idx = pkt->idx + 1; 1092254885Sdumbbell reg = pkt->reg; 1093254885Sdumbbell for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1094254885Sdumbbell r = r600_packet0_check(p, pkt, idx, reg); 1095254885Sdumbbell if (r) { 1096254885Sdumbbell return r; 1097254885Sdumbbell } 1098254885Sdumbbell } 1099254885Sdumbbell return 0; 1100254885Sdumbbell} 1101254885Sdumbbell 1102254885Sdumbbell/** 1103254885Sdumbbell * r600_cs_check_reg() - check if register is authorized or not 1104254885Sdumbbell * @parser: parser structure holding parsing context 1105254885Sdumbbell * @reg: register we are testing 1106254885Sdumbbell * @idx: index into the cs buffer 1107254885Sdumbbell * 1108254885Sdumbbell * This function will test against r600_reg_safe_bm and return 0 1109254885Sdumbbell * if register is safe. If register is not flag as safe this function 1110254885Sdumbbell * will test it against a list of register needind special handling. 1111254885Sdumbbell */ 1112254885Sdumbbellstatic int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1113254885Sdumbbell{ 1114254885Sdumbbell struct r600_cs_track *track = (struct r600_cs_track *)p->track; 1115254885Sdumbbell struct radeon_cs_reloc *reloc; 1116254885Sdumbbell u32 m, i, tmp, *ib; 1117254885Sdumbbell int r; 1118254885Sdumbbell 1119254885Sdumbbell i = (reg >> 7); 1120254885Sdumbbell if (i >= DRM_ARRAY_SIZE(r600_reg_safe_bm)) { 1121254885Sdumbbell dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1122254885Sdumbbell return -EINVAL; 1123254885Sdumbbell } 1124254885Sdumbbell m = 1 << ((reg >> 2) & 31); 1125254885Sdumbbell if (!(r600_reg_safe_bm[i] & m)) 1126254885Sdumbbell return 0; 1127254885Sdumbbell ib = p->ib.ptr; 1128254885Sdumbbell switch (reg) { 1129254885Sdumbbell /* force following reg to 0 in an attempt to disable out buffer 1130254885Sdumbbell * which will need us to better understand how it works to perform 1131254885Sdumbbell * security check on it (Jerome) 1132254885Sdumbbell */ 1133254885Sdumbbell case R_0288A8_SQ_ESGS_RING_ITEMSIZE: 1134254885Sdumbbell case R_008C44_SQ_ESGS_RING_SIZE: 1135254885Sdumbbell case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: 1136254885Sdumbbell case R_008C54_SQ_ESTMP_RING_SIZE: 1137254885Sdumbbell case R_0288C0_SQ_FBUF_RING_ITEMSIZE: 1138254885Sdumbbell case R_008C74_SQ_FBUF_RING_SIZE: 1139254885Sdumbbell case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: 1140254885Sdumbbell case R_008C5C_SQ_GSTMP_RING_SIZE: 1141254885Sdumbbell case R_0288AC_SQ_GSVS_RING_ITEMSIZE: 1142254885Sdumbbell case R_008C4C_SQ_GSVS_RING_SIZE: 1143254885Sdumbbell case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: 1144254885Sdumbbell case R_008C6C_SQ_PSTMP_RING_SIZE: 1145254885Sdumbbell case R_0288C4_SQ_REDUC_RING_ITEMSIZE: 1146254885Sdumbbell case R_008C7C_SQ_REDUC_RING_SIZE: 1147254885Sdumbbell case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: 1148254885Sdumbbell case R_008C64_SQ_VSTMP_RING_SIZE: 1149254885Sdumbbell case R_0288C8_SQ_GS_VERT_ITEMSIZE: 1150254885Sdumbbell /* get value to populate the IB don't remove */ 1151254885Sdumbbell tmp =radeon_get_ib_value(p, idx); 1152254885Sdumbbell ib[idx] = 0; 1153254885Sdumbbell break; 1154254885Sdumbbell case SQ_CONFIG: 1155254885Sdumbbell track->sq_config = radeon_get_ib_value(p, idx); 1156254885Sdumbbell break; 1157254885Sdumbbell case R_028800_DB_DEPTH_CONTROL: 1158254885Sdumbbell track->db_depth_control = radeon_get_ib_value(p, idx); 1159254885Sdumbbell track->db_dirty = true; 1160254885Sdumbbell break; 1161254885Sdumbbell case R_028010_DB_DEPTH_INFO: 1162254885Sdumbbell if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1163254885Sdumbbell r600_cs_packet_next_is_pkt3_nop(p)) { 1164254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1165254885Sdumbbell if (r) { 1166254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1167254885Sdumbbell "0x%04X\n", reg); 1168254885Sdumbbell return -EINVAL; 1169254885Sdumbbell } 1170254885Sdumbbell track->db_depth_info = radeon_get_ib_value(p, idx); 1171254885Sdumbbell ib[idx] &= C_028010_ARRAY_MODE; 1172254885Sdumbbell track->db_depth_info &= C_028010_ARRAY_MODE; 1173254885Sdumbbell if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1174254885Sdumbbell ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1175254885Sdumbbell track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1176254885Sdumbbell } else { 1177254885Sdumbbell ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1178254885Sdumbbell track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1179254885Sdumbbell } 1180254885Sdumbbell } else { 1181254885Sdumbbell track->db_depth_info = radeon_get_ib_value(p, idx); 1182254885Sdumbbell } 1183254885Sdumbbell track->db_dirty = true; 1184254885Sdumbbell break; 1185254885Sdumbbell case R_028004_DB_DEPTH_VIEW: 1186254885Sdumbbell track->db_depth_view = radeon_get_ib_value(p, idx); 1187254885Sdumbbell track->db_dirty = true; 1188254885Sdumbbell break; 1189254885Sdumbbell case R_028000_DB_DEPTH_SIZE: 1190254885Sdumbbell track->db_depth_size = radeon_get_ib_value(p, idx); 1191254885Sdumbbell track->db_depth_size_idx = idx; 1192254885Sdumbbell track->db_dirty = true; 1193254885Sdumbbell break; 1194254885Sdumbbell case R_028AB0_VGT_STRMOUT_EN: 1195254885Sdumbbell track->vgt_strmout_en = radeon_get_ib_value(p, idx); 1196254885Sdumbbell track->streamout_dirty = true; 1197254885Sdumbbell break; 1198254885Sdumbbell case R_028B20_VGT_STRMOUT_BUFFER_EN: 1199254885Sdumbbell track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); 1200254885Sdumbbell track->streamout_dirty = true; 1201254885Sdumbbell break; 1202254885Sdumbbell case VGT_STRMOUT_BUFFER_BASE_0: 1203254885Sdumbbell case VGT_STRMOUT_BUFFER_BASE_1: 1204254885Sdumbbell case VGT_STRMOUT_BUFFER_BASE_2: 1205254885Sdumbbell case VGT_STRMOUT_BUFFER_BASE_3: 1206254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1207254885Sdumbbell if (r) { 1208254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1209254885Sdumbbell "0x%04X\n", reg); 1210254885Sdumbbell return -EINVAL; 1211254885Sdumbbell } 1212254885Sdumbbell tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1213254885Sdumbbell track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1214254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1215254885Sdumbbell track->vgt_strmout_bo[tmp] = reloc->robj; 1216254885Sdumbbell track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; 1217254885Sdumbbell track->streamout_dirty = true; 1218254885Sdumbbell break; 1219254885Sdumbbell case VGT_STRMOUT_BUFFER_SIZE_0: 1220254885Sdumbbell case VGT_STRMOUT_BUFFER_SIZE_1: 1221254885Sdumbbell case VGT_STRMOUT_BUFFER_SIZE_2: 1222254885Sdumbbell case VGT_STRMOUT_BUFFER_SIZE_3: 1223254885Sdumbbell tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1224254885Sdumbbell /* size in register is DWs, convert to bytes */ 1225254885Sdumbbell track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1226254885Sdumbbell track->streamout_dirty = true; 1227254885Sdumbbell break; 1228254885Sdumbbell case CP_COHER_BASE: 1229254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1230254885Sdumbbell if (r) { 1231254885Sdumbbell dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1232254885Sdumbbell "0x%04X\n", reg); 1233254885Sdumbbell return -EINVAL; 1234254885Sdumbbell } 1235254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1236254885Sdumbbell break; 1237254885Sdumbbell case R_028238_CB_TARGET_MASK: 1238254885Sdumbbell track->cb_target_mask = radeon_get_ib_value(p, idx); 1239254885Sdumbbell track->cb_dirty = true; 1240254885Sdumbbell break; 1241254885Sdumbbell case R_02823C_CB_SHADER_MASK: 1242254885Sdumbbell track->cb_shader_mask = radeon_get_ib_value(p, idx); 1243254885Sdumbbell break; 1244254885Sdumbbell case R_028C04_PA_SC_AA_CONFIG: 1245254885Sdumbbell tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1246254885Sdumbbell track->log_nsamples = tmp; 1247254885Sdumbbell track->nsamples = 1 << tmp; 1248254885Sdumbbell track->cb_dirty = true; 1249254885Sdumbbell break; 1250254885Sdumbbell case R_028808_CB_COLOR_CONTROL: 1251254885Sdumbbell tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); 1252254885Sdumbbell track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; 1253254885Sdumbbell track->cb_dirty = true; 1254254885Sdumbbell break; 1255254885Sdumbbell case R_0280A0_CB_COLOR0_INFO: 1256254885Sdumbbell case R_0280A4_CB_COLOR1_INFO: 1257254885Sdumbbell case R_0280A8_CB_COLOR2_INFO: 1258254885Sdumbbell case R_0280AC_CB_COLOR3_INFO: 1259254885Sdumbbell case R_0280B0_CB_COLOR4_INFO: 1260254885Sdumbbell case R_0280B4_CB_COLOR5_INFO: 1261254885Sdumbbell case R_0280B8_CB_COLOR6_INFO: 1262254885Sdumbbell case R_0280BC_CB_COLOR7_INFO: 1263254885Sdumbbell if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1264254885Sdumbbell r600_cs_packet_next_is_pkt3_nop(p)) { 1265254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1266254885Sdumbbell if (r) { 1267254885Sdumbbell dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1268254885Sdumbbell return -EINVAL; 1269254885Sdumbbell } 1270254885Sdumbbell tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1271254885Sdumbbell track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1272254885Sdumbbell if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1273254885Sdumbbell ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1274254885Sdumbbell track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1275254885Sdumbbell } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1276254885Sdumbbell ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1277254885Sdumbbell track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1278254885Sdumbbell } 1279254885Sdumbbell } else { 1280254885Sdumbbell tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1281254885Sdumbbell track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1282254885Sdumbbell } 1283254885Sdumbbell track->cb_dirty = true; 1284254885Sdumbbell break; 1285254885Sdumbbell case R_028080_CB_COLOR0_VIEW: 1286254885Sdumbbell case R_028084_CB_COLOR1_VIEW: 1287254885Sdumbbell case R_028088_CB_COLOR2_VIEW: 1288254885Sdumbbell case R_02808C_CB_COLOR3_VIEW: 1289254885Sdumbbell case R_028090_CB_COLOR4_VIEW: 1290254885Sdumbbell case R_028094_CB_COLOR5_VIEW: 1291254885Sdumbbell case R_028098_CB_COLOR6_VIEW: 1292254885Sdumbbell case R_02809C_CB_COLOR7_VIEW: 1293254885Sdumbbell tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; 1294254885Sdumbbell track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1295254885Sdumbbell track->cb_dirty = true; 1296254885Sdumbbell break; 1297254885Sdumbbell case R_028060_CB_COLOR0_SIZE: 1298254885Sdumbbell case R_028064_CB_COLOR1_SIZE: 1299254885Sdumbbell case R_028068_CB_COLOR2_SIZE: 1300254885Sdumbbell case R_02806C_CB_COLOR3_SIZE: 1301254885Sdumbbell case R_028070_CB_COLOR4_SIZE: 1302254885Sdumbbell case R_028074_CB_COLOR5_SIZE: 1303254885Sdumbbell case R_028078_CB_COLOR6_SIZE: 1304254885Sdumbbell case R_02807C_CB_COLOR7_SIZE: 1305254885Sdumbbell tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; 1306254885Sdumbbell track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); 1307254885Sdumbbell track->cb_color_size_idx[tmp] = idx; 1308254885Sdumbbell track->cb_dirty = true; 1309254885Sdumbbell break; 1310254885Sdumbbell /* This register were added late, there is userspace 1311254885Sdumbbell * which does provide relocation for those but set 1312254885Sdumbbell * 0 offset. In order to avoid breaking old userspace 1313254885Sdumbbell * we detect this and set address to point to last 1314254885Sdumbbell * CB_COLOR0_BASE, note that if userspace doesn't set 1315254885Sdumbbell * CB_COLOR0_BASE before this register we will report 1316254885Sdumbbell * error. Old userspace always set CB_COLOR0_BASE 1317254885Sdumbbell * before any of this. 1318254885Sdumbbell */ 1319254885Sdumbbell case R_0280E0_CB_COLOR0_FRAG: 1320254885Sdumbbell case R_0280E4_CB_COLOR1_FRAG: 1321254885Sdumbbell case R_0280E8_CB_COLOR2_FRAG: 1322254885Sdumbbell case R_0280EC_CB_COLOR3_FRAG: 1323254885Sdumbbell case R_0280F0_CB_COLOR4_FRAG: 1324254885Sdumbbell case R_0280F4_CB_COLOR5_FRAG: 1325254885Sdumbbell case R_0280F8_CB_COLOR6_FRAG: 1326254885Sdumbbell case R_0280FC_CB_COLOR7_FRAG: 1327254885Sdumbbell tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; 1328254885Sdumbbell if (!r600_cs_packet_next_is_pkt3_nop(p)) { 1329254885Sdumbbell if (!track->cb_color_base_last[tmp]) { 1330254885Sdumbbell dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1331254885Sdumbbell return -EINVAL; 1332254885Sdumbbell } 1333254885Sdumbbell track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1334254885Sdumbbell track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; 1335254885Sdumbbell ib[idx] = track->cb_color_base_last[tmp]; 1336254885Sdumbbell } else { 1337254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1338254885Sdumbbell if (r) { 1339254885Sdumbbell dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1340254885Sdumbbell return -EINVAL; 1341254885Sdumbbell } 1342254885Sdumbbell track->cb_color_frag_bo[tmp] = reloc->robj; 1343254885Sdumbbell track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; 1344254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1345254885Sdumbbell } 1346254885Sdumbbell if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1347254885Sdumbbell track->cb_dirty = true; 1348254885Sdumbbell } 1349254885Sdumbbell break; 1350254885Sdumbbell case R_0280C0_CB_COLOR0_TILE: 1351254885Sdumbbell case R_0280C4_CB_COLOR1_TILE: 1352254885Sdumbbell case R_0280C8_CB_COLOR2_TILE: 1353254885Sdumbbell case R_0280CC_CB_COLOR3_TILE: 1354254885Sdumbbell case R_0280D0_CB_COLOR4_TILE: 1355254885Sdumbbell case R_0280D4_CB_COLOR5_TILE: 1356254885Sdumbbell case R_0280D8_CB_COLOR6_TILE: 1357254885Sdumbbell case R_0280DC_CB_COLOR7_TILE: 1358254885Sdumbbell tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; 1359254885Sdumbbell if (!r600_cs_packet_next_is_pkt3_nop(p)) { 1360254885Sdumbbell if (!track->cb_color_base_last[tmp]) { 1361254885Sdumbbell dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1362254885Sdumbbell return -EINVAL; 1363254885Sdumbbell } 1364254885Sdumbbell track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1365254885Sdumbbell track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; 1366254885Sdumbbell ib[idx] = track->cb_color_base_last[tmp]; 1367254885Sdumbbell } else { 1368254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1369254885Sdumbbell if (r) { 1370254885Sdumbbell dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1371254885Sdumbbell return -EINVAL; 1372254885Sdumbbell } 1373254885Sdumbbell track->cb_color_tile_bo[tmp] = reloc->robj; 1374254885Sdumbbell track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; 1375254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1376254885Sdumbbell } 1377254885Sdumbbell if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1378254885Sdumbbell track->cb_dirty = true; 1379254885Sdumbbell } 1380254885Sdumbbell break; 1381254885Sdumbbell case R_028100_CB_COLOR0_MASK: 1382254885Sdumbbell case R_028104_CB_COLOR1_MASK: 1383254885Sdumbbell case R_028108_CB_COLOR2_MASK: 1384254885Sdumbbell case R_02810C_CB_COLOR3_MASK: 1385254885Sdumbbell case R_028110_CB_COLOR4_MASK: 1386254885Sdumbbell case R_028114_CB_COLOR5_MASK: 1387254885Sdumbbell case R_028118_CB_COLOR6_MASK: 1388254885Sdumbbell case R_02811C_CB_COLOR7_MASK: 1389254885Sdumbbell tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; 1390254885Sdumbbell track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); 1391254885Sdumbbell if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1392254885Sdumbbell track->cb_dirty = true; 1393254885Sdumbbell } 1394254885Sdumbbell break; 1395254885Sdumbbell case CB_COLOR0_BASE: 1396254885Sdumbbell case CB_COLOR1_BASE: 1397254885Sdumbbell case CB_COLOR2_BASE: 1398254885Sdumbbell case CB_COLOR3_BASE: 1399254885Sdumbbell case CB_COLOR4_BASE: 1400254885Sdumbbell case CB_COLOR5_BASE: 1401254885Sdumbbell case CB_COLOR6_BASE: 1402254885Sdumbbell case CB_COLOR7_BASE: 1403254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1404254885Sdumbbell if (r) { 1405254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1406254885Sdumbbell "0x%04X\n", reg); 1407254885Sdumbbell return -EINVAL; 1408254885Sdumbbell } 1409254885Sdumbbell tmp = (reg - CB_COLOR0_BASE) / 4; 1410254885Sdumbbell track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1411254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1412254885Sdumbbell track->cb_color_base_last[tmp] = ib[idx]; 1413254885Sdumbbell track->cb_color_bo[tmp] = reloc->robj; 1414254885Sdumbbell track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; 1415254885Sdumbbell track->cb_dirty = true; 1416254885Sdumbbell break; 1417254885Sdumbbell case DB_DEPTH_BASE: 1418254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1419254885Sdumbbell if (r) { 1420254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1421254885Sdumbbell "0x%04X\n", reg); 1422254885Sdumbbell return -EINVAL; 1423254885Sdumbbell } 1424254885Sdumbbell track->db_offset = radeon_get_ib_value(p, idx) << 8; 1425254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1426254885Sdumbbell track->db_bo = reloc->robj; 1427254885Sdumbbell track->db_bo_mc = reloc->lobj.gpu_offset; 1428254885Sdumbbell track->db_dirty = true; 1429254885Sdumbbell break; 1430254885Sdumbbell case DB_HTILE_DATA_BASE: 1431254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1432254885Sdumbbell if (r) { 1433254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1434254885Sdumbbell "0x%04X\n", reg); 1435254885Sdumbbell return -EINVAL; 1436254885Sdumbbell } 1437254885Sdumbbell track->htile_offset = radeon_get_ib_value(p, idx) << 8; 1438254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1439254885Sdumbbell track->htile_bo = reloc->robj; 1440254885Sdumbbell track->db_dirty = true; 1441254885Sdumbbell break; 1442254885Sdumbbell case DB_HTILE_SURFACE: 1443254885Sdumbbell track->htile_surface = radeon_get_ib_value(p, idx); 1444254885Sdumbbell /* force 8x8 htile width and height */ 1445254885Sdumbbell ib[idx] |= 3; 1446254885Sdumbbell track->db_dirty = true; 1447254885Sdumbbell break; 1448254885Sdumbbell case SQ_PGM_START_FS: 1449254885Sdumbbell case SQ_PGM_START_ES: 1450254885Sdumbbell case SQ_PGM_START_VS: 1451254885Sdumbbell case SQ_PGM_START_GS: 1452254885Sdumbbell case SQ_PGM_START_PS: 1453254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_0: 1454254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_1: 1455254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_2: 1456254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_3: 1457254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_4: 1458254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_5: 1459254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_6: 1460254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_7: 1461254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_8: 1462254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_9: 1463254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_10: 1464254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_11: 1465254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_12: 1466254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_13: 1467254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_14: 1468254885Sdumbbell case SQ_ALU_CONST_CACHE_GS_15: 1469254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_0: 1470254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_1: 1471254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_2: 1472254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_3: 1473254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_4: 1474254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_5: 1475254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_6: 1476254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_7: 1477254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_8: 1478254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_9: 1479254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_10: 1480254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_11: 1481254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_12: 1482254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_13: 1483254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_14: 1484254885Sdumbbell case SQ_ALU_CONST_CACHE_PS_15: 1485254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_0: 1486254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_1: 1487254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_2: 1488254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_3: 1489254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_4: 1490254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_5: 1491254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_6: 1492254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_7: 1493254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_8: 1494254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_9: 1495254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_10: 1496254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_11: 1497254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_12: 1498254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_13: 1499254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_14: 1500254885Sdumbbell case SQ_ALU_CONST_CACHE_VS_15: 1501254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1502254885Sdumbbell if (r) { 1503254885Sdumbbell dev_warn(p->dev, "bad SET_CONTEXT_REG " 1504254885Sdumbbell "0x%04X\n", reg); 1505254885Sdumbbell return -EINVAL; 1506254885Sdumbbell } 1507254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1508254885Sdumbbell break; 1509254885Sdumbbell case SX_MEMORY_EXPORT_BASE: 1510254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1511254885Sdumbbell if (r) { 1512254885Sdumbbell dev_warn(p->dev, "bad SET_CONFIG_REG " 1513254885Sdumbbell "0x%04X\n", reg); 1514254885Sdumbbell return -EINVAL; 1515254885Sdumbbell } 1516254885Sdumbbell ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1517254885Sdumbbell break; 1518254885Sdumbbell case SX_MISC: 1519254885Sdumbbell track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1520254885Sdumbbell break; 1521254885Sdumbbell default: 1522254885Sdumbbell dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1523254885Sdumbbell return -EINVAL; 1524254885Sdumbbell } 1525254885Sdumbbell return 0; 1526254885Sdumbbell} 1527254885Sdumbbell 1528254885Sdumbbellunsigned r600_mip_minify(unsigned size, unsigned level) 1529254885Sdumbbell{ 1530254885Sdumbbell unsigned val; 1531254885Sdumbbell 1532254885Sdumbbell val = max(1U, size >> level); 1533254885Sdumbbell if (level > 0) 1534254885Sdumbbell val = roundup_pow_of_two(val); 1535254885Sdumbbell return val; 1536254885Sdumbbell} 1537254885Sdumbbell 1538254885Sdumbbellstatic void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, 1539254885Sdumbbell unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format, 1540254885Sdumbbell unsigned block_align, unsigned height_align, unsigned base_align, 1541254885Sdumbbell unsigned *l0_size, unsigned *mipmap_size) 1542254885Sdumbbell{ 1543254885Sdumbbell unsigned offset, i, level; 1544254885Sdumbbell unsigned width, height, depth, size; 1545254885Sdumbbell unsigned blocksize; 1546254885Sdumbbell unsigned nbx, nby; 1547254885Sdumbbell unsigned nlevels = llevel - blevel + 1; 1548254885Sdumbbell 1549254885Sdumbbell *l0_size = -1; 1550254885Sdumbbell blocksize = r600_fmt_get_blocksize(format); 1551254885Sdumbbell 1552254885Sdumbbell w0 = r600_mip_minify(w0, 0); 1553254885Sdumbbell h0 = r600_mip_minify(h0, 0); 1554254885Sdumbbell d0 = r600_mip_minify(d0, 0); 1555254885Sdumbbell for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { 1556254885Sdumbbell width = r600_mip_minify(w0, i); 1557254885Sdumbbell nbx = r600_fmt_get_nblocksx(format, width); 1558254885Sdumbbell 1559254885Sdumbbell nbx = roundup(nbx, block_align); 1560254885Sdumbbell 1561254885Sdumbbell height = r600_mip_minify(h0, i); 1562254885Sdumbbell nby = r600_fmt_get_nblocksy(format, height); 1563254885Sdumbbell nby = roundup(nby, height_align); 1564254885Sdumbbell 1565254885Sdumbbell depth = r600_mip_minify(d0, i); 1566254885Sdumbbell 1567254885Sdumbbell size = nbx * nby * blocksize * nsamples; 1568254885Sdumbbell if (nfaces) 1569254885Sdumbbell size *= nfaces; 1570254885Sdumbbell else 1571254885Sdumbbell size *= depth; 1572254885Sdumbbell 1573254885Sdumbbell if (i == 0) 1574254885Sdumbbell *l0_size = size; 1575254885Sdumbbell 1576254885Sdumbbell if (i == 0 || i == 1) 1577254885Sdumbbell offset = roundup(offset, base_align); 1578254885Sdumbbell 1579254885Sdumbbell offset += size; 1580254885Sdumbbell } 1581254885Sdumbbell *mipmap_size = offset; 1582254885Sdumbbell if (llevel == 0) 1583254885Sdumbbell *mipmap_size = *l0_size; 1584254885Sdumbbell if (!blevel) 1585254885Sdumbbell *mipmap_size -= *l0_size; 1586254885Sdumbbell} 1587254885Sdumbbell 1588254885Sdumbbell/** 1589254885Sdumbbell * r600_check_texture_resource() - check if register is authorized or not 1590254885Sdumbbell * @p: parser structure holding parsing context 1591254885Sdumbbell * @idx: index into the cs buffer 1592254885Sdumbbell * @texture: texture's bo structure 1593254885Sdumbbell * @mipmap: mipmap's bo structure 1594254885Sdumbbell * 1595254885Sdumbbell * This function will check that the resource has valid field and that 1596254885Sdumbbell * the texture and mipmap bo object are big enough to cover this resource. 1597254885Sdumbbell */ 1598254885Sdumbbellstatic int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, 1599254885Sdumbbell struct radeon_bo *texture, 1600254885Sdumbbell struct radeon_bo *mipmap, 1601254885Sdumbbell u64 base_offset, 1602254885Sdumbbell u64 mip_offset, 1603254885Sdumbbell u32 tiling_flags) 1604254885Sdumbbell{ 1605254885Sdumbbell struct r600_cs_track *track = p->track; 1606254885Sdumbbell u32 dim, nfaces, llevel, blevel, w0, h0, d0; 1607254885Sdumbbell u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5; 1608254885Sdumbbell u32 height_align, pitch, pitch_align, depth_align; 1609254885Sdumbbell u32 barray, larray; 1610254885Sdumbbell u64 base_align; 1611254885Sdumbbell struct array_mode_checker array_check; 1612254885Sdumbbell u32 format; 1613254885Sdumbbell bool is_array; 1614254885Sdumbbell 1615254885Sdumbbell /* on legacy kernel we don't perform advanced check */ 1616254885Sdumbbell if (p->rdev == NULL) 1617254885Sdumbbell return 0; 1618254885Sdumbbell 1619254885Sdumbbell /* convert to bytes */ 1620254885Sdumbbell base_offset <<= 8; 1621254885Sdumbbell mip_offset <<= 8; 1622254885Sdumbbell 1623254885Sdumbbell word0 = radeon_get_ib_value(p, idx + 0); 1624254885Sdumbbell if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1625254885Sdumbbell if (tiling_flags & RADEON_TILING_MACRO) 1626254885Sdumbbell word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1627254885Sdumbbell else if (tiling_flags & RADEON_TILING_MICRO) 1628254885Sdumbbell word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1629254885Sdumbbell } 1630254885Sdumbbell word1 = radeon_get_ib_value(p, idx + 1); 1631254885Sdumbbell word2 = radeon_get_ib_value(p, idx + 2) << 8; 1632254885Sdumbbell word3 = radeon_get_ib_value(p, idx + 3) << 8; 1633254885Sdumbbell word4 = radeon_get_ib_value(p, idx + 4); 1634254885Sdumbbell word5 = radeon_get_ib_value(p, idx + 5); 1635254885Sdumbbell dim = G_038000_DIM(word0); 1636254885Sdumbbell w0 = G_038000_TEX_WIDTH(word0) + 1; 1637254885Sdumbbell pitch = (G_038000_PITCH(word0) + 1) * 8; 1638254885Sdumbbell h0 = G_038004_TEX_HEIGHT(word1) + 1; 1639254885Sdumbbell d0 = G_038004_TEX_DEPTH(word1); 1640254885Sdumbbell format = G_038004_DATA_FORMAT(word1); 1641254885Sdumbbell blevel = G_038010_BASE_LEVEL(word4); 1642254885Sdumbbell llevel = G_038014_LAST_LEVEL(word5); 1643254885Sdumbbell /* pitch in texels */ 1644254885Sdumbbell array_check.array_mode = G_038000_TILE_MODE(word0); 1645254885Sdumbbell array_check.group_size = track->group_size; 1646254885Sdumbbell array_check.nbanks = track->nbanks; 1647254885Sdumbbell array_check.npipes = track->npipes; 1648254885Sdumbbell array_check.nsamples = 1; 1649254885Sdumbbell array_check.blocksize = r600_fmt_get_blocksize(format); 1650254885Sdumbbell nfaces = 1; 1651254885Sdumbbell is_array = false; 1652254885Sdumbbell switch (dim) { 1653254885Sdumbbell case V_038000_SQ_TEX_DIM_1D: 1654254885Sdumbbell case V_038000_SQ_TEX_DIM_2D: 1655254885Sdumbbell case V_038000_SQ_TEX_DIM_3D: 1656254885Sdumbbell break; 1657254885Sdumbbell case V_038000_SQ_TEX_DIM_CUBEMAP: 1658254885Sdumbbell if (p->family >= CHIP_RV770) 1659254885Sdumbbell nfaces = 8; 1660254885Sdumbbell else 1661254885Sdumbbell nfaces = 6; 1662254885Sdumbbell break; 1663254885Sdumbbell case V_038000_SQ_TEX_DIM_1D_ARRAY: 1664254885Sdumbbell case V_038000_SQ_TEX_DIM_2D_ARRAY: 1665254885Sdumbbell is_array = true; 1666254885Sdumbbell break; 1667254885Sdumbbell case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: 1668254885Sdumbbell is_array = true; 1669254885Sdumbbell /* fall through */ 1670254885Sdumbbell case V_038000_SQ_TEX_DIM_2D_MSAA: 1671254885Sdumbbell array_check.nsamples = 1 << llevel; 1672254885Sdumbbell llevel = 0; 1673254885Sdumbbell break; 1674254885Sdumbbell default: 1675254885Sdumbbell dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1676254885Sdumbbell return -EINVAL; 1677254885Sdumbbell } 1678254885Sdumbbell if (!r600_fmt_is_valid_texture(format, p->family)) { 1679254885Sdumbbell dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1680254885Sdumbbell __func__, __LINE__, format); 1681254885Sdumbbell return -EINVAL; 1682254885Sdumbbell } 1683254885Sdumbbell 1684254885Sdumbbell if (r600_get_array_mode_alignment(&array_check, 1685254885Sdumbbell &pitch_align, &height_align, &depth_align, &base_align)) { 1686254885Sdumbbell dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", 1687254885Sdumbbell __func__, __LINE__, G_038000_TILE_MODE(word0)); 1688254885Sdumbbell return -EINVAL; 1689254885Sdumbbell } 1690254885Sdumbbell 1691254885Sdumbbell /* XXX check height as well... */ 1692254885Sdumbbell 1693254885Sdumbbell if (!IS_ALIGNED(pitch, pitch_align)) { 1694254885Sdumbbell dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1695254885Sdumbbell __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1696254885Sdumbbell return -EINVAL; 1697254885Sdumbbell } 1698254885Sdumbbell if (!IS_ALIGNED(base_offset, base_align)) { 1699254885Sdumbbell dev_warn(p->dev, "%s:%d tex base offset (0x%jx, 0x%jx, %d) invalid\n", 1700254885Sdumbbell __func__, __LINE__, (uintmax_t)base_offset, (uintmax_t)base_align, G_038000_TILE_MODE(word0)); 1701254885Sdumbbell return -EINVAL; 1702254885Sdumbbell } 1703254885Sdumbbell if (!IS_ALIGNED(mip_offset, base_align)) { 1704254885Sdumbbell dev_warn(p->dev, "%s:%d tex mip offset (0x%jx, 0x%jx, %d) invalid\n", 1705254885Sdumbbell __func__, __LINE__, (uintmax_t)mip_offset, (uintmax_t)base_align, G_038000_TILE_MODE(word0)); 1706254885Sdumbbell return -EINVAL; 1707254885Sdumbbell } 1708254885Sdumbbell 1709254885Sdumbbell if (blevel > llevel) { 1710254885Sdumbbell dev_warn(p->dev, "texture blevel %d > llevel %d\n", 1711254885Sdumbbell blevel, llevel); 1712254885Sdumbbell } 1713254885Sdumbbell if (is_array) { 1714254885Sdumbbell barray = G_038014_BASE_ARRAY(word5); 1715254885Sdumbbell larray = G_038014_LAST_ARRAY(word5); 1716254885Sdumbbell 1717254885Sdumbbell nfaces = larray - barray + 1; 1718254885Sdumbbell } 1719254885Sdumbbell r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format, 1720254885Sdumbbell pitch_align, height_align, base_align, 1721254885Sdumbbell &l0_size, &mipmap_size); 1722254885Sdumbbell /* using get ib will give us the offset into the texture bo */ 1723254885Sdumbbell if ((l0_size + word2) > radeon_bo_size(texture)) { 1724254885Sdumbbell dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", 1725254885Sdumbbell w0, h0, pitch_align, height_align, 1726254885Sdumbbell array_check.array_mode, format, word2, 1727254885Sdumbbell l0_size, radeon_bo_size(texture)); 1728254885Sdumbbell dev_warn(p->dev, "alignments %d %d %d %jd\n", pitch, pitch_align, height_align, (uintmax_t)base_align); 1729254885Sdumbbell return -EINVAL; 1730254885Sdumbbell } 1731254885Sdumbbell /* using get ib will give us the offset into the mipmap bo */ 1732254885Sdumbbell if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { 1733254885Sdumbbell /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1734254885Sdumbbell w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ 1735254885Sdumbbell } 1736254885Sdumbbell return 0; 1737254885Sdumbbell} 1738254885Sdumbbell 1739254885Sdumbbellstatic bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1740254885Sdumbbell{ 1741254885Sdumbbell u32 m, i; 1742254885Sdumbbell 1743254885Sdumbbell i = (reg >> 7); 1744254885Sdumbbell if (i >= DRM_ARRAY_SIZE(r600_reg_safe_bm)) { 1745254885Sdumbbell dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1746254885Sdumbbell return false; 1747254885Sdumbbell } 1748254885Sdumbbell m = 1 << ((reg >> 2) & 31); 1749254885Sdumbbell if (!(r600_reg_safe_bm[i] & m)) 1750254885Sdumbbell return true; 1751254885Sdumbbell dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1752254885Sdumbbell return false; 1753254885Sdumbbell} 1754254885Sdumbbell 1755254885Sdumbbellstatic int r600_packet3_check(struct radeon_cs_parser *p, 1756254885Sdumbbell struct radeon_cs_packet *pkt) 1757254885Sdumbbell{ 1758254885Sdumbbell struct radeon_cs_reloc *reloc; 1759254885Sdumbbell struct r600_cs_track *track; 1760254885Sdumbbell volatile u32 *ib; 1761254885Sdumbbell unsigned idx; 1762254885Sdumbbell unsigned i; 1763254885Sdumbbell unsigned start_reg, end_reg, reg; 1764254885Sdumbbell int r; 1765254885Sdumbbell u32 idx_value; 1766254885Sdumbbell 1767254885Sdumbbell track = (struct r600_cs_track *)p->track; 1768254885Sdumbbell ib = p->ib.ptr; 1769254885Sdumbbell idx = pkt->idx + 1; 1770254885Sdumbbell idx_value = radeon_get_ib_value(p, idx); 1771254885Sdumbbell 1772254885Sdumbbell switch (pkt->opcode) { 1773254885Sdumbbell case PACKET3_SET_PREDICATION: 1774254885Sdumbbell { 1775254885Sdumbbell int pred_op; 1776254885Sdumbbell int tmp; 1777254885Sdumbbell uint64_t offset; 1778254885Sdumbbell 1779254885Sdumbbell if (pkt->count != 1) { 1780254885Sdumbbell DRM_ERROR("bad SET PREDICATION\n"); 1781254885Sdumbbell return -EINVAL; 1782254885Sdumbbell } 1783254885Sdumbbell 1784254885Sdumbbell tmp = radeon_get_ib_value(p, idx + 1); 1785254885Sdumbbell pred_op = (tmp >> 16) & 0x7; 1786254885Sdumbbell 1787254885Sdumbbell /* for the clear predicate operation */ 1788254885Sdumbbell if (pred_op == 0) 1789254885Sdumbbell return 0; 1790254885Sdumbbell 1791254885Sdumbbell if (pred_op > 2) { 1792254885Sdumbbell DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1793254885Sdumbbell return -EINVAL; 1794254885Sdumbbell } 1795254885Sdumbbell 1796254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1797254885Sdumbbell if (r) { 1798254885Sdumbbell DRM_ERROR("bad SET PREDICATION\n"); 1799254885Sdumbbell return -EINVAL; 1800254885Sdumbbell } 1801254885Sdumbbell 1802254885Sdumbbell offset = reloc->lobj.gpu_offset + 1803254885Sdumbbell (idx_value & 0xfffffff0) + 1804254885Sdumbbell ((u64)(tmp & 0xff) << 32); 1805254885Sdumbbell 1806254885Sdumbbell ib[idx + 0] = offset; 1807254885Sdumbbell ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1808254885Sdumbbell } 1809254885Sdumbbell break; 1810254885Sdumbbell 1811254885Sdumbbell case PACKET3_START_3D_CMDBUF: 1812254885Sdumbbell if (p->family >= CHIP_RV770 || pkt->count) { 1813254885Sdumbbell DRM_ERROR("bad START_3D\n"); 1814254885Sdumbbell return -EINVAL; 1815254885Sdumbbell } 1816254885Sdumbbell break; 1817254885Sdumbbell case PACKET3_CONTEXT_CONTROL: 1818254885Sdumbbell if (pkt->count != 1) { 1819254885Sdumbbell DRM_ERROR("bad CONTEXT_CONTROL\n"); 1820254885Sdumbbell return -EINVAL; 1821254885Sdumbbell } 1822254885Sdumbbell break; 1823254885Sdumbbell case PACKET3_INDEX_TYPE: 1824254885Sdumbbell case PACKET3_NUM_INSTANCES: 1825254885Sdumbbell if (pkt->count) { 1826254885Sdumbbell DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); 1827254885Sdumbbell return -EINVAL; 1828254885Sdumbbell } 1829254885Sdumbbell break; 1830254885Sdumbbell case PACKET3_DRAW_INDEX: 1831254885Sdumbbell { 1832254885Sdumbbell uint64_t offset; 1833254885Sdumbbell if (pkt->count != 3) { 1834254885Sdumbbell DRM_ERROR("bad DRAW_INDEX\n"); 1835254885Sdumbbell return -EINVAL; 1836254885Sdumbbell } 1837254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1838254885Sdumbbell if (r) { 1839254885Sdumbbell DRM_ERROR("bad DRAW_INDEX\n"); 1840254885Sdumbbell return -EINVAL; 1841254885Sdumbbell } 1842254885Sdumbbell 1843254885Sdumbbell offset = reloc->lobj.gpu_offset + 1844254885Sdumbbell idx_value + 1845254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1846254885Sdumbbell 1847254885Sdumbbell ib[idx+0] = offset; 1848254885Sdumbbell ib[idx+1] = upper_32_bits(offset) & 0xff; 1849254885Sdumbbell 1850254885Sdumbbell r = r600_cs_track_check(p); 1851254885Sdumbbell if (r) { 1852254885Sdumbbell dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1853254885Sdumbbell return r; 1854254885Sdumbbell } 1855254885Sdumbbell break; 1856254885Sdumbbell } 1857254885Sdumbbell case PACKET3_DRAW_INDEX_AUTO: 1858254885Sdumbbell if (pkt->count != 1) { 1859254885Sdumbbell DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1860254885Sdumbbell return -EINVAL; 1861254885Sdumbbell } 1862254885Sdumbbell r = r600_cs_track_check(p); 1863254885Sdumbbell if (r) { 1864254885Sdumbbell dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1865254885Sdumbbell return r; 1866254885Sdumbbell } 1867254885Sdumbbell break; 1868254885Sdumbbell case PACKET3_DRAW_INDEX_IMMD_BE: 1869254885Sdumbbell case PACKET3_DRAW_INDEX_IMMD: 1870254885Sdumbbell if (pkt->count < 2) { 1871254885Sdumbbell DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1872254885Sdumbbell return -EINVAL; 1873254885Sdumbbell } 1874254885Sdumbbell r = r600_cs_track_check(p); 1875254885Sdumbbell if (r) { 1876254885Sdumbbell dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1877254885Sdumbbell return r; 1878254885Sdumbbell } 1879254885Sdumbbell break; 1880254885Sdumbbell case PACKET3_WAIT_REG_MEM: 1881254885Sdumbbell if (pkt->count != 5) { 1882254885Sdumbbell DRM_ERROR("bad WAIT_REG_MEM\n"); 1883254885Sdumbbell return -EINVAL; 1884254885Sdumbbell } 1885254885Sdumbbell /* bit 4 is reg (0) or mem (1) */ 1886254885Sdumbbell if (idx_value & 0x10) { 1887254885Sdumbbell uint64_t offset; 1888254885Sdumbbell 1889254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1890254885Sdumbbell if (r) { 1891254885Sdumbbell DRM_ERROR("bad WAIT_REG_MEM\n"); 1892254885Sdumbbell return -EINVAL; 1893254885Sdumbbell } 1894254885Sdumbbell 1895254885Sdumbbell offset = reloc->lobj.gpu_offset + 1896254885Sdumbbell (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + 1897254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1898254885Sdumbbell 1899254885Sdumbbell ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); 1900254885Sdumbbell ib[idx+2] = upper_32_bits(offset) & 0xff; 1901254885Sdumbbell } 1902254885Sdumbbell break; 1903254885Sdumbbell case PACKET3_CP_DMA: 1904254885Sdumbbell { 1905254885Sdumbbell u32 command, size; 1906254885Sdumbbell u64 offset, tmp; 1907254885Sdumbbell if (pkt->count != 4) { 1908254885Sdumbbell DRM_ERROR("bad CP DMA\n"); 1909254885Sdumbbell return -EINVAL; 1910254885Sdumbbell } 1911254885Sdumbbell command = radeon_get_ib_value(p, idx+4); 1912254885Sdumbbell size = command & 0x1fffff; 1913254885Sdumbbell if (command & PACKET3_CP_DMA_CMD_SAS) { 1914254885Sdumbbell /* src address space is register */ 1915254885Sdumbbell DRM_ERROR("CP DMA SAS not supported\n"); 1916254885Sdumbbell return -EINVAL; 1917254885Sdumbbell } else { 1918254885Sdumbbell if (command & PACKET3_CP_DMA_CMD_SAIC) { 1919254885Sdumbbell DRM_ERROR("CP DMA SAIC only supported for registers\n"); 1920254885Sdumbbell return -EINVAL; 1921254885Sdumbbell } 1922254885Sdumbbell /* src address space is memory */ 1923254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1924254885Sdumbbell if (r) { 1925254885Sdumbbell DRM_ERROR("bad CP DMA SRC\n"); 1926254885Sdumbbell return -EINVAL; 1927254885Sdumbbell } 1928254885Sdumbbell 1929254885Sdumbbell tmp = radeon_get_ib_value(p, idx) + 1930254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1931254885Sdumbbell 1932254885Sdumbbell offset = reloc->lobj.gpu_offset + tmp; 1933254885Sdumbbell 1934254885Sdumbbell if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1935254885Sdumbbell dev_warn(p->dev, "CP DMA src buffer too small (%ju %lu)\n", 1936254885Sdumbbell (uintmax_t)tmp + size, radeon_bo_size(reloc->robj)); 1937254885Sdumbbell return -EINVAL; 1938254885Sdumbbell } 1939254885Sdumbbell 1940254885Sdumbbell ib[idx] = offset; 1941254885Sdumbbell ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1942254885Sdumbbell } 1943254885Sdumbbell if (command & PACKET3_CP_DMA_CMD_DAS) { 1944254885Sdumbbell /* dst address space is register */ 1945254885Sdumbbell DRM_ERROR("CP DMA DAS not supported\n"); 1946254885Sdumbbell return -EINVAL; 1947254885Sdumbbell } else { 1948254885Sdumbbell /* dst address space is memory */ 1949254885Sdumbbell if (command & PACKET3_CP_DMA_CMD_DAIC) { 1950254885Sdumbbell DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1951254885Sdumbbell return -EINVAL; 1952254885Sdumbbell } 1953254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1954254885Sdumbbell if (r) { 1955254885Sdumbbell DRM_ERROR("bad CP DMA DST\n"); 1956254885Sdumbbell return -EINVAL; 1957254885Sdumbbell } 1958254885Sdumbbell 1959254885Sdumbbell tmp = radeon_get_ib_value(p, idx+2) + 1960254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 1961254885Sdumbbell 1962254885Sdumbbell offset = reloc->lobj.gpu_offset + tmp; 1963254885Sdumbbell 1964254885Sdumbbell if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1965254885Sdumbbell dev_warn(p->dev, "CP DMA dst buffer too small (%ju %lu)\n", 1966254885Sdumbbell (uintmax_t)tmp + size, radeon_bo_size(reloc->robj)); 1967254885Sdumbbell return -EINVAL; 1968254885Sdumbbell } 1969254885Sdumbbell 1970254885Sdumbbell ib[idx+2] = offset; 1971254885Sdumbbell ib[idx+3] = upper_32_bits(offset) & 0xff; 1972254885Sdumbbell } 1973254885Sdumbbell break; 1974254885Sdumbbell } 1975254885Sdumbbell case PACKET3_SURFACE_SYNC: 1976254885Sdumbbell if (pkt->count != 3) { 1977254885Sdumbbell DRM_ERROR("bad SURFACE_SYNC\n"); 1978254885Sdumbbell return -EINVAL; 1979254885Sdumbbell } 1980254885Sdumbbell /* 0xffffffff/0x0 is flush all cache flag */ 1981254885Sdumbbell if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 1982254885Sdumbbell radeon_get_ib_value(p, idx + 2) != 0) { 1983254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 1984254885Sdumbbell if (r) { 1985254885Sdumbbell DRM_ERROR("bad SURFACE_SYNC\n"); 1986254885Sdumbbell return -EINVAL; 1987254885Sdumbbell } 1988254885Sdumbbell ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1989254885Sdumbbell } 1990254885Sdumbbell break; 1991254885Sdumbbell case PACKET3_EVENT_WRITE: 1992254885Sdumbbell if (pkt->count != 2 && pkt->count != 0) { 1993254885Sdumbbell DRM_ERROR("bad EVENT_WRITE\n"); 1994254885Sdumbbell return -EINVAL; 1995254885Sdumbbell } 1996254885Sdumbbell if (pkt->count) { 1997254885Sdumbbell uint64_t offset; 1998254885Sdumbbell 1999254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2000254885Sdumbbell if (r) { 2001254885Sdumbbell DRM_ERROR("bad EVENT_WRITE\n"); 2002254885Sdumbbell return -EINVAL; 2003254885Sdumbbell } 2004254885Sdumbbell offset = reloc->lobj.gpu_offset + 2005254885Sdumbbell (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 2006254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2007254885Sdumbbell 2008254885Sdumbbell ib[idx+1] = offset & 0xfffffff8; 2009254885Sdumbbell ib[idx+2] = upper_32_bits(offset) & 0xff; 2010254885Sdumbbell } 2011254885Sdumbbell break; 2012254885Sdumbbell case PACKET3_EVENT_WRITE_EOP: 2013254885Sdumbbell { 2014254885Sdumbbell uint64_t offset; 2015254885Sdumbbell 2016254885Sdumbbell if (pkt->count != 4) { 2017254885Sdumbbell DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2018254885Sdumbbell return -EINVAL; 2019254885Sdumbbell } 2020254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2021254885Sdumbbell if (r) { 2022254885Sdumbbell DRM_ERROR("bad EVENT_WRITE\n"); 2023254885Sdumbbell return -EINVAL; 2024254885Sdumbbell } 2025254885Sdumbbell 2026254885Sdumbbell offset = reloc->lobj.gpu_offset + 2027254885Sdumbbell (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2028254885Sdumbbell ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2029254885Sdumbbell 2030254885Sdumbbell ib[idx+1] = offset & 0xfffffffc; 2031254885Sdumbbell ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2032254885Sdumbbell break; 2033254885Sdumbbell } 2034254885Sdumbbell case PACKET3_SET_CONFIG_REG: 2035254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; 2036254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2037254885Sdumbbell if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || 2038254885Sdumbbell (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2039254885Sdumbbell (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2040254885Sdumbbell DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2041254885Sdumbbell return -EINVAL; 2042254885Sdumbbell } 2043254885Sdumbbell for (i = 0; i < pkt->count; i++) { 2044254885Sdumbbell reg = start_reg + (4 * i); 2045254885Sdumbbell r = r600_cs_check_reg(p, reg, idx+1+i); 2046254885Sdumbbell if (r) 2047254885Sdumbbell return r; 2048254885Sdumbbell } 2049254885Sdumbbell break; 2050254885Sdumbbell case PACKET3_SET_CONTEXT_REG: 2051254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; 2052254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2053254885Sdumbbell if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || 2054254885Sdumbbell (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 2055254885Sdumbbell (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 2056254885Sdumbbell DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 2057254885Sdumbbell return -EINVAL; 2058254885Sdumbbell } 2059254885Sdumbbell for (i = 0; i < pkt->count; i++) { 2060254885Sdumbbell reg = start_reg + (4 * i); 2061254885Sdumbbell r = r600_cs_check_reg(p, reg, idx+1+i); 2062254885Sdumbbell if (r) 2063254885Sdumbbell return r; 2064254885Sdumbbell } 2065254885Sdumbbell break; 2066254885Sdumbbell case PACKET3_SET_RESOURCE: 2067254885Sdumbbell if (pkt->count % 7) { 2068254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2069254885Sdumbbell return -EINVAL; 2070254885Sdumbbell } 2071254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; 2072254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2073254885Sdumbbell if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || 2074254885Sdumbbell (start_reg >= PACKET3_SET_RESOURCE_END) || 2075254885Sdumbbell (end_reg >= PACKET3_SET_RESOURCE_END)) { 2076254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2077254885Sdumbbell return -EINVAL; 2078254885Sdumbbell } 2079254885Sdumbbell for (i = 0; i < (pkt->count / 7); i++) { 2080254885Sdumbbell struct radeon_bo *texture, *mipmap; 2081254885Sdumbbell u32 size, offset, base_offset, mip_offset; 2082254885Sdumbbell 2083254885Sdumbbell switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 2084254885Sdumbbell case SQ_TEX_VTX_VALID_TEXTURE: 2085254885Sdumbbell /* tex base */ 2086254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2087254885Sdumbbell if (r) { 2088254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2089254885Sdumbbell return -EINVAL; 2090254885Sdumbbell } 2091254885Sdumbbell base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2092254885Sdumbbell if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 2093254885Sdumbbell if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 2094254885Sdumbbell ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 2095254885Sdumbbell else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 2096254885Sdumbbell ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 2097254885Sdumbbell } 2098254885Sdumbbell texture = reloc->robj; 2099254885Sdumbbell /* tex mip base */ 2100254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2101254885Sdumbbell if (r) { 2102254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2103254885Sdumbbell return -EINVAL; 2104254885Sdumbbell } 2105254885Sdumbbell mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2106254885Sdumbbell mipmap = reloc->robj; 2107254885Sdumbbell r = r600_check_texture_resource(p, idx+(i*7)+1, 2108254885Sdumbbell texture, mipmap, 2109254885Sdumbbell base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), 2110254885Sdumbbell mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), 2111254885Sdumbbell reloc->lobj.tiling_flags); 2112254885Sdumbbell if (r) 2113254885Sdumbbell return r; 2114254885Sdumbbell ib[idx+1+(i*7)+2] += base_offset; 2115254885Sdumbbell ib[idx+1+(i*7)+3] += mip_offset; 2116254885Sdumbbell break; 2117254885Sdumbbell case SQ_TEX_VTX_VALID_BUFFER: 2118254885Sdumbbell { 2119254885Sdumbbell uint64_t offset64; 2120254885Sdumbbell /* vtx base */ 2121254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2122254885Sdumbbell if (r) { 2123254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2124254885Sdumbbell return -EINVAL; 2125254885Sdumbbell } 2126254885Sdumbbell offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 2127254885Sdumbbell size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; 2128254885Sdumbbell if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2129254885Sdumbbell /* force size to size of the buffer */ 2130254885Sdumbbell dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2131254885Sdumbbell size + offset, radeon_bo_size(reloc->robj)); 2132254885Sdumbbell ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; 2133254885Sdumbbell } 2134254885Sdumbbell 2135254885Sdumbbell offset64 = reloc->lobj.gpu_offset + offset; 2136254885Sdumbbell ib[idx+1+(i*8)+0] = offset64; 2137254885Sdumbbell ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2138254885Sdumbbell (upper_32_bits(offset64) & 0xff); 2139254885Sdumbbell break; 2140254885Sdumbbell } 2141254885Sdumbbell case SQ_TEX_VTX_INVALID_TEXTURE: 2142254885Sdumbbell case SQ_TEX_VTX_INVALID_BUFFER: 2143254885Sdumbbell default: 2144254885Sdumbbell DRM_ERROR("bad SET_RESOURCE\n"); 2145254885Sdumbbell return -EINVAL; 2146254885Sdumbbell } 2147254885Sdumbbell } 2148254885Sdumbbell break; 2149254885Sdumbbell case PACKET3_SET_ALU_CONST: 2150254885Sdumbbell if (track->sq_config & DX9_CONSTS) { 2151254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; 2152254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2153254885Sdumbbell if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || 2154254885Sdumbbell (start_reg >= PACKET3_SET_ALU_CONST_END) || 2155254885Sdumbbell (end_reg >= PACKET3_SET_ALU_CONST_END)) { 2156254885Sdumbbell DRM_ERROR("bad SET_ALU_CONST\n"); 2157254885Sdumbbell return -EINVAL; 2158254885Sdumbbell } 2159254885Sdumbbell } 2160254885Sdumbbell break; 2161254885Sdumbbell case PACKET3_SET_BOOL_CONST: 2162254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; 2163254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2164254885Sdumbbell if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || 2165254885Sdumbbell (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2166254885Sdumbbell (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2167254885Sdumbbell DRM_ERROR("bad SET_BOOL_CONST\n"); 2168254885Sdumbbell return -EINVAL; 2169254885Sdumbbell } 2170254885Sdumbbell break; 2171254885Sdumbbell case PACKET3_SET_LOOP_CONST: 2172254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; 2173254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2174254885Sdumbbell if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || 2175254885Sdumbbell (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2176254885Sdumbbell (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2177254885Sdumbbell DRM_ERROR("bad SET_LOOP_CONST\n"); 2178254885Sdumbbell return -EINVAL; 2179254885Sdumbbell } 2180254885Sdumbbell break; 2181254885Sdumbbell case PACKET3_SET_CTL_CONST: 2182254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; 2183254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2184254885Sdumbbell if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || 2185254885Sdumbbell (start_reg >= PACKET3_SET_CTL_CONST_END) || 2186254885Sdumbbell (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2187254885Sdumbbell DRM_ERROR("bad SET_CTL_CONST\n"); 2188254885Sdumbbell return -EINVAL; 2189254885Sdumbbell } 2190254885Sdumbbell break; 2191254885Sdumbbell case PACKET3_SET_SAMPLER: 2192254885Sdumbbell if (pkt->count % 3) { 2193254885Sdumbbell DRM_ERROR("bad SET_SAMPLER\n"); 2194254885Sdumbbell return -EINVAL; 2195254885Sdumbbell } 2196254885Sdumbbell start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; 2197254885Sdumbbell end_reg = 4 * pkt->count + start_reg - 4; 2198254885Sdumbbell if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || 2199254885Sdumbbell (start_reg >= PACKET3_SET_SAMPLER_END) || 2200254885Sdumbbell (end_reg >= PACKET3_SET_SAMPLER_END)) { 2201254885Sdumbbell DRM_ERROR("bad SET_SAMPLER\n"); 2202254885Sdumbbell return -EINVAL; 2203254885Sdumbbell } 2204254885Sdumbbell break; 2205254885Sdumbbell case PACKET3_STRMOUT_BASE_UPDATE: 2206254885Sdumbbell /* RS780 and RS880 also need this */ 2207254885Sdumbbell if (p->family < CHIP_RS780) { 2208254885Sdumbbell DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n"); 2209254885Sdumbbell return -EINVAL; 2210254885Sdumbbell } 2211254885Sdumbbell if (pkt->count != 1) { 2212254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n"); 2213254885Sdumbbell return -EINVAL; 2214254885Sdumbbell } 2215254885Sdumbbell if (idx_value > 3) { 2216254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n"); 2217254885Sdumbbell return -EINVAL; 2218254885Sdumbbell } 2219254885Sdumbbell { 2220254885Sdumbbell u64 offset; 2221254885Sdumbbell 2222254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2223254885Sdumbbell if (r) { 2224254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2225254885Sdumbbell return -EINVAL; 2226254885Sdumbbell } 2227254885Sdumbbell 2228254885Sdumbbell if (reloc->robj != track->vgt_strmout_bo[idx_value]) { 2229254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n"); 2230254885Sdumbbell return -EINVAL; 2231254885Sdumbbell } 2232254885Sdumbbell 2233254885Sdumbbell offset = radeon_get_ib_value(p, idx+1) << 8; 2234254885Sdumbbell if (offset != track->vgt_strmout_bo_offset[idx_value]) { 2235254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%jx, 0x%x\n", 2236254885Sdumbbell (uintmax_t)offset, track->vgt_strmout_bo_offset[idx_value]); 2237254885Sdumbbell return -EINVAL; 2238254885Sdumbbell } 2239254885Sdumbbell 2240254885Sdumbbell if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2241254885Sdumbbell DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%jx, 0x%lx\n", 2242254885Sdumbbell (uintmax_t)offset + 4, radeon_bo_size(reloc->robj)); 2243254885Sdumbbell return -EINVAL; 2244254885Sdumbbell } 2245254885Sdumbbell ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2246254885Sdumbbell } 2247254885Sdumbbell break; 2248254885Sdumbbell case PACKET3_SURFACE_BASE_UPDATE: 2249254885Sdumbbell if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { 2250254885Sdumbbell DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2251254885Sdumbbell return -EINVAL; 2252254885Sdumbbell } 2253254885Sdumbbell if (pkt->count) { 2254254885Sdumbbell DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2255254885Sdumbbell return -EINVAL; 2256254885Sdumbbell } 2257254885Sdumbbell break; 2258254885Sdumbbell case PACKET3_STRMOUT_BUFFER_UPDATE: 2259254885Sdumbbell if (pkt->count != 4) { 2260254885Sdumbbell DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2261254885Sdumbbell return -EINVAL; 2262254885Sdumbbell } 2263254885Sdumbbell /* Updating memory at DST_ADDRESS. */ 2264254885Sdumbbell if (idx_value & 0x1) { 2265254885Sdumbbell u64 offset; 2266254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2267254885Sdumbbell if (r) { 2268254885Sdumbbell DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2269254885Sdumbbell return -EINVAL; 2270254885Sdumbbell } 2271254885Sdumbbell offset = radeon_get_ib_value(p, idx+1); 2272254885Sdumbbell offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2273254885Sdumbbell if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2274254885Sdumbbell DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%jx, 0x%lx\n", 2275254885Sdumbbell (uintmax_t)offset + 4, radeon_bo_size(reloc->robj)); 2276254885Sdumbbell return -EINVAL; 2277254885Sdumbbell } 2278254885Sdumbbell offset += reloc->lobj.gpu_offset; 2279254885Sdumbbell ib[idx+1] = offset; 2280254885Sdumbbell ib[idx+2] = upper_32_bits(offset) & 0xff; 2281254885Sdumbbell } 2282254885Sdumbbell /* Reading data from SRC_ADDRESS. */ 2283254885Sdumbbell if (((idx_value >> 1) & 0x3) == 2) { 2284254885Sdumbbell u64 offset; 2285254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2286254885Sdumbbell if (r) { 2287254885Sdumbbell DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2288254885Sdumbbell return -EINVAL; 2289254885Sdumbbell } 2290254885Sdumbbell offset = radeon_get_ib_value(p, idx+3); 2291254885Sdumbbell offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2292254885Sdumbbell if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2293254885Sdumbbell DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%jx, 0x%lx\n", 2294254885Sdumbbell (uintmax_t)offset + 4, radeon_bo_size(reloc->robj)); 2295254885Sdumbbell return -EINVAL; 2296254885Sdumbbell } 2297254885Sdumbbell offset += reloc->lobj.gpu_offset; 2298254885Sdumbbell ib[idx+3] = offset; 2299254885Sdumbbell ib[idx+4] = upper_32_bits(offset) & 0xff; 2300254885Sdumbbell } 2301254885Sdumbbell break; 2302254885Sdumbbell case PACKET3_MEM_WRITE: 2303254885Sdumbbell { 2304254885Sdumbbell u64 offset; 2305254885Sdumbbell 2306254885Sdumbbell if (pkt->count != 3) { 2307254885Sdumbbell DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2308254885Sdumbbell return -EINVAL; 2309254885Sdumbbell } 2310254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2311254885Sdumbbell if (r) { 2312254885Sdumbbell DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2313254885Sdumbbell return -EINVAL; 2314254885Sdumbbell } 2315254885Sdumbbell offset = radeon_get_ib_value(p, idx+0); 2316254885Sdumbbell offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2317254885Sdumbbell if (offset & 0x7) { 2318254885Sdumbbell DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2319254885Sdumbbell return -EINVAL; 2320254885Sdumbbell } 2321254885Sdumbbell if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2322254885Sdumbbell DRM_ERROR("bad MEM_WRITE bo too small: 0x%jx, 0x%lx\n", 2323254885Sdumbbell (uintmax_t)offset + 8, radeon_bo_size(reloc->robj)); 2324254885Sdumbbell return -EINVAL; 2325254885Sdumbbell } 2326254885Sdumbbell offset += reloc->lobj.gpu_offset; 2327254885Sdumbbell ib[idx+0] = offset; 2328254885Sdumbbell ib[idx+1] = upper_32_bits(offset) & 0xff; 2329254885Sdumbbell break; 2330254885Sdumbbell } 2331254885Sdumbbell case PACKET3_COPY_DW: 2332254885Sdumbbell if (pkt->count != 4) { 2333254885Sdumbbell DRM_ERROR("bad COPY_DW (invalid count)\n"); 2334254885Sdumbbell return -EINVAL; 2335254885Sdumbbell } 2336254885Sdumbbell if (idx_value & 0x1) { 2337254885Sdumbbell u64 offset; 2338254885Sdumbbell /* SRC is memory. */ 2339254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2340254885Sdumbbell if (r) { 2341254885Sdumbbell DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2342254885Sdumbbell return -EINVAL; 2343254885Sdumbbell } 2344254885Sdumbbell offset = radeon_get_ib_value(p, idx+1); 2345254885Sdumbbell offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2346254885Sdumbbell if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2347254885Sdumbbell DRM_ERROR("bad COPY_DW src bo too small: 0x%jx, 0x%lx\n", 2348254885Sdumbbell (uintmax_t)offset + 4, radeon_bo_size(reloc->robj)); 2349254885Sdumbbell return -EINVAL; 2350254885Sdumbbell } 2351254885Sdumbbell offset += reloc->lobj.gpu_offset; 2352254885Sdumbbell ib[idx+1] = offset; 2353254885Sdumbbell ib[idx+2] = upper_32_bits(offset) & 0xff; 2354254885Sdumbbell } else { 2355254885Sdumbbell /* SRC is a reg. */ 2356254885Sdumbbell reg = radeon_get_ib_value(p, idx+1) << 2; 2357254885Sdumbbell if (!r600_is_safe_reg(p, reg, idx+1)) 2358254885Sdumbbell return -EINVAL; 2359254885Sdumbbell } 2360254885Sdumbbell if (idx_value & 0x2) { 2361254885Sdumbbell u64 offset; 2362254885Sdumbbell /* DST is memory. */ 2363254885Sdumbbell r = r600_cs_packet_next_reloc(p, &reloc); 2364254885Sdumbbell if (r) { 2365254885Sdumbbell DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2366254885Sdumbbell return -EINVAL; 2367254885Sdumbbell } 2368254885Sdumbbell offset = radeon_get_ib_value(p, idx+3); 2369254885Sdumbbell offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2370254885Sdumbbell if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2371254885Sdumbbell DRM_ERROR("bad COPY_DW dst bo too small: 0x%jx, 0x%lx\n", 2372254885Sdumbbell (uintmax_t)offset + 4, radeon_bo_size(reloc->robj)); 2373254885Sdumbbell return -EINVAL; 2374254885Sdumbbell } 2375254885Sdumbbell offset += reloc->lobj.gpu_offset; 2376254885Sdumbbell ib[idx+3] = offset; 2377254885Sdumbbell ib[idx+4] = upper_32_bits(offset) & 0xff; 2378254885Sdumbbell } else { 2379254885Sdumbbell /* DST is a reg. */ 2380254885Sdumbbell reg = radeon_get_ib_value(p, idx+3) << 2; 2381254885Sdumbbell if (!r600_is_safe_reg(p, reg, idx+3)) 2382254885Sdumbbell return -EINVAL; 2383254885Sdumbbell } 2384254885Sdumbbell break; 2385254885Sdumbbell case PACKET3_NOP: 2386254885Sdumbbell break; 2387254885Sdumbbell default: 2388254885Sdumbbell DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2389254885Sdumbbell return -EINVAL; 2390254885Sdumbbell } 2391254885Sdumbbell return 0; 2392254885Sdumbbell} 2393254885Sdumbbell 2394254885Sdumbbellint r600_cs_parse(struct radeon_cs_parser *p) 2395254885Sdumbbell{ 2396254885Sdumbbell struct radeon_cs_packet pkt; 2397254885Sdumbbell struct r600_cs_track *track; 2398254885Sdumbbell int r; 2399254885Sdumbbell 2400254885Sdumbbell if (p->track == NULL) { 2401254885Sdumbbell /* initialize tracker, we are in kms */ 2402254885Sdumbbell track = malloc(sizeof(*track), 2403254885Sdumbbell DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2404254885Sdumbbell if (track == NULL) 2405254885Sdumbbell return -ENOMEM; 2406254885Sdumbbell r600_cs_track_init(track); 2407254885Sdumbbell if (p->rdev->family < CHIP_RV770) { 2408254885Sdumbbell track->npipes = p->rdev->config.r600.tiling_npipes; 2409254885Sdumbbell track->nbanks = p->rdev->config.r600.tiling_nbanks; 2410254885Sdumbbell track->group_size = p->rdev->config.r600.tiling_group_size; 2411254885Sdumbbell } else if (p->rdev->family <= CHIP_RV740) { 2412254885Sdumbbell track->npipes = p->rdev->config.rv770.tiling_npipes; 2413254885Sdumbbell track->nbanks = p->rdev->config.rv770.tiling_nbanks; 2414254885Sdumbbell track->group_size = p->rdev->config.rv770.tiling_group_size; 2415254885Sdumbbell } 2416254885Sdumbbell p->track = track; 2417254885Sdumbbell } 2418254885Sdumbbell do { 2419254885Sdumbbell r = r600_cs_packet_parse(p, &pkt, p->idx); 2420254885Sdumbbell if (r) { 2421254885Sdumbbell free(p->track, DRM_MEM_DRIVER); 2422254885Sdumbbell p->track = NULL; 2423254885Sdumbbell return r; 2424254885Sdumbbell } 2425254885Sdumbbell p->idx += pkt.count + 2; 2426254885Sdumbbell switch (pkt.type) { 2427254885Sdumbbell case PACKET_TYPE0: 2428254885Sdumbbell r = r600_cs_parse_packet0(p, &pkt); 2429254885Sdumbbell break; 2430254885Sdumbbell case PACKET_TYPE2: 2431254885Sdumbbell break; 2432254885Sdumbbell case PACKET_TYPE3: 2433254885Sdumbbell r = r600_packet3_check(p, &pkt); 2434254885Sdumbbell break; 2435254885Sdumbbell default: 2436254885Sdumbbell DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2437254885Sdumbbell free(p->track, DRM_MEM_DRIVER); 2438254885Sdumbbell p->track = NULL; 2439254885Sdumbbell return -EINVAL; 2440254885Sdumbbell } 2441254885Sdumbbell if (r) { 2442254885Sdumbbell free(p->track, DRM_MEM_DRIVER); 2443254885Sdumbbell p->track = NULL; 2444254885Sdumbbell return r; 2445254885Sdumbbell } 2446254885Sdumbbell } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2447254885Sdumbbell#if 0 2448254885Sdumbbell for (r = 0; r < p->ib.length_dw; r++) { 2449254885Sdumbbell DRM_INFO("%05d 0x%08X\n", r, p->ib.ptr[r]); 2450254885Sdumbbell DRM_MDELAY(1); 2451254885Sdumbbell } 2452254885Sdumbbell#endif 2453254885Sdumbbell free(p->track, DRM_MEM_DRIVER); 2454254885Sdumbbell p->track = NULL; 2455254885Sdumbbell return 0; 2456254885Sdumbbell} 2457254885Sdumbbell 2458254885Sdumbbellstatic int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) 2459254885Sdumbbell{ 2460254885Sdumbbell if (p->chunk_relocs_idx == -1) { 2461254885Sdumbbell return 0; 2462254885Sdumbbell } 2463254885Sdumbbell p->relocs = malloc(sizeof(struct radeon_cs_reloc), 2464254885Sdumbbell DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2465254885Sdumbbell if (p->relocs == NULL) { 2466254885Sdumbbell return -ENOMEM; 2467254885Sdumbbell } 2468254885Sdumbbell return 0; 2469254885Sdumbbell} 2470254885Sdumbbell 2471254885Sdumbbell/** 2472254885Sdumbbell * cs_parser_fini() - clean parser states 2473254885Sdumbbell * @parser: parser structure holding parsing context. 2474254885Sdumbbell * @error: error number 2475254885Sdumbbell * 2476254885Sdumbbell * If error is set than unvalidate buffer, otherwise just free memory 2477254885Sdumbbell * used by parsing context. 2478254885Sdumbbell **/ 2479254885Sdumbbellstatic void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) 2480254885Sdumbbell{ 2481254885Sdumbbell unsigned i; 2482254885Sdumbbell 2483254885Sdumbbell free(parser->relocs, DRM_MEM_DRIVER); 2484254885Sdumbbell for (i = 0; i < parser->nchunks; i++) { 2485254885Sdumbbell free(parser->chunks[i].kdata, DRM_MEM_DRIVER); 2486254885Sdumbbell if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) { 2487254885Sdumbbell free(parser->chunks[i].kpage[0], DRM_MEM_DRIVER); 2488254885Sdumbbell free(parser->chunks[i].kpage[1], DRM_MEM_DRIVER); 2489254885Sdumbbell } 2490254885Sdumbbell } 2491254885Sdumbbell free(parser->chunks, DRM_MEM_DRIVER); 2492254885Sdumbbell free(parser->chunks_array, DRM_MEM_DRIVER); 2493254885Sdumbbell free(parser->track, DRM_MEM_DRIVER); 2494254885Sdumbbell} 2495254885Sdumbbell 2496254885Sdumbbellint r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 2497254885Sdumbbell unsigned family, u32 *ib, int *l) 2498254885Sdumbbell{ 2499254885Sdumbbell struct radeon_cs_parser parser; 2500254885Sdumbbell struct radeon_cs_chunk *ib_chunk; 2501254885Sdumbbell struct r600_cs_track *track; 2502254885Sdumbbell int r; 2503254885Sdumbbell 2504254885Sdumbbell /* initialize tracker */ 2505254885Sdumbbell track = malloc(sizeof(*track), DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2506254885Sdumbbell if (track == NULL) 2507254885Sdumbbell return -ENOMEM; 2508254885Sdumbbell r600_cs_track_init(track); 2509254885Sdumbbell r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size); 2510254885Sdumbbell /* initialize parser */ 2511254885Sdumbbell memset(&parser, 0, sizeof(struct radeon_cs_parser)); 2512254885Sdumbbell parser.filp = filp; 2513254885Sdumbbell parser.dev = dev->device; 2514254885Sdumbbell parser.rdev = NULL; 2515254885Sdumbbell parser.family = family; 2516254885Sdumbbell parser.track = track; 2517254885Sdumbbell parser.ib.ptr = ib; 2518254885Sdumbbell r = radeon_cs_parser_init(&parser, data); 2519254885Sdumbbell if (r) { 2520254885Sdumbbell DRM_ERROR("Failed to initialize parser !\n"); 2521254885Sdumbbell r600_cs_parser_fini(&parser, r); 2522254885Sdumbbell return r; 2523254885Sdumbbell } 2524254885Sdumbbell r = r600_cs_parser_relocs_legacy(&parser); 2525254885Sdumbbell if (r) { 2526254885Sdumbbell DRM_ERROR("Failed to parse relocation !\n"); 2527254885Sdumbbell r600_cs_parser_fini(&parser, r); 2528254885Sdumbbell return r; 2529254885Sdumbbell } 2530254885Sdumbbell /* Copy the packet into the IB, the parser will read from the 2531254885Sdumbbell * input memory (cached) and write to the IB (which can be 2532254885Sdumbbell * uncached). */ 2533254885Sdumbbell ib_chunk = &parser.chunks[parser.chunk_ib_idx]; 2534254885Sdumbbell parser.ib.length_dw = ib_chunk->length_dw; 2535254885Sdumbbell *l = parser.ib.length_dw; 2536254885Sdumbbell r = r600_cs_parse(&parser); 2537254885Sdumbbell if (r) { 2538254885Sdumbbell DRM_ERROR("Invalid command stream !\n"); 2539254885Sdumbbell r600_cs_parser_fini(&parser, r); 2540254885Sdumbbell return r; 2541254885Sdumbbell } 2542254885Sdumbbell r = radeon_cs_finish_pages(&parser); 2543254885Sdumbbell if (r) { 2544254885Sdumbbell DRM_ERROR("Invalid command stream !\n"); 2545254885Sdumbbell r600_cs_parser_fini(&parser, r); 2546254885Sdumbbell return r; 2547254885Sdumbbell } 2548254885Sdumbbell r600_cs_parser_fini(&parser, r); 2549254885Sdumbbell return r; 2550254885Sdumbbell} 2551254885Sdumbbell 2552254885Sdumbbellvoid r600_cs_legacy_init(void) 2553254885Sdumbbell{ 2554254885Sdumbbell r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; 2555254885Sdumbbell} 2556254885Sdumbbell 2557254885Sdumbbell/* 2558254885Sdumbbell * DMA 2559254885Sdumbbell */ 2560254885Sdumbbell/** 2561254885Sdumbbell * r600_dma_cs_next_reloc() - parse next reloc 2562254885Sdumbbell * @p: parser structure holding parsing context. 2563254885Sdumbbell * @cs_reloc: reloc informations 2564254885Sdumbbell * 2565254885Sdumbbell * Return the next reloc, do bo validation and compute 2566254885Sdumbbell * GPU offset using the provided start. 2567254885Sdumbbell **/ 2568254885Sdumbbellint r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 2569254885Sdumbbell struct radeon_cs_reloc **cs_reloc) 2570254885Sdumbbell{ 2571254885Sdumbbell struct radeon_cs_chunk *relocs_chunk; 2572254885Sdumbbell unsigned idx; 2573254885Sdumbbell 2574254885Sdumbbell *cs_reloc = NULL; 2575254885Sdumbbell if (p->chunk_relocs_idx == -1) { 2576254885Sdumbbell DRM_ERROR("No relocation chunk !\n"); 2577254885Sdumbbell return -EINVAL; 2578254885Sdumbbell } 2579254885Sdumbbell relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 2580254885Sdumbbell idx = p->dma_reloc_idx; 2581254885Sdumbbell if (idx >= p->nrelocs) { 2582254885Sdumbbell DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 2583254885Sdumbbell idx, p->nrelocs); 2584254885Sdumbbell return -EINVAL; 2585254885Sdumbbell } 2586254885Sdumbbell *cs_reloc = p->relocs_ptr[idx]; 2587254885Sdumbbell p->dma_reloc_idx++; 2588254885Sdumbbell return 0; 2589254885Sdumbbell} 2590254885Sdumbbell 2591254885Sdumbbell#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 2592254885Sdumbbell#define GET_DMA_COUNT(h) ((h) & 0x0000ffff) 2593254885Sdumbbell#define GET_DMA_T(h) (((h) & 0x00800000) >> 23) 2594254885Sdumbbell 2595254885Sdumbbell/** 2596254885Sdumbbell * r600_dma_cs_parse() - parse the DMA IB 2597254885Sdumbbell * @p: parser structure holding parsing context. 2598254885Sdumbbell * 2599254885Sdumbbell * Parses the DMA IB from the CS ioctl and updates 2600254885Sdumbbell * the GPU addresses based on the reloc information and 2601254885Sdumbbell * checks for errors. (R6xx-R7xx) 2602254885Sdumbbell * Returns 0 for success and an error on failure. 2603254885Sdumbbell **/ 2604254885Sdumbbellint r600_dma_cs_parse(struct radeon_cs_parser *p) 2605254885Sdumbbell{ 2606254885Sdumbbell struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 2607254885Sdumbbell struct radeon_cs_reloc *src_reloc, *dst_reloc; 2608254885Sdumbbell u32 header, cmd, count, tiled; 2609254885Sdumbbell volatile u32 *ib = p->ib.ptr; 2610254885Sdumbbell u32 idx, idx_value; 2611254885Sdumbbell u64 src_offset, dst_offset; 2612254885Sdumbbell int r; 2613254885Sdumbbell 2614254885Sdumbbell do { 2615254885Sdumbbell if (p->idx >= ib_chunk->length_dw) { 2616254885Sdumbbell DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2617254885Sdumbbell p->idx, ib_chunk->length_dw); 2618254885Sdumbbell return -EINVAL; 2619254885Sdumbbell } 2620254885Sdumbbell idx = p->idx; 2621254885Sdumbbell header = radeon_get_ib_value(p, idx); 2622254885Sdumbbell cmd = GET_DMA_CMD(header); 2623254885Sdumbbell count = GET_DMA_COUNT(header); 2624254885Sdumbbell tiled = GET_DMA_T(header); 2625254885Sdumbbell 2626254885Sdumbbell switch (cmd) { 2627254885Sdumbbell case DMA_PACKET_WRITE: 2628254885Sdumbbell r = r600_dma_cs_next_reloc(p, &dst_reloc); 2629254885Sdumbbell if (r) { 2630254885Sdumbbell DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2631254885Sdumbbell return -EINVAL; 2632254885Sdumbbell } 2633254885Sdumbbell if (tiled) { 2634254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2635254885Sdumbbell dst_offset <<= 8; 2636254885Sdumbbell 2637254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2638254885Sdumbbell p->idx += count + 5; 2639254885Sdumbbell } else { 2640254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2641254885Sdumbbell dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2642254885Sdumbbell 2643254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2644254885Sdumbbell ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2645254885Sdumbbell p->idx += count + 3; 2646254885Sdumbbell } 2647254885Sdumbbell if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2648254885Sdumbbell dev_warn(p->dev, "DMA write buffer too small (%ju %lu)\n", 2649254885Sdumbbell (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2650254885Sdumbbell return -EINVAL; 2651254885Sdumbbell } 2652254885Sdumbbell break; 2653254885Sdumbbell case DMA_PACKET_COPY: 2654254885Sdumbbell r = r600_dma_cs_next_reloc(p, &src_reloc); 2655254885Sdumbbell if (r) { 2656254885Sdumbbell DRM_ERROR("bad DMA_PACKET_COPY\n"); 2657254885Sdumbbell return -EINVAL; 2658254885Sdumbbell } 2659254885Sdumbbell r = r600_dma_cs_next_reloc(p, &dst_reloc); 2660254885Sdumbbell if (r) { 2661254885Sdumbbell DRM_ERROR("bad DMA_PACKET_COPY\n"); 2662254885Sdumbbell return -EINVAL; 2663254885Sdumbbell } 2664254885Sdumbbell if (tiled) { 2665254885Sdumbbell idx_value = radeon_get_ib_value(p, idx + 2); 2666254885Sdumbbell /* detile bit */ 2667254885Sdumbbell if (idx_value & (1 << 31)) { 2668254885Sdumbbell /* tiled src, linear dst */ 2669254885Sdumbbell src_offset = radeon_get_ib_value(p, idx+1); 2670254885Sdumbbell src_offset <<= 8; 2671254885Sdumbbell ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2672254885Sdumbbell 2673254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+5); 2674254885Sdumbbell dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2675254885Sdumbbell ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2676254885Sdumbbell ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2677254885Sdumbbell } else { 2678254885Sdumbbell /* linear src, tiled dst */ 2679254885Sdumbbell src_offset = radeon_get_ib_value(p, idx+5); 2680254885Sdumbbell src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2681254885Sdumbbell ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2682254885Sdumbbell ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2683254885Sdumbbell 2684254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2685254885Sdumbbell dst_offset <<= 8; 2686254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2687254885Sdumbbell } 2688254885Sdumbbell p->idx += 7; 2689254885Sdumbbell } else { 2690254885Sdumbbell if (p->family >= CHIP_RV770) { 2691254885Sdumbbell src_offset = radeon_get_ib_value(p, idx+2); 2692254885Sdumbbell src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2693254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2694254885Sdumbbell dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2695254885Sdumbbell 2696254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2697254885Sdumbbell ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2698254885Sdumbbell ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2699254885Sdumbbell ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2700254885Sdumbbell p->idx += 5; 2701254885Sdumbbell } else { 2702254885Sdumbbell src_offset = radeon_get_ib_value(p, idx+2); 2703254885Sdumbbell src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2704254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2705254885Sdumbbell dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; 2706254885Sdumbbell 2707254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2708254885Sdumbbell ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2709254885Sdumbbell ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2710254885Sdumbbell ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16; 2711254885Sdumbbell p->idx += 4; 2712254885Sdumbbell } 2713254885Sdumbbell } 2714254885Sdumbbell if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2715254885Sdumbbell dev_warn(p->dev, "DMA copy src buffer too small (%ju %lu)\n", 2716254885Sdumbbell (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2717254885Sdumbbell return -EINVAL; 2718254885Sdumbbell } 2719254885Sdumbbell if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2720254885Sdumbbell dev_warn(p->dev, "DMA write dst buffer too small (%ju %lu)\n", 2721254885Sdumbbell (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2722254885Sdumbbell return -EINVAL; 2723254885Sdumbbell } 2724254885Sdumbbell break; 2725254885Sdumbbell case DMA_PACKET_CONSTANT_FILL: 2726254885Sdumbbell if (p->family < CHIP_RV770) { 2727254885Sdumbbell DRM_ERROR("Constant Fill is 7xx only !\n"); 2728254885Sdumbbell return -EINVAL; 2729254885Sdumbbell } 2730254885Sdumbbell r = r600_dma_cs_next_reloc(p, &dst_reloc); 2731254885Sdumbbell if (r) { 2732254885Sdumbbell DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2733254885Sdumbbell return -EINVAL; 2734254885Sdumbbell } 2735254885Sdumbbell dst_offset = radeon_get_ib_value(p, idx+1); 2736254885Sdumbbell dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 2737254885Sdumbbell if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2738254885Sdumbbell dev_warn(p->dev, "DMA constant fill buffer too small (%ju %lu)\n", 2739254885Sdumbbell (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2740254885Sdumbbell return -EINVAL; 2741254885Sdumbbell } 2742254885Sdumbbell ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2743254885Sdumbbell ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; 2744254885Sdumbbell p->idx += 4; 2745254885Sdumbbell break; 2746254885Sdumbbell case DMA_PACKET_NOP: 2747254885Sdumbbell p->idx += 1; 2748254885Sdumbbell break; 2749254885Sdumbbell default: 2750254885Sdumbbell DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 2751254885Sdumbbell return -EINVAL; 2752254885Sdumbbell } 2753254885Sdumbbell } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2754254885Sdumbbell#if 0 2755254885Sdumbbell for (r = 0; r < p->ib->length_dw; r++) { 2756254885Sdumbbell DRM_INFO("%05d 0x%08X\n", r, p->ib.ptr[r]); 2757254885Sdumbbell DRM_MDELAY(1); 2758254885Sdumbbell } 2759254885Sdumbbell#endif 2760254885Sdumbbell return 0; 2761254885Sdumbbell} 2762