1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2009 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2009 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice (including the next 13254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 14254885Sdumbbell * Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22254885Sdumbbell * DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell */ 25254885Sdumbbell 26254885Sdumbbell#include <sys/cdefs.h> 27254885Sdumbbell__FBSDID("$FreeBSD$"); 28254885Sdumbbell 29254885Sdumbbell#include <dev/drm2/drmP.h> 30254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 31254885Sdumbbell#include "radeon.h" 32254885Sdumbbell#include "radeon_asic.h" 33254885Sdumbbell 34254885Sdumbbell#include "r600d.h" 35254885Sdumbbell#include "r600_blit_shaders.h" 36254885Sdumbbell#include "radeon_blit_common.h" 37254885Sdumbbell 38254885Sdumbbell/* emits 21 on rv770+, 23 on r600 */ 39254885Sdumbbellstatic void 40254885Sdumbbellset_render_target(struct radeon_device *rdev, int format, 41254885Sdumbbell int w, int h, u64 gpu_addr) 42254885Sdumbbell{ 43254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 44254885Sdumbbell u32 cb_color_info; 45254885Sdumbbell int pitch, slice; 46254885Sdumbbell 47254885Sdumbbell h = roundup2(h, 8); 48254885Sdumbbell if (h < 8) 49254885Sdumbbell h = 8; 50254885Sdumbbell 51254885Sdumbbell cb_color_info = CB_FORMAT(format) | 52254885Sdumbbell CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | 53254885Sdumbbell CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); 54254885Sdumbbell pitch = (w / 8) - 1; 55254885Sdumbbell slice = ((w * h) / 64) - 1; 56254885Sdumbbell 57254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 58254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 59254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 60254885Sdumbbell 61254885Sdumbbell if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { 62254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); 63254885Sdumbbell radeon_ring_write(ring, 2 << 0); 64254885Sdumbbell } 65254885Sdumbbell 66254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 67254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 68254885Sdumbbell radeon_ring_write(ring, (pitch << 0) | (slice << 10)); 69254885Sdumbbell 70254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 71254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 72254885Sdumbbell radeon_ring_write(ring, 0); 73254885Sdumbbell 74254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 75254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 76254885Sdumbbell radeon_ring_write(ring, cb_color_info); 77254885Sdumbbell 78254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 79254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 80254885Sdumbbell radeon_ring_write(ring, 0); 81254885Sdumbbell 82254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 83254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 84254885Sdumbbell radeon_ring_write(ring, 0); 85254885Sdumbbell 86254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 87254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 88254885Sdumbbell radeon_ring_write(ring, 0); 89254885Sdumbbell} 90254885Sdumbbell 91254885Sdumbbell/* emits 5dw */ 92254885Sdumbbellstatic void 93254885Sdumbbellcp_set_surface_sync(struct radeon_device *rdev, 94254885Sdumbbell u32 sync_type, u32 size, 95254885Sdumbbell u64 mc_addr) 96254885Sdumbbell{ 97254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 98254885Sdumbbell u32 cp_coher_size; 99254885Sdumbbell 100254885Sdumbbell if (size == 0xffffffff) 101254885Sdumbbell cp_coher_size = 0xffffffff; 102254885Sdumbbell else 103254885Sdumbbell cp_coher_size = ((size + 255) >> 8); 104254885Sdumbbell 105254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 106254885Sdumbbell radeon_ring_write(ring, sync_type); 107254885Sdumbbell radeon_ring_write(ring, cp_coher_size); 108254885Sdumbbell radeon_ring_write(ring, mc_addr >> 8); 109254885Sdumbbell radeon_ring_write(ring, 10); /* poll interval */ 110254885Sdumbbell} 111254885Sdumbbell 112254885Sdumbbell/* emits 21dw + 1 surface sync = 26dw */ 113254885Sdumbbellstatic void 114254885Sdumbbellset_shaders(struct radeon_device *rdev) 115254885Sdumbbell{ 116254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 117254885Sdumbbell u64 gpu_addr; 118254885Sdumbbell u32 sq_pgm_resources; 119254885Sdumbbell 120254885Sdumbbell /* setup shader regs */ 121254885Sdumbbell sq_pgm_resources = (1 << 0); 122254885Sdumbbell 123254885Sdumbbell /* VS */ 124254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 125254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 126254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 127254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 128254885Sdumbbell 129254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 130254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 131254885Sdumbbell radeon_ring_write(ring, sq_pgm_resources); 132254885Sdumbbell 133254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 134254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 135254885Sdumbbell radeon_ring_write(ring, 0); 136254885Sdumbbell 137254885Sdumbbell /* PS */ 138254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; 139254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 140254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 141254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 142254885Sdumbbell 143254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 144254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 145254885Sdumbbell radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); 146254885Sdumbbell 147254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 148254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 149254885Sdumbbell radeon_ring_write(ring, 2); 150254885Sdumbbell 151254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 152254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 153254885Sdumbbell radeon_ring_write(ring, 0); 154254885Sdumbbell 155254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 156254885Sdumbbell cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); 157254885Sdumbbell} 158254885Sdumbbell 159254885Sdumbbell/* emits 9 + 1 sync (5) = 14*/ 160254885Sdumbbellstatic void 161254885Sdumbbellset_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 162254885Sdumbbell{ 163254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 164254885Sdumbbell u32 sq_vtx_constant_word2; 165254885Sdumbbell 166254885Sdumbbell sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | 167254885Sdumbbell SQ_VTXC_STRIDE(16); 168254885Sdumbbell#ifdef __BIG_ENDIAN 169254885Sdumbbell sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); 170254885Sdumbbell#endif 171254885Sdumbbell 172254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); 173254885Sdumbbell radeon_ring_write(ring, 0x460); 174254885Sdumbbell radeon_ring_write(ring, gpu_addr & 0xffffffff); 175254885Sdumbbell radeon_ring_write(ring, 48 - 1); 176254885Sdumbbell radeon_ring_write(ring, sq_vtx_constant_word2); 177254885Sdumbbell radeon_ring_write(ring, 1 << 0); 178254885Sdumbbell radeon_ring_write(ring, 0); 179254885Sdumbbell radeon_ring_write(ring, 0); 180254885Sdumbbell radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30); 181254885Sdumbbell 182254885Sdumbbell if ((rdev->family == CHIP_RV610) || 183254885Sdumbbell (rdev->family == CHIP_RV620) || 184254885Sdumbbell (rdev->family == CHIP_RS780) || 185254885Sdumbbell (rdev->family == CHIP_RS880) || 186254885Sdumbbell (rdev->family == CHIP_RV710)) 187254885Sdumbbell cp_set_surface_sync(rdev, 188254885Sdumbbell PACKET3_TC_ACTION_ENA, 48, gpu_addr); 189254885Sdumbbell else 190254885Sdumbbell cp_set_surface_sync(rdev, 191254885Sdumbbell PACKET3_VC_ACTION_ENA, 48, gpu_addr); 192254885Sdumbbell} 193254885Sdumbbell 194254885Sdumbbell/* emits 9 */ 195254885Sdumbbellstatic void 196254885Sdumbbellset_tex_resource(struct radeon_device *rdev, 197254885Sdumbbell int format, int w, int h, int pitch, 198254885Sdumbbell u64 gpu_addr, u32 size) 199254885Sdumbbell{ 200254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 201254885Sdumbbell uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; 202254885Sdumbbell 203254885Sdumbbell if (h < 1) 204254885Sdumbbell h = 1; 205254885Sdumbbell 206254885Sdumbbell sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) | 207254885Sdumbbell S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 208254885Sdumbbell sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) | 209254885Sdumbbell S_038000_TEX_WIDTH(w - 1); 210254885Sdumbbell 211254885Sdumbbell sq_tex_resource_word1 = S_038004_DATA_FORMAT(format); 212254885Sdumbbell sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1); 213254885Sdumbbell 214254885Sdumbbell sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) | 215254885Sdumbbell S_038010_DST_SEL_X(SQ_SEL_X) | 216254885Sdumbbell S_038010_DST_SEL_Y(SQ_SEL_Y) | 217254885Sdumbbell S_038010_DST_SEL_Z(SQ_SEL_Z) | 218254885Sdumbbell S_038010_DST_SEL_W(SQ_SEL_W); 219254885Sdumbbell 220254885Sdumbbell cp_set_surface_sync(rdev, 221254885Sdumbbell PACKET3_TC_ACTION_ENA, size, gpu_addr); 222254885Sdumbbell 223254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); 224254885Sdumbbell radeon_ring_write(ring, 0); 225254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word0); 226254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word1); 227254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 228254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 229254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word4); 230254885Sdumbbell radeon_ring_write(ring, 0); 231254885Sdumbbell radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30); 232254885Sdumbbell} 233254885Sdumbbell 234254885Sdumbbell/* emits 12 */ 235254885Sdumbbellstatic void 236254885Sdumbbellset_scissors(struct radeon_device *rdev, int x1, int y1, 237254885Sdumbbell int x2, int y2) 238254885Sdumbbell{ 239254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 240254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 241254885Sdumbbell radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 242254885Sdumbbell radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); 243254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 244254885Sdumbbell 245254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 246254885Sdumbbell radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 247254885Sdumbbell radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); 248254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 249254885Sdumbbell 250254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 251254885Sdumbbell radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 252254885Sdumbbell radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); 253254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 254254885Sdumbbell} 255254885Sdumbbell 256254885Sdumbbell/* emits 10 */ 257254885Sdumbbellstatic void 258254885Sdumbbelldraw_auto(struct radeon_device *rdev) 259254885Sdumbbell{ 260254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 261254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 262254885Sdumbbell radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 263254885Sdumbbell radeon_ring_write(ring, DI_PT_RECTLIST); 264254885Sdumbbell 265254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); 266254885Sdumbbell radeon_ring_write(ring, 267254885Sdumbbell#ifdef __BIG_ENDIAN 268254885Sdumbbell (2 << 2) | 269254885Sdumbbell#endif 270254885Sdumbbell DI_INDEX_SIZE_16_BIT); 271254885Sdumbbell 272254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); 273254885Sdumbbell radeon_ring_write(ring, 1); 274254885Sdumbbell 275254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); 276254885Sdumbbell radeon_ring_write(ring, 3); 277254885Sdumbbell radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); 278254885Sdumbbell 279254885Sdumbbell} 280254885Sdumbbell 281254885Sdumbbell/* emits 14 */ 282254885Sdumbbellstatic void 283254885Sdumbbellset_default_state(struct radeon_device *rdev) 284254885Sdumbbell{ 285254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 286254885Sdumbbell u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 287254885Sdumbbell u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 288254885Sdumbbell int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; 289254885Sdumbbell int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; 290254885Sdumbbell int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; 291254885Sdumbbell u64 gpu_addr; 292254885Sdumbbell int dwords; 293254885Sdumbbell 294254885Sdumbbell switch (rdev->family) { 295254885Sdumbbell case CHIP_R600: 296254885Sdumbbell num_ps_gprs = 192; 297254885Sdumbbell num_vs_gprs = 56; 298254885Sdumbbell num_temp_gprs = 4; 299254885Sdumbbell num_gs_gprs = 0; 300254885Sdumbbell num_es_gprs = 0; 301254885Sdumbbell num_ps_threads = 136; 302254885Sdumbbell num_vs_threads = 48; 303254885Sdumbbell num_gs_threads = 4; 304254885Sdumbbell num_es_threads = 4; 305254885Sdumbbell num_ps_stack_entries = 128; 306254885Sdumbbell num_vs_stack_entries = 128; 307254885Sdumbbell num_gs_stack_entries = 0; 308254885Sdumbbell num_es_stack_entries = 0; 309254885Sdumbbell break; 310254885Sdumbbell case CHIP_RV630: 311254885Sdumbbell case CHIP_RV635: 312254885Sdumbbell num_ps_gprs = 84; 313254885Sdumbbell num_vs_gprs = 36; 314254885Sdumbbell num_temp_gprs = 4; 315254885Sdumbbell num_gs_gprs = 0; 316254885Sdumbbell num_es_gprs = 0; 317254885Sdumbbell num_ps_threads = 144; 318254885Sdumbbell num_vs_threads = 40; 319254885Sdumbbell num_gs_threads = 4; 320254885Sdumbbell num_es_threads = 4; 321254885Sdumbbell num_ps_stack_entries = 40; 322254885Sdumbbell num_vs_stack_entries = 40; 323254885Sdumbbell num_gs_stack_entries = 32; 324254885Sdumbbell num_es_stack_entries = 16; 325254885Sdumbbell break; 326254885Sdumbbell case CHIP_RV610: 327254885Sdumbbell case CHIP_RV620: 328254885Sdumbbell case CHIP_RS780: 329254885Sdumbbell case CHIP_RS880: 330254885Sdumbbell default: 331254885Sdumbbell num_ps_gprs = 84; 332254885Sdumbbell num_vs_gprs = 36; 333254885Sdumbbell num_temp_gprs = 4; 334254885Sdumbbell num_gs_gprs = 0; 335254885Sdumbbell num_es_gprs = 0; 336254885Sdumbbell num_ps_threads = 136; 337254885Sdumbbell num_vs_threads = 48; 338254885Sdumbbell num_gs_threads = 4; 339254885Sdumbbell num_es_threads = 4; 340254885Sdumbbell num_ps_stack_entries = 40; 341254885Sdumbbell num_vs_stack_entries = 40; 342254885Sdumbbell num_gs_stack_entries = 32; 343254885Sdumbbell num_es_stack_entries = 16; 344254885Sdumbbell break; 345254885Sdumbbell case CHIP_RV670: 346254885Sdumbbell num_ps_gprs = 144; 347254885Sdumbbell num_vs_gprs = 40; 348254885Sdumbbell num_temp_gprs = 4; 349254885Sdumbbell num_gs_gprs = 0; 350254885Sdumbbell num_es_gprs = 0; 351254885Sdumbbell num_ps_threads = 136; 352254885Sdumbbell num_vs_threads = 48; 353254885Sdumbbell num_gs_threads = 4; 354254885Sdumbbell num_es_threads = 4; 355254885Sdumbbell num_ps_stack_entries = 40; 356254885Sdumbbell num_vs_stack_entries = 40; 357254885Sdumbbell num_gs_stack_entries = 32; 358254885Sdumbbell num_es_stack_entries = 16; 359254885Sdumbbell break; 360254885Sdumbbell case CHIP_RV770: 361254885Sdumbbell num_ps_gprs = 192; 362254885Sdumbbell num_vs_gprs = 56; 363254885Sdumbbell num_temp_gprs = 4; 364254885Sdumbbell num_gs_gprs = 0; 365254885Sdumbbell num_es_gprs = 0; 366254885Sdumbbell num_ps_threads = 188; 367254885Sdumbbell num_vs_threads = 60; 368254885Sdumbbell num_gs_threads = 0; 369254885Sdumbbell num_es_threads = 0; 370254885Sdumbbell num_ps_stack_entries = 256; 371254885Sdumbbell num_vs_stack_entries = 256; 372254885Sdumbbell num_gs_stack_entries = 0; 373254885Sdumbbell num_es_stack_entries = 0; 374254885Sdumbbell break; 375254885Sdumbbell case CHIP_RV730: 376254885Sdumbbell case CHIP_RV740: 377254885Sdumbbell num_ps_gprs = 84; 378254885Sdumbbell num_vs_gprs = 36; 379254885Sdumbbell num_temp_gprs = 4; 380254885Sdumbbell num_gs_gprs = 0; 381254885Sdumbbell num_es_gprs = 0; 382254885Sdumbbell num_ps_threads = 188; 383254885Sdumbbell num_vs_threads = 60; 384254885Sdumbbell num_gs_threads = 0; 385254885Sdumbbell num_es_threads = 0; 386254885Sdumbbell num_ps_stack_entries = 128; 387254885Sdumbbell num_vs_stack_entries = 128; 388254885Sdumbbell num_gs_stack_entries = 0; 389254885Sdumbbell num_es_stack_entries = 0; 390254885Sdumbbell break; 391254885Sdumbbell case CHIP_RV710: 392254885Sdumbbell num_ps_gprs = 192; 393254885Sdumbbell num_vs_gprs = 56; 394254885Sdumbbell num_temp_gprs = 4; 395254885Sdumbbell num_gs_gprs = 0; 396254885Sdumbbell num_es_gprs = 0; 397254885Sdumbbell num_ps_threads = 144; 398254885Sdumbbell num_vs_threads = 48; 399254885Sdumbbell num_gs_threads = 0; 400254885Sdumbbell num_es_threads = 0; 401254885Sdumbbell num_ps_stack_entries = 128; 402254885Sdumbbell num_vs_stack_entries = 128; 403254885Sdumbbell num_gs_stack_entries = 0; 404254885Sdumbbell num_es_stack_entries = 0; 405254885Sdumbbell break; 406254885Sdumbbell } 407254885Sdumbbell 408254885Sdumbbell if ((rdev->family == CHIP_RV610) || 409254885Sdumbbell (rdev->family == CHIP_RV620) || 410254885Sdumbbell (rdev->family == CHIP_RS780) || 411254885Sdumbbell (rdev->family == CHIP_RS880) || 412254885Sdumbbell (rdev->family == CHIP_RV710)) 413254885Sdumbbell sq_config = 0; 414254885Sdumbbell else 415254885Sdumbbell sq_config = VC_ENABLE; 416254885Sdumbbell 417254885Sdumbbell sq_config |= (DX9_CONSTS | 418254885Sdumbbell ALU_INST_PREFER_VECTOR | 419254885Sdumbbell PS_PRIO(0) | 420254885Sdumbbell VS_PRIO(1) | 421254885Sdumbbell GS_PRIO(2) | 422254885Sdumbbell ES_PRIO(3)); 423254885Sdumbbell 424254885Sdumbbell sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | 425254885Sdumbbell NUM_VS_GPRS(num_vs_gprs) | 426254885Sdumbbell NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); 427254885Sdumbbell sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | 428254885Sdumbbell NUM_ES_GPRS(num_es_gprs)); 429254885Sdumbbell sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | 430254885Sdumbbell NUM_VS_THREADS(num_vs_threads) | 431254885Sdumbbell NUM_GS_THREADS(num_gs_threads) | 432254885Sdumbbell NUM_ES_THREADS(num_es_threads)); 433254885Sdumbbell sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | 434254885Sdumbbell NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); 435254885Sdumbbell sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | 436254885Sdumbbell NUM_ES_STACK_ENTRIES(num_es_stack_entries)); 437254885Sdumbbell 438254885Sdumbbell /* emit an IB pointing at default state */ 439254885Sdumbbell dwords = roundup2(rdev->r600_blit.state_len, 0x10); 440254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 441254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 442254885Sdumbbell radeon_ring_write(ring, 443254885Sdumbbell#ifdef __BIG_ENDIAN 444254885Sdumbbell (2 << 0) | 445254885Sdumbbell#endif 446254885Sdumbbell (gpu_addr & 0xFFFFFFFC)); 447254885Sdumbbell radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); 448254885Sdumbbell radeon_ring_write(ring, dwords); 449254885Sdumbbell 450254885Sdumbbell /* SQ config */ 451254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 452254885Sdumbbell radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 453254885Sdumbbell radeon_ring_write(ring, sq_config); 454254885Sdumbbell radeon_ring_write(ring, sq_gpr_resource_mgmt_1); 455254885Sdumbbell radeon_ring_write(ring, sq_gpr_resource_mgmt_2); 456254885Sdumbbell radeon_ring_write(ring, sq_thread_resource_mgmt); 457254885Sdumbbell radeon_ring_write(ring, sq_stack_resource_mgmt_1); 458254885Sdumbbell radeon_ring_write(ring, sq_stack_resource_mgmt_2); 459254885Sdumbbell} 460254885Sdumbbell 461254885Sdumbbellint r600_blit_init(struct radeon_device *rdev) 462254885Sdumbbell{ 463254885Sdumbbell u32 obj_size; 464254885Sdumbbell int i, r, dwords; 465254885Sdumbbell void *ptr; 466254885Sdumbbell u32 packet2s[16]; 467254885Sdumbbell int num_packet2s = 0; 468254885Sdumbbell 469254885Sdumbbell rdev->r600_blit.primitives.set_render_target = set_render_target; 470254885Sdumbbell rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; 471254885Sdumbbell rdev->r600_blit.primitives.set_shaders = set_shaders; 472254885Sdumbbell rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; 473254885Sdumbbell rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; 474254885Sdumbbell rdev->r600_blit.primitives.set_scissors = set_scissors; 475254885Sdumbbell rdev->r600_blit.primitives.draw_auto = draw_auto; 476254885Sdumbbell rdev->r600_blit.primitives.set_default_state = set_default_state; 477254885Sdumbbell 478254885Sdumbbell rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ 479254885Sdumbbell rdev->r600_blit.ring_size_common += 40; /* shaders + def state */ 480254885Sdumbbell rdev->r600_blit.ring_size_common += 5; /* done copy */ 481254885Sdumbbell rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ 482254885Sdumbbell 483254885Sdumbbell rdev->r600_blit.ring_size_per_loop = 76; 484254885Sdumbbell /* set_render_target emits 2 extra dwords on rv6xx */ 485254885Sdumbbell if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) 486254885Sdumbbell rdev->r600_blit.ring_size_per_loop += 2; 487254885Sdumbbell 488254885Sdumbbell rdev->r600_blit.max_dim = 8192; 489254885Sdumbbell 490254885Sdumbbell rdev->r600_blit.state_offset = 0; 491254885Sdumbbell 492254885Sdumbbell if (rdev->family >= CHIP_RV770) 493254885Sdumbbell rdev->r600_blit.state_len = r7xx_default_size; 494254885Sdumbbell else 495254885Sdumbbell rdev->r600_blit.state_len = r6xx_default_size; 496254885Sdumbbell 497254885Sdumbbell dwords = rdev->r600_blit.state_len; 498254885Sdumbbell while (dwords & 0xf) { 499254885Sdumbbell packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); 500254885Sdumbbell dwords++; 501254885Sdumbbell } 502254885Sdumbbell 503254885Sdumbbell obj_size = dwords * 4; 504254885Sdumbbell obj_size = roundup2(obj_size, 256); 505254885Sdumbbell 506254885Sdumbbell rdev->r600_blit.vs_offset = obj_size; 507254885Sdumbbell obj_size += r6xx_vs_size * 4; 508254885Sdumbbell obj_size = roundup2(obj_size, 256); 509254885Sdumbbell 510254885Sdumbbell rdev->r600_blit.ps_offset = obj_size; 511254885Sdumbbell obj_size += r6xx_ps_size * 4; 512254885Sdumbbell obj_size = roundup2(obj_size, 256); 513254885Sdumbbell 514254885Sdumbbell /* pin copy shader into vram if not already initialized */ 515254885Sdumbbell if (rdev->r600_blit.shader_obj == NULL) { 516254885Sdumbbell r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, 517254885Sdumbbell RADEON_GEM_DOMAIN_VRAM, 518254885Sdumbbell NULL, &rdev->r600_blit.shader_obj); 519254885Sdumbbell if (r) { 520254885Sdumbbell DRM_ERROR("r600 failed to allocate shader\n"); 521254885Sdumbbell return r; 522254885Sdumbbell } 523254885Sdumbbell 524254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 525254885Sdumbbell if (unlikely(r != 0)) 526254885Sdumbbell return r; 527254885Sdumbbell r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 528254885Sdumbbell &rdev->r600_blit.shader_gpu_addr); 529254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 530254885Sdumbbell if (r) { 531254885Sdumbbell dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 532254885Sdumbbell return r; 533254885Sdumbbell } 534254885Sdumbbell } 535254885Sdumbbell 536254885Sdumbbell DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", 537254885Sdumbbell obj_size, 538254885Sdumbbell rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); 539254885Sdumbbell 540254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 541254885Sdumbbell if (unlikely(r != 0)) 542254885Sdumbbell return r; 543254885Sdumbbell r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); 544254885Sdumbbell if (r) { 545254885Sdumbbell DRM_ERROR("failed to map blit object %d\n", r); 546254885Sdumbbell return r; 547254885Sdumbbell } 548254885Sdumbbell if (rdev->family >= CHIP_RV770) 549254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset, 550254885Sdumbbell r7xx_default_state, rdev->r600_blit.state_len * 4); 551254885Sdumbbell else 552254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset, 553254885Sdumbbell r6xx_default_state, rdev->r600_blit.state_len * 4); 554254885Sdumbbell if (num_packet2s) 555254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 556254885Sdumbbell packet2s, num_packet2s * 4); 557254885Sdumbbell for (i = 0; i < r6xx_vs_size; i++) 558254885Sdumbbell *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]); 559254885Sdumbbell for (i = 0; i < r6xx_ps_size; i++) 560254885Sdumbbell *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); 561254885Sdumbbell radeon_bo_kunmap(rdev->r600_blit.shader_obj); 562254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 563254885Sdumbbell 564254885Sdumbbell radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 565254885Sdumbbell return 0; 566254885Sdumbbell} 567254885Sdumbbell 568254885Sdumbbellvoid r600_blit_fini(struct radeon_device *rdev) 569254885Sdumbbell{ 570254885Sdumbbell int r; 571254885Sdumbbell 572254885Sdumbbell radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 573254885Sdumbbell if (rdev->r600_blit.shader_obj == NULL) 574254885Sdumbbell return; 575254885Sdumbbell /* If we can't reserve the bo, unref should be enough to destroy 576254885Sdumbbell * it when it becomes idle. 577254885Sdumbbell */ 578254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 579254885Sdumbbell if (!r) { 580254885Sdumbbell radeon_bo_unpin(rdev->r600_blit.shader_obj); 581254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 582254885Sdumbbell } 583254885Sdumbbell radeon_bo_unref(&rdev->r600_blit.shader_obj); 584254885Sdumbbell} 585254885Sdumbbell 586254885Sdumbbellstatic unsigned r600_blit_create_rect(unsigned num_gpu_pages, 587254885Sdumbbell int *width, int *height, int max_dim) 588254885Sdumbbell{ 589254885Sdumbbell unsigned max_pages; 590254885Sdumbbell unsigned pages = num_gpu_pages; 591254885Sdumbbell int w, h; 592254885Sdumbbell 593254885Sdumbbell if (num_gpu_pages == 0) { 594254885Sdumbbell /* not supposed to be called with no pages, but just in case */ 595254885Sdumbbell h = 0; 596254885Sdumbbell w = 0; 597254885Sdumbbell pages = 0; 598254885Sdumbbell DRM_ERROR("%s: called with no pages", __func__); 599254885Sdumbbell } else { 600254885Sdumbbell int rect_order = 2; 601254885Sdumbbell h = RECT_UNIT_H; 602254885Sdumbbell while (num_gpu_pages / rect_order) { 603254885Sdumbbell h *= 2; 604254885Sdumbbell rect_order *= 4; 605254885Sdumbbell if (h >= max_dim) { 606254885Sdumbbell h = max_dim; 607254885Sdumbbell break; 608254885Sdumbbell } 609254885Sdumbbell } 610254885Sdumbbell max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H); 611254885Sdumbbell if (pages > max_pages) 612254885Sdumbbell pages = max_pages; 613254885Sdumbbell w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h; 614254885Sdumbbell w = (w / RECT_UNIT_W) * RECT_UNIT_W; 615254885Sdumbbell pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H); 616254885Sdumbbell KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0")); 617254885Sdumbbell } 618254885Sdumbbell 619254885Sdumbbell 620254885Sdumbbell DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages); 621254885Sdumbbell 622254885Sdumbbell /* return width and height only of the caller wants it */ 623254885Sdumbbell if (height) 624254885Sdumbbell *height = h; 625254885Sdumbbell if (width) 626254885Sdumbbell *width = w; 627254885Sdumbbell 628254885Sdumbbell return pages; 629254885Sdumbbell} 630254885Sdumbbell 631254885Sdumbbell 632254885Sdumbbellint r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 633254885Sdumbbell struct radeon_fence **fence, struct radeon_sa_bo **vb, 634254885Sdumbbell struct radeon_semaphore **sem) 635254885Sdumbbell{ 636254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 637254885Sdumbbell int r; 638254885Sdumbbell int ring_size; 639254885Sdumbbell int num_loops = 0; 640254885Sdumbbell int dwords_per_loop = rdev->r600_blit.ring_size_per_loop; 641254885Sdumbbell 642254885Sdumbbell /* num loops */ 643254885Sdumbbell while (num_gpu_pages) { 644254885Sdumbbell num_gpu_pages -= 645254885Sdumbbell r600_blit_create_rect(num_gpu_pages, NULL, NULL, 646254885Sdumbbell rdev->r600_blit.max_dim); 647254885Sdumbbell num_loops++; 648254885Sdumbbell } 649254885Sdumbbell 650254885Sdumbbell /* 48 bytes for vertex per loop */ 651254885Sdumbbell r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb, 652254885Sdumbbell (num_loops*48)+256, 256, true); 653254885Sdumbbell if (r) { 654254885Sdumbbell return r; 655254885Sdumbbell } 656254885Sdumbbell 657254885Sdumbbell r = radeon_semaphore_create(rdev, sem); 658254885Sdumbbell if (r) { 659254885Sdumbbell radeon_sa_bo_free(rdev, vb, NULL); 660254885Sdumbbell return r; 661254885Sdumbbell } 662254885Sdumbbell 663254885Sdumbbell /* calculate number of loops correctly */ 664254885Sdumbbell ring_size = num_loops * dwords_per_loop; 665254885Sdumbbell ring_size += rdev->r600_blit.ring_size_common; 666254885Sdumbbell r = radeon_ring_lock(rdev, ring, ring_size); 667254885Sdumbbell if (r) { 668254885Sdumbbell radeon_sa_bo_free(rdev, vb, NULL); 669254885Sdumbbell radeon_semaphore_free(rdev, sem, NULL); 670254885Sdumbbell return r; 671254885Sdumbbell } 672254885Sdumbbell 673254885Sdumbbell if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) { 674254885Sdumbbell radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring, 675254885Sdumbbell RADEON_RING_TYPE_GFX_INDEX); 676254885Sdumbbell radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX); 677254885Sdumbbell } else { 678254885Sdumbbell radeon_semaphore_free(rdev, sem, NULL); 679254885Sdumbbell } 680254885Sdumbbell 681254885Sdumbbell rdev->r600_blit.primitives.set_default_state(rdev); 682254885Sdumbbell rdev->r600_blit.primitives.set_shaders(rdev); 683254885Sdumbbell return 0; 684254885Sdumbbell} 685254885Sdumbbell 686254885Sdumbbellvoid r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 687254885Sdumbbell struct radeon_sa_bo *vb, struct radeon_semaphore *sem) 688254885Sdumbbell{ 689254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 690254885Sdumbbell int r; 691254885Sdumbbell 692254885Sdumbbell r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 693254885Sdumbbell if (r) { 694254885Sdumbbell radeon_ring_unlock_undo(rdev, ring); 695254885Sdumbbell return; 696254885Sdumbbell } 697254885Sdumbbell 698254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 699254885Sdumbbell radeon_sa_bo_free(rdev, &vb, *fence); 700254885Sdumbbell radeon_semaphore_free(rdev, &sem, *fence); 701254885Sdumbbell} 702254885Sdumbbell 703254885Sdumbbellvoid r600_kms_blit_copy(struct radeon_device *rdev, 704254885Sdumbbell u64 src_gpu_addr, u64 dst_gpu_addr, 705254885Sdumbbell unsigned num_gpu_pages, 706254885Sdumbbell struct radeon_sa_bo *vb) 707254885Sdumbbell{ 708254885Sdumbbell u64 vb_gpu_addr; 709254885Sdumbbell u32 *vb_cpu_addr; 710254885Sdumbbell 711254885Sdumbbell DRM_DEBUG("emitting copy %16jx %16jx %d\n", 712254885Sdumbbell (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages); 713254885Sdumbbell vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb); 714254885Sdumbbell vb_gpu_addr = radeon_sa_bo_gpu_addr(vb); 715254885Sdumbbell 716254885Sdumbbell while (num_gpu_pages) { 717254885Sdumbbell int w, h; 718254885Sdumbbell unsigned size_in_bytes; 719254885Sdumbbell unsigned pages_per_loop = 720254885Sdumbbell r600_blit_create_rect(num_gpu_pages, &w, &h, 721254885Sdumbbell rdev->r600_blit.max_dim); 722254885Sdumbbell 723254885Sdumbbell size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE; 724254885Sdumbbell DRM_DEBUG("rectangle w=%d h=%d\n", w, h); 725254885Sdumbbell 726254885Sdumbbell vb_cpu_addr[0] = 0; 727254885Sdumbbell vb_cpu_addr[1] = 0; 728254885Sdumbbell vb_cpu_addr[2] = 0; 729254885Sdumbbell vb_cpu_addr[3] = 0; 730254885Sdumbbell 731254885Sdumbbell vb_cpu_addr[4] = 0; 732254885Sdumbbell vb_cpu_addr[5] = int2float(h); 733254885Sdumbbell vb_cpu_addr[6] = 0; 734254885Sdumbbell vb_cpu_addr[7] = int2float(h); 735254885Sdumbbell 736254885Sdumbbell vb_cpu_addr[8] = int2float(w); 737254885Sdumbbell vb_cpu_addr[9] = int2float(h); 738254885Sdumbbell vb_cpu_addr[10] = int2float(w); 739254885Sdumbbell vb_cpu_addr[11] = int2float(h); 740254885Sdumbbell 741254885Sdumbbell rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8, 742254885Sdumbbell w, h, w, src_gpu_addr, size_in_bytes); 743254885Sdumbbell rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8, 744254885Sdumbbell w, h, dst_gpu_addr); 745254885Sdumbbell rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h); 746254885Sdumbbell rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr); 747254885Sdumbbell rdev->r600_blit.primitives.draw_auto(rdev); 748254885Sdumbbell rdev->r600_blit.primitives.cp_set_surface_sync(rdev, 749254885Sdumbbell PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, 750254885Sdumbbell size_in_bytes, dst_gpu_addr); 751254885Sdumbbell 752254885Sdumbbell vb_cpu_addr += 12; 753254885Sdumbbell vb_gpu_addr += 4*12; 754254885Sdumbbell src_gpu_addr += size_in_bytes; 755254885Sdumbbell dst_gpu_addr += size_in_bytes; 756254885Sdumbbell num_gpu_pages -= pages_per_loop; 757254885Sdumbbell } 758254885Sdumbbell} 759